1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
15 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
17 #include "AArch64FrameLowering.h"
18 #include "AArch64ISelLowering.h"
19 #include "AArch64InstrInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64SelectionDAGInfo.h"
22 #include "llvm/ADT/TargetTuple.h"
23 #include "llvm/IR/DataLayout.h"
24 #include "llvm/Target/TargetSubtargetInfo.h"
27 #define GET_SUBTARGETINFO_HEADER
28 #include "AArch64GenSubtargetInfo.inc"
35 class AArch64Subtarget : public AArch64GenSubtargetInfo {
37 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
39 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
40 ARMProcFamilyEnum ARMProcFamily;
50 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
51 bool HasZeroCycleRegMove;
53 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
54 bool HasZeroCycleZeroing;
56 // StrictAlign - Disallow unaligned memory accesses.
59 // ReserveX18 - X18 is not available as a general purpose register.
64 /// CPUString - String name of used CPU.
65 std::string CPUString;
67 /// TargetTriple - What processor and OS we're targeting.
70 AArch64FrameLowering FrameLowering;
71 AArch64InstrInfo InstrInfo;
72 AArch64SelectionDAGInfo TSInfo;
73 AArch64TargetLowering TLInfo;
75 /// initializeSubtargetDependencies - Initializes using CPUString and the
76 /// passed in feature string so that we can use initializer lists for
77 /// subtarget initialization.
78 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
81 /// This constructor initializes the data members to match that
82 /// of the specified triple.
83 AArch64Subtarget(const Triple &TT, const std::string &CPU,
84 const std::string &FS, const TargetMachine &TM,
87 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
90 const AArch64FrameLowering *getFrameLowering() const override {
91 return &FrameLowering;
93 const AArch64TargetLowering *getTargetLowering() const override {
96 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
97 const AArch64RegisterInfo *getRegisterInfo() const override {
98 return &getInstrInfo()->getRegisterInfo();
100 const Triple &getTargetTriple() const { return TargetTriple; }
101 // FIXME: Return a references once our member is a TargetTuple.
102 const TargetTuple getTargetTuple() const { return TargetTuple(TargetTriple); }
103 bool enableMachineScheduler() const override { return true; }
104 bool enablePostRAScheduler() const override {
105 return isCortexA53() || isCortexA57();
108 bool hasV8_1aOps() const { return HasV8_1aOps; }
110 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
112 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
114 bool requiresStrictAlign() const { return StrictAlign; }
116 bool isX18Reserved() const { return ReserveX18; }
117 bool hasFPARMv8() const { return HasFPARMv8; }
118 bool hasNEON() const { return HasNEON; }
119 bool hasCrypto() const { return HasCrypto; }
120 bool hasCRC() const { return HasCRC; }
121 bool hasPerfMon() const { return HasPerfMon; }
123 bool isLittleEndian() const { return IsLittle; }
125 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
126 bool isTargetIOS() const { return TargetTriple.isiOS(); }
127 bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
128 bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
130 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
131 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
132 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
134 bool isCyclone() const { return CPUString == "cyclone"; }
135 bool isCortexA57() const { return CPUString == "cortex-a57"; }
136 bool isCortexA53() const { return CPUString == "cortex-a53"; }
138 bool useAA() const override { return isCortexA53(); }
140 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
141 /// that still makes it profitable to inline the call.
142 unsigned getMaxInlineSizeThreshold() const { return 64; }
144 /// ParseSubtargetFeatures - Parses features string setting specified
145 /// subtarget options. Definition of function is auto generated by tblgen.
146 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
148 /// ClassifyGlobalReference - Find the target operand flags that describe
149 /// how a global value should be referenced for the current subtarget.
150 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
151 const TargetMachine &TM) const;
153 /// This function returns the name of a function which has an interface
154 /// like the non-standard bzero function, if such a function exists on
155 /// the current subtarget and it is considered prefereable over
156 /// memset with zero passed as the second argument. Otherwise it
158 const char *getBZeroEntry() const;
160 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
162 unsigned NumRegionInstrs) const override;
164 bool enableEarlyIfConversion() const override;
166 std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
168 } // End llvm namespace