1 //===-- AArch64Subtarget.cpp - AArch64 Subtarget Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the AArch64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "AArch64InstrInfo.h"
15 #include "AArch64PBQPRegAlloc.h"
16 #include "AArch64Subtarget.h"
17 #include "AArch64TargetMachine.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/GlobalValue.h"
21 #include "llvm/Support/TargetRegistry.h"
25 #define DEBUG_TYPE "aarch64-subtarget"
27 #define GET_SUBTARGETINFO_CTOR
28 #define GET_SUBTARGETINFO_TARGET_DESC
29 #include "AArch64GenSubtargetInfo.inc"
32 EnableEarlyIfConvert("aarch64-early-ifcvt", cl::desc("Enable the early if "
33 "converter pass"), cl::init(true), cl::Hidden);
36 AArch64Subtarget::initializeSubtargetDependencies(StringRef FS) {
37 // Determine default and user-specified characteristics
39 if (CPUString.empty())
40 CPUString = "generic";
42 ParseSubtargetFeatures(CPUString, FS);
46 AArch64Subtarget::AArch64Subtarget(const std::string &TT,
47 const std::string &CPU,
48 const std::string &FS,
49 const AArch64TargetMachine &TM,
51 : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
52 HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false),
53 HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
54 IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), TM(TM),
55 FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)),
56 TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}
58 /// ClassifyGlobalReference - Find the target operand flags that describe
59 /// how a global value should be referenced for the current subtarget.
61 AArch64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
62 const TargetMachine &TM) const {
63 bool isDecl = GV->isDeclarationForLinker();
65 // MachO large model always goes via a GOT, simply to get a single 8-byte
66 // absolute relocation on all global addresses.
67 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
68 return AArch64II::MO_GOT;
70 // The small code mode's direct accesses use ADRP, which cannot necessarily
71 // produce the value 0 (if the code is above 4GB).
72 if (TM.getCodeModel() == CodeModel::Small &&
73 GV->isWeakForLinker() && isDecl) {
74 // In PIC mode use the GOT, but in absolute mode use a constant pool load.
75 if (TM.getRelocationModel() == Reloc::Static)
76 return AArch64II::MO_CONSTPOOL;
78 return AArch64II::MO_GOT;
81 // If symbol visibility is hidden, the extra load is not needed if
82 // the symbol is definitely defined in the current translation unit.
84 // The handling of non-hidden symbols in PIC mode is rather target-dependent:
85 // + On MachO, if the symbol is defined in this module the GOT can be
87 // + On ELF, the R_AARCH64_COPY relocation means that even symbols actually
88 // defined could end up in unexpected places. Use a GOT.
89 if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) {
91 return (isDecl || GV->isWeakForLinker()) ? AArch64II::MO_GOT
92 : AArch64II::MO_NO_FLAG;
94 // No need to go through the GOT for local symbols on ELF.
95 return GV->hasLocalLinkage() ? AArch64II::MO_NO_FLAG : AArch64II::MO_GOT;
98 return AArch64II::MO_NO_FLAG;
101 /// This function returns the name of a function which has an interface
102 /// like the non-standard bzero function, if such a function exists on
103 /// the current subtarget and it is considered prefereable over
104 /// memset with zero passed as the second argument. Otherwise it
106 const char *AArch64Subtarget::getBZeroEntry() const {
107 // Prefer bzero on Darwin only.
114 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
115 MachineInstr *begin, MachineInstr *end,
116 unsigned NumRegionInstrs) const {
117 // LNT run (at least on Cyclone) showed reasonably significant gains for
118 // bi-directional scheduling. 253.perlbmk.
119 Policy.OnlyTopDown = false;
120 Policy.OnlyBottomUp = false;
123 bool AArch64Subtarget::enableEarlyIfConversion() const {
124 return EnableEarlyIfConvert;
127 std::unique_ptr<PBQPRAConstraint>
128 AArch64Subtarget::getCustomPBQPConstraints() const {
132 return llvm::make_unique<A57ChainingConstraint>();
135 const AArch64RegisterInfo *AArch64Subtarget::getRegisterInfo() const {
136 return getTargetMachine().getRegisterInfo();