lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // (outs Result), (ins Imm, OpCmode)
  19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  20
  21 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  22
  23 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  24
  25 // (outs Result), (ins Imm)
  26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  27                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  28
  29 // (outs Result), (ins LHS, RHS, CondCode)
  30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  31                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  32
  33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  35                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  36
  37 // (outs Result), (ins LHS, RHS)
  38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  39                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  40
  41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  42                                      SDTCisVT<2, i32>]>;
  43 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  44 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  45
  46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  47                                SDTCisSameAs<0, 2>]>;
  48 def Neon_uzp1    : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
  49 def Neon_uzp2    : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
  50 def Neon_zip1    : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
  51 def Neon_zip2    : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
  52 def Neon_trn1    : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
  53 def Neon_trn2    : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
  54
  55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
  56 def Neon_rev64    : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
  57 def Neon_rev32    : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
  58 def Neon_rev16    : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
  59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  60                        [SDTCisVec<0>]>>;
  61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  62                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  64                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  65                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  66
  67 def SDT_assertext : SDTypeProfile<1, 1,
  68   [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
  69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
  70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Multiclasses
  74 //===----------------------------------------------------------------------===//
  75
  76 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  77                                 string asmop, SDPatternOperator opnode8B,
  78                                 SDPatternOperator opnode16B,
  79                                 bit Commutable = 0> {
  80   let isCommutable = Commutable in {
  81     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  82                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  83                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  84                [(set (v8i8 VPR64:$Rd),
  85                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  86                NoItinerary>;
  87
  88     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  89                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  90                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  91                [(set (v16i8 VPR128:$Rd),
  92                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  93                NoItinerary>;
  94   }
  95
  96 }
  97
  98 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
  99                                   string asmop, SDPatternOperator opnode,
 100                                   bit Commutable = 0> {
 101   let isCommutable = Commutable in {
 102     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
 103               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 104               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
 105               [(set (v4i16 VPR64:$Rd),
 106                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
 107               NoItinerary>;
 108
 109     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
 110               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 111               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
 112               [(set (v8i16 VPR128:$Rd),
 113                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
 114               NoItinerary>;
 115
 116     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 117               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 118               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 119               [(set (v2i32 VPR64:$Rd),
 120                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 121               NoItinerary>;
 122
 123     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 124               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 125               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 126               [(set (v4i32 VPR128:$Rd),
 127                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 128               NoItinerary>;
 129   }
 130 }
 131 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 132                                   string asmop, SDPatternOperator opnode,
 133                                   bit Commutable = 0>
 134    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 135   let isCommutable = Commutable in {
 136     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 137                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 138                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 139                [(set (v8i8 VPR64:$Rd),
 140                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 141                NoItinerary>;
 142
 143     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 144                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 145                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 146                [(set (v16i8 VPR128:$Rd),
 147                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 148                NoItinerary>;
 149   }
 150 }
 151
 152 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 153                                    string asmop, SDPatternOperator opnode,
 154                                    bit Commutable = 0>
 155    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 156   let isCommutable = Commutable in {
 157     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 158               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 159               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 160               [(set (v2i64 VPR128:$Rd),
 161                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 162               NoItinerary>;
 163   }
 164 }
 165
 166 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 167 // but Result types can be integer or floating point types.
 168 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 169                                  string asmop, SDPatternOperator opnode2S,
 170                                  SDPatternOperator opnode4S,
 171                                  SDPatternOperator opnode2D,
 172                                  ValueType ResTy2S, ValueType ResTy4S,
 173                                  ValueType ResTy2D, bit Commutable = 0> {
 174   let isCommutable = Commutable in {
 175     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 176               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 177               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 178               [(set (ResTy2S VPR64:$Rd),
 179                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 180               NoItinerary>;
 181
 182     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 183               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 184               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 185               [(set (ResTy4S VPR128:$Rd),
 186                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 187               NoItinerary>;
 188
 189     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 190               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 191               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 192               [(set (ResTy2D VPR128:$Rd),
 193                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 194                NoItinerary>;
 195   }
 196 }
 197
 198 //===----------------------------------------------------------------------===//
 199 // Instruction Definitions
 200 //===----------------------------------------------------------------------===//
 201
 202 // Vector Arithmetic Instructions
 203
 204 // Vector Add (Integer and Floating-Point)
 205
 206 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 207 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 208                                      v2f32, v4f32, v2f64, 1>;
 209
 210 // Vector Sub (Integer and Floating-Point)
 211
 212 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 213 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 214                                      v2f32, v4f32, v2f64, 0>;
 215
 216 // Vector Multiply (Integer and Floating-Point)
 217
 218 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 219 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 220                                      v2f32, v4f32, v2f64, 1>;
 221
 222 // Vector Multiply (Polynomial)
 223
 224 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 225                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 226
 227 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 228
 229 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 230 // two operands constraints.
 231 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 232   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 233   bits<5> opcode, SDPatternOperator opnode>
 234   : NeonI_3VSame<q, u, size, opcode,
 235     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 236     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 237     [(set (OpTy VPRC:$Rd),
 238        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 239     NoItinerary> {
 240   let Constraints = "$src = $Rd";
 241 }
 242
 243 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 244                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 245
 246 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 247                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 248
 249
 250 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 251                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 252 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 253                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 254 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 255                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 256 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 257                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 258 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 259                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 260 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 261                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 262
 263 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 264                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 265 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 266                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 267 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 268                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 269 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 270                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 271 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 272                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 273 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 274                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 275
 276 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 277
 278 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 279                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 280
 281 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 282                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 283
 284 let Predicates = [HasNEON, UseFusedMAC] in {
 285 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 286                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 287 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 288                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 289 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 290                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 291
 292 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 293                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 294 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 295                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 296 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 297                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 298 }
 299
 300 // We're also allowed to match the fma instruction regardless of compile
 301 // options.
 302 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 303           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 304 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 305           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 306 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 307           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 308
 309 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 310           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 311 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 312           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 313 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 314           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 315
 316 // Vector Divide (Floating-Point)
 317
 318 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 319                                      v2f32, v4f32, v2f64, 0>;
 320
 321 // Vector Bitwise Operations
 322
 323 // Vector Bitwise AND
 324
 325 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 326
 327 // Vector Bitwise Exclusive OR
 328
 329 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 330
 331 // Vector Bitwise OR
 332
 333 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 334
 335 // ORR disassembled as MOV if Vn==Vm
 336
 337 // Vector Move - register
 338 // Alias for ORR if Vn=Vm.
 339 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 340 // custom printing of aliases.
 341 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 342                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 343 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 344                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 345
 346 // The MOVI instruction takes two immediate operands.  The first is the
 347 // immediate encoding, while the second is the cmode.  A cmode of 14, or
 348 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
 349 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
 350 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
 351
 352 def Neon_not8B  : PatFrag<(ops node:$in),
 353                           (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
 354 def Neon_not16B : PatFrag<(ops node:$in),
 355                           (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
 356
 357 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 358                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 359
 360 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 361                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 362
 363 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 364                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 365
 366 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 367                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 368
 369
 370 // Vector Bitwise OR NOT - register
 371
 372 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 373                                    Neon_orn8B, Neon_orn16B, 0>;
 374
 375 // Vector Bitwise Bit Clear (AND NOT) - register
 376
 377 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 378                                    Neon_bic8B, Neon_bic16B, 0>;
 379
 380 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 381                                    SDPatternOperator opnode16B,
 382                                    Instruction INST8B,
 383                                    Instruction INST16B> {
 384   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 385             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 386   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 387             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 388   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 389             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 390   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 391             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 392   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 393             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 394   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 395             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 396 }
 397
 398 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 399 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 400 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 401 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 402 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 403 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 404
 405 //   Vector Bitwise Select
 406 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 407                                               0b0, 0b1, 0b01, 0b00011, vselect>;
 408
 409 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 410                                               0b1, 0b1, 0b01, 0b00011, vselect>;
 411
 412 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 413                                    Instruction INST8B,
 414                                    Instruction INST16B> {
 415   // Disassociate type from instruction definition
 416   def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 417             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 418   def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 419             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 420   def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 421             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 422   def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 423             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 424   def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 425             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 426   def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 427             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 428   def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 429             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 430   def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 431             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 432
 433   // Allow to match BSL instruction pattern with non-constant operand
 434   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 435                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 436           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 437   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 438                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 439           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 440   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 441                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 442           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 443   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 444                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 445           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 446   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 447                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 448           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 449   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 450                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 451           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 452   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 453                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 454           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 455   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 456                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 457           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 458
 459   // Allow to match llvm.arm.* intrinsics.
 460   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 461                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 462             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 463   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 464                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 465             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 466   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 467                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 468             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 469   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 470                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 471             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 472   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 473                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 474             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 475   def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
 476                     (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
 477             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 478   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 479                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 480             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 481   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 482                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 483             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 484   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 485                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 486             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 487   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 488                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 489             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 490   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 491                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 492             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 493   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 494                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 495             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 496 }
 497
 498 // Additional patterns for bitwise instruction BSL
 499 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
 500
 501 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 502                            (vselect node:$src, node:$Rn, node:$Rm),
 503                            [{ (void)N; return false; }]>;
 504
 505 // Vector Bitwise Insert if True
 506
 507 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 508                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 509 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 510                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 511
 512 // Vector Bitwise Insert if False
 513
 514 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 515                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 516 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 517                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 518
 519 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 520
 521 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 522                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 523 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 524                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 525
 526 // Vector Absolute Difference and Accumulate (Unsigned)
 527 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 528                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 529 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 530                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 531 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 532                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 533 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 534                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 535 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 536                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 537 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 538                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 539
 540 // Vector Absolute Difference and Accumulate (Signed)
 541 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 542                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 543 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 544                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 545 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 546                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 547 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 548                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 549 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 550                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 551 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 552                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 553
 554
 555 // Vector Absolute Difference (Signed, Unsigned)
 556 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 557 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 558
 559 // Vector Absolute Difference (Floating Point)
 560 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 561                                     int_arm_neon_vabds, int_arm_neon_vabds,
 562                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 563
 564 // Vector Reciprocal Step (Floating Point)
 565 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 566                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 567                                        int_arm_neon_vrecps,
 568                                        v2f32, v4f32, v2f64, 0>;
 569
 570 // Vector Reciprocal Square Root Step (Floating Point)
 571 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 572                                         int_arm_neon_vrsqrts,
 573                                         int_arm_neon_vrsqrts,
 574                                         int_arm_neon_vrsqrts,
 575                                         v2f32, v4f32, v2f64, 0>;
 576
 577 // Vector Comparisons
 578
 579 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 580                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 581 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 582                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 583 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 584                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 585 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 586                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 587 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 588                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 589
 590 // NeonI_compare_aliases class: swaps register operands to implement
 591 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 592 class NeonI_compare_aliases<string asmop, string asmlane,
 593                             Instruction inst, RegisterOperand VPRC>
 594   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 595                     ", $Rm" # asmlane,
 596                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 597
 598 // Vector Comparisons (Integer)
 599
 600 // Vector Compare Mask Equal (Integer)
 601 let isCommutable =1 in {
 602 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 603 }
 604
 605 // Vector Compare Mask Higher or Same (Unsigned Integer)
 606 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 607
 608 // Vector Compare Mask Greater Than or Equal (Integer)
 609 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 610
 611 // Vector Compare Mask Higher (Unsigned Integer)
 612 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 613
 614 // Vector Compare Mask Greater Than (Integer)
 615 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 616
 617 // Vector Compare Mask Bitwise Test (Integer)
 618 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 619
 620 // Vector Compare Mask Less or Same (Unsigned Integer)
 621 // CMLS is alias for CMHS with operands reversed.
 622 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 623 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 624 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 625 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 626 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 627 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 628 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 629
 630 // Vector Compare Mask Less Than or Equal (Integer)
 631 // CMLE is alias for CMGE with operands reversed.
 632 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 633 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 634 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 635 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 636 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 637 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 638 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 639
 640 // Vector Compare Mask Lower (Unsigned Integer)
 641 // CMLO is alias for CMHI with operands reversed.
 642 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 643 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 644 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 645 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 646 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 647 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 648 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 649
 650 // Vector Compare Mask Less Than (Integer)
 651 // CMLT is alias for CMGT with operands reversed.
 652 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 653 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 654 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 655 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 656 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 657 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 658 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 659
 660
 661 def neon_uimm0_asmoperand : AsmOperandClass
 662 {
 663   let Name = "UImm0";
 664   let PredicateMethod = "isUImm<0>";
 665   let RenderMethod = "addImmOperands";
 666 }
 667
 668 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 669   let ParserMatchClass = neon_uimm0_asmoperand;
 670   let PrintMethod = "printNeonUImm0Operand";
 671
 672 }
 673
 674 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 675 {
 676   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 677              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 678              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 679              [(set (v8i8 VPR64:$Rd),
 680                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 681              NoItinerary>;
 682
 683   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 684              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 685              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 686              [(set (v16i8 VPR128:$Rd),
 687                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 688              NoItinerary>;
 689
 690   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 691             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 692             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 693             [(set (v4i16 VPR64:$Rd),
 694                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 695             NoItinerary>;
 696
 697   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 698             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 699             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 700             [(set (v8i16 VPR128:$Rd),
 701                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 702             NoItinerary>;
 703
 704   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 705             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 706             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 707             [(set (v2i32 VPR64:$Rd),
 708                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 709             NoItinerary>;
 710
 711   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 712             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 713             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 714             [(set (v4i32 VPR128:$Rd),
 715                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 716             NoItinerary>;
 717
 718   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 719             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 720             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 721             [(set (v2i64 VPR128:$Rd),
 722                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 723             NoItinerary>;
 724 }
 725
 726 // Vector Compare Mask Equal to Zero (Integer)
 727 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 728
 729 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 730 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 731
 732 // Vector Compare Mask Greater Than Zero (Signed Integer)
 733 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 734
 735 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 736 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 737
 738 // Vector Compare Mask Less Than Zero (Signed Integer)
 739 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 740
 741 // Vector Comparisons (Floating Point)
 742
 743 // Vector Compare Mask Equal (Floating Point)
 744 let isCommutable =1 in {
 745 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 746                                       Neon_cmeq, Neon_cmeq,
 747                                       v2i32, v4i32, v2i64, 0>;
 748 }
 749
 750 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 751 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 752                                       Neon_cmge, Neon_cmge,
 753                                       v2i32, v4i32, v2i64, 0>;
 754
 755 // Vector Compare Mask Greater Than (Floating Point)
 756 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 757                                       Neon_cmgt, Neon_cmgt,
 758                                       v2i32, v4i32, v2i64, 0>;
 759
 760 // Vector Compare Mask Less Than Or Equal (Floating Point)
 761 // FCMLE is alias for FCMGE with operands reversed.
 762 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 763 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 764 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 765
 766 // Vector Compare Mask Less Than (Floating Point)
 767 // FCMLT is alias for FCMGT with operands reversed.
 768 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 769 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 770 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 771
 772
 773 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 774                               string asmop, CondCode CC>
 775 {
 776   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 777             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 778             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 779             [(set (v2i32 VPR64:$Rd),
 780                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpz32:$FPImm), CC)))],
 781             NoItinerary>;
 782
 783   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 784             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 785             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 786             [(set (v4i32 VPR128:$Rd),
 787                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 788             NoItinerary>;
 789
 790   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 791             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 792             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 793             [(set (v2i64 VPR128:$Rd),
 794                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 795             NoItinerary>;
 796 }
 797
 798 // Vector Compare Mask Equal to Zero (Floating Point)
 799 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 800
 801 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 802 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 803
 804 // Vector Compare Mask Greater Than Zero (Floating Point)
 805 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 806
 807 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 808 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 809
 810 // Vector Compare Mask Less Than Zero (Floating Point)
 811 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 812
 813 // Vector Absolute Comparisons (Floating Point)
 814
 815 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 816 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 817                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 818                                       int_aarch64_neon_vacgeq,
 819                                       v2i32, v4i32, v2i64, 0>;
 820
 821 // Vector Absolute Compare Mask Greater Than (Floating Point)
 822 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 823                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 824                                       int_aarch64_neon_vacgtq,
 825                                       v2i32, v4i32, v2i64, 0>;
 826
 827 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 828 // FACLE is alias for FACGE with operands reversed.
 829 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 830 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 831 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 832
 833 // Vector Absolute Compare Mask Less Than (Floating Point)
 834 // FACLT is alias for FACGT with operands reversed.
 835 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 836 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 837 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 838
 839 // Vector halving add (Integer Signed, Unsigned)
 840 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 841                                         int_arm_neon_vhadds, 1>;
 842 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 843                                         int_arm_neon_vhaddu, 1>;
 844
 845 // Vector halving sub (Integer Signed, Unsigned)
 846 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 847                                         int_arm_neon_vhsubs, 0>;
 848 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 849                                         int_arm_neon_vhsubu, 0>;
 850
 851 // Vector rouding halving add (Integer Signed, Unsigned)
 852 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 853                                          int_arm_neon_vrhadds, 1>;
 854 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 855                                          int_arm_neon_vrhaddu, 1>;
 856
 857 // Vector Saturating add (Integer Signed, Unsigned)
 858 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 859                    int_arm_neon_vqadds, 1>;
 860 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 861                    int_arm_neon_vqaddu, 1>;
 862
 863 // Vector Saturating sub (Integer Signed, Unsigned)
 864 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 865                    int_arm_neon_vqsubs, 1>;
 866 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 867                    int_arm_neon_vqsubu, 1>;
 868
 869 // Vector Shift Left (Signed and Unsigned Integer)
 870 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 871                  int_arm_neon_vshifts, 1>;
 872 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 873                  int_arm_neon_vshiftu, 1>;
 874
 875 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 876 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 877                   int_arm_neon_vqshifts, 1>;
 878 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 879                   int_arm_neon_vqshiftu, 1>;
 880
 881 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 882 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 883                   int_arm_neon_vrshifts, 1>;
 884 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 885                   int_arm_neon_vrshiftu, 1>;
 886
 887 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 888 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 889                    int_arm_neon_vqrshifts, 1>;
 890 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 891                    int_arm_neon_vqrshiftu, 1>;
 892
 893 // Vector Maximum (Signed and Unsigned Integer)
 894 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 895 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 896
 897 // Vector Minimum (Signed and Unsigned Integer)
 898 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 899 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 900
 901 // Vector Maximum (Floating Point)
 902 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 903                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 904                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 905
 906 // Vector Minimum (Floating Point)
 907 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 908                                      int_arm_neon_vmins, int_arm_neon_vmins,
 909                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 910
 911 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 912 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 913                                        int_aarch64_neon_vmaxnm,
 914                                        int_aarch64_neon_vmaxnm,
 915                                        int_aarch64_neon_vmaxnm,
 916                                        v2f32, v4f32, v2f64, 1>;
 917
 918 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 919 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 920                                        int_aarch64_neon_vminnm,
 921                                        int_aarch64_neon_vminnm,
 922                                        int_aarch64_neon_vminnm,
 923                                        v2f32, v4f32, v2f64, 1>;
 924
 925 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 926 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 927 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 928
 929 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 930 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 931 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 932
 933 // Vector Maximum Pairwise (Floating Point)
 934 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 935                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 936                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 937
 938 // Vector Minimum Pairwise (Floating Point)
 939 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 940                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 941                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 942
 943 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 944 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 945                                        int_aarch64_neon_vpmaxnm,
 946                                        int_aarch64_neon_vpmaxnm,
 947                                        int_aarch64_neon_vpmaxnm,
 948                                        v2f32, v4f32, v2f64, 1>;
 949
 950 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 951 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 952                                        int_aarch64_neon_vpminnm,
 953                                        int_aarch64_neon_vpminnm,
 954                                        int_aarch64_neon_vpminnm,
 955                                        v2f32, v4f32, v2f64, 1>;
 956
 957 // Vector Addition Pairwise (Integer)
 958 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 959
 960 // Vector Addition Pairwise (Floating Point)
 961 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 962                                        int_arm_neon_vpadd,
 963                                        int_arm_neon_vpadd,
 964                                        int_arm_neon_vpadd,
 965                                        v2f32, v4f32, v2f64, 1>;
 966
 967 // Vector Saturating Doubling Multiply High
 968 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 969                     int_arm_neon_vqdmulh, 1>;
 970
 971 // Vector Saturating Rouding Doubling Multiply High
 972 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 973                      int_arm_neon_vqrdmulh, 1>;
 974
 975 // Vector Multiply Extended (Floating Point)
 976 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 977                                       int_aarch64_neon_vmulx,
 978                                       int_aarch64_neon_vmulx,
 979                                       int_aarch64_neon_vmulx,
 980                                       v2f32, v4f32, v2f64, 1>;
 981
 982 // Patterns to match llvm.aarch64.* intrinsic for
 983 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
 984 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
 985   : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
 986         (EXTRACT_SUBREG
 987              (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
 988              sub_32)>;
 989
 990 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
 991 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
 992 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
 993 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
 994 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
 995
 996 // Vector Immediate Instructions
 997
 998 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 999 {
1000   def _asmoperand : AsmOperandClass
1001     {
1002       let Name = "NeonMovImmShift" # PREFIX;
1003       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1004       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1005     }
1006 }
1007
1008 // Definition of vector immediates shift operands
1009
1010 // The selectable use-cases extract the shift operation
1011 // information from the OpCmode fields encoded in the immediate.
1012 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1013   uint64_t OpCmode = N->getZExtValue();
1014   unsigned ShiftImm;
1015   unsigned ShiftOnesIn;
1016   unsigned HasShift =
1017     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1018   if (!HasShift) return SDValue();
1019   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1020 }]>;
1021
1022 // Vector immediates shift operands which accept LSL and MSL
1023 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1024 // or 0, 8 (LSLH) or 8, 16 (MSL).
1025 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1026 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1027 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1028 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1029
1030 multiclass neon_mov_imm_shift_operands<string PREFIX,
1031                                        string HALF, string ISHALF, code pred>
1032 {
1033    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1034     {
1035       let PrintMethod =
1036         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1037       let DecoderMethod =
1038         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1039       let ParserMatchClass =
1040         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1041     }
1042 }
1043
1044 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1045   unsigned ShiftImm;
1046   unsigned ShiftOnesIn;
1047   unsigned HasShift =
1048     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1049   return (HasShift && !ShiftOnesIn);
1050 }]>;
1051
1052 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1053   unsigned ShiftImm;
1054   unsigned ShiftOnesIn;
1055   unsigned HasShift =
1056     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1057   return (HasShift && ShiftOnesIn);
1058 }]>;
1059
1060 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1061   unsigned ShiftImm;
1062   unsigned ShiftOnesIn;
1063   unsigned HasShift =
1064     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1065   return (HasShift && !ShiftOnesIn);
1066 }]>;
1067
1068 def neon_uimm1_asmoperand : AsmOperandClass
1069 {
1070   let Name = "UImm1";
1071   let PredicateMethod = "isUImm<1>";
1072   let RenderMethod = "addImmOperands";
1073 }
1074
1075 def neon_uimm2_asmoperand : AsmOperandClass
1076 {
1077   let Name = "UImm2";
1078   let PredicateMethod = "isUImm<2>";
1079   let RenderMethod = "addImmOperands";
1080 }
1081
1082 def neon_uimm8_asmoperand : AsmOperandClass
1083 {
1084   let Name = "UImm8";
1085   let PredicateMethod = "isUImm<8>";
1086   let RenderMethod = "addImmOperands";
1087 }
1088
1089 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1090   let ParserMatchClass = neon_uimm8_asmoperand;
1091   let PrintMethod = "printUImmHexOperand";
1092 }
1093
1094 def neon_uimm64_mask_asmoperand : AsmOperandClass
1095 {
1096   let Name = "NeonUImm64Mask";
1097   let PredicateMethod = "isNeonUImm64Mask";
1098   let RenderMethod = "addNeonUImm64MaskOperands";
1099 }
1100
1101 // MCOperand for 64-bit bytemask with each byte having only the
1102 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1103 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1104   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1105   let PrintMethod = "printNeonUImm64MaskOperand";
1106 }
1107
1108 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1109                                    SDPatternOperator opnode>
1110 {
1111     // shift zeros, per word
1112     def _2S  : NeonI_1VModImm<0b0, op,
1113                               (outs VPR64:$Rd),
1114                               (ins neon_uimm8:$Imm,
1115                                 neon_mov_imm_LSL_operand:$Simm),
1116                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1117                               [(set (v2i32 VPR64:$Rd),
1118                                  (v2i32 (opnode (timm:$Imm),
1119                                    (neon_mov_imm_LSL_operand:$Simm))))],
1120                               NoItinerary> {
1121        bits<2> Simm;
1122        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1123      }
1124
1125     def _4S  : NeonI_1VModImm<0b1, op,
1126                               (outs VPR128:$Rd),
1127                               (ins neon_uimm8:$Imm,
1128                                 neon_mov_imm_LSL_operand:$Simm),
1129                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1130                               [(set (v4i32 VPR128:$Rd),
1131                                  (v4i32 (opnode (timm:$Imm),
1132                                    (neon_mov_imm_LSL_operand:$Simm))))],
1133                               NoItinerary> {
1134       bits<2> Simm;
1135       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1136     }
1137
1138     // shift zeros, per halfword
1139     def _4H  : NeonI_1VModImm<0b0, op,
1140                               (outs VPR64:$Rd),
1141                               (ins neon_uimm8:$Imm,
1142                                 neon_mov_imm_LSLH_operand:$Simm),
1143                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1144                               [(set (v4i16 VPR64:$Rd),
1145                                  (v4i16 (opnode (timm:$Imm),
1146                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1147                               NoItinerary> {
1148       bit  Simm;
1149       let cmode = {0b1, 0b0, Simm, 0b0};
1150     }
1151
1152     def _8H  : NeonI_1VModImm<0b1, op,
1153                               (outs VPR128:$Rd),
1154                               (ins neon_uimm8:$Imm,
1155                                 neon_mov_imm_LSLH_operand:$Simm),
1156                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1157                               [(set (v8i16 VPR128:$Rd),
1158                                  (v8i16 (opnode (timm:$Imm),
1159                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1160                               NoItinerary> {
1161       bit Simm;
1162       let cmode = {0b1, 0b0, Simm, 0b0};
1163      }
1164 }
1165
1166 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1167                                                    SDPatternOperator opnode,
1168                                                    SDPatternOperator neonopnode>
1169 {
1170   let Constraints = "$src = $Rd" in {
1171     // shift zeros, per word
1172     def _2S  : NeonI_1VModImm<0b0, op,
1173                  (outs VPR64:$Rd),
1174                  (ins VPR64:$src, neon_uimm8:$Imm,
1175                    neon_mov_imm_LSL_operand:$Simm),
1176                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1177                  [(set (v2i32 VPR64:$Rd),
1178                     (v2i32 (opnode (v2i32 VPR64:$src),
1179                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1180                         neon_mov_imm_LSL_operand:$Simm)))))))],
1181                  NoItinerary> {
1182       bits<2> Simm;
1183       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1184     }
1185
1186     def _4S  : NeonI_1VModImm<0b1, op,
1187                  (outs VPR128:$Rd),
1188                  (ins VPR128:$src, neon_uimm8:$Imm,
1189                    neon_mov_imm_LSL_operand:$Simm),
1190                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1191                  [(set (v4i32 VPR128:$Rd),
1192                     (v4i32 (opnode (v4i32 VPR128:$src),
1193                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1194                         neon_mov_imm_LSL_operand:$Simm)))))))],
1195                  NoItinerary> {
1196       bits<2> Simm;
1197       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1198     }
1199
1200     // shift zeros, per halfword
1201     def _4H  : NeonI_1VModImm<0b0, op,
1202                  (outs VPR64:$Rd),
1203                  (ins VPR64:$src, neon_uimm8:$Imm,
1204                    neon_mov_imm_LSLH_operand:$Simm),
1205                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1206                  [(set (v4i16 VPR64:$Rd),
1207                     (v4i16 (opnode (v4i16 VPR64:$src),
1208                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1209                           neon_mov_imm_LSL_operand:$Simm)))))))],
1210                  NoItinerary> {
1211       bit  Simm;
1212       let cmode = {0b1, 0b0, Simm, 0b1};
1213     }
1214
1215     def _8H  : NeonI_1VModImm<0b1, op,
1216                  (outs VPR128:$Rd),
1217                  (ins VPR128:$src, neon_uimm8:$Imm,
1218                    neon_mov_imm_LSLH_operand:$Simm),
1219                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1220                  [(set (v8i16 VPR128:$Rd),
1221                     (v8i16 (opnode (v8i16 VPR128:$src),
1222                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1223                         neon_mov_imm_LSL_operand:$Simm)))))))],
1224                  NoItinerary> {
1225       bit Simm;
1226       let cmode = {0b1, 0b0, Simm, 0b1};
1227     }
1228   }
1229 }
1230
1231 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1232                                    SDPatternOperator opnode>
1233 {
1234     // shift ones, per word
1235     def _2S  : NeonI_1VModImm<0b0, op,
1236                              (outs VPR64:$Rd),
1237                              (ins neon_uimm8:$Imm,
1238                                neon_mov_imm_MSL_operand:$Simm),
1239                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1240                               [(set (v2i32 VPR64:$Rd),
1241                                  (v2i32 (opnode (timm:$Imm),
1242                                    (neon_mov_imm_MSL_operand:$Simm))))],
1243                              NoItinerary> {
1244        bit Simm;
1245        let cmode = {0b1, 0b1, 0b0, Simm};
1246      }
1247
1248    def _4S  : NeonI_1VModImm<0b1, op,
1249                               (outs VPR128:$Rd),
1250                               (ins neon_uimm8:$Imm,
1251                                 neon_mov_imm_MSL_operand:$Simm),
1252                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1253                               [(set (v4i32 VPR128:$Rd),
1254                                  (v4i32 (opnode (timm:$Imm),
1255                                    (neon_mov_imm_MSL_operand:$Simm))))],
1256                               NoItinerary> {
1257      bit Simm;
1258      let cmode = {0b1, 0b1, 0b0, Simm};
1259    }
1260 }
1261
1262 // Vector Move Immediate Shifted
1263 let isReMaterializable = 1 in {
1264 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1265 }
1266
1267 // Vector Move Inverted Immediate Shifted
1268 let isReMaterializable = 1 in {
1269 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1270 }
1271
1272 // Vector Bitwise Bit Clear (AND NOT) - immediate
1273 let isReMaterializable = 1 in {
1274 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1275                                                          and, Neon_mvni>;
1276 }
1277
1278 // Vector Bitwise OR - immedidate
1279
1280 let isReMaterializable = 1 in {
1281 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1282                                                            or, Neon_movi>;
1283 }
1284
1285 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1286 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1287 // BIC immediate instructions selection requires additional patterns to
1288 // transform Neon_movi operands into BIC immediate operands
1289
1290 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1291   uint64_t OpCmode = N->getZExtValue();
1292   unsigned ShiftImm;
1293   unsigned ShiftOnesIn;
1294   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1295   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1296   // Transform encoded shift amount 0 to 1 and 1 to 0.
1297   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1298 }]>;
1299
1300 def neon_mov_imm_LSLH_transform_operand
1301   : ImmLeaf<i32, [{
1302     unsigned ShiftImm;
1303     unsigned ShiftOnesIn;
1304     unsigned HasShift =
1305       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1306     return (HasShift && !ShiftOnesIn); }],
1307   neon_mov_imm_LSLH_transform_XFORM>;
1308
1309 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1310 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1311 def : Pat<(v4i16 (and VPR64:$src,
1312             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1313           (BICvi_lsl_4H VPR64:$src, 0,
1314             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1315
1316 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1317 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1318 def : Pat<(v8i16 (and VPR128:$src,
1319             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1320           (BICvi_lsl_8H VPR128:$src, 0,
1321             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1322
1323
1324 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1325                                    SDPatternOperator neonopnode,
1326                                    Instruction INST4H,
1327                                    Instruction INST8H> {
1328   def : Pat<(v8i8 (opnode VPR64:$src,
1329                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1330                       neon_mov_imm_LSLH_operand:$Simm))))),
1331             (INST4H VPR64:$src, neon_uimm8:$Imm,
1332               neon_mov_imm_LSLH_operand:$Simm)>;
1333   def : Pat<(v1i64 (opnode VPR64:$src,
1334                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1335                     neon_mov_imm_LSLH_operand:$Simm))))),
1336           (INST4H VPR64:$src, neon_uimm8:$Imm,
1337             neon_mov_imm_LSLH_operand:$Simm)>;
1338
1339   def : Pat<(v16i8 (opnode VPR128:$src,
1340                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1341                      neon_mov_imm_LSLH_operand:$Simm))))),
1342           (INST8H VPR128:$src, neon_uimm8:$Imm,
1343             neon_mov_imm_LSLH_operand:$Simm)>;
1344   def : Pat<(v4i32 (opnode VPR128:$src,
1345                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1346                      neon_mov_imm_LSLH_operand:$Simm))))),
1347           (INST8H VPR128:$src, neon_uimm8:$Imm,
1348             neon_mov_imm_LSLH_operand:$Simm)>;
1349   def : Pat<(v2i64 (opnode VPR128:$src,
1350                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1351                      neon_mov_imm_LSLH_operand:$Simm))))),
1352           (INST8H VPR128:$src, neon_uimm8:$Imm,
1353             neon_mov_imm_LSLH_operand:$Simm)>;
1354 }
1355
1356 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1357 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1358
1359 // Additional patterns for Vector Bitwise OR - immedidate
1360 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1361
1362
1363 // Vector Move Immediate Masked
1364 let isReMaterializable = 1 in {
1365 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1366 }
1367
1368 // Vector Move Inverted Immediate Masked
1369 let isReMaterializable = 1 in {
1370 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1371 }
1372
1373 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1374                                 Instruction inst, RegisterOperand VPRC>
1375   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1376                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1377
1378 // Aliases for Vector Move Immediate Shifted
1379 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1380 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1381 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1382 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1383
1384 // Aliases for Vector Move Inverted Immediate Shifted
1385 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1386 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1387 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1388 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1389
1390 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1391 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1392 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1393 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1394 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1395
1396 // Aliases for Vector Bitwise OR - immedidate
1397 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1398 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1399 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1400 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1401
1402 //  Vector Move Immediate - per byte
1403 let isReMaterializable = 1 in {
1404 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1405                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1406                                "movi\t$Rd.8b, $Imm",
1407                                [(set (v8i8 VPR64:$Rd),
1408                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1409                                 NoItinerary> {
1410   let cmode = 0b1110;
1411 }
1412
1413 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1414                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1415                                 "movi\t$Rd.16b, $Imm",
1416                                 [(set (v16i8 VPR128:$Rd),
1417                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1418                                  NoItinerary> {
1419   let cmode = 0b1110;
1420 }
1421 }
1422
1423 // Vector Move Immediate - bytemask, per double word
1424 let isReMaterializable = 1 in {
1425 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1426                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1427                                "movi\t $Rd.2d, $Imm",
1428                                [(set (v2i64 VPR128:$Rd),
1429                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1430                                NoItinerary> {
1431   let cmode = 0b1110;
1432 }
1433 }
1434
1435 // Vector Move Immediate - bytemask, one doubleword
1436
1437 let isReMaterializable = 1 in {
1438 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1439                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1440                            "movi\t $Rd, $Imm",
1441                            [(set (v1i64 FPR64:$Rd),
1442                              (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1443                            NoItinerary> {
1444   let cmode = 0b1110;
1445 }
1446 }
1447
1448 // Vector Floating Point Move Immediate
1449
1450 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1451                       Operand immOpType, bit q, bit op>
1452   : NeonI_1VModImm<q, op,
1453                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1454                    "fmov\t$Rd" # asmlane # ", $Imm",
1455                    [(set (OpTy VPRC:$Rd),
1456                       (OpTy (Neon_fmovi (timm:$Imm))))],
1457                    NoItinerary> {
1458      let cmode = 0b1111;
1459    }
1460
1461 let isReMaterializable = 1 in {
1462 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1463 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1464 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1465 }
1466
1467 // Vector Shift (Immediate)
1468 // Immediate in [0, 63]
1469 def imm0_63 : Operand<i32> {
1470   let ParserMatchClass = uimm6_asmoperand;
1471 }
1472
1473 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1474 // as follows:
1475 //
1476 //    Offset    Encoding
1477 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1478 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1479 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1480 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1481 //
1482 // The shift right immediate amount, in the range 1 to element bits, is computed
1483 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1484 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1485
1486 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1487   let Name = "ShrImm" # OFFSET;
1488   let RenderMethod = "addImmOperands";
1489   let DiagnosticType = "ShrImm" # OFFSET;
1490 }
1491
1492 class shr_imm<string OFFSET> : Operand<i32> {
1493   let EncoderMethod = "getShiftRightImm" # OFFSET;
1494   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1495   let ParserMatchClass =
1496     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1497 }
1498
1499 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1500 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1501 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1502 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1503
1504 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1505 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1506 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1507 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1508
1509 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1510   let Name = "ShlImm" # OFFSET;
1511   let RenderMethod = "addImmOperands";
1512   let DiagnosticType = "ShlImm" # OFFSET;
1513 }
1514
1515 class shl_imm<string OFFSET> : Operand<i32> {
1516   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1517   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1518   let ParserMatchClass =
1519     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1520 }
1521
1522 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1523 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1524 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1525 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1526
1527 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1528 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1529 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1530 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1531
1532 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1533                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1534   : NeonI_2VShiftImm<q, u, opcode,
1535                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1536                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1537                      [(set (Ty VPRC:$Rd),
1538                         (Ty (OpNode (Ty VPRC:$Rn),
1539                           (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1540                      NoItinerary>;
1541
1542 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1543   // 64-bit vector types.
1544   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1545     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1546   }
1547
1548   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1549     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1550   }
1551
1552   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1553     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1554   }
1555
1556   // 128-bit vector types.
1557   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1558     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1559   }
1560
1561   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1562     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1563   }
1564
1565   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1566     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1567   }
1568
1569   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1570     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1571   }
1572 }
1573
1574 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1575   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1576                      OpNode> {
1577     let Inst{22-19} = 0b0001;
1578   }
1579
1580   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1581                      OpNode> {
1582     let Inst{22-20} = 0b001;
1583   }
1584
1585   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1586                      OpNode> {
1587      let Inst{22-21} = 0b01;
1588   }
1589
1590   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1591                       OpNode> {
1592                       let Inst{22-19} = 0b0001;
1593                     }
1594
1595   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1596                      OpNode> {
1597                      let Inst{22-20} = 0b001;
1598                     }
1599
1600   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1601                      OpNode> {
1602                       let Inst{22-21} = 0b01;
1603                     }
1604
1605   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1606                      OpNode> {
1607                       let Inst{22} = 0b1;
1608                     }
1609 }
1610
1611 // Shift left
1612 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1613
1614 // Shift right
1615 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1616 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1617
1618 def Neon_High16B : PatFrag<(ops node:$in),
1619                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1620 def Neon_High8H  : PatFrag<(ops node:$in),
1621                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1622 def Neon_High4S  : PatFrag<(ops node:$in),
1623                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1624 def Neon_High2D  : PatFrag<(ops node:$in),
1625                            (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1626 def Neon_High4float : PatFrag<(ops node:$in),
1627                                (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1628 def Neon_High2double : PatFrag<(ops node:$in),
1629                                (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1630
1631 def Neon_Low16B : PatFrag<(ops node:$in),
1632                           (v8i8 (extract_subvector (v16i8 node:$in),
1633                                                    (iPTR 0)))>;
1634 def Neon_Low8H : PatFrag<(ops node:$in),
1635                          (v4i16 (extract_subvector (v8i16 node:$in),
1636                                                    (iPTR 0)))>;
1637 def Neon_Low4S : PatFrag<(ops node:$in),
1638                          (v2i32 (extract_subvector (v4i32 node:$in),
1639                                                    (iPTR 0)))>;
1640 def Neon_Low2D : PatFrag<(ops node:$in),
1641                          (v1i64 (extract_subvector (v2i64 node:$in),
1642                                                    (iPTR 0)))>;
1643 def Neon_Low4float : PatFrag<(ops node:$in),
1644                              (v2f32 (extract_subvector (v4f32 node:$in),
1645                                                        (iPTR 0)))>;
1646 def Neon_Low2double : PatFrag<(ops node:$in),
1647                               (v1f64 (extract_subvector (v2f64 node:$in),
1648                                                         (iPTR 0)))>;
1649
1650 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1651                    string SrcT, ValueType DestTy, ValueType SrcTy,
1652                    Operand ImmTy, SDPatternOperator ExtOp>
1653   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1654                      (ins VPR64:$Rn, ImmTy:$Imm),
1655                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1656                      [(set (DestTy VPR128:$Rd),
1657                         (DestTy (shl
1658                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1659                             (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1660                      NoItinerary>;
1661
1662 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1663                        string SrcT, ValueType DestTy, ValueType SrcTy,
1664                        int StartIndex, Operand ImmTy,
1665                        SDPatternOperator ExtOp, PatFrag getTop>
1666   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1667                      (ins VPR128:$Rn, ImmTy:$Imm),
1668                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1669                      [(set (DestTy VPR128:$Rd),
1670                         (DestTy (shl
1671                           (DestTy (ExtOp
1672                             (SrcTy (getTop VPR128:$Rn)))),
1673                               (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1674                      NoItinerary>;
1675
1676 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1677                          SDNode ExtOp> {
1678   // 64-bit vector types.
1679   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1680                          shl_imm8, ExtOp> {
1681     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1682   }
1683
1684   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1685                          shl_imm16, ExtOp> {
1686     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1687   }
1688
1689   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1690                          shl_imm32, ExtOp> {
1691     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1692   }
1693
1694   // 128-bit vector types
1695   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1696                               8, shl_imm8, ExtOp, Neon_High16B> {
1697     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1698   }
1699
1700   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1701                              4, shl_imm16, ExtOp, Neon_High8H> {
1702     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1703   }
1704
1705   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1706                              2, shl_imm32, ExtOp, Neon_High4S> {
1707     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1708   }
1709
1710   // Use other patterns to match when the immediate is 0.
1711   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1712             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1713
1714   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1715             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1716
1717   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1718             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1719
1720   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1721             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1722
1723   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1724             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1725
1726   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1727             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1728 }
1729
1730 // Shift left long
1731 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1732 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1733
1734 // Rounding/Saturating shift
1735 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1736                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1737                   SDPatternOperator OpNode>
1738   : NeonI_2VShiftImm<q, u, opcode,
1739                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1740                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1741                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1742                         (i32 ImmTy:$Imm))))],
1743                      NoItinerary>;
1744
1745 // shift right (vector by immediate)
1746 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1747                            SDPatternOperator OpNode> {
1748   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1749                          OpNode> {
1750     let Inst{22-19} = 0b0001;
1751   }
1752
1753   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1754                          OpNode> {
1755     let Inst{22-20} = 0b001;
1756   }
1757
1758   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1759                          OpNode> {
1760     let Inst{22-21} = 0b01;
1761   }
1762
1763   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1764                          OpNode> {
1765     let Inst{22-19} = 0b0001;
1766   }
1767
1768   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1769                         OpNode> {
1770     let Inst{22-20} = 0b001;
1771   }
1772
1773   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1774                         OpNode> {
1775     let Inst{22-21} = 0b01;
1776   }
1777
1778   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1779                         OpNode> {
1780     let Inst{22} = 0b1;
1781   }
1782 }
1783
1784 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1785                           SDPatternOperator OpNode> {
1786   // 64-bit vector types.
1787   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1788                         OpNode> {
1789     let Inst{22-19} = 0b0001;
1790   }
1791
1792   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1793                         OpNode> {
1794     let Inst{22-20} = 0b001;
1795   }
1796
1797   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1798                         OpNode> {
1799     let Inst{22-21} = 0b01;
1800   }
1801
1802   // 128-bit vector types.
1803   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1804                          OpNode> {
1805     let Inst{22-19} = 0b0001;
1806   }
1807
1808   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1809                         OpNode> {
1810     let Inst{22-20} = 0b001;
1811   }
1812
1813   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1814                         OpNode> {
1815     let Inst{22-21} = 0b01;
1816   }
1817
1818   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1819                         OpNode> {
1820     let Inst{22} = 0b1;
1821   }
1822 }
1823
1824 // Rounding shift right
1825 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1826                                 int_aarch64_neon_vsrshr>;
1827 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1828                                 int_aarch64_neon_vurshr>;
1829
1830 // Saturating shift left unsigned
1831 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1832
1833 // Saturating shift left
1834 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1835 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1836
1837 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1838                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1839                   SDNode OpNode>
1840   : NeonI_2VShiftImm<q, u, opcode,
1841            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1842            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1843            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1844               (Ty (OpNode (Ty VPRC:$Rn),
1845                 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1846            NoItinerary> {
1847   let Constraints = "$src = $Rd";
1848 }
1849
1850 // Shift Right accumulate
1851 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1852   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1853                         OpNode> {
1854     let Inst{22-19} = 0b0001;
1855   }
1856
1857   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1858                         OpNode> {
1859     let Inst{22-20} = 0b001;
1860   }
1861
1862   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1863                         OpNode> {
1864     let Inst{22-21} = 0b01;
1865   }
1866
1867   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1868                          OpNode> {
1869     let Inst{22-19} = 0b0001;
1870   }
1871
1872   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1873                         OpNode> {
1874     let Inst{22-20} = 0b001;
1875   }
1876
1877   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1878                         OpNode> {
1879     let Inst{22-21} = 0b01;
1880   }
1881
1882   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1883                         OpNode> {
1884     let Inst{22} = 0b1;
1885   }
1886 }
1887
1888 // Shift right and accumulate
1889 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1890 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1891
1892 // Rounding shift accumulate
1893 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1894                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1895                     SDPatternOperator OpNode>
1896   : NeonI_2VShiftImm<q, u, opcode,
1897                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1898                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1899                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1900                         (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
1901                      NoItinerary> {
1902   let Constraints = "$src = $Rd";
1903 }
1904
1905 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1906                              SDPatternOperator OpNode> {
1907   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1908                           OpNode> {
1909     let Inst{22-19} = 0b0001;
1910   }
1911
1912   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1913                           OpNode> {
1914     let Inst{22-20} = 0b001;
1915   }
1916
1917   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1918                           OpNode> {
1919     let Inst{22-21} = 0b01;
1920   }
1921
1922   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1923                            OpNode> {
1924     let Inst{22-19} = 0b0001;
1925   }
1926
1927   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1928                           OpNode> {
1929     let Inst{22-20} = 0b001;
1930   }
1931
1932   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1933                           OpNode> {
1934     let Inst{22-21} = 0b01;
1935   }
1936
1937   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1938                           OpNode> {
1939     let Inst{22} = 0b1;
1940   }
1941 }
1942
1943 // Rounding shift right and accumulate
1944 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1945 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1946
1947 // Shift insert by immediate
1948 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1949                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1950                   SDPatternOperator OpNode>
1951     : NeonI_2VShiftImm<q, u, opcode,
1952            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1953            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1954            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1955              (i32 ImmTy:$Imm))))],
1956            NoItinerary> {
1957   let Constraints = "$src = $Rd";
1958 }
1959
1960 // shift left insert (vector by immediate)
1961 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1962   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1963                         int_aarch64_neon_vsli> {
1964     let Inst{22-19} = 0b0001;
1965   }
1966
1967   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1968                         int_aarch64_neon_vsli> {
1969     let Inst{22-20} = 0b001;
1970   }
1971
1972   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1973                         int_aarch64_neon_vsli> {
1974     let Inst{22-21} = 0b01;
1975   }
1976
1977     // 128-bit vector types
1978   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1979                          int_aarch64_neon_vsli> {
1980     let Inst{22-19} = 0b0001;
1981   }
1982
1983   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1984                         int_aarch64_neon_vsli> {
1985     let Inst{22-20} = 0b001;
1986   }
1987
1988   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1989                         int_aarch64_neon_vsli> {
1990     let Inst{22-21} = 0b01;
1991   }
1992
1993   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1994                         int_aarch64_neon_vsli> {
1995     let Inst{22} = 0b1;
1996   }
1997 }
1998
1999 // shift right insert (vector by immediate)
2000 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2001     // 64-bit vector types.
2002   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2003                         int_aarch64_neon_vsri> {
2004     let Inst{22-19} = 0b0001;
2005   }
2006
2007   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2008                         int_aarch64_neon_vsri> {
2009     let Inst{22-20} = 0b001;
2010   }
2011
2012   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2013                         int_aarch64_neon_vsri> {
2014     let Inst{22-21} = 0b01;
2015   }
2016
2017     // 128-bit vector types
2018   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2019                          int_aarch64_neon_vsri> {
2020     let Inst{22-19} = 0b0001;
2021   }
2022
2023   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2024                         int_aarch64_neon_vsri> {
2025     let Inst{22-20} = 0b001;
2026   }
2027
2028   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2029                         int_aarch64_neon_vsri> {
2030     let Inst{22-21} = 0b01;
2031   }
2032
2033   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2034                         int_aarch64_neon_vsri> {
2035     let Inst{22} = 0b1;
2036   }
2037 }
2038
2039 // Shift left and insert
2040 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2041
2042 // Shift right and insert
2043 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2044
2045 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2046                     string SrcT, Operand ImmTy>
2047   : NeonI_2VShiftImm<q, u, opcode,
2048                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2049                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2050                      [], NoItinerary>;
2051
2052 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2053                        string SrcT, Operand ImmTy>
2054   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2055                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2056                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2057                      [], NoItinerary> {
2058   let Constraints = "$src = $Rd";
2059 }
2060
2061 // left long shift by immediate
2062 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2063   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2064     let Inst{22-19} = 0b0001;
2065   }
2066
2067   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2068     let Inst{22-20} = 0b001;
2069   }
2070
2071   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2072     let Inst{22-21} = 0b01;
2073   }
2074
2075   // Shift Narrow High
2076   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2077                               shr_imm8> {
2078     let Inst{22-19} = 0b0001;
2079   }
2080
2081   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2082                              shr_imm16> {
2083     let Inst{22-20} = 0b001;
2084   }
2085
2086   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2087                              shr_imm32> {
2088     let Inst{22-21} = 0b01;
2089   }
2090 }
2091
2092 // Shift right narrow
2093 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2094
2095 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2096 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2097 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2098 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2099 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2100 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2101 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2102 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2103
2104 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2105                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2106                                                      (v1i64 node:$Rn)))>;
2107 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2108                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2109                                                      (v4i16 node:$Rn)))>;
2110 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2111                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2112                                                      (v2i32 node:$Rn)))>;
2113 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2114                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2115                                                      (v2f32 node:$Rn)))>;
2116 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2117                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2118                                                      (v1f64 node:$Rn)))>;
2119
2120 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2121                              (v8i16 (srl (v8i16 node:$lhs),
2122                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2123 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2124                              (v4i32 (srl (v4i32 node:$lhs),
2125                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2126 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2127                              (v2i64 (srl (v2i64 node:$lhs),
2128                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2129 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2130                              (v8i16 (sra (v8i16 node:$lhs),
2131                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2132 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2133                              (v4i32 (sra (v4i32 node:$lhs),
2134                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2135 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2136                              (v2i64 (sra (v2i64 node:$lhs),
2137                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2138
2139 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2140 multiclass Neon_shiftNarrow_patterns<string shr> {
2141   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2142               (i32 shr_imm8:$Imm)))),
2143             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2144   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2145               (i32 shr_imm16:$Imm)))),
2146             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2147   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2148               (i32 shr_imm32:$Imm)))),
2149             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2150
2151   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2152               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2153                 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2154             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2155                          VPR128:$Rn, imm:$Imm)>;
2156   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2157               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2158                 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2159             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2160                         VPR128:$Rn, imm:$Imm)>;
2161   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2162               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2163                 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2164             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2165                         VPR128:$Rn, imm:$Imm)>;
2166 }
2167
2168 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2169   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2170             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2171   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2172             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2173   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2174             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2175
2176   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2177                 (v1i64 (bitconvert (v8i8
2178                     (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2179             (!cast<Instruction>(prefix # "_16B")
2180                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2181                 VPR128:$Rn, imm:$Imm)>;
2182   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2183                 (v1i64 (bitconvert (v4i16
2184                     (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2185             (!cast<Instruction>(prefix # "_8H")
2186                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2187                 VPR128:$Rn, imm:$Imm)>;
2188   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2189                 (v1i64 (bitconvert (v2i32
2190                     (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2191             (!cast<Instruction>(prefix # "_4S")
2192                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2193                   VPR128:$Rn, imm:$Imm)>;
2194 }
2195
2196 defm : Neon_shiftNarrow_patterns<"lshr">;
2197 defm : Neon_shiftNarrow_patterns<"ashr">;
2198
2199 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2200 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2201 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2202 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2203 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2204 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2205 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2206
2207 // Convert fix-point and float-pointing
2208 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2209                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2210                 Operand ImmTy, SDPatternOperator IntOp>
2211   : NeonI_2VShiftImm<q, u, opcode,
2212                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2213                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2214                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2215                        (i32 ImmTy:$Imm))))],
2216                      NoItinerary>;
2217
2218 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2219                               SDPatternOperator IntOp> {
2220   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2221                       shr_imm32, IntOp> {
2222     let Inst{22-21} = 0b01;
2223   }
2224
2225   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2226                       shr_imm32, IntOp> {
2227     let Inst{22-21} = 0b01;
2228   }
2229
2230   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2231                       shr_imm64, IntOp> {
2232     let Inst{22} = 0b1;
2233   }
2234 }
2235
2236 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2237                               SDPatternOperator IntOp> {
2238   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2239                       shr_imm32, IntOp> {
2240     let Inst{22-21} = 0b01;
2241   }
2242
2243   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2244                       shr_imm32, IntOp> {
2245     let Inst{22-21} = 0b01;
2246   }
2247
2248   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2249                       shr_imm64, IntOp> {
2250     let Inst{22} = 0b1;
2251   }
2252 }
2253
2254 // Convert fixed-point to floating-point
2255 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2256                                    int_arm_neon_vcvtfxs2fp>;
2257 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2258                                    int_arm_neon_vcvtfxu2fp>;
2259
2260 // Convert floating-point to fixed-point
2261 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2262                                    int_arm_neon_vcvtfp2fxs>;
2263 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2264                                    int_arm_neon_vcvtfp2fxu>;
2265
2266 multiclass Neon_sshll2_0<SDNode ext>
2267 {
2268   def _v8i8  : PatFrag<(ops node:$Rn),
2269                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2270   def _v4i16 : PatFrag<(ops node:$Rn),
2271                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2272   def _v2i32 : PatFrag<(ops node:$Rn),
2273                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2274 }
2275
2276 defm NI_sext_high : Neon_sshll2_0<sext>;
2277 defm NI_zext_high : Neon_sshll2_0<zext>;
2278
2279
2280 //===----------------------------------------------------------------------===//
2281 // Multiclasses for NeonI_Across
2282 //===----------------------------------------------------------------------===//
2283
2284 // Variant 1
2285
2286 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2287                             string asmop, SDPatternOperator opnode>
2288 {
2289     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2290                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2291                 asmop # "\t$Rd, $Rn.8b",
2292                 [(set (v1i16 FPR16:$Rd),
2293                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2294                 NoItinerary>;
2295
2296     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2297                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2298                 asmop # "\t$Rd, $Rn.16b",
2299                 [(set (v1i16 FPR16:$Rd),
2300                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2301                 NoItinerary>;
2302
2303     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2304                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2305                 asmop # "\t$Rd, $Rn.4h",
2306                 [(set (v1i32 FPR32:$Rd),
2307                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2308                 NoItinerary>;
2309
2310     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2311                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2312                 asmop # "\t$Rd, $Rn.8h",
2313                 [(set (v1i32 FPR32:$Rd),
2314                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2315                 NoItinerary>;
2316
2317     // _1d2s doesn't exist!
2318
2319     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2320                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2321                 asmop # "\t$Rd, $Rn.4s",
2322                 [(set (v1i64 FPR64:$Rd),
2323                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2324                 NoItinerary>;
2325 }
2326
2327 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2328 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2329
2330 // Variant 2
2331
2332 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2333                             string asmop, SDPatternOperator opnode>
2334 {
2335     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2336                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2337                 asmop # "\t$Rd, $Rn.8b",
2338                 [(set (v1i8 FPR8:$Rd),
2339                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2340                 NoItinerary>;
2341
2342     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2343                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2344                 asmop # "\t$Rd, $Rn.16b",
2345                 [(set (v1i8 FPR8:$Rd),
2346                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2347                 NoItinerary>;
2348
2349     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2350                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2351                 asmop # "\t$Rd, $Rn.4h",
2352                 [(set (v1i16 FPR16:$Rd),
2353                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2354                 NoItinerary>;
2355
2356     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2357                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2358                 asmop # "\t$Rd, $Rn.8h",
2359                 [(set (v1i16 FPR16:$Rd),
2360                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2361                 NoItinerary>;
2362
2363     // _1s2s doesn't exist!
2364
2365     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2366                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2367                 asmop # "\t$Rd, $Rn.4s",
2368                 [(set (v1i32 FPR32:$Rd),
2369                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2370                 NoItinerary>;
2371 }
2372
2373 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2374 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2375
2376 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2377 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2378
2379 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2380
2381 // Variant 3
2382
2383 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2384                             string asmop, SDPatternOperator opnode> {
2385     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2386                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2387                 asmop # "\t$Rd, $Rn.4s",
2388                 [(set (f32 FPR32:$Rd),
2389                     (f32 (opnode (v4f32 VPR128:$Rn))))],
2390                 NoItinerary>;
2391 }
2392
2393 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2394                                 int_aarch64_neon_vmaxnmv>;
2395 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2396                                 int_aarch64_neon_vminnmv>;
2397
2398 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2399                               int_aarch64_neon_vmaxv>;
2400 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2401                               int_aarch64_neon_vminv>;
2402
2403 // The followings are for instruction class (Perm)
2404
2405 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2406                     string asmop, RegisterOperand OpVPR, string OpS,
2407                     SDPatternOperator opnode, ValueType Ty>
2408   : NeonI_Perm<q, size, opcode,
2409                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2410                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2411                [(set (Ty OpVPR:$Rd),
2412                   (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2413                NoItinerary>;
2414
2415 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2416                           SDPatternOperator opnode> {
2417   def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop,
2418                            VPR64, "8b", opnode, v8i8>;
2419   def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2420                            VPR128, "16b",opnode, v16i8>;
2421   def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop,
2422                            VPR64, "4h", opnode, v4i16>;
2423   def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop,
2424                            VPR128, "8h", opnode, v8i16>;
2425   def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop,
2426                            VPR64, "2s", opnode, v2i32>;
2427   def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop,
2428                            VPR128, "4s", opnode, v4i32>;
2429   def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop,
2430                            VPR128, "2d", opnode, v2i64>;
2431 }
2432
2433 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2434 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2435 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2436 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2437 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2438 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2439
2440 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2441   def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2442             (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2443
2444   def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2445             (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2446
2447   def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2448             (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2449 }
2450
2451 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2452 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2453 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2454 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2455 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2456 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2457
2458 // The followings are for instruction class (3V Diff)
2459
2460 // normal long/long2 pattern
2461 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2462                  string asmop, string ResS, string OpS,
2463                  SDPatternOperator opnode, SDPatternOperator ext,
2464                  RegisterOperand OpVPR,
2465                  ValueType ResTy, ValueType OpTy>
2466   : NeonI_3VDiff<q, u, size, opcode,
2467                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2468                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2469                  [(set (ResTy VPR128:$Rd),
2470                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2471                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2472                  NoItinerary>;
2473
2474 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2475                         string asmop, SDPatternOperator opnode,
2476                         bit Commutable = 0> {
2477   let isCommutable = Commutable in {
2478     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2479                            opnode, sext, VPR64, v8i16, v8i8>;
2480     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2481                            opnode, sext, VPR64, v4i32, v4i16>;
2482     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2483                            opnode, sext, VPR64, v2i64, v2i32>;
2484   }
2485 }
2486
2487 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2488                          SDPatternOperator opnode, bit Commutable = 0> {
2489   let isCommutable = Commutable in {
2490     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2491                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2492     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2493                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2494     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2495                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2496   }
2497 }
2498
2499 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2500                         SDPatternOperator opnode, bit Commutable = 0> {
2501   let isCommutable = Commutable in {
2502     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2503                            opnode, zext, VPR64, v8i16, v8i8>;
2504     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2505                            opnode, zext, VPR64, v4i32, v4i16>;
2506     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2507                            opnode, zext, VPR64, v2i64, v2i32>;
2508   }
2509 }
2510
2511 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2512                          SDPatternOperator opnode, bit Commutable = 0> {
2513   let isCommutable = Commutable in {
2514     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2515                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2516     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2517                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2518     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2519                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2520   }
2521 }
2522
2523 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2524 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2525
2526 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2527 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2528
2529 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2530 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2531
2532 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2533 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2534
2535 // normal wide/wide2 pattern
2536 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2537                  string asmop, string ResS, string OpS,
2538                  SDPatternOperator opnode, SDPatternOperator ext,
2539                  RegisterOperand OpVPR,
2540                  ValueType ResTy, ValueType OpTy>
2541   : NeonI_3VDiff<q, u, size, opcode,
2542                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2543                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2544                  [(set (ResTy VPR128:$Rd),
2545                     (ResTy (opnode (ResTy VPR128:$Rn),
2546                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2547                  NoItinerary>;
2548
2549 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2550                         SDPatternOperator opnode> {
2551   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2552                          opnode, sext, VPR64, v8i16, v8i8>;
2553   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2554                          opnode, sext, VPR64, v4i32, v4i16>;
2555   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2556                          opnode, sext, VPR64, v2i64, v2i32>;
2557 }
2558
2559 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2560 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2561
2562 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2563                          SDPatternOperator opnode> {
2564   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2565                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2566   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2567                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2568   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2569                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2570 }
2571
2572 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2573 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2574
2575 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2576                         SDPatternOperator opnode> {
2577   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2578                          opnode, zext, VPR64, v8i16, v8i8>;
2579   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2580                          opnode, zext, VPR64, v4i32, v4i16>;
2581   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2582                          opnode, zext, VPR64, v2i64, v2i32>;
2583 }
2584
2585 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2586 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2587
2588 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2589                          SDPatternOperator opnode> {
2590   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2591                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2592   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2593                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2594   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2595                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2596 }
2597
2598 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2599 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2600
2601 // Get the high half part of the vector element.
2602 multiclass NeonI_get_high {
2603   def _8h : PatFrag<(ops node:$Rn),
2604                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2605                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2606   def _4s : PatFrag<(ops node:$Rn),
2607                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2608                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2609   def _2d : PatFrag<(ops node:$Rn),
2610                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2611                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2612 }
2613
2614 defm NI_get_hi : NeonI_get_high;
2615
2616 // pattern for addhn/subhn with 2 operands
2617 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2618                            string asmop, string ResS, string OpS,
2619                            SDPatternOperator opnode, SDPatternOperator get_hi,
2620                            ValueType ResTy, ValueType OpTy>
2621   : NeonI_3VDiff<q, u, size, opcode,
2622                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2623                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2624                  [(set (ResTy VPR64:$Rd),
2625                     (ResTy (get_hi
2626                       (OpTy (opnode (OpTy VPR128:$Rn),
2627                                     (OpTy VPR128:$Rm))))))],
2628                  NoItinerary>;
2629
2630 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2631                                 SDPatternOperator opnode, bit Commutable = 0> {
2632   let isCommutable = Commutable in {
2633     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2634                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2635     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2636                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2637     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2638                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2639   }
2640 }
2641
2642 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2643 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2644
2645 // pattern for operation with 2 operands
2646 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2647                     string asmop, string ResS, string OpS,
2648                     SDPatternOperator opnode,
2649                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2650                     ValueType ResTy, ValueType OpTy>
2651   : NeonI_3VDiff<q, u, size, opcode,
2652                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2653                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2654                  [(set (ResTy ResVPR:$Rd),
2655                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2656                  NoItinerary>;
2657
2658 // normal narrow pattern
2659 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2660                           SDPatternOperator opnode, bit Commutable = 0> {
2661   let isCommutable = Commutable in {
2662     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2663                               opnode, VPR64, VPR128, v8i8, v8i16>;
2664     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2665                               opnode, VPR64, VPR128, v4i16, v4i32>;
2666     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2667                               opnode, VPR64, VPR128, v2i32, v2i64>;
2668   }
2669 }
2670
2671 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2672 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2673
2674 // pattern for acle intrinsic with 3 operands
2675 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2676                      string asmop, string ResS, string OpS>
2677   : NeonI_3VDiff<q, u, size, opcode,
2678                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2679                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2680                  [], NoItinerary> {
2681   let Constraints = "$src = $Rd";
2682   let neverHasSideEffects = 1;
2683 }
2684
2685 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2686   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2687   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2688   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2689 }
2690
2691 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2692 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2693
2694 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2695 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2696
2697 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2698 // part.
2699 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2700                         SDPatternOperator coreop>
2701   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2702                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2703                                                         (SrcTy VPR128:$Rm)))))),
2704         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2705               VPR128:$Rn, VPR128:$Rm)>;
2706
2707 // addhn2 patterns
2708 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2709           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2710 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2711           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2712 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2713           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2714
2715 // subhn2 patterns
2716 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2717           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2718 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2719           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2720 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2721           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2722
2723 // raddhn2 patterns
2724 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2725 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2726 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2727
2728 // rsubhn2 patterns
2729 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2730 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2731 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2732
2733 // pattern that need to extend result
2734 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2735                      string asmop, string ResS, string OpS,
2736                      SDPatternOperator opnode,
2737                      RegisterOperand OpVPR,
2738                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2739   : NeonI_3VDiff<q, u, size, opcode,
2740                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2741                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2742                  [(set (ResTy VPR128:$Rd),
2743                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2744                                                 (OpTy OpVPR:$Rm))))))],
2745                  NoItinerary>;
2746
2747 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2748                            SDPatternOperator opnode, bit Commutable = 0> {
2749   let isCommutable = Commutable in {
2750     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2751                                opnode, VPR64, v8i16, v8i8, v8i8>;
2752     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2753                                opnode, VPR64, v4i32, v4i16, v4i16>;
2754     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2755                                opnode, VPR64, v2i64, v2i32, v2i32>;
2756   }
2757 }
2758
2759 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2760 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2761
2762 multiclass NeonI_Op_High<SDPatternOperator op> {
2763   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2764                      (op (v8i8 (Neon_High16B node:$Rn)),
2765                          (v8i8 (Neon_High16B node:$Rm)))>;
2766   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2767                      (op (v4i16 (Neon_High8H node:$Rn)),
2768                          (v4i16 (Neon_High8H node:$Rm)))>;
2769   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2770                      (op (v2i32 (Neon_High4S node:$Rn)),
2771                          (v2i32 (Neon_High4S node:$Rm)))>;
2772 }
2773
2774 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2775 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2776 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2777 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2778 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2779 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2780
2781 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2782                             bit Commutable = 0> {
2783   let isCommutable = Commutable in {
2784     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2785                                 !cast<PatFrag>(opnode # "_16B"),
2786                                 VPR128, v8i16, v16i8, v8i8>;
2787     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2788                                 !cast<PatFrag>(opnode # "_8H"),
2789                                 VPR128, v4i32, v8i16, v4i16>;
2790     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2791                                 !cast<PatFrag>(opnode # "_4S"),
2792                                 VPR128, v2i64, v4i32, v2i32>;
2793   }
2794 }
2795
2796 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2797 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2798
2799 // For pattern that need two operators being chained.
2800 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2801                      string asmop, string ResS, string OpS,
2802                      SDPatternOperator opnode, SDPatternOperator subop,
2803                      RegisterOperand OpVPR,
2804                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2805   : NeonI_3VDiff<q, u, size, opcode,
2806                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2807                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2808                  [(set (ResTy VPR128:$Rd),
2809                     (ResTy (opnode
2810                       (ResTy VPR128:$src),
2811                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2812                                                  (OpTy OpVPR:$Rm))))))))],
2813                  NoItinerary> {
2814   let Constraints = "$src = $Rd";
2815 }
2816
2817 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2818                              SDPatternOperator opnode, SDPatternOperator subop>{
2819   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2820                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2821   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2822                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2823   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2824                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2825 }
2826
2827 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2828                                    add, int_arm_neon_vabds>;
2829 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2830                                    add, int_arm_neon_vabdu>;
2831
2832 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2833                               SDPatternOperator opnode, string subop> {
2834   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2835                              opnode, !cast<PatFrag>(subop # "_16B"),
2836                              VPR128, v8i16, v16i8, v8i8>;
2837   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2838                              opnode, !cast<PatFrag>(subop # "_8H"),
2839                              VPR128, v4i32, v8i16, v4i16>;
2840   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2841                              opnode, !cast<PatFrag>(subop # "_4S"),
2842                              VPR128, v2i64, v4i32, v2i32>;
2843 }
2844
2845 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2846                                      "NI_sabdl_hi">;
2847 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2848                                      "NI_uabdl_hi">;
2849
2850 // Long pattern with 2 operands
2851 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2852                           SDPatternOperator opnode, bit Commutable = 0> {
2853   let isCommutable = Commutable in {
2854     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2855                               opnode, VPR128, VPR64, v8i16, v8i8>;
2856     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2857                               opnode, VPR128, VPR64, v4i32, v4i16>;
2858     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2859                               opnode, VPR128, VPR64, v2i64, v2i32>;
2860   }
2861 }
2862
2863 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2864 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2865
2866 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2867                            string asmop, string ResS, string OpS,
2868                            SDPatternOperator opnode,
2869                            ValueType ResTy, ValueType OpTy>
2870   : NeonI_3VDiff<q, u, size, opcode,
2871                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2872                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2873                  [(set (ResTy VPR128:$Rd),
2874                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2875                  NoItinerary>;
2876
2877 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2878                                    string opnode, bit Commutable = 0> {
2879   let isCommutable = Commutable in {
2880     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2881                                       !cast<PatFrag>(opnode # "_16B"),
2882                                       v8i16, v16i8>;
2883     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2884                                      !cast<PatFrag>(opnode # "_8H"),
2885                                      v4i32, v8i16>;
2886     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2887                                      !cast<PatFrag>(opnode # "_4S"),
2888                                      v2i64, v4i32>;
2889   }
2890 }
2891
2892 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2893                                          "NI_smull_hi", 1>;
2894 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2895                                          "NI_umull_hi", 1>;
2896
2897 // Long pattern with 3 operands
2898 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2899                      string asmop, string ResS, string OpS,
2900                      SDPatternOperator opnode,
2901                      ValueType ResTy, ValueType OpTy>
2902   : NeonI_3VDiff<q, u, size, opcode,
2903                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2904                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2905                  [(set (ResTy VPR128:$Rd),
2906                     (ResTy (opnode
2907                       (ResTy VPR128:$src),
2908                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2909                NoItinerary> {
2910   let Constraints = "$src = $Rd";
2911 }
2912
2913 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2914                              SDPatternOperator opnode> {
2915   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2916                              opnode, v8i16, v8i8>;
2917   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2918                              opnode, v4i32, v4i16>;
2919   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2920                              opnode, v2i64, v2i32>;
2921 }
2922
2923 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2924                          (add node:$Rd,
2925                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2926
2927 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2928                          (add node:$Rd,
2929                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2930
2931 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2932                          (sub node:$Rd,
2933                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2934
2935 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2936                          (sub node:$Rd,
2937                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2938
2939 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2940 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2941
2942 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2943 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2944
2945 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2946                            string asmop, string ResS, string OpS,
2947                            SDPatternOperator subop, SDPatternOperator opnode,
2948                            RegisterOperand OpVPR,
2949                            ValueType ResTy, ValueType OpTy>
2950   : NeonI_3VDiff<q, u, size, opcode,
2951                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2952                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2953                [(set (ResTy VPR128:$Rd),
2954                   (ResTy (subop
2955                     (ResTy VPR128:$src),
2956                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2957                NoItinerary> {
2958   let Constraints = "$src = $Rd";
2959 }
2960
2961 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2962                                    SDPatternOperator subop, string opnode> {
2963   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2964                                     subop, !cast<PatFrag>(opnode # "_16B"),
2965                                     VPR128, v8i16, v16i8>;
2966   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2967                                    subop, !cast<PatFrag>(opnode # "_8H"),
2968                                    VPR128, v4i32, v8i16>;
2969   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2970                                    subop, !cast<PatFrag>(opnode # "_4S"),
2971                                    VPR128, v2i64, v4i32>;
2972 }
2973
2974 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2975                                           add, "NI_smull_hi">;
2976 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2977                                           add, "NI_umull_hi">;
2978
2979 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2980                                           sub, "NI_smull_hi">;
2981 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2982                                           sub, "NI_umull_hi">;
2983
2984 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2985                                     SDPatternOperator opnode> {
2986   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2987                                    opnode, int_arm_neon_vqdmull,
2988                                    VPR64, v4i32, v4i16>;
2989   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2990                                    opnode, int_arm_neon_vqdmull,
2991                                    VPR64, v2i64, v2i32>;
2992 }
2993
2994 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2995                                            int_arm_neon_vqadds>;
2996 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2997                                            int_arm_neon_vqsubs>;
2998
2999 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3000                          SDPatternOperator opnode, bit Commutable = 0> {
3001   let isCommutable = Commutable in {
3002     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3003                               opnode, VPR128, VPR64, v4i32, v4i16>;
3004     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3005                               opnode, VPR128, VPR64, v2i64, v2i32>;
3006   }
3007 }
3008
3009 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3010                                 int_arm_neon_vqdmull, 1>;
3011
3012 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3013                                    string opnode, bit Commutable = 0> {
3014   let isCommutable = Commutable in {
3015     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3016                                      !cast<PatFrag>(opnode # "_8H"),
3017                                      v4i32, v8i16>;
3018     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3019                                      !cast<PatFrag>(opnode # "_4S"),
3020                                      v2i64, v4i32>;
3021   }
3022 }
3023
3024 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3025                                            "NI_qdmull_hi", 1>;
3026
3027 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3028                                      SDPatternOperator opnode> {
3029   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3030                                    opnode, NI_qdmull_hi_8H,
3031                                    VPR128, v4i32, v8i16>;
3032   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3033                                    opnode, NI_qdmull_hi_4S,
3034                                    VPR128, v2i64, v4i32>;
3035 }
3036
3037 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3038                                              int_arm_neon_vqadds>;
3039 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3040                                              int_arm_neon_vqsubs>;
3041
3042 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3043                          SDPatternOperator opnode_8h8b,
3044                          SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3045   let isCommutable = Commutable in {
3046     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3047                               opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3048
3049     def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3050                               opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3051   }
3052 }
3053
3054 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3055                               int_aarch64_neon_vmull_p64, 1>;
3056
3057 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3058                                    string opnode, bit Commutable = 0> {
3059   let isCommutable = Commutable in {
3060     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3061                                       !cast<PatFrag>(opnode # "_16B"),
3062                                       v8i16, v16i8>;
3063
3064     def _1q2d :
3065       NeonI_3VDiff<0b1, u, 0b11, opcode,
3066                    (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3067                    asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3068                    [(set (v16i8 VPR128:$Rd),
3069                       (v16i8 (int_aarch64_neon_vmull_p64
3070                         (v1i64 (scalar_to_vector
3071                           (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3072                         (v1i64 (scalar_to_vector
3073                           (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3074                    NoItinerary>;
3075   }
3076 }
3077
3078 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3079                                          1>;
3080
3081 // End of implementation for instruction class (3V Diff)
3082
3083 // The followings are vector load/store multiple N-element structure
3084 // (class SIMD lselem).
3085
3086 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3087 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3088 //              The structure consists of a sequence of sets of N values.
3089 //              The first element of the structure is placed in the first lane
3090 //              of the first first vector, the second element in the first lane
3091 //              of the second vector, and so on.
3092 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3093 // the three 64-bit vectors list {BA, DC, FE}.
3094 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3095 // 64-bit vectors list {DA, EB, FC}.
3096 // Store instructions store multiple structure to N registers like load.
3097
3098
3099 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3100                     RegisterOperand VecList, string asmop>
3101   : NeonI_LdStMult<q, 1, opcode, size,
3102                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3103                  asmop # "\t$Rt, [$Rn]",
3104                  [],
3105                  NoItinerary> {
3106   let mayLoad = 1;
3107   let neverHasSideEffects = 1;
3108 }
3109
3110 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3111   def _8B : NeonI_LDVList<0, opcode, 0b00,
3112                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3113
3114   def _4H : NeonI_LDVList<0, opcode, 0b01,
3115                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3116
3117   def _2S : NeonI_LDVList<0, opcode, 0b10,
3118                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3119
3120   def _16B : NeonI_LDVList<1, opcode, 0b00,
3121                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3122
3123   def _8H : NeonI_LDVList<1, opcode, 0b01,
3124                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3125
3126   def _4S : NeonI_LDVList<1, opcode, 0b10,
3127                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3128
3129   def _2D : NeonI_LDVList<1, opcode, 0b11,
3130                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3131 }
3132
3133 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3134 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3135 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3136
3137 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3138
3139 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3140
3141 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3142
3143 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3144 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3145 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3146
3147 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3148 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3149
3150 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3151 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3152
3153 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3154                     RegisterOperand VecList, string asmop>
3155   : NeonI_LdStMult<q, 0, opcode, size,
3156                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3157                  asmop # "\t$Rt, [$Rn]",
3158                  [],
3159                  NoItinerary> {
3160   let mayStore = 1;
3161   let neverHasSideEffects = 1;
3162 }
3163
3164 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3165   def _8B : NeonI_STVList<0, opcode, 0b00,
3166                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3167
3168   def _4H : NeonI_STVList<0, opcode, 0b01,
3169                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3170
3171   def _2S : NeonI_STVList<0, opcode, 0b10,
3172                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3173
3174   def _16B : NeonI_STVList<1, opcode, 0b00,
3175                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3176
3177   def _8H : NeonI_STVList<1, opcode, 0b01,
3178                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3179
3180   def _4S : NeonI_STVList<1, opcode, 0b10,
3181                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3182
3183   def _2D : NeonI_STVList<1, opcode, 0b11,
3184                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3185 }
3186
3187 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3188 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3189 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3190
3191 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3192
3193 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3194
3195 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3196
3197 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3198 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3199 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3200
3201 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3202 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3203
3204 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3205 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3206
3207 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3208 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3209
3210 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3211 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3212
3213 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3214 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3215
3216 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3217 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3218
3219 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3220 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3221
3222 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3223 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3224
3225 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3226           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3227 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3228           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3229
3230 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3231           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3232 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3233           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3234
3235 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3236           (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3237 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3238           (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3239
3240 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3241           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3242 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3243           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3244
3245 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3246           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3247 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3248           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3249
3250 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3251           (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3252 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3253           (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3254
3255 // End of vector load/store multiple N-element structure(class SIMD lselem)
3256
3257 // The followings are post-index vector load/store multiple N-element
3258 // structure(class SIMD lselem-post)
3259 def exact1_asmoperand : AsmOperandClass {
3260   let Name = "Exact1";
3261   let PredicateMethod = "isExactImm<1>";
3262   let RenderMethod = "addImmOperands";
3263 }
3264 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3265   let ParserMatchClass = exact1_asmoperand;
3266 }
3267
3268 def exact2_asmoperand : AsmOperandClass {
3269   let Name = "Exact2";
3270   let PredicateMethod = "isExactImm<2>";
3271   let RenderMethod = "addImmOperands";
3272 }
3273 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3274   let ParserMatchClass = exact2_asmoperand;
3275 }
3276
3277 def exact3_asmoperand : AsmOperandClass {
3278   let Name = "Exact3";
3279   let PredicateMethod = "isExactImm<3>";
3280   let RenderMethod = "addImmOperands";
3281 }
3282 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3283   let ParserMatchClass = exact3_asmoperand;
3284 }
3285
3286 def exact4_asmoperand : AsmOperandClass {
3287   let Name = "Exact4";
3288   let PredicateMethod = "isExactImm<4>";
3289   let RenderMethod = "addImmOperands";
3290 }
3291 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3292   let ParserMatchClass = exact4_asmoperand;
3293 }
3294
3295 def exact6_asmoperand : AsmOperandClass {
3296   let Name = "Exact6";
3297   let PredicateMethod = "isExactImm<6>";
3298   let RenderMethod = "addImmOperands";
3299 }
3300 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3301   let ParserMatchClass = exact6_asmoperand;
3302 }
3303
3304 def exact8_asmoperand : AsmOperandClass {
3305   let Name = "Exact8";
3306   let PredicateMethod = "isExactImm<8>";
3307   let RenderMethod = "addImmOperands";
3308 }
3309 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3310   let ParserMatchClass = exact8_asmoperand;
3311 }
3312
3313 def exact12_asmoperand : AsmOperandClass {
3314   let Name = "Exact12";
3315   let PredicateMethod = "isExactImm<12>";
3316   let RenderMethod = "addImmOperands";
3317 }
3318 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3319   let ParserMatchClass = exact12_asmoperand;
3320 }
3321
3322 def exact16_asmoperand : AsmOperandClass {
3323   let Name = "Exact16";
3324   let PredicateMethod = "isExactImm<16>";
3325   let RenderMethod = "addImmOperands";
3326 }
3327 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3328   let ParserMatchClass = exact16_asmoperand;
3329 }
3330
3331 def exact24_asmoperand : AsmOperandClass {
3332   let Name = "Exact24";
3333   let PredicateMethod = "isExactImm<24>";
3334   let RenderMethod = "addImmOperands";
3335 }
3336 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3337   let ParserMatchClass = exact24_asmoperand;
3338 }
3339
3340 def exact32_asmoperand : AsmOperandClass {
3341   let Name = "Exact32";
3342   let PredicateMethod = "isExactImm<32>";
3343   let RenderMethod = "addImmOperands";
3344 }
3345 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3346   let ParserMatchClass = exact32_asmoperand;
3347 }
3348
3349 def exact48_asmoperand : AsmOperandClass {
3350   let Name = "Exact48";
3351   let PredicateMethod = "isExactImm<48>";
3352   let RenderMethod = "addImmOperands";
3353 }
3354 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3355   let ParserMatchClass = exact48_asmoperand;
3356 }
3357
3358 def exact64_asmoperand : AsmOperandClass {
3359   let Name = "Exact64";
3360   let PredicateMethod = "isExactImm<64>";
3361   let RenderMethod = "addImmOperands";
3362 }
3363 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3364   let ParserMatchClass = exact64_asmoperand;
3365 }
3366
3367 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3368                            RegisterOperand VecList, Operand ImmTy,
3369                            string asmop> {
3370   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3371       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3372     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3373                      (outs VecList:$Rt, GPR64xsp:$wb),
3374                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3375                      asmop # "\t$Rt, [$Rn], $amt",
3376                      [],
3377                      NoItinerary> {
3378       let Rm = 0b11111;
3379     }
3380
3381     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3382                         (outs VecList:$Rt, GPR64xsp:$wb),
3383                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3384                         asmop # "\t$Rt, [$Rn], $Rm",
3385                         [],
3386                         NoItinerary>;
3387   }
3388 }
3389
3390 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3391     Operand ImmTy2, string asmop> {
3392   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3393                               !cast<RegisterOperand>(List # "8B_operand"),
3394                               ImmTy, asmop>;
3395
3396   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3397                               !cast<RegisterOperand>(List # "4H_operand"),
3398                               ImmTy, asmop>;
3399
3400   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3401                               !cast<RegisterOperand>(List # "2S_operand"),
3402                               ImmTy, asmop>;
3403
3404   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3405                                !cast<RegisterOperand>(List # "16B_operand"),
3406                                ImmTy2, asmop>;
3407
3408   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3409                               !cast<RegisterOperand>(List # "8H_operand"),
3410                               ImmTy2, asmop>;
3411
3412   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3413                               !cast<RegisterOperand>(List # "4S_operand"),
3414                               ImmTy2, asmop>;
3415
3416   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3417                               !cast<RegisterOperand>(List # "2D_operand"),
3418                               ImmTy2, asmop>;
3419 }
3420
3421 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3422 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3423 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3424                                  "ld1">;
3425
3426 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3427
3428 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3429                              "ld3">;
3430
3431 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3432
3433 // Post-index load multiple 1-element structures from N consecutive registers
3434 // (N = 2,3,4)
3435 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3436                                "ld1">;
3437 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3438                                    uimm_exact16, "ld1">;
3439
3440 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3441                                "ld1">;
3442 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3443                                    uimm_exact24, "ld1">;
3444
3445 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3446                                 "ld1">;
3447 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3448                                    uimm_exact32, "ld1">;
3449
3450 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3451                             RegisterOperand VecList, Operand ImmTy,
3452                             string asmop> {
3453   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3454       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3455     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3456                      (outs GPR64xsp:$wb),
3457                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3458                      asmop # "\t$Rt, [$Rn], $amt",
3459                      [],
3460                      NoItinerary> {
3461       let Rm = 0b11111;
3462     }
3463
3464     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3465                       (outs GPR64xsp:$wb),
3466                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3467                       asmop # "\t$Rt, [$Rn], $Rm",
3468                       [],
3469                       NoItinerary>;
3470   }
3471 }
3472
3473 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3474                            Operand ImmTy2, string asmop> {
3475   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3476                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3477
3478   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3479                               !cast<RegisterOperand>(List # "4H_operand"),
3480                               ImmTy, asmop>;
3481
3482   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3483                               !cast<RegisterOperand>(List # "2S_operand"),
3484                               ImmTy, asmop>;
3485
3486   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3487                                !cast<RegisterOperand>(List # "16B_operand"),
3488                                ImmTy2, asmop>;
3489
3490   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3491                               !cast<RegisterOperand>(List # "8H_operand"),
3492                               ImmTy2, asmop>;
3493
3494   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3495                               !cast<RegisterOperand>(List # "4S_operand"),
3496                               ImmTy2, asmop>;
3497
3498   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3499                               !cast<RegisterOperand>(List # "2D_operand"),
3500                               ImmTy2, asmop>;
3501 }
3502
3503 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3504 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3505 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3506                                  "st1">;
3507
3508 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3509
3510 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3511                              "st3">;
3512
3513 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3514
3515 // Post-index load multiple 1-element structures from N consecutive registers
3516 // (N = 2,3,4)
3517 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3518                                "st1">;
3519 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3520                                    uimm_exact16, "st1">;
3521
3522 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3523                                "st1">;
3524 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3525                                    uimm_exact24, "st1">;
3526
3527 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3528                                "st1">;
3529 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3530                                    uimm_exact32, "st1">;
3531
3532 // End of post-index vector load/store multiple N-element structure
3533 // (class SIMD lselem-post)
3534
3535 // The followings are vector load/store single N-element structure
3536 // (class SIMD lsone).
3537 def neon_uimm0_bare : Operand<i64>,
3538                         ImmLeaf<i64, [{return Imm == 0;}]> {
3539   let ParserMatchClass = neon_uimm0_asmoperand;
3540   let PrintMethod = "printUImmBareOperand";
3541 }
3542
3543 def neon_uimm1_bare : Operand<i64>,
3544                         ImmLeaf<i64, [{return Imm < 2;}]> {
3545   let ParserMatchClass = neon_uimm1_asmoperand;
3546   let PrintMethod = "printUImmBareOperand";
3547 }
3548
3549 def neon_uimm2_bare : Operand<i64>,
3550                         ImmLeaf<i64, [{return Imm < 4;}]> {
3551   let ParserMatchClass = neon_uimm2_asmoperand;
3552   let PrintMethod = "printUImmBareOperand";
3553 }
3554
3555 def neon_uimm3_bare : Operand<i64>,
3556                         ImmLeaf<i64, [{return Imm < 8;}]> {
3557   let ParserMatchClass = uimm3_asmoperand;
3558   let PrintMethod = "printUImmBareOperand";
3559 }
3560
3561 def neon_uimm4_bare : Operand<i64>,
3562                         ImmLeaf<i64, [{return Imm < 16;}]> {
3563   let ParserMatchClass = uimm4_asmoperand;
3564   let PrintMethod = "printUImmBareOperand";
3565 }
3566
3567 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3568                     RegisterOperand VecList, string asmop>
3569     : NeonI_LdOne_Dup<q, r, opcode, size,
3570                       (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3571                       asmop # "\t$Rt, [$Rn]",
3572                       [],
3573                       NoItinerary> {
3574   let mayLoad = 1;
3575   let neverHasSideEffects = 1;
3576 }
3577
3578 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3579   def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3580                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3581
3582   def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3583                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3584
3585   def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3586                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3587
3588   def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3589                           !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3590
3591   def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3592                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3593
3594   def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3595                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3596
3597   def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3598                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3599
3600   def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3601                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3602 }
3603
3604 // Load single 1-element structure to all lanes of 1 register
3605 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3606
3607 // Load single N-element structure to all lanes of N consecutive
3608 // registers (N = 2,3,4)
3609 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3610 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3611 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3612
3613
3614 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3615                     Instruction INST>
3616     : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3617           (VTy (INST GPR64xsp:$Rn))>;
3618
3619 // Match all LD1R instructions
3620 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3621
3622 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3623
3624 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3625
3626 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3627
3628 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3629 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3630
3631 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3632 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3633
3634 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3635 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3636
3637 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3638 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3639
3640
3641 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3642                                 RegisterClass RegList> {
3643   defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3644   defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3645   defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3646   defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3647 }
3648
3649 // Special vector list operand of 128-bit vectors with bare layout.
3650 // i.e. only show ".b", ".h", ".s", ".d"
3651 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3652 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3653 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3654 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3655
3656 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3657                      Operand ImmOp, string asmop>
3658     : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3659                          (outs VList:$Rt),
3660                          (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3661                          asmop # "\t$Rt[$lane], [$Rn]",
3662                          [],
3663                          NoItinerary> {
3664   let mayLoad = 1;
3665   let neverHasSideEffects = 1;
3666   let hasExtraDefRegAllocReq = 1;
3667   let Constraints = "$src = $Rt";
3668 }
3669
3670 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3671   def _B : NeonI_LDN_Lane<r, 0b00, op0,
3672                           !cast<RegisterOperand>(List # "B_operand"),
3673                           neon_uimm4_bare, asmop> {
3674     let Inst{12-10} = lane{2-0};
3675     let Inst{30} = lane{3};
3676   }
3677
3678   def _H : NeonI_LDN_Lane<r, 0b01, op0,
3679                           !cast<RegisterOperand>(List # "H_operand"),
3680                           neon_uimm3_bare, asmop> {
3681     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3682     let Inst{30} = lane{2};
3683   }
3684
3685   def _S : NeonI_LDN_Lane<r, 0b10, op0,
3686                           !cast<RegisterOperand>(List # "S_operand"),
3687                           neon_uimm2_bare, asmop> {
3688     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3689     let Inst{30} = lane{1};
3690   }
3691
3692   def _D : NeonI_LDN_Lane<r, 0b10, op0,
3693                           !cast<RegisterOperand>(List # "D_operand"),
3694                           neon_uimm1_bare, asmop> {
3695     let Inst{12-10} = 0b001;
3696     let Inst{30} = lane{0};
3697   }
3698 }
3699
3700 // Load single 1-element structure to one lane of 1 register.
3701 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3702
3703 // Load single N-element structure to one lane of N consecutive registers
3704 // (N = 2,3,4)
3705 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3706 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3707 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3708
3709 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3710                           Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3711                           Instruction INST> {
3712   def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3713                      (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3714             (VTy (EXTRACT_SUBREG
3715                      (INST GPR64xsp:$Rn,
3716                            (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3717                            ImmOp:$lane),
3718                      sub_64))>;
3719
3720   def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3721                       (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3722             (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3723 }
3724
3725 // Match all LD1LN instructions
3726 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3727                       extloadi8, LD1LN_B>;
3728
3729 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3730                       extloadi16, LD1LN_H>;
3731
3732 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3733                       load, LD1LN_S>;
3734 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3735                       load, LD1LN_S>;
3736
3737 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3738                       load, LD1LN_D>;
3739 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3740                       load, LD1LN_D>;
3741
3742 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3743                      Operand ImmOp, string asmop>
3744     : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3745                          (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3746                          asmop # "\t$Rt[$lane], [$Rn]",
3747                          [],
3748                          NoItinerary> {
3749   let mayStore = 1;
3750   let neverHasSideEffects = 1;
3751   let hasExtraDefRegAllocReq = 1;
3752 }
3753
3754 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3755   def _B : NeonI_STN_Lane<r, 0b00, op0,
3756                           !cast<RegisterOperand>(List # "B_operand"),
3757                           neon_uimm4_bare, asmop> {
3758     let Inst{12-10} = lane{2-0};
3759     let Inst{30} = lane{3};
3760   }
3761
3762   def _H : NeonI_STN_Lane<r, 0b01, op0,
3763                           !cast<RegisterOperand>(List # "H_operand"),
3764                           neon_uimm3_bare, asmop> {
3765     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3766     let Inst{30} = lane{2};
3767   }
3768
3769   def _S : NeonI_STN_Lane<r, 0b10, op0,
3770                           !cast<RegisterOperand>(List # "S_operand"),
3771                            neon_uimm2_bare, asmop> {
3772     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3773     let Inst{30} = lane{1};
3774   }
3775
3776   def _D : NeonI_STN_Lane<r, 0b10, op0,
3777                           !cast<RegisterOperand>(List # "D_operand"),
3778                           neon_uimm1_bare, asmop>{
3779     let Inst{12-10} = 0b001;
3780     let Inst{30} = lane{0};
3781   }
3782 }
3783
3784 // Store single 1-element structure from one lane of 1 register.
3785 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3786
3787 // Store single N-element structure from one lane of N consecutive registers
3788 // (N = 2,3,4)
3789 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3790 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3791 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3792
3793 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3794                           Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3795                           Instruction INST> {
3796   def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3797                      GPR64xsp:$Rn),
3798             (INST GPR64xsp:$Rn,
3799                   (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3800                   ImmOp:$lane)>;
3801
3802   def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3803                      GPR64xsp:$Rn),
3804             (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3805 }
3806
3807 // Match all ST1LN instructions
3808 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3809                       truncstorei8, ST1LN_B>;
3810
3811 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3812                       truncstorei16, ST1LN_H>;
3813
3814 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3815                       store, ST1LN_S>;
3816 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3817                       store, ST1LN_S>;
3818
3819 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3820                       store, ST1LN_D>;
3821 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3822                       store, ST1LN_D>;
3823
3824 // End of vector load/store single N-element structure (class SIMD lsone).
3825
3826
3827 // The following are post-index load/store single N-element instructions
3828 // (class SIMD lsone-post)
3829
3830 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3831                             RegisterOperand VecList, Operand ImmTy,
3832                             string asmop> {
3833   let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3834   DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3835     def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3836                       (outs VecList:$Rt, GPR64xsp:$wb),
3837                       (ins GPR64xsp:$Rn, ImmTy:$amt),
3838                       asmop # "\t$Rt, [$Rn], $amt",
3839                       [],
3840                       NoItinerary> {
3841                         let Rm = 0b11111;
3842                       }
3843
3844     def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3845                       (outs VecList:$Rt, GPR64xsp:$wb),
3846                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3847                       asmop # "\t$Rt, [$Rn], $Rm",
3848                       [],
3849                       NoItinerary>;
3850   }
3851 }
3852
3853 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3854                          Operand uimm_b, Operand uimm_h,
3855                          Operand uimm_s, Operand uimm_d> {
3856   defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3857                               !cast<RegisterOperand>(List # "8B_operand"),
3858                               uimm_b, asmop>;
3859
3860   defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3861                               !cast<RegisterOperand>(List # "4H_operand"),
3862                               uimm_h, asmop>;
3863
3864   defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3865                               !cast<RegisterOperand>(List # "2S_operand"),
3866                               uimm_s, asmop>;
3867
3868   defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3869                               !cast<RegisterOperand>(List # "1D_operand"),
3870                               uimm_d, asmop>;
3871
3872   defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3873                                !cast<RegisterOperand>(List # "16B_operand"),
3874                                uimm_b, asmop>;
3875
3876   defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3877                               !cast<RegisterOperand>(List # "8H_operand"),
3878                               uimm_h, asmop>;
3879
3880   defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3881                               !cast<RegisterOperand>(List # "4S_operand"),
3882                               uimm_s, asmop>;
3883
3884   defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3885                               !cast<RegisterOperand>(List # "2D_operand"),
3886                               uimm_d, asmop>;
3887 }
3888
3889 // Post-index load single 1-element structure to all lanes of 1 register
3890 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3891                              uimm_exact2, uimm_exact4, uimm_exact8>;
3892
3893 // Post-index load single N-element structure to all lanes of N consecutive
3894 // registers (N = 2,3,4)
3895 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3896                              uimm_exact4, uimm_exact8, uimm_exact16>;
3897 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3898                              uimm_exact6, uimm_exact12, uimm_exact24>;
3899 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3900                              uimm_exact8, uimm_exact16, uimm_exact32>;
3901
3902 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3903     Constraints = "$Rn = $wb, $Rt = $src",
3904     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3905   class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3906                                 Operand ImmTy, Operand ImmOp, string asmop>
3907       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3908                                 (outs VList:$Rt, GPR64xsp:$wb),
3909                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
3910                                     VList:$src, ImmOp:$lane),
3911                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
3912                                 [],
3913                                 NoItinerary> {
3914     let Rm = 0b11111;
3915   }
3916
3917   class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3918                                  Operand ImmTy, Operand ImmOp, string asmop>
3919       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3920                                 (outs VList:$Rt, GPR64xsp:$wb),
3921                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3922                                     VList:$src, ImmOp:$lane),
3923                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3924                                 [],
3925                                 NoItinerary>;
3926 }
3927
3928 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3929                            Operand uimm_b, Operand uimm_h,
3930                            Operand uimm_s, Operand uimm_d> {
3931   def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3932                                !cast<RegisterOperand>(List # "B_operand"),
3933                                uimm_b, neon_uimm4_bare, asmop> {
3934     let Inst{12-10} = lane{2-0};
3935     let Inst{30} = lane{3};
3936   }
3937
3938   def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3939                                    !cast<RegisterOperand>(List # "B_operand"),
3940                                    uimm_b, neon_uimm4_bare, asmop> {
3941     let Inst{12-10} = lane{2-0};
3942     let Inst{30} = lane{3};
3943   }
3944
3945   def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3946                                !cast<RegisterOperand>(List # "H_operand"),
3947                                uimm_h, neon_uimm3_bare, asmop> {
3948     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3949     let Inst{30} = lane{2};
3950   }
3951
3952   def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3953                                    !cast<RegisterOperand>(List # "H_operand"),
3954                                    uimm_h, neon_uimm3_bare, asmop> {
3955     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3956     let Inst{30} = lane{2};
3957   }
3958
3959   def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3960                                !cast<RegisterOperand>(List # "S_operand"),
3961                                uimm_s, neon_uimm2_bare, asmop> {
3962     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3963     let Inst{30} = lane{1};
3964   }
3965
3966   def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3967                                    !cast<RegisterOperand>(List # "S_operand"),
3968                                    uimm_s, neon_uimm2_bare, asmop> {
3969     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3970     let Inst{30} = lane{1};
3971   }
3972
3973   def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3974                                !cast<RegisterOperand>(List # "D_operand"),
3975                                uimm_d, neon_uimm1_bare, asmop> {
3976     let Inst{12-10} = 0b001;
3977     let Inst{30} = lane{0};
3978   }
3979
3980   def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3981                                    !cast<RegisterOperand>(List # "D_operand"),
3982                                    uimm_d, neon_uimm1_bare, asmop> {
3983     let Inst{12-10} = 0b001;
3984     let Inst{30} = lane{0};
3985   }
3986 }
3987
3988 // Post-index load single 1-element structure to one lane of 1 register.
3989 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
3990                                 uimm_exact2, uimm_exact4, uimm_exact8>;
3991
3992 // Post-index load single N-element structure to one lane of N consecutive
3993 // registers
3994 // (N = 2,3,4)
3995 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
3996                                 uimm_exact4, uimm_exact8, uimm_exact16>;
3997 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
3998                                 uimm_exact6, uimm_exact12, uimm_exact24>;
3999 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4000                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4001
4002 let mayStore = 1, neverHasSideEffects = 1,
4003     hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4004     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4005   class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4006                       Operand ImmTy, Operand ImmOp, string asmop>
4007       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4008                                 (outs GPR64xsp:$wb),
4009                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4010                                     VList:$Rt, ImmOp:$lane),
4011                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4012                                 [],
4013                                 NoItinerary> {
4014     let Rm = 0b11111;
4015   }
4016
4017   class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4018                        Operand ImmTy, Operand ImmOp, string asmop>
4019       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4020                                 (outs GPR64xsp:$wb),
4021                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4022                                     ImmOp:$lane),
4023                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4024                                 [],
4025                                 NoItinerary>;
4026 }
4027
4028 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4029                            Operand uimm_b, Operand uimm_h,
4030                            Operand uimm_s, Operand uimm_d> {
4031   def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4032                                !cast<RegisterOperand>(List # "B_operand"),
4033                                uimm_b, neon_uimm4_bare, asmop> {
4034     let Inst{12-10} = lane{2-0};
4035     let Inst{30} = lane{3};
4036   }
4037
4038   def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4039                                    !cast<RegisterOperand>(List # "B_operand"),
4040                                    uimm_b, neon_uimm4_bare, asmop> {
4041     let Inst{12-10} = lane{2-0};
4042     let Inst{30} = lane{3};
4043   }
4044
4045   def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4046                                !cast<RegisterOperand>(List # "H_operand"),
4047                                uimm_h, neon_uimm3_bare, asmop> {
4048     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4049     let Inst{30} = lane{2};
4050   }
4051
4052   def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4053                                    !cast<RegisterOperand>(List # "H_operand"),
4054                                    uimm_h, neon_uimm3_bare, asmop> {
4055     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4056     let Inst{30} = lane{2};
4057   }
4058
4059   def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4060                                !cast<RegisterOperand>(List # "S_operand"),
4061                                uimm_s, neon_uimm2_bare, asmop> {
4062     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4063     let Inst{30} = lane{1};
4064   }
4065
4066   def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4067                                    !cast<RegisterOperand>(List # "S_operand"),
4068                                    uimm_s, neon_uimm2_bare, asmop> {
4069     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4070     let Inst{30} = lane{1};
4071   }
4072
4073   def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4074                                !cast<RegisterOperand>(List # "D_operand"),
4075                                uimm_d, neon_uimm1_bare, asmop> {
4076     let Inst{12-10} = 0b001;
4077     let Inst{30} = lane{0};
4078   }
4079
4080   def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4081                                    !cast<RegisterOperand>(List # "D_operand"),
4082                                    uimm_d, neon_uimm1_bare, asmop> {
4083     let Inst{12-10} = 0b001;
4084     let Inst{30} = lane{0};
4085   }
4086 }
4087
4088 // Post-index store single 1-element structure from one lane of 1 register.
4089 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4090                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4091
4092 // Post-index store single N-element structure from one lane of N consecutive
4093 // registers (N = 2,3,4)
4094 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4095                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4096 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4097                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4098 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4099                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4100
4101 // End of post-index load/store single N-element instructions
4102 // (class SIMD lsone-post)
4103
4104 // Neon Scalar instructions implementation
4105 // Scalar Three Same
4106
4107 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4108                              RegisterClass FPRC>
4109   : NeonI_Scalar3Same<u, size, opcode,
4110                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4111                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4112                       [],
4113                       NoItinerary>;
4114
4115 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4116   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4117
4118 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4119                                       bit Commutable = 0> {
4120   let isCommutable = Commutable in {
4121     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4122     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4123   }
4124 }
4125
4126 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4127                                       string asmop, bit Commutable = 0> {
4128   let isCommutable = Commutable in {
4129     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4130     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4131   }
4132 }
4133
4134 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4135                                         string asmop, bit Commutable = 0> {
4136   let isCommutable = Commutable in {
4137     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4138     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4139     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4140     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4141   }
4142 }
4143
4144 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4145                                             Instruction INSTD> {
4146   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4147             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4148 }
4149
4150 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4151                                                Instruction INSTB,
4152                                                Instruction INSTH,
4153                                                Instruction INSTS,
4154                                                Instruction INSTD>
4155   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4156   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4157            (INSTB FPR8:$Rn, FPR8:$Rm)>;
4158
4159   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4160            (INSTH FPR16:$Rn, FPR16:$Rm)>;
4161
4162   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4163            (INSTS FPR32:$Rn, FPR32:$Rm)>;
4164 }
4165
4166 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
4167                                            Instruction INSTD>
4168   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4169         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4170
4171 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4172                                              Instruction INSTH,
4173                                              Instruction INSTS> {
4174   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4175             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4176   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4177             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4178 }
4179
4180 multiclass Neon_Scalar3Same_fabd_SD_size_patterns<SDPatternOperator opnode,
4181                                                   Instruction INSTS,
4182                                                   Instruction INSTD> {
4183   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4184             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4185   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4186             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4187 }
4188
4189 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4190                                              SDPatternOperator opnodeV,
4191                                              Instruction INSTS,
4192                                              Instruction INSTD> {
4193   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4194             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4195   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4196             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4197   def : Pat<(v1f64 (opnodeV (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4198             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4199 }
4200
4201 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
4202                                                  Instruction INSTS,
4203                                                  Instruction INSTD> {
4204   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4205             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4206   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4207             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4208 }
4209
4210 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4211                                               Instruction INSTD>
4212   : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4213         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4214
4215 // Scalar Three Different
4216
4217 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4218                              RegisterClass FPRCD, RegisterClass FPRCS>
4219   : NeonI_Scalar3Diff<u, size, opcode,
4220                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4221                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4222                       [],
4223                       NoItinerary>;
4224
4225 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4226   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4227   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4228 }
4229
4230 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4231   let Constraints = "$Src = $Rd" in {
4232     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4233                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4234                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4235                        [],
4236                        NoItinerary>;
4237     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4238                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4239                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4240                        [],
4241                        NoItinerary>;
4242   }
4243 }
4244
4245 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4246                                              Instruction INSTH,
4247                                              Instruction INSTS> {
4248   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4249             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4250   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4251             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4252 }
4253
4254 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4255                                              Instruction INSTH,
4256                                              Instruction INSTS> {
4257   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4258             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4259   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4260             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4261 }
4262
4263 // Scalar Two Registers Miscellaneous
4264
4265 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4266                              RegisterClass FPRCD, RegisterClass FPRCS>
4267   : NeonI_Scalar2SameMisc<u, size, opcode,
4268                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4269                           !strconcat(asmop, "\t$Rd, $Rn"),
4270                           [],
4271                           NoItinerary>;
4272
4273 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4274                                          string asmop> {
4275   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4276                                       FPR32>;
4277   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4278                                       FPR64>;
4279 }
4280
4281 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4282   def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4283 }
4284
4285 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4286   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4287   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4288   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4289   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4290 }
4291
4292 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4293   : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4294
4295 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4296                                                  string asmop> {
4297   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4298   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4299   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4300 }
4301
4302 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4303                                        string asmop, RegisterClass FPRC>
4304   : NeonI_Scalar2SameMisc<u, size, opcode,
4305                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4306                           !strconcat(asmop, "\t$Rd, $Rn"),
4307                           [],
4308                           NoItinerary>;
4309
4310 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4311                                                  string asmop> {
4312
4313   let Constraints = "$Src = $Rd" in {
4314     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4315     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4316     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4317     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4318   }
4319 }
4320
4321 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4322                                                   Instruction INSTD>
4323   : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4324         (INSTD FPR64:$Rn)>;
4325
4326 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4327                                                       Instruction INSTS,
4328                                                       Instruction INSTD> {
4329   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4330             (INSTS FPR32:$Rn)>;
4331   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4332             (INSTD FPR64:$Rn)>;
4333 }
4334
4335 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4336                                                 Instruction INSTD>
4337   : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4338             (INSTD FPR64:$Rn)>;
4339
4340 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4341                                                      Instruction INSTS,
4342                                                      Instruction INSTD> {
4343   def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4344             (INSTS FPR32:$Rn)>;
4345   def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4346             (INSTD FPR64:$Rn)>;
4347 }
4348
4349 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4350                                                  Instruction INSTS,
4351                                                  Instruction INSTD> {
4352   def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4353             (INSTS FPR32:$Rn)>;
4354   def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4355             (INSTD FPR64:$Rn)>;
4356 }
4357
4358 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4359                                               Instruction INSTD>
4360   : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4361         (INSTD FPR64:$Rn)>;
4362
4363 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4364   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4365                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4366                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4367                           [],
4368                           NoItinerary>;
4369
4370 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4371                                               string asmop> {
4372   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4373                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4374                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4375                            [],
4376                            NoItinerary>;
4377   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4378                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4379                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4380                            [],
4381                            NoItinerary>;
4382 }
4383
4384 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4385                                                 Instruction INSTD>
4386   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4387                        (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4388         (INSTD FPR64:$Rn, 0)>;
4389
4390 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4391                                                    Instruction INSTD>
4392   : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4393                           (i32 neon_uimm0:$Imm), CC)),
4394         (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4395
4396 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4397                                                       Instruction INSTS,
4398                                                       Instruction INSTD> {
4399   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpz32:$FPImm))),
4400             (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4401   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpz32:$FPImm))),
4402             (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4403 }
4404
4405 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4406                                                 Instruction INSTD> {
4407   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4408             (INSTD FPR64:$Rn)>;
4409 }
4410
4411 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4412                                                    Instruction INSTB,
4413                                                    Instruction INSTH,
4414                                                    Instruction INSTS,
4415                                                    Instruction INSTD>
4416   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4417   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4418             (INSTB FPR8:$Rn)>;
4419   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4420             (INSTH FPR16:$Rn)>;
4421   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4422             (INSTS FPR32:$Rn)>;
4423 }
4424
4425 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4426                                                        SDPatternOperator opnode,
4427                                                        Instruction INSTH,
4428                                                        Instruction INSTS,
4429                                                        Instruction INSTD> {
4430   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4431             (INSTH FPR16:$Rn)>;
4432   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4433             (INSTS FPR32:$Rn)>;
4434   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4435             (INSTD FPR64:$Rn)>;
4436
4437 }
4438
4439 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4440                                                        SDPatternOperator opnode,
4441                                                        Instruction INSTB,
4442                                                        Instruction INSTH,
4443                                                        Instruction INSTS,
4444                                                        Instruction INSTD> {
4445   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4446             (INSTB FPR8:$Src, FPR8:$Rn)>;
4447   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4448             (INSTH FPR16:$Src, FPR16:$Rn)>;
4449   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4450             (INSTS FPR32:$Src, FPR32:$Rn)>;
4451   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4452             (INSTD FPR64:$Src, FPR64:$Rn)>;
4453 }
4454
4455 // Scalar Shift By Immediate
4456
4457 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4458                                 RegisterClass FPRC, Operand ImmTy>
4459   : NeonI_ScalarShiftImm<u, opcode,
4460                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4461                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4462                          [], NoItinerary>;
4463
4464 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4465                                             string asmop> {
4466   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4467     bits<6> Imm;
4468     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4469     let Inst{21-16} = Imm;
4470   }
4471 }
4472
4473 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4474                                                string asmop>
4475   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4476   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4477     bits<3> Imm;
4478     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4479     let Inst{18-16} = Imm;
4480   }
4481   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4482     bits<4> Imm;
4483     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4484     let Inst{19-16} = Imm;
4485   }
4486   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4487     bits<5> Imm;
4488     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4489     let Inst{20-16} = Imm;
4490   }
4491 }
4492
4493 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4494                                             string asmop> {
4495   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4496     bits<6> Imm;
4497     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4498     let Inst{21-16} = Imm;
4499   }
4500 }
4501
4502 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4503                                               string asmop>
4504   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4505   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4506     bits<3> Imm;
4507     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4508     let Inst{18-16} = Imm;
4509   }
4510   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4511     bits<4> Imm;
4512     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4513     let Inst{19-16} = Imm;
4514   }
4515   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4516     bits<5> Imm;
4517     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4518     let Inst{20-16} = Imm;
4519   }
4520 }
4521
4522 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4523   : NeonI_ScalarShiftImm<u, opcode,
4524                          (outs FPR64:$Rd),
4525                          (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4526                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4527                          [], NoItinerary> {
4528     bits<6> Imm;
4529     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4530     let Inst{21-16} = Imm;
4531     let Constraints = "$Src = $Rd";
4532 }
4533
4534 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4535   : NeonI_ScalarShiftImm<u, opcode,
4536                          (outs FPR64:$Rd),
4537                          (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4538                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4539                          [], NoItinerary> {
4540     bits<6> Imm;
4541     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4542     let Inst{21-16} = Imm;
4543     let Constraints = "$Src = $Rd";
4544 }
4545
4546 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4547                                        RegisterClass FPRCD, RegisterClass FPRCS,
4548                                        Operand ImmTy>
4549   : NeonI_ScalarShiftImm<u, opcode,
4550                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4551                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4552                          [], NoItinerary>;
4553
4554 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4555                                                 string asmop> {
4556   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4557                                              shr_imm8> {
4558     bits<3> Imm;
4559     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4560     let Inst{18-16} = Imm;
4561   }
4562   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4563                                              shr_imm16> {
4564     bits<4> Imm;
4565     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4566     let Inst{19-16} = Imm;
4567   }
4568   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4569                                              shr_imm32> {
4570     bits<5> Imm;
4571     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4572     let Inst{20-16} = Imm;
4573   }
4574 }
4575
4576 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4577   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4578     bits<5> Imm;
4579     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4580     let Inst{20-16} = Imm;
4581   }
4582   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4583     bits<6> Imm;
4584     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4585     let Inst{21-16} = Imm;
4586   }
4587 }
4588
4589 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4590                                                Instruction INSTD> {
4591   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4592                 (INSTD FPR64:$Rn, imm:$Imm)>;
4593 }
4594
4595 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4596                                                Instruction INSTD> {
4597   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4598                 (INSTD FPR64:$Rn, imm:$Imm)>;
4599 }
4600
4601 class Neon_ScalarShiftImm_V1_D_size_patterns<SDPatternOperator opnode,
4602                                              Instruction INSTD>
4603   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4604             (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4605         (INSTD FPR64:$Rn, imm:$Imm)>;
4606
4607 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4608                                                    Instruction INSTB,
4609                                                    Instruction INSTH,
4610                                                    Instruction INSTS,
4611                                                    Instruction INSTD>
4612   : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4613   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4614                 (INSTB FPR8:$Rn, imm:$Imm)>;
4615   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4616                 (INSTH FPR16:$Rn, imm:$Imm)>;
4617   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4618                 (INSTS FPR32:$Rn, imm:$Imm)>;
4619 }
4620
4621 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4622                                                 Instruction INSTD>
4623   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4624             (i32 shl_imm64:$Imm))),
4625         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4626
4627 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4628                                                 Instruction INSTD>
4629   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4630             (i32 shr_imm64:$Imm))),
4631         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4632
4633 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4634                                                        SDPatternOperator opnode,
4635                                                        Instruction INSTH,
4636                                                        Instruction INSTS,
4637                                                        Instruction INSTD> {
4638   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4639                 (INSTH FPR16:$Rn, imm:$Imm)>;
4640   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4641                 (INSTS FPR32:$Rn, imm:$Imm)>;
4642   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4643                 (INSTD FPR64:$Rn, imm:$Imm)>;
4644 }
4645
4646 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4647                                                       Instruction INSTS,
4648                                                       Instruction INSTD> {
4649   def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4650                 (INSTS FPR32:$Rn, imm:$Imm)>;
4651   def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4652                 (INSTD FPR64:$Rn, imm:$Imm)>;
4653 }
4654
4655 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4656                                                       Instruction INSTS,
4657                                                       Instruction INSTD> {
4658   def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4659                 (INSTS FPR32:$Rn, imm:$Imm)>;
4660   def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4661                 (INSTD FPR64:$Rn, imm:$Imm)>;
4662 }
4663
4664 // Scalar Signed Shift Right (Immediate)
4665 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4666 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4667 // Pattern to match llvm.arm.* intrinsic.
4668 def : Neon_ScalarShiftImm_V1_D_size_patterns<sra, SSHRddi>;
4669
4670 // Scalar Unsigned Shift Right (Immediate)
4671 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4672 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4673 // Pattern to match llvm.arm.* intrinsic.
4674 def : Neon_ScalarShiftImm_V1_D_size_patterns<srl, USHRddi>;
4675
4676 // Scalar Signed Rounding Shift Right (Immediate)
4677 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4678 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4679
4680 // Scalar Unigned Rounding Shift Right (Immediate)
4681 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4682 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4683
4684 // Scalar Signed Shift Right and Accumulate (Immediate)
4685 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4686 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4687           <int_aarch64_neon_vsrads_n, SSRA>;
4688
4689 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4690 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4691 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4692           <int_aarch64_neon_vsradu_n, USRA>;
4693
4694 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4695 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4696 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4697           <int_aarch64_neon_vrsrads_n, SRSRA>;
4698
4699 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4700 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4701 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4702           <int_aarch64_neon_vrsradu_n, URSRA>;
4703
4704 // Scalar Shift Left (Immediate)
4705 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4706 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4707 // Pattern to match llvm.arm.* intrinsic.
4708 def : Neon_ScalarShiftImm_V1_D_size_patterns<shl, SHLddi>;
4709
4710 // Signed Saturating Shift Left (Immediate)
4711 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4712 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4713                                                SQSHLbbi, SQSHLhhi,
4714                                                SQSHLssi, SQSHLddi>;
4715 // Pattern to match llvm.arm.* intrinsic.
4716 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4717
4718 // Unsigned Saturating Shift Left (Immediate)
4719 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4720 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4721                                                UQSHLbbi, UQSHLhhi,
4722                                                UQSHLssi, UQSHLddi>;
4723 // Pattern to match llvm.arm.* intrinsic.
4724 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4725
4726 // Signed Saturating Shift Left Unsigned (Immediate)
4727 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4728 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4729                                                SQSHLUbbi, SQSHLUhhi,
4730                                                SQSHLUssi, SQSHLUddi>;
4731
4732 // Shift Right And Insert (Immediate)
4733 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4734 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4735           <int_aarch64_neon_vsri, SRI>;
4736
4737 // Shift Left And Insert (Immediate)
4738 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4739 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4740           <int_aarch64_neon_vsli, SLI>;
4741
4742 // Signed Saturating Shift Right Narrow (Immediate)
4743 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4744 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4745                                                     SQSHRNbhi, SQSHRNhsi,
4746                                                     SQSHRNsdi>;
4747
4748 // Unsigned Saturating Shift Right Narrow (Immediate)
4749 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4750 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4751                                                     UQSHRNbhi, UQSHRNhsi,
4752                                                     UQSHRNsdi>;
4753
4754 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4755 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4756 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4757                                                     SQRSHRNbhi, SQRSHRNhsi,
4758                                                     SQRSHRNsdi>;
4759
4760 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4761 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4762 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4763                                                     UQRSHRNbhi, UQRSHRNhsi,
4764                                                     UQRSHRNsdi>;
4765
4766 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4767 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4768 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4769                                                     SQSHRUNbhi, SQSHRUNhsi,
4770                                                     SQSHRUNsdi>;
4771
4772 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4773 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4774 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4775                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4776                                                     SQRSHRUNsdi>;
4777
4778 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4779 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4780 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4781                                                   SCVTF_Nssi, SCVTF_Nddi>;
4782
4783 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4784 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4785 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4786                                                   UCVTF_Nssi, UCVTF_Nddi>;
4787
4788 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4789 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4790 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4791                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4792
4793 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4794 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4795 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4796                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4797
4798 // Patterns For Convert Instructions Between v1f64 and v1i64
4799 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4800                                              Instruction INST>
4801     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4802           (INST FPR64:$Rn, imm:$Imm)>;
4803
4804 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4805                                              Instruction INST>
4806     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4807           (INST FPR64:$Rn, imm:$Imm)>;
4808
4809 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4810                                              SCVTF_Nddi>;
4811
4812 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4813                                              UCVTF_Nddi>;
4814
4815 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4816                                              FCVTZS_Nddi>;
4817
4818 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4819                                              FCVTZU_Nddi>;
4820
4821 // Scalar Integer Add
4822 let isCommutable = 1 in {
4823 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4824 }
4825
4826 // Scalar Integer Sub
4827 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4828
4829 // Pattern for Scalar Integer Add and Sub with D register only
4830 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4831 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4832
4833 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4834 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4835 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4836 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4837 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4838
4839 // Scalar Integer Saturating Add (Signed, Unsigned)
4840 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4841 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4842
4843 // Scalar Integer Saturating Sub (Signed, Unsigned)
4844 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4845 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4846
4847
4848 // Patterns to match llvm.aarch64.* intrinsic for
4849 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
4850 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4851                                            SQADDhhh, SQADDsss, SQADDddd>;
4852 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4853                                            UQADDhhh, UQADDsss, UQADDddd>;
4854 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4855                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
4856 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4857                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
4858
4859 // Scalar Integer Saturating Doubling Multiply Half High
4860 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4861
4862 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4863 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4864
4865 // Patterns to match llvm.arm.* intrinsic for
4866 // Scalar Integer Saturating Doubling Multiply Half High and
4867 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4868 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4869                                                                SQDMULHsss>;
4870 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4871                                                                 SQRDMULHsss>;
4872
4873 // Scalar Floating-point Multiply Extended
4874 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4875
4876 // Scalar Floating-point Reciprocal Step
4877 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4878 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps,
4879                                          int_arm_neon_vrecps, FRECPSsss,
4880                                          FRECPSddd>;
4881
4882 // Scalar Floating-point Reciprocal Square Root Step
4883 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4884 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts,
4885                                          int_arm_neon_vrsqrts, FRSQRTSsss,
4886                                          FRSQRTSddd>;
4887 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
4888
4889 // Patterns to match llvm.aarch64.* intrinsic for
4890 // Scalar Floating-point Multiply Extended,
4891 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4892                                                   Instruction INSTS,
4893                                                   Instruction INSTD> {
4894   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4895             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4896   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4897             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4898 }
4899
4900 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4901                                               FMULXsss,FMULXddd>;
4902
4903 // Scalar Integer Shift Left (Signed, Unsigned)
4904 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4905 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4906
4907 // Patterns to match llvm.arm.* intrinsic for
4908 // Scalar Integer Shift Left (Signed, Unsigned)
4909 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4910 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4911
4912 // Patterns to match llvm.aarch64.* intrinsic for
4913 // Scalar Integer Shift Left (Signed, Unsigned)
4914 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4915 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4916
4917 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4918 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4919 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4920
4921 // Patterns to match llvm.aarch64.* intrinsic for
4922 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4923 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4924                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
4925 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4926                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
4927
4928 // Patterns to match llvm.arm.* intrinsic for
4929 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4930 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4931 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4932
4933 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4934 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4935 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4936
4937 // Patterns to match llvm.aarch64.* intrinsic for
4938 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4939 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4940 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4941
4942 // Patterns to match llvm.arm.* intrinsic for
4943 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4944 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4945 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4946
4947 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4948 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4949 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4950
4951 // Patterns to match llvm.aarch64.* intrinsic for
4952 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4953 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4954                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4955 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4956                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4957
4958 // Patterns to match llvm.arm.* intrinsic for
4959 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4960 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4961 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4962
4963 // Signed Saturating Doubling Multiply-Add Long
4964 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4965 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4966                                             SQDMLALshh, SQDMLALdss>;
4967
4968 // Signed Saturating Doubling Multiply-Subtract Long
4969 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4970 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4971                                             SQDMLSLshh, SQDMLSLdss>;
4972
4973 // Signed Saturating Doubling Multiply Long
4974 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4975 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4976                                          SQDMULLshh, SQDMULLdss>;
4977
4978 // Scalar Signed Integer Convert To Floating-point
4979 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4980 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
4981                                                  SCVTFss, SCVTFdd>;
4982
4983 // Scalar Unsigned Integer Convert To Floating-point
4984 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4985 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
4986                                                  UCVTFss, UCVTFdd>;
4987
4988 // Scalar Floating-point Converts
4989 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4990 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4991                                                   FCVTXN>;
4992
4993 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4994 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4995                                                   FCVTNSss, FCVTNSdd>;
4996 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
4997
4998 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4999 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
5000                                                   FCVTNUss, FCVTNUdd>;
5001 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
5002
5003 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
5004 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
5005                                                   FCVTMSss, FCVTMSdd>;
5006 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
5007
5008 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
5009 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5010                                                   FCVTMUss, FCVTMUdd>;
5011 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5012
5013 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5014 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5015                                                   FCVTASss, FCVTASdd>;
5016 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5017
5018 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5019 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5020                                                   FCVTAUss, FCVTAUdd>;
5021 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5022
5023 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5024 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5025                                                   FCVTPSss, FCVTPSdd>;
5026 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5027
5028 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5029 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5030                                                   FCVTPUss, FCVTPUdd>;
5031 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5032
5033 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5034 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5035                                                   FCVTZSss, FCVTZSdd>;
5036 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5037                                                 FCVTZSdd>;
5038
5039 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5040 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5041                                                   FCVTZUss, FCVTZUdd>;
5042 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5043                                                 FCVTZUdd>;
5044
5045 // Patterns For Convert Instructions Between v1f64 and v1i64
5046 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5047                                               Instruction INST>
5048     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5049
5050 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5051                                               Instruction INST>
5052     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5053
5054 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5055 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5056
5057 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5058 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5059
5060 // Scalar Floating-point Reciprocal Estimate
5061 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5062 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5063                                              FRECPEss, FRECPEdd>;
5064 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5065                                               FRECPEdd>;
5066
5067 // Scalar Floating-point Reciprocal Exponent
5068 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5069 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5070                                              FRECPXss, FRECPXdd>;
5071
5072 // Scalar Floating-point Reciprocal Square Root Estimate
5073 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5074 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5075                                                  FRSQRTEss, FRSQRTEdd>;
5076 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5077                                               FRSQRTEdd>;
5078
5079 // Scalar Floating-point Round
5080 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5081     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5082
5083 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5084 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5085 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5086 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5087 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5088 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5089 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5090
5091 // Scalar Integer Compare
5092
5093 // Scalar Compare Bitwise Equal
5094 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5095 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5096
5097 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5098                                               Instruction INSTD,
5099                                               CondCode CC>
5100   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5101         (INSTD FPR64:$Rn, FPR64:$Rm)>;
5102
5103 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5104
5105 // Scalar Compare Signed Greather Than Or Equal
5106 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5107 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5108 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5109
5110 // Scalar Compare Unsigned Higher Or Same
5111 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5112 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5113 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5114
5115 // Scalar Compare Unsigned Higher
5116 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5117 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5118 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5119
5120 // Scalar Compare Signed Greater Than
5121 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5122 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5123 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5124
5125 // Scalar Compare Bitwise Test Bits
5126 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5127 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5128 def : Neon_Scalar3Same_cmp_D_size_patterns<Neon_tst, CMTSTddd>;
5129
5130 // Scalar Compare Bitwise Equal To Zero
5131 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5132 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5133                                                 CMEQddi>;
5134 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5135
5136 // Scalar Compare Signed Greather Than Or Equal To Zero
5137 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5138 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5139                                                 CMGEddi>;
5140 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5141
5142 // Scalar Compare Signed Greater Than Zero
5143 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5144 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5145                                                 CMGTddi>;
5146 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5147
5148 // Scalar Compare Signed Less Than Or Equal To Zero
5149 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5150 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5151                                                 CMLEddi>;
5152 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5153
5154 // Scalar Compare Less Than Zero
5155 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5156 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5157                                                 CMLTddi>;
5158 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5159
5160 // Scalar Floating-point Compare
5161
5162 // Scalar Floating-point Compare Mask Equal
5163 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5164 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fceq,
5165                                              FCMEQsss, FCMEQddd>;
5166 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5167
5168 // Scalar Floating-point Compare Mask Equal To Zero
5169 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5170 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq,
5171                                                   FCMEQZssi, FCMEQZddi>;
5172 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
5173           (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
5174
5175 // Scalar Floating-point Compare Mask Greater Than Or Equal
5176 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5177 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcge,
5178                                              FCMGEsss, FCMGEddd>;
5179 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5180
5181 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5182 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5183 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge,
5184                                                   FCMGEZssi, FCMGEZddi>;
5185
5186 // Scalar Floating-point Compare Mask Greather Than
5187 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5188 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcgt,
5189                                              FCMGTsss, FCMGTddd>;
5190 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5191
5192 // Scalar Floating-point Compare Mask Greather Than Zero
5193 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5194 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt,
5195                                                   FCMGTZssi, FCMGTZddi>;
5196
5197 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5198 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5199 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez,
5200                                                   FCMLEZssi, FCMLEZddi>;
5201
5202 // Scalar Floating-point Compare Mask Less Than Zero
5203 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5204 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz,
5205                                                   FCMLTZssi, FCMLTZddi>;
5206
5207 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5208 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5209 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcage,
5210                                              FACGEsss, FACGEddd>;
5211 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5212           (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5213
5214 // Scalar Floating-point Absolute Compare Mask Greater Than
5215 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5216 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_fcagt,
5217                                              FACGTsss, FACGTddd>;
5218 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5219           (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5220
5221 // Scakar Floating-point Absolute Difference
5222 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5223 defm : Neon_Scalar3Same_fabd_SD_size_patterns<int_aarch64_neon_vabd,
5224                                               FABDsss, FABDddd>;
5225
5226 // Scalar Absolute Value
5227 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5228 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5229
5230 // Scalar Signed Saturating Absolute Value
5231 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5232 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5233                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
5234
5235 // Scalar Negate
5236 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5237 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5238
5239 // Scalar Signed Saturating Negate
5240 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5241 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5242                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5243
5244 // Scalar Signed Saturating Accumulated of Unsigned Value
5245 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5246 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5247                                                      SUQADDbb, SUQADDhh,
5248                                                      SUQADDss, SUQADDdd>;
5249
5250 // Scalar Unsigned Saturating Accumulated of Signed Value
5251 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5252 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5253                                                      USQADDbb, USQADDhh,
5254                                                      USQADDss, USQADDdd>;
5255
5256 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5257                                           (v1i64 FPR64:$Rn))),
5258           (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5259
5260 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5261                                           (v1i64 FPR64:$Rn))),
5262           (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5263
5264 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5265           (ABSdd FPR64:$Rn)>;
5266
5267 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5268           (SQABSdd FPR64:$Rn)>;
5269
5270 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5271           (SQNEGdd FPR64:$Rn)>;
5272
5273 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5274                       (v1i64 FPR64:$Rn))),
5275           (NEGdd FPR64:$Rn)>;
5276
5277 // Scalar Signed Saturating Extract Unsigned Narrow
5278 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5279 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5280                                                      SQXTUNbh, SQXTUNhs,
5281                                                      SQXTUNsd>;
5282
5283 // Scalar Signed Saturating Extract Narrow
5284 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5285 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5286                                                      SQXTNbh, SQXTNhs,
5287                                                      SQXTNsd>;
5288
5289 // Scalar Unsigned Saturating Extract Narrow
5290 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5291 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5292                                                      UQXTNbh, UQXTNhs,
5293                                                      UQXTNsd>;
5294
5295 // Scalar Reduce Pairwise
5296
5297 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5298                                      string asmop, bit Commutable = 0> {
5299   let isCommutable = Commutable in {
5300     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5301                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
5302                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5303                                 [],
5304                                 NoItinerary>;
5305   }
5306 }
5307
5308 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5309                                      string asmop, bit Commutable = 0>
5310   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5311   let isCommutable = Commutable in {
5312     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5313                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
5314                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5315                                 [],
5316                                 NoItinerary>;
5317   }
5318 }
5319
5320 // Scalar Reduce Addition Pairwise (Integer) with
5321 // Pattern to match llvm.arm.* intrinsic
5322 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5323
5324 // Pattern to match llvm.aarch64.* intrinsic for
5325 // Scalar Reduce Addition Pairwise (Integer)
5326 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5327           (ADDPvv_D_2D VPR128:$Rn)>;
5328 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5329           (ADDPvv_D_2D VPR128:$Rn)>;
5330
5331 // Scalar Reduce Addition Pairwise (Floating Point)
5332 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5333
5334 // Scalar Reduce Maximum Pairwise (Floating Point)
5335 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5336
5337 // Scalar Reduce Minimum Pairwise (Floating Point)
5338 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5339
5340 // Scalar Reduce maxNum Pairwise (Floating Point)
5341 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5342
5343 // Scalar Reduce minNum Pairwise (Floating Point)
5344 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5345
5346 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5347                                             Instruction INSTS,
5348                                             Instruction INSTD> {
5349   def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5350             (INSTS VPR64:$Rn)>;
5351   def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5352             (INSTD VPR128:$Rn)>;
5353 }
5354
5355 // Patterns to match llvm.aarch64.* intrinsic for
5356 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5357 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5358                                         FADDPvv_S_2S, FADDPvv_D_2D>;
5359
5360 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5361                                         FMAXPvv_S_2S, FMAXPvv_D_2D>;
5362
5363 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5364                                         FMINPvv_S_2S, FMINPvv_D_2D>;
5365
5366 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5367                                         FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5368
5369 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5370                                         FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5371
5372 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5373           (FADDPvv_S_2S (v2f32
5374                (EXTRACT_SUBREG
5375                    (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5376                    sub_64)))>;
5377
5378 // Scalar by element Arithmetic
5379
5380 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5381                                     string rmlane, bit u, bit szhi, bit szlo,
5382                                     RegisterClass ResFPR, RegisterClass OpFPR,
5383                                     RegisterOperand OpVPR, Operand OpImm>
5384   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5385                              (outs ResFPR:$Rd),
5386                              (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5387                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5388                              [],
5389                              NoItinerary> {
5390   bits<3> Imm;
5391   bits<5> MRm;
5392 }
5393
5394 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5395                                                     string rmlane,
5396                                                     bit u, bit szhi, bit szlo,
5397                                                     RegisterClass ResFPR,
5398                                                     RegisterClass OpFPR,
5399                                                     RegisterOperand OpVPR,
5400                                                     Operand OpImm>
5401   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5402                              (outs ResFPR:$Rd),
5403                              (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5404                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5405                              [],
5406                              NoItinerary> {
5407   let Constraints = "$src = $Rd";
5408   bits<3> Imm;
5409   bits<5> MRm;
5410 }
5411
5412 // Scalar Floating Point  multiply (scalar, by element)
5413 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5414   0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5415   let Inst{11} = Imm{1}; // h
5416   let Inst{21} = Imm{0}; // l
5417   let Inst{20-16} = MRm;
5418 }
5419 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5420   0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5421   let Inst{11} = Imm{0}; // h
5422   let Inst{21} = 0b0;    // l
5423   let Inst{20-16} = MRm;
5424 }
5425
5426 // Scalar Floating Point  multiply extended (scalar, by element)
5427 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5428   0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5429   let Inst{11} = Imm{1}; // h
5430   let Inst{21} = Imm{0}; // l
5431   let Inst{20-16} = MRm;
5432 }
5433 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5434   0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5435   let Inst{11} = Imm{0}; // h
5436   let Inst{21} = 0b0;    // l
5437   let Inst{20-16} = MRm;
5438 }
5439
5440 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5441   SDPatternOperator opnode,
5442   Instruction INST,
5443   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5444   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5445
5446   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5447                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5448              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5449
5450   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5451                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5452              (ResTy (INST (ResTy FPRC:$Rn),
5453                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5454                OpNImm:$Imm))>;
5455
5456   // swapped operands
5457   def  : Pat<(ResTy (opnode
5458                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5459                (ResTy FPRC:$Rn))),
5460              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5461
5462   def  : Pat<(ResTy (opnode
5463                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5464                (ResTy FPRC:$Rn))),
5465              (ResTy (INST (ResTy FPRC:$Rn),
5466                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5467                OpNImm:$Imm))>;
5468 }
5469
5470 // Patterns for Scalar Floating Point  multiply (scalar, by element)
5471 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5472   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5473 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5474   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5475
5476 // Patterns for Scalar Floating Point  multiply extended (scalar, by element)
5477 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5478   FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5479   v2f32, v4f32, neon_uimm1_bare>;
5480 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5481   FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5482   v1f64, v2f64, neon_uimm0_bare>;
5483
5484
5485 // Scalar Floating Point fused multiply-add (scalar, by element)
5486 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5487   0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5488   let Inst{11} = Imm{1}; // h
5489   let Inst{21} = Imm{0}; // l
5490   let Inst{20-16} = MRm;
5491 }
5492 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5493   0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5494   let Inst{11} = Imm{0}; // h
5495   let Inst{21} = 0b0;    // l
5496   let Inst{20-16} = MRm;
5497 }
5498
5499 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5500 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5501   0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5502   let Inst{11} = Imm{1}; // h
5503   let Inst{21} = Imm{0}; // l
5504   let Inst{20-16} = MRm;
5505 }
5506 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5507   0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5508   let Inst{11} = Imm{0}; // h
5509   let Inst{21} = 0b0;    // l
5510   let Inst{20-16} = MRm;
5511 }
5512 // We are allowed to match the fma instruction regardless of compile options.
5513 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5514   Instruction FMLAI, Instruction FMLSI,
5515   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5516   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5517   // fmla
5518   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5519                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5520                (ResTy FPRC:$Ra))),
5521              (ResTy (FMLAI (ResTy FPRC:$Ra),
5522                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5523
5524   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5525                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5526                (ResTy FPRC:$Ra))),
5527              (ResTy (FMLAI (ResTy FPRC:$Ra),
5528                (ResTy FPRC:$Rn),
5529                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5530                OpNImm:$Imm))>;
5531
5532   // swapped fmla operands
5533   def  : Pat<(ResTy (fma
5534                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5535                (ResTy FPRC:$Rn),
5536                (ResTy FPRC:$Ra))),
5537              (ResTy (FMLAI (ResTy FPRC:$Ra),
5538                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5539
5540   def  : Pat<(ResTy (fma
5541                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5542                (ResTy FPRC:$Rn),
5543                (ResTy FPRC:$Ra))),
5544              (ResTy (FMLAI (ResTy FPRC:$Ra),
5545                (ResTy FPRC:$Rn),
5546                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5547                OpNImm:$Imm))>;
5548
5549   // fmls
5550   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5551                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5552                (ResTy FPRC:$Ra))),
5553              (ResTy (FMLSI (ResTy FPRC:$Ra),
5554                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5555
5556   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5557                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5558                (ResTy FPRC:$Ra))),
5559              (ResTy (FMLSI (ResTy FPRC:$Ra),
5560                (ResTy FPRC:$Rn),
5561                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5562                OpNImm:$Imm))>;
5563
5564   // swapped fmls operands
5565   def  : Pat<(ResTy (fma
5566                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5567                (ResTy FPRC:$Rn),
5568                (ResTy FPRC:$Ra))),
5569              (ResTy (FMLSI (ResTy FPRC:$Ra),
5570                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5571
5572   def  : Pat<(ResTy (fma
5573                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5574                (ResTy FPRC:$Rn),
5575                (ResTy FPRC:$Ra))),
5576              (ResTy (FMLSI (ResTy FPRC:$Ra),
5577                (ResTy FPRC:$Rn),
5578                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5579                OpNImm:$Imm))>;
5580 }
5581
5582 // Scalar Floating Point fused multiply-add and
5583 // multiply-subtract (scalar, by element)
5584 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5585   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5586 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5587   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5588 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5589   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5590
5591 // Scalar Signed saturating doubling multiply long (scalar, by element)
5592 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5593   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5594   let Inst{11} = 0b0; // h
5595   let Inst{21} = Imm{1}; // l
5596   let Inst{20} = Imm{0}; // m
5597   let Inst{19-16} = MRm{3-0};
5598 }
5599 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5600   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5601   let Inst{11} = Imm{2}; // h
5602   let Inst{21} = Imm{1}; // l
5603   let Inst{20} = Imm{0}; // m
5604   let Inst{19-16} = MRm{3-0};
5605 }
5606 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5607   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5608   let Inst{11} = 0b0;    // h
5609   let Inst{21} = Imm{0}; // l
5610   let Inst{20-16} = MRm;
5611 }
5612 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5613   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5614   let Inst{11} = Imm{1};    // h
5615   let Inst{21} = Imm{0};    // l
5616   let Inst{20-16} = MRm;
5617 }
5618
5619 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5620   SDPatternOperator opnode,
5621   Instruction INST,
5622   ValueType ResTy, RegisterClass FPRC,
5623   ValueType OpVTy, ValueType OpTy,
5624   ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5625
5626   def  : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5627                (OpVTy (scalar_to_vector
5628                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5629              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5630
5631   //swapped operands
5632   def  : Pat<(ResTy (opnode
5633                (OpVTy (scalar_to_vector
5634                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5635                  (OpVTy FPRC:$Rn))),
5636              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5637 }
5638
5639
5640 // Patterns for Scalar Signed saturating doubling
5641 // multiply long (scalar, by element)
5642 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5643   SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5644   i32, VPR64Lo, neon_uimm2_bare>;
5645 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5646   SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5647   i32, VPR128Lo, neon_uimm3_bare>;
5648 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5649   SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5650   i32, VPR64Lo, neon_uimm1_bare>;
5651 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5652   SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5653   i32, VPR128Lo, neon_uimm2_bare>;
5654
5655 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5656 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5657   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5658   let Inst{11} = 0b0; // h
5659   let Inst{21} = Imm{1}; // l
5660   let Inst{20} = Imm{0}; // m
5661   let Inst{19-16} = MRm{3-0};
5662 }
5663 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5664   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5665   let Inst{11} = Imm{2}; // h
5666   let Inst{21} = Imm{1}; // l
5667   let Inst{20} = Imm{0}; // m
5668   let Inst{19-16} = MRm{3-0};
5669 }
5670 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5671   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5672   let Inst{11} = 0b0;    // h
5673   let Inst{21} = Imm{0}; // l
5674   let Inst{20-16} = MRm;
5675 }
5676 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5677   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5678   let Inst{11} = Imm{1};    // h
5679   let Inst{21} = Imm{0};    // l
5680   let Inst{20-16} = MRm;
5681 }
5682
5683 // Scalar Signed saturating doubling
5684 // multiply-subtract long (scalar, by element)
5685 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5686   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5687   let Inst{11} = 0b0; // h
5688   let Inst{21} = Imm{1}; // l
5689   let Inst{20} = Imm{0}; // m
5690   let Inst{19-16} = MRm{3-0};
5691 }
5692 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5693   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5694   let Inst{11} = Imm{2}; // h
5695   let Inst{21} = Imm{1}; // l
5696   let Inst{20} = Imm{0}; // m
5697   let Inst{19-16} = MRm{3-0};
5698 }
5699 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5700   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5701   let Inst{11} = 0b0;    // h
5702   let Inst{21} = Imm{0}; // l
5703   let Inst{20-16} = MRm;
5704 }
5705 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5706   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5707   let Inst{11} = Imm{1};    // h
5708   let Inst{21} = Imm{0};    // l
5709   let Inst{20-16} = MRm;
5710 }
5711
5712 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5713   SDPatternOperator opnode,
5714   SDPatternOperator coreopnode,
5715   Instruction INST,
5716   ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5717   ValueType OpTy,
5718   ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5719
5720   def  : Pat<(ResTy (opnode
5721                (ResTy ResFPRC:$Ra),
5722                (ResTy (coreopnode (OpTy FPRC:$Rn),
5723                  (OpTy (scalar_to_vector
5724                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5725              (ResTy (INST (ResTy ResFPRC:$Ra),
5726                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5727
5728   // swapped operands
5729   def  : Pat<(ResTy (opnode
5730                (ResTy ResFPRC:$Ra),
5731                (ResTy (coreopnode
5732                  (OpTy (scalar_to_vector
5733                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5734                  (OpTy FPRC:$Rn))))),
5735              (ResTy (INST (ResTy ResFPRC:$Ra),
5736                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5737 }
5738
5739 // Patterns for Scalar Signed saturating
5740 // doubling multiply-add long (scalar, by element)
5741 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5742   int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5743   i32, VPR64Lo, neon_uimm2_bare>;
5744 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5745   int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5746   i32, VPR128Lo, neon_uimm3_bare>;
5747 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5748   int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5749   i32, VPR64Lo, neon_uimm1_bare>;
5750 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5751   int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5752   i32, VPR128Lo, neon_uimm2_bare>;
5753
5754 // Patterns for Scalar Signed saturating
5755 // doubling multiply-sub long (scalar, by element)
5756 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5757   int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5758   i32, VPR64Lo, neon_uimm2_bare>;
5759 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5760   int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5761   i32, VPR128Lo, neon_uimm3_bare>;
5762 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5763   int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5764   i32, VPR64Lo, neon_uimm1_bare>;
5765 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5766   int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5767   i32, VPR128Lo, neon_uimm2_bare>;
5768
5769 // Scalar general arithmetic operation
5770 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
5771                                         Instruction INST>
5772     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5773
5774 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
5775                                         Instruction INST>
5776     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5777           (INST FPR64:$Rn, FPR64:$Rm)>;
5778
5779 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
5780                                         Instruction INST>
5781     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
5782               (v1f64 FPR64:$Ra))),
5783           (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5784
5785 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
5786 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
5787 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
5788 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
5789 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
5790 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
5791 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
5792 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
5793 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
5794
5795 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
5796 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
5797
5798 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
5799 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
5800
5801 // Scalar Signed saturating doubling multiply returning
5802 // high half (scalar, by element)
5803 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5804   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5805   let Inst{11} = 0b0; // h
5806   let Inst{21} = Imm{1}; // l
5807   let Inst{20} = Imm{0}; // m
5808   let Inst{19-16} = MRm{3-0};
5809 }
5810 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5811   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5812   let Inst{11} = Imm{2}; // h
5813   let Inst{21} = Imm{1}; // l
5814   let Inst{20} = Imm{0}; // m
5815   let Inst{19-16} = MRm{3-0};
5816 }
5817 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5818   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5819   let Inst{11} = 0b0;    // h
5820   let Inst{21} = Imm{0}; // l
5821   let Inst{20-16} = MRm;
5822 }
5823 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5824   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5825   let Inst{11} = Imm{1};    // h
5826   let Inst{21} = Imm{0};    // l
5827   let Inst{20-16} = MRm;
5828 }
5829
5830 // Patterns for Scalar Signed saturating doubling multiply returning
5831 // high half (scalar, by element)
5832 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5833   SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5834   i32, VPR64Lo, neon_uimm2_bare>;
5835 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5836   SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5837   i32, VPR128Lo, neon_uimm3_bare>;
5838 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5839   SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5840   i32, VPR64Lo, neon_uimm1_bare>;
5841 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5842   SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5843   i32, VPR128Lo, neon_uimm2_bare>;
5844
5845 // Scalar Signed saturating rounding doubling multiply
5846 // returning high half (scalar, by element)
5847 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5848   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5849   let Inst{11} = 0b0; // h
5850   let Inst{21} = Imm{1}; // l
5851   let Inst{20} = Imm{0}; // m
5852   let Inst{19-16} = MRm{3-0};
5853 }
5854 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5855   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5856   let Inst{11} = Imm{2}; // h
5857   let Inst{21} = Imm{1}; // l
5858   let Inst{20} = Imm{0}; // m
5859   let Inst{19-16} = MRm{3-0};
5860 }
5861 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5862   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5863   let Inst{11} = 0b0;    // h
5864   let Inst{21} = Imm{0}; // l
5865   let Inst{20-16} = MRm;
5866 }
5867 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5868   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5869   let Inst{11} = Imm{1};    // h
5870   let Inst{21} = Imm{0};    // l
5871   let Inst{20-16} = MRm;
5872 }
5873
5874 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5875   SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5876   VPR64Lo, neon_uimm2_bare>;
5877 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5878   SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5879   VPR128Lo, neon_uimm3_bare>;
5880 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5881   SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5882   VPR64Lo, neon_uimm1_bare>;
5883 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5884   SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5885   VPR128Lo, neon_uimm2_bare>;
5886
5887 // Scalar Copy - DUP element to scalar
5888 class NeonI_Scalar_DUP<string asmop, string asmlane,
5889                        RegisterClass ResRC, RegisterOperand VPRC,
5890                        Operand OpImm>
5891   : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5892                      asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5893                      [],
5894                      NoItinerary> {
5895   bits<4> Imm;
5896 }
5897
5898 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5899   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5900 }
5901 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5902   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5903 }
5904 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5905   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5906 }
5907 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5908   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5909 }
5910
5911 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5912   ValueType OpTy, Operand OpImm,
5913   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5914   def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5915             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5916
5917   def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5918             (ResTy (DUPI
5919               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5920                 OpNImm:$Imm))>;
5921 }
5922
5923 // Patterns for vector extract of FP data using scalar DUP instructions
5924 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5925   v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5926 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5927   v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5928
5929 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
5930   ValueType ResTy, ValueType OpTy,Operand OpLImm,
5931   ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5932
5933   def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5934             (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5935
5936   def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5937             (ResTy (DUPI
5938               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5939                 OpNImm:$Imm))>;
5940 }
5941
5942 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
5943 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
5944                                         v8i8, v16i8, neon_uimm3_bare>;
5945 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
5946                                         v4i16, v8i16, neon_uimm2_bare>;
5947 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
5948                                         v2i32, v4i32, neon_uimm1_bare>;
5949
5950 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
5951                                           ValueType OpTy, ValueType ElemTy,
5952                                           Operand OpImm, ValueType OpNTy,
5953                                           ValueType ExTy, Operand OpNImm> {
5954
5955   def : Pat<(ResTy (vector_insert (ResTy undef),
5956               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5957               (neon_uimm0_bare:$Imm))),
5958             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5959
5960   def : Pat<(ResTy (vector_insert (ResTy undef),
5961               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5962               (OpNImm:$Imm))),
5963             (ResTy (DUPI
5964               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5965               OpNImm:$Imm))>;
5966 }
5967
5968 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
5969                                           ValueType OpTy, ValueType ElemTy,
5970                                           Operand OpImm, ValueType OpNTy,
5971                                           ValueType ExTy, Operand OpNImm> {
5972
5973   def : Pat<(ResTy (scalar_to_vector
5974               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
5975             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5976
5977   def : Pat<(ResTy (scalar_to_vector
5978               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
5979             (ResTy (DUPI
5980               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5981               OpNImm:$Imm))>;
5982 }
5983
5984 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
5985 // instructions.
5986 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5987   v1i64, v2i64, i64, neon_uimm1_bare,
5988   v1i64, v2i64, neon_uimm0_bare>;
5989 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5990   v1i32, v4i32, i32, neon_uimm2_bare,
5991   v2i32, v4i32, neon_uimm1_bare>;
5992 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
5993   v1i16, v8i16, i32, neon_uimm3_bare,
5994   v4i16, v8i16, neon_uimm2_bare>;
5995 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
5996   v1i8, v16i8, i32, neon_uimm4_bare,
5997   v8i8, v16i8, neon_uimm3_bare>;
5998 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5999   v1i64, v2i64, i64, neon_uimm1_bare,
6000   v1i64, v2i64, neon_uimm0_bare>;
6001 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
6002   v1i32, v4i32, i32, neon_uimm2_bare,
6003   v2i32, v4i32, neon_uimm1_bare>;
6004 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
6005   v1i16, v8i16, i32, neon_uimm3_bare,
6006   v4i16, v8i16, neon_uimm2_bare>;
6007 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
6008   v1i8, v16i8, i32, neon_uimm4_bare,
6009   v8i8, v16i8, neon_uimm3_bare>;
6010
6011 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6012                                   Instruction DUPI, Operand OpImm,
6013                                   RegisterClass ResRC> {
6014   def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6015           (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6016 }
6017
6018 // Aliases for Scalar copy - DUP element (scalar)
6019 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6020 // custom printing of aliases.
6021 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6022 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6023 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6024 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6025
6026 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6027                       ValueType OpTy> {
6028   def : Pat<(ResTy (GetLow VPR128:$Rn)),
6029             (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6030   def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6031             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6032 }
6033
6034 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6035 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6036 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6037 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6038 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6039 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6040
6041 //===----------------------------------------------------------------------===//
6042 // Non-Instruction Patterns
6043 //===----------------------------------------------------------------------===//
6044
6045 // 64-bit vector bitcasts...
6046
6047 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
6048 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
6049 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
6050 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
6051
6052 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
6053 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
6054 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
6055 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
6056
6057 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
6058 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
6059 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
6060 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
6061
6062 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
6063 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
6064 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
6065 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
6066
6067 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
6068 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6069 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6070 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6071
6072 // ..and 128-bit vector bitcasts...
6073
6074 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
6075 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
6076 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
6077 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
6078 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
6079
6080 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
6081 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
6082 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
6083 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
6084 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
6085
6086 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
6087 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
6088 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
6089 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
6090 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
6091
6092 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
6093 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
6094 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
6095 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
6096 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
6097
6098 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
6099 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
6100 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
6101 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
6102 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
6103
6104 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
6105 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
6106 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
6107 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
6108 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
6109
6110 // ...and scalar bitcasts...
6111 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
6112 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
6113 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
6114 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
6115
6116 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
6117 def : Pat<(i64 (bitconvert (v1f64  FPR64:$src))), (FMOVxd $src)>;
6118 def : Pat<(i64 (bitconvert (v2i32  FPR64:$src))), (FMOVxd $src)>;
6119 def : Pat<(i64 (bitconvert (v2f32  FPR64:$src))), (FMOVxd $src)>;
6120 def : Pat<(i64 (bitconvert (v4i16  FPR64:$src))), (FMOVxd $src)>;
6121 def : Pat<(i64 (bitconvert (v8i8  FPR64:$src))), (FMOVxd $src)>;
6122
6123 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
6124
6125 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6126 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6127 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6128
6129 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
6130 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
6131 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
6132 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
6133 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
6134
6135 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
6136 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
6137 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
6138 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
6139 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
6140 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
6141
6142 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
6143 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
6144 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
6145 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
6146
6147 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6148 def : Pat<(v1f64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6149 def : Pat<(v2i32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6150 def : Pat<(v2f32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6151 def : Pat<(v4i16 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6152 def : Pat<(v8i8 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6153
6154 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
6155
6156 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
6157 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
6158 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
6159 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
6160 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
6161
6162 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
6163 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
6164 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
6165 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
6166 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
6167 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
6168
6169 // Scalar Three Same
6170
6171 def neon_uimm3 : Operand<i64>,
6172                    ImmLeaf<i64, [{return Imm < 8;}]> {
6173   let ParserMatchClass = uimm3_asmoperand;
6174   let PrintMethod = "printUImmHexOperand";
6175 }
6176
6177 def neon_uimm4 : Operand<i64>,
6178                    ImmLeaf<i64, [{return Imm < 16;}]> {
6179   let ParserMatchClass = uimm4_asmoperand;
6180   let PrintMethod = "printUImmHexOperand";
6181 }
6182
6183 // Bitwise Extract
6184 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6185                     string OpS, RegisterOperand OpVPR, Operand OpImm>
6186   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6187                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6188                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6189                      ", $Rm." # OpS # ", $Index",
6190                      [],
6191                      NoItinerary>{
6192   bits<4> Index;
6193 }
6194
6195 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6196                                VPR64, neon_uimm3> {
6197   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6198 }
6199
6200 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6201                                VPR128, neon_uimm4> {
6202   let Inst{14-11} = Index;
6203 }
6204
6205 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6206                  Operand OpImm>
6207   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6208                                  (i64 OpImm:$Imm))),
6209               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6210
6211 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
6212 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6213 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6214 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6215 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6216 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6217 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6218 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6219 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6220 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6221 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6222 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6223
6224 // Table lookup
6225 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6226              string asmop, string OpS, RegisterOperand OpVPR,
6227              RegisterOperand VecList>
6228   : NeonI_TBL<q, op2, len, op,
6229               (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6230               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6231               [],
6232               NoItinerary>;
6233
6234 // The vectors in look up table are always 16b
6235 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6236   def _8b  : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6237                     !cast<RegisterOperand>(List # "16B_operand")>;
6238
6239   def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6240                     !cast<RegisterOperand>(List # "16B_operand")>;
6241 }
6242
6243 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6244 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6245 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6246 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6247
6248 // Table lookup extention
6249 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6250              string asmop, string OpS, RegisterOperand OpVPR,
6251              RegisterOperand VecList>
6252   : NeonI_TBL<q, op2, len, op,
6253               (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6254               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6255               [],
6256               NoItinerary> {
6257   let Constraints = "$src = $Rd";
6258 }
6259
6260 // The vectors in look up table are always 16b
6261 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6262   def _8b  : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6263                     !cast<RegisterOperand>(List # "16B_operand")>;
6264
6265   def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6266                     !cast<RegisterOperand>(List # "16B_operand")>;
6267 }
6268
6269 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6270 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6271 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6272 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6273
6274 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6275                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6276   : NeonI_copy<0b1, 0b0, 0b0011,
6277                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6278                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6279                [(set (ResTy VPR128:$Rd),
6280                  (ResTy (vector_insert
6281                    (ResTy VPR128:$src),
6282                    (OpTy OpGPR:$Rn),
6283                    (OpImm:$Imm))))],
6284                NoItinerary> {
6285   bits<4> Imm;
6286   let Constraints = "$src = $Rd";
6287 }
6288
6289 //Insert element (vector, from main)
6290 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6291                            neon_uimm4_bare> {
6292   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6293 }
6294 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6295                            neon_uimm3_bare> {
6296   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6297 }
6298 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6299                            neon_uimm2_bare> {
6300   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6301 }
6302 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6303                            neon_uimm1_bare> {
6304   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6305 }
6306
6307 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6308                     (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6309 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6310                     (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6311 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6312                     (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6313 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6314                     (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6315
6316 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6317                              RegisterClass OpGPR, ValueType OpTy,
6318                              Operand OpImm, Instruction INS>
6319   : Pat<(ResTy (vector_insert
6320               (ResTy VPR64:$src),
6321               (OpTy OpGPR:$Rn),
6322               (OpImm:$Imm))),
6323         (ResTy (EXTRACT_SUBREG
6324           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6325             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6326
6327 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6328                                           neon_uimm3_bare, INSbw>;
6329 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6330                                           neon_uimm2_bare, INShw>;
6331 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6332                                           neon_uimm1_bare, INSsw>;
6333 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6334                                           neon_uimm0_bare, INSdx>;
6335
6336 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6337   : NeonI_insert<0b1, 0b1,
6338                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6339                  ResImm:$Immd, ResImm:$Immn),
6340                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6341                  [],
6342                  NoItinerary> {
6343   let Constraints = "$src = $Rd";
6344   bits<4> Immd;
6345   bits<4> Immn;
6346 }
6347
6348 //Insert element (vector, from element)
6349 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6350   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6351   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6352 }
6353 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6354   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6355   let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6356   // bit 11 is unspecified, but should be set to zero.
6357 }
6358 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6359   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6360   let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6361   // bits 11-12 are unspecified, but should be set to zero.
6362 }
6363 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6364   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6365   let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6366   // bits 11-13 are unspecified, but should be set to zero.
6367 }
6368
6369 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6370                     (INSELb VPR128:$Rd, VPR128:$Rn,
6371                       neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6372 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6373                     (INSELh VPR128:$Rd, VPR128:$Rn,
6374                       neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6375 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6376                     (INSELs VPR128:$Rd, VPR128:$Rn,
6377                       neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6378 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6379                     (INSELd VPR128:$Rd, VPR128:$Rn,
6380                       neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6381
6382 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6383                                 ValueType MidTy, Operand StImm, Operand NaImm,
6384                                 Instruction INS> {
6385 def : Pat<(ResTy (vector_insert
6386             (ResTy VPR128:$src),
6387             (MidTy (vector_extract
6388               (ResTy VPR128:$Rn),
6389               (StImm:$Immn))),
6390             (StImm:$Immd))),
6391           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6392               StImm:$Immd, StImm:$Immn)>;
6393
6394 def : Pat <(ResTy (vector_insert
6395              (ResTy VPR128:$src),
6396              (MidTy (vector_extract
6397                (NaTy VPR64:$Rn),
6398                (NaImm:$Immn))),
6399              (StImm:$Immd))),
6400            (INS (ResTy VPR128:$src),
6401              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6402              StImm:$Immd, NaImm:$Immn)>;
6403
6404 def : Pat <(NaTy (vector_insert
6405              (NaTy VPR64:$src),
6406              (MidTy (vector_extract
6407                (ResTy VPR128:$Rn),
6408                (StImm:$Immn))),
6409              (NaImm:$Immd))),
6410            (NaTy (EXTRACT_SUBREG
6411              (ResTy (INS
6412                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6413                (ResTy VPR128:$Rn),
6414                NaImm:$Immd, StImm:$Immn)),
6415              sub_64))>;
6416
6417 def : Pat <(NaTy (vector_insert
6418              (NaTy VPR64:$src),
6419              (MidTy (vector_extract
6420                (NaTy VPR64:$Rn),
6421                (NaImm:$Immn))),
6422              (NaImm:$Immd))),
6423            (NaTy (EXTRACT_SUBREG
6424              (ResTy (INS
6425                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6426                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6427                NaImm:$Immd, NaImm:$Immn)),
6428              sub_64))>;
6429 }
6430
6431 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6432                             neon_uimm1_bare, INSELs>;
6433 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6434                             neon_uimm0_bare, INSELd>;
6435 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6436                             neon_uimm3_bare, INSELb>;
6437 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6438                             neon_uimm2_bare, INSELh>;
6439 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6440                             neon_uimm1_bare, INSELs>;
6441 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6442                             neon_uimm0_bare, INSELd>;
6443
6444 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6445                                       ValueType MidTy,
6446                                       RegisterClass OpFPR, Operand ResImm,
6447                                       SubRegIndex SubIndex, Instruction INS> {
6448 def : Pat <(ResTy (vector_insert
6449              (ResTy VPR128:$src),
6450              (MidTy OpFPR:$Rn),
6451              (ResImm:$Imm))),
6452            (INS (ResTy VPR128:$src),
6453              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6454              ResImm:$Imm,
6455              (i64 0))>;
6456
6457 def : Pat <(NaTy (vector_insert
6458              (NaTy VPR64:$src),
6459              (MidTy OpFPR:$Rn),
6460              (ResImm:$Imm))),
6461            (NaTy (EXTRACT_SUBREG
6462              (ResTy (INS
6463                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6464                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6465                ResImm:$Imm,
6466                (i64 0))),
6467              sub_64))>;
6468 }
6469
6470 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6471                                   sub_32, INSELs>;
6472 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6473                                   sub_64, INSELd>;
6474
6475 class NeonI_SMOV<string asmop, string Res, bit Q,
6476                  ValueType OpTy, ValueType eleTy,
6477                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6478   : NeonI_copy<Q, 0b0, 0b0101,
6479                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6480                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6481                [(set (ResTy ResGPR:$Rd),
6482                  (ResTy (sext_inreg
6483                    (ResTy (vector_extract
6484                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
6485                    eleTy)))],
6486                NoItinerary> {
6487   bits<4> Imm;
6488 }
6489
6490 //Signed integer move (main, from element)
6491 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6492                         GPR32, i32> {
6493   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6494 }
6495 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6496                         GPR32, i32> {
6497   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6498 }
6499 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6500                         GPR64, i64> {
6501   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6502 }
6503 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6504                         GPR64, i64> {
6505   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6506 }
6507 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6508                         GPR64, i64> {
6509   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6510 }
6511
6512 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6513                                ValueType eleTy, Operand StImm,  Operand NaImm,
6514                                Instruction SMOVI> {
6515   def : Pat<(i64 (sext_inreg
6516               (i64 (anyext
6517                 (i32 (vector_extract
6518                   (StTy VPR128:$Rn), (StImm:$Imm))))),
6519               eleTy)),
6520             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6521
6522   def : Pat<(i64 (sext
6523               (i32 (vector_extract
6524                 (StTy VPR128:$Rn), (StImm:$Imm))))),
6525             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6526
6527   def : Pat<(i64 (sext_inreg
6528               (i64 (vector_extract
6529                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6530               eleTy)),
6531             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6532               NaImm:$Imm)>;
6533
6534   def : Pat<(i64 (sext_inreg
6535               (i64 (anyext
6536                 (i32 (vector_extract
6537                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6538               eleTy)),
6539             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6540               NaImm:$Imm)>;
6541
6542   def : Pat<(i64 (sext
6543               (i32 (vector_extract
6544                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6545             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6546               NaImm:$Imm)>;
6547 }
6548
6549 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6550                           neon_uimm3_bare, SMOVxb>;
6551 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6552                           neon_uimm2_bare, SMOVxh>;
6553 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6554                           neon_uimm1_bare, SMOVxs>;
6555
6556 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6557                           ValueType eleTy, Operand StImm,  Operand NaImm,
6558                           Instruction SMOVI>
6559   : Pat<(i32 (sext_inreg
6560           (i32 (vector_extract
6561             (NaTy VPR64:$Rn), (NaImm:$Imm))),
6562           eleTy)),
6563         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6564           NaImm:$Imm)>;
6565
6566 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6567                          neon_uimm3_bare, SMOVwb>;
6568 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6569                          neon_uimm2_bare, SMOVwh>;
6570
6571 class NeonI_UMOV<string asmop, string Res, bit Q,
6572                  ValueType OpTy, Operand OpImm,
6573                  RegisterClass ResGPR, ValueType ResTy>
6574   : NeonI_copy<Q, 0b0, 0b0111,
6575                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6576                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6577                [(set (ResTy ResGPR:$Rd),
6578                   (ResTy (vector_extract
6579                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6580                NoItinerary> {
6581   bits<4> Imm;
6582 }
6583
6584 //Unsigned integer move (main, from element)
6585 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6586                          GPR32, i32> {
6587   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6588 }
6589 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6590                          GPR32, i32> {
6591   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6592 }
6593 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6594                          GPR32, i32> {
6595   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6596 }
6597 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6598                          GPR64, i64> {
6599   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6600 }
6601
6602 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6603                     (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6604 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6605                     (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6606
6607 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6608                          Operand StImm,  Operand NaImm,
6609                          Instruction SMOVI>
6610   : Pat<(ResTy (vector_extract
6611           (NaTy VPR64:$Rn), NaImm:$Imm)),
6612         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6613           NaImm:$Imm)>;
6614
6615 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6616                         neon_uimm3_bare, UMOVwb>;
6617 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6618                         neon_uimm2_bare, UMOVwh>;
6619 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6620                         neon_uimm1_bare, UMOVws>;
6621
6622 def : Pat<(i32 (and
6623             (i32 (vector_extract
6624               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6625             255)),
6626           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6627
6628 def : Pat<(i32 (and
6629             (i32 (vector_extract
6630               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6631             65535)),
6632           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6633
6634 def : Pat<(i64 (zext
6635             (i32 (vector_extract
6636               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6637           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6638
6639 def : Pat<(i32 (and
6640             (i32 (vector_extract
6641               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6642             255)),
6643           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6644             neon_uimm3_bare:$Imm)>;
6645
6646 def : Pat<(i32 (and
6647             (i32 (vector_extract
6648               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6649             65535)),
6650           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6651             neon_uimm2_bare:$Imm)>;
6652
6653 def : Pat<(i64 (zext
6654             (i32 (vector_extract
6655               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6656           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6657             neon_uimm0_bare:$Imm)>;
6658
6659 // Additional copy patterns for scalar types
6660 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6661           (UMOVwb (v16i8
6662             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6663
6664 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6665           (UMOVwh (v8i16
6666             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6667
6668 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6669           (FMOVws FPR32:$Rn)>;
6670
6671 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6672           (FMOVxd FPR64:$Rn)>;
6673
6674 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6675           (f64 FPR64:$Rn)>;
6676
6677 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6678           (v1i8 (EXTRACT_SUBREG (v16i8
6679             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6680             sub_8))>;
6681
6682 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6683           (v1i16 (EXTRACT_SUBREG (v8i16
6684             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6685             sub_16))>;
6686
6687 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6688           (FMOVsw $src)>;
6689
6690 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6691           (FMOVdx $src)>;
6692
6693 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
6694           (v8i8 (EXTRACT_SUBREG (v16i8
6695             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6696             sub_64))>;
6697
6698 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
6699           (v4i16 (EXTRACT_SUBREG (v8i16
6700             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6701             sub_64))>;
6702
6703 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6704           (v2i32 (EXTRACT_SUBREG (v16i8
6705             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6706             sub_64))>;
6707
6708 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
6709           (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6710
6711 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
6712           (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6713
6714 def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
6715           (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6716
6717 def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
6718           (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6719
6720 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6721           (v2i32 (EXTRACT_SUBREG (v16i8
6722             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6723             sub_64))>;
6724
6725 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6726           (v2i32 (EXTRACT_SUBREG (v16i8
6727             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6728             sub_64))>;
6729
6730 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6731           (v1f64 FPR64:$Rn)>;
6732
6733 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6734           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6735                          (f64 FPR64:$src), sub_64)>;
6736
6737 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
6738                     RegisterOperand ResVPR, Operand OpImm>
6739   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6740                (ins VPR128:$Rn, OpImm:$Imm),
6741                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6742                [],
6743                NoItinerary> {
6744   bits<4> Imm;
6745 }
6746
6747 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6748                               neon_uimm4_bare> {
6749   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6750 }
6751
6752 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6753                               neon_uimm3_bare> {
6754   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6755 }
6756
6757 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6758                               neon_uimm2_bare> {
6759   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6760 }
6761
6762 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6763                               neon_uimm1_bare> {
6764   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6765 }
6766
6767 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6768                               neon_uimm4_bare> {
6769   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6770 }
6771
6772 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6773                               neon_uimm3_bare> {
6774   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6775 }
6776
6777 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6778                               neon_uimm2_bare> {
6779   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6780 }
6781
6782 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6783                                        ValueType OpTy,ValueType NaTy,
6784                                        ValueType ExTy, Operand OpLImm,
6785                                        Operand OpNImm> {
6786 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6787         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6788
6789 def : Pat<(ResTy (Neon_vduplane
6790             (NaTy VPR64:$Rn), OpNImm:$Imm)),
6791           (ResTy (DUPELT
6792             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6793 }
6794 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6795                              neon_uimm4_bare, neon_uimm3_bare>;
6796 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6797                              neon_uimm4_bare, neon_uimm3_bare>;
6798 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6799                              neon_uimm3_bare, neon_uimm2_bare>;
6800 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6801                              neon_uimm3_bare, neon_uimm2_bare>;
6802 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6803                              neon_uimm2_bare, neon_uimm1_bare>;
6804 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6805                              neon_uimm2_bare, neon_uimm1_bare>;
6806 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6807                              neon_uimm1_bare, neon_uimm0_bare>;
6808 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6809                              neon_uimm2_bare, neon_uimm1_bare>;
6810 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6811                              neon_uimm2_bare, neon_uimm1_bare>;
6812 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6813                              neon_uimm1_bare, neon_uimm0_bare>;
6814
6815 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6816           (v2f32 (DUPELT2s
6817             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6818             (i64 0)))>;
6819 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6820           (v4f32 (DUPELT4s
6821             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6822             (i64 0)))>;
6823 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6824           (v2f64 (DUPELT2d
6825             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6826             (i64 0)))>;
6827
6828 class NeonI_DUP<bit Q, string asmop, string rdlane,
6829                 RegisterOperand ResVPR, ValueType ResTy,
6830                 RegisterClass OpGPR, ValueType OpTy>
6831   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6832                asmop # "\t$Rd" # rdlane # ", $Rn",
6833                [(set (ResTy ResVPR:$Rd),
6834                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6835                NoItinerary>;
6836
6837 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6838   let Inst{20-16} = 0b00001;
6839   // bits 17-20 are unspecified, but should be set to zero.
6840 }
6841
6842 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6843   let Inst{20-16} = 0b00010;
6844   // bits 18-20 are unspecified, but should be set to zero.
6845 }
6846
6847 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6848   let Inst{20-16} = 0b00100;
6849   // bits 19-20 are unspecified, but should be set to zero.
6850 }
6851
6852 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6853   let Inst{20-16} = 0b01000;
6854   // bit 20 is unspecified, but should be set to zero.
6855 }
6856
6857 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6858   let Inst{20-16} = 0b00001;
6859   // bits 17-20 are unspecified, but should be set to zero.
6860 }
6861
6862 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6863   let Inst{20-16} = 0b00010;
6864   // bits 18-20 are unspecified, but should be set to zero.
6865 }
6866
6867 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6868   let Inst{20-16} = 0b00100;
6869   // bits 19-20 are unspecified, but should be set to zero.
6870 }
6871
6872 // patterns for CONCAT_VECTORS
6873 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6874 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6875           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6876 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6877           (INSELd
6878             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6879             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6880             (i64 1),
6881             (i64 0))>;
6882 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6883           (DUPELT2d
6884             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6885             (i64 0))> ;
6886 }
6887
6888 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6889 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6890 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6891 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6892 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6893 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6894
6895 //patterns for EXTRACT_SUBVECTOR
6896 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6897           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6898 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6899           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6900 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6901           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6902 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6903           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6904 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6905           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6906 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6907           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6908
6909 // The followings are for instruction class (3V Elem)
6910
6911 // Variant 1
6912
6913 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6914              string asmop, string ResS, string OpS, string EleOpS,
6915              Operand OpImm, RegisterOperand ResVPR,
6916              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6917   : NeonI_2VElem<q, u, size, opcode,
6918                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6919                                          EleOpVPR:$Re, OpImm:$Index),
6920                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6921                  ", $Re." # EleOpS # "[$Index]",
6922                  [],
6923                  NoItinerary> {
6924   bits<3> Index;
6925   bits<5> Re;
6926
6927   let Constraints = "$src = $Rd";
6928 }
6929
6930 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6931   // vector register class for element is always 128-bit to cover the max index
6932   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6933                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
6934     let Inst{11} = {Index{1}};
6935     let Inst{21} = {Index{0}};
6936     let Inst{20-16} = Re;
6937   }
6938
6939   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6940                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
6941     let Inst{11} = {Index{1}};
6942     let Inst{21} = {Index{0}};
6943     let Inst{20-16} = Re;
6944   }
6945
6946   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6947   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6948                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6949     let Inst{11} = {Index{2}};
6950     let Inst{21} = {Index{1}};
6951     let Inst{20} = {Index{0}};
6952     let Inst{19-16} = Re{3-0};
6953   }
6954
6955   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6956                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6957     let Inst{11} = {Index{2}};
6958     let Inst{21} = {Index{1}};
6959     let Inst{20} = {Index{0}};
6960     let Inst{19-16} = Re{3-0};
6961   }
6962 }
6963
6964 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6965 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6966
6967 // Pattern for lane in 128-bit vector
6968 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6969                    RegisterOperand ResVPR, RegisterOperand OpVPR,
6970                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6971                    ValueType EleOpTy>
6972   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6973           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6974         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6975
6976 // Pattern for lane in 64-bit vector
6977 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6978                   RegisterOperand ResVPR, RegisterOperand OpVPR,
6979                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6980                   ValueType EleOpTy>
6981   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6982           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6983         (INST ResVPR:$src, OpVPR:$Rn,
6984           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6985
6986 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6987 {
6988   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6989                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
6990
6991   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6992                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
6993
6994   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6995                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6996
6997   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6998                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6999
7000   // Index can only be half of the max value for lane in 64-bit vector
7001
7002   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7003                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
7004
7005   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7006                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7007 }
7008
7009 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
7010 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
7011
7012 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
7013                  string asmop, string ResS, string OpS, string EleOpS,
7014                  Operand OpImm, RegisterOperand ResVPR,
7015                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7016   : NeonI_2VElem<q, u, size, opcode,
7017                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7018                                          EleOpVPR:$Re, OpImm:$Index),
7019                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7020                  ", $Re." # EleOpS # "[$Index]",
7021                  [],
7022                  NoItinerary> {
7023   bits<3> Index;
7024   bits<5> Re;
7025 }
7026
7027 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7028   // vector register class for element is always 128-bit to cover the max index
7029   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7030                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7031     let Inst{11} = {Index{1}};
7032     let Inst{21} = {Index{0}};
7033     let Inst{20-16} = Re;
7034   }
7035
7036   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7037                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7038     let Inst{11} = {Index{1}};
7039     let Inst{21} = {Index{0}};
7040     let Inst{20-16} = Re;
7041   }
7042
7043   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7044   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7045                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7046     let Inst{11} = {Index{2}};
7047     let Inst{21} = {Index{1}};
7048     let Inst{20} = {Index{0}};
7049     let Inst{19-16} = Re{3-0};
7050   }
7051
7052   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7053                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7054     let Inst{11} = {Index{2}};
7055     let Inst{21} = {Index{1}};
7056     let Inst{20} = {Index{0}};
7057     let Inst{19-16} = Re{3-0};
7058   }
7059 }
7060
7061 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7062 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7063 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7064
7065 // Pattern for lane in 128-bit vector
7066 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7067                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7068                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7069   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7070           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7071         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7072
7073 // Pattern for lane in 64-bit vector
7074 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7075                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7076                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7077   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7078           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7079         (INST OpVPR:$Rn,
7080           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7081
7082 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7083   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7084                          op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7085
7086   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7087                          op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7088
7089   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7090                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7091
7092   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7093                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7094
7095   // Index can only be half of the max value for lane in 64-bit vector
7096
7097   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7098                         op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7099
7100   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7101                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7102 }
7103
7104 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7105 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7106 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7107
7108 // Variant 2
7109
7110 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7111   // vector register class for element is always 128-bit to cover the max index
7112   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7113                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7114     let Inst{11} = {Index{1}};
7115     let Inst{21} = {Index{0}};
7116     let Inst{20-16} = Re;
7117   }
7118
7119   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7120                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7121     let Inst{11} = {Index{1}};
7122     let Inst{21} = {Index{0}};
7123     let Inst{20-16} = Re;
7124   }
7125
7126   // _1d2d doesn't exist!
7127
7128   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7129                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
7130     let Inst{11} = {Index{0}};
7131     let Inst{21} = 0b0;
7132     let Inst{20-16} = Re;
7133   }
7134 }
7135
7136 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7137 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7138
7139 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7140                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7141                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7142                          SDPatternOperator coreop>
7143   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7144           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7145         (INST OpVPR:$Rn,
7146           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7147
7148 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7149   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7150                          op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7151
7152   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7153                          op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7154
7155   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7156                          op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7157
7158   // Index can only be half of the max value for lane in 64-bit vector
7159
7160   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7161                         op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7162
7163   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7164                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
7165                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7166 }
7167
7168 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7169 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7170
7171 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7172                        (v2f32 VPR64:$Rn))),
7173           (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7174
7175 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7176                        (v4f32 VPR128:$Rn))),
7177           (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7178
7179 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7180                        (v2f64 VPR128:$Rn))),
7181           (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7182
7183 // The followings are patterns using fma
7184 // -ffp-contract=fast generates fma
7185
7186 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7187   // vector register class for element is always 128-bit to cover the max index
7188   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7189                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7190     let Inst{11} = {Index{1}};
7191     let Inst{21} = {Index{0}};
7192     let Inst{20-16} = Re;
7193   }
7194
7195   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7196                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7197     let Inst{11} = {Index{1}};
7198     let Inst{21} = {Index{0}};
7199     let Inst{20-16} = Re;
7200   }
7201
7202   // _1d2d doesn't exist!
7203
7204   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7205                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
7206     let Inst{11} = {Index{0}};
7207     let Inst{21} = 0b0;
7208     let Inst{20-16} = Re;
7209   }
7210 }
7211
7212 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7213 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7214
7215 // Pattern for lane in 128-bit vector
7216 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7217                        RegisterOperand ResVPR, RegisterOperand OpVPR,
7218                        ValueType ResTy, ValueType OpTy,
7219                        SDPatternOperator coreop>
7220   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7221                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
7222         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7223
7224 // Pattern for lane 0
7225 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7226                       RegisterOperand ResVPR, ValueType ResTy>
7227   : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7228                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7229                    (ResTy ResVPR:$src))),
7230         (INST ResVPR:$src, ResVPR:$Rn,
7231               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7232
7233 // Pattern for lane in 64-bit vector
7234 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7235                       RegisterOperand ResVPR, RegisterOperand OpVPR,
7236                       ValueType ResTy, ValueType OpTy,
7237                       SDPatternOperator coreop>
7238   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7239                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7240         (INST ResVPR:$src, ResVPR:$Rn,
7241           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7242
7243 // Pattern for lane in 64-bit vector
7244 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7245                            SDPatternOperator op,
7246                            RegisterOperand ResVPR, RegisterOperand OpVPR,
7247                            ValueType ResTy, ValueType OpTy,
7248                            SDPatternOperator coreop>
7249   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7250                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7251         (INST ResVPR:$src, ResVPR:$Rn,
7252           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7253
7254
7255 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7256   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7257                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7258                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7259
7260   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7261                         op, VPR64, v2f32>;
7262
7263   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7264                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7265                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7266
7267   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7268                         op, VPR128, v4f32>;
7269
7270   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7271                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7272                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7273
7274   // Index can only be half of the max value for lane in 64-bit vector
7275
7276   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7277                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7278                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7279
7280   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7281                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7282                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7283 }
7284
7285 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7286
7287 // Pattern for lane 0
7288 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7289                       RegisterOperand ResVPR, ValueType ResTy>
7290   : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7291                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7292                    (ResTy ResVPR:$src))),
7293         (INST ResVPR:$src, ResVPR:$Rn,
7294               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7295
7296 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7297 {
7298   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7299                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7300                          BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7301
7302   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7303                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7304                          BinOpFrag<(Neon_vduplane
7305                                      (fneg node:$LHS), node:$RHS)>>;
7306
7307   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7308                         op, VPR64, v2f32>;
7309
7310   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7311                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7312                          BinOpFrag<(fneg (Neon_vduplane
7313                                      node:$LHS, node:$RHS))>>;
7314
7315   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7316                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7317                          BinOpFrag<(Neon_vduplane
7318                                      (fneg node:$LHS), node:$RHS)>>;
7319
7320   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7321                         op, VPR128, v4f32>;
7322
7323   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7324                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7325                          BinOpFrag<(fneg (Neon_vduplane
7326                                      node:$LHS, node:$RHS))>>;
7327
7328   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7329                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7330                          BinOpFrag<(Neon_vduplane
7331                                      (fneg node:$LHS), node:$RHS)>>;
7332
7333   // Index can only be half of the max value for lane in 64-bit vector
7334
7335   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7336                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7337                         BinOpFrag<(fneg (Neon_vduplane
7338                                     node:$LHS, node:$RHS))>>;
7339
7340   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7341                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7342                         BinOpFrag<(Neon_vduplane
7343                                     (fneg node:$LHS), node:$RHS)>>;
7344
7345   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7346                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7347                         BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7348
7349   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7350                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7351                         BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7352
7353   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7354                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7355                              BinOpFrag<(fneg (Neon_combine_2d
7356                                          node:$LHS, node:$RHS))>>;
7357
7358   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7359                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7360                              BinOpFrag<(Neon_combine_2d
7361                                          (fneg node:$LHS), (fneg node:$RHS))>>;
7362 }
7363
7364 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7365
7366 // Variant 3: Long type
7367 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7368 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7369
7370 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7371   // vector register class for element is always 128-bit to cover the max index
7372   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7373                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
7374     let Inst{11} = {Index{1}};
7375     let Inst{21} = {Index{0}};
7376     let Inst{20-16} = Re;
7377   }
7378
7379   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7380                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7381     let Inst{11} = {Index{1}};
7382     let Inst{21} = {Index{0}};
7383     let Inst{20-16} = Re;
7384   }
7385
7386   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7387   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7388                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7389     let Inst{11} = {Index{2}};
7390     let Inst{21} = {Index{1}};
7391     let Inst{20} = {Index{0}};
7392     let Inst{19-16} = Re{3-0};
7393   }
7394
7395   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7396                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7397     let Inst{11} = {Index{2}};
7398     let Inst{21} = {Index{1}};
7399     let Inst{20} = {Index{0}};
7400     let Inst{19-16} = Re{3-0};
7401   }
7402 }
7403
7404 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7405 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7406 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7407 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7408 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7409 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7410
7411 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7412   // vector register class for element is always 128-bit to cover the max index
7413   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7414                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
7415     let Inst{11} = {Index{1}};
7416     let Inst{21} = {Index{0}};
7417     let Inst{20-16} = Re;
7418   }
7419
7420   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7421                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7422     let Inst{11} = {Index{1}};
7423     let Inst{21} = {Index{0}};
7424     let Inst{20-16} = Re;
7425   }
7426
7427   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7428   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7429                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7430     let Inst{11} = {Index{2}};
7431     let Inst{21} = {Index{1}};
7432     let Inst{20} = {Index{0}};
7433     let Inst{19-16} = Re{3-0};
7434   }
7435
7436   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7437                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7438     let Inst{11} = {Index{2}};
7439     let Inst{21} = {Index{1}};
7440     let Inst{20} = {Index{0}};
7441     let Inst{19-16} = Re{3-0};
7442   }
7443 }
7444
7445 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7446 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7447 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7448
7449 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7450           (FMOVdd $src)>;
7451
7452 // Pattern for lane in 128-bit vector
7453 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7454                      RegisterOperand EleOpVPR, ValueType ResTy,
7455                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7456                      SDPatternOperator hiop>
7457   : Pat<(ResTy (op (ResTy VPR128:$src),
7458           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7459           (HalfOpTy (Neon_vduplane
7460                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7461         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7462
7463 // Pattern for lane in 64-bit vector
7464 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7465                     RegisterOperand EleOpVPR, ValueType ResTy,
7466                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7467                     SDPatternOperator hiop>
7468   : Pat<(ResTy (op (ResTy VPR128:$src),
7469           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7470           (HalfOpTy (Neon_vduplane
7471                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7472         (INST VPR128:$src, VPR128:$Rn,
7473           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7474
7475 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7476                      ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7477                      SDPatternOperator hiop, Instruction DupInst>
7478   : Pat<(ResTy (op (ResTy VPR128:$src),
7479           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7480           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7481         (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7482
7483 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7484   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7485                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7486
7487   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7488                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7489
7490   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7491                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7492
7493   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7494                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7495
7496   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7497                        op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7498
7499   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7500                        op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7501
7502   // Index can only be half of the max value for lane in 64-bit vector
7503
7504   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7505                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7506
7507   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7508                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7509
7510   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7511                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7512
7513   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7514                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7515 }
7516
7517 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7518 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7519 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7520 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7521
7522 // Pattern for lane in 128-bit vector
7523 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7524                          RegisterOperand EleOpVPR, ValueType ResTy,
7525                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7526                          SDPatternOperator hiop>
7527   : Pat<(ResTy (op
7528           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7529           (HalfOpTy (Neon_vduplane
7530                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7531         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7532
7533 // Pattern for lane in 64-bit vector
7534 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7535                         RegisterOperand EleOpVPR, ValueType ResTy,
7536                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7537                         SDPatternOperator hiop>
7538   : Pat<(ResTy (op
7539           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7540           (HalfOpTy (Neon_vduplane
7541                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7542         (INST VPR128:$Rn,
7543           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7544
7545 // Pattern for fixed lane 0
7546 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7547                          ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7548                          SDPatternOperator hiop, Instruction DupInst>
7549   : Pat<(ResTy (op
7550           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7551           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7552         (INST VPR128:$Rn, (DupInst $Re), 0)>;
7553
7554 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7555   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7556                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7557
7558   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7559                          op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7560
7561   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7562                          op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7563
7564   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7565                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7566
7567   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7568                            op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7569
7570   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7571                            op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7572
7573   // Index can only be half of the max value for lane in 64-bit vector
7574
7575   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7576                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7577
7578   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7579                         op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7580
7581   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7582                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7583
7584   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7585                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7586 }
7587
7588 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7589 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7590 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7591
7592 multiclass NI_qdma<SDPatternOperator op> {
7593   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7594                     (op node:$Ra,
7595                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7596
7597   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7598                     (op node:$Ra,
7599                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7600 }
7601
7602 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7603 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7604
7605 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7606   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7607                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7608                      v4i32, v4i16, v8i16>;
7609
7610   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7611                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7612                      v2i64, v2i32, v4i32>;
7613
7614   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7615                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
7616                        v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7617
7618   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7619                        !cast<PatFrag>(op # "_2d"), VPR128,
7620                        v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7621
7622   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7623                        !cast<PatFrag>(op # "_4s"),
7624                        v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7625
7626   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7627                        !cast<PatFrag>(op # "_2d"),
7628                        v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7629
7630   // Index can only be half of the max value for lane in 64-bit vector
7631
7632   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7633                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7634                     v4i32, v4i16, v4i16>;
7635
7636   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7637                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7638                     v2i64, v2i32, v2i32>;
7639
7640   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7641                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
7642                       v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7643
7644   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7645                       !cast<PatFrag>(op # "_2d"), VPR64,
7646                       v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7647 }
7648
7649 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7650 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7651
7652 // End of implementation for instruction class (3V Elem)
7653
7654 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7655                 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7656                 SDPatternOperator Neon_Rev>
7657   : NeonI_2VMisc<Q, U, size, opcode,
7658                (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7659                asmop # "\t$Rd." # Res # ", $Rn." # Res,
7660                [(set (ResTy ResVPR:$Rd),
7661                   (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7662                NoItinerary> ;
7663
7664 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7665                           v16i8, Neon_rev64>;
7666 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7667                          v8i16, Neon_rev64>;
7668 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7669                          v4i32, Neon_rev64>;
7670 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7671                          v8i8, Neon_rev64>;
7672 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7673                          v4i16, Neon_rev64>;
7674 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7675                          v2i32, Neon_rev64>;
7676
7677 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7678 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7679
7680 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7681                           v16i8, Neon_rev32>;
7682 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7683                           v8i16, Neon_rev32>;
7684 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7685                          v8i8, Neon_rev32>;
7686 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7687                          v4i16, Neon_rev32>;
7688
7689 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7690                           v16i8, Neon_rev16>;
7691 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7692                          v8i8, Neon_rev16>;
7693
7694 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7695                              SDPatternOperator Neon_Padd> {
7696   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7697                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7698                            asmop # "\t$Rd.8h, $Rn.16b",
7699                            [(set (v8i16 VPR128:$Rd),
7700                               (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7701                            NoItinerary>;
7702
7703   def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7704                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7705                           asmop # "\t$Rd.4h, $Rn.8b",
7706                           [(set (v4i16 VPR64:$Rd),
7707                              (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7708                           NoItinerary>;
7709
7710   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7711                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7712                            asmop # "\t$Rd.4s, $Rn.8h",
7713                            [(set (v4i32 VPR128:$Rd),
7714                               (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7715                            NoItinerary>;
7716
7717   def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7718                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7719                           asmop # "\t$Rd.2s, $Rn.4h",
7720                           [(set (v2i32 VPR64:$Rd),
7721                              (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7722                           NoItinerary>;
7723
7724   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7725                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7726                            asmop # "\t$Rd.2d, $Rn.4s",
7727                            [(set (v2i64 VPR128:$Rd),
7728                               (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7729                            NoItinerary>;
7730
7731   def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7732                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7733                           asmop # "\t$Rd.1d, $Rn.2s",
7734                           [(set (v1i64 VPR64:$Rd),
7735                              (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7736                           NoItinerary>;
7737 }
7738
7739 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7740                                 int_arm_neon_vpaddls>;
7741 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7742                                 int_arm_neon_vpaddlu>;
7743
7744 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7745           (SADDLP2s1d $Rn)>;
7746 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7747           (UADDLP2s1d $Rn)>;
7748
7749 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7750                              SDPatternOperator Neon_Padd> {
7751   let Constraints = "$src = $Rd" in {
7752     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7753                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7754                              asmop # "\t$Rd.8h, $Rn.16b",
7755                              [(set (v8i16 VPR128:$Rd),
7756                                 (v8i16 (Neon_Padd
7757                                   (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7758                              NoItinerary>;
7759
7760     def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7761                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7762                             asmop # "\t$Rd.4h, $Rn.8b",
7763                             [(set (v4i16 VPR64:$Rd),
7764                                (v4i16 (Neon_Padd
7765                                  (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7766                             NoItinerary>;
7767
7768     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7769                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7770                             asmop # "\t$Rd.4s, $Rn.8h",
7771                             [(set (v4i32 VPR128:$Rd),
7772                                (v4i32 (Neon_Padd
7773                                  (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7774                             NoItinerary>;
7775
7776     def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7777                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7778                             asmop # "\t$Rd.2s, $Rn.4h",
7779                             [(set (v2i32 VPR64:$Rd),
7780                                (v2i32 (Neon_Padd
7781                                  (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7782                             NoItinerary>;
7783
7784     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7785                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7786                             asmop # "\t$Rd.2d, $Rn.4s",
7787                             [(set (v2i64 VPR128:$Rd),
7788                                (v2i64 (Neon_Padd
7789                                  (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7790                             NoItinerary>;
7791
7792     def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7793                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7794                             asmop # "\t$Rd.1d, $Rn.2s",
7795                             [(set (v1i64 VPR64:$Rd),
7796                                (v1i64 (Neon_Padd
7797                                  (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7798                             NoItinerary>;
7799   }
7800 }
7801
7802 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7803                                    int_arm_neon_vpadals>;
7804 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7805                                    int_arm_neon_vpadalu>;
7806
7807 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7808   def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7809                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7810                          asmop # "\t$Rd.16b, $Rn.16b",
7811                          [], NoItinerary>;
7812
7813   def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7814                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7815                         asmop # "\t$Rd.8h, $Rn.8h",
7816                         [], NoItinerary>;
7817
7818   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7819                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7820                         asmop # "\t$Rd.4s, $Rn.4s",
7821                         [], NoItinerary>;
7822
7823   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7824                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7825                         asmop # "\t$Rd.2d, $Rn.2d",
7826                         [], NoItinerary>;
7827
7828   def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7829                          (outs VPR64:$Rd), (ins VPR64:$Rn),
7830                          asmop # "\t$Rd.8b, $Rn.8b",
7831                          [], NoItinerary>;
7832
7833   def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7834                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7835                         asmop # "\t$Rd.4h, $Rn.4h",
7836                         [], NoItinerary>;
7837
7838   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7839                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7840                         asmop # "\t$Rd.2s, $Rn.2s",
7841                         [], NoItinerary>;
7842 }
7843
7844 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7845 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7846 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7847 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7848
7849 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7850                                           SDPatternOperator Neon_Op> {
7851   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7852             (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7853
7854   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7855             (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7856
7857   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7858             (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7859
7860   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7861             (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7862
7863   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7864             (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7865
7866   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7867             (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7868
7869   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7870             (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7871 }
7872
7873 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7874 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7875 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7876
7877 def : Pat<(v16i8 (sub
7878             (v16i8 Neon_AllZero),
7879             (v16i8 VPR128:$Rn))),
7880           (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7881 def : Pat<(v8i8 (sub
7882             (v8i8 Neon_AllZero),
7883             (v8i8 VPR64:$Rn))),
7884           (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7885 def : Pat<(v8i16 (sub
7886             (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7887             (v8i16 VPR128:$Rn))),
7888           (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7889 def : Pat<(v4i16 (sub
7890             (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7891             (v4i16 VPR64:$Rn))),
7892           (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7893 def : Pat<(v4i32 (sub
7894             (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7895             (v4i32 VPR128:$Rn))),
7896           (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7897 def : Pat<(v2i32 (sub
7898             (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7899             (v2i32 VPR64:$Rn))),
7900           (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7901 def : Pat<(v2i64 (sub
7902             (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7903             (v2i64 VPR128:$Rn))),
7904           (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7905
7906 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7907   let Constraints = "$src = $Rd" in {
7908     def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7909                            (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7910                            asmop # "\t$Rd.16b, $Rn.16b",
7911                            [], NoItinerary>;
7912
7913     def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7914                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7915                           asmop # "\t$Rd.8h, $Rn.8h",
7916                           [], NoItinerary>;
7917
7918     def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7919                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7920                           asmop # "\t$Rd.4s, $Rn.4s",
7921                           [], NoItinerary>;
7922
7923     def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7924                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7925                           asmop # "\t$Rd.2d, $Rn.2d",
7926                           [], NoItinerary>;
7927
7928     def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7929                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7930                           asmop # "\t$Rd.8b, $Rn.8b",
7931                           [], NoItinerary>;
7932
7933     def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7934                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7935                           asmop # "\t$Rd.4h, $Rn.4h",
7936                           [], NoItinerary>;
7937
7938     def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7939                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7940                           asmop # "\t$Rd.2s, $Rn.2s",
7941                           [], NoItinerary>;
7942   }
7943 }
7944
7945 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7946 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7947
7948 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7949                                            SDPatternOperator Neon_Op> {
7950   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7951             (v16i8 (!cast<Instruction>(Prefix # 16b)
7952               (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7953
7954   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7955             (v8i16 (!cast<Instruction>(Prefix # 8h)
7956               (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7957
7958   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7959             (v4i32 (!cast<Instruction>(Prefix # 4s)
7960               (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7961
7962   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7963             (v2i64 (!cast<Instruction>(Prefix # 2d)
7964               (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7965
7966   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7967             (v8i8 (!cast<Instruction>(Prefix # 8b)
7968               (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7969
7970   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7971             (v4i16 (!cast<Instruction>(Prefix # 4h)
7972               (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7973
7974   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7975             (v2i32 (!cast<Instruction>(Prefix # 2s)
7976               (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7977 }
7978
7979 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7980 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7981
7982 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7983                           SDPatternOperator Neon_Op> {
7984   def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7985                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7986                          asmop # "\t$Rd.16b, $Rn.16b",
7987                          [(set (v16i8 VPR128:$Rd),
7988                             (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7989                          NoItinerary>;
7990
7991   def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7992                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7993                         asmop # "\t$Rd.8h, $Rn.8h",
7994                         [(set (v8i16 VPR128:$Rd),
7995                            (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7996                         NoItinerary>;
7997
7998   def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7999                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8000                         asmop # "\t$Rd.4s, $Rn.4s",
8001                         [(set (v4i32 VPR128:$Rd),
8002                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8003                         NoItinerary>;
8004
8005   def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
8006                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8007                         asmop # "\t$Rd.8b, $Rn.8b",
8008                         [(set (v8i8 VPR64:$Rd),
8009                            (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
8010                         NoItinerary>;
8011
8012   def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8013                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8014                         asmop # "\t$Rd.4h, $Rn.4h",
8015                         [(set (v4i16 VPR64:$Rd),
8016                            (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8017                         NoItinerary>;
8018
8019   def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8020                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8021                         asmop # "\t$Rd.2s, $Rn.2s",
8022                         [(set (v2i32 VPR64:$Rd),
8023                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8024                         NoItinerary>;
8025 }
8026
8027 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8028 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8029
8030 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8031                               bits<5> Opcode> {
8032   def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8033                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8034                          asmop # "\t$Rd.16b, $Rn.16b",
8035                          [], NoItinerary>;
8036
8037   def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8038                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8039                         asmop # "\t$Rd.8b, $Rn.8b",
8040                         [], NoItinerary>;
8041 }
8042
8043 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8044 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8045 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8046
8047 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8048                     (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8049 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8050                     (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8051
8052 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8053           (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8054 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8055           (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8056
8057 def : Pat<(v16i8 (xor
8058             (v16i8 VPR128:$Rn),
8059             (v16i8 Neon_AllOne))),
8060           (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8061 def : Pat<(v8i8 (xor
8062             (v8i8 VPR64:$Rn),
8063             (v8i8 Neon_AllOne))),
8064           (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8065 def : Pat<(v8i16 (xor
8066             (v8i16 VPR128:$Rn),
8067             (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8068           (NOT16b VPR128:$Rn)>;
8069 def : Pat<(v4i16 (xor
8070             (v4i16 VPR64:$Rn),
8071             (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8072           (NOT8b VPR64:$Rn)>;
8073 def : Pat<(v4i32 (xor
8074             (v4i32 VPR128:$Rn),
8075             (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8076           (NOT16b VPR128:$Rn)>;
8077 def : Pat<(v2i32 (xor
8078             (v2i32 VPR64:$Rn),
8079             (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8080           (NOT8b VPR64:$Rn)>;
8081 def : Pat<(v2i64 (xor
8082             (v2i64 VPR128:$Rn),
8083             (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8084           (NOT16b VPR128:$Rn)>;
8085
8086 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8087           (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8088 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8089           (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8090
8091 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8092                                 SDPatternOperator Neon_Op> {
8093   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8094                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8095                         asmop # "\t$Rd.4s, $Rn.4s",
8096                         [(set (v4f32 VPR128:$Rd),
8097                            (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8098                         NoItinerary>;
8099
8100   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8101                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8102                         asmop # "\t$Rd.2d, $Rn.2d",
8103                         [(set (v2f64 VPR128:$Rd),
8104                            (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8105                         NoItinerary>;
8106
8107   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8108                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8109                         asmop # "\t$Rd.2s, $Rn.2s",
8110                         [(set (v2f32 VPR64:$Rd),
8111                            (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8112                         NoItinerary>;
8113 }
8114
8115 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8116 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8117
8118 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8119   def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8120                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8121                           asmop # "\t$Rd.8b, $Rn.8h",
8122                           [], NoItinerary>;
8123
8124   def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8125                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8126                           asmop # "\t$Rd.4h, $Rn.4s",
8127                           [], NoItinerary>;
8128
8129   def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8130                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8131                           asmop # "\t$Rd.2s, $Rn.2d",
8132                           [], NoItinerary>;
8133
8134   let Constraints = "$Rd = $src" in {
8135     def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8136                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8137                              asmop # "2\t$Rd.16b, $Rn.8h",
8138                              [], NoItinerary>;
8139
8140     def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8141                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8142                             asmop # "2\t$Rd.8h, $Rn.4s",
8143                             [], NoItinerary>;
8144
8145     def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8146                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8147                             asmop # "2\t$Rd.4s, $Rn.2d",
8148                             [], NoItinerary>;
8149   }
8150 }
8151
8152 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8153 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8154 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8155 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8156
8157 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8158                                         SDPatternOperator Neon_Op> {
8159   def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8160             (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8161
8162   def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8163             (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8164
8165   def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8166             (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8167
8168   def : Pat<(v16i8 (concat_vectors
8169               (v8i8 VPR64:$src),
8170               (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8171             (!cast<Instruction>(Prefix # 8h16b)
8172               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8173               VPR128:$Rn)>;
8174
8175   def : Pat<(v8i16 (concat_vectors
8176               (v4i16 VPR64:$src),
8177               (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8178             (!cast<Instruction>(Prefix # 4s8h)
8179               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8180               VPR128:$Rn)>;
8181
8182   def : Pat<(v4i32 (concat_vectors
8183               (v2i32 VPR64:$src),
8184               (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8185             (!cast<Instruction>(Prefix # 2d4s)
8186               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8187               VPR128:$Rn)>;
8188 }
8189
8190 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8191 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8192 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8193 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8194
8195 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8196   let DecoderMethod = "DecodeSHLLInstruction" in {
8197     def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8198                             (outs VPR128:$Rd),
8199                             (ins VPR64:$Rn, uimm_exact8:$Imm),
8200                             asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8201                             [], NoItinerary>;
8202
8203     def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8204                             (outs VPR128:$Rd),
8205                             (ins VPR64:$Rn, uimm_exact16:$Imm),
8206                             asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8207                             [], NoItinerary>;
8208
8209     def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8210                             (outs VPR128:$Rd),
8211                             (ins VPR64:$Rn, uimm_exact32:$Imm),
8212                             asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8213                             [], NoItinerary>;
8214
8215     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8216                             (outs VPR128:$Rd),
8217                             (ins VPR128:$Rn, uimm_exact8:$Imm),
8218                             asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8219                             [], NoItinerary>;
8220
8221     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8222                             (outs VPR128:$Rd),
8223                             (ins VPR128:$Rn, uimm_exact16:$Imm),
8224                             asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8225                             [], NoItinerary>;
8226
8227     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8228                             (outs VPR128:$Rd),
8229                             (ins VPR128:$Rn, uimm_exact32:$Imm),
8230                             asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8231                             [], NoItinerary>;
8232   }
8233 }
8234
8235 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8236
8237 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8238                           SDPatternOperator ExtOp, Operand Neon_Imm,
8239                           string suffix>
8240   : Pat<(DesTy (shl
8241           (DesTy (ExtOp (OpTy VPR64:$Rn))),
8242             (DesTy (Neon_vdup
8243               (i32 Neon_Imm:$Imm))))),
8244         (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8245
8246 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8247                                SDPatternOperator ExtOp, Operand Neon_Imm,
8248                                string suffix, PatFrag GetHigh>
8249   : Pat<(DesTy (shl
8250           (DesTy (ExtOp
8251             (OpTy (GetHigh VPR128:$Rn)))),
8252               (DesTy (Neon_vdup
8253                 (i32 Neon_Imm:$Imm))))),
8254         (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8255
8256 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8257 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8258 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8259 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8260 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8261 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8262 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8263                                Neon_High16B>;
8264 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8265                                Neon_High16B>;
8266 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8267                                Neon_High8H>;
8268 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8269                                Neon_High8H>;
8270 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8271                                Neon_High4S>;
8272 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8273                                Neon_High4S>;
8274
8275 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8276   def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8277                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8278                           asmop # "\t$Rd.4h, $Rn.4s",
8279                           [], NoItinerary>;
8280
8281   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8282                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8283                           asmop # "\t$Rd.2s, $Rn.2d",
8284                           [], NoItinerary>;
8285
8286   let Constraints = "$src = $Rd" in {
8287     def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8288                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8289                             asmop # "2\t$Rd.8h, $Rn.4s",
8290                             [], NoItinerary>;
8291
8292     def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8293                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8294                             asmop # "2\t$Rd.4s, $Rn.2d",
8295                             [], NoItinerary>;
8296   }
8297 }
8298
8299 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8300
8301 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8302                                        SDPatternOperator f32_to_f16_Op,
8303                                        SDPatternOperator f64_to_f32_Op> {
8304
8305   def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8306               (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8307
8308   def : Pat<(v8i16 (concat_vectors
8309                 (v4i16 VPR64:$src),
8310                 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8311                   (!cast<Instruction>(prefix # "4s8h")
8312                     (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8313                     (v4f32 VPR128:$Rn))>;
8314
8315   def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8316             (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8317
8318   def : Pat<(v4f32 (concat_vectors
8319               (v2f32 VPR64:$src),
8320               (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8321                 (!cast<Instruction>(prefix # "2d4s")
8322                   (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8323                   (v2f64 VPR128:$Rn))>;
8324 }
8325
8326 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8327
8328 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8329                                  bits<5> opcode> {
8330   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8331                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8332                           asmop # "\t$Rd.2s, $Rn.2d",
8333                           [], NoItinerary>;
8334
8335   def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8336                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8337                           asmop # "2\t$Rd.4s, $Rn.2d",
8338                           [], NoItinerary> {
8339     let Constraints = "$src = $Rd";
8340   }
8341
8342   def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8343             (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8344
8345   def : Pat<(v4f32 (concat_vectors
8346               (v2f32 VPR64:$src),
8347               (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8348             (!cast<Instruction>(prefix # "2d4s")
8349                (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8350                VPR128:$Rn)>;
8351 }
8352
8353 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8354
8355 def Neon_High4Float : PatFrag<(ops node:$in),
8356                               (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8357
8358 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8359   def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8360                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8361                           asmop # "\t$Rd.4s, $Rn.4h",
8362                           [], NoItinerary>;
8363
8364   def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8365                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8366                           asmop # "\t$Rd.2d, $Rn.2s",
8367                           [], NoItinerary>;
8368
8369   def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8370                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8371                           asmop # "2\t$Rd.4s, $Rn.8h",
8372                           [], NoItinerary>;
8373
8374   def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8375                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8376                           asmop # "2\t$Rd.2d, $Rn.4s",
8377                           [], NoItinerary>;
8378 }
8379
8380 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8381
8382 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8383   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8384             (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8385
8386   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8387               (v4i16 (Neon_High8H
8388                 (v8i16 VPR128:$Rn))))),
8389             (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8390
8391   def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8392             (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8393
8394   def : Pat<(v2f64 (fextend
8395               (v2f32 (Neon_High4Float
8396                 (v4f32 VPR128:$Rn))))),
8397             (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8398 }
8399
8400 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8401
8402 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8403                                 ValueType ResTy4s, ValueType OpTy4s,
8404                                 ValueType ResTy2d, ValueType OpTy2d,
8405                                 ValueType ResTy2s, ValueType OpTy2s,
8406                                 SDPatternOperator Neon_Op> {
8407
8408   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8409                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8410                         asmop # "\t$Rd.4s, $Rn.4s",
8411                         [(set (ResTy4s VPR128:$Rd),
8412                            (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8413                         NoItinerary>;
8414
8415   def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8416                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8417                         asmop # "\t$Rd.2d, $Rn.2d",
8418                         [(set (ResTy2d VPR128:$Rd),
8419                            (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8420                         NoItinerary>;
8421
8422   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8423                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8424                         asmop # "\t$Rd.2s, $Rn.2s",
8425                         [(set (ResTy2s VPR64:$Rd),
8426                            (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8427                         NoItinerary>;
8428 }
8429
8430 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8431                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8432   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8433                                 v2f64, v2i32, v2f32, Neon_Op>;
8434 }
8435
8436 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8437                                      int_arm_neon_vcvtns>;
8438 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8439                                      int_arm_neon_vcvtnu>;
8440 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8441                                      int_arm_neon_vcvtps>;
8442 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8443                                      int_arm_neon_vcvtpu>;
8444 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8445                                      int_arm_neon_vcvtms>;
8446 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8447                                      int_arm_neon_vcvtmu>;
8448 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8449 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8450 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8451                                      int_arm_neon_vcvtas>;
8452 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8453                                      int_arm_neon_vcvtau>;
8454
8455 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8456                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8457   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8458                                 v2i64, v2f32, v2i32, Neon_Op>;
8459 }
8460
8461 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8462 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8463
8464 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8465                                  bits<5> opcode, SDPatternOperator Neon_Op> {
8466   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8467                                 v2f64, v2f32, v2f32, Neon_Op>;
8468 }
8469
8470 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8471                                      int_aarch64_neon_frintn>;
8472 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8473 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8474 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8475 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8476 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8477 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8478 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8479                                     int_arm_neon_vrecpe>;
8480 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8481                                      int_arm_neon_vrsqrte>;
8482 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8483
8484 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8485                                bits<5> opcode, SDPatternOperator Neon_Op> {
8486   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8487                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8488                         asmop # "\t$Rd.4s, $Rn.4s",
8489                         [(set (v4i32 VPR128:$Rd),
8490                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8491                         NoItinerary>;
8492
8493   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8494                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8495                         asmop # "\t$Rd.2s, $Rn.2s",
8496                         [(set (v2i32 VPR64:$Rd),
8497                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8498                         NoItinerary>;
8499 }
8500
8501 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8502                                   int_arm_neon_vrecpe>;
8503 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8504                                    int_arm_neon_vrsqrte>;
8505
8506 // Crypto Class
8507 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8508                          string asmop, SDPatternOperator opnode>
8509   : NeonI_Crypto_AES<size, opcode,
8510                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8511                      asmop # "\t$Rd.16b, $Rn.16b",
8512                      [(set (v16i8 VPR128:$Rd),
8513                         (v16i8 (opnode (v16i8 VPR128:$src),
8514                                        (v16i8 VPR128:$Rn))))],
8515                      NoItinerary>{
8516   let Constraints = "$src = $Rd";
8517   let Predicates = [HasNEON, HasCrypto];
8518 }
8519
8520 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8521 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8522
8523 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8524                       string asmop, SDPatternOperator opnode>
8525   : NeonI_Crypto_AES<size, opcode,
8526                      (outs VPR128:$Rd), (ins VPR128:$Rn),
8527                      asmop # "\t$Rd.16b, $Rn.16b",
8528                      [(set (v16i8 VPR128:$Rd),
8529                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8530                      NoItinerary>;
8531
8532 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8533 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8534
8535 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8536                          string asmop, SDPatternOperator opnode>
8537   : NeonI_Crypto_SHA<size, opcode,
8538                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8539                      asmop # "\t$Rd.4s, $Rn.4s",
8540                      [(set (v4i32 VPR128:$Rd),
8541                         (v4i32 (opnode (v4i32 VPR128:$src),
8542                                        (v4i32 VPR128:$Rn))))],
8543                      NoItinerary> {
8544   let Constraints = "$src = $Rd";
8545   let Predicates = [HasNEON, HasCrypto];
8546 }
8547
8548 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8549                                  int_arm_neon_sha1su1>;
8550 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8551                                    int_arm_neon_sha256su0>;
8552
8553 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8554                          string asmop, SDPatternOperator opnode>
8555   : NeonI_Crypto_SHA<size, opcode,
8556                      (outs FPR32:$Rd), (ins FPR32:$Rn),
8557                      asmop # "\t$Rd, $Rn",
8558                      [(set (v1i32 FPR32:$Rd),
8559                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8560                      NoItinerary> {
8561   let Predicates = [HasNEON, HasCrypto];
8562 }
8563
8564 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8565
8566 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8567                            SDPatternOperator opnode>
8568   : NeonI_Crypto_3VSHA<size, opcode,
8569                        (outs VPR128:$Rd),
8570                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8571                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8572                        [(set (v4i32 VPR128:$Rd),
8573                           (v4i32 (opnode (v4i32 VPR128:$src),
8574                                          (v4i32 VPR128:$Rn),
8575                                          (v4i32 VPR128:$Rm))))],
8576                        NoItinerary> {
8577   let Constraints = "$src = $Rd";
8578   let Predicates = [HasNEON, HasCrypto];
8579 }
8580
8581 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8582                                    int_arm_neon_sha1su0>;
8583 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8584                                      int_arm_neon_sha256su1>;
8585
8586 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8587                            SDPatternOperator opnode>
8588   : NeonI_Crypto_3VSHA<size, opcode,
8589                        (outs FPR128:$Rd),
8590                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8591                        asmop # "\t$Rd, $Rn, $Rm.4s",
8592                        [(set (v4i32 FPR128:$Rd),
8593                           (v4i32 (opnode (v4i32 FPR128:$src),
8594                                          (v4i32 FPR128:$Rn),
8595                                          (v4i32 VPR128:$Rm))))],
8596                        NoItinerary> {
8597   let Constraints = "$src = $Rd";
8598   let Predicates = [HasNEON, HasCrypto];
8599 }
8600
8601 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8602                                    int_arm_neon_sha256h>;
8603 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8604                                     int_arm_neon_sha256h2>;
8605
8606 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8607                            SDPatternOperator opnode>
8608   : NeonI_Crypto_3VSHA<size, opcode,
8609                        (outs FPR128:$Rd),
8610                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8611                        asmop # "\t$Rd, $Rn, $Rm.4s",
8612                        [(set (v4i32 FPR128:$Rd),
8613                           (v4i32 (opnode (v4i32 FPR128:$src),
8614                                          (v1i32 FPR32:$Rn),
8615                                          (v4i32 VPR128:$Rm))))],
8616                        NoItinerary> {
8617   let Constraints = "$src = $Rd";
8618   let Predicates = [HasNEON, HasCrypto];
8619 }
8620
8621 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8622 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8623 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8624
8625 //
8626 // Patterns for handling half-precision values
8627 //
8628
8629 // Convert f16 value coming in as i16 value to f32
8630 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8631           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8632 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8633           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8634
8635 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8636             f32_to_f16 (f32 FPR32:$Rn))))))),
8637           (f32 FPR32:$Rn)>;
8638
8639 // Patterns for vector extract of half-precision FP value in i16 storage type
8640 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8641             (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8642           (FCVTsh (f16 (DUPhv_H
8643             (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8644             neon_uimm2_bare:$Imm)))>;
8645
8646 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8647             (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8648           (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8649
8650 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8651 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8652             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8653             (neon_uimm3_bare:$Imm))),
8654           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8655             (v8i16 (SUBREG_TO_REG (i64 0),
8656               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8657               sub_16)),
8658             neon_uimm3_bare:$Imm, 0))>;
8659
8660 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8661             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8662             (neon_uimm2_bare:$Imm))),
8663           (v4i16 (EXTRACT_SUBREG
8664             (v8i16 (INSELh
8665               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8666               (v8i16 (SUBREG_TO_REG (i64 0),
8667                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8668                 sub_16)),
8669               neon_uimm2_bare:$Imm, 0)),
8670             sub_64))>;
8671
8672 // Patterns for vector insert of half-precision FP value in i16 storage type
8673 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8674             (i32 (assertsext (i32 (fp_to_sint
8675               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8676             (neon_uimm3_bare:$Imm))),
8677           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8678             (v8i16 (SUBREG_TO_REG (i64 0),
8679               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8680               sub_16)),
8681             neon_uimm3_bare:$Imm, 0))>;
8682
8683 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8684             (i32 (assertsext (i32 (fp_to_sint
8685               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8686             (neon_uimm2_bare:$Imm))),
8687           (v4i16 (EXTRACT_SUBREG
8688             (v8i16 (INSELh
8689               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8690               (v8i16 (SUBREG_TO_REG (i64 0),
8691                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8692                 sub_16)),
8693               neon_uimm2_bare:$Imm, 0)),
8694             sub_64))>;
8695
8696 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8697             (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8698               (neon_uimm3_bare:$Imm1))),
8699           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8700             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8701
8702 // Patterns for vector copy of half-precision FP value in i16 storage type
8703 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8704             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8705               (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8706               65535)))))))),
8707             (neon_uimm3_bare:$Imm1))),
8708           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8709             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8710
8711 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8712             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8713               (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8714               65535)))))))),
8715             (neon_uimm3_bare:$Imm1))),
8716           (v4i16 (EXTRACT_SUBREG
8717             (v8i16 (INSELh
8718               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8719               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8720               neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),
8721             sub_64))>;
8722
8723