lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17
  18 // (outs Result), (ins Imm, OpCmode)
  19 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  20
  21 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  22
  23 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  24
  25 // (outs Result), (ins Imm)
  26 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  27                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  28
  29 // (outs Result), (ins LHS, RHS, CondCode)
  30 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  31                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  32
  33 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  34 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  35                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  36
  37 // (outs Result), (ins LHS, RHS)
  38 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  39                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  40
  41 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  42                                      SDTCisVT<2, i32>]>;
  43 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  44 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  45
  46 def SDTPERMUTE : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  47                                SDTCisSameAs<0, 2>]>;
  48 def Neon_uzp1    : SDNode<"AArch64ISD::NEON_UZP1", SDTPERMUTE>;
  49 def Neon_uzp2    : SDNode<"AArch64ISD::NEON_UZP2", SDTPERMUTE>;
  50 def Neon_zip1    : SDNode<"AArch64ISD::NEON_ZIP1", SDTPERMUTE>;
  51 def Neon_zip2    : SDNode<"AArch64ISD::NEON_ZIP2", SDTPERMUTE>;
  52 def Neon_trn1    : SDNode<"AArch64ISD::NEON_TRN1", SDTPERMUTE>;
  53 def Neon_trn2    : SDNode<"AArch64ISD::NEON_TRN2", SDTPERMUTE>;
  54
  55 def SDTVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
  56 def Neon_rev64    : SDNode<"AArch64ISD::NEON_REV64", SDTVSHUF>;
  57 def Neon_rev32    : SDNode<"AArch64ISD::NEON_REV32", SDTVSHUF>;
  58 def Neon_rev16    : SDNode<"AArch64ISD::NEON_REV16", SDTVSHUF>;
  59 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  60                        [SDTCisVec<0>]>>;
  61 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  62                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  63 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  64                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  65                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  66
  67 def SDT_assertext : SDTypeProfile<1, 1,
  68   [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
  69 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
  70 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
  71
  72 //===----------------------------------------------------------------------===//
  73 // Multiclasses
  74 //===----------------------------------------------------------------------===//
  75
  76 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  77                                 string asmop, SDPatternOperator opnode8B,
  78                                 SDPatternOperator opnode16B,
  79                                 bit Commutable = 0> {
  80   let isCommutable = Commutable in {
  81     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  82                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  83                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  84                [(set (v8i8 VPR64:$Rd),
  85                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  86                NoItinerary>;
  87
  88     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  89                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  90                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  91                [(set (v16i8 VPR128:$Rd),
  92                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  93                NoItinerary>;
  94   }
  95
  96 }
  97
  98 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
  99                                   string asmop, SDPatternOperator opnode,
 100                                   bit Commutable = 0> {
 101   let isCommutable = Commutable in {
 102     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
 103               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 104               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
 105               [(set (v4i16 VPR64:$Rd),
 106                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
 107               NoItinerary>;
 108
 109     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
 110               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 111               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
 112               [(set (v8i16 VPR128:$Rd),
 113                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
 114               NoItinerary>;
 115
 116     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 117               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 118               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 119               [(set (v2i32 VPR64:$Rd),
 120                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 121               NoItinerary>;
 122
 123     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 124               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 125               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 126               [(set (v4i32 VPR128:$Rd),
 127                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 128               NoItinerary>;
 129   }
 130 }
 131 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 132                                   string asmop, SDPatternOperator opnode,
 133                                   bit Commutable = 0>
 134    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 135   let isCommutable = Commutable in {
 136     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 137                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 138                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 139                [(set (v8i8 VPR64:$Rd),
 140                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 141                NoItinerary>;
 142
 143     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 144                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 145                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 146                [(set (v16i8 VPR128:$Rd),
 147                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 148                NoItinerary>;
 149   }
 150 }
 151
 152 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 153                                    string asmop, SDPatternOperator opnode,
 154                                    bit Commutable = 0>
 155    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 156   let isCommutable = Commutable in {
 157     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 158               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 159               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 160               [(set (v2i64 VPR128:$Rd),
 161                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 162               NoItinerary>;
 163   }
 164 }
 165
 166 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 167 // but Result types can be integer or floating point types.
 168 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 169                                  string asmop, SDPatternOperator opnode2S,
 170                                  SDPatternOperator opnode4S,
 171                                  SDPatternOperator opnode2D,
 172                                  ValueType ResTy2S, ValueType ResTy4S,
 173                                  ValueType ResTy2D, bit Commutable = 0> {
 174   let isCommutable = Commutable in {
 175     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 176               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 177               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 178               [(set (ResTy2S VPR64:$Rd),
 179                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 180               NoItinerary>;
 181
 182     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 183               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 184               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 185               [(set (ResTy4S VPR128:$Rd),
 186                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 187               NoItinerary>;
 188
 189     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 190               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 191               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 192               [(set (ResTy2D VPR128:$Rd),
 193                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 194                NoItinerary>;
 195   }
 196 }
 197
 198 //===----------------------------------------------------------------------===//
 199 // Instruction Definitions
 200 //===----------------------------------------------------------------------===//
 201
 202 // Vector Arithmetic Instructions
 203
 204 // Vector Add (Integer and Floating-Point)
 205
 206 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 207 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 208                                      v2f32, v4f32, v2f64, 1>;
 209
 210 // Vector Sub (Integer and Floating-Point)
 211
 212 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 213 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 214                                      v2f32, v4f32, v2f64, 0>;
 215
 216 // Vector Multiply (Integer and Floating-Point)
 217
 218 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 219 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 220                                      v2f32, v4f32, v2f64, 1>;
 221
 222 // Vector Multiply (Polynomial)
 223
 224 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 225                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 226
 227 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 228
 229 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 230 // two operands constraints.
 231 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 232   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 233   bits<5> opcode, SDPatternOperator opnode>
 234   : NeonI_3VSame<q, u, size, opcode,
 235     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 236     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 237     [(set (OpTy VPRC:$Rd),
 238        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 239     NoItinerary> {
 240   let Constraints = "$src = $Rd";
 241 }
 242
 243 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 244                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 245
 246 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 247                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 248
 249
 250 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 251                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 252 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 253                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 254 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 255                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 256 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 257                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 258 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 259                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 260 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 261                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 262
 263 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 264                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 265 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 266                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 267 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 268                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 269 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 270                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 271 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 272                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 273 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 274                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 275
 276 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 277
 278 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 279                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 280
 281 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 282                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 283
 284 let Predicates = [HasNEON, UseFusedMAC] in {
 285 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 286                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 287 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 288                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 289 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 290                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 291
 292 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 293                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 294 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 295                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 296 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 297                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 298 }
 299
 300 // We're also allowed to match the fma instruction regardless of compile
 301 // options.
 302 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 303           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 304 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 305           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 306 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 307           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 308
 309 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 310           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 311 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 312           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 313 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 314           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 315
 316 // Vector Divide (Floating-Point)
 317
 318 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 319                                      v2f32, v4f32, v2f64, 0>;
 320
 321 // Vector Bitwise Operations
 322
 323 // Vector Bitwise AND
 324
 325 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 326
 327 // Vector Bitwise Exclusive OR
 328
 329 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 330
 331 // Vector Bitwise OR
 332
 333 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 334
 335 // ORR disassembled as MOV if Vn==Vm
 336
 337 // Vector Move - register
 338 // Alias for ORR if Vn=Vm.
 339 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 340 // custom printing of aliases.
 341 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 342                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 343 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 344                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 345
 346 // The MOVI instruction takes two immediate operands.  The first is the
 347 // immediate encoding, while the second is the cmode.  A cmode of 14, or
 348 // 0b1110, produces a MOVI operation, rather than a MVNI, ORR, or BIC.
 349 def Neon_AllZero : PatFrag<(ops), (Neon_movi (i32 0), (i32 14))>;
 350 def Neon_AllOne : PatFrag<(ops), (Neon_movi (i32 255), (i32 14))>;
 351
 352 def Neon_not8B  : PatFrag<(ops node:$in),
 353                           (xor node:$in, (bitconvert (v8i8 Neon_AllOne)))>;
 354 def Neon_not16B : PatFrag<(ops node:$in),
 355                           (xor node:$in, (bitconvert (v16i8 Neon_AllOne)))>;
 356
 357 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 358                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 359
 360 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 361                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 362
 363 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 364                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 365
 366 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 367                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 368
 369
 370 // Vector Bitwise OR NOT - register
 371
 372 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 373                                    Neon_orn8B, Neon_orn16B, 0>;
 374
 375 // Vector Bitwise Bit Clear (AND NOT) - register
 376
 377 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 378                                    Neon_bic8B, Neon_bic16B, 0>;
 379
 380 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 381                                    SDPatternOperator opnode16B,
 382                                    Instruction INST8B,
 383                                    Instruction INST16B> {
 384   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 385             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 386   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 387             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 388   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 389             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 390   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 391             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 392   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 393             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 394   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 395             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 396 }
 397
 398 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 399 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 400 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 401 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 402 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 403 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 404
 405 //   Vector Bitwise Select
 406 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 407                                               0b0, 0b1, 0b01, 0b00011, vselect>;
 408
 409 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 410                                               0b1, 0b1, 0b01, 0b00011, vselect>;
 411
 412 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 413                                    Instruction INST8B,
 414                                    Instruction INST16B> {
 415   // Disassociate type from instruction definition
 416   def : Pat<(v8i8 (opnode (v8i8 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 417             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 418   def : Pat<(v2i32 (opnode (v2i32 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 419             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 420   def : Pat<(v4i16 (opnode (v4i16 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 421             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 422   def : Pat<(v1i64 (opnode (v1i64 VPR64:$src), VPR64:$Rn, VPR64:$Rm)),
 423             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 424   def : Pat<(v16i8 (opnode (v16i8 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 425             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 426   def : Pat<(v4i32 (opnode (v4i32 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 427             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 428   def : Pat<(v8i16 (opnode (v8i16 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 429             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 430   def : Pat<(v2i64 (opnode (v2i64 VPR128:$src), VPR128:$Rn, VPR128:$Rm)),
 431             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 432
 433   // Allow to match BSL instruction pattern with non-constant operand
 434   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 435                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 436           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 437   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 438                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 439           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 440   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 441                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 442           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 443   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 444                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 445           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 446   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 447                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 448           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 449   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 450                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 451           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 452   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 453                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 454           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 455   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 456                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 457           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 458
 459   // Allow to match llvm.arm.* intrinsics.
 460   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 461                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 462             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 463   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 464                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 465             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 466   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 467                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 468             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 469   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 470                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 471             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 472   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 473                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 474             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 475   def : Pat<(v1f64 (int_arm_neon_vbsl (v1f64 VPR64:$src),
 476                     (v1f64 VPR64:$Rn), (v1f64 VPR64:$Rm))),
 477             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 478   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 479                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 480             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 481   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 482                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 483             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 484   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 485                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 486             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 487   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 488                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 489             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 490   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 491                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 492             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 493   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 494                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 495             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 496 }
 497
 498 // Additional patterns for bitwise instruction BSL
 499 defm: Neon_bitwise3V_patterns<vselect, BSLvvv_8B, BSLvvv_16B>;
 500
 501 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 502                            (vselect node:$src, node:$Rn, node:$Rm),
 503                            [{ (void)N; return false; }]>;
 504
 505 // Vector Bitwise Insert if True
 506
 507 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 508                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 509 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 510                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 511
 512 // Vector Bitwise Insert if False
 513
 514 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 515                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 516 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 517                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 518
 519 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 520
 521 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 522                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 523 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 524                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 525
 526 // Vector Absolute Difference and Accumulate (Unsigned)
 527 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 528                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 529 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 530                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 531 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 532                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 533 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 534                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 535 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 536                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 537 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 538                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 539
 540 // Vector Absolute Difference and Accumulate (Signed)
 541 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 542                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 543 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 544                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 545 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 546                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 547 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 548                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 549 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 550                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 551 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 552                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 553
 554
 555 // Vector Absolute Difference (Signed, Unsigned)
 556 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 557 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 558
 559 // Vector Absolute Difference (Floating Point)
 560 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 561                                     int_arm_neon_vabds, int_arm_neon_vabds,
 562                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 563
 564 // Vector Reciprocal Step (Floating Point)
 565 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 566                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 567                                        int_arm_neon_vrecps,
 568                                        v2f32, v4f32, v2f64, 0>;
 569
 570 // Vector Reciprocal Square Root Step (Floating Point)
 571 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 572                                         int_arm_neon_vrsqrts,
 573                                         int_arm_neon_vrsqrts,
 574                                         int_arm_neon_vrsqrts,
 575                                         v2f32, v4f32, v2f64, 0>;
 576
 577 // Vector Comparisons
 578
 579 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 580                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 581 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 582                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 583 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 584                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 585 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 586                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 587 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 588                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 589
 590 // NeonI_compare_aliases class: swaps register operands to implement
 591 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 592 class NeonI_compare_aliases<string asmop, string asmlane,
 593                             Instruction inst, RegisterOperand VPRC>
 594   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 595                     ", $Rm" # asmlane,
 596                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 597
 598 // Vector Comparisons (Integer)
 599
 600 // Vector Compare Mask Equal (Integer)
 601 let isCommutable =1 in {
 602 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 603 }
 604
 605 // Vector Compare Mask Higher or Same (Unsigned Integer)
 606 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 607
 608 // Vector Compare Mask Greater Than or Equal (Integer)
 609 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 610
 611 // Vector Compare Mask Higher (Unsigned Integer)
 612 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 613
 614 // Vector Compare Mask Greater Than (Integer)
 615 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 616
 617 // Vector Compare Mask Bitwise Test (Integer)
 618 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 619
 620 // Vector Compare Mask Less or Same (Unsigned Integer)
 621 // CMLS is alias for CMHS with operands reversed.
 622 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 623 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 624 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 625 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 626 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 627 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 628 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 629
 630 // Vector Compare Mask Less Than or Equal (Integer)
 631 // CMLE is alias for CMGE with operands reversed.
 632 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 633 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 634 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 635 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 636 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 637 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 638 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 639
 640 // Vector Compare Mask Lower (Unsigned Integer)
 641 // CMLO is alias for CMHI with operands reversed.
 642 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 643 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 644 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 645 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 646 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 647 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 648 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 649
 650 // Vector Compare Mask Less Than (Integer)
 651 // CMLT is alias for CMGT with operands reversed.
 652 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 653 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 654 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 655 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 656 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 657 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 658 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 659
 660
 661 def neon_uimm0_asmoperand : AsmOperandClass
 662 {
 663   let Name = "UImm0";
 664   let PredicateMethod = "isUImm<0>";
 665   let RenderMethod = "addImmOperands";
 666 }
 667
 668 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 669   let ParserMatchClass = neon_uimm0_asmoperand;
 670   let PrintMethod = "printNeonUImm0Operand";
 671
 672 }
 673
 674 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 675 {
 676   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 677              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 678              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 679              [(set (v8i8 VPR64:$Rd),
 680                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 681              NoItinerary>;
 682
 683   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 684              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 685              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 686              [(set (v16i8 VPR128:$Rd),
 687                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 688              NoItinerary>;
 689
 690   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 691             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 692             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 693             [(set (v4i16 VPR64:$Rd),
 694                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 695             NoItinerary>;
 696
 697   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 698             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 699             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 700             [(set (v8i16 VPR128:$Rd),
 701                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 702             NoItinerary>;
 703
 704   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 705             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 706             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 707             [(set (v2i32 VPR64:$Rd),
 708                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 709             NoItinerary>;
 710
 711   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 712             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 713             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 714             [(set (v4i32 VPR128:$Rd),
 715                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 716             NoItinerary>;
 717
 718   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 719             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 720             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 721             [(set (v2i64 VPR128:$Rd),
 722                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 723             NoItinerary>;
 724 }
 725
 726 // Vector Compare Mask Equal to Zero (Integer)
 727 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 728
 729 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 730 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 731
 732 // Vector Compare Mask Greater Than Zero (Signed Integer)
 733 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 734
 735 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 736 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 737
 738 // Vector Compare Mask Less Than Zero (Signed Integer)
 739 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 740
 741 // Vector Comparisons (Floating Point)
 742
 743 // Vector Compare Mask Equal (Floating Point)
 744 let isCommutable =1 in {
 745 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 746                                       Neon_cmeq, Neon_cmeq,
 747                                       v2i32, v4i32, v2i64, 0>;
 748 }
 749
 750 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 751 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 752                                       Neon_cmge, Neon_cmge,
 753                                       v2i32, v4i32, v2i64, 0>;
 754
 755 // Vector Compare Mask Greater Than (Floating Point)
 756 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 757                                       Neon_cmgt, Neon_cmgt,
 758                                       v2i32, v4i32, v2i64, 0>;
 759
 760 // Vector Compare Mask Less Than Or Equal (Floating Point)
 761 // FCMLE is alias for FCMGE with operands reversed.
 762 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 763 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 764 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 765
 766 // Vector Compare Mask Less Than (Floating Point)
 767 // FCMLT is alias for FCMGT with operands reversed.
 768 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 769 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 770 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 771
 772
 773 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 774                               string asmop, CondCode CC>
 775 {
 776   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 777             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 778             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 779             [(set (v2i32 VPR64:$Rd),
 780                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpz32:$FPImm), CC)))],
 781             NoItinerary>;
 782
 783   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 784             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 785             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 786             [(set (v4i32 VPR128:$Rd),
 787                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 788             NoItinerary>;
 789
 790   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 791             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 792             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 793             [(set (v2i64 VPR128:$Rd),
 794                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpz32:$FPImm), CC)))],
 795             NoItinerary>;
 796 }
 797
 798 // Vector Compare Mask Equal to Zero (Floating Point)
 799 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 800
 801 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 802 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 803
 804 // Vector Compare Mask Greater Than Zero (Floating Point)
 805 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 806
 807 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 808 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 809
 810 // Vector Compare Mask Less Than Zero (Floating Point)
 811 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 812
 813 // Vector Absolute Comparisons (Floating Point)
 814
 815 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 816 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 817                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 818                                       int_aarch64_neon_vacgeq,
 819                                       v2i32, v4i32, v2i64, 0>;
 820
 821 // Vector Absolute Compare Mask Greater Than (Floating Point)
 822 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 823                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 824                                       int_aarch64_neon_vacgtq,
 825                                       v2i32, v4i32, v2i64, 0>;
 826
 827 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 828 // FACLE is alias for FACGE with operands reversed.
 829 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 830 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 831 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 832
 833 // Vector Absolute Compare Mask Less Than (Floating Point)
 834 // FACLT is alias for FACGT with operands reversed.
 835 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 836 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 837 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 838
 839 // Vector halving add (Integer Signed, Unsigned)
 840 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 841                                         int_arm_neon_vhadds, 1>;
 842 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 843                                         int_arm_neon_vhaddu, 1>;
 844
 845 // Vector halving sub (Integer Signed, Unsigned)
 846 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 847                                         int_arm_neon_vhsubs, 0>;
 848 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 849                                         int_arm_neon_vhsubu, 0>;
 850
 851 // Vector rouding halving add (Integer Signed, Unsigned)
 852 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 853                                          int_arm_neon_vrhadds, 1>;
 854 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 855                                          int_arm_neon_vrhaddu, 1>;
 856
 857 // Vector Saturating add (Integer Signed, Unsigned)
 858 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 859                    int_arm_neon_vqadds, 1>;
 860 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 861                    int_arm_neon_vqaddu, 1>;
 862
 863 // Vector Saturating sub (Integer Signed, Unsigned)
 864 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 865                    int_arm_neon_vqsubs, 1>;
 866 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 867                    int_arm_neon_vqsubu, 1>;
 868
 869 // Vector Shift Left (Signed and Unsigned Integer)
 870 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 871                  int_arm_neon_vshifts, 1>;
 872 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 873                  int_arm_neon_vshiftu, 1>;
 874
 875 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 876 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 877                   int_arm_neon_vqshifts, 1>;
 878 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 879                   int_arm_neon_vqshiftu, 1>;
 880
 881 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 882 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 883                   int_arm_neon_vrshifts, 1>;
 884 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 885                   int_arm_neon_vrshiftu, 1>;
 886
 887 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 888 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 889                    int_arm_neon_vqrshifts, 1>;
 890 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 891                    int_arm_neon_vqrshiftu, 1>;
 892
 893 // Vector Maximum (Signed and Unsigned Integer)
 894 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 895 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 896
 897 // Vector Minimum (Signed and Unsigned Integer)
 898 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 899 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 900
 901 // Vector Maximum (Floating Point)
 902 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 903                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 904                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 905
 906 // Vector Minimum (Floating Point)
 907 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 908                                      int_arm_neon_vmins, int_arm_neon_vmins,
 909                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 910
 911 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 912 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 913                                        int_aarch64_neon_vmaxnm,
 914                                        int_aarch64_neon_vmaxnm,
 915                                        int_aarch64_neon_vmaxnm,
 916                                        v2f32, v4f32, v2f64, 1>;
 917
 918 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 919 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 920                                        int_aarch64_neon_vminnm,
 921                                        int_aarch64_neon_vminnm,
 922                                        int_aarch64_neon_vminnm,
 923                                        v2f32, v4f32, v2f64, 1>;
 924
 925 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 926 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 927 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 928
 929 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 930 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 931 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 932
 933 // Vector Maximum Pairwise (Floating Point)
 934 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 935                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 936                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 937
 938 // Vector Minimum Pairwise (Floating Point)
 939 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 940                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 941                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 942
 943 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 944 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 945                                        int_aarch64_neon_vpmaxnm,
 946                                        int_aarch64_neon_vpmaxnm,
 947                                        int_aarch64_neon_vpmaxnm,
 948                                        v2f32, v4f32, v2f64, 1>;
 949
 950 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 951 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 952                                        int_aarch64_neon_vpminnm,
 953                                        int_aarch64_neon_vpminnm,
 954                                        int_aarch64_neon_vpminnm,
 955                                        v2f32, v4f32, v2f64, 1>;
 956
 957 // Vector Addition Pairwise (Integer)
 958 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 959
 960 // Vector Addition Pairwise (Floating Point)
 961 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 962                                        int_arm_neon_vpadd,
 963                                        int_arm_neon_vpadd,
 964                                        int_arm_neon_vpadd,
 965                                        v2f32, v4f32, v2f64, 1>;
 966
 967 // Vector Saturating Doubling Multiply High
 968 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 969                     int_arm_neon_vqdmulh, 1>;
 970
 971 // Vector Saturating Rouding Doubling Multiply High
 972 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 973                      int_arm_neon_vqrdmulh, 1>;
 974
 975 // Vector Multiply Extended (Floating Point)
 976 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 977                                       int_aarch64_neon_vmulx,
 978                                       int_aarch64_neon_vmulx,
 979                                       int_aarch64_neon_vmulx,
 980                                       v2f32, v4f32, v2f64, 1>;
 981
 982 // Patterns to match llvm.aarch64.* intrinsic for
 983 // ADDP, SMINP, UMINP, SMAXP, UMAXP having i32 as output
 984 class Neon_VectorPair_v2i32_pattern<SDPatternOperator opnode, Instruction INST>
 985   : Pat<(v1i32 (opnode (v2i32 VPR64:$Rn))),
 986         (EXTRACT_SUBREG
 987              (v2i32 (INST (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rn))),
 988              sub_32)>;
 989
 990 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_sminv, SMINPvvv_2S>;
 991 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_uminv, UMINPvvv_2S>;
 992 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_smaxv, SMAXPvvv_2S>;
 993 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_umaxv, UMAXPvvv_2S>;
 994 def : Neon_VectorPair_v2i32_pattern<int_aarch64_neon_vaddv, ADDP_2S>;
 995
 996 // Vector Immediate Instructions
 997
 998 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 999 {
1000   def _asmoperand : AsmOperandClass
1001     {
1002       let Name = "NeonMovImmShift" # PREFIX;
1003       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
1004       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
1005     }
1006 }
1007
1008 // Definition of vector immediates shift operands
1009
1010 // The selectable use-cases extract the shift operation
1011 // information from the OpCmode fields encoded in the immediate.
1012 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
1013   uint64_t OpCmode = N->getZExtValue();
1014   unsigned ShiftImm;
1015   unsigned ShiftOnesIn;
1016   unsigned HasShift =
1017     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1018   if (!HasShift) return SDValue();
1019   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
1020 }]>;
1021
1022 // Vector immediates shift operands which accept LSL and MSL
1023 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1024 // or 0, 8 (LSLH) or 8, 16 (MSL).
1025 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1026 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1027 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1028 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1029
1030 multiclass neon_mov_imm_shift_operands<string PREFIX,
1031                                        string HALF, string ISHALF, code pred>
1032 {
1033    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1034     {
1035       let PrintMethod =
1036         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1037       let DecoderMethod =
1038         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1039       let ParserMatchClass =
1040         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1041     }
1042 }
1043
1044 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1045   unsigned ShiftImm;
1046   unsigned ShiftOnesIn;
1047   unsigned HasShift =
1048     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1049   return (HasShift && !ShiftOnesIn);
1050 }]>;
1051
1052 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1053   unsigned ShiftImm;
1054   unsigned ShiftOnesIn;
1055   unsigned HasShift =
1056     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1057   return (HasShift && ShiftOnesIn);
1058 }]>;
1059
1060 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1061   unsigned ShiftImm;
1062   unsigned ShiftOnesIn;
1063   unsigned HasShift =
1064     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1065   return (HasShift && !ShiftOnesIn);
1066 }]>;
1067
1068 def neon_uimm1_asmoperand : AsmOperandClass
1069 {
1070   let Name = "UImm1";
1071   let PredicateMethod = "isUImm<1>";
1072   let RenderMethod = "addImmOperands";
1073 }
1074
1075 def neon_uimm2_asmoperand : AsmOperandClass
1076 {
1077   let Name = "UImm2";
1078   let PredicateMethod = "isUImm<2>";
1079   let RenderMethod = "addImmOperands";
1080 }
1081
1082 def neon_uimm8_asmoperand : AsmOperandClass
1083 {
1084   let Name = "UImm8";
1085   let PredicateMethod = "isUImm<8>";
1086   let RenderMethod = "addImmOperands";
1087 }
1088
1089 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1090   let ParserMatchClass = neon_uimm8_asmoperand;
1091   let PrintMethod = "printUImmHexOperand";
1092 }
1093
1094 def neon_uimm64_mask_asmoperand : AsmOperandClass
1095 {
1096   let Name = "NeonUImm64Mask";
1097   let PredicateMethod = "isNeonUImm64Mask";
1098   let RenderMethod = "addNeonUImm64MaskOperands";
1099 }
1100
1101 // MCOperand for 64-bit bytemask with each byte having only the
1102 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1103 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1104   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1105   let PrintMethod = "printNeonUImm64MaskOperand";
1106 }
1107
1108 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1109                                    SDPatternOperator opnode>
1110 {
1111     // shift zeros, per word
1112     def _2S  : NeonI_1VModImm<0b0, op,
1113                               (outs VPR64:$Rd),
1114                               (ins neon_uimm8:$Imm,
1115                                 neon_mov_imm_LSL_operand:$Simm),
1116                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1117                               [(set (v2i32 VPR64:$Rd),
1118                                  (v2i32 (opnode (timm:$Imm),
1119                                    (neon_mov_imm_LSL_operand:$Simm))))],
1120                               NoItinerary> {
1121        bits<2> Simm;
1122        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1123      }
1124
1125     def _4S  : NeonI_1VModImm<0b1, op,
1126                               (outs VPR128:$Rd),
1127                               (ins neon_uimm8:$Imm,
1128                                 neon_mov_imm_LSL_operand:$Simm),
1129                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1130                               [(set (v4i32 VPR128:$Rd),
1131                                  (v4i32 (opnode (timm:$Imm),
1132                                    (neon_mov_imm_LSL_operand:$Simm))))],
1133                               NoItinerary> {
1134       bits<2> Simm;
1135       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1136     }
1137
1138     // shift zeros, per halfword
1139     def _4H  : NeonI_1VModImm<0b0, op,
1140                               (outs VPR64:$Rd),
1141                               (ins neon_uimm8:$Imm,
1142                                 neon_mov_imm_LSLH_operand:$Simm),
1143                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1144                               [(set (v4i16 VPR64:$Rd),
1145                                  (v4i16 (opnode (timm:$Imm),
1146                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1147                               NoItinerary> {
1148       bit  Simm;
1149       let cmode = {0b1, 0b0, Simm, 0b0};
1150     }
1151
1152     def _8H  : NeonI_1VModImm<0b1, op,
1153                               (outs VPR128:$Rd),
1154                               (ins neon_uimm8:$Imm,
1155                                 neon_mov_imm_LSLH_operand:$Simm),
1156                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1157                               [(set (v8i16 VPR128:$Rd),
1158                                  (v8i16 (opnode (timm:$Imm),
1159                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1160                               NoItinerary> {
1161       bit Simm;
1162       let cmode = {0b1, 0b0, Simm, 0b0};
1163      }
1164 }
1165
1166 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1167                                                    SDPatternOperator opnode,
1168                                                    SDPatternOperator neonopnode>
1169 {
1170   let Constraints = "$src = $Rd" in {
1171     // shift zeros, per word
1172     def _2S  : NeonI_1VModImm<0b0, op,
1173                  (outs VPR64:$Rd),
1174                  (ins VPR64:$src, neon_uimm8:$Imm,
1175                    neon_mov_imm_LSL_operand:$Simm),
1176                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1177                  [(set (v2i32 VPR64:$Rd),
1178                     (v2i32 (opnode (v2i32 VPR64:$src),
1179                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1180                         neon_mov_imm_LSL_operand:$Simm)))))))],
1181                  NoItinerary> {
1182       bits<2> Simm;
1183       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1184     }
1185
1186     def _4S  : NeonI_1VModImm<0b1, op,
1187                  (outs VPR128:$Rd),
1188                  (ins VPR128:$src, neon_uimm8:$Imm,
1189                    neon_mov_imm_LSL_operand:$Simm),
1190                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1191                  [(set (v4i32 VPR128:$Rd),
1192                     (v4i32 (opnode (v4i32 VPR128:$src),
1193                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1194                         neon_mov_imm_LSL_operand:$Simm)))))))],
1195                  NoItinerary> {
1196       bits<2> Simm;
1197       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1198     }
1199
1200     // shift zeros, per halfword
1201     def _4H  : NeonI_1VModImm<0b0, op,
1202                  (outs VPR64:$Rd),
1203                  (ins VPR64:$src, neon_uimm8:$Imm,
1204                    neon_mov_imm_LSLH_operand:$Simm),
1205                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1206                  [(set (v4i16 VPR64:$Rd),
1207                     (v4i16 (opnode (v4i16 VPR64:$src),
1208                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1209                           neon_mov_imm_LSL_operand:$Simm)))))))],
1210                  NoItinerary> {
1211       bit  Simm;
1212       let cmode = {0b1, 0b0, Simm, 0b1};
1213     }
1214
1215     def _8H  : NeonI_1VModImm<0b1, op,
1216                  (outs VPR128:$Rd),
1217                  (ins VPR128:$src, neon_uimm8:$Imm,
1218                    neon_mov_imm_LSLH_operand:$Simm),
1219                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1220                  [(set (v8i16 VPR128:$Rd),
1221                     (v8i16 (opnode (v8i16 VPR128:$src),
1222                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1223                         neon_mov_imm_LSL_operand:$Simm)))))))],
1224                  NoItinerary> {
1225       bit Simm;
1226       let cmode = {0b1, 0b0, Simm, 0b1};
1227     }
1228   }
1229 }
1230
1231 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1232                                    SDPatternOperator opnode>
1233 {
1234     // shift ones, per word
1235     def _2S  : NeonI_1VModImm<0b0, op,
1236                              (outs VPR64:$Rd),
1237                              (ins neon_uimm8:$Imm,
1238                                neon_mov_imm_MSL_operand:$Simm),
1239                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1240                               [(set (v2i32 VPR64:$Rd),
1241                                  (v2i32 (opnode (timm:$Imm),
1242                                    (neon_mov_imm_MSL_operand:$Simm))))],
1243                              NoItinerary> {
1244        bit Simm;
1245        let cmode = {0b1, 0b1, 0b0, Simm};
1246      }
1247
1248    def _4S  : NeonI_1VModImm<0b1, op,
1249                               (outs VPR128:$Rd),
1250                               (ins neon_uimm8:$Imm,
1251                                 neon_mov_imm_MSL_operand:$Simm),
1252                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1253                               [(set (v4i32 VPR128:$Rd),
1254                                  (v4i32 (opnode (timm:$Imm),
1255                                    (neon_mov_imm_MSL_operand:$Simm))))],
1256                               NoItinerary> {
1257      bit Simm;
1258      let cmode = {0b1, 0b1, 0b0, Simm};
1259    }
1260 }
1261
1262 // Vector Move Immediate Shifted
1263 let isReMaterializable = 1 in {
1264 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1265 }
1266
1267 // Vector Move Inverted Immediate Shifted
1268 let isReMaterializable = 1 in {
1269 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1270 }
1271
1272 // Vector Bitwise Bit Clear (AND NOT) - immediate
1273 let isReMaterializable = 1 in {
1274 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1275                                                          and, Neon_mvni>;
1276 }
1277
1278 // Vector Bitwise OR - immedidate
1279
1280 let isReMaterializable = 1 in {
1281 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1282                                                            or, Neon_movi>;
1283 }
1284
1285 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1286 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1287 // BIC immediate instructions selection requires additional patterns to
1288 // transform Neon_movi operands into BIC immediate operands
1289
1290 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1291   uint64_t OpCmode = N->getZExtValue();
1292   unsigned ShiftImm;
1293   unsigned ShiftOnesIn;
1294   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1295   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1296   // Transform encoded shift amount 0 to 1 and 1 to 0.
1297   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1298 }]>;
1299
1300 def neon_mov_imm_LSLH_transform_operand
1301   : ImmLeaf<i32, [{
1302     unsigned ShiftImm;
1303     unsigned ShiftOnesIn;
1304     unsigned HasShift =
1305       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1306     return (HasShift && !ShiftOnesIn); }],
1307   neon_mov_imm_LSLH_transform_XFORM>;
1308
1309 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1310 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1311 def : Pat<(v4i16 (and VPR64:$src,
1312             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1313           (BICvi_lsl_4H VPR64:$src, 0,
1314             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1315
1316 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1317 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1318 def : Pat<(v8i16 (and VPR128:$src,
1319             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1320           (BICvi_lsl_8H VPR128:$src, 0,
1321             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1322
1323
1324 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1325                                    SDPatternOperator neonopnode,
1326                                    Instruction INST4H,
1327                                    Instruction INST8H> {
1328   def : Pat<(v8i8 (opnode VPR64:$src,
1329                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1330                       neon_mov_imm_LSLH_operand:$Simm))))),
1331             (INST4H VPR64:$src, neon_uimm8:$Imm,
1332               neon_mov_imm_LSLH_operand:$Simm)>;
1333   def : Pat<(v1i64 (opnode VPR64:$src,
1334                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1335                     neon_mov_imm_LSLH_operand:$Simm))))),
1336           (INST4H VPR64:$src, neon_uimm8:$Imm,
1337             neon_mov_imm_LSLH_operand:$Simm)>;
1338
1339   def : Pat<(v16i8 (opnode VPR128:$src,
1340                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1341                      neon_mov_imm_LSLH_operand:$Simm))))),
1342           (INST8H VPR128:$src, neon_uimm8:$Imm,
1343             neon_mov_imm_LSLH_operand:$Simm)>;
1344   def : Pat<(v4i32 (opnode VPR128:$src,
1345                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1346                      neon_mov_imm_LSLH_operand:$Simm))))),
1347           (INST8H VPR128:$src, neon_uimm8:$Imm,
1348             neon_mov_imm_LSLH_operand:$Simm)>;
1349   def : Pat<(v2i64 (opnode VPR128:$src,
1350                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1351                      neon_mov_imm_LSLH_operand:$Simm))))),
1352           (INST8H VPR128:$src, neon_uimm8:$Imm,
1353             neon_mov_imm_LSLH_operand:$Simm)>;
1354 }
1355
1356 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1357 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1358
1359 // Additional patterns for Vector Bitwise OR - immedidate
1360 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1361
1362
1363 // Vector Move Immediate Masked
1364 let isReMaterializable = 1 in {
1365 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1366 }
1367
1368 // Vector Move Inverted Immediate Masked
1369 let isReMaterializable = 1 in {
1370 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1371 }
1372
1373 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1374                                 Instruction inst, RegisterOperand VPRC>
1375   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1376                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1377
1378 // Aliases for Vector Move Immediate Shifted
1379 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1380 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1381 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1382 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1383
1384 // Aliases for Vector Move Inverted Immediate Shifted
1385 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1386 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1387 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1388 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1389
1390 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1391 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1392 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1393 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1394 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1395
1396 // Aliases for Vector Bitwise OR - immedidate
1397 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1398 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1399 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1400 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1401
1402 //  Vector Move Immediate - per byte
1403 let isReMaterializable = 1 in {
1404 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1405                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1406                                "movi\t$Rd.8b, $Imm",
1407                                [(set (v8i8 VPR64:$Rd),
1408                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1409                                 NoItinerary> {
1410   let cmode = 0b1110;
1411 }
1412
1413 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1414                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1415                                 "movi\t$Rd.16b, $Imm",
1416                                 [(set (v16i8 VPR128:$Rd),
1417                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1418                                  NoItinerary> {
1419   let cmode = 0b1110;
1420 }
1421 }
1422
1423 // Vector Move Immediate - bytemask, per double word
1424 let isReMaterializable = 1 in {
1425 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1426                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1427                                "movi\t $Rd.2d, $Imm",
1428                                [(set (v2i64 VPR128:$Rd),
1429                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1430                                NoItinerary> {
1431   let cmode = 0b1110;
1432 }
1433 }
1434
1435 // Vector Move Immediate - bytemask, one doubleword
1436
1437 let isReMaterializable = 1 in {
1438 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1439                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1440                            "movi\t $Rd, $Imm",
1441                            [(set (v1i64 FPR64:$Rd),
1442                              (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1443                            NoItinerary> {
1444   let cmode = 0b1110;
1445 }
1446 }
1447
1448 // Vector Floating Point Move Immediate
1449
1450 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1451                       Operand immOpType, bit q, bit op>
1452   : NeonI_1VModImm<q, op,
1453                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1454                    "fmov\t$Rd" # asmlane # ", $Imm",
1455                    [(set (OpTy VPRC:$Rd),
1456                       (OpTy (Neon_fmovi (timm:$Imm))))],
1457                    NoItinerary> {
1458      let cmode = 0b1111;
1459    }
1460
1461 let isReMaterializable = 1 in {
1462 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1463 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1464 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1465 }
1466
1467 // Vector Shift (Immediate)
1468 // Immediate in [0, 63]
1469 def imm0_63 : Operand<i32> {
1470   let ParserMatchClass = uimm6_asmoperand;
1471 }
1472
1473 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1474 // as follows:
1475 //
1476 //    Offset    Encoding
1477 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1478 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1479 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1480 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1481 //
1482 // The shift right immediate amount, in the range 1 to element bits, is computed
1483 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1484 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1485
1486 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1487   let Name = "ShrImm" # OFFSET;
1488   let RenderMethod = "addImmOperands";
1489   let DiagnosticType = "ShrImm" # OFFSET;
1490 }
1491
1492 class shr_imm<string OFFSET> : Operand<i32> {
1493   let EncoderMethod = "getShiftRightImm" # OFFSET;
1494   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1495   let ParserMatchClass =
1496     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1497 }
1498
1499 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1500 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1501 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1502 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1503
1504 def shr_imm8 : shr_imm<"8">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 8;}]>;
1505 def shr_imm16 : shr_imm<"16">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 16;}]>;
1506 def shr_imm32 : shr_imm<"32">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 32;}]>;
1507 def shr_imm64 : shr_imm<"64">, ImmLeaf<i32, [{return Imm > 0 && Imm <= 64;}]>;
1508
1509 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1510   let Name = "ShlImm" # OFFSET;
1511   let RenderMethod = "addImmOperands";
1512   let DiagnosticType = "ShlImm" # OFFSET;
1513 }
1514
1515 class shl_imm<string OFFSET> : Operand<i32> {
1516   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1517   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1518   let ParserMatchClass =
1519     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1520 }
1521
1522 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1523 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1524 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1525 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1526
1527 def shl_imm8 : shl_imm<"8">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 8;}]>;
1528 def shl_imm16 : shl_imm<"16">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 16;}]>;
1529 def shl_imm32 : shl_imm<"32">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 32;}]>;
1530 def shl_imm64 : shl_imm<"64">, ImmLeaf<i32, [{return Imm >= 0 && Imm < 64;}]>;
1531
1532 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1533                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1534   : NeonI_2VShiftImm<q, u, opcode,
1535                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1536                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1537                      [(set (Ty VPRC:$Rd),
1538                         (Ty (OpNode (Ty VPRC:$Rn),
1539                           (Ty (Neon_vdup (i32 ImmTy:$Imm))))))],
1540                      NoItinerary>;
1541
1542 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1543   // 64-bit vector types.
1544   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8, shl> {
1545     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1546   }
1547
1548   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16, shl> {
1549     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1550   }
1551
1552   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32, shl> {
1553     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1554   }
1555
1556   // 128-bit vector types.
1557   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8, shl> {
1558     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1559   }
1560
1561   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16, shl> {
1562     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1563   }
1564
1565   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32, shl> {
1566     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1567   }
1568
1569   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64, shl> {
1570     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1571   }
1572 }
1573
1574 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1575   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1576                      OpNode> {
1577     let Inst{22-19} = 0b0001;
1578   }
1579
1580   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1581                      OpNode> {
1582     let Inst{22-20} = 0b001;
1583   }
1584
1585   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1586                      OpNode> {
1587      let Inst{22-21} = 0b01;
1588   }
1589
1590   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1591                       OpNode> {
1592                       let Inst{22-19} = 0b0001;
1593                     }
1594
1595   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1596                      OpNode> {
1597                      let Inst{22-20} = 0b001;
1598                     }
1599
1600   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1601                      OpNode> {
1602                       let Inst{22-21} = 0b01;
1603                     }
1604
1605   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1606                      OpNode> {
1607                       let Inst{22} = 0b1;
1608                     }
1609 }
1610
1611 // Shift left
1612 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1613
1614 // Shift right
1615 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1616 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1617
1618 def Neon_High16B : PatFrag<(ops node:$in),
1619                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1620 def Neon_High8H  : PatFrag<(ops node:$in),
1621                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1622 def Neon_High4S  : PatFrag<(ops node:$in),
1623                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1624 def Neon_High2D  : PatFrag<(ops node:$in),
1625                            (extract_subvector (v2i64 node:$in), (iPTR 1))>;
1626 def Neon_High4float : PatFrag<(ops node:$in),
1627                                (extract_subvector (v4f32 node:$in), (iPTR 2))>;
1628 def Neon_High2double : PatFrag<(ops node:$in),
1629                                (extract_subvector (v2f64 node:$in), (iPTR 1))>;
1630
1631 def Neon_Low16B : PatFrag<(ops node:$in),
1632                           (v8i8 (extract_subvector (v16i8 node:$in),
1633                                                    (iPTR 0)))>;
1634 def Neon_Low8H : PatFrag<(ops node:$in),
1635                          (v4i16 (extract_subvector (v8i16 node:$in),
1636                                                    (iPTR 0)))>;
1637 def Neon_Low4S : PatFrag<(ops node:$in),
1638                          (v2i32 (extract_subvector (v4i32 node:$in),
1639                                                    (iPTR 0)))>;
1640 def Neon_Low2D : PatFrag<(ops node:$in),
1641                          (v1i64 (extract_subvector (v2i64 node:$in),
1642                                                    (iPTR 0)))>;
1643 def Neon_Low4float : PatFrag<(ops node:$in),
1644                              (v2f32 (extract_subvector (v4f32 node:$in),
1645                                                        (iPTR 0)))>;
1646 def Neon_Low2double : PatFrag<(ops node:$in),
1647                               (v1f64 (extract_subvector (v2f64 node:$in),
1648                                                         (iPTR 0)))>;
1649
1650 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1651                    string SrcT, ValueType DestTy, ValueType SrcTy,
1652                    Operand ImmTy, SDPatternOperator ExtOp>
1653   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1654                      (ins VPR64:$Rn, ImmTy:$Imm),
1655                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1656                      [(set (DestTy VPR128:$Rd),
1657                         (DestTy (shl
1658                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1659                             (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1660                      NoItinerary>;
1661
1662 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1663                        string SrcT, ValueType DestTy, ValueType SrcTy,
1664                        int StartIndex, Operand ImmTy,
1665                        SDPatternOperator ExtOp, PatFrag getTop>
1666   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1667                      (ins VPR128:$Rn, ImmTy:$Imm),
1668                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1669                      [(set (DestTy VPR128:$Rd),
1670                         (DestTy (shl
1671                           (DestTy (ExtOp
1672                             (SrcTy (getTop VPR128:$Rn)))),
1673                               (DestTy (Neon_vdup (i32 ImmTy:$Imm))))))],
1674                      NoItinerary>;
1675
1676 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1677                          SDNode ExtOp> {
1678   // 64-bit vector types.
1679   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1680                          shl_imm8, ExtOp> {
1681     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1682   }
1683
1684   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1685                          shl_imm16, ExtOp> {
1686     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1687   }
1688
1689   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1690                          shl_imm32, ExtOp> {
1691     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1692   }
1693
1694   // 128-bit vector types
1695   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b", v8i16, v8i8,
1696                               8, shl_imm8, ExtOp, Neon_High16B> {
1697     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1698   }
1699
1700   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h", v4i32, v4i16,
1701                              4, shl_imm16, ExtOp, Neon_High8H> {
1702     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1703   }
1704
1705   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s", v2i64, v2i32,
1706                              2, shl_imm32, ExtOp, Neon_High4S> {
1707     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1708   }
1709
1710   // Use other patterns to match when the immediate is 0.
1711   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1712             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1713
1714   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1715             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1716
1717   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1718             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1719
1720   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1721             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1722
1723   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1724             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1725
1726   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1727             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1728 }
1729
1730 // Shift left long
1731 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1732 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1733
1734 // Rounding/Saturating shift
1735 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1736                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1737                   SDPatternOperator OpNode>
1738   : NeonI_2VShiftImm<q, u, opcode,
1739                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1740                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1741                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1742                         (i32 ImmTy:$Imm))))],
1743                      NoItinerary>;
1744
1745 // shift right (vector by immediate)
1746 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1747                            SDPatternOperator OpNode> {
1748   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1749                          OpNode> {
1750     let Inst{22-19} = 0b0001;
1751   }
1752
1753   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1754                          OpNode> {
1755     let Inst{22-20} = 0b001;
1756   }
1757
1758   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1759                          OpNode> {
1760     let Inst{22-21} = 0b01;
1761   }
1762
1763   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1764                          OpNode> {
1765     let Inst{22-19} = 0b0001;
1766   }
1767
1768   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1769                         OpNode> {
1770     let Inst{22-20} = 0b001;
1771   }
1772
1773   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1774                         OpNode> {
1775     let Inst{22-21} = 0b01;
1776   }
1777
1778   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1779                         OpNode> {
1780     let Inst{22} = 0b1;
1781   }
1782 }
1783
1784 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1785                           SDPatternOperator OpNode> {
1786   // 64-bit vector types.
1787   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1788                         OpNode> {
1789     let Inst{22-19} = 0b0001;
1790   }
1791
1792   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1793                         OpNode> {
1794     let Inst{22-20} = 0b001;
1795   }
1796
1797   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1798                         OpNode> {
1799     let Inst{22-21} = 0b01;
1800   }
1801
1802   // 128-bit vector types.
1803   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1804                          OpNode> {
1805     let Inst{22-19} = 0b0001;
1806   }
1807
1808   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1809                         OpNode> {
1810     let Inst{22-20} = 0b001;
1811   }
1812
1813   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1814                         OpNode> {
1815     let Inst{22-21} = 0b01;
1816   }
1817
1818   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1819                         OpNode> {
1820     let Inst{22} = 0b1;
1821   }
1822 }
1823
1824 // Rounding shift right
1825 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1826                                 int_aarch64_neon_vsrshr>;
1827 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1828                                 int_aarch64_neon_vurshr>;
1829
1830 // Saturating shift left unsigned
1831 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1832
1833 // Saturating shift left
1834 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1835 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1836
1837 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1838                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1839                   SDNode OpNode>
1840   : NeonI_2VShiftImm<q, u, opcode,
1841            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1842            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1843            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1844               (Ty (OpNode (Ty VPRC:$Rn),
1845                 (Ty (Neon_vdup (i32 ImmTy:$Imm))))))))],
1846            NoItinerary> {
1847   let Constraints = "$src = $Rd";
1848 }
1849
1850 // Shift Right accumulate
1851 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1852   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1853                         OpNode> {
1854     let Inst{22-19} = 0b0001;
1855   }
1856
1857   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1858                         OpNode> {
1859     let Inst{22-20} = 0b001;
1860   }
1861
1862   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1863                         OpNode> {
1864     let Inst{22-21} = 0b01;
1865   }
1866
1867   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1868                          OpNode> {
1869     let Inst{22-19} = 0b0001;
1870   }
1871
1872   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1873                         OpNode> {
1874     let Inst{22-20} = 0b001;
1875   }
1876
1877   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1878                         OpNode> {
1879     let Inst{22-21} = 0b01;
1880   }
1881
1882   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1883                         OpNode> {
1884     let Inst{22} = 0b1;
1885   }
1886 }
1887
1888 // Shift right and accumulate
1889 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1890 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1891
1892 // Rounding shift accumulate
1893 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1894                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1895                     SDPatternOperator OpNode>
1896   : NeonI_2VShiftImm<q, u, opcode,
1897                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1898                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1899                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1900                         (Ty (OpNode (Ty VPRC:$Rn), (i32 ImmTy:$Imm))))))],
1901                      NoItinerary> {
1902   let Constraints = "$src = $Rd";
1903 }
1904
1905 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1906                              SDPatternOperator OpNode> {
1907   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1908                           OpNode> {
1909     let Inst{22-19} = 0b0001;
1910   }
1911
1912   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1913                           OpNode> {
1914     let Inst{22-20} = 0b001;
1915   }
1916
1917   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1918                           OpNode> {
1919     let Inst{22-21} = 0b01;
1920   }
1921
1922   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1923                            OpNode> {
1924     let Inst{22-19} = 0b0001;
1925   }
1926
1927   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1928                           OpNode> {
1929     let Inst{22-20} = 0b001;
1930   }
1931
1932   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1933                           OpNode> {
1934     let Inst{22-21} = 0b01;
1935   }
1936
1937   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1938                           OpNode> {
1939     let Inst{22} = 0b1;
1940   }
1941 }
1942
1943 // Rounding shift right and accumulate
1944 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1945 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1946
1947 // Shift insert by immediate
1948 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1949                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1950                   SDPatternOperator OpNode>
1951     : NeonI_2VShiftImm<q, u, opcode,
1952            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1953            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1954            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1955              (i32 ImmTy:$Imm))))],
1956            NoItinerary> {
1957   let Constraints = "$src = $Rd";
1958 }
1959
1960 // shift left insert (vector by immediate)
1961 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1962   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shl_imm8,
1963                         int_aarch64_neon_vsli> {
1964     let Inst{22-19} = 0b0001;
1965   }
1966
1967   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shl_imm16,
1968                         int_aarch64_neon_vsli> {
1969     let Inst{22-20} = 0b001;
1970   }
1971
1972   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shl_imm32,
1973                         int_aarch64_neon_vsli> {
1974     let Inst{22-21} = 0b01;
1975   }
1976
1977     // 128-bit vector types
1978   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shl_imm8,
1979                          int_aarch64_neon_vsli> {
1980     let Inst{22-19} = 0b0001;
1981   }
1982
1983   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shl_imm16,
1984                         int_aarch64_neon_vsli> {
1985     let Inst{22-20} = 0b001;
1986   }
1987
1988   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shl_imm32,
1989                         int_aarch64_neon_vsli> {
1990     let Inst{22-21} = 0b01;
1991   }
1992
1993   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shl_imm64,
1994                         int_aarch64_neon_vsli> {
1995     let Inst{22} = 0b1;
1996   }
1997 }
1998
1999 // shift right insert (vector by immediate)
2000 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
2001     // 64-bit vector types.
2002   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
2003                         int_aarch64_neon_vsri> {
2004     let Inst{22-19} = 0b0001;
2005   }
2006
2007   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
2008                         int_aarch64_neon_vsri> {
2009     let Inst{22-20} = 0b001;
2010   }
2011
2012   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
2013                         int_aarch64_neon_vsri> {
2014     let Inst{22-21} = 0b01;
2015   }
2016
2017     // 128-bit vector types
2018   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
2019                          int_aarch64_neon_vsri> {
2020     let Inst{22-19} = 0b0001;
2021   }
2022
2023   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
2024                         int_aarch64_neon_vsri> {
2025     let Inst{22-20} = 0b001;
2026   }
2027
2028   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
2029                         int_aarch64_neon_vsri> {
2030     let Inst{22-21} = 0b01;
2031   }
2032
2033   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
2034                         int_aarch64_neon_vsri> {
2035     let Inst{22} = 0b1;
2036   }
2037 }
2038
2039 // Shift left and insert
2040 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2041
2042 // Shift right and insert
2043 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2044
2045 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2046                     string SrcT, Operand ImmTy>
2047   : NeonI_2VShiftImm<q, u, opcode,
2048                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2049                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2050                      [], NoItinerary>;
2051
2052 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2053                        string SrcT, Operand ImmTy>
2054   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2055                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2056                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2057                      [], NoItinerary> {
2058   let Constraints = "$src = $Rd";
2059 }
2060
2061 // left long shift by immediate
2062 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2063   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2064     let Inst{22-19} = 0b0001;
2065   }
2066
2067   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2068     let Inst{22-20} = 0b001;
2069   }
2070
2071   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2072     let Inst{22-21} = 0b01;
2073   }
2074
2075   // Shift Narrow High
2076   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2077                               shr_imm8> {
2078     let Inst{22-19} = 0b0001;
2079   }
2080
2081   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2082                              shr_imm16> {
2083     let Inst{22-20} = 0b001;
2084   }
2085
2086   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2087                              shr_imm32> {
2088     let Inst{22-21} = 0b01;
2089   }
2090 }
2091
2092 // Shift right narrow
2093 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2094
2095 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2096 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2097 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2098 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2099 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2100 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2101 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2102 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2103
2104 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2105                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2106                                                      (v1i64 node:$Rn)))>;
2107 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2108                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2109                                                      (v4i16 node:$Rn)))>;
2110 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2111                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2112                                                      (v2i32 node:$Rn)))>;
2113 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2114                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2115                                                      (v2f32 node:$Rn)))>;
2116 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2117                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2118                                                      (v1f64 node:$Rn)))>;
2119
2120 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2121                              (v8i16 (srl (v8i16 node:$lhs),
2122                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2123 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2124                              (v4i32 (srl (v4i32 node:$lhs),
2125                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2126 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2127                              (v2i64 (srl (v2i64 node:$lhs),
2128                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2129 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2130                              (v8i16 (sra (v8i16 node:$lhs),
2131                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2132 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2133                              (v4i32 (sra (v4i32 node:$lhs),
2134                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2135 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2136                              (v2i64 (sra (v2i64 node:$lhs),
2137                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2138
2139 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2140 multiclass Neon_shiftNarrow_patterns<string shr> {
2141   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2142               (i32 shr_imm8:$Imm)))),
2143             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2144   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2145               (i32 shr_imm16:$Imm)))),
2146             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2147   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2148               (i32 shr_imm32:$Imm)))),
2149             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2150
2151   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2152               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2153                 VPR128:$Rn, (i32 shr_imm8:$Imm))))))),
2154             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2155                          VPR128:$Rn, imm:$Imm)>;
2156   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2157               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2158                 VPR128:$Rn, (i32 shr_imm16:$Imm))))))),
2159             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2160                         VPR128:$Rn, imm:$Imm)>;
2161   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2162               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2163                 VPR128:$Rn, (i32 shr_imm32:$Imm))))))),
2164             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2165                         VPR128:$Rn, imm:$Imm)>;
2166 }
2167
2168 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2169   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), shr_imm8:$Imm)),
2170             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2171   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), shr_imm16:$Imm)),
2172             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2173   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), shr_imm32:$Imm)),
2174             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2175
2176   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2177                 (v1i64 (bitconvert (v8i8
2178                     (op (v8i16 VPR128:$Rn), shr_imm8:$Imm))))),
2179             (!cast<Instruction>(prefix # "_16B")
2180                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2181                 VPR128:$Rn, imm:$Imm)>;
2182   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2183                 (v1i64 (bitconvert (v4i16
2184                     (op (v4i32 VPR128:$Rn), shr_imm16:$Imm))))),
2185             (!cast<Instruction>(prefix # "_8H")
2186                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2187                 VPR128:$Rn, imm:$Imm)>;
2188   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2189                 (v1i64 (bitconvert (v2i32
2190                     (op (v2i64 VPR128:$Rn), shr_imm32:$Imm))))),
2191             (!cast<Instruction>(prefix # "_4S")
2192                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2193                   VPR128:$Rn, imm:$Imm)>;
2194 }
2195
2196 defm : Neon_shiftNarrow_patterns<"lshr">;
2197 defm : Neon_shiftNarrow_patterns<"ashr">;
2198
2199 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2200 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2201 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2202 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2203 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2204 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2205 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2206
2207 // Convert fix-point and float-pointing
2208 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2209                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2210                 Operand ImmTy, SDPatternOperator IntOp>
2211   : NeonI_2VShiftImm<q, u, opcode,
2212                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2213                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2214                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2215                        (i32 ImmTy:$Imm))))],
2216                      NoItinerary>;
2217
2218 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2219                               SDPatternOperator IntOp> {
2220   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2221                       shr_imm32, IntOp> {
2222     let Inst{22-21} = 0b01;
2223   }
2224
2225   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2226                       shr_imm32, IntOp> {
2227     let Inst{22-21} = 0b01;
2228   }
2229
2230   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2231                       shr_imm64, IntOp> {
2232     let Inst{22} = 0b1;
2233   }
2234 }
2235
2236 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2237                               SDPatternOperator IntOp> {
2238   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2239                       shr_imm32, IntOp> {
2240     let Inst{22-21} = 0b01;
2241   }
2242
2243   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2244                       shr_imm32, IntOp> {
2245     let Inst{22-21} = 0b01;
2246   }
2247
2248   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2249                       shr_imm64, IntOp> {
2250     let Inst{22} = 0b1;
2251   }
2252 }
2253
2254 // Convert fixed-point to floating-point
2255 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2256                                    int_arm_neon_vcvtfxs2fp>;
2257 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2258                                    int_arm_neon_vcvtfxu2fp>;
2259
2260 // Convert floating-point to fixed-point
2261 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2262                                    int_arm_neon_vcvtfp2fxs>;
2263 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2264                                    int_arm_neon_vcvtfp2fxu>;
2265
2266 multiclass Neon_sshll2_0<SDNode ext>
2267 {
2268   def _v8i8  : PatFrag<(ops node:$Rn),
2269                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2270   def _v4i16 : PatFrag<(ops node:$Rn),
2271                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2272   def _v2i32 : PatFrag<(ops node:$Rn),
2273                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2274 }
2275
2276 defm NI_sext_high : Neon_sshll2_0<sext>;
2277 defm NI_zext_high : Neon_sshll2_0<zext>;
2278
2279
2280 //===----------------------------------------------------------------------===//
2281 // Multiclasses for NeonI_Across
2282 //===----------------------------------------------------------------------===//
2283
2284 // Variant 1
2285
2286 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2287                             string asmop, SDPatternOperator opnode>
2288 {
2289     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2290                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2291                 asmop # "\t$Rd, $Rn.8b",
2292                 [(set (v1i16 FPR16:$Rd),
2293                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2294                 NoItinerary>;
2295
2296     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2297                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2298                 asmop # "\t$Rd, $Rn.16b",
2299                 [(set (v1i16 FPR16:$Rd),
2300                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2301                 NoItinerary>;
2302
2303     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2304                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2305                 asmop # "\t$Rd, $Rn.4h",
2306                 [(set (v1i32 FPR32:$Rd),
2307                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2308                 NoItinerary>;
2309
2310     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2311                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2312                 asmop # "\t$Rd, $Rn.8h",
2313                 [(set (v1i32 FPR32:$Rd),
2314                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2315                 NoItinerary>;
2316
2317     // _1d2s doesn't exist!
2318
2319     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2320                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2321                 asmop # "\t$Rd, $Rn.4s",
2322                 [(set (v1i64 FPR64:$Rd),
2323                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2324                 NoItinerary>;
2325 }
2326
2327 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2328 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2329
2330 // Variant 2
2331
2332 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2333                             string asmop, SDPatternOperator opnode>
2334 {
2335     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2336                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2337                 asmop # "\t$Rd, $Rn.8b",
2338                 [(set (v1i8 FPR8:$Rd),
2339                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2340                 NoItinerary>;
2341
2342     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2343                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2344                 asmop # "\t$Rd, $Rn.16b",
2345                 [(set (v1i8 FPR8:$Rd),
2346                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2347                 NoItinerary>;
2348
2349     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2350                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2351                 asmop # "\t$Rd, $Rn.4h",
2352                 [(set (v1i16 FPR16:$Rd),
2353                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2354                 NoItinerary>;
2355
2356     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2357                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2358                 asmop # "\t$Rd, $Rn.8h",
2359                 [(set (v1i16 FPR16:$Rd),
2360                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2361                 NoItinerary>;
2362
2363     // _1s2s doesn't exist!
2364
2365     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2366                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2367                 asmop # "\t$Rd, $Rn.4s",
2368                 [(set (v1i32 FPR32:$Rd),
2369                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2370                 NoItinerary>;
2371 }
2372
2373 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2374 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2375
2376 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2377 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2378
2379 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2380
2381 // Variant 3
2382
2383 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2384                             string asmop, SDPatternOperator opnode> {
2385     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2386                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2387                 asmop # "\t$Rd, $Rn.4s",
2388                 [(set (f32 FPR32:$Rd),
2389                     (f32 (opnode (v4f32 VPR128:$Rn))))],
2390                 NoItinerary>;
2391 }
2392
2393 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2394                                 int_aarch64_neon_vmaxnmv>;
2395 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2396                                 int_aarch64_neon_vminnmv>;
2397
2398 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2399                               int_aarch64_neon_vmaxv>;
2400 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2401                               int_aarch64_neon_vminv>;
2402
2403 // The followings are for instruction class (Perm)
2404
2405 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2406                     string asmop, RegisterOperand OpVPR, string OpS,
2407                     SDPatternOperator opnode, ValueType Ty>
2408   : NeonI_Perm<q, size, opcode,
2409                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2410                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2411                [(set (Ty OpVPR:$Rd),
2412                   (Ty (opnode (Ty OpVPR:$Rn), (Ty OpVPR:$Rm))))],
2413                NoItinerary>;
2414
2415 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop,
2416                           SDPatternOperator opnode> {
2417   def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop,
2418                            VPR64, "8b", opnode, v8i8>;
2419   def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop,
2420                            VPR128, "16b",opnode, v16i8>;
2421   def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop,
2422                            VPR64, "4h", opnode, v4i16>;
2423   def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop,
2424                            VPR128, "8h", opnode, v8i16>;
2425   def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop,
2426                            VPR64, "2s", opnode, v2i32>;
2427   def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop,
2428                            VPR128, "4s", opnode, v4i32>;
2429   def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop,
2430                            VPR128, "2d", opnode, v2i64>;
2431 }
2432
2433 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1", Neon_uzp1>;
2434 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1", Neon_trn1>;
2435 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1", Neon_zip1>;
2436 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2", Neon_uzp2>;
2437 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2", Neon_trn2>;
2438 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2", Neon_zip2>;
2439
2440 multiclass NeonI_Perm_float_pat<string INS, SDPatternOperator opnode> {
2441   def : Pat<(v2f32 (opnode (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
2442             (!cast<Instruction>(INS # "_2s") VPR64:$Rn, VPR64:$Rm)>;
2443
2444   def : Pat<(v4f32 (opnode (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
2445             (!cast<Instruction>(INS # "_4s") VPR128:$Rn, VPR128:$Rm)>;
2446
2447   def : Pat<(v2f64 (opnode (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
2448             (!cast<Instruction>(INS # "_2d") VPR128:$Rn, VPR128:$Rm)>;
2449 }
2450
2451 defm : NeonI_Perm_float_pat<"UZP1vvv", Neon_uzp1>;
2452 defm : NeonI_Perm_float_pat<"UZP2vvv", Neon_uzp2>;
2453 defm : NeonI_Perm_float_pat<"ZIP1vvv", Neon_zip1>;
2454 defm : NeonI_Perm_float_pat<"ZIP2vvv", Neon_zip2>;
2455 defm : NeonI_Perm_float_pat<"TRN1vvv", Neon_trn1>;
2456 defm : NeonI_Perm_float_pat<"TRN2vvv", Neon_trn2>;
2457
2458 // The followings are for instruction class (3V Diff)
2459
2460 // normal long/long2 pattern
2461 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2462                  string asmop, string ResS, string OpS,
2463                  SDPatternOperator opnode, SDPatternOperator ext,
2464                  RegisterOperand OpVPR,
2465                  ValueType ResTy, ValueType OpTy>
2466   : NeonI_3VDiff<q, u, size, opcode,
2467                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2468                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2469                  [(set (ResTy VPR128:$Rd),
2470                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2471                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2472                  NoItinerary>;
2473
2474 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2475                         string asmop, SDPatternOperator opnode,
2476                         bit Commutable = 0> {
2477   let isCommutable = Commutable in {
2478     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2479                            opnode, sext, VPR64, v8i16, v8i8>;
2480     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2481                            opnode, sext, VPR64, v4i32, v4i16>;
2482     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2483                            opnode, sext, VPR64, v2i64, v2i32>;
2484   }
2485 }
2486
2487 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2488                          SDPatternOperator opnode, bit Commutable = 0> {
2489   let isCommutable = Commutable in {
2490     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2491                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2492     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2493                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2494     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2495                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2496   }
2497 }
2498
2499 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2500                         SDPatternOperator opnode, bit Commutable = 0> {
2501   let isCommutable = Commutable in {
2502     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2503                            opnode, zext, VPR64, v8i16, v8i8>;
2504     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2505                            opnode, zext, VPR64, v4i32, v4i16>;
2506     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2507                            opnode, zext, VPR64, v2i64, v2i32>;
2508   }
2509 }
2510
2511 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2512                          SDPatternOperator opnode, bit Commutable = 0> {
2513   let isCommutable = Commutable in {
2514     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2515                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2516     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2517                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2518     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2519                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2520   }
2521 }
2522
2523 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2524 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2525
2526 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2527 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2528
2529 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2530 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2531
2532 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2533 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2534
2535 // normal wide/wide2 pattern
2536 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2537                  string asmop, string ResS, string OpS,
2538                  SDPatternOperator opnode, SDPatternOperator ext,
2539                  RegisterOperand OpVPR,
2540                  ValueType ResTy, ValueType OpTy>
2541   : NeonI_3VDiff<q, u, size, opcode,
2542                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2543                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2544                  [(set (ResTy VPR128:$Rd),
2545                     (ResTy (opnode (ResTy VPR128:$Rn),
2546                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2547                  NoItinerary>;
2548
2549 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2550                         SDPatternOperator opnode> {
2551   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2552                          opnode, sext, VPR64, v8i16, v8i8>;
2553   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2554                          opnode, sext, VPR64, v4i32, v4i16>;
2555   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2556                          opnode, sext, VPR64, v2i64, v2i32>;
2557 }
2558
2559 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2560 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2561
2562 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2563                          SDPatternOperator opnode> {
2564   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2565                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2566   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2567                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2568   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2569                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2570 }
2571
2572 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2573 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2574
2575 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2576                         SDPatternOperator opnode> {
2577   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2578                          opnode, zext, VPR64, v8i16, v8i8>;
2579   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2580                          opnode, zext, VPR64, v4i32, v4i16>;
2581   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2582                          opnode, zext, VPR64, v2i64, v2i32>;
2583 }
2584
2585 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2586 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2587
2588 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2589                          SDPatternOperator opnode> {
2590   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2591                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2592   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2593                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2594   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2595                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2596 }
2597
2598 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2599 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2600
2601 // Get the high half part of the vector element.
2602 multiclass NeonI_get_high {
2603   def _8h : PatFrag<(ops node:$Rn),
2604                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2605                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2606   def _4s : PatFrag<(ops node:$Rn),
2607                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2608                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2609   def _2d : PatFrag<(ops node:$Rn),
2610                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2611                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2612 }
2613
2614 defm NI_get_hi : NeonI_get_high;
2615
2616 // pattern for addhn/subhn with 2 operands
2617 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2618                            string asmop, string ResS, string OpS,
2619                            SDPatternOperator opnode, SDPatternOperator get_hi,
2620                            ValueType ResTy, ValueType OpTy>
2621   : NeonI_3VDiff<q, u, size, opcode,
2622                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2623                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2624                  [(set (ResTy VPR64:$Rd),
2625                     (ResTy (get_hi
2626                       (OpTy (opnode (OpTy VPR128:$Rn),
2627                                     (OpTy VPR128:$Rm))))))],
2628                  NoItinerary>;
2629
2630 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2631                                 SDPatternOperator opnode, bit Commutable = 0> {
2632   let isCommutable = Commutable in {
2633     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2634                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2635     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2636                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2637     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2638                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2639   }
2640 }
2641
2642 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2643 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2644
2645 // pattern for operation with 2 operands
2646 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2647                     string asmop, string ResS, string OpS,
2648                     SDPatternOperator opnode,
2649                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2650                     ValueType ResTy, ValueType OpTy>
2651   : NeonI_3VDiff<q, u, size, opcode,
2652                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2653                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2654                  [(set (ResTy ResVPR:$Rd),
2655                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2656                  NoItinerary>;
2657
2658 // normal narrow pattern
2659 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2660                           SDPatternOperator opnode, bit Commutable = 0> {
2661   let isCommutable = Commutable in {
2662     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2663                               opnode, VPR64, VPR128, v8i8, v8i16>;
2664     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2665                               opnode, VPR64, VPR128, v4i16, v4i32>;
2666     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2667                               opnode, VPR64, VPR128, v2i32, v2i64>;
2668   }
2669 }
2670
2671 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2672 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2673
2674 // pattern for acle intrinsic with 3 operands
2675 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2676                      string asmop, string ResS, string OpS>
2677   : NeonI_3VDiff<q, u, size, opcode,
2678                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2679                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2680                  [], NoItinerary> {
2681   let Constraints = "$src = $Rd";
2682   let neverHasSideEffects = 1;
2683 }
2684
2685 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2686   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2687   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2688   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2689 }
2690
2691 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2692 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2693
2694 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2695 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2696
2697 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2698 // part.
2699 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2700                         SDPatternOperator coreop>
2701   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2702                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2703                                                         (SrcTy VPR128:$Rm)))))),
2704         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2705               VPR128:$Rn, VPR128:$Rm)>;
2706
2707 // addhn2 patterns
2708 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2709           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2710 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2711           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2712 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2713           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2714
2715 // subhn2 patterns
2716 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2717           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2718 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2719           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2720 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2721           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2722
2723 // raddhn2 patterns
2724 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2725 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2726 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2727
2728 // rsubhn2 patterns
2729 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2730 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2731 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2732
2733 // pattern that need to extend result
2734 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2735                      string asmop, string ResS, string OpS,
2736                      SDPatternOperator opnode,
2737                      RegisterOperand OpVPR,
2738                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2739   : NeonI_3VDiff<q, u, size, opcode,
2740                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2741                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2742                  [(set (ResTy VPR128:$Rd),
2743                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2744                                                 (OpTy OpVPR:$Rm))))))],
2745                  NoItinerary>;
2746
2747 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2748                            SDPatternOperator opnode, bit Commutable = 0> {
2749   let isCommutable = Commutable in {
2750     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2751                                opnode, VPR64, v8i16, v8i8, v8i8>;
2752     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2753                                opnode, VPR64, v4i32, v4i16, v4i16>;
2754     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2755                                opnode, VPR64, v2i64, v2i32, v2i32>;
2756   }
2757 }
2758
2759 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2760 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2761
2762 multiclass NeonI_Op_High<SDPatternOperator op> {
2763   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2764                      (op (v8i8 (Neon_High16B node:$Rn)),
2765                          (v8i8 (Neon_High16B node:$Rm)))>;
2766   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
2767                      (op (v4i16 (Neon_High8H node:$Rn)),
2768                          (v4i16 (Neon_High8H node:$Rm)))>;
2769   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
2770                      (op (v2i32 (Neon_High4S node:$Rn)),
2771                          (v2i32 (Neon_High4S node:$Rm)))>;
2772 }
2773
2774 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
2775 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
2776 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
2777 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
2778 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
2779 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
2780
2781 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
2782                             bit Commutable = 0> {
2783   let isCommutable = Commutable in {
2784     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2785                                 !cast<PatFrag>(opnode # "_16B"),
2786                                 VPR128, v8i16, v16i8, v8i8>;
2787     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2788                                 !cast<PatFrag>(opnode # "_8H"),
2789                                 VPR128, v4i32, v8i16, v4i16>;
2790     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2791                                 !cast<PatFrag>(opnode # "_4S"),
2792                                 VPR128, v2i64, v4i32, v2i32>;
2793   }
2794 }
2795
2796 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
2797 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
2798
2799 // For pattern that need two operators being chained.
2800 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
2801                      string asmop, string ResS, string OpS,
2802                      SDPatternOperator opnode, SDPatternOperator subop,
2803                      RegisterOperand OpVPR,
2804                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2805   : NeonI_3VDiff<q, u, size, opcode,
2806                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2807                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2808                  [(set (ResTy VPR128:$Rd),
2809                     (ResTy (opnode
2810                       (ResTy VPR128:$src),
2811                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
2812                                                  (OpTy OpVPR:$Rm))))))))],
2813                  NoItinerary> {
2814   let Constraints = "$src = $Rd";
2815 }
2816
2817 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
2818                              SDPatternOperator opnode, SDPatternOperator subop>{
2819   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2820                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
2821   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2822                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
2823   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2824                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
2825 }
2826
2827 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
2828                                    add, int_arm_neon_vabds>;
2829 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
2830                                    add, int_arm_neon_vabdu>;
2831
2832 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
2833                               SDPatternOperator opnode, string subop> {
2834   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2835                              opnode, !cast<PatFrag>(subop # "_16B"),
2836                              VPR128, v8i16, v16i8, v8i8>;
2837   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2838                              opnode, !cast<PatFrag>(subop # "_8H"),
2839                              VPR128, v4i32, v8i16, v4i16>;
2840   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2841                              opnode, !cast<PatFrag>(subop # "_4S"),
2842                              VPR128, v2i64, v4i32, v2i32>;
2843 }
2844
2845 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
2846                                      "NI_sabdl_hi">;
2847 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
2848                                      "NI_uabdl_hi">;
2849
2850 // Long pattern with 2 operands
2851 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
2852                           SDPatternOperator opnode, bit Commutable = 0> {
2853   let isCommutable = Commutable in {
2854     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2855                               opnode, VPR128, VPR64, v8i16, v8i8>;
2856     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2857                               opnode, VPR128, VPR64, v4i32, v4i16>;
2858     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2859                               opnode, VPR128, VPR64, v2i64, v2i32>;
2860   }
2861 }
2862
2863 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
2864 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
2865
2866 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
2867                            string asmop, string ResS, string OpS,
2868                            SDPatternOperator opnode,
2869                            ValueType ResTy, ValueType OpTy>
2870   : NeonI_3VDiff<q, u, size, opcode,
2871                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2872                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2873                  [(set (ResTy VPR128:$Rd),
2874                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
2875                  NoItinerary>;
2876
2877 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
2878                                    string opnode, bit Commutable = 0> {
2879   let isCommutable = Commutable in {
2880     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2881                                       !cast<PatFrag>(opnode # "_16B"),
2882                                       v8i16, v16i8>;
2883     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2884                                      !cast<PatFrag>(opnode # "_8H"),
2885                                      v4i32, v8i16>;
2886     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2887                                      !cast<PatFrag>(opnode # "_4S"),
2888                                      v2i64, v4i32>;
2889   }
2890 }
2891
2892 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
2893                                          "NI_smull_hi", 1>;
2894 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
2895                                          "NI_umull_hi", 1>;
2896
2897 // Long pattern with 3 operands
2898 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2899                      string asmop, string ResS, string OpS,
2900                      SDPatternOperator opnode,
2901                      ValueType ResTy, ValueType OpTy>
2902   : NeonI_3VDiff<q, u, size, opcode,
2903                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
2904                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2905                  [(set (ResTy VPR128:$Rd),
2906                     (ResTy (opnode
2907                       (ResTy VPR128:$src),
2908                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
2909                NoItinerary> {
2910   let Constraints = "$src = $Rd";
2911 }
2912
2913 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
2914                              SDPatternOperator opnode> {
2915   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2916                              opnode, v8i16, v8i8>;
2917   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2918                              opnode, v4i32, v4i16>;
2919   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2920                              opnode, v2i64, v2i32>;
2921 }
2922
2923 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2924                          (add node:$Rd,
2925                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2926
2927 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2928                          (add node:$Rd,
2929                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2930
2931 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2932                          (sub node:$Rd,
2933                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
2934
2935 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
2936                          (sub node:$Rd,
2937                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
2938
2939 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
2940 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
2941
2942 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
2943 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
2944
2945 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
2946                            string asmop, string ResS, string OpS,
2947                            SDPatternOperator subop, SDPatternOperator opnode,
2948                            RegisterOperand OpVPR,
2949                            ValueType ResTy, ValueType OpTy>
2950   : NeonI_3VDiff<q, u, size, opcode,
2951                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
2952                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2953                [(set (ResTy VPR128:$Rd),
2954                   (ResTy (subop
2955                     (ResTy VPR128:$src),
2956                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
2957                NoItinerary> {
2958   let Constraints = "$src = $Rd";
2959 }
2960
2961 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
2962                                    SDPatternOperator subop, string opnode> {
2963   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2964                                     subop, !cast<PatFrag>(opnode # "_16B"),
2965                                     VPR128, v8i16, v16i8>;
2966   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2967                                    subop, !cast<PatFrag>(opnode # "_8H"),
2968                                    VPR128, v4i32, v8i16>;
2969   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2970                                    subop, !cast<PatFrag>(opnode # "_4S"),
2971                                    VPR128, v2i64, v4i32>;
2972 }
2973
2974 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
2975                                           add, "NI_smull_hi">;
2976 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
2977                                           add, "NI_umull_hi">;
2978
2979 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
2980                                           sub, "NI_smull_hi">;
2981 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
2982                                           sub, "NI_umull_hi">;
2983
2984 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
2985                                     SDPatternOperator opnode> {
2986   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2987                                    opnode, int_arm_neon_vqdmull,
2988                                    VPR64, v4i32, v4i16>;
2989   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2990                                    opnode, int_arm_neon_vqdmull,
2991                                    VPR64, v2i64, v2i32>;
2992 }
2993
2994 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
2995                                            int_arm_neon_vqadds>;
2996 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
2997                                            int_arm_neon_vqsubs>;
2998
2999 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3000                          SDPatternOperator opnode, bit Commutable = 0> {
3001   let isCommutable = Commutable in {
3002     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3003                               opnode, VPR128, VPR64, v4i32, v4i16>;
3004     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3005                               opnode, VPR128, VPR64, v2i64, v2i32>;
3006   }
3007 }
3008
3009 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3010                                 int_arm_neon_vqdmull, 1>;
3011
3012 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3013                                    string opnode, bit Commutable = 0> {
3014   let isCommutable = Commutable in {
3015     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3016                                      !cast<PatFrag>(opnode # "_8H"),
3017                                      v4i32, v8i16>;
3018     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3019                                      !cast<PatFrag>(opnode # "_4S"),
3020                                      v2i64, v4i32>;
3021   }
3022 }
3023
3024 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3025                                            "NI_qdmull_hi", 1>;
3026
3027 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3028                                      SDPatternOperator opnode> {
3029   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3030                                    opnode, NI_qdmull_hi_8H,
3031                                    VPR128, v4i32, v8i16>;
3032   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3033                                    opnode, NI_qdmull_hi_4S,
3034                                    VPR128, v2i64, v4i32>;
3035 }
3036
3037 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3038                                              int_arm_neon_vqadds>;
3039 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3040                                              int_arm_neon_vqsubs>;
3041
3042 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3043                          SDPatternOperator opnode_8h8b,
3044                          SDPatternOperator opnode_1q1d, bit Commutable = 0> {
3045   let isCommutable = Commutable in {
3046     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3047                               opnode_8h8b, VPR128, VPR64, v8i16, v8i8>;
3048
3049     def _1q1d : NeonI_3VD_2Op<0b0, u, 0b11, opcode, asmop, "1q", "1d",
3050                               opnode_1q1d, VPR128, VPR64, v16i8, v1i64>;
3051   }
3052 }
3053
3054 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp,
3055                               int_aarch64_neon_vmull_p64, 1>;
3056
3057 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3058                                    string opnode, bit Commutable = 0> {
3059   let isCommutable = Commutable in {
3060     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3061                                       !cast<PatFrag>(opnode # "_16B"),
3062                                       v8i16, v16i8>;
3063
3064     def _1q2d :
3065       NeonI_3VDiff<0b1, u, 0b11, opcode,
3066                    (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3067                    asmop # "\t$Rd.1q, $Rn.2d, $Rm.2d",
3068                    [(set (v16i8 VPR128:$Rd),
3069                       (v16i8 (int_aarch64_neon_vmull_p64
3070                         (v1i64 (scalar_to_vector
3071                           (i64 (vector_extract (v2i64 VPR128:$Rn), 1)))),
3072                         (v1i64 (scalar_to_vector
3073                           (i64 (vector_extract (v2i64 VPR128:$Rm), 1)))))))],
3074                    NoItinerary>;
3075   }
3076 }
3077
3078 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3079                                          1>;
3080
3081 // End of implementation for instruction class (3V Diff)
3082
3083 // The followings are vector load/store multiple N-element structure
3084 // (class SIMD lselem).
3085
3086 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3087 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3088 //              The structure consists of a sequence of sets of N values.
3089 //              The first element of the structure is placed in the first lane
3090 //              of the first first vector, the second element in the first lane
3091 //              of the second vector, and so on.
3092 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3093 // the three 64-bit vectors list {BA, DC, FE}.
3094 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3095 // 64-bit vectors list {DA, EB, FC}.
3096 // Store instructions store multiple structure to N registers like load.
3097
3098
3099 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3100                     RegisterOperand VecList, string asmop>
3101   : NeonI_LdStMult<q, 1, opcode, size,
3102                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3103                  asmop # "\t$Rt, [$Rn]",
3104                  [],
3105                  NoItinerary> {
3106   let mayLoad = 1;
3107   let neverHasSideEffects = 1;
3108 }
3109
3110 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3111   def _8B : NeonI_LDVList<0, opcode, 0b00,
3112                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3113
3114   def _4H : NeonI_LDVList<0, opcode, 0b01,
3115                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3116
3117   def _2S : NeonI_LDVList<0, opcode, 0b10,
3118                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3119
3120   def _16B : NeonI_LDVList<1, opcode, 0b00,
3121                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3122
3123   def _8H : NeonI_LDVList<1, opcode, 0b01,
3124                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3125
3126   def _4S : NeonI_LDVList<1, opcode, 0b10,
3127                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3128
3129   def _2D : NeonI_LDVList<1, opcode, 0b11,
3130                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3131 }
3132
3133 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3134 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3135 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3136
3137 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3138
3139 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3140
3141 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3142
3143 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3144 defm LD1x2 : LDVList_BHSD<0b1010, "VPair", "ld1">;
3145 def LD1x2_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3146
3147 defm LD1x3 : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3148 def LD1x3_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3149
3150 defm LD1x4 : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3151 def LD1x4_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3152
3153 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3154                     RegisterOperand VecList, string asmop>
3155   : NeonI_LdStMult<q, 0, opcode, size,
3156                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3157                  asmop # "\t$Rt, [$Rn]",
3158                  [],
3159                  NoItinerary> {
3160   let mayStore = 1;
3161   let neverHasSideEffects = 1;
3162 }
3163
3164 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3165   def _8B : NeonI_STVList<0, opcode, 0b00,
3166                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3167
3168   def _4H : NeonI_STVList<0, opcode, 0b01,
3169                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3170
3171   def _2S : NeonI_STVList<0, opcode, 0b10,
3172                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3173
3174   def _16B : NeonI_STVList<1, opcode, 0b00,
3175                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3176
3177   def _8H : NeonI_STVList<1, opcode, 0b01,
3178                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3179
3180   def _4S : NeonI_STVList<1, opcode, 0b10,
3181                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3182
3183   def _2D : NeonI_STVList<1, opcode, 0b11,
3184                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3185 }
3186
3187 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3188 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3189 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3190
3191 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3192
3193 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3194
3195 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3196
3197 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3198 defm ST1x2 : STVList_BHSD<0b1010, "VPair", "st1">;
3199 def ST1x2_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3200
3201 defm ST1x3 : STVList_BHSD<0b0110, "VTriple", "st1">;
3202 def ST1x3_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3203
3204 defm ST1x4 : STVList_BHSD<0b0010, "VQuad", "st1">;
3205 def ST1x4_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3206
3207 def : Pat<(v2f64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3208 def : Pat<(v2i64 (load GPR64xsp:$addr)), (LD1_2D GPR64xsp:$addr)>;
3209
3210 def : Pat<(v4f32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3211 def : Pat<(v4i32 (load GPR64xsp:$addr)), (LD1_4S GPR64xsp:$addr)>;
3212
3213 def : Pat<(v8i16 (load GPR64xsp:$addr)), (LD1_8H GPR64xsp:$addr)>;
3214 def : Pat<(v16i8 (load GPR64xsp:$addr)), (LD1_16B GPR64xsp:$addr)>;
3215
3216 def : Pat<(v1f64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3217 def : Pat<(v1i64 (load GPR64xsp:$addr)), (LD1_1D GPR64xsp:$addr)>;
3218
3219 def : Pat<(v2f32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3220 def : Pat<(v2i32 (load GPR64xsp:$addr)), (LD1_2S GPR64xsp:$addr)>;
3221
3222 def : Pat<(v4i16 (load GPR64xsp:$addr)), (LD1_4H GPR64xsp:$addr)>;
3223 def : Pat<(v8i8 (load GPR64xsp:$addr)), (LD1_8B GPR64xsp:$addr)>;
3224
3225 def : Pat<(store (v2i64 VPR128:$value), GPR64xsp:$addr),
3226           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3227 def : Pat<(store (v2f64 VPR128:$value), GPR64xsp:$addr),
3228           (ST1_2D GPR64xsp:$addr, VPR128:$value)>;
3229
3230 def : Pat<(store (v4i32 VPR128:$value), GPR64xsp:$addr),
3231           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3232 def : Pat<(store (v4f32 VPR128:$value), GPR64xsp:$addr),
3233           (ST1_4S GPR64xsp:$addr, VPR128:$value)>;
3234
3235 def : Pat<(store (v8i16 VPR128:$value), GPR64xsp:$addr),
3236           (ST1_8H GPR64xsp:$addr, VPR128:$value)>;
3237 def : Pat<(store (v16i8 VPR128:$value), GPR64xsp:$addr),
3238           (ST1_16B GPR64xsp:$addr, VPR128:$value)>;
3239
3240 def : Pat<(store (v1i64 VPR64:$value), GPR64xsp:$addr),
3241           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3242 def : Pat<(store (v1f64 VPR64:$value), GPR64xsp:$addr),
3243           (ST1_1D GPR64xsp:$addr, VPR64:$value)>;
3244
3245 def : Pat<(store (v2i32 VPR64:$value), GPR64xsp:$addr),
3246           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3247 def : Pat<(store (v2f32 VPR64:$value), GPR64xsp:$addr),
3248           (ST1_2S GPR64xsp:$addr, VPR64:$value)>;
3249
3250 def : Pat<(store (v4i16 VPR64:$value), GPR64xsp:$addr),
3251           (ST1_4H GPR64xsp:$addr, VPR64:$value)>;
3252 def : Pat<(store (v8i8 VPR64:$value), GPR64xsp:$addr),
3253           (ST1_8B GPR64xsp:$addr, VPR64:$value)>;
3254
3255 // Match load/store of v1i8/v1i16/v1i32 type to FPR8/FPR16/FPR32 load/store.
3256 // FIXME: for now we have v1i8, v1i16, v1i32 legal types, if they are illegal,
3257 // these patterns are not needed any more.
3258 def : Pat<(v1i8 (load GPR64xsp:$addr)), (LSFP8_LDR $addr, 0)>;
3259 def : Pat<(v1i16 (load GPR64xsp:$addr)), (LSFP16_LDR $addr, 0)>;
3260 def : Pat<(v1i32 (load GPR64xsp:$addr)), (LSFP32_LDR $addr, 0)>;
3261
3262 def : Pat<(store (v1i8 FPR8:$value), GPR64xsp:$addr),
3263           (LSFP8_STR $value, $addr, 0)>;
3264 def : Pat<(store (v1i16 FPR16:$value), GPR64xsp:$addr),
3265           (LSFP16_STR $value, $addr, 0)>;
3266 def : Pat<(store (v1i32 FPR32:$value), GPR64xsp:$addr),
3267           (LSFP32_STR $value, $addr, 0)>;
3268
3269
3270 // End of vector load/store multiple N-element structure(class SIMD lselem)
3271
3272 // The followings are post-index vector load/store multiple N-element
3273 // structure(class SIMD lselem-post)
3274 def exact1_asmoperand : AsmOperandClass {
3275   let Name = "Exact1";
3276   let PredicateMethod = "isExactImm<1>";
3277   let RenderMethod = "addImmOperands";
3278 }
3279 def uimm_exact1 : Operand<i32>, ImmLeaf<i32, [{return Imm == 1;}]> {
3280   let ParserMatchClass = exact1_asmoperand;
3281 }
3282
3283 def exact2_asmoperand : AsmOperandClass {
3284   let Name = "Exact2";
3285   let PredicateMethod = "isExactImm<2>";
3286   let RenderMethod = "addImmOperands";
3287 }
3288 def uimm_exact2 : Operand<i32>, ImmLeaf<i32, [{return Imm == 2;}]> {
3289   let ParserMatchClass = exact2_asmoperand;
3290 }
3291
3292 def exact3_asmoperand : AsmOperandClass {
3293   let Name = "Exact3";
3294   let PredicateMethod = "isExactImm<3>";
3295   let RenderMethod = "addImmOperands";
3296 }
3297 def uimm_exact3 : Operand<i32>, ImmLeaf<i32, [{return Imm == 3;}]> {
3298   let ParserMatchClass = exact3_asmoperand;
3299 }
3300
3301 def exact4_asmoperand : AsmOperandClass {
3302   let Name = "Exact4";
3303   let PredicateMethod = "isExactImm<4>";
3304   let RenderMethod = "addImmOperands";
3305 }
3306 def uimm_exact4 : Operand<i32>, ImmLeaf<i32, [{return Imm == 4;}]> {
3307   let ParserMatchClass = exact4_asmoperand;
3308 }
3309
3310 def exact6_asmoperand : AsmOperandClass {
3311   let Name = "Exact6";
3312   let PredicateMethod = "isExactImm<6>";
3313   let RenderMethod = "addImmOperands";
3314 }
3315 def uimm_exact6 : Operand<i32>, ImmLeaf<i32, [{return Imm == 6;}]> {
3316   let ParserMatchClass = exact6_asmoperand;
3317 }
3318
3319 def exact8_asmoperand : AsmOperandClass {
3320   let Name = "Exact8";
3321   let PredicateMethod = "isExactImm<8>";
3322   let RenderMethod = "addImmOperands";
3323 }
3324 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3325   let ParserMatchClass = exact8_asmoperand;
3326 }
3327
3328 def exact12_asmoperand : AsmOperandClass {
3329   let Name = "Exact12";
3330   let PredicateMethod = "isExactImm<12>";
3331   let RenderMethod = "addImmOperands";
3332 }
3333 def uimm_exact12 : Operand<i32>, ImmLeaf<i32, [{return Imm == 12;}]> {
3334   let ParserMatchClass = exact12_asmoperand;
3335 }
3336
3337 def exact16_asmoperand : AsmOperandClass {
3338   let Name = "Exact16";
3339   let PredicateMethod = "isExactImm<16>";
3340   let RenderMethod = "addImmOperands";
3341 }
3342 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3343   let ParserMatchClass = exact16_asmoperand;
3344 }
3345
3346 def exact24_asmoperand : AsmOperandClass {
3347   let Name = "Exact24";
3348   let PredicateMethod = "isExactImm<24>";
3349   let RenderMethod = "addImmOperands";
3350 }
3351 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3352   let ParserMatchClass = exact24_asmoperand;
3353 }
3354
3355 def exact32_asmoperand : AsmOperandClass {
3356   let Name = "Exact32";
3357   let PredicateMethod = "isExactImm<32>";
3358   let RenderMethod = "addImmOperands";
3359 }
3360 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3361   let ParserMatchClass = exact32_asmoperand;
3362 }
3363
3364 def exact48_asmoperand : AsmOperandClass {
3365   let Name = "Exact48";
3366   let PredicateMethod = "isExactImm<48>";
3367   let RenderMethod = "addImmOperands";
3368 }
3369 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3370   let ParserMatchClass = exact48_asmoperand;
3371 }
3372
3373 def exact64_asmoperand : AsmOperandClass {
3374   let Name = "Exact64";
3375   let PredicateMethod = "isExactImm<64>";
3376   let RenderMethod = "addImmOperands";
3377 }
3378 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3379   let ParserMatchClass = exact64_asmoperand;
3380 }
3381
3382 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3383                            RegisterOperand VecList, Operand ImmTy,
3384                            string asmop> {
3385   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3386       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3387     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3388                      (outs VecList:$Rt, GPR64xsp:$wb),
3389                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3390                      asmop # "\t$Rt, [$Rn], $amt",
3391                      [],
3392                      NoItinerary> {
3393       let Rm = 0b11111;
3394     }
3395
3396     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3397                         (outs VecList:$Rt, GPR64xsp:$wb),
3398                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3399                         asmop # "\t$Rt, [$Rn], $Rm",
3400                         [],
3401                         NoItinerary>;
3402   }
3403 }
3404
3405 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3406     Operand ImmTy2, string asmop> {
3407   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3408                               !cast<RegisterOperand>(List # "8B_operand"),
3409                               ImmTy, asmop>;
3410
3411   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3412                               !cast<RegisterOperand>(List # "4H_operand"),
3413                               ImmTy, asmop>;
3414
3415   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3416                               !cast<RegisterOperand>(List # "2S_operand"),
3417                               ImmTy, asmop>;
3418
3419   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3420                                !cast<RegisterOperand>(List # "16B_operand"),
3421                                ImmTy2, asmop>;
3422
3423   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3424                               !cast<RegisterOperand>(List # "8H_operand"),
3425                               ImmTy2, asmop>;
3426
3427   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3428                               !cast<RegisterOperand>(List # "4S_operand"),
3429                               ImmTy2, asmop>;
3430
3431   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3432                               !cast<RegisterOperand>(List # "2D_operand"),
3433                               ImmTy2, asmop>;
3434 }
3435
3436 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3437 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3438 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3439                                  "ld1">;
3440
3441 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3442
3443 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3444                              "ld3">;
3445
3446 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3447
3448 // Post-index load multiple 1-element structures from N consecutive registers
3449 // (N = 2,3,4)
3450 defm LD1x2WB : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3451                                "ld1">;
3452 defm LD1x2WB_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3453                                    uimm_exact16, "ld1">;
3454
3455 defm LD1x3WB : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3456                                "ld1">;
3457 defm LD1x3WB_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3458                                    uimm_exact24, "ld1">;
3459
3460 defm LD1x4WB : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3461                                 "ld1">;
3462 defm LD1x4WB_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3463                                    uimm_exact32, "ld1">;
3464
3465 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3466                             RegisterOperand VecList, Operand ImmTy,
3467                             string asmop> {
3468   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3469       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3470     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3471                      (outs GPR64xsp:$wb),
3472                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3473                      asmop # "\t$Rt, [$Rn], $amt",
3474                      [],
3475                      NoItinerary> {
3476       let Rm = 0b11111;
3477     }
3478
3479     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3480                       (outs GPR64xsp:$wb),
3481                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3482                       asmop # "\t$Rt, [$Rn], $Rm",
3483                       [],
3484                       NoItinerary>;
3485   }
3486 }
3487
3488 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3489                            Operand ImmTy2, string asmop> {
3490   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3491                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3492
3493   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3494                               !cast<RegisterOperand>(List # "4H_operand"),
3495                               ImmTy, asmop>;
3496
3497   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3498                               !cast<RegisterOperand>(List # "2S_operand"),
3499                               ImmTy, asmop>;
3500
3501   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3502                                !cast<RegisterOperand>(List # "16B_operand"),
3503                                ImmTy2, asmop>;
3504
3505   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3506                               !cast<RegisterOperand>(List # "8H_operand"),
3507                               ImmTy2, asmop>;
3508
3509   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3510                               !cast<RegisterOperand>(List # "4S_operand"),
3511                               ImmTy2, asmop>;
3512
3513   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3514                               !cast<RegisterOperand>(List # "2D_operand"),
3515                               ImmTy2, asmop>;
3516 }
3517
3518 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3519 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3520 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3521                                  "st1">;
3522
3523 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3524
3525 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3526                              "st3">;
3527
3528 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3529
3530 // Post-index load multiple 1-element structures from N consecutive registers
3531 // (N = 2,3,4)
3532 defm ST1x2WB : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3533                                "st1">;
3534 defm ST1x2WB_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3535                                    uimm_exact16, "st1">;
3536
3537 defm ST1x3WB : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3538                                "st1">;
3539 defm ST1x3WB_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3540                                    uimm_exact24, "st1">;
3541
3542 defm ST1x4WB : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3543                                "st1">;
3544 defm ST1x4WB_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3545                                    uimm_exact32, "st1">;
3546
3547 // End of post-index vector load/store multiple N-element structure
3548 // (class SIMD lselem-post)
3549
3550 // The followings are vector load/store single N-element structure
3551 // (class SIMD lsone).
3552 def neon_uimm0_bare : Operand<i64>,
3553                         ImmLeaf<i64, [{return Imm == 0;}]> {
3554   let ParserMatchClass = neon_uimm0_asmoperand;
3555   let PrintMethod = "printUImmBareOperand";
3556 }
3557
3558 def neon_uimm1_bare : Operand<i64>,
3559                         ImmLeaf<i64, [{return Imm < 2;}]> {
3560   let ParserMatchClass = neon_uimm1_asmoperand;
3561   let PrintMethod = "printUImmBareOperand";
3562 }
3563
3564 def neon_uimm2_bare : Operand<i64>,
3565                         ImmLeaf<i64, [{return Imm < 4;}]> {
3566   let ParserMatchClass = neon_uimm2_asmoperand;
3567   let PrintMethod = "printUImmBareOperand";
3568 }
3569
3570 def neon_uimm3_bare : Operand<i64>,
3571                         ImmLeaf<i64, [{return Imm < 8;}]> {
3572   let ParserMatchClass = uimm3_asmoperand;
3573   let PrintMethod = "printUImmBareOperand";
3574 }
3575
3576 def neon_uimm4_bare : Operand<i64>,
3577                         ImmLeaf<i64, [{return Imm < 16;}]> {
3578   let ParserMatchClass = uimm4_asmoperand;
3579   let PrintMethod = "printUImmBareOperand";
3580 }
3581
3582 class NeonI_LDN_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3583                     RegisterOperand VecList, string asmop>
3584     : NeonI_LdOne_Dup<q, r, opcode, size,
3585                       (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3586                       asmop # "\t$Rt, [$Rn]",
3587                       [],
3588                       NoItinerary> {
3589   let mayLoad = 1;
3590   let neverHasSideEffects = 1;
3591 }
3592
3593 multiclass LDN_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop> {
3594   def _8B : NeonI_LDN_Dup<0, r, opcode, 0b00,
3595                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3596
3597   def _4H : NeonI_LDN_Dup<0, r, opcode, 0b01,
3598                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3599
3600   def _2S : NeonI_LDN_Dup<0, r, opcode, 0b10,
3601                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3602
3603   def _1D : NeonI_LDN_Dup<0, r, opcode, 0b11,
3604                           !cast<RegisterOperand>(List # "1D_operand"), asmop>;
3605
3606   def _16B : NeonI_LDN_Dup<1, r, opcode, 0b00,
3607                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3608
3609   def _8H : NeonI_LDN_Dup<1, r, opcode, 0b01,
3610                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3611
3612   def _4S : NeonI_LDN_Dup<1, r, opcode, 0b10,
3613                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3614
3615   def _2D : NeonI_LDN_Dup<1, r, opcode, 0b11,
3616                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3617 }
3618
3619 // Load single 1-element structure to all lanes of 1 register
3620 defm LD1R : LDN_Dup_BHSD<0b0, 0b110, "VOne", "ld1r">;
3621
3622 // Load single N-element structure to all lanes of N consecutive
3623 // registers (N = 2,3,4)
3624 defm LD2R : LDN_Dup_BHSD<0b1, 0b110, "VPair", "ld2r">;
3625 defm LD3R : LDN_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r">;
3626 defm LD4R : LDN_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r">;
3627
3628
3629 class LD1R_pattern <ValueType VTy, ValueType DTy, PatFrag LoadOp,
3630                     Instruction INST>
3631     : Pat<(VTy (Neon_vdup (DTy (LoadOp GPR64xsp:$Rn)))),
3632           (VTy (INST GPR64xsp:$Rn))>;
3633
3634 // Match all LD1R instructions
3635 def : LD1R_pattern<v8i8, i32, extloadi8, LD1R_8B>;
3636
3637 def : LD1R_pattern<v16i8, i32, extloadi8, LD1R_16B>;
3638
3639 def : LD1R_pattern<v4i16, i32, extloadi16, LD1R_4H>;
3640
3641 def : LD1R_pattern<v8i16, i32, extloadi16, LD1R_8H>;
3642
3643 def : LD1R_pattern<v2i32, i32, load, LD1R_2S>;
3644 def : LD1R_pattern<v2f32, f32, load, LD1R_2S>;
3645
3646 def : LD1R_pattern<v4i32, i32, load, LD1R_4S>;
3647 def : LD1R_pattern<v4f32, f32, load, LD1R_4S>;
3648
3649 def : LD1R_pattern<v1i64, i64, load, LD1R_1D>;
3650 def : LD1R_pattern<v1f64, f64, load, LD1R_1D>;
3651
3652 def : LD1R_pattern<v2i64, i64, load, LD1R_2D>;
3653 def : LD1R_pattern<v2f64, f64, load, LD1R_2D>;
3654
3655
3656 multiclass VectorList_Bare_BHSD<string PREFIX, int Count,
3657                                 RegisterClass RegList> {
3658   defm B : VectorList_operands<PREFIX, "B", Count, RegList>;
3659   defm H : VectorList_operands<PREFIX, "H", Count, RegList>;
3660   defm S : VectorList_operands<PREFIX, "S", Count, RegList>;
3661   defm D : VectorList_operands<PREFIX, "D", Count, RegList>;
3662 }
3663
3664 // Special vector list operand of 128-bit vectors with bare layout.
3665 // i.e. only show ".b", ".h", ".s", ".d"
3666 defm VOne : VectorList_Bare_BHSD<"VOne", 1, FPR128>;
3667 defm VPair : VectorList_Bare_BHSD<"VPair", 2, QPair>;
3668 defm VTriple : VectorList_Bare_BHSD<"VTriple", 3, QTriple>;
3669 defm VQuad : VectorList_Bare_BHSD<"VQuad", 4, QQuad>;
3670
3671 class NeonI_LDN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3672                      Operand ImmOp, string asmop>
3673     : NeonI_LdStOne_Lane<1, r, op2_1, op0,
3674                          (outs VList:$Rt),
3675                          (ins GPR64xsp:$Rn, VList:$src, ImmOp:$lane),
3676                          asmop # "\t$Rt[$lane], [$Rn]",
3677                          [],
3678                          NoItinerary> {
3679   let mayLoad = 1;
3680   let neverHasSideEffects = 1;
3681   let hasExtraDefRegAllocReq = 1;
3682   let Constraints = "$src = $Rt";
3683 }
3684
3685 multiclass LDN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3686   def _B : NeonI_LDN_Lane<r, 0b00, op0,
3687                           !cast<RegisterOperand>(List # "B_operand"),
3688                           neon_uimm4_bare, asmop> {
3689     let Inst{12-10} = lane{2-0};
3690     let Inst{30} = lane{3};
3691   }
3692
3693   def _H : NeonI_LDN_Lane<r, 0b01, op0,
3694                           !cast<RegisterOperand>(List # "H_operand"),
3695                           neon_uimm3_bare, asmop> {
3696     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3697     let Inst{30} = lane{2};
3698   }
3699
3700   def _S : NeonI_LDN_Lane<r, 0b10, op0,
3701                           !cast<RegisterOperand>(List # "S_operand"),
3702                           neon_uimm2_bare, asmop> {
3703     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3704     let Inst{30} = lane{1};
3705   }
3706
3707   def _D : NeonI_LDN_Lane<r, 0b10, op0,
3708                           !cast<RegisterOperand>(List # "D_operand"),
3709                           neon_uimm1_bare, asmop> {
3710     let Inst{12-10} = 0b001;
3711     let Inst{30} = lane{0};
3712   }
3713 }
3714
3715 // Load single 1-element structure to one lane of 1 register.
3716 defm LD1LN : LDN_Lane_BHSD<0b0, 0b0, "VOne", "ld1">;
3717
3718 // Load single N-element structure to one lane of N consecutive registers
3719 // (N = 2,3,4)
3720 defm LD2LN : LDN_Lane_BHSD<0b1, 0b0, "VPair", "ld2">;
3721 defm LD3LN : LDN_Lane_BHSD<0b0, 0b1, "VTriple", "ld3">;
3722 defm LD4LN : LDN_Lane_BHSD<0b1, 0b1, "VQuad", "ld4">;
3723
3724 multiclass LD1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3725                           Operand ImmOp, Operand ImmOp2, PatFrag LoadOp,
3726                           Instruction INST> {
3727   def : Pat<(VTy (vector_insert (VTy VPR64:$src),
3728                      (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp:$lane))),
3729             (VTy (EXTRACT_SUBREG
3730                      (INST GPR64xsp:$Rn,
3731                            (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
3732                            ImmOp:$lane),
3733                      sub_64))>;
3734
3735   def : Pat<(VTy2 (vector_insert (VTy2 VPR128:$src),
3736                       (DTy (LoadOp GPR64xsp:$Rn)), (ImmOp2:$lane))),
3737             (VTy2 (INST GPR64xsp:$Rn, VPR128:$src, ImmOp2:$lane))>;
3738 }
3739
3740 // Match all LD1LN instructions
3741 defm : LD1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3742                       extloadi8, LD1LN_B>;
3743
3744 defm : LD1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3745                       extloadi16, LD1LN_H>;
3746
3747 defm : LD1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3748                       load, LD1LN_S>;
3749 defm : LD1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3750                       load, LD1LN_S>;
3751
3752 defm : LD1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3753                       load, LD1LN_D>;
3754 defm : LD1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3755                       load, LD1LN_D>;
3756
3757 class NeonI_STN_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3758                      Operand ImmOp, string asmop>
3759     : NeonI_LdStOne_Lane<0, r, op2_1, op0,
3760                          (outs), (ins GPR64xsp:$Rn, VList:$Rt, ImmOp:$lane),
3761                          asmop # "\t$Rt[$lane], [$Rn]",
3762                          [],
3763                          NoItinerary> {
3764   let mayStore = 1;
3765   let neverHasSideEffects = 1;
3766   let hasExtraDefRegAllocReq = 1;
3767 }
3768
3769 multiclass STN_Lane_BHSD<bit r, bit op0, string List, string asmop> {
3770   def _B : NeonI_STN_Lane<r, 0b00, op0,
3771                           !cast<RegisterOperand>(List # "B_operand"),
3772                           neon_uimm4_bare, asmop> {
3773     let Inst{12-10} = lane{2-0};
3774     let Inst{30} = lane{3};
3775   }
3776
3777   def _H : NeonI_STN_Lane<r, 0b01, op0,
3778                           !cast<RegisterOperand>(List # "H_operand"),
3779                           neon_uimm3_bare, asmop> {
3780     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3781     let Inst{30} = lane{2};
3782   }
3783
3784   def _S : NeonI_STN_Lane<r, 0b10, op0,
3785                           !cast<RegisterOperand>(List # "S_operand"),
3786                            neon_uimm2_bare, asmop> {
3787     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3788     let Inst{30} = lane{1};
3789   }
3790
3791   def _D : NeonI_STN_Lane<r, 0b10, op0,
3792                           !cast<RegisterOperand>(List # "D_operand"),
3793                           neon_uimm1_bare, asmop>{
3794     let Inst{12-10} = 0b001;
3795     let Inst{30} = lane{0};
3796   }
3797 }
3798
3799 // Store single 1-element structure from one lane of 1 register.
3800 defm ST1LN : STN_Lane_BHSD<0b0, 0b0, "VOne", "st1">;
3801
3802 // Store single N-element structure from one lane of N consecutive registers
3803 // (N = 2,3,4)
3804 defm ST2LN : STN_Lane_BHSD<0b1, 0b0, "VPair", "st2">;
3805 defm ST3LN : STN_Lane_BHSD<0b0, 0b1, "VTriple", "st3">;
3806 defm ST4LN : STN_Lane_BHSD<0b1, 0b1, "VQuad", "st4">;
3807
3808 multiclass ST1LN_patterns<ValueType VTy, ValueType VTy2, ValueType DTy,
3809                           Operand ImmOp, Operand ImmOp2, PatFrag StoreOp,
3810                           Instruction INST> {
3811   def : Pat<(StoreOp (DTy (vector_extract (VTy VPR64:$Rt), ImmOp:$lane)),
3812                      GPR64xsp:$Rn),
3813             (INST GPR64xsp:$Rn,
3814                   (SUBREG_TO_REG (i64 0), VPR64:$Rt, sub_64),
3815                   ImmOp:$lane)>;
3816
3817   def : Pat<(StoreOp (DTy (vector_extract (VTy2 VPR128:$Rt), ImmOp2:$lane)),
3818                      GPR64xsp:$Rn),
3819             (INST GPR64xsp:$Rn, VPR128:$Rt, ImmOp2:$lane)>;
3820 }
3821
3822 // Match all ST1LN instructions
3823 defm : ST1LN_patterns<v8i8, v16i8, i32, neon_uimm3_bare, neon_uimm4_bare,
3824                       truncstorei8, ST1LN_B>;
3825
3826 defm : ST1LN_patterns<v4i16, v8i16, i32, neon_uimm2_bare, neon_uimm3_bare,
3827                       truncstorei16, ST1LN_H>;
3828
3829 defm : ST1LN_patterns<v2i32, v4i32, i32, neon_uimm1_bare, neon_uimm2_bare,
3830                       store, ST1LN_S>;
3831 defm : ST1LN_patterns<v2f32, v4f32, f32, neon_uimm1_bare, neon_uimm2_bare,
3832                       store, ST1LN_S>;
3833
3834 defm : ST1LN_patterns<v1i64, v2i64, i64, neon_uimm0_bare, neon_uimm1_bare,
3835                       store, ST1LN_D>;
3836 defm : ST1LN_patterns<v1f64, v2f64, f64, neon_uimm0_bare, neon_uimm1_bare,
3837                       store, ST1LN_D>;
3838
3839 // End of vector load/store single N-element structure (class SIMD lsone).
3840
3841
3842 // The following are post-index load/store single N-element instructions
3843 // (class SIMD lsone-post)
3844
3845 multiclass NeonI_LDN_WB_Dup<bit q, bit r, bits<3> opcode, bits<2> size,
3846                             RegisterOperand VecList, Operand ImmTy,
3847                             string asmop> {
3848   let mayLoad = 1, neverHasSideEffects = 1, Constraints = "$wb = $Rn",
3849   DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3850     def _fixed : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3851                       (outs VecList:$Rt, GPR64xsp:$wb),
3852                       (ins GPR64xsp:$Rn, ImmTy:$amt),
3853                       asmop # "\t$Rt, [$Rn], $amt",
3854                       [],
3855                       NoItinerary> {
3856                         let Rm = 0b11111;
3857                       }
3858
3859     def _register : NeonI_LdOne_Dup_Post<q, r, opcode, size,
3860                       (outs VecList:$Rt, GPR64xsp:$wb),
3861                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3862                       asmop # "\t$Rt, [$Rn], $Rm",
3863                       [],
3864                       NoItinerary>;
3865   }
3866 }
3867
3868 multiclass LDWB_Dup_BHSD<bit r, bits<3> opcode, string List, string asmop,
3869                          Operand uimm_b, Operand uimm_h,
3870                          Operand uimm_s, Operand uimm_d> {
3871   defm _8B : NeonI_LDN_WB_Dup<0, r, opcode, 0b00,
3872                               !cast<RegisterOperand>(List # "8B_operand"),
3873                               uimm_b, asmop>;
3874
3875   defm _4H : NeonI_LDN_WB_Dup<0, r, opcode, 0b01,
3876                               !cast<RegisterOperand>(List # "4H_operand"),
3877                               uimm_h, asmop>;
3878
3879   defm _2S : NeonI_LDN_WB_Dup<0, r, opcode, 0b10,
3880                               !cast<RegisterOperand>(List # "2S_operand"),
3881                               uimm_s, asmop>;
3882
3883   defm _1D : NeonI_LDN_WB_Dup<0, r, opcode, 0b11,
3884                               !cast<RegisterOperand>(List # "1D_operand"),
3885                               uimm_d, asmop>;
3886
3887   defm _16B : NeonI_LDN_WB_Dup<1, r, opcode, 0b00,
3888                                !cast<RegisterOperand>(List # "16B_operand"),
3889                                uimm_b, asmop>;
3890
3891   defm _8H : NeonI_LDN_WB_Dup<1, r, opcode, 0b01,
3892                               !cast<RegisterOperand>(List # "8H_operand"),
3893                               uimm_h, asmop>;
3894
3895   defm _4S : NeonI_LDN_WB_Dup<1, r, opcode, 0b10,
3896                               !cast<RegisterOperand>(List # "4S_operand"),
3897                               uimm_s, asmop>;
3898
3899   defm _2D : NeonI_LDN_WB_Dup<1, r, opcode, 0b11,
3900                               !cast<RegisterOperand>(List # "2D_operand"),
3901                               uimm_d, asmop>;
3902 }
3903
3904 // Post-index load single 1-element structure to all lanes of 1 register
3905 defm LD1R_WB : LDWB_Dup_BHSD<0b0, 0b110, "VOne", "ld1r", uimm_exact1,
3906                              uimm_exact2, uimm_exact4, uimm_exact8>;
3907
3908 // Post-index load single N-element structure to all lanes of N consecutive
3909 // registers (N = 2,3,4)
3910 defm LD2R_WB : LDWB_Dup_BHSD<0b1, 0b110, "VPair", "ld2r", uimm_exact2,
3911                              uimm_exact4, uimm_exact8, uimm_exact16>;
3912 defm LD3R_WB : LDWB_Dup_BHSD<0b0, 0b111, "VTriple", "ld3r", uimm_exact3,
3913                              uimm_exact6, uimm_exact12, uimm_exact24>;
3914 defm LD4R_WB : LDWB_Dup_BHSD<0b1, 0b111, "VQuad", "ld4r", uimm_exact4,
3915                              uimm_exact8, uimm_exact16, uimm_exact32>;
3916
3917 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
3918     Constraints = "$Rn = $wb, $Rt = $src",
3919     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
3920   class LDN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3921                                 Operand ImmTy, Operand ImmOp, string asmop>
3922       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3923                                 (outs VList:$Rt, GPR64xsp:$wb),
3924                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
3925                                     VList:$src, ImmOp:$lane),
3926                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
3927                                 [],
3928                                 NoItinerary> {
3929     let Rm = 0b11111;
3930   }
3931
3932   class LDN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
3933                                  Operand ImmTy, Operand ImmOp, string asmop>
3934       : NeonI_LdStOne_Lane_Post<1, r, op2_1, op0,
3935                                 (outs VList:$Rt, GPR64xsp:$wb),
3936                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm,
3937                                     VList:$src, ImmOp:$lane),
3938                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
3939                                 [],
3940                                 NoItinerary>;
3941 }
3942
3943 multiclass LD_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
3944                            Operand uimm_b, Operand uimm_h,
3945                            Operand uimm_s, Operand uimm_d> {
3946   def _B_fixed : LDN_WBFx_Lane<r, 0b00, op0,
3947                                !cast<RegisterOperand>(List # "B_operand"),
3948                                uimm_b, neon_uimm4_bare, asmop> {
3949     let Inst{12-10} = lane{2-0};
3950     let Inst{30} = lane{3};
3951   }
3952
3953   def _B_register : LDN_WBReg_Lane<r, 0b00, op0,
3954                                    !cast<RegisterOperand>(List # "B_operand"),
3955                                    uimm_b, neon_uimm4_bare, asmop> {
3956     let Inst{12-10} = lane{2-0};
3957     let Inst{30} = lane{3};
3958   }
3959
3960   def _H_fixed : LDN_WBFx_Lane<r, 0b01, op0,
3961                                !cast<RegisterOperand>(List # "H_operand"),
3962                                uimm_h, neon_uimm3_bare, asmop> {
3963     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3964     let Inst{30} = lane{2};
3965   }
3966
3967   def _H_register : LDN_WBReg_Lane<r, 0b01, op0,
3968                                    !cast<RegisterOperand>(List # "H_operand"),
3969                                    uimm_h, neon_uimm3_bare, asmop> {
3970     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
3971     let Inst{30} = lane{2};
3972   }
3973
3974   def _S_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3975                                !cast<RegisterOperand>(List # "S_operand"),
3976                                uimm_s, neon_uimm2_bare, asmop> {
3977     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3978     let Inst{30} = lane{1};
3979   }
3980
3981   def _S_register : LDN_WBReg_Lane<r, 0b10, op0,
3982                                    !cast<RegisterOperand>(List # "S_operand"),
3983                                    uimm_s, neon_uimm2_bare, asmop> {
3984     let Inst{12-10} = {lane{0}, 0b0, 0b0};
3985     let Inst{30} = lane{1};
3986   }
3987
3988   def _D_fixed : LDN_WBFx_Lane<r, 0b10, op0,
3989                                !cast<RegisterOperand>(List # "D_operand"),
3990                                uimm_d, neon_uimm1_bare, asmop> {
3991     let Inst{12-10} = 0b001;
3992     let Inst{30} = lane{0};
3993   }
3994
3995   def _D_register : LDN_WBReg_Lane<r, 0b10, op0,
3996                                    !cast<RegisterOperand>(List # "D_operand"),
3997                                    uimm_d, neon_uimm1_bare, asmop> {
3998     let Inst{12-10} = 0b001;
3999     let Inst{30} = lane{0};
4000   }
4001 }
4002
4003 // Post-index load single 1-element structure to one lane of 1 register.
4004 defm LD1LN_WB : LD_Lane_WB_BHSD<0b0, 0b0, "VOne", "ld1", uimm_exact1,
4005                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4006
4007 // Post-index load single N-element structure to one lane of N consecutive
4008 // registers
4009 // (N = 2,3,4)
4010 defm LD2LN_WB : LD_Lane_WB_BHSD<0b1, 0b0, "VPair", "ld2", uimm_exact2,
4011                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4012 defm LD3LN_WB : LD_Lane_WB_BHSD<0b0, 0b1, "VTriple", "ld3", uimm_exact3,
4013                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4014 defm LD4LN_WB : LD_Lane_WB_BHSD<0b1, 0b1, "VQuad", "ld4", uimm_exact4,
4015                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4016
4017 let mayStore = 1, neverHasSideEffects = 1,
4018     hasExtraDefRegAllocReq = 1, Constraints = "$Rn = $wb",
4019     DecoderMethod = "DecodeVLDSTLanePostInstruction" in {
4020   class STN_WBFx_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4021                       Operand ImmTy, Operand ImmOp, string asmop>
4022       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4023                                 (outs GPR64xsp:$wb),
4024                                 (ins GPR64xsp:$Rn, ImmTy:$amt,
4025                                     VList:$Rt, ImmOp:$lane),
4026                                 asmop # "\t$Rt[$lane], [$Rn], $amt",
4027                                 [],
4028                                 NoItinerary> {
4029     let Rm = 0b11111;
4030   }
4031
4032   class STN_WBReg_Lane<bit r, bits<2> op2_1, bit op0, RegisterOperand VList,
4033                        Operand ImmTy, Operand ImmOp, string asmop>
4034       : NeonI_LdStOne_Lane_Post<0, r, op2_1, op0,
4035                                 (outs GPR64xsp:$wb),
4036                                 (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VList:$Rt,
4037                                     ImmOp:$lane),
4038                                 asmop # "\t$Rt[$lane], [$Rn], $Rm",
4039                                 [],
4040                                 NoItinerary>;
4041 }
4042
4043 multiclass ST_Lane_WB_BHSD<bit r, bit op0, string List, string asmop,
4044                            Operand uimm_b, Operand uimm_h,
4045                            Operand uimm_s, Operand uimm_d> {
4046   def _B_fixed : STN_WBFx_Lane<r, 0b00, op0,
4047                                !cast<RegisterOperand>(List # "B_operand"),
4048                                uimm_b, neon_uimm4_bare, asmop> {
4049     let Inst{12-10} = lane{2-0};
4050     let Inst{30} = lane{3};
4051   }
4052
4053   def _B_register : STN_WBReg_Lane<r, 0b00, op0,
4054                                    !cast<RegisterOperand>(List # "B_operand"),
4055                                    uimm_b, neon_uimm4_bare, asmop> {
4056     let Inst{12-10} = lane{2-0};
4057     let Inst{30} = lane{3};
4058   }
4059
4060   def _H_fixed : STN_WBFx_Lane<r, 0b01, op0,
4061                                !cast<RegisterOperand>(List # "H_operand"),
4062                                uimm_h, neon_uimm3_bare, asmop> {
4063     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4064     let Inst{30} = lane{2};
4065   }
4066
4067   def _H_register : STN_WBReg_Lane<r, 0b01, op0,
4068                                    !cast<RegisterOperand>(List # "H_operand"),
4069                                    uimm_h, neon_uimm3_bare, asmop> {
4070     let Inst{12-10} = {lane{1}, lane{0}, 0b0};
4071     let Inst{30} = lane{2};
4072   }
4073
4074   def _S_fixed : STN_WBFx_Lane<r, 0b10, op0,
4075                                !cast<RegisterOperand>(List # "S_operand"),
4076                                uimm_s, neon_uimm2_bare, asmop> {
4077     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4078     let Inst{30} = lane{1};
4079   }
4080
4081   def _S_register : STN_WBReg_Lane<r, 0b10, op0,
4082                                    !cast<RegisterOperand>(List # "S_operand"),
4083                                    uimm_s, neon_uimm2_bare, asmop> {
4084     let Inst{12-10} = {lane{0}, 0b0, 0b0};
4085     let Inst{30} = lane{1};
4086   }
4087
4088   def _D_fixed : STN_WBFx_Lane<r, 0b10, op0,
4089                                !cast<RegisterOperand>(List # "D_operand"),
4090                                uimm_d, neon_uimm1_bare, asmop> {
4091     let Inst{12-10} = 0b001;
4092     let Inst{30} = lane{0};
4093   }
4094
4095   def _D_register : STN_WBReg_Lane<r, 0b10, op0,
4096                                    !cast<RegisterOperand>(List # "D_operand"),
4097                                    uimm_d, neon_uimm1_bare, asmop> {
4098     let Inst{12-10} = 0b001;
4099     let Inst{30} = lane{0};
4100   }
4101 }
4102
4103 // Post-index store single 1-element structure from one lane of 1 register.
4104 defm ST1LN_WB : ST_Lane_WB_BHSD<0b0, 0b0, "VOne", "st1", uimm_exact1,
4105                                 uimm_exact2, uimm_exact4, uimm_exact8>;
4106
4107 // Post-index store single N-element structure from one lane of N consecutive
4108 // registers (N = 2,3,4)
4109 defm ST2LN_WB : ST_Lane_WB_BHSD<0b1, 0b0, "VPair", "st2", uimm_exact2,
4110                                 uimm_exact4, uimm_exact8, uimm_exact16>;
4111 defm ST3LN_WB : ST_Lane_WB_BHSD<0b0, 0b1, "VTriple", "st3", uimm_exact3,
4112                                 uimm_exact6, uimm_exact12, uimm_exact24>;
4113 defm ST4LN_WB : ST_Lane_WB_BHSD<0b1, 0b1, "VQuad", "st4", uimm_exact4,
4114                                 uimm_exact8, uimm_exact16, uimm_exact32>;
4115
4116 // End of post-index load/store single N-element instructions
4117 // (class SIMD lsone-post)
4118
4119 // Neon Scalar instructions implementation
4120 // Scalar Three Same
4121
4122 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4123                              RegisterClass FPRC>
4124   : NeonI_Scalar3Same<u, size, opcode,
4125                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
4126                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4127                       [],
4128                       NoItinerary>;
4129
4130 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
4131   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4132
4133 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
4134                                       bit Commutable = 0> {
4135   let isCommutable = Commutable in {
4136     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4137     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4138   }
4139 }
4140
4141 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
4142                                       string asmop, bit Commutable = 0> {
4143   let isCommutable = Commutable in {
4144     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
4145     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
4146   }
4147 }
4148
4149 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
4150                                         string asmop, bit Commutable = 0> {
4151   let isCommutable = Commutable in {
4152     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
4153     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
4154     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
4155     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
4156   }
4157 }
4158
4159 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
4160                                             Instruction INSTD> {
4161   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
4162             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4163 }
4164
4165 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
4166                                                Instruction INSTB,
4167                                                Instruction INSTH,
4168                                                Instruction INSTS,
4169                                                Instruction INSTD>
4170   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
4171   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
4172            (INSTB FPR8:$Rn, FPR8:$Rm)>;
4173   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4174            (INSTH FPR16:$Rn, FPR16:$Rm)>;
4175   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4176            (INSTS FPR32:$Rn, FPR32:$Rm)>;
4177 }
4178
4179 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
4180                                              Instruction INSTH,
4181                                              Instruction INSTS> {
4182   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4183             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4184   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4185             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4186 }
4187
4188 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
4189                                              ValueType SResTy, ValueType STy,
4190                                              Instruction INSTS, ValueType DResTy,
4191                                              ValueType DTy, Instruction INSTD> {
4192   def : Pat<(SResTy (opnode (STy FPR32:$Rn), (STy FPR32:$Rm))),
4193             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4194   def : Pat<(DResTy (opnode (DTy FPR64:$Rn), (DTy FPR64:$Rm))),
4195             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4196 }
4197
4198 class Neon_Scalar3Same_cmp_V1_D_size_patterns<CondCode CC,
4199                                               Instruction INSTD>
4200   : Pat<(v1i64 (Neon_cmp (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm), CC)),
4201         (INSTD FPR64:$Rn, FPR64:$Rm)>;
4202
4203 // Scalar Three Different
4204
4205 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
4206                              RegisterClass FPRCD, RegisterClass FPRCS>
4207   : NeonI_Scalar3Diff<u, size, opcode,
4208                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
4209                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4210                       [],
4211                       NoItinerary>;
4212
4213 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
4214   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
4215   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
4216 }
4217
4218 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
4219   let Constraints = "$Src = $Rd" in {
4220     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
4221                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
4222                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4223                        [],
4224                        NoItinerary>;
4225     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
4226                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
4227                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
4228                        [],
4229                        NoItinerary>;
4230   }
4231 }
4232
4233 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
4234                                              Instruction INSTH,
4235                                              Instruction INSTS> {
4236   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4237             (INSTH FPR16:$Rn, FPR16:$Rm)>;
4238   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4239             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4240 }
4241
4242 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
4243                                              Instruction INSTH,
4244                                              Instruction INSTS> {
4245   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
4246             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
4247   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
4248             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
4249 }
4250
4251 // Scalar Two Registers Miscellaneous
4252
4253 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
4254                              RegisterClass FPRCD, RegisterClass FPRCS>
4255   : NeonI_Scalar2SameMisc<u, size, opcode,
4256                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
4257                           !strconcat(asmop, "\t$Rd, $Rn"),
4258                           [],
4259                           NoItinerary>;
4260
4261 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
4262                                          string asmop> {
4263   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
4264                                       FPR32>;
4265   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
4266                                       FPR64>;
4267 }
4268
4269 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
4270   def dd : NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
4271 }
4272
4273 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
4274   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
4275   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
4276   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
4277   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
4278 }
4279
4280 class NeonI_Scalar2SameMisc_fcvtxn_D_size<bit u, bits<5> opcode, string asmop>
4281   : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR32, FPR64>;
4282
4283 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
4284                                                  string asmop> {
4285   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
4286   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
4287   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
4288 }
4289
4290 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
4291                                        string asmop, RegisterClass FPRC>
4292   : NeonI_Scalar2SameMisc<u, size, opcode,
4293                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
4294                           !strconcat(asmop, "\t$Rd, $Rn"),
4295                           [],
4296                           NoItinerary>;
4297
4298 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
4299                                                  string asmop> {
4300
4301   let Constraints = "$Src = $Rd" in {
4302     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
4303     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
4304     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
4305     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
4306   }
4307 }
4308
4309 class Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<SDPatternOperator opnode,
4310                                                   Instruction INSTD>
4311   : Pat<(f32 (opnode (f64 FPR64:$Rn))),
4312         (INSTD FPR64:$Rn)>;
4313
4314 multiclass Neon_Scalar2SameMisc_fcvt_SD_size_patterns<SDPatternOperator opnode,
4315                                                       Instruction INSTS,
4316                                                       Instruction INSTD> {
4317   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn))),
4318             (INSTS FPR32:$Rn)>;
4319   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn))),
4320             (INSTD FPR64:$Rn)>;
4321 }
4322
4323 class Neon_Scalar2SameMisc_vcvt_D_size_patterns<SDPatternOperator opnode,
4324                                                 Instruction INSTD>
4325   : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))),
4326             (INSTD FPR64:$Rn)>;
4327
4328 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator opnode,
4329                                                      Instruction INSTS,
4330                                                      Instruction INSTD> {
4331   def : Pat<(f32 (opnode (v1i32 FPR32:$Rn))),
4332             (INSTS FPR32:$Rn)>;
4333   def : Pat<(f64 (opnode (v1i64 FPR64:$Rn))),
4334             (INSTD FPR64:$Rn)>;
4335 }
4336
4337 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
4338                                                  Instruction INSTS,
4339                                                  Instruction INSTD> {
4340   def : Pat<(f32 (opnode (f32 FPR32:$Rn))),
4341             (INSTS FPR32:$Rn)>;
4342   def : Pat<(f64 (opnode (f64 FPR64:$Rn))),
4343             (INSTD FPR64:$Rn)>;
4344 }
4345
4346 class Neon_Scalar2SameMisc_V1_D_size_patterns<SDPatternOperator opnode,
4347                                               Instruction INSTD>
4348   : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
4349         (INSTD FPR64:$Rn)>;
4350
4351 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
4352   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4353                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
4354                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4355                           [],
4356                           NoItinerary>;
4357
4358 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
4359                                               string asmop> {
4360   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
4361                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
4362                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4363                            [],
4364                            NoItinerary>;
4365   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
4366                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz32:$FPImm),
4367                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
4368                            [],
4369                            NoItinerary>;
4370 }
4371
4372 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
4373                                                 Instruction INSTD>
4374   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4375                        (v1i64 (bitconvert (v8i8 Neon_AllZero))))),
4376         (INSTD FPR64:$Rn, 0)>;
4377
4378 class Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<CondCode CC,
4379                                                    Instruction INSTD>
4380   : Pat<(v1i64 (Neon_cmpz (v1i64 FPR64:$Rn),
4381                           (i32 neon_uimm0:$Imm), CC)),
4382         (INSTD FPR64:$Rn, neon_uimm0:$Imm)>;
4383
4384 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
4385                                                       Instruction INSTS,
4386                                                       Instruction INSTD> {
4387   def : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (f32 fpz32:$FPImm))),
4388             (INSTS FPR32:$Rn, fpz32:$FPImm)>;
4389   def : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (f32 fpz32:$FPImm))),
4390             (INSTD FPR64:$Rn, fpz32:$FPImm)>;
4391 }
4392
4393 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
4394                                                 Instruction INSTD> {
4395   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
4396             (INSTD FPR64:$Rn)>;
4397 }
4398
4399 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
4400                                                    Instruction INSTB,
4401                                                    Instruction INSTH,
4402                                                    Instruction INSTS,
4403                                                    Instruction INSTD>
4404   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
4405   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
4406             (INSTB FPR8:$Rn)>;
4407   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
4408             (INSTH FPR16:$Rn)>;
4409   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
4410             (INSTS FPR32:$Rn)>;
4411 }
4412
4413 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
4414                                                        SDPatternOperator opnode,
4415                                                        Instruction INSTH,
4416                                                        Instruction INSTS,
4417                                                        Instruction INSTD> {
4418   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
4419             (INSTH FPR16:$Rn)>;
4420   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
4421             (INSTS FPR32:$Rn)>;
4422   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
4423             (INSTD FPR64:$Rn)>;
4424
4425 }
4426
4427 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
4428                                                        SDPatternOperator opnode,
4429                                                        Instruction INSTB,
4430                                                        Instruction INSTH,
4431                                                        Instruction INSTS,
4432                                                        Instruction INSTD> {
4433   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
4434             (INSTB FPR8:$Src, FPR8:$Rn)>;
4435   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
4436             (INSTH FPR16:$Src, FPR16:$Rn)>;
4437   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
4438             (INSTS FPR32:$Src, FPR32:$Rn)>;
4439   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
4440             (INSTD FPR64:$Src, FPR64:$Rn)>;
4441 }
4442
4443 // Scalar Shift By Immediate
4444
4445 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
4446                                 RegisterClass FPRC, Operand ImmTy>
4447   : NeonI_ScalarShiftImm<u, opcode,
4448                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
4449                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4450                          [], NoItinerary>;
4451
4452 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
4453                                             string asmop> {
4454   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4455     bits<6> Imm;
4456     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4457     let Inst{21-16} = Imm;
4458   }
4459 }
4460
4461 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
4462                                                string asmop>
4463   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
4464   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
4465     bits<3> Imm;
4466     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4467     let Inst{18-16} = Imm;
4468   }
4469   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
4470     bits<4> Imm;
4471     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4472     let Inst{19-16} = Imm;
4473   }
4474   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4475     bits<5> Imm;
4476     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4477     let Inst{20-16} = Imm;
4478   }
4479 }
4480
4481 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
4482                                             string asmop> {
4483   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
4484     bits<6> Imm;
4485     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4486     let Inst{21-16} = Imm;
4487   }
4488 }
4489
4490 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4491                                               string asmop>
4492   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4493   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4494     bits<3> Imm;
4495     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4496     let Inst{18-16} = Imm;
4497   }
4498   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4499     bits<4> Imm;
4500     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4501     let Inst{19-16} = Imm;
4502   }
4503   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4504     bits<5> Imm;
4505     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4506     let Inst{20-16} = Imm;
4507   }
4508 }
4509
4510 class NeonI_ScalarShiftRightImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4511   : NeonI_ScalarShiftImm<u, opcode,
4512                          (outs FPR64:$Rd),
4513                          (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4514                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4515                          [], NoItinerary> {
4516     bits<6> Imm;
4517     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4518     let Inst{21-16} = Imm;
4519     let Constraints = "$Src = $Rd";
4520 }
4521
4522 class NeonI_ScalarShiftLeftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4523   : NeonI_ScalarShiftImm<u, opcode,
4524                          (outs FPR64:$Rd),
4525                          (ins FPR64:$Src, FPR64:$Rn, shl_imm64:$Imm),
4526                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4527                          [], NoItinerary> {
4528     bits<6> Imm;
4529     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4530     let Inst{21-16} = Imm;
4531     let Constraints = "$Src = $Rd";
4532 }
4533
4534 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4535                                        RegisterClass FPRCD, RegisterClass FPRCS,
4536                                        Operand ImmTy>
4537   : NeonI_ScalarShiftImm<u, opcode,
4538                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4539                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4540                          [], NoItinerary>;
4541
4542 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4543                                                 string asmop> {
4544   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4545                                              shr_imm8> {
4546     bits<3> Imm;
4547     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4548     let Inst{18-16} = Imm;
4549   }
4550   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4551                                              shr_imm16> {
4552     bits<4> Imm;
4553     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4554     let Inst{19-16} = Imm;
4555   }
4556   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4557                                              shr_imm32> {
4558     bits<5> Imm;
4559     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4560     let Inst{20-16} = Imm;
4561   }
4562 }
4563
4564 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4565   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4566     bits<5> Imm;
4567     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4568     let Inst{20-16} = Imm;
4569   }
4570   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4571     bits<6> Imm;
4572     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4573     let Inst{21-16} = Imm;
4574   }
4575 }
4576
4577 multiclass Neon_ScalarShiftRImm_D_size_patterns<SDPatternOperator opnode,
4578                                                Instruction INSTD> {
4579   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4580                 (INSTD FPR64:$Rn, imm:$Imm)>;
4581 }
4582
4583 multiclass Neon_ScalarShiftLImm_D_size_patterns<SDPatternOperator opnode,
4584                                                Instruction INSTD> {
4585   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 shl_imm64:$Imm))),
4586                 (INSTD FPR64:$Rn, imm:$Imm)>;
4587 }
4588
4589 class Neon_ScalarShiftImm_V1_D_size_patterns<SDPatternOperator opnode,
4590                                              Instruction INSTD>
4591   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
4592             (v1i64 (Neon_vdup (i32 shr_imm64:$Imm))))),
4593         (INSTD FPR64:$Rn, imm:$Imm)>;
4594
4595 multiclass Neon_ScalarShiftLImm_BHSD_size_patterns<SDPatternOperator opnode,
4596                                                    Instruction INSTB,
4597                                                    Instruction INSTH,
4598                                                    Instruction INSTS,
4599                                                    Instruction INSTD>
4600   : Neon_ScalarShiftLImm_D_size_patterns<opnode, INSTD> {
4601   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 shl_imm8:$Imm))),
4602                 (INSTB FPR8:$Rn, imm:$Imm)>;
4603   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 shl_imm16:$Imm))),
4604                 (INSTH FPR16:$Rn, imm:$Imm)>;
4605   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 shl_imm32:$Imm))),
4606                 (INSTS FPR32:$Rn, imm:$Imm)>;
4607 }
4608
4609 class Neon_ScalarShiftLImm_accum_D_size_patterns<SDPatternOperator opnode,
4610                                                 Instruction INSTD>
4611   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4612             (i32 shl_imm64:$Imm))),
4613         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4614
4615 class Neon_ScalarShiftRImm_accum_D_size_patterns<SDPatternOperator opnode,
4616                                                 Instruction INSTD>
4617   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn),
4618             (i32 shr_imm64:$Imm))),
4619         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4620
4621 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4622                                                        SDPatternOperator opnode,
4623                                                        Instruction INSTH,
4624                                                        Instruction INSTS,
4625                                                        Instruction INSTD> {
4626   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 shr_imm16:$Imm))),
4627                 (INSTH FPR16:$Rn, imm:$Imm)>;
4628   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4629                 (INSTS FPR32:$Rn, imm:$Imm)>;
4630   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4631                 (INSTD FPR64:$Rn, imm:$Imm)>;
4632 }
4633
4634 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator opnode,
4635                                                       Instruction INSTS,
4636                                                       Instruction INSTD> {
4637   def ssi : Pat<(f32 (opnode (v1i32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4638                 (INSTS FPR32:$Rn, imm:$Imm)>;
4639   def ddi : Pat<(f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4640                 (INSTD FPR64:$Rn, imm:$Imm)>;
4641 }
4642
4643 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator opnode,
4644                                                       Instruction INSTS,
4645                                                       Instruction INSTD> {
4646   def ssi : Pat<(v1i32 (opnode (f32 FPR32:$Rn), (i32 shr_imm32:$Imm))),
4647                 (INSTS FPR32:$Rn, imm:$Imm)>;
4648   def ddi : Pat<(v1i64 (opnode (f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4649                 (INSTD FPR64:$Rn, imm:$Imm)>;
4650 }
4651
4652 // Scalar Signed Shift Right (Immediate)
4653 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4654 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4655 // Pattern to match llvm.arm.* intrinsic.
4656 def : Neon_ScalarShiftImm_V1_D_size_patterns<sra, SSHRddi>;
4657
4658 // Scalar Unsigned Shift Right (Immediate)
4659 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4660 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4661 // Pattern to match llvm.arm.* intrinsic.
4662 def : Neon_ScalarShiftImm_V1_D_size_patterns<srl, USHRddi>;
4663
4664 // Scalar Signed Rounding Shift Right (Immediate)
4665 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4666 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vsrshr, SRSHRddi>;
4667
4668 // Scalar Unigned Rounding Shift Right (Immediate)
4669 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4670 defm : Neon_ScalarShiftRImm_D_size_patterns<int_aarch64_neon_vurshr, URSHRddi>;
4671
4672 // Scalar Signed Shift Right and Accumulate (Immediate)
4673 def SSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00010, "ssra">;
4674 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4675           <int_aarch64_neon_vsrads_n, SSRA>;
4676
4677 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4678 def USRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00010, "usra">;
4679 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4680           <int_aarch64_neon_vsradu_n, USRA>;
4681
4682 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4683 def SRSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b0, 0b00110, "srsra">;
4684 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4685           <int_aarch64_neon_vrsrads_n, SRSRA>;
4686
4687 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4688 def URSRA : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b00110, "ursra">;
4689 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4690           <int_aarch64_neon_vrsradu_n, URSRA>;
4691
4692 // Scalar Shift Left (Immediate)
4693 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4694 defm : Neon_ScalarShiftLImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4695 // Pattern to match llvm.arm.* intrinsic.
4696 def : Neon_ScalarShiftImm_V1_D_size_patterns<shl, SHLddi>;
4697
4698 // Signed Saturating Shift Left (Immediate)
4699 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4700 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4701                                                SQSHLbbi, SQSHLhhi,
4702                                                SQSHLssi, SQSHLddi>;
4703 // Pattern to match llvm.arm.* intrinsic.
4704 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_sqrshlImm, SQSHLddi>;
4705
4706 // Unsigned Saturating Shift Left (Immediate)
4707 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4708 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4709                                                UQSHLbbi, UQSHLhhi,
4710                                                UQSHLssi, UQSHLddi>;
4711 // Pattern to match llvm.arm.* intrinsic.
4712 defm : Neon_ScalarShiftLImm_D_size_patterns<Neon_uqrshlImm, UQSHLddi>;
4713
4714 // Signed Saturating Shift Left Unsigned (Immediate)
4715 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4716 defm : Neon_ScalarShiftLImm_BHSD_size_patterns<int_aarch64_neon_vsqshlu,
4717                                                SQSHLUbbi, SQSHLUhhi,
4718                                                SQSHLUssi, SQSHLUddi>;
4719
4720 // Shift Right And Insert (Immediate)
4721 def SRI : NeonI_ScalarShiftRightImm_accum_D_size<0b1, 0b01000, "sri">;
4722 def : Neon_ScalarShiftRImm_accum_D_size_patterns
4723           <int_aarch64_neon_vsri, SRI>;
4724
4725 // Shift Left And Insert (Immediate)
4726 def SLI : NeonI_ScalarShiftLeftImm_accum_D_size<0b1, 0b01010, "sli">;
4727 def : Neon_ScalarShiftLImm_accum_D_size_patterns
4728           <int_aarch64_neon_vsli, SLI>;
4729
4730 // Signed Saturating Shift Right Narrow (Immediate)
4731 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4732 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4733                                                     SQSHRNbhi, SQSHRNhsi,
4734                                                     SQSHRNsdi>;
4735
4736 // Unsigned Saturating Shift Right Narrow (Immediate)
4737 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4738 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4739                                                     UQSHRNbhi, UQSHRNhsi,
4740                                                     UQSHRNsdi>;
4741
4742 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4743 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4744 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4745                                                     SQRSHRNbhi, SQRSHRNhsi,
4746                                                     SQRSHRNsdi>;
4747
4748 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4749 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4750 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4751                                                     UQRSHRNbhi, UQRSHRNhsi,
4752                                                     UQRSHRNsdi>;
4753
4754 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4755 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4756 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4757                                                     SQSHRUNbhi, SQSHRUNhsi,
4758                                                     SQSHRUNsdi>;
4759
4760 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4761 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4762 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4763                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4764                                                     SQRSHRUNsdi>;
4765
4766 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4767 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4768 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxs2fp_n,
4769                                                   SCVTF_Nssi, SCVTF_Nddi>;
4770
4771 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4772 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4773 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtfxu2fp_n,
4774                                                   UCVTF_Nssi, UCVTF_Nddi>;
4775
4776 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4777 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4778 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxs_n,
4779                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4780
4781 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4782 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4783 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvtfp2fxu_n,
4784                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4785
4786 // Patterns For Convert Instructions Between v1f64 and v1i64
4787 class Neon_ScalarShiftImm_cvtf_v1f64_pattern<SDPatternOperator opnode,
4788                                              Instruction INST>
4789     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4790           (INST FPR64:$Rn, imm:$Imm)>;
4791
4792 class Neon_ScalarShiftImm_fcvt_v1f64_pattern<SDPatternOperator opnode,
4793                                              Instruction INST>
4794     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (i32 shr_imm64:$Imm))),
4795           (INST FPR64:$Rn, imm:$Imm)>;
4796
4797 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxs2fp,
4798                                              SCVTF_Nddi>;
4799
4800 def : Neon_ScalarShiftImm_cvtf_v1f64_pattern<int_arm_neon_vcvtfxu2fp,
4801                                              UCVTF_Nddi>;
4802
4803 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxs,
4804                                              FCVTZS_Nddi>;
4805
4806 def : Neon_ScalarShiftImm_fcvt_v1f64_pattern<int_arm_neon_vcvtfp2fxu,
4807                                              FCVTZU_Nddi>;
4808
4809 // Scalar Integer Add
4810 let isCommutable = 1 in {
4811 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4812 }
4813
4814 // Scalar Integer Sub
4815 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4816
4817 // Pattern for Scalar Integer Add and Sub with D register only
4818 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4819 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4820
4821 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4822 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4823 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4824 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4825 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4826
4827 // Scalar Integer Saturating Add (Signed, Unsigned)
4828 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4829 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4830
4831 // Scalar Integer Saturating Sub (Signed, Unsigned)
4832 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4833 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4834
4835
4836 // Patterns to match llvm.aarch64.* intrinsic for
4837 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
4838 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqadds, SQADDbbb,
4839                                            SQADDhhh, SQADDsss, SQADDddd>;
4840 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqaddu, UQADDbbb,
4841                                            UQADDhhh, UQADDsss, UQADDddd>;
4842 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubs, SQSUBbbb,
4843                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
4844 defm : Neon_Scalar3Same_BHSD_size_patterns<int_arm_neon_vqsubu, UQSUBbbb,
4845                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
4846
4847 // Scalar Integer Saturating Doubling Multiply Half High
4848 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4849
4850 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4851 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4852
4853 // Patterns to match llvm.arm.* intrinsic for
4854 // Scalar Integer Saturating Doubling Multiply Half High and
4855 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4856 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4857                                                                SQDMULHsss>;
4858 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4859                                                                 SQRDMULHsss>;
4860
4861 // Scalar Floating-point Multiply Extended
4862 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4863
4864 // Scalar Floating-point Reciprocal Step
4865 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4866 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrecps, f32, f32,
4867                                          FRECPSsss, f64, f64, FRECPSddd>;
4868 def : Pat<(v1f64 (int_arm_neon_vrecps (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4869           (FRECPSddd FPR64:$Rn, FPR64:$Rm)>;
4870
4871 // Scalar Floating-point Reciprocal Square Root Step
4872 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4873 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vrsqrts, f32, f32,
4874                                          FRSQRTSsss, f64, f64, FRSQRTSddd>;
4875 def : Pat<(v1f64 (int_arm_neon_vrsqrts (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4876           (FRSQRTSddd FPR64:$Rn, FPR64:$Rm)>;
4877 def : Pat<(v1f64 (fsqrt (v1f64 FPR64:$Rn))), (FSQRTdd FPR64:$Rn)>;
4878
4879 // Patterns to match llvm.aarch64.* intrinsic for
4880 // Scalar Floating-point Multiply Extended,
4881 multiclass Neon_Scalar3Same_MULX_SD_size_patterns<SDPatternOperator opnode,
4882                                                   Instruction INSTS,
4883                                                   Instruction INSTD> {
4884   def : Pat<(f32 (opnode (f32 FPR32:$Rn), (f32 FPR32:$Rm))),
4885             (INSTS FPR32:$Rn, FPR32:$Rm)>;
4886   def : Pat<(f64 (opnode (f64 FPR64:$Rn), (f64 FPR64:$Rm))),
4887             (INSTD FPR64:$Rn, FPR64:$Rm)>;
4888 }
4889
4890 defm : Neon_Scalar3Same_MULX_SD_size_patterns<int_aarch64_neon_vmulx,
4891                                               FMULXsss,FMULXddd>;
4892
4893 // Scalar Integer Shift Left (Signed, Unsigned)
4894 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4895 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4896
4897 // Patterns to match llvm.arm.* intrinsic for
4898 // Scalar Integer Shift Left (Signed, Unsigned)
4899 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4900 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4901
4902 // Patterns to match llvm.aarch64.* intrinsic for
4903 // Scalar Integer Shift Left (Signed, Unsigned)
4904 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4905 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4906
4907 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4908 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4909 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4910
4911 // Patterns to match llvm.aarch64.* intrinsic for
4912 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4913 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4914                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
4915 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4916                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
4917
4918 // Patterns to match llvm.arm.* intrinsic for
4919 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4920 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4921 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4922
4923 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4924 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4925 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4926
4927 // Patterns to match llvm.aarch64.* intrinsic for
4928 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4929 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4930 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4931
4932 // Patterns to match llvm.arm.* intrinsic for
4933 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4934 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4935 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4936
4937 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4938 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4939 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4940
4941 // Patterns to match llvm.aarch64.* intrinsic for
4942 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4943 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4944                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4945 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4946                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4947
4948 // Patterns to match llvm.arm.* intrinsic for
4949 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4950 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4951 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4952
4953 // Signed Saturating Doubling Multiply-Add Long
4954 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4955 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4956                                             SQDMLALshh, SQDMLALdss>;
4957
4958 // Signed Saturating Doubling Multiply-Subtract Long
4959 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4960 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4961                                             SQDMLSLshh, SQDMLSLdss>;
4962
4963 // Signed Saturating Doubling Multiply Long
4964 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4965 defm : Neon_Scalar3Diff_HS_size_patterns<int_arm_neon_vqdmull,
4966                                          SQDMULLshh, SQDMULLdss>;
4967
4968 // Scalar Signed Integer Convert To Floating-point
4969 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4970 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fps,
4971                                                  SCVTFss, SCVTFdd>;
4972
4973 // Scalar Unsigned Integer Convert To Floating-point
4974 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4975 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtint2fpu,
4976                                                  UCVTFss, UCVTFdd>;
4977
4978 // Scalar Floating-point Converts
4979 def FCVTXN : NeonI_Scalar2SameMisc_fcvtxn_D_size<0b1, 0b10110, "fcvtxn">;
4980 def : Neon_Scalar2SameMisc_fcvtxn_D_size_patterns<int_aarch64_neon_fcvtxn,
4981                                                   FCVTXN>;
4982
4983 defm FCVTNS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11010, "fcvtns">;
4984 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtns,
4985                                                   FCVTNSss, FCVTNSdd>;
4986 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtns, FCVTNSdd>;
4987
4988 defm FCVTNU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11010, "fcvtnu">;
4989 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtnu,
4990                                                   FCVTNUss, FCVTNUdd>;
4991 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtnu, FCVTNUdd>;
4992
4993 defm FCVTMS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11011, "fcvtms">;
4994 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtms,
4995                                                   FCVTMSss, FCVTMSdd>;
4996 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtms, FCVTMSdd>;
4997
4998 defm FCVTMU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11011, "fcvtmu">;
4999 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtmu,
5000                                                   FCVTMUss, FCVTMUdd>;
5001 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtmu, FCVTMUdd>;
5002
5003 defm FCVTAS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11100, "fcvtas">;
5004 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtas,
5005                                                   FCVTASss, FCVTASdd>;
5006 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtas, FCVTASdd>;
5007
5008 defm FCVTAU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11100, "fcvtau">;
5009 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtau,
5010                                                   FCVTAUss, FCVTAUdd>;
5011 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtau, FCVTAUdd>;
5012
5013 defm FCVTPS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11010, "fcvtps">;
5014 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtps,
5015                                                   FCVTPSss, FCVTPSdd>;
5016 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtps, FCVTPSdd>;
5017
5018 defm FCVTPU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11010, "fcvtpu">;
5019 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtpu,
5020                                                   FCVTPUss, FCVTPUdd>;
5021 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_arm_neon_vcvtpu, FCVTPUdd>;
5022
5023 defm FCVTZS : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11011, "fcvtzs">;
5024 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzs,
5025                                                   FCVTZSss, FCVTZSdd>;
5026 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzs,
5027                                                 FCVTZSdd>;
5028
5029 defm FCVTZU : NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11011, "fcvtzu">;
5030 defm : Neon_Scalar2SameMisc_fcvt_SD_size_patterns<int_aarch64_neon_fcvtzu,
5031                                                   FCVTZUss, FCVTZUdd>;
5032 def : Neon_Scalar2SameMisc_vcvt_D_size_patterns<int_aarch64_neon_vcvtzu,
5033                                                 FCVTZUdd>;
5034
5035 // Patterns For Convert Instructions Between v1f64 and v1i64
5036 class Neon_Scalar2SameMisc_cvtf_v1f64_pattern<SDPatternOperator opnode,
5037                                               Instruction INST>
5038     : Pat<(v1f64 (opnode (v1i64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5039
5040 class Neon_Scalar2SameMisc_fcvt_v1f64_pattern<SDPatternOperator opnode,
5041                                               Instruction INST>
5042     : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5043
5044 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<sint_to_fp, SCVTFdd>;
5045 def : Neon_Scalar2SameMisc_cvtf_v1f64_pattern<uint_to_fp, UCVTFdd>;
5046
5047 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_sint, FCVTZSdd>;
5048 def : Neon_Scalar2SameMisc_fcvt_v1f64_pattern<fp_to_uint, FCVTZUdd>;
5049
5050 // Scalar Floating-point Reciprocal Estimate
5051 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
5052 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpe,
5053                                              FRECPEss, FRECPEdd>;
5054 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrecpe,
5055                                               FRECPEdd>;
5056
5057 // Scalar Floating-point Reciprocal Exponent
5058 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
5059 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
5060                                              FRECPXss, FRECPXdd>;
5061
5062 // Scalar Floating-point Reciprocal Square Root Estimate
5063 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
5064 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrsqrte,
5065                                                  FRSQRTEss, FRSQRTEdd>;
5066 def : Neon_Scalar2SameMisc_V1_D_size_patterns<int_arm_neon_vrsqrte,
5067                                               FRSQRTEdd>;
5068
5069 // Scalar Floating-point Round
5070 class Neon_ScalarFloatRound_pattern<SDPatternOperator opnode, Instruction INST>
5071     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5072
5073 def : Neon_ScalarFloatRound_pattern<fceil, FRINTPdd>;
5074 def : Neon_ScalarFloatRound_pattern<ffloor, FRINTMdd>;
5075 def : Neon_ScalarFloatRound_pattern<ftrunc, FRINTZdd>;
5076 def : Neon_ScalarFloatRound_pattern<frint, FRINTXdd>;
5077 def : Neon_ScalarFloatRound_pattern<fnearbyint, FRINTIdd>;
5078 def : Neon_ScalarFloatRound_pattern<frnd, FRINTAdd>;
5079 def : Neon_ScalarFloatRound_pattern<int_aarch64_neon_frintn, FRINTNdd>;
5080
5081 // Scalar Integer Compare
5082
5083 // Scalar Compare Bitwise Equal
5084 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
5085 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
5086
5087 class Neon_Scalar3Same_cmp_D_size_v1_patterns<SDPatternOperator opnode,
5088                                               Instruction INSTD,
5089                                               CondCode CC>
5090   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm), CC)),
5091         (INSTD FPR64:$Rn, FPR64:$Rm)>;
5092
5093 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMEQddd, SETEQ>;
5094
5095 // Scalar Compare Signed Greather Than Or Equal
5096 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
5097 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
5098 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGEddd, SETGE>;
5099
5100 // Scalar Compare Unsigned Higher Or Same
5101 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
5102 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
5103 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHSddd, SETUGE>;
5104
5105 // Scalar Compare Unsigned Higher
5106 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
5107 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
5108 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMHIddd, SETUGT>;
5109
5110 // Scalar Compare Signed Greater Than
5111 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
5112 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
5113 def : Neon_Scalar3Same_cmp_D_size_v1_patterns<Neon_cmp, CMGTddd, SETGT>;
5114
5115 // Scalar Compare Bitwise Test Bits
5116 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
5117 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
5118 defm : Neon_Scalar3Same_D_size_patterns<Neon_tst, CMTSTddd>;
5119
5120 // Scalar Compare Bitwise Equal To Zero
5121 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
5122 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
5123                                                 CMEQddi>;
5124 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETEQ, CMEQddi>;
5125
5126 // Scalar Compare Signed Greather Than Or Equal To Zero
5127 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
5128 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
5129                                                 CMGEddi>;
5130 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGE, CMGEddi>;
5131
5132 // Scalar Compare Signed Greater Than Zero
5133 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
5134 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
5135                                                 CMGTddi>;
5136 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETGT, CMGTddi>;
5137
5138 // Scalar Compare Signed Less Than Or Equal To Zero
5139 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
5140 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
5141                                                 CMLEddi>;
5142 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLE, CMLEddi>;
5143
5144 // Scalar Compare Less Than Zero
5145 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
5146 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
5147                                                 CMLTddi>;
5148 def : Neon_Scalar2SameMisc_cmpz_D_V1_size_patterns<SETLT, CMLTddi>;
5149
5150 // Scalar Floating-point Compare
5151
5152 // Scalar Floating-point Compare Mask Equal
5153 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
5154 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fceq, v1i32, f32,
5155                                          FCMEQsss, v1i64, f64, FCMEQddd>;
5156 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETEQ, FCMEQddd>;
5157
5158 // Scalar Floating-point Compare Mask Equal To Zero
5159 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
5160 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fceq,
5161                                                   FCMEQZssi, FCMEQZddi>;
5162 def : Pat<(v1i64 (Neon_cmpz (v1f64 FPR64:$Rn), (f32 fpz32:$FPImm), SETEQ)),
5163           (FCMEQZddi FPR64:$Rn, fpz32:$FPImm)>;
5164
5165 // Scalar Floating-point Compare Mask Greater Than Or Equal
5166 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
5167 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcge, v1i32, f32,
5168                                          FCMGEsss, v1i64, f64, FCMGEddd>;
5169 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGE, FCMGEddd>;
5170
5171 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
5172 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
5173 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcge,
5174                                                   FCMGEZssi, FCMGEZddi>;
5175
5176 // Scalar Floating-point Compare Mask Greather Than
5177 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
5178 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcgt, v1i32, f32,
5179                                          FCMGTsss, v1i64, f64, FCMGTddd>;
5180 def : Neon_Scalar3Same_cmp_V1_D_size_patterns<SETGT, FCMGTddd>;
5181
5182 // Scalar Floating-point Compare Mask Greather Than Zero
5183 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
5184 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcgt,
5185                                                   FCMGTZssi, FCMGTZddi>;
5186
5187 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
5188 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
5189 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fclez,
5190                                                   FCMLEZssi, FCMLEZddi>;
5191
5192 // Scalar Floating-point Compare Mask Less Than Zero
5193 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
5194 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_fcltz,
5195                                                   FCMLTZssi, FCMLTZddi>;
5196
5197 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
5198 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
5199 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcage, v1i32, f32,
5200                                          FACGEsss, v1i64, f64, FACGEddd>;
5201 def : Pat<(v1i64 (int_aarch64_neon_vcage (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5202           (FACGEddd FPR64:$Rn, FPR64:$Rm)>;
5203
5204 // Scalar Floating-point Absolute Compare Mask Greater Than
5205 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
5206 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_fcagt, v1i32, f32,
5207                                          FACGTsss, v1i64, f64, FACGTddd>;
5208 def : Pat<(v1i64 (int_aarch64_neon_vcagt (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5209           (FACGTddd FPR64:$Rn, FPR64:$Rm)>;
5210
5211 // Scalar Floating-point Absolute Difference
5212 defm FABD: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11010, "fabd">;
5213 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vabd, f32, f32,
5214                                          FABDsss, f64, f64, FABDddd>;
5215
5216 // Scalar Absolute Value
5217 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
5218 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
5219
5220 // Scalar Signed Saturating Absolute Value
5221 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
5222 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
5223                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
5224
5225 // Scalar Negate
5226 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
5227 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
5228
5229 // Scalar Signed Saturating Negate
5230 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
5231 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
5232                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
5233
5234 // Scalar Signed Saturating Accumulated of Unsigned Value
5235 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
5236 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
5237                                                      SUQADDbb, SUQADDhh,
5238                                                      SUQADDss, SUQADDdd>;
5239
5240 // Scalar Unsigned Saturating Accumulated of Signed Value
5241 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
5242 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
5243                                                      USQADDbb, USQADDhh,
5244                                                      USQADDss, USQADDdd>;
5245
5246 def : Pat<(v1i64 (int_aarch64_neon_suqadd (v1i64 FPR64:$Src),
5247                                           (v1i64 FPR64:$Rn))),
5248           (SUQADDdd FPR64:$Src, FPR64:$Rn)>;
5249
5250 def : Pat<(v1i64 (int_aarch64_neon_usqadd (v1i64 FPR64:$Src),
5251                                           (v1i64 FPR64:$Rn))),
5252           (USQADDdd FPR64:$Src, FPR64:$Rn)>;
5253
5254 def : Pat<(v1i64 (int_arm_neon_vabs (v1i64 FPR64:$Rn))),
5255           (ABSdd FPR64:$Rn)>;
5256
5257 def : Pat<(v1i64 (int_arm_neon_vqabs (v1i64 FPR64:$Rn))),
5258           (SQABSdd FPR64:$Rn)>;
5259
5260 def : Pat<(v1i64 (int_arm_neon_vqneg (v1i64 FPR64:$Rn))),
5261           (SQNEGdd FPR64:$Rn)>;
5262
5263 def : Pat<(v1i64 (sub (v1i64 (bitconvert (v8i8 Neon_AllZero))),
5264                       (v1i64 FPR64:$Rn))),
5265           (NEGdd FPR64:$Rn)>;
5266
5267 // Scalar Signed Saturating Extract Unsigned Narrow
5268 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
5269 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
5270                                                      SQXTUNbh, SQXTUNhs,
5271                                                      SQXTUNsd>;
5272
5273 // Scalar Signed Saturating Extract Narrow
5274 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
5275 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
5276                                                      SQXTNbh, SQXTNhs,
5277                                                      SQXTNsd>;
5278
5279 // Scalar Unsigned Saturating Extract Narrow
5280 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
5281 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
5282                                                      UQXTNbh, UQXTNhs,
5283                                                      UQXTNsd>;
5284
5285 // Scalar Reduce Pairwise
5286
5287 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
5288                                      string asmop, bit Commutable = 0> {
5289   let isCommutable = Commutable in {
5290     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
5291                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
5292                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
5293                                 [],
5294                                 NoItinerary>;
5295   }
5296 }
5297
5298 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
5299                                      string asmop, bit Commutable = 0>
5300   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
5301   let isCommutable = Commutable in {
5302     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
5303                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
5304                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
5305                                 [],
5306                                 NoItinerary>;
5307   }
5308 }
5309
5310 // Scalar Reduce Addition Pairwise (Integer) with
5311 // Pattern to match llvm.arm.* intrinsic
5312 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
5313
5314 // Pattern to match llvm.aarch64.* intrinsic for
5315 // Scalar Reduce Addition Pairwise (Integer)
5316 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
5317           (ADDPvv_D_2D VPR128:$Rn)>;
5318 def : Pat<(v1i64 (int_aarch64_neon_vaddv (v2i64 VPR128:$Rn))),
5319           (ADDPvv_D_2D VPR128:$Rn)>;
5320
5321 // Scalar Reduce Addition Pairwise (Floating Point)
5322 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
5323
5324 // Scalar Reduce Maximum Pairwise (Floating Point)
5325 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
5326
5327 // Scalar Reduce Minimum Pairwise (Floating Point)
5328 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
5329
5330 // Scalar Reduce maxNum Pairwise (Floating Point)
5331 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
5332
5333 // Scalar Reduce minNum Pairwise (Floating Point)
5334 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
5335
5336 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnode,
5337                                             Instruction INSTS,
5338                                             Instruction INSTD> {
5339   def : Pat<(f32 (opnode (v2f32 VPR64:$Rn))),
5340             (INSTS VPR64:$Rn)>;
5341   def : Pat<(f64 (opnode (v2f64 VPR128:$Rn))),
5342             (INSTD VPR128:$Rn)>;
5343 }
5344
5345 // Patterns to match llvm.aarch64.* intrinsic for
5346 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
5347 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
5348                                         FADDPvv_S_2S, FADDPvv_D_2D>;
5349
5350 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
5351                                         FMAXPvv_S_2S, FMAXPvv_D_2D>;
5352
5353 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
5354                                         FMINPvv_S_2S, FMINPvv_D_2D>;
5355
5356 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
5357                                         FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
5358
5359 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
5360                                         FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
5361
5362 def : Pat<(f32 (int_aarch64_neon_vpfadd (v4f32 VPR128:$Rn))),
5363           (FADDPvv_S_2S (v2f32
5364                (EXTRACT_SUBREG
5365                    (v4f32 (FADDP_4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rn))),
5366                    sub_64)))>;
5367
5368 // Scalar by element Arithmetic
5369
5370 class NeonI_ScalarXIndexedElemArith<string asmop, bits<4> opcode,
5371                                     string rmlane, bit u, bit szhi, bit szlo,
5372                                     RegisterClass ResFPR, RegisterClass OpFPR,
5373                                     RegisterOperand OpVPR, Operand OpImm>
5374   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5375                              (outs ResFPR:$Rd),
5376                              (ins OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5377                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5378                              [],
5379                              NoItinerary> {
5380   bits<3> Imm;
5381   bits<5> MRm;
5382 }
5383
5384 class NeonI_ScalarXIndexedElemArith_Constraint_Impl<string asmop, bits<4> opcode,
5385                                                     string rmlane,
5386                                                     bit u, bit szhi, bit szlo,
5387                                                     RegisterClass ResFPR,
5388                                                     RegisterClass OpFPR,
5389                                                     RegisterOperand OpVPR,
5390                                                     Operand OpImm>
5391   : NeonI_ScalarXIndexedElem<u, szhi, szlo, opcode,
5392                              (outs ResFPR:$Rd),
5393                              (ins ResFPR:$src, OpFPR:$Rn, OpVPR:$MRm, OpImm:$Imm),
5394                              asmop # "\t$Rd, $Rn, $MRm" # rmlane # "[$Imm]",
5395                              [],
5396                              NoItinerary> {
5397   let Constraints = "$src = $Rd";
5398   bits<3> Imm;
5399   bits<5> MRm;
5400 }
5401
5402 // Scalar Floating Point  multiply (scalar, by element)
5403 def FMULssv_4S : NeonI_ScalarXIndexedElemArith<"fmul",
5404   0b1001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5405   let Inst{11} = Imm{1}; // h
5406   let Inst{21} = Imm{0}; // l
5407   let Inst{20-16} = MRm;
5408 }
5409 def FMULddv_2D : NeonI_ScalarXIndexedElemArith<"fmul",
5410   0b1001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5411   let Inst{11} = Imm{0}; // h
5412   let Inst{21} = 0b0;    // l
5413   let Inst{20-16} = MRm;
5414 }
5415
5416 // Scalar Floating Point  multiply extended (scalar, by element)
5417 def FMULXssv_4S : NeonI_ScalarXIndexedElemArith<"fmulx",
5418   0b1001, ".s", 0b1, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5419   let Inst{11} = Imm{1}; // h
5420   let Inst{21} = Imm{0}; // l
5421   let Inst{20-16} = MRm;
5422 }
5423 def FMULXddv_2D : NeonI_ScalarXIndexedElemArith<"fmulx",
5424   0b1001, ".d", 0b1, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5425   let Inst{11} = Imm{0}; // h
5426   let Inst{21} = 0b0;    // l
5427   let Inst{20-16} = MRm;
5428 }
5429
5430 multiclass Neon_ScalarXIndexedElem_MUL_MULX_Patterns<
5431   SDPatternOperator opnode,
5432   Instruction INST,
5433   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5434   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5435
5436   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5437                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)))),
5438              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5439
5440   def  : Pat<(ResTy (opnode (ResTy FPRC:$Rn),
5441                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)))),
5442              (ResTy (INST (ResTy FPRC:$Rn),
5443                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5444                OpNImm:$Imm))>;
5445
5446   // swapped operands
5447   def  : Pat<(ResTy (opnode
5448                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5449                (ResTy FPRC:$Rn))),
5450              (ResTy (INST (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5451
5452   def  : Pat<(ResTy (opnode
5453                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5454                (ResTy FPRC:$Rn))),
5455              (ResTy (INST (ResTy FPRC:$Rn),
5456                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5457                OpNImm:$Imm))>;
5458 }
5459
5460 // Patterns for Scalar Floating Point  multiply (scalar, by element)
5461 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULssv_4S,
5462   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5463 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<fmul, FMULddv_2D,
5464   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5465
5466 // Patterns for Scalar Floating Point  multiply extended (scalar, by element)
5467 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5468   FMULXssv_4S, f32, FPR32, v4f32, neon_uimm2_bare,
5469   v2f32, v4f32, neon_uimm1_bare>;
5470 defm : Neon_ScalarXIndexedElem_MUL_MULX_Patterns<int_aarch64_neon_vmulx,
5471   FMULXddv_2D, f64, FPR64, v2f64, neon_uimm1_bare,
5472   v1f64, v2f64, neon_uimm0_bare>;
5473
5474 // Scalar Floating Point fused multiply-add (scalar, by element)
5475 def FMLAssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5476   0b0001, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5477   let Inst{11} = Imm{1}; // h
5478   let Inst{21} = Imm{0}; // l
5479   let Inst{20-16} = MRm;
5480 }
5481 def FMLAddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmla",
5482   0b0001, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5483   let Inst{11} = Imm{0}; // h
5484   let Inst{21} = 0b0;    // l
5485   let Inst{20-16} = MRm;
5486 }
5487
5488 // Scalar Floating Point fused multiply-subtract (scalar, by element)
5489 def FMLSssv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5490   0b0101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5491   let Inst{11} = Imm{1}; // h
5492   let Inst{21} = Imm{0}; // l
5493   let Inst{20-16} = MRm;
5494 }
5495 def FMLSddv_2D : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"fmls",
5496   0b0101, ".d", 0b0, 0b1, 0b1, FPR64, FPR64, VPR128, neon_uimm1_bare> {
5497   let Inst{11} = Imm{0}; // h
5498   let Inst{21} = 0b0;    // l
5499   let Inst{20-16} = MRm;
5500 }
5501 // We are allowed to match the fma instruction regardless of compile options.
5502 multiclass Neon_ScalarXIndexedElem_FMA_Patterns<
5503   Instruction FMLAI, Instruction FMLSI,
5504   ValueType ResTy, RegisterClass FPRC, ValueType OpTy, Operand OpImm,
5505   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5506   // fmla
5507   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5508                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5509                (ResTy FPRC:$Ra))),
5510              (ResTy (FMLAI (ResTy FPRC:$Ra),
5511                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5512
5513   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5514                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5515                (ResTy FPRC:$Ra))),
5516              (ResTy (FMLAI (ResTy FPRC:$Ra),
5517                (ResTy FPRC:$Rn),
5518                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5519                OpNImm:$Imm))>;
5520
5521   // swapped fmla operands
5522   def  : Pat<(ResTy (fma
5523                (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm)),
5524                (ResTy FPRC:$Rn),
5525                (ResTy FPRC:$Ra))),
5526              (ResTy (FMLAI (ResTy FPRC:$Ra),
5527                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5528
5529   def  : Pat<(ResTy (fma
5530                (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm)),
5531                (ResTy FPRC:$Rn),
5532                (ResTy FPRC:$Ra))),
5533              (ResTy (FMLAI (ResTy FPRC:$Ra),
5534                (ResTy FPRC:$Rn),
5535                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5536                OpNImm:$Imm))>;
5537
5538   // fmls
5539   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5540                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5541                (ResTy FPRC:$Ra))),
5542              (ResTy (FMLSI (ResTy FPRC:$Ra),
5543                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5544
5545   def  : Pat<(ResTy (fma (ResTy FPRC:$Rn),
5546                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5547                (ResTy FPRC:$Ra))),
5548              (ResTy (FMLSI (ResTy FPRC:$Ra),
5549                (ResTy FPRC:$Rn),
5550                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5551                OpNImm:$Imm))>;
5552
5553   // swapped fmls operands
5554   def  : Pat<(ResTy (fma
5555                (fneg (ResTy (vector_extract (OpTy VPR128:$MRm), OpImm:$Imm))),
5556                (ResTy FPRC:$Rn),
5557                (ResTy FPRC:$Ra))),
5558              (ResTy (FMLSI (ResTy FPRC:$Ra),
5559                (ResTy FPRC:$Rn), (OpTy VPR128:$MRm), OpImm:$Imm))>;
5560
5561   def  : Pat<(ResTy (fma
5562                (fneg (ResTy (vector_extract (OpNTy VPR64:$MRm), OpNImm:$Imm))),
5563                (ResTy FPRC:$Rn),
5564                (ResTy FPRC:$Ra))),
5565              (ResTy (FMLSI (ResTy FPRC:$Ra),
5566                (ResTy FPRC:$Rn),
5567                (ExTy (SUBREG_TO_REG (i64 0), VPR64:$MRm, sub_64)),
5568                OpNImm:$Imm))>;
5569 }
5570
5571 // Scalar Floating Point fused multiply-add and
5572 // multiply-subtract (scalar, by element)
5573 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAssv_4S, FMLSssv_4S,
5574   f32, FPR32, v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5575 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5576   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5577 defm : Neon_ScalarXIndexedElem_FMA_Patterns<FMLAddv_2D, FMLSddv_2D,
5578   f64, FPR64, v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5579
5580 // Scalar Signed saturating doubling multiply long (scalar, by element)
5581 def SQDMULLshv_4H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5582   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5583   let Inst{11} = 0b0; // h
5584   let Inst{21} = Imm{1}; // l
5585   let Inst{20} = Imm{0}; // m
5586   let Inst{19-16} = MRm{3-0};
5587 }
5588 def SQDMULLshv_8H : NeonI_ScalarXIndexedElemArith<"sqdmull",
5589   0b1011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5590   let Inst{11} = Imm{2}; // h
5591   let Inst{21} = Imm{1}; // l
5592   let Inst{20} = Imm{0}; // m
5593   let Inst{19-16} = MRm{3-0};
5594 }
5595 def SQDMULLdsv_2S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5596   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5597   let Inst{11} = 0b0;    // h
5598   let Inst{21} = Imm{0}; // l
5599   let Inst{20-16} = MRm;
5600 }
5601 def SQDMULLdsv_4S : NeonI_ScalarXIndexedElemArith<"sqdmull",
5602   0b1011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5603   let Inst{11} = Imm{1};    // h
5604   let Inst{21} = Imm{0};    // l
5605   let Inst{20-16} = MRm;
5606 }
5607
5608 multiclass Neon_ScalarXIndexedElem_MUL_Patterns<
5609   SDPatternOperator opnode,
5610   Instruction INST,
5611   ValueType ResTy, RegisterClass FPRC,
5612   ValueType OpVTy, ValueType OpTy,
5613   ValueType VecOpTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5614
5615   def  : Pat<(ResTy (opnode (OpVTy FPRC:$Rn),
5616                (OpVTy (scalar_to_vector
5617                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))))),
5618              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5619
5620   //swapped operands
5621   def  : Pat<(ResTy (opnode
5622                (OpVTy (scalar_to_vector
5623                  (ExTy (vector_extract (VecOpTy VPRC:$MRm), OpImm:$Imm)))),
5624                  (OpVTy FPRC:$Rn))),
5625              (ResTy (INST (OpVTy FPRC:$Rn), (VecOpTy VPRC:$MRm), OpImm:$Imm))>;
5626 }
5627
5628
5629 // Patterns for Scalar Signed saturating doubling
5630 // multiply long (scalar, by element)
5631 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5632   SQDMULLshv_4H, v1i32, FPR16, v1i16, i16, v4i16,
5633   i32, VPR64Lo, neon_uimm2_bare>;
5634 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5635   SQDMULLshv_8H, v1i32, FPR16, v1i16, i16, v8i16,
5636   i32, VPR128Lo, neon_uimm3_bare>;
5637 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5638   SQDMULLdsv_2S, v1i64, FPR32, v1i32, i32, v2i32,
5639   i32, VPR64Lo, neon_uimm1_bare>;
5640 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmull,
5641   SQDMULLdsv_4S, v1i64, FPR32, v1i32, i32, v4i32,
5642   i32, VPR128Lo, neon_uimm2_bare>;
5643
5644 // Scalar Signed saturating doubling multiply-add long (scalar, by element)
5645 def SQDMLALshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5646   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5647   let Inst{11} = 0b0; // h
5648   let Inst{21} = Imm{1}; // l
5649   let Inst{20} = Imm{0}; // m
5650   let Inst{19-16} = MRm{3-0};
5651 }
5652 def SQDMLALshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5653   0b0011, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5654   let Inst{11} = Imm{2}; // h
5655   let Inst{21} = Imm{1}; // l
5656   let Inst{20} = Imm{0}; // m
5657   let Inst{19-16} = MRm{3-0};
5658 }
5659 def SQDMLALdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5660   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5661   let Inst{11} = 0b0;    // h
5662   let Inst{21} = Imm{0}; // l
5663   let Inst{20-16} = MRm;
5664 }
5665 def SQDMLALdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlal",
5666   0b0011, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5667   let Inst{11} = Imm{1};    // h
5668   let Inst{21} = Imm{0};    // l
5669   let Inst{20-16} = MRm;
5670 }
5671
5672 // Scalar Signed saturating doubling
5673 // multiply-subtract long (scalar, by element)
5674 def SQDMLSLshv_4H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5675   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR64Lo, neon_uimm2_bare> {
5676   let Inst{11} = 0b0; // h
5677   let Inst{21} = Imm{1}; // l
5678   let Inst{20} = Imm{0}; // m
5679   let Inst{19-16} = MRm{3-0};
5680 }
5681 def SQDMLSLshv_8H : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5682   0b0111, ".h", 0b0, 0b0, 0b1, FPR32, FPR16, VPR128Lo, neon_uimm3_bare> {
5683   let Inst{11} = Imm{2}; // h
5684   let Inst{21} = Imm{1}; // l
5685   let Inst{20} = Imm{0}; // m
5686   let Inst{19-16} = MRm{3-0};
5687 }
5688 def SQDMLSLdsv_2S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5689   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR64, neon_uimm1_bare> {
5690   let Inst{11} = 0b0;    // h
5691   let Inst{21} = Imm{0}; // l
5692   let Inst{20-16} = MRm;
5693 }
5694 def SQDMLSLdsv_4S : NeonI_ScalarXIndexedElemArith_Constraint_Impl<"sqdmlsl",
5695   0b0111, ".s", 0b0, 0b1, 0b0, FPR64, FPR32, VPR128, neon_uimm2_bare> {
5696   let Inst{11} = Imm{1};    // h
5697   let Inst{21} = Imm{0};    // l
5698   let Inst{20-16} = MRm;
5699 }
5700
5701 multiclass Neon_ScalarXIndexedElem_MLAL_Patterns<
5702   SDPatternOperator opnode,
5703   SDPatternOperator coreopnode,
5704   Instruction INST,
5705   ValueType ResTy, RegisterClass ResFPRC, RegisterClass FPRC,
5706   ValueType OpTy,
5707   ValueType OpVTy, ValueType ExTy, RegisterOperand VPRC, Operand OpImm> {
5708
5709   def  : Pat<(ResTy (opnode
5710                (ResTy ResFPRC:$Ra),
5711                (ResTy (coreopnode (OpTy FPRC:$Rn),
5712                  (OpTy (scalar_to_vector
5713                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))))))),
5714              (ResTy (INST (ResTy ResFPRC:$Ra),
5715                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5716
5717   // swapped operands
5718   def  : Pat<(ResTy (opnode
5719                (ResTy ResFPRC:$Ra),
5720                (ResTy (coreopnode
5721                  (OpTy (scalar_to_vector
5722                    (ExTy (vector_extract (OpVTy VPRC:$MRm), OpImm:$Imm)))),
5723                  (OpTy FPRC:$Rn))))),
5724              (ResTy (INST (ResTy ResFPRC:$Ra),
5725                (OpTy FPRC:$Rn), (OpVTy VPRC:$MRm), OpImm:$Imm))>;
5726 }
5727
5728 // Patterns for Scalar Signed saturating
5729 // doubling multiply-add long (scalar, by element)
5730 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5731   int_arm_neon_vqdmull, SQDMLALshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5732   i32, VPR64Lo, neon_uimm2_bare>;
5733 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5734   int_arm_neon_vqdmull, SQDMLALshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5735   i32, VPR128Lo, neon_uimm3_bare>;
5736 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5737   int_arm_neon_vqdmull, SQDMLALdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5738   i32, VPR64Lo, neon_uimm1_bare>;
5739 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqadds,
5740   int_arm_neon_vqdmull, SQDMLALdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5741   i32, VPR128Lo, neon_uimm2_bare>;
5742
5743 // Patterns for Scalar Signed saturating
5744 // doubling multiply-sub long (scalar, by element)
5745 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5746   int_arm_neon_vqdmull, SQDMLSLshv_4H, v1i32, FPR32, FPR16, v1i16, v4i16,
5747   i32, VPR64Lo, neon_uimm2_bare>;
5748 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5749   int_arm_neon_vqdmull, SQDMLSLshv_8H, v1i32, FPR32, FPR16, v1i16, v8i16,
5750   i32, VPR128Lo, neon_uimm3_bare>;
5751 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5752   int_arm_neon_vqdmull, SQDMLSLdsv_2S, v1i64, FPR64, FPR32, v1i32, v2i32,
5753   i32, VPR64Lo, neon_uimm1_bare>;
5754 defm : Neon_ScalarXIndexedElem_MLAL_Patterns<int_arm_neon_vqsubs,
5755   int_arm_neon_vqdmull, SQDMLSLdsv_4S, v1i64, FPR64, FPR32, v1i32, v4i32,
5756   i32, VPR128Lo, neon_uimm2_bare>;
5757
5758 // Scalar Signed saturating doubling multiply returning
5759 // high half (scalar, by element)
5760 def SQDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5761   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5762   let Inst{11} = 0b0; // h
5763   let Inst{21} = Imm{1}; // l
5764   let Inst{20} = Imm{0}; // m
5765   let Inst{19-16} = MRm{3-0};
5766 }
5767 def SQDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5768   0b1100, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5769   let Inst{11} = Imm{2}; // h
5770   let Inst{21} = Imm{1}; // l
5771   let Inst{20} = Imm{0}; // m
5772   let Inst{19-16} = MRm{3-0};
5773 }
5774 def SQDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5775   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5776   let Inst{11} = 0b0;    // h
5777   let Inst{21} = Imm{0}; // l
5778   let Inst{20-16} = MRm;
5779 }
5780 def SQDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqdmulh",
5781   0b1100, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5782   let Inst{11} = Imm{1};    // h
5783   let Inst{21} = Imm{0};    // l
5784   let Inst{20-16} = MRm;
5785 }
5786
5787 // Patterns for Scalar Signed saturating doubling multiply returning
5788 // high half (scalar, by element)
5789 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5790   SQDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16,
5791   i32, VPR64Lo, neon_uimm2_bare>;
5792 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5793   SQDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16,
5794   i32, VPR128Lo, neon_uimm3_bare>;
5795 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5796   SQDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32,
5797   i32, VPR64Lo, neon_uimm1_bare>;
5798 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqdmulh,
5799   SQDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32,
5800   i32, VPR128Lo, neon_uimm2_bare>;
5801
5802 // Scalar Signed saturating rounding doubling multiply
5803 // returning high half (scalar, by element)
5804 def SQRDMULHhhv_4H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5805   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR64Lo, neon_uimm2_bare> {
5806   let Inst{11} = 0b0; // h
5807   let Inst{21} = Imm{1}; // l
5808   let Inst{20} = Imm{0}; // m
5809   let Inst{19-16} = MRm{3-0};
5810 }
5811 def SQRDMULHhhv_8H : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5812   0b1101, ".h", 0b0, 0b0, 0b1, FPR16, FPR16, VPR128Lo, neon_uimm3_bare> {
5813   let Inst{11} = Imm{2}; // h
5814   let Inst{21} = Imm{1}; // l
5815   let Inst{20} = Imm{0}; // m
5816   let Inst{19-16} = MRm{3-0};
5817 }
5818 def SQRDMULHssv_2S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5819   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR64, neon_uimm1_bare> {
5820   let Inst{11} = 0b0;    // h
5821   let Inst{21} = Imm{0}; // l
5822   let Inst{20-16} = MRm;
5823 }
5824 def SQRDMULHssv_4S : NeonI_ScalarXIndexedElemArith<"sqrdmulh",
5825   0b1101, ".s", 0b0, 0b1, 0b0, FPR32, FPR32, VPR128, neon_uimm2_bare> {
5826   let Inst{11} = Imm{1};    // h
5827   let Inst{21} = Imm{0};    // l
5828   let Inst{20-16} = MRm;
5829 }
5830
5831 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5832   SQRDMULHhhv_4H, v1i16, FPR16, v1i16, i16, v4i16, i32,
5833   VPR64Lo, neon_uimm2_bare>;
5834 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5835   SQRDMULHhhv_8H, v1i16, FPR16, v1i16, i16, v8i16, i32,
5836   VPR128Lo, neon_uimm3_bare>;
5837 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5838   SQRDMULHssv_2S, v1i32, FPR32, v1i32, i32, v2i32, i32,
5839   VPR64Lo, neon_uimm1_bare>;
5840 defm : Neon_ScalarXIndexedElem_MUL_Patterns<int_arm_neon_vqrdmulh,
5841   SQRDMULHssv_4S, v1i32, FPR32, v1i32, i32, v4i32, i32,
5842   VPR128Lo, neon_uimm2_bare>;
5843
5844 // Scalar general arithmetic operation
5845 class Neon_Scalar_GeneralMath2D_pattern<SDPatternOperator opnode,
5846                                         Instruction INST>
5847     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))), (INST FPR64:$Rn)>;
5848
5849 class Neon_Scalar_GeneralMath3D_pattern<SDPatternOperator opnode,
5850                                         Instruction INST>
5851     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5852           (INST FPR64:$Rn, FPR64:$Rm)>;
5853
5854 class Neon_Scalar_GeneralMath4D_pattern<SDPatternOperator opnode,
5855                                         Instruction INST>
5856     : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm),
5857               (v1f64 FPR64:$Ra))),
5858           (INST FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
5859
5860 def : Neon_Scalar_GeneralMath3D_pattern<fadd, FADDddd>;
5861 def : Neon_Scalar_GeneralMath3D_pattern<fmul, FMULddd>;
5862 def : Neon_Scalar_GeneralMath3D_pattern<fsub, FSUBddd>;
5863 def : Neon_Scalar_GeneralMath3D_pattern<fdiv, FDIVddd>;
5864 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vabds, FABDddd>;
5865 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmaxs, FMAXddd>;
5866 def : Neon_Scalar_GeneralMath3D_pattern<int_arm_neon_vmins, FMINddd>;
5867 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vmaxnm, FMAXNMddd>;
5868 def : Neon_Scalar_GeneralMath3D_pattern<int_aarch64_neon_vminnm, FMINNMddd>;
5869
5870 def : Neon_Scalar_GeneralMath2D_pattern<fabs, FABSdd>;
5871 def : Neon_Scalar_GeneralMath2D_pattern<fneg, FNEGdd>;
5872
5873 def : Neon_Scalar_GeneralMath4D_pattern<fma, FMADDdddd>;
5874 def : Neon_Scalar_GeneralMath4D_pattern<fmsub, FMSUBdddd>;
5875
5876 // Scalar Copy - DUP element to scalar
5877 class NeonI_Scalar_DUP<string asmop, string asmlane,
5878                        RegisterClass ResRC, RegisterOperand VPRC,
5879                        Operand OpImm>
5880   : NeonI_ScalarCopy<(outs ResRC:$Rd), (ins VPRC:$Rn, OpImm:$Imm),
5881                      asmop # "\t$Rd, $Rn." # asmlane # "[$Imm]",
5882                      [],
5883                      NoItinerary> {
5884   bits<4> Imm;
5885 }
5886
5887 def DUPbv_B : NeonI_Scalar_DUP<"dup", "b", FPR8, VPR128, neon_uimm4_bare> {
5888   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5889 }
5890 def DUPhv_H : NeonI_Scalar_DUP<"dup", "h", FPR16, VPR128, neon_uimm3_bare> {
5891   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5892 }
5893 def DUPsv_S : NeonI_Scalar_DUP<"dup", "s", FPR32, VPR128, neon_uimm2_bare> {
5894   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5895 }
5896 def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
5897   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5898 }
5899
5900 multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
5901   ValueType OpTy, Operand OpImm,
5902   ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
5903   def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5904             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5905
5906   def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5907             (ResTy (DUPI
5908               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5909                 OpNImm:$Imm))>;
5910 }
5911
5912 // Patterns for vector extract of FP data using scalar DUP instructions
5913 defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
5914   v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
5915 defm : NeonI_Scalar_DUP_Elt_pattern<DUPdv_D, f64,
5916   v2f64, neon_uimm1_bare, v1f64, v2f64, neon_uimm0_bare>;
5917
5918 multiclass NeonI_Scalar_DUP_Ext_Vec_pattern<Instruction DUPI,
5919   ValueType ResTy, ValueType OpTy,Operand OpLImm,
5920   ValueType NOpTy, ValueType ExTy, Operand OpNImm> {
5921
5922   def : Pat<(ResTy (extract_subvector (OpTy VPR128:$Rn), OpLImm:$Imm)),
5923             (ResTy (DUPI VPR128:$Rn, OpLImm:$Imm))>;
5924
5925   def : Pat<(ResTy (extract_subvector (NOpTy VPR64:$Rn), OpNImm:$Imm)),
5926             (ResTy (DUPI
5927               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5928                 OpNImm:$Imm))>;
5929 }
5930
5931 // Patterns for extract subvectors of v1ix data using scalar DUP instructions.
5932 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPbv_B, v1i8, v16i8, neon_uimm4_bare,
5933                                         v8i8, v16i8, neon_uimm3_bare>;
5934 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPhv_H, v1i16, v8i16, neon_uimm3_bare,
5935                                         v4i16, v8i16, neon_uimm2_bare>;
5936 defm : NeonI_Scalar_DUP_Ext_Vec_pattern<DUPsv_S, v1i32, v4i32, neon_uimm2_bare,
5937                                         v2i32, v4i32, neon_uimm1_bare>;
5938
5939 multiclass NeonI_Scalar_DUP_Copy_pattern1<Instruction DUPI, ValueType ResTy,
5940                                           ValueType OpTy, ValueType ElemTy,
5941                                           Operand OpImm, ValueType OpNTy,
5942                                           ValueType ExTy, Operand OpNImm> {
5943
5944   def : Pat<(ResTy (vector_insert (ResTy undef),
5945               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
5946               (neon_uimm0_bare:$Imm))),
5947             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5948
5949   def : Pat<(ResTy (vector_insert (ResTy undef),
5950               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
5951               (OpNImm:$Imm))),
5952             (ResTy (DUPI
5953               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5954               OpNImm:$Imm))>;
5955 }
5956
5957 multiclass NeonI_Scalar_DUP_Copy_pattern2<Instruction DUPI, ValueType ResTy,
5958                                           ValueType OpTy, ValueType ElemTy,
5959                                           Operand OpImm, ValueType OpNTy,
5960                                           ValueType ExTy, Operand OpNImm> {
5961
5962   def : Pat<(ResTy (scalar_to_vector
5963               (ElemTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)))),
5964             (ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
5965
5966   def : Pat<(ResTy (scalar_to_vector
5967               (ElemTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)))),
5968             (ResTy (DUPI
5969               (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5970               OpNImm:$Imm))>;
5971 }
5972
5973 // Patterns for vector copy to v1ix and v1fx vectors using scalar DUP
5974 // instructions.
5975 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPdv_D,
5976   v1i64, v2i64, i64, neon_uimm1_bare,
5977   v1i64, v2i64, neon_uimm0_bare>;
5978 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPsv_S,
5979   v1i32, v4i32, i32, neon_uimm2_bare,
5980   v2i32, v4i32, neon_uimm1_bare>;
5981 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPhv_H,
5982   v1i16, v8i16, i32, neon_uimm3_bare,
5983   v4i16, v8i16, neon_uimm2_bare>;
5984 defm : NeonI_Scalar_DUP_Copy_pattern1<DUPbv_B,
5985   v1i8, v16i8, i32, neon_uimm4_bare,
5986   v8i8, v16i8, neon_uimm3_bare>;
5987 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPdv_D,
5988   v1i64, v2i64, i64, neon_uimm1_bare,
5989   v1i64, v2i64, neon_uimm0_bare>;
5990 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPsv_S,
5991   v1i32, v4i32, i32, neon_uimm2_bare,
5992   v2i32, v4i32, neon_uimm1_bare>;
5993 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPhv_H,
5994   v1i16, v8i16, i32, neon_uimm3_bare,
5995   v4i16, v8i16, neon_uimm2_bare>;
5996 defm : NeonI_Scalar_DUP_Copy_pattern2<DUPbv_B,
5997   v1i8, v16i8, i32, neon_uimm4_bare,
5998   v8i8, v16i8, neon_uimm3_bare>;
5999
6000 multiclass NeonI_Scalar_DUP_alias<string asmop, string asmlane,
6001                                   Instruction DUPI, Operand OpImm,
6002                                   RegisterClass ResRC> {
6003   def : NeonInstAlias<!strconcat(asmop, "$Rd, $Rn" # asmlane # "[$Imm]"),
6004           (DUPI ResRC:$Rd, VPR128:$Rn, OpImm:$Imm), 0b0>;
6005 }
6006
6007 // Aliases for Scalar copy - DUP element (scalar)
6008 // FIXME: This is actually the preferred syntax but TableGen can't deal with
6009 // custom printing of aliases.
6010 defm : NeonI_Scalar_DUP_alias<"mov", ".b", DUPbv_B, neon_uimm4_bare, FPR8>;
6011 defm : NeonI_Scalar_DUP_alias<"mov", ".h", DUPhv_H, neon_uimm3_bare, FPR16>;
6012 defm : NeonI_Scalar_DUP_alias<"mov", ".s", DUPsv_S, neon_uimm2_bare, FPR32>;
6013 defm : NeonI_Scalar_DUP_alias<"mov", ".d", DUPdv_D, neon_uimm1_bare, FPR64>;
6014
6015 multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh, ValueType ResTy,
6016                       ValueType OpTy> {
6017   def : Pat<(ResTy (GetLow VPR128:$Rn)),
6018             (ResTy (EXTRACT_SUBREG (OpTy VPR128:$Rn), sub_64))>;
6019   def : Pat<(ResTy (GetHigh VPR128:$Rn)),
6020             (ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
6021 }
6022
6023 defm : NeonI_SDUP<Neon_Low16B, Neon_High16B, v8i8, v16i8>;
6024 defm : NeonI_SDUP<Neon_Low8H, Neon_High8H, v4i16, v8i16>;
6025 defm : NeonI_SDUP<Neon_Low4S, Neon_High4S, v2i32, v4i32>;
6026 defm : NeonI_SDUP<Neon_Low2D, Neon_High2D, v1i64, v2i64>;
6027 defm : NeonI_SDUP<Neon_Low4float, Neon_High4float, v2f32, v4f32>;
6028 defm : NeonI_SDUP<Neon_Low2double, Neon_High2double, v1f64, v2f64>;
6029
6030 //===----------------------------------------------------------------------===//
6031 // Non-Instruction Patterns
6032 //===----------------------------------------------------------------------===//
6033
6034 // 64-bit vector bitcasts...
6035
6036 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
6037 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
6038 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
6039 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
6040
6041 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
6042 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
6043 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
6044 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
6045
6046 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
6047 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
6048 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
6049 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
6050
6051 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
6052 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
6053 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
6054 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
6055
6056 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
6057 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6058 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6059 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6060
6061 // ..and 128-bit vector bitcasts...
6062
6063 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
6064 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
6065 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
6066 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
6067 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
6068
6069 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
6070 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
6071 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
6072 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
6073 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
6074
6075 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
6076 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
6077 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
6078 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
6079 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
6080
6081 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
6082 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
6083 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
6084 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
6085 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
6086
6087 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
6088 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
6089 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
6090 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
6091 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
6092
6093 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
6094 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
6095 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
6096 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
6097 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
6098
6099 // ...and scalar bitcasts...
6100 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
6101 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
6102 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
6103 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
6104
6105 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
6106 def : Pat<(i64 (bitconvert (v1f64  FPR64:$src))), (FMOVxd $src)>;
6107 def : Pat<(i64 (bitconvert (v2i32  FPR64:$src))), (FMOVxd $src)>;
6108 def : Pat<(i64 (bitconvert (v2f32  FPR64:$src))), (FMOVxd $src)>;
6109 def : Pat<(i64 (bitconvert (v4i16  FPR64:$src))), (FMOVxd $src)>;
6110 def : Pat<(i64 (bitconvert (v8i8  FPR64:$src))), (FMOVxd $src)>;
6111
6112 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
6113
6114 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
6115 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
6116 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
6117
6118 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
6119 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
6120 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
6121 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
6122 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
6123
6124 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
6125 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
6126 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
6127 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
6128 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
6129 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
6130
6131 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
6132 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
6133 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
6134 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
6135
6136 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6137 def : Pat<(v1f64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6138 def : Pat<(v2i32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6139 def : Pat<(v2f32 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6140 def : Pat<(v4i16 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6141 def : Pat<(v8i8 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
6142
6143 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
6144
6145 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
6146 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
6147 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
6148 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
6149 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
6150
6151 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
6152 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
6153 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
6154 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
6155 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
6156 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
6157
6158 // Scalar Three Same
6159
6160 def neon_uimm3 : Operand<i64>,
6161                    ImmLeaf<i64, [{return Imm < 8;}]> {
6162   let ParserMatchClass = uimm3_asmoperand;
6163   let PrintMethod = "printUImmHexOperand";
6164 }
6165
6166 def neon_uimm4 : Operand<i64>,
6167                    ImmLeaf<i64, [{return Imm < 16;}]> {
6168   let ParserMatchClass = uimm4_asmoperand;
6169   let PrintMethod = "printUImmHexOperand";
6170 }
6171
6172 // Bitwise Extract
6173 class NeonI_Extract<bit q, bits<2> op2, string asmop,
6174                     string OpS, RegisterOperand OpVPR, Operand OpImm>
6175   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
6176                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
6177                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
6178                      ", $Rm." # OpS # ", $Index",
6179                      [],
6180                      NoItinerary>{
6181   bits<4> Index;
6182 }
6183
6184 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
6185                                VPR64, neon_uimm3> {
6186   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
6187 }
6188
6189 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
6190                                VPR128, neon_uimm4> {
6191   let Inst{14-11} = Index;
6192 }
6193
6194 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
6195                  Operand OpImm>
6196   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
6197                                  (i64 OpImm:$Imm))),
6198               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
6199
6200 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
6201 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6202 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6203 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6204 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6205 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
6206 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
6207 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
6208 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
6209 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
6210 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
6211 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
6212
6213 // Table lookup
6214 class NI_TBL<bit q, bits<2> op2, bits<2> len, bit op,
6215              string asmop, string OpS, RegisterOperand OpVPR,
6216              RegisterOperand VecList>
6217   : NeonI_TBL<q, op2, len, op,
6218               (outs OpVPR:$Rd), (ins VecList:$Rn, OpVPR:$Rm),
6219               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6220               [],
6221               NoItinerary>;
6222
6223 // The vectors in look up table are always 16b
6224 multiclass NI_TBL_pat<bits<2> len, bit op, string asmop, string List> {
6225   def _8b  : NI_TBL<0, 0b00, len, op, asmop, "8b", VPR64,
6226                     !cast<RegisterOperand>(List # "16B_operand")>;
6227
6228   def _16b : NI_TBL<1, 0b00, len, op, asmop, "16b", VPR128,
6229                     !cast<RegisterOperand>(List # "16B_operand")>;
6230 }
6231
6232 defm TBL1 : NI_TBL_pat<0b00, 0b0, "tbl", "VOne">;
6233 defm TBL2 : NI_TBL_pat<0b01, 0b0, "tbl", "VPair">;
6234 defm TBL3 : NI_TBL_pat<0b10, 0b0, "tbl", "VTriple">;
6235 defm TBL4 : NI_TBL_pat<0b11, 0b0, "tbl", "VQuad">;
6236
6237 // Table lookup extention
6238 class NI_TBX<bit q, bits<2> op2, bits<2> len, bit op,
6239              string asmop, string OpS, RegisterOperand OpVPR,
6240              RegisterOperand VecList>
6241   : NeonI_TBL<q, op2, len, op,
6242               (outs OpVPR:$Rd), (ins OpVPR:$src, VecList:$Rn, OpVPR:$Rm),
6243               asmop # "\t$Rd." # OpS # ", $Rn, $Rm." # OpS,
6244               [],
6245               NoItinerary> {
6246   let Constraints = "$src = $Rd";
6247 }
6248
6249 // The vectors in look up table are always 16b
6250 multiclass NI_TBX_pat<bits<2> len, bit op, string asmop, string List> {
6251   def _8b  : NI_TBX<0, 0b00, len, op, asmop, "8b", VPR64,
6252                     !cast<RegisterOperand>(List # "16B_operand")>;
6253
6254   def _16b : NI_TBX<1, 0b00, len, op, asmop, "16b", VPR128,
6255                     !cast<RegisterOperand>(List # "16B_operand")>;
6256 }
6257
6258 defm TBX1 : NI_TBX_pat<0b00, 0b1, "tbx", "VOne">;
6259 defm TBX2 : NI_TBX_pat<0b01, 0b1, "tbx", "VPair">;
6260 defm TBX3 : NI_TBX_pat<0b10, 0b1, "tbx", "VTriple">;
6261 defm TBX4 : NI_TBX_pat<0b11, 0b1, "tbx", "VQuad">;
6262
6263 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
6264                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
6265   : NeonI_copy<0b1, 0b0, 0b0011,
6266                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
6267                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
6268                [(set (ResTy VPR128:$Rd),
6269                  (ResTy (vector_insert
6270                    (ResTy VPR128:$src),
6271                    (OpTy OpGPR:$Rn),
6272                    (OpImm:$Imm))))],
6273                NoItinerary> {
6274   bits<4> Imm;
6275   let Constraints = "$src = $Rd";
6276 }
6277
6278 //Insert element (vector, from main)
6279 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
6280                            neon_uimm4_bare> {
6281   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6282 }
6283 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
6284                            neon_uimm3_bare> {
6285   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6286 }
6287 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
6288                            neon_uimm2_bare> {
6289   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6290 }
6291 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
6292                            neon_uimm1_bare> {
6293   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6294 }
6295
6296 def : NeonInstAlias<"mov $Rd.b[$Imm], $Rn",
6297                     (INSbw VPR128:$Rd, GPR32:$Rn, neon_uimm4_bare:$Imm), 0>;
6298 def : NeonInstAlias<"mov $Rd.h[$Imm], $Rn",
6299                     (INShw VPR128:$Rd, GPR32:$Rn, neon_uimm3_bare:$Imm), 0>;
6300 def : NeonInstAlias<"mov $Rd.s[$Imm], $Rn",
6301                     (INSsw VPR128:$Rd, GPR32:$Rn, neon_uimm2_bare:$Imm), 0>;
6302 def : NeonInstAlias<"mov $Rd.d[$Imm], $Rn",
6303                     (INSdx VPR128:$Rd, GPR64:$Rn, neon_uimm1_bare:$Imm), 0>;
6304
6305 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
6306                              RegisterClass OpGPR, ValueType OpTy,
6307                              Operand OpImm, Instruction INS>
6308   : Pat<(ResTy (vector_insert
6309               (ResTy VPR64:$src),
6310               (OpTy OpGPR:$Rn),
6311               (OpImm:$Imm))),
6312         (ResTy (EXTRACT_SUBREG
6313           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
6314             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
6315
6316 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
6317                                           neon_uimm3_bare, INSbw>;
6318 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
6319                                           neon_uimm2_bare, INShw>;
6320 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
6321                                           neon_uimm1_bare, INSsw>;
6322 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
6323                                           neon_uimm0_bare, INSdx>;
6324
6325 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
6326   : NeonI_insert<0b1, 0b1,
6327                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
6328                  ResImm:$Immd, ResImm:$Immn),
6329                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
6330                  [],
6331                  NoItinerary> {
6332   let Constraints = "$src = $Rd";
6333   bits<4> Immd;
6334   bits<4> Immn;
6335 }
6336
6337 //Insert element (vector, from element)
6338 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
6339   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
6340   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
6341 }
6342 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
6343   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
6344   let Inst{14-11} = {Immn{2}, Immn{1}, Immn{0}, 0b0};
6345   // bit 11 is unspecified, but should be set to zero.
6346 }
6347 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
6348   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
6349   let Inst{14-11} = {Immn{1}, Immn{0}, 0b0, 0b0};
6350   // bits 11-12 are unspecified, but should be set to zero.
6351 }
6352 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
6353   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
6354   let Inst{14-11} = {Immn{0}, 0b0, 0b0, 0b0};
6355   // bits 11-13 are unspecified, but should be set to zero.
6356 }
6357
6358 def : NeonInstAlias<"mov $Rd.b[$Immd], $Rn.b[$Immn]",
6359                     (INSELb VPR128:$Rd, VPR128:$Rn,
6360                       neon_uimm4_bare:$Immd, neon_uimm4_bare:$Immn), 0>;
6361 def : NeonInstAlias<"mov $Rd.h[$Immd], $Rn.h[$Immn]",
6362                     (INSELh VPR128:$Rd, VPR128:$Rn,
6363                       neon_uimm3_bare:$Immd, neon_uimm3_bare:$Immn), 0>;
6364 def : NeonInstAlias<"mov $Rd.s[$Immd], $Rn.s[$Immn]",
6365                     (INSELs VPR128:$Rd, VPR128:$Rn,
6366                       neon_uimm2_bare:$Immd, neon_uimm2_bare:$Immn), 0>;
6367 def : NeonInstAlias<"mov $Rd.d[$Immd], $Rn.d[$Immn]",
6368                     (INSELd VPR128:$Rd, VPR128:$Rn,
6369                       neon_uimm1_bare:$Immd, neon_uimm1_bare:$Immn), 0>;
6370
6371 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
6372                                 ValueType MidTy, Operand StImm, Operand NaImm,
6373                                 Instruction INS> {
6374 def : Pat<(ResTy (vector_insert
6375             (ResTy VPR128:$src),
6376             (MidTy (vector_extract
6377               (ResTy VPR128:$Rn),
6378               (StImm:$Immn))),
6379             (StImm:$Immd))),
6380           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
6381               StImm:$Immd, StImm:$Immn)>;
6382
6383 def : Pat <(ResTy (vector_insert
6384              (ResTy VPR128:$src),
6385              (MidTy (vector_extract
6386                (NaTy VPR64:$Rn),
6387                (NaImm:$Immn))),
6388              (StImm:$Immd))),
6389            (INS (ResTy VPR128:$src),
6390              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6391              StImm:$Immd, NaImm:$Immn)>;
6392
6393 def : Pat <(NaTy (vector_insert
6394              (NaTy VPR64:$src),
6395              (MidTy (vector_extract
6396                (ResTy VPR128:$Rn),
6397                (StImm:$Immn))),
6398              (NaImm:$Immd))),
6399            (NaTy (EXTRACT_SUBREG
6400              (ResTy (INS
6401                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6402                (ResTy VPR128:$Rn),
6403                NaImm:$Immd, StImm:$Immn)),
6404              sub_64))>;
6405
6406 def : Pat <(NaTy (vector_insert
6407              (NaTy VPR64:$src),
6408              (MidTy (vector_extract
6409                (NaTy VPR64:$Rn),
6410                (NaImm:$Immn))),
6411              (NaImm:$Immd))),
6412            (NaTy (EXTRACT_SUBREG
6413              (ResTy (INS
6414                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6415                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
6416                NaImm:$Immd, NaImm:$Immn)),
6417              sub_64))>;
6418 }
6419
6420 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
6421                             neon_uimm1_bare, INSELs>;
6422 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
6423                             neon_uimm0_bare, INSELd>;
6424 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6425                             neon_uimm3_bare, INSELb>;
6426 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6427                             neon_uimm2_bare, INSELh>;
6428 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6429                             neon_uimm1_bare, INSELs>;
6430 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
6431                             neon_uimm0_bare, INSELd>;
6432
6433 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
6434                                       ValueType MidTy,
6435                                       RegisterClass OpFPR, Operand ResImm,
6436                                       SubRegIndex SubIndex, Instruction INS> {
6437 def : Pat <(ResTy (vector_insert
6438              (ResTy VPR128:$src),
6439              (MidTy OpFPR:$Rn),
6440              (ResImm:$Imm))),
6441            (INS (ResTy VPR128:$src),
6442              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
6443              ResImm:$Imm,
6444              (i64 0))>;
6445
6446 def : Pat <(NaTy (vector_insert
6447              (NaTy VPR64:$src),
6448              (MidTy OpFPR:$Rn),
6449              (ResImm:$Imm))),
6450            (NaTy (EXTRACT_SUBREG
6451              (ResTy (INS
6452                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
6453                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
6454                ResImm:$Imm,
6455                (i64 0))),
6456              sub_64))>;
6457 }
6458
6459 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
6460                                   sub_32, INSELs>;
6461 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
6462                                   sub_64, INSELd>;
6463
6464 class NeonI_SMOV<string asmop, string Res, bit Q,
6465                  ValueType OpTy, ValueType eleTy,
6466                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
6467   : NeonI_copy<Q, 0b0, 0b0101,
6468                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6469                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6470                [(set (ResTy ResGPR:$Rd),
6471                  (ResTy (sext_inreg
6472                    (ResTy (vector_extract
6473                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
6474                    eleTy)))],
6475                NoItinerary> {
6476   bits<4> Imm;
6477 }
6478
6479 //Signed integer move (main, from element)
6480 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
6481                         GPR32, i32> {
6482   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6483 }
6484 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
6485                         GPR32, i32> {
6486   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6487 }
6488 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
6489                         GPR64, i64> {
6490   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6491 }
6492 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
6493                         GPR64, i64> {
6494   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6495 }
6496 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
6497                         GPR64, i64> {
6498   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6499 }
6500
6501 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
6502                                ValueType eleTy, Operand StImm,  Operand NaImm,
6503                                Instruction SMOVI> {
6504   def : Pat<(i64 (sext_inreg
6505               (i64 (anyext
6506                 (i32 (vector_extract
6507                   (StTy VPR128:$Rn), (StImm:$Imm))))),
6508               eleTy)),
6509             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6510
6511   def : Pat<(i64 (sext
6512               (i32 (vector_extract
6513                 (StTy VPR128:$Rn), (StImm:$Imm))))),
6514             (SMOVI VPR128:$Rn, StImm:$Imm)>;
6515
6516   def : Pat<(i64 (sext_inreg
6517               (i64 (vector_extract
6518                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
6519               eleTy)),
6520             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6521               NaImm:$Imm)>;
6522
6523   def : Pat<(i64 (sext_inreg
6524               (i64 (anyext
6525                 (i32 (vector_extract
6526                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6527               eleTy)),
6528             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6529               NaImm:$Imm)>;
6530
6531   def : Pat<(i64 (sext
6532               (i32 (vector_extract
6533                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
6534             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6535               NaImm:$Imm)>;
6536 }
6537
6538 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6539                           neon_uimm3_bare, SMOVxb>;
6540 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6541                           neon_uimm2_bare, SMOVxh>;
6542 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6543                           neon_uimm1_bare, SMOVxs>;
6544
6545 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
6546                           ValueType eleTy, Operand StImm,  Operand NaImm,
6547                           Instruction SMOVI>
6548   : Pat<(i32 (sext_inreg
6549           (i32 (vector_extract
6550             (NaTy VPR64:$Rn), (NaImm:$Imm))),
6551           eleTy)),
6552         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6553           NaImm:$Imm)>;
6554
6555 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
6556                          neon_uimm3_bare, SMOVwb>;
6557 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
6558                          neon_uimm2_bare, SMOVwh>;
6559
6560 class NeonI_UMOV<string asmop, string Res, bit Q,
6561                  ValueType OpTy, Operand OpImm,
6562                  RegisterClass ResGPR, ValueType ResTy>
6563   : NeonI_copy<Q, 0b0, 0b0111,
6564                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
6565                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
6566                [(set (ResTy ResGPR:$Rd),
6567                   (ResTy (vector_extract
6568                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
6569                NoItinerary> {
6570   bits<4> Imm;
6571 }
6572
6573 //Unsigned integer move (main, from element)
6574 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
6575                          GPR32, i32> {
6576   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6577 }
6578 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
6579                          GPR32, i32> {
6580   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6581 }
6582 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
6583                          GPR32, i32> {
6584   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6585 }
6586 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
6587                          GPR64, i64> {
6588   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6589 }
6590
6591 def : NeonInstAlias<"mov $Rd, $Rn.s[$Imm]",
6592                     (UMOVws GPR32:$Rd, VPR128:$Rn, neon_uimm2_bare:$Imm), 0>;
6593 def : NeonInstAlias<"mov $Rd, $Rn.d[$Imm]",
6594                     (UMOVxd GPR64:$Rd, VPR128:$Rn, neon_uimm1_bare:$Imm), 0>;
6595
6596 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
6597                          Operand StImm,  Operand NaImm,
6598                          Instruction SMOVI>
6599   : Pat<(ResTy (vector_extract
6600           (NaTy VPR64:$Rn), NaImm:$Imm)),
6601         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6602           NaImm:$Imm)>;
6603
6604 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
6605                         neon_uimm3_bare, UMOVwb>;
6606 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
6607                         neon_uimm2_bare, UMOVwh>;
6608 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
6609                         neon_uimm1_bare, UMOVws>;
6610
6611 def : Pat<(i32 (and
6612             (i32 (vector_extract
6613               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
6614             255)),
6615           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
6616
6617 def : Pat<(i32 (and
6618             (i32 (vector_extract
6619               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
6620             65535)),
6621           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
6622
6623 def : Pat<(i64 (zext
6624             (i32 (vector_extract
6625               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
6626           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
6627
6628 def : Pat<(i32 (and
6629             (i32 (vector_extract
6630               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
6631             255)),
6632           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6633             neon_uimm3_bare:$Imm)>;
6634
6635 def : Pat<(i32 (and
6636             (i32 (vector_extract
6637               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
6638             65535)),
6639           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6640             neon_uimm2_bare:$Imm)>;
6641
6642 def : Pat<(i64 (zext
6643             (i32 (vector_extract
6644               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
6645           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
6646             neon_uimm0_bare:$Imm)>;
6647
6648 // Additional copy patterns for scalar types
6649 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
6650           (UMOVwb (v16i8
6651             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
6652
6653 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
6654           (UMOVwh (v8i16
6655             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
6656
6657 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
6658           (FMOVws FPR32:$Rn)>;
6659
6660 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6661           (FMOVxd FPR64:$Rn)>;
6662
6663 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6664           (f64 FPR64:$Rn)>;
6665
6666 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6667           (v1i8 (EXTRACT_SUBREG (v16i8
6668             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6669             sub_8))>;
6670
6671 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6672           (v1i16 (EXTRACT_SUBREG (v8i16
6673             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6674             sub_16))>;
6675
6676 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6677           (FMOVsw $src)>;
6678
6679 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6680           (FMOVdx $src)>;
6681
6682 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
6683           (v8i8 (EXTRACT_SUBREG (v16i8
6684             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6685             sub_64))>;
6686
6687 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
6688           (v4i16 (EXTRACT_SUBREG (v8i16
6689             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6690             sub_64))>;
6691
6692 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6693           (v2i32 (EXTRACT_SUBREG (v16i8
6694             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6695             sub_64))>;
6696
6697 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
6698           (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6699
6700 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
6701           (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6702
6703 def : Pat<(v4i32 (scalar_to_vector GPR32:$Rn)),
6704           (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6705
6706 def : Pat<(v2i64 (scalar_to_vector GPR64:$Rn)),
6707           (INSdx (v2i64 (IMPLICIT_DEF)), $Rn, (i64 0))>;
6708
6709 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6710           (v2i32 (EXTRACT_SUBREG (v16i8
6711             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6712             sub_64))>;
6713
6714 def : Pat<(v2i32 (scalar_to_vector GPR32:$Rn)),
6715           (v2i32 (EXTRACT_SUBREG (v16i8
6716             (INSsw (v4i32 (IMPLICIT_DEF)), $Rn, (i64 0))),
6717             sub_64))>;
6718
6719 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6720           (v1f64 FPR64:$Rn)>;
6721
6722 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6723           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6724                          (f64 FPR64:$src), sub_64)>;
6725
6726 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
6727                     RegisterOperand ResVPR, Operand OpImm>
6728   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6729                (ins VPR128:$Rn, OpImm:$Imm),
6730                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6731                [],
6732                NoItinerary> {
6733   bits<4> Imm;
6734 }
6735
6736 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6737                               neon_uimm4_bare> {
6738   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6739 }
6740
6741 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6742                               neon_uimm3_bare> {
6743   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6744 }
6745
6746 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6747                               neon_uimm2_bare> {
6748   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6749 }
6750
6751 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6752                               neon_uimm1_bare> {
6753   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6754 }
6755
6756 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6757                               neon_uimm4_bare> {
6758   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6759 }
6760
6761 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6762                               neon_uimm3_bare> {
6763   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6764 }
6765
6766 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6767                               neon_uimm2_bare> {
6768   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6769 }
6770
6771 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6772                                        ValueType OpTy,ValueType NaTy,
6773                                        ValueType ExTy, Operand OpLImm,
6774                                        Operand OpNImm> {
6775 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6776         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6777
6778 def : Pat<(ResTy (Neon_vduplane
6779             (NaTy VPR64:$Rn), OpNImm:$Imm)),
6780           (ResTy (DUPELT
6781             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6782 }
6783 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6784                              neon_uimm4_bare, neon_uimm3_bare>;
6785 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6786                              neon_uimm4_bare, neon_uimm3_bare>;
6787 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6788                              neon_uimm3_bare, neon_uimm2_bare>;
6789 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6790                              neon_uimm3_bare, neon_uimm2_bare>;
6791 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6792                              neon_uimm2_bare, neon_uimm1_bare>;
6793 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6794                              neon_uimm2_bare, neon_uimm1_bare>;
6795 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6796                              neon_uimm1_bare, neon_uimm0_bare>;
6797 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6798                              neon_uimm2_bare, neon_uimm1_bare>;
6799 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6800                              neon_uimm2_bare, neon_uimm1_bare>;
6801 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6802                              neon_uimm1_bare, neon_uimm0_bare>;
6803
6804 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6805           (v2f32 (DUPELT2s
6806             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6807             (i64 0)))>;
6808 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6809           (v4f32 (DUPELT4s
6810             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6811             (i64 0)))>;
6812 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6813           (v2f64 (DUPELT2d
6814             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6815             (i64 0)))>;
6816
6817 class NeonI_DUP<bit Q, string asmop, string rdlane,
6818                 RegisterOperand ResVPR, ValueType ResTy,
6819                 RegisterClass OpGPR, ValueType OpTy>
6820   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6821                asmop # "\t$Rd" # rdlane # ", $Rn",
6822                [(set (ResTy ResVPR:$Rd),
6823                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6824                NoItinerary>;
6825
6826 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6827   let Inst{20-16} = 0b00001;
6828   // bits 17-20 are unspecified, but should be set to zero.
6829 }
6830
6831 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6832   let Inst{20-16} = 0b00010;
6833   // bits 18-20 are unspecified, but should be set to zero.
6834 }
6835
6836 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6837   let Inst{20-16} = 0b00100;
6838   // bits 19-20 are unspecified, but should be set to zero.
6839 }
6840
6841 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6842   let Inst{20-16} = 0b01000;
6843   // bit 20 is unspecified, but should be set to zero.
6844 }
6845
6846 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6847   let Inst{20-16} = 0b00001;
6848   // bits 17-20 are unspecified, but should be set to zero.
6849 }
6850
6851 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6852   let Inst{20-16} = 0b00010;
6853   // bits 18-20 are unspecified, but should be set to zero.
6854 }
6855
6856 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6857   let Inst{20-16} = 0b00100;
6858   // bits 19-20 are unspecified, but should be set to zero.
6859 }
6860
6861 // patterns for CONCAT_VECTORS
6862 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6863 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6864           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6865 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6866           (INSELd
6867             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6868             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6869             (i64 1),
6870             (i64 0))>;
6871 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6872           (DUPELT2d
6873             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6874             (i64 0))> ;
6875 }
6876
6877 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6878 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6879 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6880 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6881 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6882 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6883
6884 //patterns for EXTRACT_SUBVECTOR
6885 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6886           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6887 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6888           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6889 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6890           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6891 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6892           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6893 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6894           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6895 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6896           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6897
6898 // The followings are for instruction class (3V Elem)
6899
6900 // Variant 1
6901
6902 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
6903              string asmop, string ResS, string OpS, string EleOpS,
6904              Operand OpImm, RegisterOperand ResVPR,
6905              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
6906   : NeonI_2VElem<q, u, size, opcode,
6907                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
6908                                          EleOpVPR:$Re, OpImm:$Index),
6909                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
6910                  ", $Re." # EleOpS # "[$Index]",
6911                  [],
6912                  NoItinerary> {
6913   bits<3> Index;
6914   bits<5> Re;
6915
6916   let Constraints = "$src = $Rd";
6917 }
6918
6919 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
6920   // vector register class for element is always 128-bit to cover the max index
6921   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
6922                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
6923     let Inst{11} = {Index{1}};
6924     let Inst{21} = {Index{0}};
6925     let Inst{20-16} = Re;
6926   }
6927
6928   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
6929                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
6930     let Inst{11} = {Index{1}};
6931     let Inst{21} = {Index{0}};
6932     let Inst{20-16} = Re;
6933   }
6934
6935   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
6936   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
6937                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
6938     let Inst{11} = {Index{2}};
6939     let Inst{21} = {Index{1}};
6940     let Inst{20} = {Index{0}};
6941     let Inst{19-16} = Re{3-0};
6942   }
6943
6944   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
6945                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
6946     let Inst{11} = {Index{2}};
6947     let Inst{21} = {Index{1}};
6948     let Inst{20} = {Index{0}};
6949     let Inst{19-16} = Re{3-0};
6950   }
6951 }
6952
6953 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
6954 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
6955
6956 // Pattern for lane in 128-bit vector
6957 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
6958                    RegisterOperand ResVPR, RegisterOperand OpVPR,
6959                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6960                    ValueType EleOpTy>
6961   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6962           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6963         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
6964
6965 // Pattern for lane in 64-bit vector
6966 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
6967                   RegisterOperand ResVPR, RegisterOperand OpVPR,
6968                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
6969                   ValueType EleOpTy>
6970   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
6971           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
6972         (INST ResVPR:$src, OpVPR:$Rn,
6973           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
6974
6975 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
6976 {
6977   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
6978                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>;
6979
6980   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
6981                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>;
6982
6983   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
6984                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
6985
6986   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
6987                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
6988
6989   // Index can only be half of the max value for lane in 64-bit vector
6990
6991   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
6992                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>;
6993
6994   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
6995                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
6996 }
6997
6998 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
6999 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
7000
7001 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
7002                  string asmop, string ResS, string OpS, string EleOpS,
7003                  Operand OpImm, RegisterOperand ResVPR,
7004                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
7005   : NeonI_2VElem<q, u, size, opcode,
7006                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
7007                                          EleOpVPR:$Re, OpImm:$Index),
7008                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
7009                  ", $Re." # EleOpS # "[$Index]",
7010                  [],
7011                  NoItinerary> {
7012   bits<3> Index;
7013   bits<5> Re;
7014 }
7015
7016 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
7017   // vector register class for element is always 128-bit to cover the max index
7018   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7019                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7020     let Inst{11} = {Index{1}};
7021     let Inst{21} = {Index{0}};
7022     let Inst{20-16} = Re;
7023   }
7024
7025   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7026                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7027     let Inst{11} = {Index{1}};
7028     let Inst{21} = {Index{0}};
7029     let Inst{20-16} = Re;
7030   }
7031
7032   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7033   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
7034                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
7035     let Inst{11} = {Index{2}};
7036     let Inst{21} = {Index{1}};
7037     let Inst{20} = {Index{0}};
7038     let Inst{19-16} = Re{3-0};
7039   }
7040
7041   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
7042                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7043     let Inst{11} = {Index{2}};
7044     let Inst{21} = {Index{1}};
7045     let Inst{20} = {Index{0}};
7046     let Inst{19-16} = Re{3-0};
7047   }
7048 }
7049
7050 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
7051 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
7052 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
7053
7054 // Pattern for lane in 128-bit vector
7055 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7056                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7057                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7058   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7059           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7060         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7061
7062 // Pattern for lane in 64-bit vector
7063 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7064                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7065                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy>
7066   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7067           (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7068         (INST OpVPR:$Rn,
7069           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7070
7071 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
7072   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7073                          op, VPR64, VPR128, v2i32, v2i32, v4i32>;
7074
7075   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7076                          op, VPR128, VPR128, v4i32, v4i32, v4i32>;
7077
7078   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
7079                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>;
7080
7081   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
7082                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>;
7083
7084   // Index can only be half of the max value for lane in 64-bit vector
7085
7086   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7087                         op, VPR64, VPR64, v2i32, v2i32, v2i32>;
7088
7089   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
7090                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>;
7091 }
7092
7093 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
7094 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
7095 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
7096
7097 // Variant 2
7098
7099 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
7100   // vector register class for element is always 128-bit to cover the max index
7101   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7102                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
7103     let Inst{11} = {Index{1}};
7104     let Inst{21} = {Index{0}};
7105     let Inst{20-16} = Re;
7106   }
7107
7108   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7109                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7110     let Inst{11} = {Index{1}};
7111     let Inst{21} = {Index{0}};
7112     let Inst{20-16} = Re;
7113   }
7114
7115   // _1d2d doesn't exist!
7116
7117   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7118                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
7119     let Inst{11} = {Index{0}};
7120     let Inst{21} = 0b0;
7121     let Inst{20-16} = Re;
7122   }
7123 }
7124
7125 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
7126 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
7127
7128 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
7129                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
7130                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
7131                          SDPatternOperator coreop>
7132   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
7133           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
7134         (INST OpVPR:$Rn,
7135           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
7136
7137 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
7138   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
7139                          op, VPR64, VPR128, v2f32, v2f32, v4f32>;
7140
7141   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
7142                          op, VPR128, VPR128, v4f32, v4f32, v4f32>;
7143
7144   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7145                          op, VPR128, VPR128, v2f64, v2f64, v2f64>;
7146
7147   // Index can only be half of the max value for lane in 64-bit vector
7148
7149   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
7150                         op, VPR64, VPR64, v2f32, v2f32, v2f32>;
7151
7152   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
7153                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
7154                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7155 }
7156
7157 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
7158 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
7159
7160 def : Pat<(v2f32 (fmul (v2f32 (Neon_vdup (f32 FPR32:$Re))),
7161                        (v2f32 VPR64:$Rn))),
7162           (FMULve_2s4s VPR64:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7163
7164 def : Pat<(v4f32 (fmul (v4f32 (Neon_vdup (f32 FPR32:$Re))),
7165                        (v4f32 VPR128:$Rn))),
7166           (FMULve_4s4s VPR128:$Rn, (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7167
7168 def : Pat<(v2f64 (fmul (v2f64 (Neon_vdup (f64 FPR64:$Re))),
7169                        (v2f64 VPR128:$Rn))),
7170           (FMULve_2d2d VPR128:$Rn, (SUBREG_TO_REG (i64 0), $Re, sub_64), 0)>;
7171
7172 // The followings are patterns using fma
7173 // -ffp-contract=fast generates fma
7174
7175 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
7176   // vector register class for element is always 128-bit to cover the max index
7177   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
7178                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
7179     let Inst{11} = {Index{1}};
7180     let Inst{21} = {Index{0}};
7181     let Inst{20-16} = Re;
7182   }
7183
7184   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
7185                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7186     let Inst{11} = {Index{1}};
7187     let Inst{21} = {Index{0}};
7188     let Inst{20-16} = Re;
7189   }
7190
7191   // _1d2d doesn't exist!
7192
7193   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
7194                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
7195     let Inst{11} = {Index{0}};
7196     let Inst{21} = 0b0;
7197     let Inst{20-16} = Re;
7198   }
7199 }
7200
7201 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
7202 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
7203
7204 // Pattern for lane in 128-bit vector
7205 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7206                        RegisterOperand ResVPR, RegisterOperand OpVPR,
7207                        ValueType ResTy, ValueType OpTy,
7208                        SDPatternOperator coreop>
7209   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7210                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
7211         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
7212
7213 // Pattern for lane 0
7214 class NI_2VEfma_lane0<Instruction INST, SDPatternOperator op,
7215                       RegisterOperand ResVPR, ValueType ResTy>
7216   : Pat<(ResTy (op (ResTy ResVPR:$Rn),
7217                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7218                    (ResTy ResVPR:$src))),
7219         (INST ResVPR:$src, ResVPR:$Rn,
7220               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7221
7222 // Pattern for lane in 64-bit vector
7223 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7224                       RegisterOperand ResVPR, RegisterOperand OpVPR,
7225                       ValueType ResTy, ValueType OpTy,
7226                       SDPatternOperator coreop>
7227   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
7228                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7229         (INST ResVPR:$src, ResVPR:$Rn,
7230           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
7231
7232 // Pattern for lane in 64-bit vector
7233 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
7234                            SDPatternOperator op,
7235                            RegisterOperand ResVPR, RegisterOperand OpVPR,
7236                            ValueType ResTy, ValueType OpTy,
7237                            SDPatternOperator coreop>
7238   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
7239                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
7240         (INST ResVPR:$src, ResVPR:$Rn,
7241           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
7242
7243
7244 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
7245   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7246                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7247                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7248
7249   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_2s4s"),
7250                         op, VPR64, v2f32>;
7251
7252   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7253                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7254                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7255
7256   def : NI_2VEfma_lane0<!cast<Instruction>(subop # "_4s4s"),
7257                         op, VPR128, v4f32>;
7258
7259   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7260                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7261                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7262
7263   // Index can only be half of the max value for lane in 64-bit vector
7264
7265   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7266                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7267                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
7268
7269   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7270                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7271                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
7272 }
7273
7274 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
7275
7276 // Pattern for lane 0
7277 class NI_2VEfms_lane0<Instruction INST, SDPatternOperator op,
7278                       RegisterOperand ResVPR, ValueType ResTy>
7279   : Pat<(ResTy (op (ResTy (fneg ResVPR:$Rn)),
7280                    (ResTy (Neon_vdup (f32 FPR32:$Re))),
7281                    (ResTy ResVPR:$src))),
7282         (INST ResVPR:$src, ResVPR:$Rn,
7283               (SUBREG_TO_REG (i32 0), $Re, sub_32), 0)>;
7284
7285 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
7286 {
7287   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7288                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7289                          BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7290
7291   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
7292                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
7293                          BinOpFrag<(Neon_vduplane
7294                                      (fneg node:$LHS), node:$RHS)>>;
7295
7296   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_2s4s"),
7297                         op, VPR64, v2f32>;
7298
7299   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7300                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7301                          BinOpFrag<(fneg (Neon_vduplane
7302                                      node:$LHS, node:$RHS))>>;
7303
7304   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
7305                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
7306                          BinOpFrag<(Neon_vduplane
7307                                      (fneg node:$LHS), node:$RHS)>>;
7308
7309   def : NI_2VEfms_lane0<!cast<Instruction>(subop # "_4s4s"),
7310                         op, VPR128, v4f32>;
7311
7312   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7313                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7314                          BinOpFrag<(fneg (Neon_vduplane
7315                                      node:$LHS, node:$RHS))>>;
7316
7317   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
7318                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
7319                          BinOpFrag<(Neon_vduplane
7320                                      (fneg node:$LHS), node:$RHS)>>;
7321
7322   // Index can only be half of the max value for lane in 64-bit vector
7323
7324   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7325                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7326                         BinOpFrag<(fneg (Neon_vduplane
7327                                     node:$LHS, node:$RHS))>>;
7328
7329   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
7330                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
7331                         BinOpFrag<(Neon_vduplane
7332                                     (fneg node:$LHS), node:$RHS)>>;
7333
7334   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7335                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7336                         BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>;
7337
7338   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
7339                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
7340                         BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>;
7341
7342   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7343                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7344                              BinOpFrag<(fneg (Neon_combine_2d
7345                                          node:$LHS, node:$RHS))>>;
7346
7347   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
7348                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
7349                              BinOpFrag<(Neon_combine_2d
7350                                          (fneg node:$LHS), (fneg node:$RHS))>>;
7351 }
7352
7353 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
7354
7355 // Variant 3: Long type
7356 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
7357 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
7358
7359 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
7360   // vector register class for element is always 128-bit to cover the max index
7361   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7362                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
7363     let Inst{11} = {Index{1}};
7364     let Inst{21} = {Index{0}};
7365     let Inst{20-16} = Re;
7366   }
7367
7368   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7369                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
7370     let Inst{11} = {Index{1}};
7371     let Inst{21} = {Index{0}};
7372     let Inst{20-16} = Re;
7373   }
7374
7375   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7376   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7377                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7378     let Inst{11} = {Index{2}};
7379     let Inst{21} = {Index{1}};
7380     let Inst{20} = {Index{0}};
7381     let Inst{19-16} = Re{3-0};
7382   }
7383
7384   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7385                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7386     let Inst{11} = {Index{2}};
7387     let Inst{21} = {Index{1}};
7388     let Inst{20} = {Index{0}};
7389     let Inst{19-16} = Re{3-0};
7390   }
7391 }
7392
7393 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
7394 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
7395 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
7396 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
7397 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
7398 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
7399
7400 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
7401   // vector register class for element is always 128-bit to cover the max index
7402   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
7403                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
7404     let Inst{11} = {Index{1}};
7405     let Inst{21} = {Index{0}};
7406     let Inst{20-16} = Re;
7407   }
7408
7409   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
7410                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
7411     let Inst{11} = {Index{1}};
7412     let Inst{21} = {Index{0}};
7413     let Inst{20-16} = Re;
7414   }
7415
7416   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
7417   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
7418                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
7419     let Inst{11} = {Index{2}};
7420     let Inst{21} = {Index{1}};
7421     let Inst{20} = {Index{0}};
7422     let Inst{19-16} = Re{3-0};
7423   }
7424
7425   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
7426                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
7427     let Inst{11} = {Index{2}};
7428     let Inst{21} = {Index{1}};
7429     let Inst{20} = {Index{0}};
7430     let Inst{19-16} = Re{3-0};
7431   }
7432 }
7433
7434 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
7435 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
7436 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
7437
7438 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
7439           (FMOVdd $src)>;
7440
7441 // Pattern for lane in 128-bit vector
7442 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7443                      RegisterOperand EleOpVPR, ValueType ResTy,
7444                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7445                      SDPatternOperator hiop>
7446   : Pat<(ResTy (op (ResTy VPR128:$src),
7447           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7448           (HalfOpTy (Neon_vduplane
7449                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7450         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7451
7452 // Pattern for lane in 64-bit vector
7453 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7454                     RegisterOperand EleOpVPR, ValueType ResTy,
7455                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7456                     SDPatternOperator hiop>
7457   : Pat<(ResTy (op (ResTy VPR128:$src),
7458           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7459           (HalfOpTy (Neon_vduplane
7460                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7461         (INST VPR128:$src, VPR128:$Rn,
7462           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7463
7464 class NI_2VEL2_lane0<Instruction INST, SDPatternOperator op,
7465                      ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7466                      SDPatternOperator hiop, Instruction DupInst>
7467   : Pat<(ResTy (op (ResTy VPR128:$src),
7468           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7469           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7470         (INST VPR128:$src, VPR128:$Rn, (DupInst $Re), 0)>;
7471
7472 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
7473   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7474                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7475
7476   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7477                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>;
7478
7479   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7480                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7481
7482   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7483                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7484
7485   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7486                        op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7487
7488   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7489                        op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7490
7491   // Index can only be half of the max value for lane in 64-bit vector
7492
7493   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7494                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7495
7496   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7497                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>;
7498
7499   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7500                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7501
7502   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7503                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7504 }
7505
7506 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
7507 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
7508 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
7509 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
7510
7511 // Pattern for lane in 128-bit vector
7512 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
7513                          RegisterOperand EleOpVPR, ValueType ResTy,
7514                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7515                          SDPatternOperator hiop>
7516   : Pat<(ResTy (op
7517           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7518           (HalfOpTy (Neon_vduplane
7519                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7520         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
7521
7522 // Pattern for lane in 64-bit vector
7523 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
7524                         RegisterOperand EleOpVPR, ValueType ResTy,
7525                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
7526                         SDPatternOperator hiop>
7527   : Pat<(ResTy (op
7528           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7529           (HalfOpTy (Neon_vduplane
7530                       (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
7531         (INST VPR128:$Rn,
7532           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
7533
7534 // Pattern for fixed lane 0
7535 class NI_2VEL2_mul_lane0<Instruction INST, SDPatternOperator op,
7536                          ValueType ResTy, ValueType OpTy, ValueType HalfOpTy,
7537                          SDPatternOperator hiop, Instruction DupInst>
7538   : Pat<(ResTy (op
7539           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
7540           (HalfOpTy (Neon_vdup (i32 GPR32:$Re))))),
7541         (INST VPR128:$Rn, (DupInst $Re), 0)>;
7542
7543 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
7544   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7545                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>;
7546
7547   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7548                          op, VPR64, VPR128, v2i64, v2i32, v4i32>;
7549
7550   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7551                          op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7552
7553   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7554                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7555
7556   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_4s8h"),
7557                            op, v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7558
7559   def : NI_2VEL2_mul_lane0<!cast<Instruction>(subop # "_2d4s"),
7560                            op, v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7561
7562   // Index can only be half of the max value for lane in 64-bit vector
7563
7564   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7565                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>;
7566
7567   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7568                         op, VPR64, VPR64, v2i64, v2i32, v2i32>;
7569
7570   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7571                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7572
7573   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7574                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7575 }
7576
7577 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
7578 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
7579 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
7580
7581 multiclass NI_qdma<SDPatternOperator op> {
7582   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7583                     (op node:$Ra,
7584                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7585
7586   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
7587                     (op node:$Ra,
7588                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
7589 }
7590
7591 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
7592 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
7593
7594 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
7595   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
7596                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
7597                      v4i32, v4i16, v8i16>;
7598
7599   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
7600                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
7601                      v2i64, v2i32, v4i32>;
7602
7603   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
7604                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
7605                        v4i32, v8i16, v8i16, v4i16, Neon_High8H>;
7606
7607   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
7608                        !cast<PatFrag>(op # "_2d"), VPR128,
7609                        v2i64, v4i32, v4i32, v2i32, Neon_High4S>;
7610
7611   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_4s8h"),
7612                        !cast<PatFrag>(op # "_4s"),
7613                        v4i32, v8i16, v4i16, Neon_High8H, DUP8h>;
7614
7615   def : NI_2VEL2_lane0<!cast<Instruction>(subop # "_2d4s"),
7616                        !cast<PatFrag>(op # "_2d"),
7617                        v2i64, v4i32, v2i32, Neon_High4S, DUP4s>;
7618
7619   // Index can only be half of the max value for lane in 64-bit vector
7620
7621   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
7622                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
7623                     v4i32, v4i16, v4i16>;
7624
7625   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
7626                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
7627                     v2i64, v2i32, v2i32>;
7628
7629   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
7630                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
7631                       v4i32, v8i16, v4i16, v4i16, Neon_High8H>;
7632
7633   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
7634                       !cast<PatFrag>(op # "_2d"), VPR64,
7635                       v2i64, v4i32, v2i32, v2i32, Neon_High4S>;
7636 }
7637
7638 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
7639 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
7640
7641 // End of implementation for instruction class (3V Elem)
7642
7643 class NeonI_REV<string asmop, string Res, bits<2> size, bit Q, bit U,
7644                 bits<5> opcode, RegisterOperand ResVPR, ValueType ResTy,
7645                 SDPatternOperator Neon_Rev>
7646   : NeonI_2VMisc<Q, U, size, opcode,
7647                (outs ResVPR:$Rd), (ins ResVPR:$Rn),
7648                asmop # "\t$Rd." # Res # ", $Rn." # Res,
7649                [(set (ResTy ResVPR:$Rd),
7650                   (ResTy (Neon_Rev (ResTy ResVPR:$Rn))))],
7651                NoItinerary> ;
7652
7653 def REV64_16b : NeonI_REV<"rev64", "16b", 0b00, 0b1, 0b0, 0b00000, VPR128,
7654                           v16i8, Neon_rev64>;
7655 def REV64_8h : NeonI_REV<"rev64", "8h", 0b01, 0b1, 0b0, 0b00000, VPR128,
7656                          v8i16, Neon_rev64>;
7657 def REV64_4s : NeonI_REV<"rev64", "4s", 0b10, 0b1, 0b0, 0b00000, VPR128,
7658                          v4i32, Neon_rev64>;
7659 def REV64_8b : NeonI_REV<"rev64", "8b", 0b00, 0b0, 0b0, 0b00000, VPR64,
7660                          v8i8, Neon_rev64>;
7661 def REV64_4h : NeonI_REV<"rev64", "4h", 0b01, 0b0, 0b0, 0b00000, VPR64,
7662                          v4i16, Neon_rev64>;
7663 def REV64_2s : NeonI_REV<"rev64", "2s", 0b10, 0b0, 0b0, 0b00000, VPR64,
7664                          v2i32, Neon_rev64>;
7665
7666 def : Pat<(v4f32 (Neon_rev64 (v4f32 VPR128:$Rn))), (REV64_4s VPR128:$Rn)>;
7667 def : Pat<(v2f32 (Neon_rev64 (v2f32 VPR64:$Rn))), (REV64_2s VPR64:$Rn)>;
7668
7669 def REV32_16b : NeonI_REV<"rev32", "16b", 0b00, 0b1, 0b1, 0b00000, VPR128,
7670                           v16i8, Neon_rev32>;
7671 def REV32_8h : NeonI_REV<"rev32", "8h", 0b01, 0b1, 0b1, 0b00000, VPR128,
7672                           v8i16, Neon_rev32>;
7673 def REV32_8b : NeonI_REV<"rev32", "8b", 0b00, 0b0, 0b1, 0b00000, VPR64,
7674                          v8i8, Neon_rev32>;
7675 def REV32_4h : NeonI_REV<"rev32", "4h", 0b01, 0b0, 0b1, 0b00000, VPR64,
7676                          v4i16, Neon_rev32>;
7677
7678 def REV16_16b : NeonI_REV<"rev16", "16b", 0b00, 0b1, 0b0, 0b00001, VPR128,
7679                           v16i8, Neon_rev16>;
7680 def REV16_8b : NeonI_REV<"rev16", "8b", 0b00, 0b0, 0b0, 0b00001, VPR64,
7681                          v8i8, Neon_rev16>;
7682
7683 multiclass NeonI_PairwiseAdd<string asmop, bit U, bits<5> opcode,
7684                              SDPatternOperator Neon_Padd> {
7685   def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7686                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7687                            asmop # "\t$Rd.8h, $Rn.16b",
7688                            [(set (v8i16 VPR128:$Rd),
7689                               (v8i16 (Neon_Padd (v16i8 VPR128:$Rn))))],
7690                            NoItinerary>;
7691
7692   def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7693                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7694                           asmop # "\t$Rd.4h, $Rn.8b",
7695                           [(set (v4i16 VPR64:$Rd),
7696                              (v4i16 (Neon_Padd (v8i8 VPR64:$Rn))))],
7697                           NoItinerary>;
7698
7699   def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7700                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7701                            asmop # "\t$Rd.4s, $Rn.8h",
7702                            [(set (v4i32 VPR128:$Rd),
7703                               (v4i32 (Neon_Padd (v8i16 VPR128:$Rn))))],
7704                            NoItinerary>;
7705
7706   def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7707                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7708                           asmop # "\t$Rd.2s, $Rn.4h",
7709                           [(set (v2i32 VPR64:$Rd),
7710                              (v2i32 (Neon_Padd (v4i16 VPR64:$Rn))))],
7711                           NoItinerary>;
7712
7713   def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7714                            (outs VPR128:$Rd), (ins VPR128:$Rn),
7715                            asmop # "\t$Rd.2d, $Rn.4s",
7716                            [(set (v2i64 VPR128:$Rd),
7717                               (v2i64 (Neon_Padd (v4i32 VPR128:$Rn))))],
7718                            NoItinerary>;
7719
7720   def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7721                           (outs VPR64:$Rd), (ins VPR64:$Rn),
7722                           asmop # "\t$Rd.1d, $Rn.2s",
7723                           [(set (v1i64 VPR64:$Rd),
7724                              (v1i64 (Neon_Padd (v2i32 VPR64:$Rn))))],
7725                           NoItinerary>;
7726 }
7727
7728 defm SADDLP : NeonI_PairwiseAdd<"saddlp", 0b0, 0b00010,
7729                                 int_arm_neon_vpaddls>;
7730 defm UADDLP : NeonI_PairwiseAdd<"uaddlp", 0b1, 0b00010,
7731                                 int_arm_neon_vpaddlu>;
7732
7733 def : Pat<(v1i64 (int_aarch64_neon_saddlv (v2i32 VPR64:$Rn))),
7734           (SADDLP2s1d $Rn)>;
7735 def : Pat<(v1i64 (int_aarch64_neon_uaddlv (v2i32 VPR64:$Rn))),
7736           (UADDLP2s1d $Rn)>;
7737
7738 multiclass NeonI_PairwiseAddAcc<string asmop, bit U, bits<5> opcode,
7739                              SDPatternOperator Neon_Padd> {
7740   let Constraints = "$src = $Rd" in {
7741     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
7742                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7743                              asmop # "\t$Rd.8h, $Rn.16b",
7744                              [(set (v8i16 VPR128:$Rd),
7745                                 (v8i16 (Neon_Padd
7746                                   (v8i16 VPR128:$src), (v16i8 VPR128:$Rn))))],
7747                              NoItinerary>;
7748
7749     def 8b4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
7750                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7751                             asmop # "\t$Rd.4h, $Rn.8b",
7752                             [(set (v4i16 VPR64:$Rd),
7753                                (v4i16 (Neon_Padd
7754                                  (v4i16 VPR64:$src), (v8i8 VPR64:$Rn))))],
7755                             NoItinerary>;
7756
7757     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
7758                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7759                             asmop # "\t$Rd.4s, $Rn.8h",
7760                             [(set (v4i32 VPR128:$Rd),
7761                                (v4i32 (Neon_Padd
7762                                  (v4i32 VPR128:$src), (v8i16 VPR128:$Rn))))],
7763                             NoItinerary>;
7764
7765     def 4h2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
7766                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7767                             asmop # "\t$Rd.2s, $Rn.4h",
7768                             [(set (v2i32 VPR64:$Rd),
7769                                (v2i32 (Neon_Padd
7770                                  (v2i32 VPR64:$src), (v4i16 VPR64:$Rn))))],
7771                             NoItinerary>;
7772
7773     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
7774                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7775                             asmop # "\t$Rd.2d, $Rn.4s",
7776                             [(set (v2i64 VPR128:$Rd),
7777                                (v2i64 (Neon_Padd
7778                                  (v2i64 VPR128:$src), (v4i32 VPR128:$Rn))))],
7779                             NoItinerary>;
7780
7781     def 2s1d : NeonI_2VMisc<0b0, U, 0b10, opcode,
7782                             (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7783                             asmop # "\t$Rd.1d, $Rn.2s",
7784                             [(set (v1i64 VPR64:$Rd),
7785                                (v1i64 (Neon_Padd
7786                                  (v1i64 VPR64:$src), (v2i32 VPR64:$Rn))))],
7787                             NoItinerary>;
7788   }
7789 }
7790
7791 defm SADALP : NeonI_PairwiseAddAcc<"sadalp", 0b0, 0b00110,
7792                                    int_arm_neon_vpadals>;
7793 defm UADALP : NeonI_PairwiseAddAcc<"uadalp", 0b1, 0b00110,
7794                                    int_arm_neon_vpadalu>;
7795
7796 multiclass NeonI_2VMisc_BHSDsize_1Arg<string asmop, bit U, bits<5> opcode> {
7797   def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7798                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7799                          asmop # "\t$Rd.16b, $Rn.16b",
7800                          [], NoItinerary>;
7801
7802   def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7803                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7804                         asmop # "\t$Rd.8h, $Rn.8h",
7805                         [], NoItinerary>;
7806
7807   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7808                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7809                         asmop # "\t$Rd.4s, $Rn.4s",
7810                         [], NoItinerary>;
7811
7812   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7813                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7814                         asmop # "\t$Rd.2d, $Rn.2d",
7815                         [], NoItinerary>;
7816
7817   def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7818                          (outs VPR64:$Rd), (ins VPR64:$Rn),
7819                          asmop # "\t$Rd.8b, $Rn.8b",
7820                          [], NoItinerary>;
7821
7822   def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7823                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7824                         asmop # "\t$Rd.4h, $Rn.4h",
7825                         [], NoItinerary>;
7826
7827   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7828                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7829                         asmop # "\t$Rd.2s, $Rn.2s",
7830                         [], NoItinerary>;
7831 }
7832
7833 defm SQABS : NeonI_2VMisc_BHSDsize_1Arg<"sqabs", 0b0, 0b00111>;
7834 defm SQNEG : NeonI_2VMisc_BHSDsize_1Arg<"sqneg", 0b1, 0b00111>;
7835 defm ABS : NeonI_2VMisc_BHSDsize_1Arg<"abs", 0b0, 0b01011>;
7836 defm NEG : NeonI_2VMisc_BHSDsize_1Arg<"neg", 0b1, 0b01011>;
7837
7838 multiclass NeonI_2VMisc_BHSD_1Arg_Pattern<string Prefix,
7839                                           SDPatternOperator Neon_Op> {
7840   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$Rn))),
7841             (v16i8 (!cast<Instruction>(Prefix # 16b) (v16i8 VPR128:$Rn)))>;
7842
7843   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$Rn))),
7844             (v8i16 (!cast<Instruction>(Prefix # 8h) (v8i16 VPR128:$Rn)))>;
7845
7846   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$Rn))),
7847             (v4i32 (!cast<Instruction>(Prefix # 4s) (v4i32 VPR128:$Rn)))>;
7848
7849   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$Rn))),
7850             (v2i64 (!cast<Instruction>(Prefix # 2d) (v2i64 VPR128:$Rn)))>;
7851
7852   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$Rn))),
7853             (v8i8 (!cast<Instruction>(Prefix # 8b) (v8i8 VPR64:$Rn)))>;
7854
7855   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$Rn))),
7856             (v4i16 (!cast<Instruction>(Prefix # 4h) (v4i16 VPR64:$Rn)))>;
7857
7858   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$Rn))),
7859             (v2i32 (!cast<Instruction>(Prefix # 2s) (v2i32 VPR64:$Rn)))>;
7860 }
7861
7862 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQABS", int_arm_neon_vqabs>;
7863 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"SQNEG", int_arm_neon_vqneg>;
7864 defm : NeonI_2VMisc_BHSD_1Arg_Pattern<"ABS", int_arm_neon_vabs>;
7865
7866 def : Pat<(v16i8 (sub
7867             (v16i8 Neon_AllZero),
7868             (v16i8 VPR128:$Rn))),
7869           (v16i8 (NEG16b (v16i8 VPR128:$Rn)))>;
7870 def : Pat<(v8i8 (sub
7871             (v8i8 Neon_AllZero),
7872             (v8i8 VPR64:$Rn))),
7873           (v8i8 (NEG8b (v8i8 VPR64:$Rn)))>;
7874 def : Pat<(v8i16 (sub
7875             (v8i16 (bitconvert (v16i8 Neon_AllZero))),
7876             (v8i16 VPR128:$Rn))),
7877           (v8i16 (NEG8h (v8i16 VPR128:$Rn)))>;
7878 def : Pat<(v4i16 (sub
7879             (v4i16 (bitconvert (v8i8 Neon_AllZero))),
7880             (v4i16 VPR64:$Rn))),
7881           (v4i16 (NEG4h (v4i16 VPR64:$Rn)))>;
7882 def : Pat<(v4i32 (sub
7883             (v4i32 (bitconvert (v16i8 Neon_AllZero))),
7884             (v4i32 VPR128:$Rn))),
7885           (v4i32 (NEG4s (v4i32 VPR128:$Rn)))>;
7886 def : Pat<(v2i32 (sub
7887             (v2i32 (bitconvert (v8i8 Neon_AllZero))),
7888             (v2i32 VPR64:$Rn))),
7889           (v2i32 (NEG2s (v2i32 VPR64:$Rn)))>;
7890 def : Pat<(v2i64 (sub
7891             (v2i64 (bitconvert (v16i8 Neon_AllZero))),
7892             (v2i64 VPR128:$Rn))),
7893           (v2i64 (NEG2d (v2i64 VPR128:$Rn)))>;
7894
7895 multiclass NeonI_2VMisc_BHSDsize_2Args<string asmop, bit U, bits<5> opcode> {
7896   let Constraints = "$src = $Rd" in {
7897     def 16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
7898                            (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7899                            asmop # "\t$Rd.16b, $Rn.16b",
7900                            [], NoItinerary>;
7901
7902     def 8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
7903                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7904                           asmop # "\t$Rd.8h, $Rn.8h",
7905                           [], NoItinerary>;
7906
7907     def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
7908                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7909                           asmop # "\t$Rd.4s, $Rn.4s",
7910                           [], NoItinerary>;
7911
7912     def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
7913                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
7914                           asmop # "\t$Rd.2d, $Rn.2d",
7915                           [], NoItinerary>;
7916
7917     def 8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
7918                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7919                           asmop # "\t$Rd.8b, $Rn.8b",
7920                           [], NoItinerary>;
7921
7922     def 4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
7923                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7924                           asmop # "\t$Rd.4h, $Rn.4h",
7925                           [], NoItinerary>;
7926
7927     def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
7928                           (outs VPR64:$Rd), (ins VPR64:$src, VPR64:$Rn),
7929                           asmop # "\t$Rd.2s, $Rn.2s",
7930                           [], NoItinerary>;
7931   }
7932 }
7933
7934 defm SUQADD : NeonI_2VMisc_BHSDsize_2Args<"suqadd", 0b0, 0b00011>;
7935 defm USQADD : NeonI_2VMisc_BHSDsize_2Args<"usqadd", 0b1, 0b00011>;
7936
7937 multiclass NeonI_2VMisc_BHSD_2Args_Pattern<string Prefix,
7938                                            SDPatternOperator Neon_Op> {
7939   def : Pat<(v16i8 (Neon_Op (v16i8 VPR128:$src), (v16i8 VPR128:$Rn))),
7940             (v16i8 (!cast<Instruction>(Prefix # 16b)
7941               (v16i8 VPR128:$src), (v16i8 VPR128:$Rn)))>;
7942
7943   def : Pat<(v8i16 (Neon_Op (v8i16 VPR128:$src), (v8i16 VPR128:$Rn))),
7944             (v8i16 (!cast<Instruction>(Prefix # 8h)
7945               (v8i16 VPR128:$src), (v8i16 VPR128:$Rn)))>;
7946
7947   def : Pat<(v4i32 (Neon_Op (v4i32 VPR128:$src), (v4i32 VPR128:$Rn))),
7948             (v4i32 (!cast<Instruction>(Prefix # 4s)
7949               (v4i32 VPR128:$src), (v4i32 VPR128:$Rn)))>;
7950
7951   def : Pat<(v2i64 (Neon_Op (v2i64 VPR128:$src), (v2i64 VPR128:$Rn))),
7952             (v2i64 (!cast<Instruction>(Prefix # 2d)
7953               (v2i64 VPR128:$src), (v2i64 VPR128:$Rn)))>;
7954
7955   def : Pat<(v8i8 (Neon_Op (v8i8 VPR64:$src), (v8i8 VPR64:$Rn))),
7956             (v8i8 (!cast<Instruction>(Prefix # 8b)
7957               (v8i8 VPR64:$src), (v8i8 VPR64:$Rn)))>;
7958
7959   def : Pat<(v4i16 (Neon_Op (v4i16 VPR64:$src), (v4i16 VPR64:$Rn))),
7960             (v4i16 (!cast<Instruction>(Prefix # 4h)
7961               (v4i16 VPR64:$src), (v4i16 VPR64:$Rn)))>;
7962
7963   def : Pat<(v2i32 (Neon_Op (v2i32 VPR64:$src), (v2i32 VPR64:$Rn))),
7964             (v2i32 (!cast<Instruction>(Prefix # 2s)
7965               (v2i32 VPR64:$src), (v2i32 VPR64:$Rn)))>;
7966 }
7967
7968 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"SUQADD", int_aarch64_neon_suqadd>;
7969 defm : NeonI_2VMisc_BHSD_2Args_Pattern<"USQADD", int_aarch64_neon_usqadd>;
7970
7971 multiclass NeonI_2VMisc_BHSsizes<string asmop, bit U,
7972                           SDPatternOperator Neon_Op> {
7973   def 16b : NeonI_2VMisc<0b1, U, 0b00, 0b00100,
7974                          (outs VPR128:$Rd), (ins VPR128:$Rn),
7975                          asmop # "\t$Rd.16b, $Rn.16b",
7976                          [(set (v16i8 VPR128:$Rd),
7977                             (v16i8 (Neon_Op (v16i8 VPR128:$Rn))))],
7978                          NoItinerary>;
7979
7980   def 8h : NeonI_2VMisc<0b1, U, 0b01, 0b00100,
7981                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7982                         asmop # "\t$Rd.8h, $Rn.8h",
7983                         [(set (v8i16 VPR128:$Rd),
7984                            (v8i16 (Neon_Op (v8i16 VPR128:$Rn))))],
7985                         NoItinerary>;
7986
7987   def 4s : NeonI_2VMisc<0b1, U, 0b10, 0b00100,
7988                         (outs VPR128:$Rd), (ins VPR128:$Rn),
7989                         asmop # "\t$Rd.4s, $Rn.4s",
7990                         [(set (v4i32 VPR128:$Rd),
7991                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
7992                         NoItinerary>;
7993
7994   def 8b : NeonI_2VMisc<0b0, U, 0b00, 0b00100,
7995                         (outs VPR64:$Rd), (ins VPR64:$Rn),
7996                         asmop # "\t$Rd.8b, $Rn.8b",
7997                         [(set (v8i8 VPR64:$Rd),
7998                            (v8i8 (Neon_Op (v8i8 VPR64:$Rn))))],
7999                         NoItinerary>;
8000
8001   def 4h : NeonI_2VMisc<0b0, U, 0b01, 0b00100,
8002                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8003                         asmop # "\t$Rd.4h, $Rn.4h",
8004                         [(set (v4i16 VPR64:$Rd),
8005                            (v4i16 (Neon_Op (v4i16 VPR64:$Rn))))],
8006                         NoItinerary>;
8007
8008   def 2s : NeonI_2VMisc<0b0, U, 0b10, 0b00100,
8009                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8010                         asmop # "\t$Rd.2s, $Rn.2s",
8011                         [(set (v2i32 VPR64:$Rd),
8012                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8013                         NoItinerary>;
8014 }
8015
8016 defm CLS : NeonI_2VMisc_BHSsizes<"cls", 0b0, int_arm_neon_vcls>;
8017 defm CLZ : NeonI_2VMisc_BHSsizes<"clz", 0b1, ctlz>;
8018
8019 multiclass NeonI_2VMisc_Bsize<string asmop, bit U, bits<2> size,
8020                               bits<5> Opcode> {
8021   def 16b : NeonI_2VMisc<0b1, U, size, Opcode,
8022                          (outs VPR128:$Rd), (ins VPR128:$Rn),
8023                          asmop # "\t$Rd.16b, $Rn.16b",
8024                          [], NoItinerary>;
8025
8026   def 8b : NeonI_2VMisc<0b0, U, size, Opcode,
8027                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8028                         asmop # "\t$Rd.8b, $Rn.8b",
8029                         [], NoItinerary>;
8030 }
8031
8032 defm CNT : NeonI_2VMisc_Bsize<"cnt", 0b0, 0b00, 0b00101>;
8033 defm NOT : NeonI_2VMisc_Bsize<"not", 0b1, 0b00, 0b00101>;
8034 defm RBIT : NeonI_2VMisc_Bsize<"rbit", 0b1, 0b01, 0b00101>;
8035
8036 def : NeonInstAlias<"mvn $Rd.16b, $Rn.16b",
8037                     (NOT16b VPR128:$Rd, VPR128:$Rn), 0>;
8038 def : NeonInstAlias<"mvn $Rd.8b, $Rn.8b",
8039                     (NOT8b VPR64:$Rd, VPR64:$Rn), 0>;
8040
8041 def : Pat<(v16i8 (ctpop (v16i8 VPR128:$Rn))),
8042           (v16i8 (CNT16b (v16i8 VPR128:$Rn)))>;
8043 def : Pat<(v8i8 (ctpop (v8i8 VPR64:$Rn))),
8044           (v8i8 (CNT8b (v8i8 VPR64:$Rn)))>;
8045
8046 def : Pat<(v16i8 (xor
8047             (v16i8 VPR128:$Rn),
8048             (v16i8 Neon_AllOne))),
8049           (v16i8 (NOT16b (v16i8 VPR128:$Rn)))>;
8050 def : Pat<(v8i8 (xor
8051             (v8i8 VPR64:$Rn),
8052             (v8i8 Neon_AllOne))),
8053           (v8i8 (NOT8b (v8i8 VPR64:$Rn)))>;
8054 def : Pat<(v8i16 (xor
8055             (v8i16 VPR128:$Rn),
8056             (v8i16 (bitconvert (v16i8 Neon_AllOne))))),
8057           (NOT16b VPR128:$Rn)>;
8058 def : Pat<(v4i16 (xor
8059             (v4i16 VPR64:$Rn),
8060             (v4i16 (bitconvert (v8i8 Neon_AllOne))))),
8061           (NOT8b VPR64:$Rn)>;
8062 def : Pat<(v4i32 (xor
8063             (v4i32 VPR128:$Rn),
8064             (v4i32 (bitconvert (v16i8 Neon_AllOne))))),
8065           (NOT16b VPR128:$Rn)>;
8066 def : Pat<(v2i32 (xor
8067             (v2i32 VPR64:$Rn),
8068             (v2i32 (bitconvert (v8i8 Neon_AllOne))))),
8069           (NOT8b VPR64:$Rn)>;
8070 def : Pat<(v2i64 (xor
8071             (v2i64 VPR128:$Rn),
8072             (v2i64 (bitconvert (v16i8 Neon_AllOne))))),
8073           (NOT16b VPR128:$Rn)>;
8074
8075 def : Pat<(v16i8 (int_aarch64_neon_rbit (v16i8 VPR128:$Rn))),
8076           (v16i8 (RBIT16b (v16i8 VPR128:$Rn)))>;
8077 def : Pat<(v8i8 (int_aarch64_neon_rbit (v8i8 VPR64:$Rn))),
8078           (v8i8 (RBIT8b (v8i8 VPR64:$Rn)))>;
8079
8080 multiclass NeonI_2VMisc_SDsizes<string asmop, bit U, bits<5> opcode,
8081                                 SDPatternOperator Neon_Op> {
8082   def 4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8083                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8084                         asmop # "\t$Rd.4s, $Rn.4s",
8085                         [(set (v4f32 VPR128:$Rd),
8086                            (v4f32 (Neon_Op (v4f32 VPR128:$Rn))))],
8087                         NoItinerary>;
8088
8089   def 2d : NeonI_2VMisc<0b1, U, 0b11, opcode,
8090                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8091                         asmop # "\t$Rd.2d, $Rn.2d",
8092                         [(set (v2f64 VPR128:$Rd),
8093                            (v2f64 (Neon_Op (v2f64 VPR128:$Rn))))],
8094                         NoItinerary>;
8095
8096   def 2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8097                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8098                         asmop # "\t$Rd.2s, $Rn.2s",
8099                         [(set (v2f32 VPR64:$Rd),
8100                            (v2f32 (Neon_Op (v2f32 VPR64:$Rn))))],
8101                         NoItinerary>;
8102 }
8103
8104 defm FABS : NeonI_2VMisc_SDsizes<"fabs", 0b0, 0b01111, fabs>;
8105 defm FNEG : NeonI_2VMisc_SDsizes<"fneg", 0b1, 0b01111, fneg>;
8106
8107 multiclass NeonI_2VMisc_HSD_Narrow<string asmop, bit U, bits<5> opcode> {
8108   def 8h8b : NeonI_2VMisc<0b0, U, 0b00, opcode,
8109                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8110                           asmop # "\t$Rd.8b, $Rn.8h",
8111                           [], NoItinerary>;
8112
8113   def 4s4h : NeonI_2VMisc<0b0, U, 0b01, opcode,
8114                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8115                           asmop # "\t$Rd.4h, $Rn.4s",
8116                           [], NoItinerary>;
8117
8118   def 2d2s : NeonI_2VMisc<0b0, U, 0b10, opcode,
8119                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8120                           asmop # "\t$Rd.2s, $Rn.2d",
8121                           [], NoItinerary>;
8122
8123   let Constraints = "$Rd = $src" in {
8124     def 8h16b : NeonI_2VMisc<0b1, U, 0b00, opcode,
8125                              (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8126                              asmop # "2\t$Rd.16b, $Rn.8h",
8127                              [], NoItinerary>;
8128
8129     def 4s8h : NeonI_2VMisc<0b1, U, 0b01, opcode,
8130                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8131                             asmop # "2\t$Rd.8h, $Rn.4s",
8132                             [], NoItinerary>;
8133
8134     def 2d4s : NeonI_2VMisc<0b1, U, 0b10, opcode,
8135                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8136                             asmop # "2\t$Rd.4s, $Rn.2d",
8137                             [], NoItinerary>;
8138   }
8139 }
8140
8141 defm XTN : NeonI_2VMisc_HSD_Narrow<"xtn", 0b0, 0b10010>;
8142 defm SQXTUN : NeonI_2VMisc_HSD_Narrow<"sqxtun", 0b1, 0b10010>;
8143 defm SQXTN : NeonI_2VMisc_HSD_Narrow<"sqxtn", 0b0, 0b10100>;
8144 defm UQXTN : NeonI_2VMisc_HSD_Narrow<"uqxtn", 0b1, 0b10100>;
8145
8146 multiclass NeonI_2VMisc_Narrow_Patterns<string Prefix,
8147                                         SDPatternOperator Neon_Op> {
8148   def : Pat<(v8i8 (Neon_Op (v8i16 VPR128:$Rn))),
8149             (v8i8 (!cast<Instruction>(Prefix # 8h8b) (v8i16 VPR128:$Rn)))>;
8150
8151   def : Pat<(v4i16 (Neon_Op (v4i32 VPR128:$Rn))),
8152             (v4i16 (!cast<Instruction>(Prefix # 4s4h) (v4i32 VPR128:$Rn)))>;
8153
8154   def : Pat<(v2i32 (Neon_Op (v2i64 VPR128:$Rn))),
8155             (v2i32 (!cast<Instruction>(Prefix # 2d2s) (v2i64 VPR128:$Rn)))>;
8156
8157   def : Pat<(v16i8 (concat_vectors
8158               (v8i8 VPR64:$src),
8159               (v8i8 (Neon_Op (v8i16 VPR128:$Rn))))),
8160             (!cast<Instruction>(Prefix # 8h16b)
8161               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8162               VPR128:$Rn)>;
8163
8164   def : Pat<(v8i16 (concat_vectors
8165               (v4i16 VPR64:$src),
8166               (v4i16 (Neon_Op (v4i32 VPR128:$Rn))))),
8167             (!cast<Instruction>(Prefix # 4s8h)
8168               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8169               VPR128:$Rn)>;
8170
8171   def : Pat<(v4i32 (concat_vectors
8172               (v2i32 VPR64:$src),
8173               (v2i32 (Neon_Op (v2i64 VPR128:$Rn))))),
8174             (!cast<Instruction>(Prefix # 2d4s)
8175               (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64),
8176               VPR128:$Rn)>;
8177 }
8178
8179 defm : NeonI_2VMisc_Narrow_Patterns<"XTN", trunc>;
8180 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTUN", int_arm_neon_vqmovnsu>;
8181 defm : NeonI_2VMisc_Narrow_Patterns<"SQXTN", int_arm_neon_vqmovns>;
8182 defm : NeonI_2VMisc_Narrow_Patterns<"UQXTN", int_arm_neon_vqmovnu>;
8183
8184 multiclass NeonI_2VMisc_SHIFT<string asmop, bit U, bits<5> opcode> {
8185   let DecoderMethod = "DecodeSHLLInstruction" in {
8186     def 8b8h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8187                             (outs VPR128:$Rd),
8188                             (ins VPR64:$Rn, uimm_exact8:$Imm),
8189                             asmop # "\t$Rd.8h, $Rn.8b, $Imm",
8190                             [], NoItinerary>;
8191
8192     def 4h4s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8193                             (outs VPR128:$Rd),
8194                             (ins VPR64:$Rn, uimm_exact16:$Imm),
8195                             asmop # "\t$Rd.4s, $Rn.4h, $Imm",
8196                             [], NoItinerary>;
8197
8198     def 2s2d : NeonI_2VMisc<0b0, U, 0b10, opcode,
8199                             (outs VPR128:$Rd),
8200                             (ins VPR64:$Rn, uimm_exact32:$Imm),
8201                             asmop # "\t$Rd.2d, $Rn.2s, $Imm",
8202                             [], NoItinerary>;
8203
8204     def 16b8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8205                             (outs VPR128:$Rd),
8206                             (ins VPR128:$Rn, uimm_exact8:$Imm),
8207                             asmop # "2\t$Rd.8h, $Rn.16b, $Imm",
8208                             [], NoItinerary>;
8209
8210     def 8h4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8211                             (outs VPR128:$Rd),
8212                             (ins VPR128:$Rn, uimm_exact16:$Imm),
8213                             asmop # "2\t$Rd.4s, $Rn.8h, $Imm",
8214                             [], NoItinerary>;
8215
8216     def 4s2d : NeonI_2VMisc<0b1, U, 0b10, opcode,
8217                             (outs VPR128:$Rd),
8218                             (ins VPR128:$Rn, uimm_exact32:$Imm),
8219                             asmop # "2\t$Rd.2d, $Rn.4s, $Imm",
8220                             [], NoItinerary>;
8221   }
8222 }
8223
8224 defm SHLL : NeonI_2VMisc_SHIFT<"shll", 0b1, 0b10011>;
8225
8226 class NeonI_SHLL_Patterns<ValueType OpTy, ValueType DesTy,
8227                           SDPatternOperator ExtOp, Operand Neon_Imm,
8228                           string suffix>
8229   : Pat<(DesTy (shl
8230           (DesTy (ExtOp (OpTy VPR64:$Rn))),
8231             (DesTy (Neon_vdup
8232               (i32 Neon_Imm:$Imm))))),
8233         (!cast<Instruction>("SHLL" # suffix) VPR64:$Rn, Neon_Imm:$Imm)>;
8234
8235 class NeonI_SHLL_High_Patterns<ValueType OpTy, ValueType DesTy,
8236                                SDPatternOperator ExtOp, Operand Neon_Imm,
8237                                string suffix, PatFrag GetHigh>
8238   : Pat<(DesTy (shl
8239           (DesTy (ExtOp
8240             (OpTy (GetHigh VPR128:$Rn)))),
8241               (DesTy (Neon_vdup
8242                 (i32 Neon_Imm:$Imm))))),
8243         (!cast<Instruction>("SHLL" # suffix) VPR128:$Rn, Neon_Imm:$Imm)>;
8244
8245 def : NeonI_SHLL_Patterns<v8i8, v8i16, zext, uimm_exact8, "8b8h">;
8246 def : NeonI_SHLL_Patterns<v8i8, v8i16, sext, uimm_exact8, "8b8h">;
8247 def : NeonI_SHLL_Patterns<v4i16, v4i32, zext, uimm_exact16, "4h4s">;
8248 def : NeonI_SHLL_Patterns<v4i16, v4i32, sext, uimm_exact16, "4h4s">;
8249 def : NeonI_SHLL_Patterns<v2i32, v2i64, zext, uimm_exact32, "2s2d">;
8250 def : NeonI_SHLL_Patterns<v2i32, v2i64, sext, uimm_exact32, "2s2d">;
8251 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, zext, uimm_exact8, "16b8h",
8252                                Neon_High16B>;
8253 def : NeonI_SHLL_High_Patterns<v8i8, v8i16, sext, uimm_exact8, "16b8h",
8254                                Neon_High16B>;
8255 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, zext, uimm_exact16, "8h4s",
8256                                Neon_High8H>;
8257 def : NeonI_SHLL_High_Patterns<v4i16, v4i32, sext, uimm_exact16, "8h4s",
8258                                Neon_High8H>;
8259 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, zext, uimm_exact32, "4s2d",
8260                                Neon_High4S>;
8261 def : NeonI_SHLL_High_Patterns<v2i32, v2i64, sext, uimm_exact32, "4s2d",
8262                                Neon_High4S>;
8263
8264 multiclass NeonI_2VMisc_SD_Narrow<string asmop, bit U, bits<5> opcode> {
8265   def 4s4h : NeonI_2VMisc<0b0, U, 0b00, opcode,
8266                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8267                           asmop # "\t$Rd.4h, $Rn.4s",
8268                           [], NoItinerary>;
8269
8270   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8271                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8272                           asmop # "\t$Rd.2s, $Rn.2d",
8273                           [], NoItinerary>;
8274
8275   let Constraints = "$src = $Rd" in {
8276     def 4s8h : NeonI_2VMisc<0b1, U, 0b00, opcode,
8277                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8278                             asmop # "2\t$Rd.8h, $Rn.4s",
8279                             [], NoItinerary>;
8280
8281     def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8282                             (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8283                             asmop # "2\t$Rd.4s, $Rn.2d",
8284                             [], NoItinerary>;
8285   }
8286 }
8287
8288 defm FCVTN : NeonI_2VMisc_SD_Narrow<"fcvtn", 0b0, 0b10110>;
8289
8290 multiclass NeonI_2VMisc_Narrow_Pattern<string prefix,
8291                                        SDPatternOperator f32_to_f16_Op,
8292                                        SDPatternOperator f64_to_f32_Op> {
8293
8294   def : Pat<(v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))),
8295               (!cast<Instruction>(prefix # "4s4h") (v4f32 VPR128:$Rn))>;
8296
8297   def : Pat<(v8i16 (concat_vectors
8298                 (v4i16 VPR64:$src),
8299                 (v4i16 (f32_to_f16_Op (v4f32 VPR128:$Rn))))),
8300                   (!cast<Instruction>(prefix # "4s8h")
8301                     (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8302                     (v4f32 VPR128:$Rn))>;
8303
8304   def : Pat<(v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))),
8305             (!cast<Instruction>(prefix # "2d2s") (v2f64 VPR128:$Rn))>;
8306
8307   def : Pat<(v4f32 (concat_vectors
8308               (v2f32 VPR64:$src),
8309               (v2f32 (f64_to_f32_Op (v2f64 VPR128:$Rn))))),
8310                 (!cast<Instruction>(prefix # "2d4s")
8311                   (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8312                   (v2f64 VPR128:$Rn))>;
8313 }
8314
8315 defm : NeonI_2VMisc_Narrow_Pattern<"FCVTN", int_arm_neon_vcvtfp2hf, fround>;
8316
8317 multiclass NeonI_2VMisc_D_Narrow<string asmop, string prefix, bit U,
8318                                  bits<5> opcode> {
8319   def 2d2s : NeonI_2VMisc<0b0, U, 0b01, opcode,
8320                           (outs VPR64:$Rd), (ins VPR128:$Rn),
8321                           asmop # "\t$Rd.2s, $Rn.2d",
8322                           [], NoItinerary>;
8323
8324   def 2d4s : NeonI_2VMisc<0b1, U, 0b01, opcode,
8325                           (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8326                           asmop # "2\t$Rd.4s, $Rn.2d",
8327                           [], NoItinerary> {
8328     let Constraints = "$src = $Rd";
8329   }
8330
8331   def : Pat<(v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))),
8332             (!cast<Instruction>(prefix # "2d2s") VPR128:$Rn)>;
8333
8334   def : Pat<(v4f32 (concat_vectors
8335               (v2f32 VPR64:$src),
8336               (v2f32 (int_aarch64_neon_vcvtxn (v2f64 VPR128:$Rn))))),
8337             (!cast<Instruction>(prefix # "2d4s")
8338                (v4f32 (SUBREG_TO_REG (i32 0), VPR64:$src, sub_64)),
8339                VPR128:$Rn)>;
8340 }
8341
8342 defm FCVTXN : NeonI_2VMisc_D_Narrow<"fcvtxn","FCVTXN", 0b1, 0b10110>;
8343
8344 def Neon_High4Float : PatFrag<(ops node:$in),
8345                               (extract_subvector (v4f32 node:$in), (iPTR 2))>;
8346
8347 multiclass NeonI_2VMisc_HS_Extend<string asmop, bit U, bits<5> opcode> {
8348   def 4h4s : NeonI_2VMisc<0b0, U, 0b00, opcode,
8349                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8350                           asmop # "\t$Rd.4s, $Rn.4h",
8351                           [], NoItinerary>;
8352
8353   def 2s2d : NeonI_2VMisc<0b0, U, 0b01, opcode,
8354                           (outs VPR128:$Rd), (ins VPR64:$Rn),
8355                           asmop # "\t$Rd.2d, $Rn.2s",
8356                           [], NoItinerary>;
8357
8358   def 8h4s : NeonI_2VMisc<0b1, U, 0b00, opcode,
8359                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8360                           asmop # "2\t$Rd.4s, $Rn.8h",
8361                           [], NoItinerary>;
8362
8363   def 4s2d : NeonI_2VMisc<0b1, U, 0b01, opcode,
8364                           (outs VPR128:$Rd), (ins VPR128:$Rn),
8365                           asmop # "2\t$Rd.2d, $Rn.4s",
8366                           [], NoItinerary>;
8367 }
8368
8369 defm FCVTL : NeonI_2VMisc_HS_Extend<"fcvtl", 0b0, 0b10111>;
8370
8371 multiclass NeonI_2VMisc_Extend_Pattern<string prefix> {
8372   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp (v4i16 VPR64:$Rn))),
8373             (!cast<Instruction>(prefix # "4h4s") VPR64:$Rn)>;
8374
8375   def : Pat<(v4f32 (int_arm_neon_vcvthf2fp
8376               (v4i16 (Neon_High8H
8377                 (v8i16 VPR128:$Rn))))),
8378             (!cast<Instruction>(prefix # "8h4s") VPR128:$Rn)>;
8379
8380   def : Pat<(v2f64 (fextend (v2f32 VPR64:$Rn))),
8381             (!cast<Instruction>(prefix # "2s2d") VPR64:$Rn)>;
8382
8383   def : Pat<(v2f64 (fextend
8384               (v2f32 (Neon_High4Float
8385                 (v4f32 VPR128:$Rn))))),
8386             (!cast<Instruction>(prefix # "4s2d") VPR128:$Rn)>;
8387 }
8388
8389 defm : NeonI_2VMisc_Extend_Pattern<"FCVTL">;
8390
8391 multiclass NeonI_2VMisc_SD_Conv<string asmop, bit Size, bit U, bits<5> opcode,
8392                                 ValueType ResTy4s, ValueType OpTy4s,
8393                                 ValueType ResTy2d, ValueType OpTy2d,
8394                                 ValueType ResTy2s, ValueType OpTy2s,
8395                                 SDPatternOperator Neon_Op> {
8396
8397   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8398                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8399                         asmop # "\t$Rd.4s, $Rn.4s",
8400                         [(set (ResTy4s VPR128:$Rd),
8401                            (ResTy4s (Neon_Op (OpTy4s VPR128:$Rn))))],
8402                         NoItinerary>;
8403
8404   def 2d : NeonI_2VMisc<0b1, U, {Size, 0b1}, opcode,
8405                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8406                         asmop # "\t$Rd.2d, $Rn.2d",
8407                         [(set (ResTy2d VPR128:$Rd),
8408                            (ResTy2d (Neon_Op (OpTy2d VPR128:$Rn))))],
8409                         NoItinerary>;
8410
8411   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8412                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8413                         asmop # "\t$Rd.2s, $Rn.2s",
8414                         [(set (ResTy2s VPR64:$Rd),
8415                            (ResTy2s (Neon_Op (OpTy2s VPR64:$Rn))))],
8416                         NoItinerary>;
8417 }
8418
8419 multiclass NeonI_2VMisc_fp_to_int<string asmop, bit Size, bit U,
8420                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8421   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4i32, v4f32, v2i64,
8422                                 v2f64, v2i32, v2f32, Neon_Op>;
8423 }
8424
8425 defm FCVTNS : NeonI_2VMisc_fp_to_int<"fcvtns", 0b0, 0b0, 0b11010,
8426                                      int_arm_neon_vcvtns>;
8427 defm FCVTNU : NeonI_2VMisc_fp_to_int<"fcvtnu", 0b0, 0b1, 0b11010,
8428                                      int_arm_neon_vcvtnu>;
8429 defm FCVTPS : NeonI_2VMisc_fp_to_int<"fcvtps", 0b1, 0b0, 0b11010,
8430                                      int_arm_neon_vcvtps>;
8431 defm FCVTPU : NeonI_2VMisc_fp_to_int<"fcvtpu", 0b1, 0b1, 0b11010,
8432                                      int_arm_neon_vcvtpu>;
8433 defm FCVTMS : NeonI_2VMisc_fp_to_int<"fcvtms", 0b0, 0b0, 0b11011,
8434                                      int_arm_neon_vcvtms>;
8435 defm FCVTMU : NeonI_2VMisc_fp_to_int<"fcvtmu", 0b0, 0b1, 0b11011,
8436                                      int_arm_neon_vcvtmu>;
8437 defm FCVTZS : NeonI_2VMisc_fp_to_int<"fcvtzs", 0b1, 0b0, 0b11011, fp_to_sint>;
8438 defm FCVTZU : NeonI_2VMisc_fp_to_int<"fcvtzu", 0b1, 0b1, 0b11011, fp_to_uint>;
8439 defm FCVTAS : NeonI_2VMisc_fp_to_int<"fcvtas", 0b0, 0b0, 0b11100,
8440                                      int_arm_neon_vcvtas>;
8441 defm FCVTAU : NeonI_2VMisc_fp_to_int<"fcvtau", 0b0, 0b1, 0b11100,
8442                                      int_arm_neon_vcvtau>;
8443
8444 multiclass NeonI_2VMisc_int_to_fp<string asmop, bit Size, bit U,
8445                                   bits<5> opcode, SDPatternOperator Neon_Op> {
8446   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4i32, v2f64,
8447                                 v2i64, v2f32, v2i32, Neon_Op>;
8448 }
8449
8450 defm SCVTF : NeonI_2VMisc_int_to_fp<"scvtf", 0b0, 0b0, 0b11101, sint_to_fp>;
8451 defm UCVTF : NeonI_2VMisc_int_to_fp<"ucvtf", 0b0, 0b1, 0b11101, uint_to_fp>;
8452
8453 multiclass NeonI_2VMisc_fp_to_fp<string asmop, bit Size, bit U,
8454                                  bits<5> opcode, SDPatternOperator Neon_Op> {
8455   defm _ : NeonI_2VMisc_SD_Conv<asmop, Size, U, opcode, v4f32, v4f32, v2f64,
8456                                 v2f64, v2f32, v2f32, Neon_Op>;
8457 }
8458
8459 defm FRINTN : NeonI_2VMisc_fp_to_fp<"frintn", 0b0, 0b0, 0b11000,
8460                                      int_aarch64_neon_frintn>;
8461 defm FRINTA : NeonI_2VMisc_fp_to_fp<"frinta", 0b0, 0b1, 0b11000, frnd>;
8462 defm FRINTP : NeonI_2VMisc_fp_to_fp<"frintp", 0b1, 0b0, 0b11000, fceil>;
8463 defm FRINTM : NeonI_2VMisc_fp_to_fp<"frintm", 0b0, 0b0, 0b11001, ffloor>;
8464 defm FRINTX : NeonI_2VMisc_fp_to_fp<"frintx", 0b0, 0b1, 0b11001, frint>;
8465 defm FRINTZ : NeonI_2VMisc_fp_to_fp<"frintz", 0b1, 0b0, 0b11001, ftrunc>;
8466 defm FRINTI : NeonI_2VMisc_fp_to_fp<"frinti", 0b1, 0b1, 0b11001, fnearbyint>;
8467 defm FRECPE : NeonI_2VMisc_fp_to_fp<"frecpe", 0b1, 0b0, 0b11101,
8468                                     int_arm_neon_vrecpe>;
8469 defm FRSQRTE : NeonI_2VMisc_fp_to_fp<"frsqrte", 0b1, 0b1, 0b11101,
8470                                      int_arm_neon_vrsqrte>;
8471 defm FSQRT : NeonI_2VMisc_fp_to_fp<"fsqrt", 0b1, 0b1, 0b11111, fsqrt>;
8472
8473 multiclass NeonI_2VMisc_S_Conv<string asmop, bit Size, bit U,
8474                                bits<5> opcode, SDPatternOperator Neon_Op> {
8475   def 4s : NeonI_2VMisc<0b1, U, {Size, 0b0}, opcode,
8476                         (outs VPR128:$Rd), (ins VPR128:$Rn),
8477                         asmop # "\t$Rd.4s, $Rn.4s",
8478                         [(set (v4i32 VPR128:$Rd),
8479                            (v4i32 (Neon_Op (v4i32 VPR128:$Rn))))],
8480                         NoItinerary>;
8481
8482   def 2s : NeonI_2VMisc<0b0, U, {Size, 0b0}, opcode,
8483                         (outs VPR64:$Rd), (ins VPR64:$Rn),
8484                         asmop # "\t$Rd.2s, $Rn.2s",
8485                         [(set (v2i32 VPR64:$Rd),
8486                            (v2i32 (Neon_Op (v2i32 VPR64:$Rn))))],
8487                         NoItinerary>;
8488 }
8489
8490 defm URECPE : NeonI_2VMisc_S_Conv<"urecpe", 0b1, 0b0, 0b11100,
8491                                   int_arm_neon_vrecpe>;
8492 defm URSQRTE : NeonI_2VMisc_S_Conv<"ursqrte", 0b1, 0b1, 0b11100,
8493                                    int_arm_neon_vrsqrte>;
8494
8495 // Crypto Class
8496 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
8497                          string asmop, SDPatternOperator opnode>
8498   : NeonI_Crypto_AES<size, opcode,
8499                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8500                      asmop # "\t$Rd.16b, $Rn.16b",
8501                      [(set (v16i8 VPR128:$Rd),
8502                         (v16i8 (opnode (v16i8 VPR128:$src),
8503                                        (v16i8 VPR128:$Rn))))],
8504                      NoItinerary>{
8505   let Constraints = "$src = $Rd";
8506   let Predicates = [HasNEON, HasCrypto];
8507 }
8508
8509 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
8510 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
8511
8512 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
8513                       string asmop, SDPatternOperator opnode>
8514   : NeonI_Crypto_AES<size, opcode,
8515                      (outs VPR128:$Rd), (ins VPR128:$Rn),
8516                      asmop # "\t$Rd.16b, $Rn.16b",
8517                      [(set (v16i8 VPR128:$Rd),
8518                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
8519                      NoItinerary>;
8520
8521 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
8522 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
8523
8524 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
8525                          string asmop, SDPatternOperator opnode>
8526   : NeonI_Crypto_SHA<size, opcode,
8527                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
8528                      asmop # "\t$Rd.4s, $Rn.4s",
8529                      [(set (v4i32 VPR128:$Rd),
8530                         (v4i32 (opnode (v4i32 VPR128:$src),
8531                                        (v4i32 VPR128:$Rn))))],
8532                      NoItinerary> {
8533   let Constraints = "$src = $Rd";
8534   let Predicates = [HasNEON, HasCrypto];
8535 }
8536
8537 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
8538                                  int_arm_neon_sha1su1>;
8539 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
8540                                    int_arm_neon_sha256su0>;
8541
8542 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
8543                          string asmop, SDPatternOperator opnode>
8544   : NeonI_Crypto_SHA<size, opcode,
8545                      (outs FPR32:$Rd), (ins FPR32:$Rn),
8546                      asmop # "\t$Rd, $Rn",
8547                      [(set (v1i32 FPR32:$Rd),
8548                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
8549                      NoItinerary> {
8550   let Predicates = [HasNEON, HasCrypto];
8551 }
8552
8553 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
8554
8555 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
8556                            SDPatternOperator opnode>
8557   : NeonI_Crypto_3VSHA<size, opcode,
8558                        (outs VPR128:$Rd),
8559                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
8560                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
8561                        [(set (v4i32 VPR128:$Rd),
8562                           (v4i32 (opnode (v4i32 VPR128:$src),
8563                                          (v4i32 VPR128:$Rn),
8564                                          (v4i32 VPR128:$Rm))))],
8565                        NoItinerary> {
8566   let Constraints = "$src = $Rd";
8567   let Predicates = [HasNEON, HasCrypto];
8568 }
8569
8570 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
8571                                    int_arm_neon_sha1su0>;
8572 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
8573                                      int_arm_neon_sha256su1>;
8574
8575 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
8576                            SDPatternOperator opnode>
8577   : NeonI_Crypto_3VSHA<size, opcode,
8578                        (outs FPR128:$Rd),
8579                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
8580                        asmop # "\t$Rd, $Rn, $Rm.4s",
8581                        [(set (v4i32 FPR128:$Rd),
8582                           (v4i32 (opnode (v4i32 FPR128:$src),
8583                                          (v4i32 FPR128:$Rn),
8584                                          (v4i32 VPR128:$Rm))))],
8585                        NoItinerary> {
8586   let Constraints = "$src = $Rd";
8587   let Predicates = [HasNEON, HasCrypto];
8588 }
8589
8590 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
8591                                    int_arm_neon_sha256h>;
8592 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
8593                                     int_arm_neon_sha256h2>;
8594
8595 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
8596                            SDPatternOperator opnode>
8597   : NeonI_Crypto_3VSHA<size, opcode,
8598                        (outs FPR128:$Rd),
8599                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
8600                        asmop # "\t$Rd, $Rn, $Rm.4s",
8601                        [(set (v4i32 FPR128:$Rd),
8602                           (v4i32 (opnode (v4i32 FPR128:$src),
8603                                          (v1i32 FPR32:$Rn),
8604                                          (v4i32 VPR128:$Rm))))],
8605                        NoItinerary> {
8606   let Constraints = "$src = $Rd";
8607   let Predicates = [HasNEON, HasCrypto];
8608 }
8609
8610 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
8611 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
8612 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
8613
8614 //
8615 // Patterns for handling half-precision values
8616 //
8617
8618 // Convert f16 value coming in as i16 value to f32
8619 def : Pat<(f32 (f16_to_f32 (i32 (and (i32 GPR32:$Rn), 65535)))),
8620           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8621 def : Pat<(f32 (f16_to_f32 (i32 (assertzext GPR32:$Rn)))),
8622           (FCVTsh (EXTRACT_SUBREG (FMOVsw GPR32:$Rn), sub_16))>;
8623
8624 def : Pat<(f32 (f16_to_f32 (i32 (assertzext (i32 (
8625             f32_to_f16 (f32 FPR32:$Rn))))))),
8626           (f32 FPR32:$Rn)>;
8627
8628 // Patterns for vector extract of half-precision FP value in i16 storage type
8629 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8630             (v4i16 VPR64:$Rn), neon_uimm2_bare:$Imm)), 65535)))),
8631           (FCVTsh (f16 (DUPhv_H
8632             (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8633             neon_uimm2_bare:$Imm)))>;
8634
8635 def : Pat<(f32 (f16_to_f32 ( i32 (and (i32 (vector_extract
8636             (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)), 65535)))),
8637           (FCVTsh (f16 (DUPhv_H (v8i16 VPR128:$Rn), neon_uimm3_bare:$Imm)))>;
8638
8639 // Patterns for vector insert of half-precision FP value 0 in i16 storage type
8640 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8641             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8642             (neon_uimm3_bare:$Imm))),
8643           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8644             (v8i16 (SUBREG_TO_REG (i64 0),
8645               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8646               sub_16)),
8647             neon_uimm3_bare:$Imm, 0))>;
8648
8649 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8650             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 0))))))),
8651             (neon_uimm2_bare:$Imm))),
8652           (v4i16 (EXTRACT_SUBREG
8653             (v8i16 (INSELh
8654               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8655               (v8i16 (SUBREG_TO_REG (i64 0),
8656                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 WZR))), sub_16)),
8657                 sub_16)),
8658               neon_uimm2_bare:$Imm, 0)),
8659             sub_64))>;
8660
8661 // Patterns for vector insert of half-precision FP value in i16 storage type
8662 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8663             (i32 (assertsext (i32 (fp_to_sint
8664               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8665             (neon_uimm3_bare:$Imm))),
8666           (v8i16 (INSELh (v8i16 VPR128:$Rn),
8667             (v8i16 (SUBREG_TO_REG (i64 0),
8668               (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8669               sub_16)),
8670             neon_uimm3_bare:$Imm, 0))>;
8671
8672 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8673             (i32 (assertsext (i32 (fp_to_sint
8674               (f32 (f16_to_f32 (i32 (and (i32 GPR32:$src), 65535)))))))),
8675             (neon_uimm2_bare:$Imm))),
8676           (v4i16 (EXTRACT_SUBREG
8677             (v8i16 (INSELh
8678               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8679               (v8i16 (SUBREG_TO_REG (i64 0),
8680                 (f16 (EXTRACT_SUBREG (f32 (FMOVsw (i32 GPR32:$src))), sub_16)),
8681                 sub_16)),
8682               neon_uimm2_bare:$Imm, 0)),
8683             sub_64))>;
8684
8685 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8686             (i32 (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8687               (neon_uimm3_bare:$Imm1))),
8688           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8689             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8690
8691 // Patterns for vector copy of half-precision FP value in i16 storage type
8692 def : Pat<(v8i16 (vector_insert (v8i16 VPR128:$Rn),
8693             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8694               (vector_extract (v8i16 VPR128:$src), neon_uimm3_bare:$Imm2)),
8695               65535)))))))),
8696             (neon_uimm3_bare:$Imm1))),
8697           (v8i16 (INSELh (v8i16 VPR128:$Rn), (v8i16 VPR128:$src),
8698             neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2))>;
8699
8700 def : Pat<(v4i16 (vector_insert (v4i16 VPR64:$Rn),
8701             (i32 (assertsext (i32 (fp_to_sint(f32 (f16_to_f32 (i32 (and (i32
8702               (vector_extract (v4i16 VPR64:$src), neon_uimm3_bare:$Imm2)),
8703               65535)))))))),
8704             (neon_uimm3_bare:$Imm1))),
8705           (v4i16 (EXTRACT_SUBREG
8706             (v8i16 (INSELh
8707               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
8708               (v8i16 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
8709               neon_uimm3_bare:$Imm1, neon_uimm3_bare:$Imm2)),
8710             sub_64))>;
8711
8712