lib/Target/AArch64/AArch64InstrNEON.td

   1 //===-- AArch64InstrNEON.td - NEON support for AArch64 -----*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the AArch64 NEON instruction set.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // NEON-specific DAG Nodes.
  16 //===----------------------------------------------------------------------===//
  17 def Neon_bsl       : SDNode<"AArch64ISD::NEON_BSL", SDTypeProfile<1, 3,
  18                       [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
  19                       SDTCisSameAs<0, 3>]>>;
  20
  21 // (outs Result), (ins Imm, OpCmode)
  22 def SDT_Neon_movi : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
  23
  24 def Neon_movi     : SDNode<"AArch64ISD::NEON_MOVIMM", SDT_Neon_movi>;
  25
  26 def Neon_mvni     : SDNode<"AArch64ISD::NEON_MVNIMM", SDT_Neon_movi>;
  27
  28 // (outs Result), (ins Imm)
  29 def Neon_fmovi : SDNode<"AArch64ISD::NEON_FMOVIMM", SDTypeProfile<1, 1,
  30                         [SDTCisVec<0>, SDTCisVT<1, i32>]>>;
  31
  32 // (outs Result), (ins LHS, RHS, CondCode)
  33 def Neon_cmp : SDNode<"AArch64ISD::NEON_CMP", SDTypeProfile<1, 3,
  34                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  35
  36 // (outs Result), (ins LHS, 0/0.0 constant, CondCode)
  37 def Neon_cmpz : SDNode<"AArch64ISD::NEON_CMPZ", SDTypeProfile<1, 3,
  38                  [SDTCisVec<0>,  SDTCisVec<1>]>>;
  39
  40 // (outs Result), (ins LHS, RHS)
  41 def Neon_tst : SDNode<"AArch64ISD::NEON_TST", SDTypeProfile<1, 2,
  42                  [SDTCisVec<0>,  SDTCisSameAs<1, 2>]>>;
  43
  44 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
  45                                      SDTCisVT<2, i32>]>;
  46 def Neon_sqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLs", SDTARMVSH>;
  47 def Neon_uqrshlImm   : SDNode<"AArch64ISD::NEON_QSHLu", SDTARMVSH>;
  48
  49 def Neon_vdup : SDNode<"AArch64ISD::NEON_VDUP", SDTypeProfile<1, 1,
  50                        [SDTCisVec<0>]>>;
  51 def Neon_vduplane : SDNode<"AArch64ISD::NEON_VDUPLANE", SDTypeProfile<1, 2,
  52                            [SDTCisVec<0>, SDTCisVec<1>, SDTCisVT<2, i64>]>>;
  53 def Neon_vextract : SDNode<"AArch64ISD::NEON_VEXTRACT", SDTypeProfile<1, 3,
  54                            [SDTCisVec<0>,  SDTCisSameAs<0, 1>,
  55                            SDTCisSameAs<0, 2>, SDTCisVT<3, i64>]>>;
  56
  57 //===----------------------------------------------------------------------===//
  58 // Multiclasses
  59 //===----------------------------------------------------------------------===//
  60
  61 multiclass NeonI_3VSame_B_sizes<bit u, bits<2> size,  bits<5> opcode,
  62                                 string asmop, SDPatternOperator opnode8B,
  63                                 SDPatternOperator opnode16B,
  64                                 bit Commutable = 0> {
  65   let isCommutable = Commutable in {
  66     def _8B :  NeonI_3VSame<0b0, u, size, opcode,
  67                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  68                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
  69                [(set (v8i8 VPR64:$Rd),
  70                   (v8i8 (opnode8B (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
  71                NoItinerary>;
  72
  73     def _16B : NeonI_3VSame<0b1, u, size, opcode,
  74                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  75                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
  76                [(set (v16i8 VPR128:$Rd),
  77                   (v16i8 (opnode16B (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
  78                NoItinerary>;
  79   }
  80
  81 }
  82
  83 multiclass NeonI_3VSame_HS_sizes<bit u, bits<5> opcode,
  84                                   string asmop, SDPatternOperator opnode,
  85                                   bit Commutable = 0> {
  86   let isCommutable = Commutable in {
  87     def _4H : NeonI_3VSame<0b0, u, 0b01, opcode,
  88               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
  89               asmop # "\t$Rd.4h, $Rn.4h, $Rm.4h",
  90               [(set (v4i16 VPR64:$Rd),
  91                  (v4i16 (opnode (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))))],
  92               NoItinerary>;
  93
  94     def _8H : NeonI_3VSame<0b1, u, 0b01, opcode,
  95               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
  96               asmop # "\t$Rd.8h, $Rn.8h, $Rm.8h",
  97               [(set (v8i16 VPR128:$Rd),
  98                  (v8i16 (opnode (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))))],
  99               NoItinerary>;
 100
 101     def _2S : NeonI_3VSame<0b0, u, 0b10, opcode,
 102               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 103               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 104               [(set (v2i32 VPR64:$Rd),
 105                  (v2i32 (opnode (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))))],
 106               NoItinerary>;
 107
 108     def _4S : NeonI_3VSame<0b1, u, 0b10, opcode,
 109               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 110               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 111               [(set (v4i32 VPR128:$Rd),
 112                  (v4i32 (opnode (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))))],
 113               NoItinerary>;
 114   }
 115 }
 116 multiclass NeonI_3VSame_BHS_sizes<bit u, bits<5> opcode,
 117                                   string asmop, SDPatternOperator opnode,
 118                                   bit Commutable = 0>
 119    : NeonI_3VSame_HS_sizes<u, opcode,  asmop, opnode, Commutable> {
 120   let isCommutable = Commutable in {
 121     def _8B :  NeonI_3VSame<0b0, u, 0b00, opcode,
 122                (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 123                asmop # "\t$Rd.8b, $Rn.8b, $Rm.8b",
 124                [(set (v8i8 VPR64:$Rd),
 125                   (v8i8 (opnode (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))))],
 126                NoItinerary>;
 127
 128     def _16B : NeonI_3VSame<0b1, u, 0b00, opcode,
 129                (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 130                asmop # "\t$Rd.16b, $Rn.16b, $Rm.16b",
 131                [(set (v16i8 VPR128:$Rd),
 132                   (v16i8 (opnode (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))))],
 133                NoItinerary>;
 134   }
 135 }
 136
 137 multiclass NeonI_3VSame_BHSD_sizes<bit u, bits<5> opcode,
 138                                    string asmop, SDPatternOperator opnode,
 139                                    bit Commutable = 0>
 140    : NeonI_3VSame_BHS_sizes<u, opcode,  asmop, opnode, Commutable> {
 141   let isCommutable = Commutable in {
 142     def _2D : NeonI_3VSame<0b1, u, 0b11, opcode,
 143               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 144               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 145               [(set (v2i64 VPR128:$Rd),
 146                  (v2i64 (opnode (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))))],
 147               NoItinerary>;
 148   }
 149 }
 150
 151 // Multiclass NeonI_3VSame_SD_sizes: Operand types are floating point types,
 152 // but Result types can be integer or floating point types.
 153 multiclass NeonI_3VSame_SD_sizes<bit u, bit size, bits<5> opcode,
 154                                  string asmop, SDPatternOperator opnode2S,
 155                                  SDPatternOperator opnode4S,
 156                                  SDPatternOperator opnode2D,
 157                                  ValueType ResTy2S, ValueType ResTy4S,
 158                                  ValueType ResTy2D, bit Commutable = 0> {
 159   let isCommutable = Commutable in {
 160     def _2S : NeonI_3VSame<0b0, u, {size, 0b0}, opcode,
 161               (outs VPR64:$Rd), (ins VPR64:$Rn, VPR64:$Rm),
 162               asmop # "\t$Rd.2s, $Rn.2s, $Rm.2s",
 163               [(set (ResTy2S VPR64:$Rd),
 164                  (ResTy2S (opnode2S (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))))],
 165               NoItinerary>;
 166
 167     def _4S : NeonI_3VSame<0b1, u, {size, 0b0}, opcode,
 168               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 169               asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
 170               [(set (ResTy4S VPR128:$Rd),
 171                  (ResTy4S (opnode4S (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))))],
 172               NoItinerary>;
 173
 174     def _2D : NeonI_3VSame<0b1, u, {size, 0b1}, opcode,
 175               (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
 176               asmop # "\t$Rd.2d, $Rn.2d, $Rm.2d",
 177               [(set (ResTy2D VPR128:$Rd),
 178                  (ResTy2D (opnode2D (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))))],
 179                NoItinerary>;
 180   }
 181 }
 182
 183 //===----------------------------------------------------------------------===//
 184 // Instruction Definitions
 185 //===----------------------------------------------------------------------===//
 186
 187 // Vector Arithmetic Instructions
 188
 189 // Vector Add (Integer and Floating-Point)
 190
 191 defm ADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b10000, "add", add, 1>;
 192 defm FADDvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11010, "fadd", fadd, fadd, fadd,
 193                                      v2f32, v4f32, v2f64, 1>;
 194
 195 // Vector Sub (Integer and Floating-Point)
 196
 197 defm SUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b10000, "sub", sub, 0>;
 198 defm FSUBvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11010, "fsub", fsub, fsub, fsub,
 199                                      v2f32, v4f32, v2f64, 0>;
 200
 201 // Vector Multiply (Integer and Floating-Point)
 202
 203 defm MULvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b10011, "mul", mul, 1>;
 204 defm FMULvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11011, "fmul", fmul, fmul, fmul,
 205                                      v2f32, v4f32, v2f64, 1>;
 206
 207 // Vector Multiply (Polynomial)
 208
 209 defm PMULvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b10011, "pmul",
 210                                     int_arm_neon_vmulp, int_arm_neon_vmulp, 1>;
 211
 212 // Vector Multiply-accumulate and Multiply-subtract (Integer)
 213
 214 // class NeonI_3VSame_Constraint_impl: NeonI_3VSame with no data type and
 215 // two operands constraints.
 216 class NeonI_3VSame_Constraint_impl<string asmop, string asmlane,
 217   RegisterOperand VPRC, ValueType OpTy, bit q, bit u, bits<2> size,
 218   bits<5> opcode, SDPatternOperator opnode>
 219   : NeonI_3VSame<q, u, size, opcode,
 220     (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, VPRC:$Rm),
 221     asmop # "\t$Rd" # asmlane # ", $Rn" # asmlane # ", $Rm" # asmlane,
 222     [(set (OpTy VPRC:$Rd),
 223        (OpTy (opnode (OpTy VPRC:$src), (OpTy VPRC:$Rn), (OpTy VPRC:$Rm))))],
 224     NoItinerary> {
 225   let Constraints = "$src = $Rd";
 226 }
 227
 228 def Neon_mla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 229                        (add node:$Ra, (mul node:$Rn, node:$Rm))>;
 230
 231 def Neon_mls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 232                        (sub node:$Ra, (mul node:$Rn, node:$Rm))>;
 233
 234
 235 def MLAvvv_8B:  NeonI_3VSame_Constraint_impl<"mla", ".8b",  VPR64,  v8i8,
 236                                              0b0, 0b0, 0b00, 0b10010, Neon_mla>;
 237 def MLAvvv_16B: NeonI_3VSame_Constraint_impl<"mla", ".16b", VPR128, v16i8,
 238                                              0b1, 0b0, 0b00, 0b10010, Neon_mla>;
 239 def MLAvvv_4H:  NeonI_3VSame_Constraint_impl<"mla", ".4h",  VPR64,  v4i16,
 240                                              0b0, 0b0, 0b01, 0b10010, Neon_mla>;
 241 def MLAvvv_8H:  NeonI_3VSame_Constraint_impl<"mla", ".8h",  VPR128, v8i16,
 242                                              0b1, 0b0, 0b01, 0b10010, Neon_mla>;
 243 def MLAvvv_2S:  NeonI_3VSame_Constraint_impl<"mla", ".2s",  VPR64,  v2i32,
 244                                              0b0, 0b0, 0b10, 0b10010, Neon_mla>;
 245 def MLAvvv_4S:  NeonI_3VSame_Constraint_impl<"mla", ".4s",  VPR128, v4i32,
 246                                              0b1, 0b0, 0b10, 0b10010, Neon_mla>;
 247
 248 def MLSvvv_8B:  NeonI_3VSame_Constraint_impl<"mls", ".8b",  VPR64,  v8i8,
 249                                              0b0, 0b1, 0b00, 0b10010, Neon_mls>;
 250 def MLSvvv_16B: NeonI_3VSame_Constraint_impl<"mls", ".16b", VPR128, v16i8,
 251                                              0b1, 0b1, 0b00, 0b10010, Neon_mls>;
 252 def MLSvvv_4H:  NeonI_3VSame_Constraint_impl<"mls", ".4h",  VPR64,  v4i16,
 253                                              0b0, 0b1, 0b01, 0b10010, Neon_mls>;
 254 def MLSvvv_8H:  NeonI_3VSame_Constraint_impl<"mls", ".8h",  VPR128, v8i16,
 255                                              0b1, 0b1, 0b01, 0b10010, Neon_mls>;
 256 def MLSvvv_2S:  NeonI_3VSame_Constraint_impl<"mls", ".2s",  VPR64,  v2i32,
 257                                              0b0, 0b1, 0b10, 0b10010, Neon_mls>;
 258 def MLSvvv_4S:  NeonI_3VSame_Constraint_impl<"mls", ".4s",  VPR128, v4i32,
 259                                              0b1, 0b1, 0b10, 0b10010, Neon_mls>;
 260
 261 // Vector Multiply-accumulate and Multiply-subtract (Floating Point)
 262
 263 def Neon_fmla : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 264                         (fadd node:$Ra, (fmul node:$Rn, node:$Rm))>;
 265
 266 def Neon_fmls : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 267                         (fsub node:$Ra, (fmul node:$Rn, node:$Rm))>;
 268
 269 let Predicates = [HasNEON, UseFusedMAC] in {
 270 def FMLAvvv_2S: NeonI_3VSame_Constraint_impl<"fmla", ".2s",  VPR64,  v2f32,
 271                                              0b0, 0b0, 0b00, 0b11001, Neon_fmla>;
 272 def FMLAvvv_4S: NeonI_3VSame_Constraint_impl<"fmla", ".4s",  VPR128, v4f32,
 273                                              0b1, 0b0, 0b00, 0b11001, Neon_fmla>;
 274 def FMLAvvv_2D: NeonI_3VSame_Constraint_impl<"fmla", ".2d",  VPR128, v2f64,
 275                                              0b1, 0b0, 0b01, 0b11001, Neon_fmla>;
 276
 277 def FMLSvvv_2S: NeonI_3VSame_Constraint_impl<"fmls", ".2s",  VPR64,  v2f32,
 278                                               0b0, 0b0, 0b10, 0b11001, Neon_fmls>;
 279 def FMLSvvv_4S: NeonI_3VSame_Constraint_impl<"fmls", ".4s",  VPR128, v4f32,
 280                                              0b1, 0b0, 0b10, 0b11001, Neon_fmls>;
 281 def FMLSvvv_2D: NeonI_3VSame_Constraint_impl<"fmls", ".2d",  VPR128, v2f64,
 282                                              0b1, 0b0, 0b11, 0b11001, Neon_fmls>;
 283 }
 284
 285 // We're also allowed to match the fma instruction regardless of compile
 286 // options.
 287 def : Pat<(v2f32 (fma VPR64:$Rn, VPR64:$Rm, VPR64:$Ra)),
 288           (FMLAvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 289 def : Pat<(v4f32 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 290           (FMLAvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 291 def : Pat<(v2f64 (fma VPR128:$Rn, VPR128:$Rm, VPR128:$Ra)),
 292           (FMLAvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 293
 294 def : Pat<(v2f32 (fma (fneg VPR64:$Rn), VPR64:$Rm, VPR64:$Ra)),
 295           (FMLSvvv_2S VPR64:$Ra, VPR64:$Rn, VPR64:$Rm)>;
 296 def : Pat<(v4f32 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 297           (FMLSvvv_4S VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 298 def : Pat<(v2f64 (fma (fneg VPR128:$Rn), VPR128:$Rm, VPR128:$Ra)),
 299           (FMLSvvv_2D VPR128:$Ra, VPR128:$Rn, VPR128:$Rm)>;
 300
 301 // Vector Divide (Floating-Point)
 302
 303 defm FDIVvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11111, "fdiv", fdiv, fdiv, fdiv,
 304                                      v2f32, v4f32, v2f64, 0>;
 305
 306 // Vector Bitwise Operations
 307
 308 // Vector Bitwise AND
 309
 310 defm ANDvvv : NeonI_3VSame_B_sizes<0b0, 0b00, 0b00011, "and", and, and, 1>;
 311
 312 // Vector Bitwise Exclusive OR
 313
 314 defm EORvvv : NeonI_3VSame_B_sizes<0b1, 0b00, 0b00011, "eor", xor, xor, 1>;
 315
 316 // Vector Bitwise OR
 317
 318 defm ORRvvv : NeonI_3VSame_B_sizes<0b0, 0b10, 0b00011, "orr", or, or, 1>;
 319
 320 // ORR disassembled as MOV if Vn==Vm
 321
 322 // Vector Move - register
 323 // Alias for ORR if Vn=Vm.
 324 // FIXME: This is actually the preferred syntax but TableGen can't deal with
 325 // custom printing of aliases.
 326 def : NeonInstAlias<"mov $Rd.8b, $Rn.8b",
 327                     (ORRvvv_8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rn), 0>;
 328 def : NeonInstAlias<"mov $Rd.16b, $Rn.16b",
 329                     (ORRvvv_16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rn), 0>;
 330
 331 def Neon_immAllOnes: PatLeaf<(Neon_movi (i32 timm), (i32 imm)), [{
 332   ConstantSDNode *ImmConstVal = cast<ConstantSDNode>(N->getOperand(0));
 333   ConstantSDNode *OpCmodeConstVal = cast<ConstantSDNode>(N->getOperand(1));
 334   unsigned EltBits;
 335   uint64_t EltVal = A64Imms::decodeNeonModImm(ImmConstVal->getZExtValue(),
 336     OpCmodeConstVal->getZExtValue(), EltBits);
 337   return (EltBits == 8 && EltVal == 0xff);
 338 }]>;
 339
 340 def Neon_immAllZeros: PatLeaf<(Neon_movi (i32 timm), (i32 imm)), [{
 341   ConstantSDNode *ImmConstVal = cast<ConstantSDNode>(N->getOperand(0));
 342   ConstantSDNode *OpCmodeConstVal = cast<ConstantSDNode>(N->getOperand(1));
 343   unsigned EltBits;
 344   uint64_t EltVal = A64Imms::decodeNeonModImm(ImmConstVal->getZExtValue(),
 345     OpCmodeConstVal->getZExtValue(), EltBits);
 346   return (EltBits == 8 && EltVal == 0x0);
 347 }]>;
 348
 349
 350 def Neon_not8B  : PatFrag<(ops node:$in),
 351                           (xor node:$in, (bitconvert (v8i8 Neon_immAllOnes)))>;
 352 def Neon_not16B : PatFrag<(ops node:$in),
 353                           (xor node:$in, (bitconvert (v16i8 Neon_immAllOnes)))>;
 354
 355 def Neon_orn8B : PatFrag<(ops node:$Rn, node:$Rm),
 356                          (or node:$Rn, (Neon_not8B node:$Rm))>;
 357
 358 def Neon_orn16B : PatFrag<(ops node:$Rn, node:$Rm),
 359                           (or node:$Rn, (Neon_not16B node:$Rm))>;
 360
 361 def Neon_bic8B : PatFrag<(ops node:$Rn, node:$Rm),
 362                          (and node:$Rn, (Neon_not8B node:$Rm))>;
 363
 364 def Neon_bic16B : PatFrag<(ops node:$Rn, node:$Rm),
 365                           (and node:$Rn, (Neon_not16B node:$Rm))>;
 366
 367
 368 // Vector Bitwise OR NOT - register
 369
 370 defm ORNvvv : NeonI_3VSame_B_sizes<0b0, 0b11, 0b00011, "orn",
 371                                    Neon_orn8B, Neon_orn16B, 0>;
 372
 373 // Vector Bitwise Bit Clear (AND NOT) - register
 374
 375 defm BICvvv : NeonI_3VSame_B_sizes<0b0, 0b01, 0b00011, "bic",
 376                                    Neon_bic8B, Neon_bic16B, 0>;
 377
 378 multiclass Neon_bitwise2V_patterns<SDPatternOperator opnode8B,
 379                                    SDPatternOperator opnode16B,
 380                                    Instruction INST8B,
 381                                    Instruction INST16B> {
 382   def : Pat<(v2i32 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 383             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 384   def : Pat<(v4i16 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 385             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 386   def : Pat<(v1i64 (opnode8B VPR64:$Rn, VPR64:$Rm)),
 387             (INST8B VPR64:$Rn, VPR64:$Rm)>;
 388   def : Pat<(v4i32 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 389             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 390   def : Pat<(v8i16 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 391             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 392   def : Pat<(v2i64 (opnode16B VPR128:$Rn, VPR128:$Rm)),
 393             (INST16B VPR128:$Rn, VPR128:$Rm)>;
 394 }
 395
 396 // Additional patterns for bitwise instructions AND, EOR, ORR, BIC, ORN
 397 defm : Neon_bitwise2V_patterns<and, and, ANDvvv_8B, ANDvvv_16B>;
 398 defm : Neon_bitwise2V_patterns<or,  or,  ORRvvv_8B, ORRvvv_16B>;
 399 defm : Neon_bitwise2V_patterns<xor, xor, EORvvv_8B, EORvvv_16B>;
 400 defm : Neon_bitwise2V_patterns<Neon_bic8B, Neon_bic16B, BICvvv_8B, BICvvv_16B>;
 401 defm : Neon_bitwise2V_patterns<Neon_orn8B, Neon_orn16B, ORNvvv_8B, ORNvvv_16B>;
 402
 403 //   Vector Bitwise Select
 404 def BSLvvv_8B  : NeonI_3VSame_Constraint_impl<"bsl", ".8b",  VPR64, v8i8,
 405                                               0b0, 0b1, 0b01, 0b00011, Neon_bsl>;
 406
 407 def BSLvvv_16B : NeonI_3VSame_Constraint_impl<"bsl", ".16b", VPR128, v16i8,
 408                                               0b1, 0b1, 0b01, 0b00011, Neon_bsl>;
 409
 410 multiclass Neon_bitwise3V_patterns<SDPatternOperator opnode,
 411                                    Instruction INST8B,
 412                                    Instruction INST16B> {
 413   // Disassociate type from instruction definition
 414   def : Pat<(v2i32 (opnode VPR64:$src,VPR64:$Rn, VPR64:$Rm)),
 415             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 416   def : Pat<(v4i16 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 417             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 418   def : Pat<(v1i64 (opnode VPR64:$src, VPR64:$Rn, VPR64:$Rm)),
 419             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 420   def : Pat<(v4i32 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 421             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 422   def : Pat<(v8i16 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 423             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 424   def : Pat<(v2i64 (opnode VPR128:$src, VPR128:$Rn, VPR128:$Rm)),
 425             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 426
 427   // Allow to match BSL instruction pattern with non-constant operand
 428   def : Pat<(v8i8 (or (and VPR64:$Rn, VPR64:$Rd),
 429                     (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 430           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 431   def : Pat<(v4i16 (or (and VPR64:$Rn, VPR64:$Rd),
 432                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 433           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 434   def : Pat<(v2i32 (or (and VPR64:$Rn, VPR64:$Rd),
 435                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 436           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 437   def : Pat<(v1i64 (or (and VPR64:$Rn, VPR64:$Rd),
 438                      (and VPR64:$Rm, (Neon_not8B VPR64:$Rd)))),
 439           (INST8B VPR64:$Rd, VPR64:$Rn, VPR64:$Rm)>;
 440   def : Pat<(v16i8 (or (and VPR128:$Rn, VPR128:$Rd),
 441                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 442           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 443   def : Pat<(v8i16 (or (and VPR128:$Rn, VPR128:$Rd),
 444                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 445           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 446   def : Pat<(v4i32 (or (and VPR128:$Rn, VPR128:$Rd),
 447                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 448           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 449   def : Pat<(v2i64 (or (and VPR128:$Rn, VPR128:$Rd),
 450                      (and VPR128:$Rm, (Neon_not16B VPR128:$Rd)))),
 451           (INST16B VPR128:$Rd, VPR128:$Rn, VPR128:$Rm)>;
 452
 453   // Allow to match llvm.arm.* intrinsics.
 454   def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 VPR64:$src),
 455                     (v8i8 VPR64:$Rn), (v8i8 VPR64:$Rm))),
 456             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 457   def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 VPR64:$src),
 458                     (v4i16 VPR64:$Rn), (v4i16 VPR64:$Rm))),
 459             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 460   def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 VPR64:$src),
 461                     (v2i32 VPR64:$Rn), (v2i32 VPR64:$Rm))),
 462             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 463   def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 VPR64:$src),
 464                     (v1i64 VPR64:$Rn), (v1i64 VPR64:$Rm))),
 465             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 466   def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 VPR64:$src),
 467                     (v2f32 VPR64:$Rn), (v2f32 VPR64:$Rm))),
 468             (INST8B VPR64:$src, VPR64:$Rn, VPR64:$Rm)>;
 469   def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 VPR128:$src),
 470                     (v16i8 VPR128:$Rn), (v16i8 VPR128:$Rm))),
 471             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 472   def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 VPR128:$src),
 473                     (v8i16 VPR128:$Rn), (v8i16 VPR128:$Rm))),
 474             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 475   def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 VPR128:$src),
 476                     (v4i32 VPR128:$Rn), (v4i32 VPR128:$Rm))),
 477             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 478   def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 VPR128:$src),
 479                     (v2i64 VPR128:$Rn), (v2i64 VPR128:$Rm))),
 480             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 481   def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 VPR128:$src),
 482                     (v4f32 VPR128:$Rn), (v4f32 VPR128:$Rm))),
 483             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 484   def : Pat<(v2f64 (int_arm_neon_vbsl (v2f64 VPR128:$src),
 485                     (v2f64 VPR128:$Rn), (v2f64 VPR128:$Rm))),
 486             (INST16B VPR128:$src, VPR128:$Rn, VPR128:$Rm)>;
 487 }
 488
 489 // Additional patterns for bitwise instruction BSL
 490 defm: Neon_bitwise3V_patterns<Neon_bsl, BSLvvv_8B, BSLvvv_16B>;
 491
 492 def Neon_NoBSLop : PatFrag<(ops node:$src, node:$Rn, node:$Rm),
 493                            (Neon_bsl node:$src, node:$Rn, node:$Rm),
 494                            [{ (void)N; return false; }]>;
 495
 496 // Vector Bitwise Insert if True
 497
 498 def BITvvv_8B  : NeonI_3VSame_Constraint_impl<"bit", ".8b", VPR64,   v8i8,
 499                    0b0, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 500 def BITvvv_16B : NeonI_3VSame_Constraint_impl<"bit", ".16b", VPR128, v16i8,
 501                    0b1, 0b1, 0b10, 0b00011, Neon_NoBSLop>;
 502
 503 // Vector Bitwise Insert if False
 504
 505 def BIFvvv_8B  : NeonI_3VSame_Constraint_impl<"bif", ".8b", VPR64,  v8i8,
 506                                 0b0, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 507 def BIFvvv_16B : NeonI_3VSame_Constraint_impl<"bif", ".16b", VPR128, v16i8,
 508                                 0b1, 0b1, 0b11, 0b00011, Neon_NoBSLop>;
 509
 510 // Vector Absolute Difference and Accumulate (Signed, Unsigned)
 511
 512 def Neon_uaba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 513                        (add node:$Ra, (int_arm_neon_vabdu node:$Rn, node:$Rm))>;
 514 def Neon_saba : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
 515                        (add node:$Ra, (int_arm_neon_vabds node:$Rn, node:$Rm))>;
 516
 517 // Vector Absolute Difference and Accumulate (Unsigned)
 518 def UABAvvv_8B :  NeonI_3VSame_Constraint_impl<"uaba", ".8b",  VPR64,  v8i8,
 519                     0b0, 0b1, 0b00, 0b01111, Neon_uaba>;
 520 def UABAvvv_16B : NeonI_3VSame_Constraint_impl<"uaba", ".16b", VPR128, v16i8,
 521                     0b1, 0b1, 0b00, 0b01111, Neon_uaba>;
 522 def UABAvvv_4H :  NeonI_3VSame_Constraint_impl<"uaba", ".4h",  VPR64,  v4i16,
 523                     0b0, 0b1, 0b01, 0b01111, Neon_uaba>;
 524 def UABAvvv_8H :  NeonI_3VSame_Constraint_impl<"uaba", ".8h",  VPR128, v8i16,
 525                     0b1, 0b1, 0b01, 0b01111, Neon_uaba>;
 526 def UABAvvv_2S :  NeonI_3VSame_Constraint_impl<"uaba", ".2s",  VPR64,  v2i32,
 527                     0b0, 0b1, 0b10, 0b01111, Neon_uaba>;
 528 def UABAvvv_4S :  NeonI_3VSame_Constraint_impl<"uaba", ".4s",  VPR128, v4i32,
 529                     0b1, 0b1, 0b10, 0b01111, Neon_uaba>;
 530
 531 // Vector Absolute Difference and Accumulate (Signed)
 532 def SABAvvv_8B :  NeonI_3VSame_Constraint_impl<"saba", ".8b",  VPR64,  v8i8,
 533                     0b0, 0b0, 0b00, 0b01111, Neon_saba>;
 534 def SABAvvv_16B : NeonI_3VSame_Constraint_impl<"saba", ".16b", VPR128, v16i8,
 535                     0b1, 0b0, 0b00, 0b01111, Neon_saba>;
 536 def SABAvvv_4H :  NeonI_3VSame_Constraint_impl<"saba", ".4h",  VPR64,  v4i16,
 537                     0b0, 0b0, 0b01, 0b01111, Neon_saba>;
 538 def SABAvvv_8H :  NeonI_3VSame_Constraint_impl<"saba", ".8h",  VPR128, v8i16,
 539                     0b1, 0b0, 0b01, 0b01111, Neon_saba>;
 540 def SABAvvv_2S :  NeonI_3VSame_Constraint_impl<"saba", ".2s",  VPR64,  v2i32,
 541                     0b0, 0b0, 0b10, 0b01111, Neon_saba>;
 542 def SABAvvv_4S :  NeonI_3VSame_Constraint_impl<"saba", ".4s",  VPR128, v4i32,
 543                     0b1, 0b0, 0b10, 0b01111, Neon_saba>;
 544
 545
 546 // Vector Absolute Difference (Signed, Unsigned)
 547 defm UABDvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01110, "uabd", int_arm_neon_vabdu, 0>;
 548 defm SABDvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01110, "sabd", int_arm_neon_vabds, 0>;
 549
 550 // Vector Absolute Difference (Floating Point)
 551 defm FABDvvv: NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11010, "fabd",
 552                                     int_arm_neon_vabds, int_arm_neon_vabds,
 553                                     int_arm_neon_vabds, v2f32, v4f32, v2f64, 0>;
 554
 555 // Vector Reciprocal Step (Floating Point)
 556 defm FRECPSvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11111, "frecps",
 557                                        int_arm_neon_vrecps, int_arm_neon_vrecps,
 558                                        int_arm_neon_vrecps,
 559                                        v2f32, v4f32, v2f64, 0>;
 560
 561 // Vector Reciprocal Square Root Step (Floating Point)
 562 defm FRSQRTSvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11111, "frsqrts",
 563                                         int_arm_neon_vrsqrts,
 564                                         int_arm_neon_vrsqrts,
 565                                         int_arm_neon_vrsqrts,
 566                                         v2f32, v4f32, v2f64, 0>;
 567
 568 // Vector Comparisons
 569
 570 def Neon_cmeq : PatFrag<(ops node:$lhs, node:$rhs),
 571                         (Neon_cmp node:$lhs, node:$rhs, SETEQ)>;
 572 def Neon_cmphs : PatFrag<(ops node:$lhs, node:$rhs),
 573                          (Neon_cmp node:$lhs, node:$rhs, SETUGE)>;
 574 def Neon_cmge : PatFrag<(ops node:$lhs, node:$rhs),
 575                         (Neon_cmp node:$lhs, node:$rhs, SETGE)>;
 576 def Neon_cmhi : PatFrag<(ops node:$lhs, node:$rhs),
 577                         (Neon_cmp node:$lhs, node:$rhs, SETUGT)>;
 578 def Neon_cmgt : PatFrag<(ops node:$lhs, node:$rhs),
 579                         (Neon_cmp node:$lhs, node:$rhs, SETGT)>;
 580
 581 // NeonI_compare_aliases class: swaps register operands to implement
 582 // comparison aliases, e.g., CMLE is alias for CMGE with operands reversed.
 583 class NeonI_compare_aliases<string asmop, string asmlane,
 584                             Instruction inst, RegisterOperand VPRC>
 585   : NeonInstAlias<asmop # "\t$Rd" # asmlane #", $Rn" # asmlane #
 586                     ", $Rm" # asmlane,
 587                   (inst VPRC:$Rd, VPRC:$Rm, VPRC:$Rn), 0b0>;
 588
 589 // Vector Comparisons (Integer)
 590
 591 // Vector Compare Mask Equal (Integer)
 592 let isCommutable =1 in {
 593 defm CMEQvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b10001, "cmeq", Neon_cmeq, 0>;
 594 }
 595
 596 // Vector Compare Mask Higher or Same (Unsigned Integer)
 597 defm CMHSvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00111, "cmhs", Neon_cmphs, 0>;
 598
 599 // Vector Compare Mask Greater Than or Equal (Integer)
 600 defm CMGEvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00111, "cmge", Neon_cmge, 0>;
 601
 602 // Vector Compare Mask Higher (Unsigned Integer)
 603 defm CMHIvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b00110, "cmhi", Neon_cmhi, 0>;
 604
 605 // Vector Compare Mask Greater Than (Integer)
 606 defm CMGTvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b00110, "cmgt", Neon_cmgt, 0>;
 607
 608 // Vector Compare Mask Bitwise Test (Integer)
 609 defm CMTSTvvv:  NeonI_3VSame_BHSD_sizes<0b0, 0b10001, "cmtst", Neon_tst, 0>;
 610
 611 // Vector Compare Mask Less or Same (Unsigned Integer)
 612 // CMLS is alias for CMHS with operands reversed.
 613 def CMLSvvv_8B  : NeonI_compare_aliases<"cmls", ".8b",  CMHSvvv_8B,  VPR64>;
 614 def CMLSvvv_16B : NeonI_compare_aliases<"cmls", ".16b", CMHSvvv_16B, VPR128>;
 615 def CMLSvvv_4H  : NeonI_compare_aliases<"cmls", ".4h",  CMHSvvv_4H,  VPR64>;
 616 def CMLSvvv_8H  : NeonI_compare_aliases<"cmls", ".8h",  CMHSvvv_8H,  VPR128>;
 617 def CMLSvvv_2S  : NeonI_compare_aliases<"cmls", ".2s",  CMHSvvv_2S,  VPR64>;
 618 def CMLSvvv_4S  : NeonI_compare_aliases<"cmls", ".4s",  CMHSvvv_4S,  VPR128>;
 619 def CMLSvvv_2D  : NeonI_compare_aliases<"cmls", ".2d",  CMHSvvv_2D,  VPR128>;
 620
 621 // Vector Compare Mask Less Than or Equal (Integer)
 622 // CMLE is alias for CMGE with operands reversed.
 623 def CMLEvvv_8B  : NeonI_compare_aliases<"cmle", ".8b",  CMGEvvv_8B,  VPR64>;
 624 def CMLEvvv_16B : NeonI_compare_aliases<"cmle", ".16b", CMGEvvv_16B, VPR128>;
 625 def CMLEvvv_4H  : NeonI_compare_aliases<"cmle", ".4h",  CMGEvvv_4H,  VPR64>;
 626 def CMLEvvv_8H  : NeonI_compare_aliases<"cmle", ".8h",  CMGEvvv_8H,  VPR128>;
 627 def CMLEvvv_2S  : NeonI_compare_aliases<"cmle", ".2s",  CMGEvvv_2S,  VPR64>;
 628 def CMLEvvv_4S  : NeonI_compare_aliases<"cmle", ".4s",  CMGEvvv_4S,  VPR128>;
 629 def CMLEvvv_2D  : NeonI_compare_aliases<"cmle", ".2d",  CMGEvvv_2D,  VPR128>;
 630
 631 // Vector Compare Mask Lower (Unsigned Integer)
 632 // CMLO is alias for CMHI with operands reversed.
 633 def CMLOvvv_8B  : NeonI_compare_aliases<"cmlo", ".8b",  CMHIvvv_8B,  VPR64>;
 634 def CMLOvvv_16B : NeonI_compare_aliases<"cmlo", ".16b", CMHIvvv_16B, VPR128>;
 635 def CMLOvvv_4H  : NeonI_compare_aliases<"cmlo", ".4h",  CMHIvvv_4H,  VPR64>;
 636 def CMLOvvv_8H  : NeonI_compare_aliases<"cmlo", ".8h",  CMHIvvv_8H,  VPR128>;
 637 def CMLOvvv_2S  : NeonI_compare_aliases<"cmlo", ".2s",  CMHIvvv_2S,  VPR64>;
 638 def CMLOvvv_4S  : NeonI_compare_aliases<"cmlo", ".4s",  CMHIvvv_4S,  VPR128>;
 639 def CMLOvvv_2D  : NeonI_compare_aliases<"cmlo", ".2d",  CMHIvvv_2D,  VPR128>;
 640
 641 // Vector Compare Mask Less Than (Integer)
 642 // CMLT is alias for CMGT with operands reversed.
 643 def CMLTvvv_8B  : NeonI_compare_aliases<"cmlt", ".8b",  CMGTvvv_8B,  VPR64>;
 644 def CMLTvvv_16B : NeonI_compare_aliases<"cmlt", ".16b", CMGTvvv_16B, VPR128>;
 645 def CMLTvvv_4H  : NeonI_compare_aliases<"cmlt", ".4h",  CMGTvvv_4H,  VPR64>;
 646 def CMLTvvv_8H  : NeonI_compare_aliases<"cmlt", ".8h",  CMGTvvv_8H,  VPR128>;
 647 def CMLTvvv_2S  : NeonI_compare_aliases<"cmlt", ".2s",  CMGTvvv_2S,  VPR64>;
 648 def CMLTvvv_4S  : NeonI_compare_aliases<"cmlt", ".4s",  CMGTvvv_4S,  VPR128>;
 649 def CMLTvvv_2D  : NeonI_compare_aliases<"cmlt", ".2d",  CMGTvvv_2D,  VPR128>;
 650
 651
 652 def neon_uimm0_asmoperand : AsmOperandClass
 653 {
 654   let Name = "UImm0";
 655   let PredicateMethod = "isUImm<0>";
 656   let RenderMethod = "addImmOperands";
 657 }
 658
 659 def neon_uimm0 : Operand<i32>, ImmLeaf<i32, [{return Imm == 0;}]> {
 660   let ParserMatchClass = neon_uimm0_asmoperand;
 661   let PrintMethod = "printNeonUImm0Operand";
 662
 663 }
 664
 665 multiclass NeonI_cmpz_sizes<bit u, bits<5> opcode, string asmop, CondCode CC>
 666 {
 667   def _8B :  NeonI_2VMisc<0b0, u, 0b00, opcode,
 668              (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 669              asmop # "\t$Rd.8b, $Rn.8b, $Imm",
 670              [(set (v8i8 VPR64:$Rd),
 671                 (v8i8 (Neon_cmpz (v8i8 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 672              NoItinerary>;
 673
 674   def _16B : NeonI_2VMisc<0b1, u, 0b00, opcode,
 675              (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 676              asmop # "\t$Rd.16b, $Rn.16b, $Imm",
 677              [(set (v16i8 VPR128:$Rd),
 678                 (v16i8 (Neon_cmpz (v16i8 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 679              NoItinerary>;
 680
 681   def _4H : NeonI_2VMisc<0b0, u, 0b01, opcode,
 682             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 683             asmop # "\t$Rd.4h, $Rn.4h, $Imm",
 684             [(set (v4i16 VPR64:$Rd),
 685                (v4i16 (Neon_cmpz (v4i16 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 686             NoItinerary>;
 687
 688   def _8H : NeonI_2VMisc<0b1, u, 0b01, opcode,
 689             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 690             asmop # "\t$Rd.8h, $Rn.8h, $Imm",
 691             [(set (v8i16 VPR128:$Rd),
 692                (v8i16 (Neon_cmpz (v8i16 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 693             NoItinerary>;
 694
 695   def _2S : NeonI_2VMisc<0b0, u, 0b10, opcode,
 696             (outs VPR64:$Rd), (ins VPR64:$Rn, neon_uimm0:$Imm),
 697             asmop # "\t$Rd.2s, $Rn.2s, $Imm",
 698             [(set (v2i32 VPR64:$Rd),
 699                (v2i32 (Neon_cmpz (v2i32 VPR64:$Rn), (i32 imm:$Imm), CC)))],
 700             NoItinerary>;
 701
 702   def _4S : NeonI_2VMisc<0b1, u, 0b10, opcode,
 703             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 704             asmop # "\t$Rd.4s, $Rn.4s, $Imm",
 705             [(set (v4i32 VPR128:$Rd),
 706                (v4i32 (Neon_cmpz (v4i32 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 707             NoItinerary>;
 708
 709   def _2D : NeonI_2VMisc<0b1, u, 0b11, opcode,
 710             (outs VPR128:$Rd), (ins VPR128:$Rn, neon_uimm0:$Imm),
 711             asmop # "\t$Rd.2d, $Rn.2d, $Imm",
 712             [(set (v2i64 VPR128:$Rd),
 713                (v2i64 (Neon_cmpz (v2i64 VPR128:$Rn), (i32 imm:$Imm), CC)))],
 714             NoItinerary>;
 715 }
 716
 717 // Vector Compare Mask Equal to Zero (Integer)
 718 defm CMEQvvi : NeonI_cmpz_sizes<0b0, 0b01001, "cmeq", SETEQ>;
 719
 720 // Vector Compare Mask Greater Than or Equal to Zero (Signed Integer)
 721 defm CMGEvvi : NeonI_cmpz_sizes<0b1, 0b01000, "cmge", SETGE>;
 722
 723 // Vector Compare Mask Greater Than Zero (Signed Integer)
 724 defm CMGTvvi : NeonI_cmpz_sizes<0b0, 0b01000, "cmgt", SETGT>;
 725
 726 // Vector Compare Mask Less Than or Equal To Zero (Signed Integer)
 727 defm CMLEvvi : NeonI_cmpz_sizes<0b1, 0b01001, "cmle", SETLE>;
 728
 729 // Vector Compare Mask Less Than Zero (Signed Integer)
 730 defm CMLTvvi : NeonI_cmpz_sizes<0b0, 0b01010, "cmlt", SETLT>;
 731
 732 // Vector Comparisons (Floating Point)
 733
 734 // Vector Compare Mask Equal (Floating Point)
 735 let isCommutable =1 in {
 736 defm FCMEQvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11100, "fcmeq", Neon_cmeq,
 737                                       Neon_cmeq, Neon_cmeq,
 738                                       v2i32, v4i32, v2i64, 0>;
 739 }
 740
 741 // Vector Compare Mask Greater Than Or Equal (Floating Point)
 742 defm FCMGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11100, "fcmge", Neon_cmge,
 743                                       Neon_cmge, Neon_cmge,
 744                                       v2i32, v4i32, v2i64, 0>;
 745
 746 // Vector Compare Mask Greater Than (Floating Point)
 747 defm FCMGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11100, "fcmgt", Neon_cmgt,
 748                                       Neon_cmgt, Neon_cmgt,
 749                                       v2i32, v4i32, v2i64, 0>;
 750
 751 // Vector Compare Mask Less Than Or Equal (Floating Point)
 752 // FCMLE is alias for FCMGE with operands reversed.
 753 def FCMLEvvv_2S  : NeonI_compare_aliases<"fcmle", ".2s",  FCMGEvvv_2S,  VPR64>;
 754 def FCMLEvvv_4S  : NeonI_compare_aliases<"fcmle", ".4s",  FCMGEvvv_4S,  VPR128>;
 755 def FCMLEvvv_2D  : NeonI_compare_aliases<"fcmle", ".2d",  FCMGEvvv_2D,  VPR128>;
 756
 757 // Vector Compare Mask Less Than (Floating Point)
 758 // FCMLT is alias for FCMGT with operands reversed.
 759 def FCMLTvvv_2S  : NeonI_compare_aliases<"fcmlt", ".2s",  FCMGTvvv_2S,  VPR64>;
 760 def FCMLTvvv_4S  : NeonI_compare_aliases<"fcmlt", ".4s",  FCMGTvvv_4S,  VPR128>;
 761 def FCMLTvvv_2D  : NeonI_compare_aliases<"fcmlt", ".2d",  FCMGTvvv_2D,  VPR128>;
 762
 763
 764 multiclass NeonI_fpcmpz_sizes<bit u, bit size, bits<5> opcode,
 765                               string asmop, CondCode CC>
 766 {
 767   def _2S : NeonI_2VMisc<0b0, u, {size, 0b0}, opcode,
 768             (outs VPR64:$Rd), (ins VPR64:$Rn, fpz32:$FPImm),
 769             asmop # "\t$Rd.2s, $Rn.2s, $FPImm",
 770             [(set (v2i32 VPR64:$Rd),
 771                (v2i32 (Neon_cmpz (v2f32 VPR64:$Rn), (f32 fpimm:$FPImm), CC)))],
 772             NoItinerary>;
 773
 774   def _4S : NeonI_2VMisc<0b1, u, {size, 0b0}, opcode,
 775             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 776             asmop # "\t$Rd.4s, $Rn.4s, $FPImm",
 777             [(set (v4i32 VPR128:$Rd),
 778                (v4i32 (Neon_cmpz (v4f32 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 779             NoItinerary>;
 780
 781   def _2D : NeonI_2VMisc<0b1, u, {size, 0b1}, opcode,
 782             (outs VPR128:$Rd), (ins VPR128:$Rn, fpz32:$FPImm),
 783             asmop # "\t$Rd.2d, $Rn.2d, $FPImm",
 784             [(set (v2i64 VPR128:$Rd),
 785                (v2i64 (Neon_cmpz (v2f64 VPR128:$Rn), (f32 fpimm:$FPImm), CC)))],
 786             NoItinerary>;
 787 }
 788
 789 // Vector Compare Mask Equal to Zero (Floating Point)
 790 defm FCMEQvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01101, "fcmeq", SETEQ>;
 791
 792 // Vector Compare Mask Greater Than or Equal to Zero (Floating Point)
 793 defm FCMGEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01100, "fcmge", SETGE>;
 794
 795 // Vector Compare Mask Greater Than Zero (Floating Point)
 796 defm FCMGTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01100, "fcmgt", SETGT>;
 797
 798 // Vector Compare Mask Less Than or Equal To Zero (Floating Point)
 799 defm FCMLEvvi : NeonI_fpcmpz_sizes<0b1, 0b1, 0b01101, "fcmle", SETLE>;
 800
 801 // Vector Compare Mask Less Than Zero (Floating Point)
 802 defm FCMLTvvi : NeonI_fpcmpz_sizes<0b0, 0b1, 0b01110, "fcmlt", SETLT>;
 803
 804 // Vector Absolute Comparisons (Floating Point)
 805
 806 // Vector Absolute Compare Mask Greater Than Or Equal (Floating Point)
 807 defm FACGEvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11101, "facge",
 808                                       int_arm_neon_vacged, int_arm_neon_vacgeq,
 809                                       int_aarch64_neon_vacgeq,
 810                                       v2i32, v4i32, v2i64, 0>;
 811
 812 // Vector Absolute Compare Mask Greater Than (Floating Point)
 813 defm FACGTvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11101, "facgt",
 814                                       int_arm_neon_vacgtd, int_arm_neon_vacgtq,
 815                                       int_aarch64_neon_vacgtq,
 816                                       v2i32, v4i32, v2i64, 0>;
 817
 818 // Vector Absolute Compare Mask Less Than Or Equal (Floating Point)
 819 // FACLE is alias for FACGE with operands reversed.
 820 def FACLEvvv_2S  : NeonI_compare_aliases<"facle", ".2s",  FACGEvvv_2S,  VPR64>;
 821 def FACLEvvv_4S  : NeonI_compare_aliases<"facle", ".4s",  FACGEvvv_4S,  VPR128>;
 822 def FACLEvvv_2D  : NeonI_compare_aliases<"facle", ".2d",  FACGEvvv_2D,  VPR128>;
 823
 824 // Vector Absolute Compare Mask Less Than (Floating Point)
 825 // FACLT is alias for FACGT with operands reversed.
 826 def FACLTvvv_2S  : NeonI_compare_aliases<"faclt", ".2s",  FACGTvvv_2S,  VPR64>;
 827 def FACLTvvv_4S  : NeonI_compare_aliases<"faclt", ".4s",  FACGTvvv_4S,  VPR128>;
 828 def FACLTvvv_2D  : NeonI_compare_aliases<"faclt", ".2d",  FACGTvvv_2D,  VPR128>;
 829
 830 // Vector halving add (Integer Signed, Unsigned)
 831 defm SHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00000, "shadd",
 832                                         int_arm_neon_vhadds, 1>;
 833 defm UHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00000, "uhadd",
 834                                         int_arm_neon_vhaddu, 1>;
 835
 836 // Vector halving sub (Integer Signed, Unsigned)
 837 defm SHSUBvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00100, "shsub",
 838                                         int_arm_neon_vhsubs, 0>;
 839 defm UHSUBvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00100, "uhsub",
 840                                         int_arm_neon_vhsubu, 0>;
 841
 842 // Vector rouding halving add (Integer Signed, Unsigned)
 843 defm SRHADDvvv :  NeonI_3VSame_BHS_sizes<0b0, 0b00010, "srhadd",
 844                                          int_arm_neon_vrhadds, 1>;
 845 defm URHADDvvv :  NeonI_3VSame_BHS_sizes<0b1, 0b00010, "urhadd",
 846                                          int_arm_neon_vrhaddu, 1>;
 847
 848 // Vector Saturating add (Integer Signed, Unsigned)
 849 defm SQADDvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00001, "sqadd",
 850                    int_arm_neon_vqadds, 1>;
 851 defm UQADDvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00001, "uqadd",
 852                    int_arm_neon_vqaddu, 1>;
 853
 854 // Vector Saturating sub (Integer Signed, Unsigned)
 855 defm SQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b0, 0b00101, "sqsub",
 856                    int_arm_neon_vqsubs, 1>;
 857 defm UQSUBvvv :  NeonI_3VSame_BHSD_sizes<0b1, 0b00101, "uqsub",
 858                    int_arm_neon_vqsubu, 1>;
 859
 860 // Vector Shift Left (Signed and Unsigned Integer)
 861 defm SSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01000, "sshl",
 862                  int_arm_neon_vshifts, 1>;
 863 defm USHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01000, "ushl",
 864                  int_arm_neon_vshiftu, 1>;
 865
 866 // Vector Saturating Shift Left (Signed and Unsigned Integer)
 867 defm SQSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01001, "sqshl",
 868                   int_arm_neon_vqshifts, 1>;
 869 defm UQSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01001, "uqshl",
 870                   int_arm_neon_vqshiftu, 1>;
 871
 872 // Vector Rouding Shift Left (Signed and Unsigned Integer)
 873 defm SRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01010, "srshl",
 874                   int_arm_neon_vrshifts, 1>;
 875 defm URSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01010, "urshl",
 876                   int_arm_neon_vrshiftu, 1>;
 877
 878 // Vector Saturating Rouding Shift Left (Signed and Unsigned Integer)
 879 defm SQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b0, 0b01011, "sqrshl",
 880                    int_arm_neon_vqrshifts, 1>;
 881 defm UQRSHLvvv : NeonI_3VSame_BHSD_sizes<0b1, 0b01011, "uqrshl",
 882                    int_arm_neon_vqrshiftu, 1>;
 883
 884 // Vector Maximum (Signed and Unsigned Integer)
 885 defm SMAXvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01100, "smax", int_arm_neon_vmaxs, 1>;
 886 defm UMAXvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01100, "umax", int_arm_neon_vmaxu, 1>;
 887
 888 // Vector Minimum (Signed and Unsigned Integer)
 889 defm SMINvvv : NeonI_3VSame_BHS_sizes<0b0, 0b01101, "smin", int_arm_neon_vmins, 1>;
 890 defm UMINvvv : NeonI_3VSame_BHS_sizes<0b1, 0b01101, "umin", int_arm_neon_vminu, 1>;
 891
 892 // Vector Maximum (Floating Point)
 893 defm FMAXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11110, "fmax",
 894                                      int_arm_neon_vmaxs, int_arm_neon_vmaxs,
 895                                      int_arm_neon_vmaxs, v2f32, v4f32, v2f64, 1>;
 896
 897 // Vector Minimum (Floating Point)
 898 defm FMINvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11110, "fmin",
 899                                      int_arm_neon_vmins, int_arm_neon_vmins,
 900                                      int_arm_neon_vmins, v2f32, v4f32, v2f64, 1>;
 901
 902 // Vector maxNum (Floating Point) -  prefer a number over a quiet NaN)
 903 defm FMAXNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11000, "fmaxnm",
 904                                        int_aarch64_neon_vmaxnm,
 905                                        int_aarch64_neon_vmaxnm,
 906                                        int_aarch64_neon_vmaxnm,
 907                                        v2f32, v4f32, v2f64, 1>;
 908
 909 // Vector minNum (Floating Point) - prefer a number over a quiet NaN)
 910 defm FMINNMvvv : NeonI_3VSame_SD_sizes<0b0, 0b1, 0b11000, "fminnm",
 911                                        int_aarch64_neon_vminnm,
 912                                        int_aarch64_neon_vminnm,
 913                                        int_aarch64_neon_vminnm,
 914                                        v2f32, v4f32, v2f64, 1>;
 915
 916 // Vector Maximum Pairwise (Signed and Unsigned Integer)
 917 defm SMAXPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10100, "smaxp", int_arm_neon_vpmaxs, 1>;
 918 defm UMAXPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10100, "umaxp", int_arm_neon_vpmaxu, 1>;
 919
 920 // Vector Minimum Pairwise (Signed and Unsigned Integer)
 921 defm SMINPvvv : NeonI_3VSame_BHS_sizes<0b0, 0b10101, "sminp", int_arm_neon_vpmins, 1>;
 922 defm UMINPvvv : NeonI_3VSame_BHS_sizes<0b1, 0b10101, "uminp", int_arm_neon_vpminu, 1>;
 923
 924 // Vector Maximum Pairwise (Floating Point)
 925 defm FMAXPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11110, "fmaxp",
 926                                      int_arm_neon_vpmaxs, int_arm_neon_vpmaxs,
 927                                      int_arm_neon_vpmaxs, v2f32, v4f32, v2f64, 1>;
 928
 929 // Vector Minimum Pairwise (Floating Point)
 930 defm FMINPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11110, "fminp",
 931                                      int_arm_neon_vpmins, int_arm_neon_vpmins,
 932                                      int_arm_neon_vpmins, v2f32, v4f32, v2f64, 1>;
 933
 934 // Vector maxNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 935 defm FMAXNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11000, "fmaxnmp",
 936                                        int_aarch64_neon_vpmaxnm,
 937                                        int_aarch64_neon_vpmaxnm,
 938                                        int_aarch64_neon_vpmaxnm,
 939                                        v2f32, v4f32, v2f64, 1>;
 940
 941 // Vector minNum Pairwise (Floating Point) -  prefer a number over a quiet NaN)
 942 defm FMINNMPvvv : NeonI_3VSame_SD_sizes<0b1, 0b1, 0b11000, "fminnmp",
 943                                        int_aarch64_neon_vpminnm,
 944                                        int_aarch64_neon_vpminnm,
 945                                        int_aarch64_neon_vpminnm,
 946                                        v2f32, v4f32, v2f64, 1>;
 947
 948 // Vector Addition Pairwise (Integer)
 949 defm ADDP : NeonI_3VSame_BHSD_sizes<0b0, 0b10111, "addp", int_arm_neon_vpadd, 1>;
 950
 951 // Vector Addition Pairwise (Floating Point)
 952 defm FADDP : NeonI_3VSame_SD_sizes<0b1, 0b0, 0b11010, "faddp",
 953                                        int_arm_neon_vpadd,
 954                                        int_arm_neon_vpadd,
 955                                        int_arm_neon_vpadd,
 956                                        v2f32, v4f32, v2f64, 1>;
 957
 958 // Vector Saturating Doubling Multiply High
 959 defm SQDMULHvvv : NeonI_3VSame_HS_sizes<0b0, 0b10110, "sqdmulh",
 960                     int_arm_neon_vqdmulh, 1>;
 961
 962 // Vector Saturating Rouding Doubling Multiply High
 963 defm SQRDMULHvvv : NeonI_3VSame_HS_sizes<0b1, 0b10110, "sqrdmulh",
 964                      int_arm_neon_vqrdmulh, 1>;
 965
 966 // Vector Multiply Extended (Floating Point)
 967 defm FMULXvvv : NeonI_3VSame_SD_sizes<0b0, 0b0, 0b11011, "fmulx",
 968                                       int_aarch64_neon_vmulx,
 969                                       int_aarch64_neon_vmulx,
 970                                       int_aarch64_neon_vmulx,
 971                                       v2f32, v4f32, v2f64, 1>;
 972
 973 // Vector Immediate Instructions
 974
 975 multiclass neon_mov_imm_shift_asmoperands<string PREFIX>
 976 {
 977   def _asmoperand : AsmOperandClass
 978     {
 979       let Name = "NeonMovImmShift" # PREFIX;
 980       let RenderMethod = "addNeonMovImmShift" # PREFIX # "Operands";
 981       let PredicateMethod = "isNeonMovImmShift" # PREFIX;
 982     }
 983 }
 984
 985 // Definition of vector immediates shift operands
 986
 987 // The selectable use-cases extract the shift operation
 988 // information from the OpCmode fields encoded in the immediate.
 989 def neon_mod_shift_imm_XFORM : SDNodeXForm<imm, [{
 990   uint64_t OpCmode = N->getZExtValue();
 991   unsigned ShiftImm;
 992   unsigned ShiftOnesIn;
 993   unsigned HasShift =
 994     A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
 995   if (!HasShift) return SDValue();
 996   return CurDAG->getTargetConstant(ShiftImm, MVT::i32);
 997 }]>;
 998
 999 // Vector immediates shift operands which accept LSL and MSL
1000 // shift operators with shift value in the range of 0, 8, 16, 24 (LSL),
1001 // or 0, 8 (LSLH) or 8, 16 (MSL).
1002 defm neon_mov_imm_LSL : neon_mov_imm_shift_asmoperands<"LSL">;
1003 defm neon_mov_imm_MSL : neon_mov_imm_shift_asmoperands<"MSL">;
1004 // LSLH restricts shift amount to  0, 8 out of 0, 8, 16, 24
1005 defm neon_mov_imm_LSLH : neon_mov_imm_shift_asmoperands<"LSLH">;
1006
1007 multiclass neon_mov_imm_shift_operands<string PREFIX,
1008                                        string HALF, string ISHALF, code pred>
1009 {
1010    def _operand : Operand<i32>, ImmLeaf<i32, pred, neon_mod_shift_imm_XFORM>
1011     {
1012       let PrintMethod =
1013         "printNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1014       let DecoderMethod =
1015         "DecodeNeonMovImmShiftOperand<A64SE::" # PREFIX # ", " # ISHALF # ">";
1016       let ParserMatchClass =
1017         !cast<AsmOperandClass>("neon_mov_imm_" # PREFIX # HALF # "_asmoperand");
1018     }
1019 }
1020
1021 defm neon_mov_imm_LSL  : neon_mov_imm_shift_operands<"LSL", "", "false", [{
1022   unsigned ShiftImm;
1023   unsigned ShiftOnesIn;
1024   unsigned HasShift =
1025     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1026   return (HasShift && !ShiftOnesIn);
1027 }]>;
1028
1029 defm neon_mov_imm_MSL  : neon_mov_imm_shift_operands<"MSL", "", "false", [{
1030   unsigned ShiftImm;
1031   unsigned ShiftOnesIn;
1032   unsigned HasShift =
1033     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1034   return (HasShift && ShiftOnesIn);
1035 }]>;
1036
1037 defm neon_mov_imm_LSLH  : neon_mov_imm_shift_operands<"LSL", "H", "true", [{
1038   unsigned ShiftImm;
1039   unsigned ShiftOnesIn;
1040   unsigned HasShift =
1041     A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1042   return (HasShift && !ShiftOnesIn);
1043 }]>;
1044
1045 def neon_uimm1_asmoperand : AsmOperandClass
1046 {
1047   let Name = "UImm1";
1048   let PredicateMethod = "isUImm<1>";
1049   let RenderMethod = "addImmOperands";
1050 }
1051
1052 def neon_uimm2_asmoperand : AsmOperandClass
1053 {
1054   let Name = "UImm2";
1055   let PredicateMethod = "isUImm<2>";
1056   let RenderMethod = "addImmOperands";
1057 }
1058
1059 def neon_uimm8_asmoperand : AsmOperandClass
1060 {
1061   let Name = "UImm8";
1062   let PredicateMethod = "isUImm<8>";
1063   let RenderMethod = "addImmOperands";
1064 }
1065
1066 def neon_uimm8 : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1067   let ParserMatchClass = neon_uimm8_asmoperand;
1068   let PrintMethod = "printUImmHexOperand";
1069 }
1070
1071 def neon_uimm64_mask_asmoperand : AsmOperandClass
1072 {
1073   let Name = "NeonUImm64Mask";
1074   let PredicateMethod = "isNeonUImm64Mask";
1075   let RenderMethod = "addNeonUImm64MaskOperands";
1076 }
1077
1078 // MCOperand for 64-bit bytemask with each byte having only the
1079 // value 0x00 and 0xff is encoded as an unsigned 8-bit value
1080 def neon_uimm64_mask : Operand<i32>, ImmLeaf<i32, [{(void)Imm; return true;}]> {
1081   let ParserMatchClass = neon_uimm64_mask_asmoperand;
1082   let PrintMethod = "printNeonUImm64MaskOperand";
1083 }
1084
1085 multiclass NeonI_mov_imm_lsl_sizes<string asmop, bit op,
1086                                    SDPatternOperator opnode>
1087 {
1088     // shift zeros, per word
1089     def _2S  : NeonI_1VModImm<0b0, op,
1090                               (outs VPR64:$Rd),
1091                               (ins neon_uimm8:$Imm,
1092                                 neon_mov_imm_LSL_operand:$Simm),
1093                               !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1094                               [(set (v2i32 VPR64:$Rd),
1095                                  (v2i32 (opnode (timm:$Imm),
1096                                    (neon_mov_imm_LSL_operand:$Simm))))],
1097                               NoItinerary> {
1098        bits<2> Simm;
1099        let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1100      }
1101
1102     def _4S  : NeonI_1VModImm<0b1, op,
1103                               (outs VPR128:$Rd),
1104                               (ins neon_uimm8:$Imm,
1105                                 neon_mov_imm_LSL_operand:$Simm),
1106                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1107                               [(set (v4i32 VPR128:$Rd),
1108                                  (v4i32 (opnode (timm:$Imm),
1109                                    (neon_mov_imm_LSL_operand:$Simm))))],
1110                               NoItinerary> {
1111       bits<2> Simm;
1112       let cmode = {0b0, Simm{1}, Simm{0}, 0b0};
1113     }
1114
1115     // shift zeros, per halfword
1116     def _4H  : NeonI_1VModImm<0b0, op,
1117                               (outs VPR64:$Rd),
1118                               (ins neon_uimm8:$Imm,
1119                                 neon_mov_imm_LSLH_operand:$Simm),
1120                               !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1121                               [(set (v4i16 VPR64:$Rd),
1122                                  (v4i16 (opnode (timm:$Imm),
1123                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1124                               NoItinerary> {
1125       bit  Simm;
1126       let cmode = {0b1, 0b0, Simm, 0b0};
1127     }
1128
1129     def _8H  : NeonI_1VModImm<0b1, op,
1130                               (outs VPR128:$Rd),
1131                               (ins neon_uimm8:$Imm,
1132                                 neon_mov_imm_LSLH_operand:$Simm),
1133                               !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1134                               [(set (v8i16 VPR128:$Rd),
1135                                  (v8i16 (opnode (timm:$Imm),
1136                                    (neon_mov_imm_LSLH_operand:$Simm))))],
1137                               NoItinerary> {
1138       bit Simm;
1139       let cmode = {0b1, 0b0, Simm, 0b0};
1140      }
1141 }
1142
1143 multiclass NeonI_mov_imm_with_constraint_lsl_sizes<string asmop, bit op,
1144                                                    SDPatternOperator opnode,
1145                                                    SDPatternOperator neonopnode>
1146 {
1147   let Constraints = "$src = $Rd" in {
1148     // shift zeros, per word
1149     def _2S  : NeonI_1VModImm<0b0, op,
1150                  (outs VPR64:$Rd),
1151                  (ins VPR64:$src, neon_uimm8:$Imm,
1152                    neon_mov_imm_LSL_operand:$Simm),
1153                  !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1154                  [(set (v2i32 VPR64:$Rd),
1155                     (v2i32 (opnode (v2i32 VPR64:$src),
1156                       (v2i32 (bitconvert (v2i32 (neonopnode timm:$Imm,
1157                         neon_mov_imm_LSL_operand:$Simm)))))))],
1158                  NoItinerary> {
1159       bits<2> Simm;
1160       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1161     }
1162
1163     def _4S  : NeonI_1VModImm<0b1, op,
1164                  (outs VPR128:$Rd),
1165                  (ins VPR128:$src, neon_uimm8:$Imm,
1166                    neon_mov_imm_LSL_operand:$Simm),
1167                  !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1168                  [(set (v4i32 VPR128:$Rd),
1169                     (v4i32 (opnode (v4i32 VPR128:$src),
1170                       (v4i32 (bitconvert (v4i32 (neonopnode timm:$Imm,
1171                         neon_mov_imm_LSL_operand:$Simm)))))))],
1172                  NoItinerary> {
1173       bits<2> Simm;
1174       let cmode = {0b0, Simm{1}, Simm{0}, 0b1};
1175     }
1176
1177     // shift zeros, per halfword
1178     def _4H  : NeonI_1VModImm<0b0, op,
1179                  (outs VPR64:$Rd),
1180                  (ins VPR64:$src, neon_uimm8:$Imm,
1181                    neon_mov_imm_LSLH_operand:$Simm),
1182                  !strconcat(asmop, "\t$Rd.4h, $Imm$Simm"),
1183                  [(set (v4i16 VPR64:$Rd),
1184                     (v4i16 (opnode (v4i16 VPR64:$src),
1185                        (v4i16 (bitconvert (v4i16 (neonopnode timm:$Imm,
1186                           neon_mov_imm_LSL_operand:$Simm)))))))],
1187                  NoItinerary> {
1188       bit  Simm;
1189       let cmode = {0b1, 0b0, Simm, 0b1};
1190     }
1191
1192     def _8H  : NeonI_1VModImm<0b1, op,
1193                  (outs VPR128:$Rd),
1194                  (ins VPR128:$src, neon_uimm8:$Imm,
1195                    neon_mov_imm_LSLH_operand:$Simm),
1196                  !strconcat(asmop, "\t$Rd.8h, $Imm$Simm"),
1197                  [(set (v8i16 VPR128:$Rd),
1198                     (v8i16 (opnode (v8i16 VPR128:$src),
1199                       (v8i16 (bitconvert (v8i16 (neonopnode timm:$Imm,
1200                         neon_mov_imm_LSL_operand:$Simm)))))))],
1201                  NoItinerary> {
1202       bit Simm;
1203       let cmode = {0b1, 0b0, Simm, 0b1};
1204     }
1205   }
1206 }
1207
1208 multiclass NeonI_mov_imm_msl_sizes<string asmop, bit op,
1209                                    SDPatternOperator opnode>
1210 {
1211     // shift ones, per word
1212     def _2S  : NeonI_1VModImm<0b0, op,
1213                              (outs VPR64:$Rd),
1214                              (ins neon_uimm8:$Imm,
1215                                neon_mov_imm_MSL_operand:$Simm),
1216                              !strconcat(asmop, "\t$Rd.2s, $Imm$Simm"),
1217                               [(set (v2i32 VPR64:$Rd),
1218                                  (v2i32 (opnode (timm:$Imm),
1219                                    (neon_mov_imm_MSL_operand:$Simm))))],
1220                              NoItinerary> {
1221        bit Simm;
1222        let cmode = {0b1, 0b1, 0b0, Simm};
1223      }
1224
1225    def _4S  : NeonI_1VModImm<0b1, op,
1226                               (outs VPR128:$Rd),
1227                               (ins neon_uimm8:$Imm,
1228                                 neon_mov_imm_MSL_operand:$Simm),
1229                               !strconcat(asmop, "\t$Rd.4s, $Imm$Simm"),
1230                               [(set (v4i32 VPR128:$Rd),
1231                                  (v4i32 (opnode (timm:$Imm),
1232                                    (neon_mov_imm_MSL_operand:$Simm))))],
1233                               NoItinerary> {
1234      bit Simm;
1235      let cmode = {0b1, 0b1, 0b0, Simm};
1236    }
1237 }
1238
1239 // Vector Move Immediate Shifted
1240 let isReMaterializable = 1 in {
1241 defm MOVIvi_lsl : NeonI_mov_imm_lsl_sizes<"movi", 0b0, Neon_movi>;
1242 }
1243
1244 // Vector Move Inverted Immediate Shifted
1245 let isReMaterializable = 1 in {
1246 defm MVNIvi_lsl : NeonI_mov_imm_lsl_sizes<"mvni", 0b1, Neon_mvni>;
1247 }
1248
1249 // Vector Bitwise Bit Clear (AND NOT) - immediate
1250 let isReMaterializable = 1 in {
1251 defm BICvi_lsl : NeonI_mov_imm_with_constraint_lsl_sizes<"bic", 0b1,
1252                                                          and, Neon_mvni>;
1253 }
1254
1255 // Vector Bitwise OR - immedidate
1256
1257 let isReMaterializable = 1 in {
1258 defm ORRvi_lsl   : NeonI_mov_imm_with_constraint_lsl_sizes<"orr", 0b0,
1259                                                            or, Neon_movi>;
1260 }
1261
1262 // Additional patterns for Vector Bitwise Bit Clear (AND NOT) - immedidate
1263 // LowerBUILD_VECTOR favors lowering MOVI over MVNI.
1264 // BIC immediate instructions selection requires additional patterns to
1265 // transform Neon_movi operands into BIC immediate operands
1266
1267 def neon_mov_imm_LSLH_transform_XFORM : SDNodeXForm<imm, [{
1268   uint64_t OpCmode = N->getZExtValue();
1269   unsigned ShiftImm;
1270   unsigned ShiftOnesIn;
1271   (void)A64Imms::decodeNeonModShiftImm(OpCmode, ShiftImm, ShiftOnesIn);
1272   // LSLH restricts shift amount to  0, 8 which are encoded as 0 and 1
1273   // Transform encoded shift amount 0 to 1 and 1 to 0.
1274   return CurDAG->getTargetConstant(!ShiftImm, MVT::i32);
1275 }]>;
1276
1277 def neon_mov_imm_LSLH_transform_operand
1278   : ImmLeaf<i32, [{
1279     unsigned ShiftImm;
1280     unsigned ShiftOnesIn;
1281     unsigned HasShift =
1282       A64Imms::decodeNeonModShiftImm(Imm, ShiftImm, ShiftOnesIn);
1283     return (HasShift && !ShiftOnesIn); }],
1284   neon_mov_imm_LSLH_transform_XFORM>;
1285
1286 // Transform (and A, (4h Neon_movi 0xff)) -> BIC 4h (A, 0x00, LSL 8)
1287 // Transform (and A, (4h Neon_movi 0xff LSL #8)) -> BIC 4h (A, 0x00)
1288 def : Pat<(v4i16 (and VPR64:$src,
1289             (v4i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1290           (BICvi_lsl_4H VPR64:$src, 0,
1291             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1292
1293 // Transform (and A, (8h Neon_movi 8h 0xff)) -> BIC 8h (A, 0x00, LSL 8)
1294 // Transform (and A, (8h Neon_movi 0xff LSL #8)) -> BIC 8h (A, 0x00)
1295 def : Pat<(v8i16 (and VPR128:$src,
1296             (v8i16 (Neon_movi 255, neon_mov_imm_LSLH_transform_operand:$Simm)))),
1297           (BICvi_lsl_8H VPR128:$src, 0,
1298             neon_mov_imm_LSLH_transform_operand:$Simm)>;
1299
1300
1301 multiclass Neon_bitwiseVi_patterns<SDPatternOperator opnode,
1302                                    SDPatternOperator neonopnode,
1303                                    Instruction INST4H,
1304                                    Instruction INST8H> {
1305   def : Pat<(v8i8 (opnode VPR64:$src,
1306                     (bitconvert(v4i16 (neonopnode timm:$Imm,
1307                       neon_mov_imm_LSLH_operand:$Simm))))),
1308             (INST4H VPR64:$src, neon_uimm8:$Imm,
1309               neon_mov_imm_LSLH_operand:$Simm)>;
1310   def : Pat<(v1i64 (opnode VPR64:$src,
1311                   (bitconvert(v4i16 (neonopnode timm:$Imm,
1312                     neon_mov_imm_LSLH_operand:$Simm))))),
1313           (INST4H VPR64:$src, neon_uimm8:$Imm,
1314             neon_mov_imm_LSLH_operand:$Simm)>;
1315
1316   def : Pat<(v16i8 (opnode VPR128:$src,
1317                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1318                      neon_mov_imm_LSLH_operand:$Simm))))),
1319           (INST8H VPR128:$src, neon_uimm8:$Imm,
1320             neon_mov_imm_LSLH_operand:$Simm)>;
1321   def : Pat<(v4i32 (opnode VPR128:$src,
1322                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1323                      neon_mov_imm_LSLH_operand:$Simm))))),
1324           (INST8H VPR128:$src, neon_uimm8:$Imm,
1325             neon_mov_imm_LSLH_operand:$Simm)>;
1326   def : Pat<(v2i64 (opnode VPR128:$src,
1327                    (bitconvert(v8i16 (neonopnode timm:$Imm,
1328                      neon_mov_imm_LSLH_operand:$Simm))))),
1329           (INST8H VPR128:$src, neon_uimm8:$Imm,
1330             neon_mov_imm_LSLH_operand:$Simm)>;
1331 }
1332
1333 // Additional patterns for Vector Vector Bitwise Bit Clear (AND NOT) - immediate
1334 defm : Neon_bitwiseVi_patterns<or, Neon_mvni, BICvi_lsl_4H, BICvi_lsl_8H>;
1335
1336 // Additional patterns for Vector Bitwise OR - immedidate
1337 defm : Neon_bitwiseVi_patterns<or, Neon_movi, ORRvi_lsl_4H, ORRvi_lsl_8H>;
1338
1339
1340 // Vector Move Immediate Masked
1341 let isReMaterializable = 1 in {
1342 defm MOVIvi_msl : NeonI_mov_imm_msl_sizes<"movi", 0b0, Neon_movi>;
1343 }
1344
1345 // Vector Move Inverted Immediate Masked
1346 let isReMaterializable = 1 in {
1347 defm MVNIvi_msl : NeonI_mov_imm_msl_sizes<"mvni", 0b1, Neon_mvni>;
1348 }
1349
1350 class NeonI_mov_imm_lsl_aliases<string asmop, string asmlane,
1351                                 Instruction inst, RegisterOperand VPRC>
1352   : NeonInstAlias<!strconcat(asmop, "\t$Rd," # asmlane # ", $Imm"),
1353                         (inst VPRC:$Rd, neon_uimm8:$Imm,  0), 0b0>;
1354
1355 // Aliases for Vector Move Immediate Shifted
1356 def : NeonI_mov_imm_lsl_aliases<"movi", ".2s", MOVIvi_lsl_2S, VPR64>;
1357 def : NeonI_mov_imm_lsl_aliases<"movi", ".4s", MOVIvi_lsl_4S, VPR128>;
1358 def : NeonI_mov_imm_lsl_aliases<"movi", ".4h", MOVIvi_lsl_4H, VPR64>;
1359 def : NeonI_mov_imm_lsl_aliases<"movi", ".8h", MOVIvi_lsl_8H, VPR128>;
1360
1361 // Aliases for Vector Move Inverted Immediate Shifted
1362 def : NeonI_mov_imm_lsl_aliases<"mvni", ".2s", MVNIvi_lsl_2S, VPR64>;
1363 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4s", MVNIvi_lsl_4S, VPR128>;
1364 def : NeonI_mov_imm_lsl_aliases<"mvni", ".4h", MVNIvi_lsl_4H, VPR64>;
1365 def : NeonI_mov_imm_lsl_aliases<"mvni", ".8h", MVNIvi_lsl_8H, VPR128>;
1366
1367 // Aliases for Vector Bitwise Bit Clear (AND NOT) - immediate
1368 def : NeonI_mov_imm_lsl_aliases<"bic", ".2s", BICvi_lsl_2S, VPR64>;
1369 def : NeonI_mov_imm_lsl_aliases<"bic", ".4s", BICvi_lsl_4S, VPR128>;
1370 def : NeonI_mov_imm_lsl_aliases<"bic", ".4h", BICvi_lsl_4H, VPR64>;
1371 def : NeonI_mov_imm_lsl_aliases<"bic", ".8h", BICvi_lsl_8H, VPR128>;
1372
1373 // Aliases for Vector Bitwise OR - immedidate
1374 def : NeonI_mov_imm_lsl_aliases<"orr", ".2s", ORRvi_lsl_2S, VPR64>;
1375 def : NeonI_mov_imm_lsl_aliases<"orr", ".4s", ORRvi_lsl_4S, VPR128>;
1376 def : NeonI_mov_imm_lsl_aliases<"orr", ".4h", ORRvi_lsl_4H, VPR64>;
1377 def : NeonI_mov_imm_lsl_aliases<"orr", ".8h", ORRvi_lsl_8H, VPR128>;
1378
1379 //  Vector Move Immediate - per byte
1380 let isReMaterializable = 1 in {
1381 def MOVIvi_8B : NeonI_1VModImm<0b0, 0b0,
1382                                (outs VPR64:$Rd), (ins neon_uimm8:$Imm),
1383                                "movi\t$Rd.8b, $Imm",
1384                                [(set (v8i8 VPR64:$Rd),
1385                                   (v8i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1386                                 NoItinerary> {
1387   let cmode = 0b1110;
1388 }
1389
1390 def MOVIvi_16B : NeonI_1VModImm<0b1, 0b0,
1391                                 (outs VPR128:$Rd), (ins neon_uimm8:$Imm),
1392                                 "movi\t$Rd.16b, $Imm",
1393                                 [(set (v16i8 VPR128:$Rd),
1394                                    (v16i8 (Neon_movi (timm:$Imm), (i32 imm))))],
1395                                  NoItinerary> {
1396   let cmode = 0b1110;
1397 }
1398 }
1399
1400 // Vector Move Immediate - bytemask, per double word
1401 let isReMaterializable = 1 in {
1402 def MOVIvi_2D : NeonI_1VModImm<0b1, 0b1,
1403                                (outs VPR128:$Rd), (ins neon_uimm64_mask:$Imm),
1404                                "movi\t $Rd.2d, $Imm",
1405                                [(set (v2i64 VPR128:$Rd),
1406                                   (v2i64 (Neon_movi (timm:$Imm), (i32 imm))))],
1407                                NoItinerary> {
1408   let cmode = 0b1110;
1409 }
1410 }
1411
1412 // Vector Move Immediate - bytemask, one doubleword
1413
1414 let isReMaterializable = 1 in {
1415 def MOVIdi : NeonI_1VModImm<0b0, 0b1,
1416                            (outs FPR64:$Rd), (ins neon_uimm64_mask:$Imm),
1417                            "movi\t $Rd, $Imm",
1418                            [(set (f64 FPR64:$Rd),
1419                               (f64 (bitconvert
1420                                 (v1i64 (Neon_movi (timm:$Imm), (i32 imm))))))],
1421                            NoItinerary> {
1422   let cmode = 0b1110;
1423 }
1424 }
1425
1426 // Vector Floating Point Move Immediate
1427
1428 class NeonI_FMOV_impl<string asmlane, RegisterOperand VPRC, ValueType OpTy,
1429                       Operand immOpType, bit q, bit op>
1430   : NeonI_1VModImm<q, op,
1431                    (outs VPRC:$Rd), (ins immOpType:$Imm),
1432                    "fmov\t$Rd" # asmlane # ", $Imm",
1433                    [(set (OpTy VPRC:$Rd),
1434                       (OpTy (Neon_fmovi (timm:$Imm))))],
1435                    NoItinerary> {
1436      let cmode = 0b1111;
1437    }
1438
1439 let isReMaterializable = 1 in {
1440 def FMOVvi_2S : NeonI_FMOV_impl<".2s", VPR64,  v2f32, fmov32_operand, 0b0, 0b0>;
1441 def FMOVvi_4S : NeonI_FMOV_impl<".4s", VPR128, v4f32, fmov32_operand, 0b1, 0b0>;
1442 def FMOVvi_2D : NeonI_FMOV_impl<".2d", VPR128, v2f64, fmov64_operand, 0b1, 0b1>;
1443 }
1444
1445 // Vector Shift (Immediate)
1446 // Immediate in [0, 63]
1447 def imm0_63 : Operand<i32> {
1448   let ParserMatchClass = uimm6_asmoperand;
1449 }
1450
1451 // Shift Right/Left Immediate - The immh:immb field of these shifts are encoded
1452 // as follows:
1453 //
1454 //    Offset    Encoding
1455 //     8        immh:immb<6:3> = '0001xxx', <imm> is encoded in immh:immb<2:0>
1456 //     16       immh:immb<6:4> = '001xxxx', <imm> is encoded in immh:immb<3:0>
1457 //     32       immh:immb<6:5> = '01xxxxx', <imm> is encoded in immh:immb<4:0>
1458 //     64       immh:immb<6>   = '1xxxxxx', <imm> is encoded in immh:immb<5:0>
1459 //
1460 // The shift right immediate amount, in the range 1 to element bits, is computed
1461 // as Offset - UInt(immh:immb).  The shift left immediate amount, in the range 0
1462 // to element bits - 1, is computed as UInt(immh:immb) - Offset.
1463
1464 class shr_imm_asmoperands<string OFFSET> : AsmOperandClass {
1465   let Name = "ShrImm" # OFFSET;
1466   let RenderMethod = "addImmOperands";
1467   let DiagnosticType = "ShrImm" # OFFSET;
1468 }
1469
1470 class shr_imm<string OFFSET> : Operand<i32> {
1471   let EncoderMethod = "getShiftRightImm" # OFFSET;
1472   let DecoderMethod = "DecodeShiftRightImm" # OFFSET;
1473   let ParserMatchClass =
1474     !cast<AsmOperandClass>("shr_imm" # OFFSET # "_asmoperand");
1475 }
1476
1477 def shr_imm8_asmoperand : shr_imm_asmoperands<"8">;
1478 def shr_imm16_asmoperand : shr_imm_asmoperands<"16">;
1479 def shr_imm32_asmoperand : shr_imm_asmoperands<"32">;
1480 def shr_imm64_asmoperand : shr_imm_asmoperands<"64">;
1481
1482 def shr_imm8 : shr_imm<"8">;
1483 def shr_imm16 : shr_imm<"16">;
1484 def shr_imm32 : shr_imm<"32">;
1485 def shr_imm64 : shr_imm<"64">;
1486
1487 class shl_imm_asmoperands<string OFFSET> : AsmOperandClass {
1488   let Name = "ShlImm" # OFFSET;
1489   let RenderMethod = "addImmOperands";
1490   let DiagnosticType = "ShlImm" # OFFSET;
1491 }
1492
1493 class shl_imm<string OFFSET> : Operand<i32> {
1494   let EncoderMethod = "getShiftLeftImm" # OFFSET;
1495   let DecoderMethod = "DecodeShiftLeftImm" # OFFSET;
1496   let ParserMatchClass =
1497     !cast<AsmOperandClass>("shl_imm" # OFFSET # "_asmoperand");
1498 }
1499
1500 def shl_imm8_asmoperand : shl_imm_asmoperands<"8">;
1501 def shl_imm16_asmoperand : shl_imm_asmoperands<"16">;
1502 def shl_imm32_asmoperand : shl_imm_asmoperands<"32">;
1503 def shl_imm64_asmoperand : shl_imm_asmoperands<"64">;
1504
1505 def shl_imm8 : shl_imm<"8">;
1506 def shl_imm16 : shl_imm<"16">;
1507 def shl_imm32 : shl_imm<"32">;
1508 def shl_imm64 : shl_imm<"64">;
1509
1510 class N2VShift<bit q, bit u, bits<5> opcode, string asmop, string T,
1511                RegisterOperand VPRC, ValueType Ty, Operand ImmTy, SDNode OpNode>
1512   : NeonI_2VShiftImm<q, u, opcode,
1513                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1514                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1515                      [(set (Ty VPRC:$Rd),
1516                         (Ty (OpNode (Ty VPRC:$Rn),
1517                           (Ty (Neon_vdup (i32 imm:$Imm))))))],
1518                      NoItinerary>;
1519
1520 multiclass NeonI_N2VShL<bit u, bits<5> opcode, string asmop> {
1521   // 64-bit vector types.
1522   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3, shl> {
1523     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1524   }
1525
1526   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4, shl> {
1527     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1528   }
1529
1530   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5, shl> {
1531     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1532   }
1533
1534   // 128-bit vector types.
1535   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3, shl> {
1536     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1537   }
1538
1539   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4, shl> {
1540     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1541   }
1542
1543   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5, shl> {
1544     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1545   }
1546
1547   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63, shl> {
1548     let Inst{22} = 0b1;        // immh:immb = 1xxxxxx
1549   }
1550 }
1551
1552 multiclass NeonI_N2VShR<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1553   def _8B : N2VShift<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1554                      OpNode> {
1555     let Inst{22-19} = 0b0001;
1556   }
1557
1558   def _4H : N2VShift<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1559                      OpNode> {
1560     let Inst{22-20} = 0b001;
1561   }
1562
1563   def _2S : N2VShift<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1564                      OpNode> {
1565      let Inst{22-21} = 0b01;
1566   }
1567
1568   def _16B : N2VShift<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1569                       OpNode> {
1570                       let Inst{22-19} = 0b0001;
1571                     }
1572
1573   def _8H : N2VShift<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1574                      OpNode> {
1575                      let Inst{22-20} = 0b001;
1576                     }
1577
1578   def _4S : N2VShift<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1579                      OpNode> {
1580                       let Inst{22-21} = 0b01;
1581                     }
1582
1583   def _2D : N2VShift<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1584                      OpNode> {
1585                       let Inst{22} = 0b1;
1586                     }
1587 }
1588
1589 // Shift left
1590 defm SHLvvi : NeonI_N2VShL<0b0, 0b01010, "shl">;
1591
1592 // Shift right
1593 defm SSHRvvi : NeonI_N2VShR<0b0, 0b00000, "sshr", sra>;
1594 defm USHRvvi : NeonI_N2VShR<0b1, 0b00000, "ushr", srl>;
1595
1596 def Neon_High16B : PatFrag<(ops node:$in),
1597                            (extract_subvector (v16i8 node:$in), (iPTR 8))>;
1598 def Neon_High8H  : PatFrag<(ops node:$in),
1599                            (extract_subvector (v8i16 node:$in), (iPTR 4))>;
1600 def Neon_High4S  : PatFrag<(ops node:$in),
1601                            (extract_subvector (v4i32 node:$in), (iPTR 2))>;
1602
1603 def Neon_low8H : PatFrag<(ops node:$in),
1604                          (v4i16 (extract_subvector (v8i16 node:$in),
1605                                                    (iPTR 0)))>;
1606 def Neon_low4S : PatFrag<(ops node:$in),
1607                          (v2i32 (extract_subvector (v4i32 node:$in),
1608                                                    (iPTR 0)))>;
1609 def Neon_low4f : PatFrag<(ops node:$in),
1610                          (v2f32 (extract_subvector (v4f32 node:$in),
1611                                                    (iPTR 0)))>;
1612
1613 class N2VShiftLong<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1614                    string SrcT, ValueType DestTy, ValueType SrcTy,
1615                    Operand ImmTy, SDPatternOperator ExtOp>
1616   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1617                      (ins VPR64:$Rn, ImmTy:$Imm),
1618                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1619                      [(set (DestTy VPR128:$Rd),
1620                         (DestTy (shl
1621                           (DestTy (ExtOp (SrcTy VPR64:$Rn))),
1622                             (DestTy (Neon_vdup (i32 imm:$Imm))))))],
1623                      NoItinerary>;
1624
1625 class N2VShiftLongHigh<bit q, bit u, bits<5> opcode, string asmop, string DestT,
1626                        string SrcT, ValueType DestTy, ValueType SrcTy,
1627                        int StartIndex, Operand ImmTy,
1628                        SDPatternOperator ExtOp, PatFrag getTop>
1629   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
1630                      (ins VPR128:$Rn, ImmTy:$Imm),
1631                      asmop # "2\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
1632                      [(set (DestTy VPR128:$Rd),
1633                         (DestTy (shl
1634                           (DestTy (ExtOp
1635                             (SrcTy (getTop VPR128:$Rn)))),
1636                               (DestTy (Neon_vdup (i32 imm:$Imm))))))],
1637                      NoItinerary>;
1638
1639 multiclass NeonI_N2VShLL<string prefix, bit u, bits<5> opcode, string asmop,
1640                          SDNode ExtOp> {
1641   // 64-bit vector types.
1642   def _8B : N2VShiftLong<0b0, u, opcode, asmop, "8h", "8b", v8i16, v8i8,
1643                          uimm3, ExtOp> {
1644     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1645   }
1646
1647   def _4H : N2VShiftLong<0b0, u, opcode, asmop, "4s", "4h", v4i32, v4i16,
1648                          uimm4, ExtOp> {
1649     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1650   }
1651
1652   def _2S : N2VShiftLong<0b0, u, opcode, asmop, "2d", "2s", v2i64, v2i32,
1653                          uimm5, ExtOp> {
1654     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1655   }
1656
1657   // 128-bit vector types
1658   def _16B : N2VShiftLongHigh<0b1, u, opcode, asmop, "8h", "16b",
1659                               v8i16, v8i8, 8, uimm3, ExtOp, Neon_High16B> {
1660     let Inst{22-19} = 0b0001;  // immh:immb = 0001xxx
1661   }
1662
1663   def _8H : N2VShiftLongHigh<0b1, u, opcode, asmop, "4s", "8h",
1664                              v4i32, v4i16, 4, uimm4, ExtOp, Neon_High8H> {
1665     let Inst{22-20} = 0b001;   // immh:immb = 001xxxx
1666   }
1667
1668   def _4S : N2VShiftLongHigh<0b1, u, opcode, asmop, "2d", "4s",
1669                              v2i64, v2i32, 2, uimm5, ExtOp, Neon_High4S> {
1670     let Inst{22-21} = 0b01;    // immh:immb = 01xxxxx
1671   }
1672
1673   // Use other patterns to match when the immediate is 0.
1674   def : Pat<(v8i16 (ExtOp (v8i8 VPR64:$Rn))),
1675             (!cast<Instruction>(prefix # "_8B") VPR64:$Rn, 0)>;
1676
1677   def : Pat<(v4i32 (ExtOp (v4i16 VPR64:$Rn))),
1678             (!cast<Instruction>(prefix # "_4H") VPR64:$Rn, 0)>;
1679
1680   def : Pat<(v2i64 (ExtOp (v2i32 VPR64:$Rn))),
1681             (!cast<Instruction>(prefix # "_2S") VPR64:$Rn, 0)>;
1682
1683   def : Pat<(v8i16 (ExtOp (v8i8 (Neon_High16B VPR128:$Rn)))),
1684             (!cast<Instruction>(prefix # "_16B") VPR128:$Rn, 0)>;
1685
1686   def : Pat<(v4i32 (ExtOp (v4i16 (Neon_High8H VPR128:$Rn)))),
1687             (!cast<Instruction>(prefix # "_8H") VPR128:$Rn, 0)>;
1688
1689   def : Pat<(v2i64 (ExtOp (v2i32 (Neon_High4S VPR128:$Rn)))),
1690             (!cast<Instruction>(prefix # "_4S") VPR128:$Rn, 0)>;
1691 }
1692
1693 // Shift left long
1694 defm SSHLLvvi : NeonI_N2VShLL<"SSHLLvvi", 0b0, 0b10100, "sshll", sext>;
1695 defm USHLLvvi : NeonI_N2VShLL<"USHLLvvi", 0b1, 0b10100, "ushll", zext>;
1696
1697 // Rounding/Saturating shift
1698 class N2VShift_RQ<bit q, bit u, bits<5> opcode, string asmop, string T,
1699                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1700                   SDPatternOperator OpNode>
1701   : NeonI_2VShiftImm<q, u, opcode,
1702                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
1703                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1704                      [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$Rn),
1705                         (i32 imm:$Imm))))],
1706                      NoItinerary>;
1707
1708 // shift right (vector by immediate)
1709 multiclass NeonI_N2VShR_RQ<bit u, bits<5> opcode, string asmop,
1710                            SDPatternOperator OpNode> {
1711   def _8B  : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1712                          OpNode> {
1713     let Inst{22-19} = 0b0001;
1714   }
1715
1716   def _4H  : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1717                          OpNode> {
1718     let Inst{22-20} = 0b001;
1719   }
1720
1721   def _2S  : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1722                          OpNode> {
1723     let Inst{22-21} = 0b01;
1724   }
1725
1726   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1727                          OpNode> {
1728     let Inst{22-19} = 0b0001;
1729   }
1730
1731   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1732                         OpNode> {
1733     let Inst{22-20} = 0b001;
1734   }
1735
1736   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1737                         OpNode> {
1738     let Inst{22-21} = 0b01;
1739   }
1740
1741   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1742                         OpNode> {
1743     let Inst{22} = 0b1;
1744   }
1745 }
1746
1747 multiclass NeonI_N2VShL_Q<bit u, bits<5> opcode, string asmop,
1748                           SDPatternOperator OpNode> {
1749   // 64-bit vector types.
1750   def _8B : N2VShift_RQ<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1751                         OpNode> {
1752     let Inst{22-19} = 0b0001;
1753   }
1754
1755   def _4H : N2VShift_RQ<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1756                         OpNode> {
1757     let Inst{22-20} = 0b001;
1758   }
1759
1760   def _2S : N2VShift_RQ<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1761                         OpNode> {
1762     let Inst{22-21} = 0b01;
1763   }
1764
1765   // 128-bit vector types.
1766   def _16B : N2VShift_RQ<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1767                          OpNode> {
1768     let Inst{22-19} = 0b0001;
1769   }
1770
1771   def _8H : N2VShift_RQ<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1772                         OpNode> {
1773     let Inst{22-20} = 0b001;
1774   }
1775
1776   def _4S : N2VShift_RQ<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1777                         OpNode> {
1778     let Inst{22-21} = 0b01;
1779   }
1780
1781   def _2D : N2VShift_RQ<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1782                         OpNode> {
1783     let Inst{22} = 0b1;
1784   }
1785 }
1786
1787 // Rounding shift right
1788 defm SRSHRvvi : NeonI_N2VShR_RQ<0b0, 0b00100, "srshr",
1789                                 int_aarch64_neon_vsrshr>;
1790 defm URSHRvvi : NeonI_N2VShR_RQ<0b1, 0b00100, "urshr",
1791                                 int_aarch64_neon_vurshr>;
1792
1793 // Saturating shift left unsigned
1794 defm SQSHLUvvi : NeonI_N2VShL_Q<0b1, 0b01100, "sqshlu", int_aarch64_neon_vsqshlu>;
1795
1796 // Saturating shift left
1797 defm SQSHLvvi : NeonI_N2VShL_Q<0b0, 0b01110, "sqshl", Neon_sqrshlImm>;
1798 defm UQSHLvvi : NeonI_N2VShL_Q<0b1, 0b01110, "uqshl", Neon_uqrshlImm>;
1799
1800 class N2VShiftAdd<bit q, bit u, bits<5> opcode, string asmop, string T,
1801                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1802                   SDNode OpNode>
1803   : NeonI_2VShiftImm<q, u, opcode,
1804            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1805            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1806            [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1807               (Ty (OpNode (Ty VPRC:$Rn),
1808                 (Ty (Neon_vdup (i32 imm:$Imm))))))))],
1809            NoItinerary> {
1810   let Constraints = "$src = $Rd";
1811 }
1812
1813 // Shift Right accumulate
1814 multiclass NeonI_N2VShRAdd<bit u, bits<5> opcode, string asmop, SDNode OpNode> {
1815   def _8B : N2VShiftAdd<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1816                         OpNode> {
1817     let Inst{22-19} = 0b0001;
1818   }
1819
1820   def _4H : N2VShiftAdd<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1821                         OpNode> {
1822     let Inst{22-20} = 0b001;
1823   }
1824
1825   def _2S : N2VShiftAdd<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1826                         OpNode> {
1827     let Inst{22-21} = 0b01;
1828   }
1829
1830   def _16B : N2VShiftAdd<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1831                          OpNode> {
1832     let Inst{22-19} = 0b0001;
1833   }
1834
1835   def _8H : N2VShiftAdd<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1836                         OpNode> {
1837     let Inst{22-20} = 0b001;
1838   }
1839
1840   def _4S : N2VShiftAdd<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1841                         OpNode> {
1842     let Inst{22-21} = 0b01;
1843   }
1844
1845   def _2D : N2VShiftAdd<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1846                         OpNode> {
1847     let Inst{22} = 0b1;
1848   }
1849 }
1850
1851 // Shift right and accumulate
1852 defm SSRAvvi    : NeonI_N2VShRAdd<0, 0b00010, "ssra", sra>;
1853 defm USRAvvi    : NeonI_N2VShRAdd<1, 0b00010, "usra", srl>;
1854
1855 // Rounding shift accumulate
1856 class N2VShiftAdd_R<bit q, bit u, bits<5> opcode, string asmop, string T,
1857                     RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1858                     SDPatternOperator OpNode>
1859   : NeonI_2VShiftImm<q, u, opcode,
1860                      (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1861                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1862                      [(set (Ty VPRC:$Rd), (Ty (add (Ty VPRC:$src),
1863                         (Ty (OpNode (Ty VPRC:$Rn), (i32 imm:$Imm))))))],
1864                      NoItinerary> {
1865   let Constraints = "$src = $Rd";
1866 }
1867
1868 multiclass NeonI_N2VShRAdd_R<bit u, bits<5> opcode, string asmop,
1869                              SDPatternOperator OpNode> {
1870   def _8B : N2VShiftAdd_R<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1871                           OpNode> {
1872     let Inst{22-19} = 0b0001;
1873   }
1874
1875   def _4H : N2VShiftAdd_R<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1876                           OpNode> {
1877     let Inst{22-20} = 0b001;
1878   }
1879
1880   def _2S : N2VShiftAdd_R<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1881                           OpNode> {
1882     let Inst{22-21} = 0b01;
1883   }
1884
1885   def _16B : N2VShiftAdd_R<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1886                            OpNode> {
1887     let Inst{22-19} = 0b0001;
1888   }
1889
1890   def _8H : N2VShiftAdd_R<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1891                           OpNode> {
1892     let Inst{22-20} = 0b001;
1893   }
1894
1895   def _4S : N2VShiftAdd_R<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1896                           OpNode> {
1897     let Inst{22-21} = 0b01;
1898   }
1899
1900   def _2D : N2VShiftAdd_R<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1901                           OpNode> {
1902     let Inst{22} = 0b1;
1903   }
1904 }
1905
1906 // Rounding shift right and accumulate
1907 defm SRSRAvvi : NeonI_N2VShRAdd_R<0, 0b00110, "srsra", int_aarch64_neon_vsrshr>;
1908 defm URSRAvvi : NeonI_N2VShRAdd_R<1, 0b00110, "ursra", int_aarch64_neon_vurshr>;
1909
1910 // Shift insert by immediate
1911 class N2VShiftIns<bit q, bit u, bits<5> opcode, string asmop, string T,
1912                   RegisterOperand VPRC, ValueType Ty, Operand ImmTy,
1913                   SDPatternOperator OpNode>
1914     : NeonI_2VShiftImm<q, u, opcode,
1915            (outs VPRC:$Rd), (ins VPRC:$src, VPRC:$Rn, ImmTy:$Imm),
1916            asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
1917            [(set (Ty VPRC:$Rd), (Ty (OpNode (Ty VPRC:$src), (Ty VPRC:$Rn),
1918              (i32 imm:$Imm))))],
1919            NoItinerary> {
1920   let Constraints = "$src = $Rd";
1921 }
1922
1923 // shift left insert (vector by immediate)
1924 multiclass NeonI_N2VShLIns<bit u, bits<5> opcode, string asmop> {
1925   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, uimm3,
1926                         int_aarch64_neon_vsli> {
1927     let Inst{22-19} = 0b0001;
1928   }
1929
1930   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, uimm4,
1931                         int_aarch64_neon_vsli> {
1932     let Inst{22-20} = 0b001;
1933   }
1934
1935   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, uimm5,
1936                         int_aarch64_neon_vsli> {
1937     let Inst{22-21} = 0b01;
1938   }
1939
1940     // 128-bit vector types
1941   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, uimm3,
1942                          int_aarch64_neon_vsli> {
1943     let Inst{22-19} = 0b0001;
1944   }
1945
1946   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, uimm4,
1947                         int_aarch64_neon_vsli> {
1948     let Inst{22-20} = 0b001;
1949   }
1950
1951   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, uimm5,
1952                         int_aarch64_neon_vsli> {
1953     let Inst{22-21} = 0b01;
1954   }
1955
1956   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, imm0_63,
1957                         int_aarch64_neon_vsli> {
1958     let Inst{22} = 0b1;
1959   }
1960 }
1961
1962 // shift right insert (vector by immediate)
1963 multiclass NeonI_N2VShRIns<bit u, bits<5> opcode, string asmop> {
1964     // 64-bit vector types.
1965   def _8B : N2VShiftIns<0b0, u, opcode, asmop, "8b", VPR64, v8i8, shr_imm8,
1966                         int_aarch64_neon_vsri> {
1967     let Inst{22-19} = 0b0001;
1968   }
1969
1970   def _4H : N2VShiftIns<0b0, u, opcode, asmop, "4h", VPR64, v4i16, shr_imm16,
1971                         int_aarch64_neon_vsri> {
1972     let Inst{22-20} = 0b001;
1973   }
1974
1975   def _2S : N2VShiftIns<0b0, u, opcode, asmop, "2s", VPR64, v2i32, shr_imm32,
1976                         int_aarch64_neon_vsri> {
1977     let Inst{22-21} = 0b01;
1978   }
1979
1980     // 128-bit vector types
1981   def _16B : N2VShiftIns<0b1, u, opcode, asmop, "16b", VPR128, v16i8, shr_imm8,
1982                          int_aarch64_neon_vsri> {
1983     let Inst{22-19} = 0b0001;
1984   }
1985
1986   def _8H : N2VShiftIns<0b1, u, opcode, asmop, "8h", VPR128, v8i16, shr_imm16,
1987                         int_aarch64_neon_vsri> {
1988     let Inst{22-20} = 0b001;
1989   }
1990
1991   def _4S : N2VShiftIns<0b1, u, opcode, asmop, "4s", VPR128, v4i32, shr_imm32,
1992                         int_aarch64_neon_vsri> {
1993     let Inst{22-21} = 0b01;
1994   }
1995
1996   def _2D : N2VShiftIns<0b1, u, opcode, asmop, "2d", VPR128, v2i64, shr_imm64,
1997                         int_aarch64_neon_vsri> {
1998     let Inst{22} = 0b1;
1999   }
2000 }
2001
2002 // Shift left and insert
2003 defm SLIvvi   : NeonI_N2VShLIns<0b1, 0b01010, "sli">;
2004
2005 // Shift right and insert
2006 defm SRIvvi   : NeonI_N2VShRIns<0b1, 0b01000, "sri">;
2007
2008 class N2VShR_Narrow<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2009                     string SrcT, Operand ImmTy>
2010   : NeonI_2VShiftImm<q, u, opcode,
2011                      (outs VPR64:$Rd), (ins VPR128:$Rn, ImmTy:$Imm),
2012                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2013                      [], NoItinerary>;
2014
2015 class N2VShR_Narrow_Hi<bit q, bit u, bits<5> opcode, string asmop, string DestT,
2016                        string SrcT, Operand ImmTy>
2017   : NeonI_2VShiftImm<q, u, opcode, (outs VPR128:$Rd),
2018                      (ins VPR128:$src, VPR128:$Rn, ImmTy:$Imm),
2019                      asmop # "\t$Rd." # DestT # ", $Rn." # SrcT # ", $Imm",
2020                      [], NoItinerary> {
2021   let Constraints = "$src = $Rd";
2022 }
2023
2024 // left long shift by immediate
2025 multiclass NeonI_N2VShR_Narrow<bit u, bits<5> opcode, string asmop> {
2026   def _8B : N2VShR_Narrow<0b0, u, opcode, asmop, "8b", "8h", shr_imm8> {
2027     let Inst{22-19} = 0b0001;
2028   }
2029
2030   def _4H : N2VShR_Narrow<0b0, u, opcode, asmop, "4h", "4s", shr_imm16> {
2031     let Inst{22-20} = 0b001;
2032   }
2033
2034   def _2S : N2VShR_Narrow<0b0, u, opcode, asmop, "2s", "2d", shr_imm32> {
2035     let Inst{22-21} = 0b01;
2036   }
2037
2038   // Shift Narrow High
2039   def _16B : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "16b", "8h",
2040                               shr_imm8> {
2041     let Inst{22-19} = 0b0001;
2042   }
2043
2044   def _8H : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "8h", "4s",
2045                              shr_imm16> {
2046     let Inst{22-20} = 0b001;
2047   }
2048
2049   def _4S : N2VShR_Narrow_Hi<0b1, u, opcode, asmop # "2", "4s", "2d",
2050                              shr_imm32> {
2051     let Inst{22-21} = 0b01;
2052   }
2053 }
2054
2055 // Shift right narrow
2056 defm SHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10000, "shrn">;
2057
2058 // Shift right narrow (prefix Q is saturating, prefix R is rounding)
2059 defm QSHRUNvvi :NeonI_N2VShR_Narrow<0b1, 0b10000, "sqshrun">;
2060 defm RSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10001, "rshrn">;
2061 defm QRSHRUNvvi : NeonI_N2VShR_Narrow<0b1, 0b10001, "sqrshrun">;
2062 defm SQSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10010, "sqshrn">;
2063 defm UQSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10010, "uqshrn">;
2064 defm SQRSHRNvvi : NeonI_N2VShR_Narrow<0b0, 0b10011, "sqrshrn">;
2065 defm UQRSHRNvvi : NeonI_N2VShR_Narrow<0b1, 0b10011, "uqrshrn">;
2066
2067 def Neon_combine_2D : PatFrag<(ops node:$Rm, node:$Rn),
2068                               (v2i64 (concat_vectors (v1i64 node:$Rm),
2069                                                      (v1i64 node:$Rn)))>;
2070 def Neon_combine_8H : PatFrag<(ops node:$Rm, node:$Rn),
2071                               (v8i16 (concat_vectors (v4i16 node:$Rm),
2072                                                      (v4i16 node:$Rn)))>;
2073 def Neon_combine_4S : PatFrag<(ops node:$Rm, node:$Rn),
2074                               (v4i32 (concat_vectors (v2i32 node:$Rm),
2075                                                      (v2i32 node:$Rn)))>;
2076 def Neon_combine_4f : PatFrag<(ops node:$Rm, node:$Rn),
2077                               (v4f32 (concat_vectors (v2f32 node:$Rm),
2078                                                      (v2f32 node:$Rn)))>;
2079 def Neon_combine_2d : PatFrag<(ops node:$Rm, node:$Rn),
2080                               (v2f64 (concat_vectors (v1f64 node:$Rm),
2081                                                      (v1f64 node:$Rn)))>;
2082
2083 def Neon_lshrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2084                              (v8i16 (srl (v8i16 node:$lhs),
2085                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2086 def Neon_lshrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2087                              (v4i32 (srl (v4i32 node:$lhs),
2088                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2089 def Neon_lshrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2090                              (v2i64 (srl (v2i64 node:$lhs),
2091                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2092 def Neon_ashrImm8H : PatFrag<(ops node:$lhs, node:$rhs),
2093                              (v8i16 (sra (v8i16 node:$lhs),
2094                                (v8i16 (Neon_vdup (i32 node:$rhs)))))>;
2095 def Neon_ashrImm4S : PatFrag<(ops node:$lhs, node:$rhs),
2096                              (v4i32 (sra (v4i32 node:$lhs),
2097                                (v4i32 (Neon_vdup (i32 node:$rhs)))))>;
2098 def Neon_ashrImm2D : PatFrag<(ops node:$lhs, node:$rhs),
2099                              (v2i64 (sra (v2i64 node:$lhs),
2100                                (v2i64 (Neon_vdup (i32 node:$rhs)))))>;
2101
2102 // Normal shift right narrow is matched by IR (srl/sra, trunc, concat_vectors)
2103 multiclass Neon_shiftNarrow_patterns<string shr> {
2104   def : Pat<(v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H") VPR128:$Rn,
2105               (i32 imm:$Imm)))),
2106             (SHRNvvi_8B VPR128:$Rn, imm:$Imm)>;
2107   def : Pat<(v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S") VPR128:$Rn,
2108               (i32 imm:$Imm)))),
2109             (SHRNvvi_4H VPR128:$Rn, imm:$Imm)>;
2110   def : Pat<(v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D") VPR128:$Rn,
2111               (i32 imm:$Imm)))),
2112             (SHRNvvi_2S VPR128:$Rn, imm:$Imm)>;
2113
2114   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2115               (v8i8 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm8H")
2116                 VPR128:$Rn, (i32 imm:$Imm))))))),
2117             (SHRNvvi_16B (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
2118                          VPR128:$Rn, imm:$Imm)>;
2119   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2120               (v4i16 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm4S")
2121                 VPR128:$Rn, (i32 imm:$Imm))))))),
2122             (SHRNvvi_8H (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2123                         VPR128:$Rn, imm:$Imm)>;
2124   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src), (v1i64 (bitconvert
2125               (v2i32 (trunc (!cast<PatFrag>("Neon_" # shr # "Imm2D")
2126                 VPR128:$Rn, (i32 imm:$Imm))))))),
2127             (SHRNvvi_4S (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2128                         VPR128:$Rn, imm:$Imm)>;
2129 }
2130
2131 multiclass Neon_shiftNarrow_QR_patterns<SDPatternOperator op, string prefix> {
2132   def : Pat<(v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm)),
2133             (!cast<Instruction>(prefix # "_8B") VPR128:$Rn, imm:$Imm)>;
2134   def : Pat<(v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm)),
2135             (!cast<Instruction>(prefix # "_4H") VPR128:$Rn, imm:$Imm)>;
2136   def : Pat<(v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm)),
2137             (!cast<Instruction>(prefix # "_2S") VPR128:$Rn, imm:$Imm)>;
2138
2139   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2140                 (v1i64 (bitconvert (v8i8 (op (v8i16 VPR128:$Rn), imm:$Imm))))),
2141             (!cast<Instruction>(prefix # "_16B")
2142                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2143                 VPR128:$Rn, imm:$Imm)>;
2144   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2145                 (v1i64 (bitconvert (v4i16 (op (v4i32 VPR128:$Rn), imm:$Imm))))),
2146             (!cast<Instruction>(prefix # "_8H")
2147                 (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2148                 VPR128:$Rn, imm:$Imm)>;
2149   def : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2150                 (v1i64 (bitconvert (v2i32 (op (v2i64 VPR128:$Rn), imm:$Imm))))),
2151             (!cast<Instruction>(prefix # "_4S")
2152                   (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2153                   VPR128:$Rn, imm:$Imm)>;
2154 }
2155
2156 defm : Neon_shiftNarrow_patterns<"lshr">;
2157 defm : Neon_shiftNarrow_patterns<"ashr">;
2158
2159 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrun, "QSHRUNvvi">;
2160 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vrshrn, "RSHRNvvi">;
2161 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrun, "QRSHRUNvvi">;
2162 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqshrn, "SQSHRNvvi">;
2163 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqshrn, "UQSHRNvvi">;
2164 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vsqrshrn, "SQRSHRNvvi">;
2165 defm : Neon_shiftNarrow_QR_patterns<int_aarch64_neon_vuqrshrn, "UQRSHRNvvi">;
2166
2167 // Convert fix-point and float-pointing
2168 class N2VCvt_Fx<bit q, bit u, bits<5> opcode, string asmop, string T,
2169                 RegisterOperand VPRC, ValueType DestTy, ValueType SrcTy,
2170                 Operand ImmTy, SDPatternOperator IntOp>
2171   : NeonI_2VShiftImm<q, u, opcode,
2172                      (outs VPRC:$Rd), (ins VPRC:$Rn, ImmTy:$Imm),
2173                      asmop # "\t$Rd." # T # ", $Rn." # T # ", $Imm",
2174                      [(set (DestTy VPRC:$Rd), (DestTy (IntOp (SrcTy VPRC:$Rn),
2175                        (i32 imm:$Imm))))],
2176                      NoItinerary>;
2177
2178 multiclass NeonI_N2VCvt_Fx2fp<bit u, bits<5> opcode, string asmop,
2179                               SDPatternOperator IntOp> {
2180   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2f32, v2i32,
2181                       shr_imm32, IntOp> {
2182     let Inst{22-21} = 0b01;
2183   }
2184
2185   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4f32, v4i32,
2186                       shr_imm32, IntOp> {
2187     let Inst{22-21} = 0b01;
2188   }
2189
2190   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2f64, v2i64,
2191                       shr_imm64, IntOp> {
2192     let Inst{22} = 0b1;
2193   }
2194 }
2195
2196 multiclass NeonI_N2VCvt_Fp2fx<bit u, bits<5> opcode, string asmop,
2197                               SDPatternOperator IntOp> {
2198   def _2S : N2VCvt_Fx<0, u, opcode, asmop, "2s", VPR64, v2i32, v2f32,
2199                       shr_imm32, IntOp> {
2200     let Inst{22-21} = 0b01;
2201   }
2202
2203   def _4S : N2VCvt_Fx<1, u, opcode, asmop, "4s", VPR128, v4i32, v4f32,
2204                       shr_imm32, IntOp> {
2205     let Inst{22-21} = 0b01;
2206   }
2207
2208   def _2D : N2VCvt_Fx<1, u, opcode, asmop, "2d", VPR128, v2i64, v2f64,
2209                       shr_imm64, IntOp> {
2210     let Inst{22} = 0b1;
2211   }
2212 }
2213
2214 // Convert fixed-point to floating-point
2215 defm VCVTxs2f : NeonI_N2VCvt_Fx2fp<0, 0b11100, "scvtf",
2216                                    int_arm_neon_vcvtfxs2fp>;
2217 defm VCVTxu2f : NeonI_N2VCvt_Fx2fp<1, 0b11100, "ucvtf",
2218                                    int_arm_neon_vcvtfxu2fp>;
2219
2220 // Convert floating-point to fixed-point
2221 defm VCVTf2xs : NeonI_N2VCvt_Fp2fx<0, 0b11111, "fcvtzs",
2222                                    int_arm_neon_vcvtfp2fxs>;
2223 defm VCVTf2xu : NeonI_N2VCvt_Fp2fx<1, 0b11111, "fcvtzu",
2224                                    int_arm_neon_vcvtfp2fxu>;
2225
2226 multiclass Neon_sshll2_0<SDNode ext>
2227 {
2228   def _v8i8  : PatFrag<(ops node:$Rn),
2229                        (v8i16 (ext (v8i8 (Neon_High16B node:$Rn))))>;
2230   def _v4i16 : PatFrag<(ops node:$Rn),
2231                        (v4i32 (ext (v4i16 (Neon_High8H node:$Rn))))>;
2232   def _v2i32 : PatFrag<(ops node:$Rn),
2233                        (v2i64 (ext (v2i32 (Neon_High4S node:$Rn))))>;
2234 }
2235
2236 defm NI_sext_high : Neon_sshll2_0<sext>;
2237 defm NI_zext_high : Neon_sshll2_0<zext>;
2238
2239
2240 //===----------------------------------------------------------------------===//
2241 // Multiclasses for NeonI_Across
2242 //===----------------------------------------------------------------------===//
2243
2244 // Variant 1
2245
2246 multiclass NeonI_2VAcross_1<bit u, bits<5> opcode,
2247                             string asmop, SDPatternOperator opnode>
2248 {
2249     def _1h8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2250                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2251                 asmop # "\t$Rd, $Rn.8b",
2252                 [(set (v1i16 FPR16:$Rd),
2253                     (v1i16 (opnode (v8i8 VPR64:$Rn))))],
2254                 NoItinerary>;
2255
2256     def _1h16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2257                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2258                 asmop # "\t$Rd, $Rn.16b",
2259                 [(set (v1i16 FPR16:$Rd),
2260                     (v1i16 (opnode (v16i8 VPR128:$Rn))))],
2261                 NoItinerary>;
2262
2263     def _1s4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2264                 (outs FPR32:$Rd), (ins VPR64:$Rn),
2265                 asmop # "\t$Rd, $Rn.4h",
2266                 [(set (v1i32 FPR32:$Rd),
2267                     (v1i32 (opnode (v4i16 VPR64:$Rn))))],
2268                 NoItinerary>;
2269
2270     def _1s8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2271                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2272                 asmop # "\t$Rd, $Rn.8h",
2273                 [(set (v1i32 FPR32:$Rd),
2274                     (v1i32 (opnode (v8i16 VPR128:$Rn))))],
2275                 NoItinerary>;
2276
2277     // _1d2s doesn't exist!
2278
2279     def _1d4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2280                 (outs FPR64:$Rd), (ins VPR128:$Rn),
2281                 asmop # "\t$Rd, $Rn.4s",
2282                 [(set (v1i64 FPR64:$Rd),
2283                     (v1i64 (opnode (v4i32 VPR128:$Rn))))],
2284                 NoItinerary>;
2285 }
2286
2287 defm SADDLV : NeonI_2VAcross_1<0b0, 0b00011, "saddlv", int_aarch64_neon_saddlv>;
2288 defm UADDLV : NeonI_2VAcross_1<0b1, 0b00011, "uaddlv", int_aarch64_neon_uaddlv>;
2289
2290 // Variant 2
2291
2292 multiclass NeonI_2VAcross_2<bit u, bits<5> opcode,
2293                             string asmop, SDPatternOperator opnode>
2294 {
2295     def _1b8b:  NeonI_2VAcross<0b0, u, 0b00, opcode,
2296                 (outs FPR8:$Rd), (ins VPR64:$Rn),
2297                 asmop # "\t$Rd, $Rn.8b",
2298                 [(set (v1i8 FPR8:$Rd),
2299                     (v1i8 (opnode (v8i8 VPR64:$Rn))))],
2300                 NoItinerary>;
2301
2302     def _1b16b: NeonI_2VAcross<0b1, u, 0b00, opcode,
2303                 (outs FPR8:$Rd), (ins VPR128:$Rn),
2304                 asmop # "\t$Rd, $Rn.16b",
2305                 [(set (v1i8 FPR8:$Rd),
2306                     (v1i8 (opnode (v16i8 VPR128:$Rn))))],
2307                 NoItinerary>;
2308
2309     def _1h4h:  NeonI_2VAcross<0b0, u, 0b01, opcode,
2310                 (outs FPR16:$Rd), (ins VPR64:$Rn),
2311                 asmop # "\t$Rd, $Rn.4h",
2312                 [(set (v1i16 FPR16:$Rd),
2313                     (v1i16 (opnode (v4i16 VPR64:$Rn))))],
2314                 NoItinerary>;
2315
2316     def _1h8h:  NeonI_2VAcross<0b1, u, 0b01, opcode,
2317                 (outs FPR16:$Rd), (ins VPR128:$Rn),
2318                 asmop # "\t$Rd, $Rn.8h",
2319                 [(set (v1i16 FPR16:$Rd),
2320                     (v1i16 (opnode (v8i16 VPR128:$Rn))))],
2321                 NoItinerary>;
2322
2323     // _1s2s doesn't exist!
2324
2325     def _1s4s:  NeonI_2VAcross<0b1, u, 0b10, opcode,
2326                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2327                 asmop # "\t$Rd, $Rn.4s",
2328                 [(set (v1i32 FPR32:$Rd),
2329                     (v1i32 (opnode (v4i32 VPR128:$Rn))))],
2330                 NoItinerary>;
2331 }
2332
2333 defm SMAXV : NeonI_2VAcross_2<0b0, 0b01010, "smaxv", int_aarch64_neon_smaxv>;
2334 defm UMAXV : NeonI_2VAcross_2<0b1, 0b01010, "umaxv", int_aarch64_neon_umaxv>;
2335
2336 defm SMINV : NeonI_2VAcross_2<0b0, 0b11010, "sminv", int_aarch64_neon_sminv>;
2337 defm UMINV : NeonI_2VAcross_2<0b1, 0b11010, "uminv", int_aarch64_neon_uminv>;
2338
2339 defm ADDV : NeonI_2VAcross_2<0b0, 0b11011, "addv", int_aarch64_neon_vaddv>;
2340
2341 // Variant 3
2342
2343 multiclass NeonI_2VAcross_3<bit u, bits<5> opcode, bits<2> size,
2344                             string asmop, SDPatternOperator opnode> {
2345     def _1s4s:  NeonI_2VAcross<0b1, u, size, opcode,
2346                 (outs FPR32:$Rd), (ins VPR128:$Rn),
2347                 asmop # "\t$Rd, $Rn.4s",
2348                 [(set (v1f32 FPR32:$Rd),
2349                     (v1f32 (opnode (v4f32 VPR128:$Rn))))],
2350                 NoItinerary>;
2351 }
2352
2353 defm FMAXNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b00, "fmaxnmv",
2354                                 int_aarch64_neon_vmaxnmv>;
2355 defm FMINNMV : NeonI_2VAcross_3<0b1, 0b01100, 0b10, "fminnmv",
2356                                 int_aarch64_neon_vminnmv>;
2357
2358 defm FMAXV : NeonI_2VAcross_3<0b1, 0b01111, 0b00, "fmaxv",
2359                               int_aarch64_neon_vmaxv>;
2360 defm FMINV : NeonI_2VAcross_3<0b1, 0b01111, 0b10, "fminv",
2361                               int_aarch64_neon_vminv>;
2362
2363 // The followings are for instruction class (Perm)
2364
2365 class NeonI_Permute<bit q, bits<2> size, bits<3> opcode,
2366                     string asmop, RegisterOperand OpVPR, string OpS>
2367   : NeonI_Perm<q, size, opcode,
2368                (outs OpVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2369                asmop # "\t$Rd." # OpS # ", $Rn." # OpS # ", $Rm." # OpS,
2370                [], NoItinerary>;
2371
2372 multiclass NeonI_Perm_pat<bits<3> opcode, string asmop> {
2373    def _8b  : NeonI_Permute<0b0, 0b00, opcode, asmop, VPR64,  "8b">;
2374    def _16b : NeonI_Permute<0b1, 0b00, opcode, asmop, VPR128, "16b">;
2375    def _4h  : NeonI_Permute<0b0, 0b01, opcode, asmop, VPR64,  "4h">;
2376    def _8h  : NeonI_Permute<0b1, 0b01, opcode, asmop, VPR128, "8h">;
2377    def _2s  : NeonI_Permute<0b0, 0b10, opcode, asmop, VPR64,  "2s">;
2378    def _4s  : NeonI_Permute<0b1, 0b10, opcode, asmop, VPR128, "4s">;
2379    def _2d  : NeonI_Permute<0b1, 0b11, opcode, asmop, VPR128, "2d">;
2380 }
2381
2382 defm UZP1vvv : NeonI_Perm_pat<0b001, "uzp1">;
2383 defm TRN1vvv : NeonI_Perm_pat<0b010, "trn1">;
2384 defm ZIP1vvv : NeonI_Perm_pat<0b011, "zip1">;
2385 defm UZP2vvv : NeonI_Perm_pat<0b101, "uzp2">;
2386 defm TRN2vvv : NeonI_Perm_pat<0b110, "trn2">;
2387 defm ZIP2vvv : NeonI_Perm_pat<0b111, "zip2">;
2388
2389 // Extract and Insert
2390 def NI_ei_i32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
2391                         (vector_insert node:$Rn,
2392                           (i32 (vector_extract node:$Rm, node:$Ext)),
2393                           node:$Ins)>;
2394
2395 def NI_ei_f32 : PatFrag<(ops node:$Rn, node:$Rm, node:$Ext, node:$Ins),
2396                         (vector_insert node:$Rn,
2397                           (f32 (vector_extract node:$Rm, node:$Ext)),
2398                           node:$Ins)>;
2399
2400 // uzp1
2401 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2402           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2403           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2404           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2405           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2406           (v16i8 VPR128:$Rn),
2407           (v16i8 VPR128:$Rn), 2,  1)),
2408           (v16i8 VPR128:$Rn), 4,  2)),
2409           (v16i8 VPR128:$Rn), 6,  3)),
2410           (v16i8 VPR128:$Rn), 8,  4)),
2411           (v16i8 VPR128:$Rn), 10, 5)),
2412           (v16i8 VPR128:$Rn), 12, 6)),
2413           (v16i8 VPR128:$Rn), 14, 7)),
2414           (v16i8 VPR128:$Rm), 0,  8)),
2415           (v16i8 VPR128:$Rm), 2,  9)),
2416           (v16i8 VPR128:$Rm), 4,  10)),
2417           (v16i8 VPR128:$Rm), 6,  11)),
2418           (v16i8 VPR128:$Rm), 8,  12)),
2419           (v16i8 VPR128:$Rm), 10, 13)),
2420           (v16i8 VPR128:$Rm), 12, 14)),
2421           (v16i8 VPR128:$Rm), 14, 15)),
2422           (UZP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2423
2424 class NI_Uzp1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2425   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2426         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2427         (Ty VPR:$Rn),
2428         (Ty VPR:$Rn), 2, 1)),
2429         (Ty VPR:$Rn), 4, 2)),
2430         (Ty VPR:$Rn), 6, 3)),
2431         (Ty VPR:$Rm), 0, 4)),
2432         (Ty VPR:$Rm), 2, 5)),
2433         (Ty VPR:$Rm), 4, 6)),
2434         (Ty VPR:$Rm), 6, 7)),
2435         (INST VPR:$Rn, VPR:$Rm)>;
2436
2437 def : NI_Uzp1_v8<v8i8, VPR64, UZP1vvv_8b>;
2438 def : NI_Uzp1_v8<v8i16, VPR128, UZP1vvv_8h>;
2439
2440 class NI_Uzp1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2441                  PatFrag ei>
2442   : Pat<(Ty (ei (Ty (ei (Ty (ei
2443         (Ty VPR:$Rn),
2444         (Ty VPR:$Rn), 2, 1)),
2445         (Ty VPR:$Rm), 0, 2)),
2446         (Ty VPR:$Rm), 2, 3)),
2447         (INST VPR:$Rn, VPR:$Rm)>;
2448
2449 def : NI_Uzp1_v4<v4i16, VPR64, UZP1vvv_4h, NI_ei_i32>;
2450 def : NI_Uzp1_v4<v4i32, VPR128, UZP1vvv_4s, NI_ei_i32>;
2451 def : NI_Uzp1_v4<v4f32, VPR128, UZP1vvv_4s, NI_ei_f32>;
2452
2453 // uzp2
2454 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2455           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2456           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2457           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2458           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2459           (v16i8 VPR128:$Rm),
2460           (v16i8 VPR128:$Rn), 1,  0)),
2461           (v16i8 VPR128:$Rn), 3,  1)),
2462           (v16i8 VPR128:$Rn), 5,  2)),
2463           (v16i8 VPR128:$Rn), 7,  3)),
2464           (v16i8 VPR128:$Rn), 9,  4)),
2465           (v16i8 VPR128:$Rn), 11, 5)),
2466           (v16i8 VPR128:$Rn), 13, 6)),
2467           (v16i8 VPR128:$Rn), 15, 7)),
2468           (v16i8 VPR128:$Rm), 1,  8)),
2469           (v16i8 VPR128:$Rm), 3,  9)),
2470           (v16i8 VPR128:$Rm), 5,  10)),
2471           (v16i8 VPR128:$Rm), 7,  11)),
2472           (v16i8 VPR128:$Rm), 9,  12)),
2473           (v16i8 VPR128:$Rm), 11, 13)),
2474           (v16i8 VPR128:$Rm), 13, 14)),
2475           (UZP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2476
2477 class NI_Uzp2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2478   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2479         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2480         (Ty VPR:$Rm),
2481         (Ty VPR:$Rn), 1, 0)),
2482         (Ty VPR:$Rn), 3, 1)),
2483         (Ty VPR:$Rn), 5, 2)),
2484         (Ty VPR:$Rn), 7, 3)),
2485         (Ty VPR:$Rm), 1, 4)),
2486         (Ty VPR:$Rm), 3, 5)),
2487         (Ty VPR:$Rm), 5, 6)),
2488         (INST VPR:$Rn, VPR:$Rm)>;
2489
2490 def : NI_Uzp2_v8<v8i8, VPR64, UZP2vvv_8b>;
2491 def : NI_Uzp2_v8<v8i16, VPR128, UZP2vvv_8h>;
2492
2493 class NI_Uzp2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2494                  PatFrag ei>
2495   : Pat<(Ty (ei (Ty (ei (Ty (ei
2496         (Ty VPR:$Rm),
2497         (Ty VPR:$Rn), 1, 0)),
2498         (Ty VPR:$Rn), 3, 1)),
2499         (Ty VPR:$Rm), 1, 2)),
2500         (INST VPR:$Rn, VPR:$Rm)>;
2501
2502 def : NI_Uzp2_v4<v4i16, VPR64, UZP2vvv_4h, NI_ei_i32>;
2503 def : NI_Uzp2_v4<v4i32, VPR128, UZP2vvv_4s, NI_ei_i32>;
2504 def : NI_Uzp2_v4<v4f32, VPR128, UZP2vvv_4s, NI_ei_f32>;
2505
2506 // zip1
2507 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2508           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2509           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2510           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2511           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2512           (v16i8 VPR128:$Rn),
2513           (v16i8 VPR128:$Rm), 0, 1)),
2514           (v16i8 VPR128:$Rn), 1, 2)),
2515           (v16i8 VPR128:$Rm), 1, 3)),
2516           (v16i8 VPR128:$Rn), 2, 4)),
2517           (v16i8 VPR128:$Rm), 2, 5)),
2518           (v16i8 VPR128:$Rn), 3, 6)),
2519           (v16i8 VPR128:$Rm), 3, 7)),
2520           (v16i8 VPR128:$Rn), 4, 8)),
2521           (v16i8 VPR128:$Rm), 4, 9)),
2522           (v16i8 VPR128:$Rn), 5, 10)),
2523           (v16i8 VPR128:$Rm), 5, 11)),
2524           (v16i8 VPR128:$Rn), 6, 12)),
2525           (v16i8 VPR128:$Rm), 6, 13)),
2526           (v16i8 VPR128:$Rn), 7, 14)),
2527           (v16i8 VPR128:$Rm), 7, 15)),
2528           (ZIP1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2529
2530 class NI_Zip1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2531   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2532         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2533         (Ty VPR:$Rn),
2534         (Ty VPR:$Rm), 0, 1)),
2535         (Ty VPR:$Rn), 1, 2)),
2536         (Ty VPR:$Rm), 1, 3)),
2537         (Ty VPR:$Rn), 2, 4)),
2538         (Ty VPR:$Rm), 2, 5)),
2539         (Ty VPR:$Rn), 3, 6)),
2540         (Ty VPR:$Rm), 3, 7)),
2541         (INST VPR:$Rn, VPR:$Rm)>;
2542
2543 def : NI_Zip1_v8<v8i8, VPR64, ZIP1vvv_8b>;
2544 def : NI_Zip1_v8<v8i16, VPR128, ZIP1vvv_8h>;
2545
2546 class NI_Zip1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2547                  PatFrag ei>
2548   : Pat<(Ty (ei (Ty (ei (Ty (ei
2549         (Ty VPR:$Rn),
2550         (Ty VPR:$Rm), 0, 1)),
2551         (Ty VPR:$Rn), 1, 2)),
2552         (Ty VPR:$Rm), 1, 3)),
2553         (INST VPR:$Rn, VPR:$Rm)>;
2554
2555 def : NI_Zip1_v4<v4i16, VPR64, ZIP1vvv_4h, NI_ei_i32>;
2556 def : NI_Zip1_v4<v4i32, VPR128, ZIP1vvv_4s, NI_ei_i32>;
2557 def : NI_Zip1_v4<v4f32, VPR128, ZIP1vvv_4s, NI_ei_f32>;
2558
2559 // zip2
2560 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2561           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2562           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2563           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2564           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2565           (v16i8 VPR128:$Rm),
2566           (v16i8 VPR128:$Rn), 8, 0)),
2567           (v16i8 VPR128:$Rm), 8, 1)),
2568           (v16i8 VPR128:$Rn), 9, 2)),
2569           (v16i8 VPR128:$Rm), 9, 3)),
2570           (v16i8 VPR128:$Rn), 10, 4)),
2571           (v16i8 VPR128:$Rm), 10, 5)),
2572           (v16i8 VPR128:$Rn), 11, 6)),
2573           (v16i8 VPR128:$Rm), 11, 7)),
2574           (v16i8 VPR128:$Rn), 12, 8)),
2575           (v16i8 VPR128:$Rm), 12, 9)),
2576           (v16i8 VPR128:$Rn), 13, 10)),
2577           (v16i8 VPR128:$Rm), 13, 11)),
2578           (v16i8 VPR128:$Rn), 14, 12)),
2579           (v16i8 VPR128:$Rm), 14, 13)),
2580           (v16i8 VPR128:$Rn), 15, 14)),
2581           (ZIP2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2582
2583 class NI_Zip2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2584   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2585         (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2586         (Ty VPR:$Rm),
2587         (Ty VPR:$Rn), 4, 0)),
2588         (Ty VPR:$Rm), 4, 1)),
2589         (Ty VPR:$Rn), 5, 2)),
2590         (Ty VPR:$Rm), 5, 3)),
2591         (Ty VPR:$Rn), 6, 4)),
2592         (Ty VPR:$Rm), 6, 5)),
2593         (Ty VPR:$Rn), 7, 6)),
2594         (INST VPR:$Rn, VPR:$Rm)>;
2595
2596 def : NI_Zip2_v8<v8i8, VPR64, ZIP2vvv_8b>;
2597 def : NI_Zip2_v8<v8i16, VPR128, ZIP2vvv_8h>;
2598
2599 class NI_Zip2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2600                  PatFrag ei>
2601   : Pat<(Ty (ei (Ty (ei (Ty (ei
2602         (Ty VPR:$Rm),
2603         (Ty VPR:$Rn), 2, 0)),
2604         (Ty VPR:$Rm), 2, 1)),
2605         (Ty VPR:$Rn), 3, 2)),
2606         (INST VPR:$Rn, VPR:$Rm)>;
2607
2608 def : NI_Zip2_v4<v4i16, VPR64, ZIP2vvv_4h, NI_ei_i32>;
2609 def : NI_Zip2_v4<v4i32, VPR128, ZIP2vvv_4s, NI_ei_i32>;
2610 def : NI_Zip2_v4<v4f32, VPR128, ZIP2vvv_4s, NI_ei_f32>;
2611
2612 // trn1
2613 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2614           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2615           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2616           (v16i8 VPR128:$Rn),
2617           (v16i8 VPR128:$Rm), 0,  1)),
2618           (v16i8 VPR128:$Rm), 2,  3)),
2619           (v16i8 VPR128:$Rm), 4,  5)),
2620           (v16i8 VPR128:$Rm), 6,  7)),
2621           (v16i8 VPR128:$Rm), 8,  9)),
2622           (v16i8 VPR128:$Rm), 10, 11)),
2623           (v16i8 VPR128:$Rm), 12, 13)),
2624           (v16i8 VPR128:$Rm), 14, 15)),
2625           (TRN1vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2626
2627 class NI_Trn1_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2628   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2629         (Ty VPR:$Rn),
2630         (Ty VPR:$Rm), 0, 1)),
2631         (Ty VPR:$Rm), 2, 3)),
2632         (Ty VPR:$Rm), 4, 5)),
2633         (Ty VPR:$Rm), 6, 7)),
2634         (INST VPR:$Rn, VPR:$Rm)>;
2635
2636 def : NI_Trn1_v8<v8i8, VPR64, TRN1vvv_8b>;
2637 def : NI_Trn1_v8<v8i16, VPR128, TRN1vvv_8h>;
2638
2639 class NI_Trn1_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2640                  PatFrag ei>
2641   : Pat<(Ty (ei (Ty (ei
2642         (Ty VPR:$Rn),
2643         (Ty VPR:$Rm), 0, 1)),
2644         (Ty VPR:$Rm), 2, 3)),
2645         (INST VPR:$Rn, VPR:$Rm)>;
2646
2647 def : NI_Trn1_v4<v4i16, VPR64, TRN1vvv_4h, NI_ei_i32>;
2648 def : NI_Trn1_v4<v4i32, VPR128, TRN1vvv_4s, NI_ei_i32>;
2649 def : NI_Trn1_v4<v4f32, VPR128, TRN1vvv_4s, NI_ei_f32>;
2650
2651 // trn2
2652 def : Pat<(v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2653           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2654           (v16i8 (NI_ei_i32 (v16i8 (NI_ei_i32
2655           (v16i8 VPR128:$Rm),
2656           (v16i8 VPR128:$Rn), 1,  0)),
2657           (v16i8 VPR128:$Rn), 3,  2)),
2658           (v16i8 VPR128:$Rn), 5,  4)),
2659           (v16i8 VPR128:$Rn), 7,  6)),
2660           (v16i8 VPR128:$Rn), 9,  8)),
2661           (v16i8 VPR128:$Rn), 11, 10)),
2662           (v16i8 VPR128:$Rn), 13, 12)),
2663           (v16i8 VPR128:$Rn), 15, 14)),
2664           (TRN2vvv_16b VPR128:$Rn, VPR128:$Rm)>;
2665
2666 class NI_Trn2_v8<ValueType Ty, RegisterOperand VPR, Instruction INST>
2667   : Pat<(Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32 (Ty (NI_ei_i32
2668         (Ty VPR:$Rm),
2669         (Ty VPR:$Rn), 1, 0)),
2670         (Ty VPR:$Rn), 3, 2)),
2671         (Ty VPR:$Rn), 5, 4)),
2672         (Ty VPR:$Rn), 7, 6)),
2673         (INST VPR:$Rn, VPR:$Rm)>;
2674
2675 def : NI_Trn2_v8<v8i8, VPR64, TRN2vvv_8b>;
2676 def : NI_Trn2_v8<v8i16, VPR128, TRN2vvv_8h>;
2677
2678 class NI_Trn2_v4<ValueType Ty, RegisterOperand VPR, Instruction INST,
2679                  PatFrag ei>
2680   : Pat<(Ty (ei (Ty (ei
2681         (Ty VPR:$Rm),
2682         (Ty VPR:$Rn), 1, 0)),
2683         (Ty VPR:$Rn), 3, 2)),
2684         (INST VPR:$Rn, VPR:$Rm)>;
2685
2686 def : NI_Trn2_v4<v4i16, VPR64, TRN2vvv_4h, NI_ei_i32>;
2687 def : NI_Trn2_v4<v4i32, VPR128, TRN2vvv_4s, NI_ei_i32>;
2688 def : NI_Trn2_v4<v4f32, VPR128, TRN2vvv_4s, NI_ei_f32>;
2689
2690 // End of implementation for instruction class (Perm)
2691
2692 // The followings are for instruction class (3V Diff)
2693
2694 // normal long/long2 pattern
2695 class NeonI_3VDL<bit q, bit u, bits<2> size, bits<4> opcode,
2696                  string asmop, string ResS, string OpS,
2697                  SDPatternOperator opnode, SDPatternOperator ext,
2698                  RegisterOperand OpVPR,
2699                  ValueType ResTy, ValueType OpTy>
2700   : NeonI_3VDiff<q, u, size, opcode,
2701                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2702                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2703                  [(set (ResTy VPR128:$Rd),
2704                     (ResTy (opnode (ResTy (ext (OpTy OpVPR:$Rn))),
2705                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2706                  NoItinerary>;
2707
2708 multiclass NeonI_3VDL_s<bit u, bits<4> opcode,
2709                         string asmop, SDPatternOperator opnode,
2710                         bit Commutable = 0> {
2711   let isCommutable = Commutable in {
2712     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2713                            opnode, sext, VPR64, v8i16, v8i8>;
2714     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2715                            opnode, sext, VPR64, v4i32, v4i16>;
2716     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2717                            opnode, sext, VPR64, v2i64, v2i32>;
2718   }
2719 }
2720
2721 multiclass NeonI_3VDL2_s<bit u, bits<4> opcode, string asmop,
2722                          SDPatternOperator opnode, bit Commutable = 0> {
2723   let isCommutable = Commutable in {
2724     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2725                             opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2726     def _4s8h  : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2727                             opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2728     def _2d4s  : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2729                             opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2730   }
2731 }
2732
2733 multiclass NeonI_3VDL_u<bit u, bits<4> opcode, string asmop,
2734                         SDPatternOperator opnode, bit Commutable = 0> {
2735   let isCommutable = Commutable in {
2736     def _8h8b : NeonI_3VDL<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2737                            opnode, zext, VPR64, v8i16, v8i8>;
2738     def _4s4h : NeonI_3VDL<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2739                            opnode, zext, VPR64, v4i32, v4i16>;
2740     def _2d2s : NeonI_3VDL<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2741                            opnode, zext, VPR64, v2i64, v2i32>;
2742   }
2743 }
2744
2745 multiclass NeonI_3VDL2_u<bit u, bits<4> opcode, string asmop,
2746                          SDPatternOperator opnode, bit Commutable = 0> {
2747   let isCommutable = Commutable in {
2748     def _8h16b : NeonI_3VDL<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2749                             opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2750     def _4s8h : NeonI_3VDL<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2751                            opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2752     def _2d4s : NeonI_3VDL<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2753                            opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2754   }
2755 }
2756
2757 defm SADDLvvv :  NeonI_3VDL_s<0b0, 0b0000, "saddl", add, 1>;
2758 defm UADDLvvv :  NeonI_3VDL_u<0b1, 0b0000, "uaddl", add, 1>;
2759
2760 defm SADDL2vvv :  NeonI_3VDL2_s<0b0, 0b0000, "saddl2", add, 1>;
2761 defm UADDL2vvv :  NeonI_3VDL2_u<0b1, 0b0000, "uaddl2", add, 1>;
2762
2763 defm SSUBLvvv :  NeonI_3VDL_s<0b0, 0b0010, "ssubl", sub, 0>;
2764 defm USUBLvvv :  NeonI_3VDL_u<0b1, 0b0010, "usubl", sub, 0>;
2765
2766 defm SSUBL2vvv :  NeonI_3VDL2_s<0b0, 0b0010, "ssubl2", sub, 0>;
2767 defm USUBL2vvv :  NeonI_3VDL2_u<0b1, 0b0010, "usubl2", sub, 0>;
2768
2769 // normal wide/wide2 pattern
2770 class NeonI_3VDW<bit q, bit u, bits<2> size, bits<4> opcode,
2771                  string asmop, string ResS, string OpS,
2772                  SDPatternOperator opnode, SDPatternOperator ext,
2773                  RegisterOperand OpVPR,
2774                  ValueType ResTy, ValueType OpTy>
2775   : NeonI_3VDiff<q, u, size, opcode,
2776                  (outs VPR128:$Rd), (ins VPR128:$Rn, OpVPR:$Rm),
2777                  asmop # "\t$Rd." # ResS # ", $Rn." # ResS # ", $Rm." # OpS,
2778                  [(set (ResTy VPR128:$Rd),
2779                     (ResTy (opnode (ResTy VPR128:$Rn),
2780                                    (ResTy (ext (OpTy OpVPR:$Rm))))))],
2781                  NoItinerary>;
2782
2783 multiclass NeonI_3VDW_s<bit u, bits<4> opcode, string asmop,
2784                         SDPatternOperator opnode> {
2785   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2786                          opnode, sext, VPR64, v8i16, v8i8>;
2787   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2788                          opnode, sext, VPR64, v4i32, v4i16>;
2789   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2790                          opnode, sext, VPR64, v2i64, v2i32>;
2791 }
2792
2793 defm SADDWvvv :  NeonI_3VDW_s<0b0, 0b0001, "saddw", add>;
2794 defm SSUBWvvv :  NeonI_3VDW_s<0b0, 0b0011, "ssubw", sub>;
2795
2796 multiclass NeonI_3VDW2_s<bit u, bits<4> opcode, string asmop,
2797                          SDPatternOperator opnode> {
2798   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2799                           opnode, NI_sext_high_v8i8, VPR128, v8i16, v16i8>;
2800   def _4s8h  : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2801                           opnode, NI_sext_high_v4i16, VPR128, v4i32, v8i16>;
2802   def _2d4s  : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2803                           opnode, NI_sext_high_v2i32, VPR128, v2i64, v4i32>;
2804 }
2805
2806 defm SADDW2vvv :  NeonI_3VDW2_s<0b0, 0b0001, "saddw2", add>;
2807 defm SSUBW2vvv :  NeonI_3VDW2_s<0b0, 0b0011, "ssubw2", sub>;
2808
2809 multiclass NeonI_3VDW_u<bit u, bits<4> opcode, string asmop,
2810                         SDPatternOperator opnode> {
2811   def _8h8b : NeonI_3VDW<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2812                          opnode, zext, VPR64, v8i16, v8i8>;
2813   def _4s4h : NeonI_3VDW<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2814                          opnode, zext, VPR64, v4i32, v4i16>;
2815   def _2d2s : NeonI_3VDW<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2816                          opnode, zext, VPR64, v2i64, v2i32>;
2817 }
2818
2819 defm UADDWvvv :  NeonI_3VDW_u<0b1, 0b0001, "uaddw", add>;
2820 defm USUBWvvv :  NeonI_3VDW_u<0b1, 0b0011, "usubw", sub>;
2821
2822 multiclass NeonI_3VDW2_u<bit u, bits<4> opcode, string asmop,
2823                          SDPatternOperator opnode> {
2824   def _8h16b : NeonI_3VDW<0b1, u, 0b00, opcode, asmop, "8h", "16b",
2825                           opnode, NI_zext_high_v8i8, VPR128, v8i16, v16i8>;
2826   def _4s8h : NeonI_3VDW<0b1, u, 0b01, opcode, asmop, "4s", "8h",
2827                          opnode, NI_zext_high_v4i16, VPR128, v4i32, v8i16>;
2828   def _2d4s : NeonI_3VDW<0b1, u, 0b10, opcode, asmop, "2d", "4s",
2829                          opnode, NI_zext_high_v2i32, VPR128, v2i64, v4i32>;
2830 }
2831
2832 defm UADDW2vvv :  NeonI_3VDW2_u<0b1, 0b0001, "uaddw2", add>;
2833 defm USUBW2vvv :  NeonI_3VDW2_u<0b1, 0b0011, "usubw2", sub>;
2834
2835 // Get the high half part of the vector element.
2836 multiclass NeonI_get_high {
2837   def _8h : PatFrag<(ops node:$Rn),
2838                     (v8i8 (trunc (v8i16 (srl (v8i16 node:$Rn),
2839                                              (v8i16 (Neon_vdup (i32 8)))))))>;
2840   def _4s : PatFrag<(ops node:$Rn),
2841                     (v4i16 (trunc (v4i32 (srl (v4i32 node:$Rn),
2842                                               (v4i32 (Neon_vdup (i32 16)))))))>;
2843   def _2d : PatFrag<(ops node:$Rn),
2844                     (v2i32 (trunc (v2i64 (srl (v2i64 node:$Rn),
2845                                               (v2i64 (Neon_vdup (i32 32)))))))>;
2846 }
2847
2848 defm NI_get_hi : NeonI_get_high;
2849
2850 // pattern for addhn/subhn with 2 operands
2851 class NeonI_3VDN_addhn_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2852                            string asmop, string ResS, string OpS,
2853                            SDPatternOperator opnode, SDPatternOperator get_hi,
2854                            ValueType ResTy, ValueType OpTy>
2855   : NeonI_3VDiff<q, u, size, opcode,
2856                  (outs VPR64:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
2857                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2858                  [(set (ResTy VPR64:$Rd),
2859                     (ResTy (get_hi
2860                       (OpTy (opnode (OpTy VPR128:$Rn),
2861                                     (OpTy VPR128:$Rm))))))],
2862                  NoItinerary>;
2863
2864 multiclass NeonI_3VDN_addhn_2Op<bit u, bits<4> opcode, string asmop,
2865                                 SDPatternOperator opnode, bit Commutable = 0> {
2866   let isCommutable = Commutable in {
2867     def _8b8h : NeonI_3VDN_addhn_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2868                                      opnode, NI_get_hi_8h, v8i8, v8i16>;
2869     def _4h4s : NeonI_3VDN_addhn_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2870                                      opnode, NI_get_hi_4s, v4i16, v4i32>;
2871     def _2s2d : NeonI_3VDN_addhn_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2872                                      opnode, NI_get_hi_2d, v2i32, v2i64>;
2873   }
2874 }
2875
2876 defm ADDHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0100, "addhn", add, 1>;
2877 defm SUBHNvvv  : NeonI_3VDN_addhn_2Op<0b0, 0b0110, "subhn", sub, 0>;
2878
2879 // pattern for operation with 2 operands
2880 class NeonI_3VD_2Op<bit q, bit u, bits<2> size, bits<4> opcode,
2881                     string asmop, string ResS, string OpS,
2882                     SDPatternOperator opnode,
2883                     RegisterOperand ResVPR, RegisterOperand OpVPR,
2884                     ValueType ResTy, ValueType OpTy>
2885   : NeonI_3VDiff<q, u, size, opcode,
2886                  (outs ResVPR:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2887                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2888                  [(set (ResTy ResVPR:$Rd),
2889                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))],
2890                  NoItinerary>;
2891
2892 // normal narrow pattern
2893 multiclass NeonI_3VDN_2Op<bit u, bits<4> opcode, string asmop,
2894                           SDPatternOperator opnode, bit Commutable = 0> {
2895   let isCommutable = Commutable in {
2896     def _8b8h : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8b", "8h",
2897                               opnode, VPR64, VPR128, v8i8, v8i16>;
2898     def _4h4s : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4h", "4s",
2899                               opnode, VPR64, VPR128, v4i16, v4i32>;
2900     def _2s2d : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2s", "2d",
2901                               opnode, VPR64, VPR128, v2i32, v2i64>;
2902   }
2903 }
2904
2905 defm RADDHNvvv : NeonI_3VDN_2Op<0b1, 0b0100, "raddhn", int_arm_neon_vraddhn, 1>;
2906 defm RSUBHNvvv : NeonI_3VDN_2Op<0b1, 0b0110, "rsubhn", int_arm_neon_vrsubhn, 0>;
2907
2908 // pattern for acle intrinsic with 3 operands
2909 class NeonI_3VDN_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
2910                      string asmop, string ResS, string OpS>
2911   : NeonI_3VDiff<q, u, size, opcode,
2912                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
2913                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2914                  [], NoItinerary> {
2915   let Constraints = "$src = $Rd";
2916   let neverHasSideEffects = 1;
2917 }
2918
2919 multiclass NeonI_3VDN_3Op_v1<bit u, bits<4> opcode, string asmop> {
2920   def _16b8h : NeonI_3VDN_3Op<0b1, u, 0b00, opcode, asmop, "16b", "8h">;
2921   def _8h4s : NeonI_3VDN_3Op<0b1, u, 0b01, opcode, asmop, "8h", "4s">;
2922   def _4s2d : NeonI_3VDN_3Op<0b1, u, 0b10, opcode, asmop, "4s", "2d">;
2923 }
2924
2925 defm ADDHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0100, "addhn2">;
2926 defm SUBHN2vvv  : NeonI_3VDN_3Op_v1<0b0, 0b0110, "subhn2">;
2927
2928 defm RADDHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0100, "raddhn2">;
2929 defm RSUBHN2vvv : NeonI_3VDN_3Op_v1<0b1, 0b0110, "rsubhn2">;
2930
2931 // Patterns have to be separate because there's a SUBREG_TO_REG in the output
2932 // part.
2933 class NarrowHighHalfPat<Instruction INST, ValueType DstTy, ValueType SrcTy,
2934                         SDPatternOperator coreop>
2935   : Pat<(Neon_combine_2D (v1i64 VPR64:$src),
2936                       (v1i64 (bitconvert (DstTy (coreop (SrcTy VPR128:$Rn),
2937                                                         (SrcTy VPR128:$Rm)))))),
2938         (INST (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64),
2939               VPR128:$Rn, VPR128:$Rm)>;
2940
2941 // addhn2 patterns
2942 def : NarrowHighHalfPat<ADDHN2vvv_16b8h, v8i8,  v8i16,
2943           BinOpFrag<(NI_get_hi_8h (add node:$LHS, node:$RHS))>>;
2944 def : NarrowHighHalfPat<ADDHN2vvv_8h4s,  v4i16, v4i32,
2945           BinOpFrag<(NI_get_hi_4s (add node:$LHS, node:$RHS))>>;
2946 def : NarrowHighHalfPat<ADDHN2vvv_4s2d,  v2i32, v2i64,
2947           BinOpFrag<(NI_get_hi_2d (add node:$LHS, node:$RHS))>>;
2948
2949 // subhn2 patterns
2950 def : NarrowHighHalfPat<SUBHN2vvv_16b8h, v8i8,  v8i16,
2951           BinOpFrag<(NI_get_hi_8h (sub node:$LHS, node:$RHS))>>;
2952 def : NarrowHighHalfPat<SUBHN2vvv_8h4s,  v4i16, v4i32,
2953           BinOpFrag<(NI_get_hi_4s (sub node:$LHS, node:$RHS))>>;
2954 def : NarrowHighHalfPat<SUBHN2vvv_4s2d,  v2i32, v2i64,
2955           BinOpFrag<(NI_get_hi_2d (sub node:$LHS, node:$RHS))>>;
2956
2957 // raddhn2 patterns
2958 def : NarrowHighHalfPat<RADDHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vraddhn>;
2959 def : NarrowHighHalfPat<RADDHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vraddhn>;
2960 def : NarrowHighHalfPat<RADDHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vraddhn>;
2961
2962 // rsubhn2 patterns
2963 def : NarrowHighHalfPat<RSUBHN2vvv_16b8h, v8i8,  v8i16, int_arm_neon_vrsubhn>;
2964 def : NarrowHighHalfPat<RSUBHN2vvv_8h4s,  v4i16, v4i32, int_arm_neon_vrsubhn>;
2965 def : NarrowHighHalfPat<RSUBHN2vvv_4s2d,  v2i32, v2i64, int_arm_neon_vrsubhn>;
2966
2967 // pattern that need to extend result
2968 class NeonI_3VDL_Ext<bit q, bit u, bits<2> size, bits<4> opcode,
2969                      string asmop, string ResS, string OpS,
2970                      SDPatternOperator opnode,
2971                      RegisterOperand OpVPR,
2972                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
2973   : NeonI_3VDiff<q, u, size, opcode,
2974                  (outs VPR128:$Rd), (ins OpVPR:$Rn, OpVPR:$Rm),
2975                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
2976                  [(set (ResTy VPR128:$Rd),
2977                     (ResTy (zext (OpSTy (opnode (OpTy OpVPR:$Rn),
2978                                                 (OpTy OpVPR:$Rm))))))],
2979                  NoItinerary>;
2980
2981 multiclass NeonI_3VDL_zext<bit u, bits<4> opcode, string asmop,
2982                            SDPatternOperator opnode, bit Commutable = 0> {
2983   let isCommutable = Commutable in {
2984     def _8h8b : NeonI_3VDL_Ext<0b0, u, 0b00, opcode, asmop, "8h", "8b",
2985                                opnode, VPR64, v8i16, v8i8, v8i8>;
2986     def _4s4h : NeonI_3VDL_Ext<0b0, u, 0b01, opcode, asmop, "4s", "4h",
2987                                opnode, VPR64, v4i32, v4i16, v4i16>;
2988     def _2d2s : NeonI_3VDL_Ext<0b0, u, 0b10, opcode, asmop, "2d", "2s",
2989                                opnode, VPR64, v2i64, v2i32, v2i32>;
2990   }
2991 }
2992
2993 defm SABDLvvv : NeonI_3VDL_zext<0b0, 0b0111, "sabdl", int_arm_neon_vabds, 1>;
2994 defm UABDLvvv : NeonI_3VDL_zext<0b1, 0b0111, "uabdl", int_arm_neon_vabdu, 1>;
2995
2996 multiclass NeonI_Op_High<SDPatternOperator op> {
2997   def _16B : PatFrag<(ops node:$Rn, node:$Rm),
2998                      (op (v8i8 (Neon_High16B node:$Rn)),
2999                          (v8i8 (Neon_High16B node:$Rm)))>;
3000   def _8H  : PatFrag<(ops node:$Rn, node:$Rm),
3001                      (op (v4i16 (Neon_High8H node:$Rn)),
3002                          (v4i16 (Neon_High8H node:$Rm)))>;
3003   def _4S  : PatFrag<(ops node:$Rn, node:$Rm),
3004                      (op (v2i32 (Neon_High4S node:$Rn)),
3005                          (v2i32 (Neon_High4S node:$Rm)))>;
3006 }
3007
3008 defm NI_sabdl_hi : NeonI_Op_High<int_arm_neon_vabds>;
3009 defm NI_uabdl_hi : NeonI_Op_High<int_arm_neon_vabdu>;
3010 defm NI_smull_hi : NeonI_Op_High<int_arm_neon_vmulls>;
3011 defm NI_umull_hi : NeonI_Op_High<int_arm_neon_vmullu>;
3012 defm NI_qdmull_hi : NeonI_Op_High<int_arm_neon_vqdmull>;
3013 defm NI_pmull_hi : NeonI_Op_High<int_arm_neon_vmullp>;
3014
3015 multiclass NeonI_3VDL_Abd_u<bit u, bits<4> opcode, string asmop, string opnode,
3016                             bit Commutable = 0> {
3017   let isCommutable = Commutable in {
3018     def _8h8b  : NeonI_3VDL_Ext<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3019                                 !cast<PatFrag>(opnode # "_16B"),
3020                                 VPR128, v8i16, v16i8, v8i8>;
3021     def _4s4h  : NeonI_3VDL_Ext<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3022                                 !cast<PatFrag>(opnode # "_8H"),
3023                                 VPR128, v4i32, v8i16, v4i16>;
3024     def _2d2s  : NeonI_3VDL_Ext<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3025                                 !cast<PatFrag>(opnode # "_4S"),
3026                                 VPR128, v2i64, v4i32, v2i32>;
3027   }
3028 }
3029
3030 defm SABDL2vvv : NeonI_3VDL_Abd_u<0b0, 0b0111, "sabdl2", "NI_sabdl_hi", 1>;
3031 defm UABDL2vvv : NeonI_3VDL_Abd_u<0b1, 0b0111, "uabdl2", "NI_uabdl_hi", 1>;
3032
3033 // For pattern that need two operators being chained.
3034 class NeonI_3VDL_Aba<bit q, bit u, bits<2> size, bits<4> opcode,
3035                      string asmop, string ResS, string OpS,
3036                      SDPatternOperator opnode, SDPatternOperator subop,
3037                      RegisterOperand OpVPR,
3038                      ValueType ResTy, ValueType OpTy, ValueType OpSTy>
3039   : NeonI_3VDiff<q, u, size, opcode,
3040                  (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3041                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3042                  [(set (ResTy VPR128:$Rd),
3043                     (ResTy (opnode
3044                       (ResTy VPR128:$src),
3045                       (ResTy (zext (OpSTy (subop (OpTy OpVPR:$Rn),
3046                                                  (OpTy OpVPR:$Rm))))))))],
3047                  NoItinerary> {
3048   let Constraints = "$src = $Rd";
3049 }
3050
3051 multiclass NeonI_3VDL_Aba_v1<bit u, bits<4> opcode, string asmop,
3052                              SDPatternOperator opnode, SDPatternOperator subop>{
3053   def _8h8b : NeonI_3VDL_Aba<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3054                              opnode, subop, VPR64, v8i16, v8i8, v8i8>;
3055   def _4s4h : NeonI_3VDL_Aba<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3056                              opnode, subop, VPR64, v4i32, v4i16, v4i16>;
3057   def _2d2s : NeonI_3VDL_Aba<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3058                              opnode, subop, VPR64, v2i64, v2i32, v2i32>;
3059 }
3060
3061 defm SABALvvv :  NeonI_3VDL_Aba_v1<0b0, 0b0101, "sabal",
3062                                    add, int_arm_neon_vabds>;
3063 defm UABALvvv :  NeonI_3VDL_Aba_v1<0b1, 0b0101, "uabal",
3064                                    add, int_arm_neon_vabdu>;
3065
3066 multiclass NeonI_3VDL2_Aba_v1<bit u, bits<4> opcode, string asmop,
3067                               SDPatternOperator opnode, string subop> {
3068   def _8h8b : NeonI_3VDL_Aba<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3069                              opnode, !cast<PatFrag>(subop # "_16B"),
3070                              VPR128, v8i16, v16i8, v8i8>;
3071   def _4s4h : NeonI_3VDL_Aba<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3072                              opnode, !cast<PatFrag>(subop # "_8H"),
3073                              VPR128, v4i32, v8i16, v4i16>;
3074   def _2d2s : NeonI_3VDL_Aba<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3075                              opnode, !cast<PatFrag>(subop # "_4S"),
3076                              VPR128, v2i64, v4i32, v2i32>;
3077 }
3078
3079 defm SABAL2vvv :  NeonI_3VDL2_Aba_v1<0b0, 0b0101, "sabal2", add,
3080                                      "NI_sabdl_hi">;
3081 defm UABAL2vvv :  NeonI_3VDL2_Aba_v1<0b1, 0b0101, "uabal2", add,
3082                                      "NI_uabdl_hi">;
3083
3084 // Long pattern with 2 operands
3085 multiclass NeonI_3VDL_2Op<bit u, bits<4> opcode, string asmop,
3086                           SDPatternOperator opnode, bit Commutable = 0> {
3087   let isCommutable = Commutable in {
3088     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3089                               opnode, VPR128, VPR64, v8i16, v8i8>;
3090     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3091                               opnode, VPR128, VPR64, v4i32, v4i16>;
3092     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3093                               opnode, VPR128, VPR64, v2i64, v2i32>;
3094   }
3095 }
3096
3097 defm SMULLvvv :  NeonI_3VDL_2Op<0b0, 0b1100, "smull", int_arm_neon_vmulls, 1>;
3098 defm UMULLvvv :  NeonI_3VDL_2Op<0b1, 0b1100, "umull", int_arm_neon_vmullu, 1>;
3099
3100 class NeonI_3VDL2_2Op_mull<bit q, bit u, bits<2> size, bits<4> opcode,
3101                            string asmop, string ResS, string OpS,
3102                            SDPatternOperator opnode,
3103                            ValueType ResTy, ValueType OpTy>
3104   : NeonI_3VDiff<q, u, size, opcode,
3105                  (outs VPR128:$Rd), (ins VPR128:$Rn, VPR128:$Rm),
3106                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3107                  [(set (ResTy VPR128:$Rd),
3108                     (ResTy (opnode (OpTy VPR128:$Rn), (OpTy VPR128:$Rm))))],
3109                  NoItinerary>;
3110
3111 multiclass NeonI_3VDL2_2Op_mull_v1<bit u, bits<4> opcode, string asmop,
3112                                    string opnode, bit Commutable = 0> {
3113   let isCommutable = Commutable in {
3114     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3115                                       !cast<PatFrag>(opnode # "_16B"),
3116                                       v8i16, v16i8>;
3117     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3118                                      !cast<PatFrag>(opnode # "_8H"),
3119                                      v4i32, v8i16>;
3120     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3121                                      !cast<PatFrag>(opnode # "_4S"),
3122                                      v2i64, v4i32>;
3123   }
3124 }
3125
3126 defm SMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b0, 0b1100, "smull2",
3127                                          "NI_smull_hi", 1>;
3128 defm UMULL2vvv : NeonI_3VDL2_2Op_mull_v1<0b1, 0b1100, "umull2",
3129                                          "NI_umull_hi", 1>;
3130
3131 // Long pattern with 3 operands
3132 class NeonI_3VDL_3Op<bit q, bit u, bits<2> size, bits<4> opcode,
3133                      string asmop, string ResS, string OpS,
3134                      SDPatternOperator opnode,
3135                      ValueType ResTy, ValueType OpTy>
3136   : NeonI_3VDiff<q, u, size, opcode,
3137                  (outs VPR128:$Rd), (ins VPR128:$src, VPR64:$Rn, VPR64:$Rm),
3138                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3139                  [(set (ResTy VPR128:$Rd),
3140                     (ResTy (opnode
3141                       (ResTy VPR128:$src),
3142                       (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))))],
3143                NoItinerary> {
3144   let Constraints = "$src = $Rd";
3145 }
3146
3147 multiclass NeonI_3VDL_3Op_v1<bit u, bits<4> opcode, string asmop,
3148                              SDPatternOperator opnode> {
3149   def _8h8b : NeonI_3VDL_3Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3150                              opnode, v8i16, v8i8>;
3151   def _4s4h : NeonI_3VDL_3Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3152                              opnode, v4i32, v4i16>;
3153   def _2d2s : NeonI_3VDL_3Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3154                              opnode, v2i64, v2i32>;
3155 }
3156
3157 def Neon_smlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3158                          (add node:$Rd,
3159                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3160
3161 def Neon_umlal : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3162                          (add node:$Rd,
3163                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3164
3165 def Neon_smlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3166                          (sub node:$Rd,
3167                             (int_arm_neon_vmulls node:$Rn, node:$Rm))>;
3168
3169 def Neon_umlsl : PatFrag<(ops node:$Rd, node:$Rn, node:$Rm),
3170                          (sub node:$Rd,
3171                             (int_arm_neon_vmullu node:$Rn, node:$Rm))>;
3172
3173 defm SMLALvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1000, "smlal", Neon_smlal>;
3174 defm UMLALvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1000, "umlal", Neon_umlal>;
3175
3176 defm SMLSLvvv :  NeonI_3VDL_3Op_v1<0b0, 0b1010, "smlsl", Neon_smlsl>;
3177 defm UMLSLvvv :  NeonI_3VDL_3Op_v1<0b1, 0b1010, "umlsl", Neon_umlsl>;
3178
3179 class NeonI_3VDL2_3Op_mlas<bit q, bit u, bits<2> size, bits<4> opcode,
3180                            string asmop, string ResS, string OpS,
3181                            SDPatternOperator subop, SDPatternOperator opnode,
3182                            RegisterOperand OpVPR,
3183                            ValueType ResTy, ValueType OpTy>
3184   : NeonI_3VDiff<q, u, size, opcode,
3185                (outs VPR128:$Rd), (ins VPR128:$src, OpVPR:$Rn, OpVPR:$Rm),
3186                asmop # "\t$Rd." # ResS # ", $Rn." # OpS # ", $Rm." # OpS,
3187                [(set (ResTy VPR128:$Rd),
3188                   (ResTy (subop
3189                     (ResTy VPR128:$src),
3190                     (ResTy (opnode (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm))))))],
3191                NoItinerary> {
3192   let Constraints = "$src = $Rd";
3193 }
3194
3195 multiclass NeonI_3VDL2_3Op_mlas_v1<bit u, bits<4> opcode, string asmop,
3196                                    SDPatternOperator subop, string opnode> {
3197   def _8h16b : NeonI_3VDL2_3Op_mlas<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3198                                     subop, !cast<PatFrag>(opnode # "_16B"),
3199                                     VPR128, v8i16, v16i8>;
3200   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3201                                    subop, !cast<PatFrag>(opnode # "_8H"),
3202                                    VPR128, v4i32, v8i16>;
3203   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3204                                    subop, !cast<PatFrag>(opnode # "_4S"),
3205                                    VPR128, v2i64, v4i32>;
3206 }
3207
3208 defm SMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1000, "smlal2",
3209                                           add, "NI_smull_hi">;
3210 defm UMLAL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1000, "umlal2",
3211                                           add, "NI_umull_hi">;
3212
3213 defm SMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b0, 0b1010, "smlsl2",
3214                                           sub, "NI_smull_hi">;
3215 defm UMLSL2vvv :  NeonI_3VDL2_3Op_mlas_v1<0b1, 0b1010, "umlsl2",
3216                                           sub, "NI_umull_hi">;
3217
3218 multiclass NeonI_3VDL_qdmlal_3Op_v2<bit u, bits<4> opcode, string asmop,
3219                                     SDPatternOperator opnode> {
3220   def _4s4h : NeonI_3VDL2_3Op_mlas<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3221                                    opnode, int_arm_neon_vqdmull,
3222                                    VPR64, v4i32, v4i16>;
3223   def _2d2s : NeonI_3VDL2_3Op_mlas<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3224                                    opnode, int_arm_neon_vqdmull,
3225                                    VPR64, v2i64, v2i32>;
3226 }
3227
3228 defm SQDMLALvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1001, "sqdmlal",
3229                                            int_arm_neon_vqadds>;
3230 defm SQDMLSLvvv : NeonI_3VDL_qdmlal_3Op_v2<0b0, 0b1011, "sqdmlsl",
3231                                            int_arm_neon_vqsubs>;
3232
3233 multiclass NeonI_3VDL_v2<bit u, bits<4> opcode, string asmop,
3234                          SDPatternOperator opnode, bit Commutable = 0> {
3235   let isCommutable = Commutable in {
3236     def _4s4h : NeonI_3VD_2Op<0b0, u, 0b01, opcode, asmop, "4s", "4h",
3237                               opnode, VPR128, VPR64, v4i32, v4i16>;
3238     def _2d2s : NeonI_3VD_2Op<0b0, u, 0b10, opcode, asmop, "2d", "2s",
3239                               opnode, VPR128, VPR64, v2i64, v2i32>;
3240   }
3241 }
3242
3243 defm SQDMULLvvv : NeonI_3VDL_v2<0b0, 0b1101, "sqdmull",
3244                                 int_arm_neon_vqdmull, 1>;
3245
3246 multiclass NeonI_3VDL2_2Op_mull_v2<bit u, bits<4> opcode, string asmop,
3247                                    string opnode, bit Commutable = 0> {
3248   let isCommutable = Commutable in {
3249     def _4s8h : NeonI_3VDL2_2Op_mull<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3250                                      !cast<PatFrag>(opnode # "_8H"),
3251                                      v4i32, v8i16>;
3252     def _2d4s : NeonI_3VDL2_2Op_mull<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3253                                      !cast<PatFrag>(opnode # "_4S"),
3254                                      v2i64, v4i32>;
3255   }
3256 }
3257
3258 defm SQDMULL2vvv : NeonI_3VDL2_2Op_mull_v2<0b0, 0b1101, "sqdmull2",
3259                                            "NI_qdmull_hi", 1>;
3260
3261 multiclass NeonI_3VDL2_3Op_qdmlal_v2<bit u, bits<4> opcode, string asmop,
3262                                      SDPatternOperator opnode> {
3263   def _4s8h : NeonI_3VDL2_3Op_mlas<0b1, u, 0b01, opcode, asmop, "4s", "8h",
3264                                    opnode, NI_qdmull_hi_8H,
3265                                    VPR128, v4i32, v8i16>;
3266   def _2d4s : NeonI_3VDL2_3Op_mlas<0b1, u, 0b10, opcode, asmop, "2d", "4s",
3267                                    opnode, NI_qdmull_hi_4S,
3268                                    VPR128, v2i64, v4i32>;
3269 }
3270
3271 defm SQDMLAL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1001, "sqdmlal2",
3272                                              int_arm_neon_vqadds>;
3273 defm SQDMLSL2vvv : NeonI_3VDL2_3Op_qdmlal_v2<0b0, 0b1011, "sqdmlsl2",
3274                                              int_arm_neon_vqsubs>;
3275
3276 multiclass NeonI_3VDL_v3<bit u, bits<4> opcode, string asmop,
3277                          SDPatternOperator opnode, bit Commutable = 0> {
3278   let isCommutable = Commutable in {
3279     def _8h8b : NeonI_3VD_2Op<0b0, u, 0b00, opcode, asmop, "8h", "8b",
3280                               opnode, VPR128, VPR64, v8i16, v8i8>;
3281   }
3282 }
3283
3284 defm PMULLvvv : NeonI_3VDL_v3<0b0, 0b1110, "pmull", int_arm_neon_vmullp, 1>;
3285
3286 multiclass NeonI_3VDL2_2Op_mull_v3<bit u, bits<4> opcode, string asmop,
3287                                    string opnode, bit Commutable = 0> {
3288   let isCommutable = Commutable in {
3289     def _8h16b : NeonI_3VDL2_2Op_mull<0b1, u, 0b00, opcode, asmop, "8h", "16b",
3290                                       !cast<PatFrag>(opnode # "_16B"),
3291                                       v8i16, v16i8>;
3292   }
3293 }
3294
3295 defm PMULL2vvv : NeonI_3VDL2_2Op_mull_v3<0b0, 0b1110, "pmull2", "NI_pmull_hi",
3296                                          1>;
3297
3298 // End of implementation for instruction class (3V Diff)
3299
3300 // The followings are vector load/store multiple N-element structure
3301 // (class SIMD lselem).
3302
3303 // ld1:         load multiple 1-element structure to 1/2/3/4 registers.
3304 // ld2/ld3/ld4: load multiple N-element structure to N registers (N = 2, 3, 4).
3305 //              The structure consists of a sequence of sets of N values.
3306 //              The first element of the structure is placed in the first lane
3307 //              of the first first vector, the second element in the first lane
3308 //              of the second vector, and so on.
3309 // E.g. LD1_3V_2S will load 32-bit elements {A, B, C, D, E, F} sequentially into
3310 // the three 64-bit vectors list {BA, DC, FE}.
3311 // E.g. LD3_2S will load 32-bit elements {A, B, C, D, E, F} into the three
3312 // 64-bit vectors list {DA, EB, FC}.
3313 // Store instructions store multiple structure to N registers like load.
3314
3315
3316 class NeonI_LDVList<bit q, bits<4> opcode, bits<2> size,
3317                     RegisterOperand VecList, string asmop>
3318   : NeonI_LdStMult<q, 1, opcode, size,
3319                  (outs VecList:$Rt), (ins GPR64xsp:$Rn),
3320                  asmop # "\t$Rt, [$Rn]",
3321                  [],
3322                  NoItinerary> {
3323   let mayLoad = 1;
3324   let neverHasSideEffects = 1;
3325 }
3326
3327 multiclass LDVList_BHSD<bits<4> opcode, string List, string asmop> {
3328   def _8B : NeonI_LDVList<0, opcode, 0b00,
3329                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3330
3331   def _4H : NeonI_LDVList<0, opcode, 0b01,
3332                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3333
3334   def _2S : NeonI_LDVList<0, opcode, 0b10,
3335                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3336
3337   def _16B : NeonI_LDVList<1, opcode, 0b00,
3338                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3339
3340   def _8H : NeonI_LDVList<1, opcode, 0b01,
3341                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3342
3343   def _4S : NeonI_LDVList<1, opcode, 0b10,
3344                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3345
3346   def _2D : NeonI_LDVList<1, opcode, 0b11,
3347                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3348 }
3349
3350 // Load multiple N-element structure to N consecutive registers (N = 1,2,3,4)
3351 defm LD1 : LDVList_BHSD<0b0111, "VOne", "ld1">;
3352 def LD1_1D : NeonI_LDVList<0, 0b0111, 0b11, VOne1D_operand, "ld1">;
3353
3354 defm LD2 : LDVList_BHSD<0b1000, "VPair", "ld2">;
3355
3356 defm LD3 : LDVList_BHSD<0b0100, "VTriple", "ld3">;
3357
3358 defm LD4 : LDVList_BHSD<0b0000, "VQuad", "ld4">;
3359
3360 // Load multiple 1-element structure to N consecutive registers (N = 2,3,4)
3361 defm LD1_2V : LDVList_BHSD<0b1010, "VPair", "ld1">;
3362 def LD1_2V_1D : NeonI_LDVList<0, 0b1010, 0b11, VPair1D_operand, "ld1">;
3363
3364 defm LD1_3V : LDVList_BHSD<0b0110, "VTriple", "ld1">;
3365 def LD1_3V_1D : NeonI_LDVList<0, 0b0110, 0b11, VTriple1D_operand, "ld1">;
3366
3367 defm LD1_4V : LDVList_BHSD<0b0010, "VQuad", "ld1">;
3368 def LD1_4V_1D : NeonI_LDVList<0, 0b0010, 0b11, VQuad1D_operand, "ld1">;
3369
3370 class NeonI_STVList<bit q, bits<4> opcode, bits<2> size,
3371                     RegisterOperand VecList, string asmop>
3372   : NeonI_LdStMult<q, 0, opcode, size,
3373                  (outs), (ins GPR64xsp:$Rn, VecList:$Rt),
3374                  asmop # "\t$Rt, [$Rn]",
3375                  [],
3376                  NoItinerary> {
3377   let mayStore = 1;
3378   let neverHasSideEffects = 1;
3379 }
3380
3381 multiclass STVList_BHSD<bits<4> opcode, string List, string asmop> {
3382   def _8B : NeonI_STVList<0, opcode, 0b00,
3383                           !cast<RegisterOperand>(List # "8B_operand"), asmop>;
3384
3385   def _4H : NeonI_STVList<0, opcode, 0b01,
3386                           !cast<RegisterOperand>(List # "4H_operand"), asmop>;
3387
3388   def _2S : NeonI_STVList<0, opcode, 0b10,
3389                           !cast<RegisterOperand>(List # "2S_operand"), asmop>;
3390
3391   def _16B : NeonI_STVList<1, opcode, 0b00,
3392                            !cast<RegisterOperand>(List # "16B_operand"), asmop>;
3393
3394   def _8H : NeonI_STVList<1, opcode, 0b01,
3395                           !cast<RegisterOperand>(List # "8H_operand"), asmop>;
3396
3397   def _4S : NeonI_STVList<1, opcode, 0b10,
3398                           !cast<RegisterOperand>(List # "4S_operand"), asmop>;
3399
3400   def _2D : NeonI_STVList<1, opcode, 0b11,
3401                           !cast<RegisterOperand>(List # "2D_operand"), asmop>;
3402 }
3403
3404 // Store multiple N-element structures from N registers (N = 1,2,3,4)
3405 defm ST1 : STVList_BHSD<0b0111, "VOne", "st1">;
3406 def ST1_1D : NeonI_STVList<0, 0b0111, 0b11, VOne1D_operand, "st1">;
3407
3408 defm ST2 : STVList_BHSD<0b1000, "VPair", "st2">;
3409
3410 defm ST3 : STVList_BHSD<0b0100, "VTriple", "st3">;
3411
3412 defm ST4 : STVList_BHSD<0b0000, "VQuad", "st4">;
3413
3414 // Store multiple 1-element structures from N consecutive registers (N = 2,3,4)
3415 defm ST1_2V : STVList_BHSD<0b1010, "VPair", "st1">;
3416 def ST1_2V_1D : NeonI_STVList<0, 0b1010, 0b11, VPair1D_operand, "st1">;
3417
3418 defm ST1_3V : STVList_BHSD<0b0110, "VTriple", "st1">;
3419 def ST1_3V_1D : NeonI_STVList<0, 0b0110, 0b11, VTriple1D_operand, "st1">;
3420
3421 defm ST1_4V : STVList_BHSD<0b0010, "VQuad", "st1">;
3422 def ST1_4V_1D : NeonI_STVList<0, 0b0010, 0b11, VQuad1D_operand, "st1">;
3423
3424 // End of vector load/store multiple N-element structure(class SIMD lselem)
3425
3426 // The followings are post-index vector load/store multiple N-element
3427 // structure(class SIMD lselem-post)
3428 def exact8_asmoperand : AsmOperandClass {
3429   let Name = "Exact8";
3430   let PredicateMethod = "isExactImm<8>";
3431   let RenderMethod = "addImmOperands";
3432 }
3433 def uimm_exact8 : Operand<i32>, ImmLeaf<i32, [{return Imm == 8;}]> {
3434   let ParserMatchClass = exact8_asmoperand;
3435 }
3436
3437 def exact16_asmoperand : AsmOperandClass {
3438   let Name = "Exact16";
3439   let PredicateMethod = "isExactImm<16>";
3440   let RenderMethod = "addImmOperands";
3441 }
3442 def uimm_exact16 : Operand<i32>, ImmLeaf<i32, [{return Imm == 16;}]> {
3443   let ParserMatchClass = exact16_asmoperand;
3444 }
3445
3446 def exact24_asmoperand : AsmOperandClass {
3447   let Name = "Exact24";
3448   let PredicateMethod = "isExactImm<24>";
3449   let RenderMethod = "addImmOperands";
3450 }
3451 def uimm_exact24 : Operand<i32>, ImmLeaf<i32, [{return Imm == 24;}]> {
3452   let ParserMatchClass = exact24_asmoperand;
3453 }
3454
3455 def exact32_asmoperand : AsmOperandClass {
3456   let Name = "Exact32";
3457   let PredicateMethod = "isExactImm<32>";
3458   let RenderMethod = "addImmOperands";
3459 }
3460 def uimm_exact32 : Operand<i32>, ImmLeaf<i32, [{return Imm == 32;}]> {
3461   let ParserMatchClass = exact32_asmoperand;
3462 }
3463
3464 def exact48_asmoperand : AsmOperandClass {
3465   let Name = "Exact48";
3466   let PredicateMethod = "isExactImm<48>";
3467   let RenderMethod = "addImmOperands";
3468 }
3469 def uimm_exact48 : Operand<i32>, ImmLeaf<i32, [{return Imm == 48;}]> {
3470   let ParserMatchClass = exact48_asmoperand;
3471 }
3472
3473 def exact64_asmoperand : AsmOperandClass {
3474   let Name = "Exact64";
3475   let PredicateMethod = "isExactImm<64>";
3476   let RenderMethod = "addImmOperands";
3477 }
3478 def uimm_exact64 : Operand<i32>, ImmLeaf<i32, [{return Imm == 64;}]> {
3479   let ParserMatchClass = exact64_asmoperand;
3480 }
3481
3482 multiclass NeonI_LDWB_VList<bit q, bits<4> opcode, bits<2> size,
3483                            RegisterOperand VecList, Operand ImmTy,
3484                            string asmop> {
3485   let Constraints = "$Rn = $wb", mayLoad = 1, neverHasSideEffects = 1,
3486       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3487     def _fixed : NeonI_LdStMult_Post<q, 1, opcode, size,
3488                      (outs VecList:$Rt, GPR64xsp:$wb),
3489                      (ins GPR64xsp:$Rn, ImmTy:$amt),
3490                      asmop # "\t$Rt, [$Rn], $amt",
3491                      [],
3492                      NoItinerary> {
3493       let Rm = 0b11111;
3494     }
3495
3496     def _register : NeonI_LdStMult_Post<q, 1, opcode, size,
3497                         (outs VecList:$Rt, GPR64xsp:$wb),
3498                         (ins GPR64xsp:$Rn, GPR64noxzr:$Rm),
3499                         asmop # "\t$Rt, [$Rn], $Rm",
3500                         [],
3501                         NoItinerary>;
3502   }
3503 }
3504
3505 multiclass LDWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3506     Operand ImmTy2, string asmop> {
3507   defm _8B : NeonI_LDWB_VList<0, opcode, 0b00,
3508                               !cast<RegisterOperand>(List # "8B_operand"),
3509                               ImmTy, asmop>;
3510
3511   defm _4H : NeonI_LDWB_VList<0, opcode, 0b01,
3512                               !cast<RegisterOperand>(List # "4H_operand"),
3513                               ImmTy, asmop>;
3514
3515   defm _2S : NeonI_LDWB_VList<0, opcode, 0b10,
3516                               !cast<RegisterOperand>(List # "2S_operand"),
3517                               ImmTy, asmop>;
3518
3519   defm _16B : NeonI_LDWB_VList<1, opcode, 0b00,
3520                                !cast<RegisterOperand>(List # "16B_operand"),
3521                                ImmTy2, asmop>;
3522
3523   defm _8H : NeonI_LDWB_VList<1, opcode, 0b01,
3524                               !cast<RegisterOperand>(List # "8H_operand"),
3525                               ImmTy2, asmop>;
3526
3527   defm _4S : NeonI_LDWB_VList<1, opcode, 0b10,
3528                               !cast<RegisterOperand>(List # "4S_operand"),
3529                               ImmTy2, asmop>;
3530
3531   defm _2D : NeonI_LDWB_VList<1, opcode, 0b11,
3532                               !cast<RegisterOperand>(List # "2D_operand"),
3533                               ImmTy2, asmop>;
3534 }
3535
3536 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3537 defm LD1WB : LDWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "ld1">;
3538 defm LD1WB_1D : NeonI_LDWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3539                                  "ld1">;
3540
3541 defm LD2WB : LDWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "ld2">;
3542
3543 defm LD3WB : LDWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3544                              "ld3">;
3545
3546 defm LD4WB : LDWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "ld4">;
3547
3548 // Post-index load multiple 1-element structures from N consecutive registers
3549 // (N = 2,3,4)
3550 defm LD1WB2V : LDWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3551                                "ld1">;
3552 defm LD1WB2V_1D : NeonI_LDWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3553                                    uimm_exact16, "ld1">;
3554
3555 defm LD1WB3V : LDWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3556                                "ld1">;
3557 defm LD1WB3V_1D : NeonI_LDWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3558                                    uimm_exact24, "ld1">;
3559
3560 defm LD1WB_4V : LDWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3561                                 "ld1">;
3562 defm LD1WB4V_1D : NeonI_LDWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3563                                    uimm_exact32, "ld1">;
3564
3565 multiclass NeonI_STWB_VList<bit q, bits<4> opcode, bits<2> size,
3566                             RegisterOperand VecList, Operand ImmTy,
3567                             string asmop> {
3568   let Constraints = "$Rn = $wb", mayStore = 1, neverHasSideEffects = 1,
3569       DecoderMethod = "DecodeVLDSTPostInstruction" in {
3570     def _fixed : NeonI_LdStMult_Post<q, 0, opcode, size,
3571                      (outs GPR64xsp:$wb),
3572                      (ins GPR64xsp:$Rn, ImmTy:$amt, VecList:$Rt),
3573                      asmop # "\t$Rt, [$Rn], $amt",
3574                      [],
3575                      NoItinerary> {
3576       let Rm = 0b11111;
3577     }
3578
3579     def _register : NeonI_LdStMult_Post<q, 0, opcode, size,
3580                       (outs GPR64xsp:$wb),
3581                       (ins GPR64xsp:$Rn, GPR64noxzr:$Rm, VecList:$Rt),
3582                       asmop # "\t$Rt, [$Rn], $Rm",
3583                       [],
3584                       NoItinerary>;
3585   }
3586 }
3587
3588 multiclass STWB_VList_BHSD<bits<4> opcode, string List, Operand ImmTy,
3589                            Operand ImmTy2, string asmop> {
3590   defm _8B : NeonI_STWB_VList<0, opcode, 0b00,
3591                  !cast<RegisterOperand>(List # "8B_operand"), ImmTy, asmop>;
3592
3593   defm _4H : NeonI_STWB_VList<0, opcode, 0b01,
3594                               !cast<RegisterOperand>(List # "4H_operand"),
3595                               ImmTy, asmop>;
3596
3597   defm _2S : NeonI_STWB_VList<0, opcode, 0b10,
3598                               !cast<RegisterOperand>(List # "2S_operand"),
3599                               ImmTy, asmop>;
3600
3601   defm _16B : NeonI_STWB_VList<1, opcode, 0b00,
3602                                !cast<RegisterOperand>(List # "16B_operand"),
3603                                ImmTy2, asmop>;
3604
3605   defm _8H : NeonI_STWB_VList<1, opcode, 0b01,
3606                               !cast<RegisterOperand>(List # "8H_operand"),
3607                               ImmTy2, asmop>;
3608
3609   defm _4S : NeonI_STWB_VList<1, opcode, 0b10,
3610                               !cast<RegisterOperand>(List # "4S_operand"),
3611                               ImmTy2, asmop>;
3612
3613   defm _2D : NeonI_STWB_VList<1, opcode, 0b11,
3614                               !cast<RegisterOperand>(List # "2D_operand"),
3615                               ImmTy2, asmop>;
3616 }
3617
3618 // Post-index load multiple N-element structures from N registers (N = 1,2,3,4)
3619 defm ST1WB : STWB_VList_BHSD<0b0111, "VOne", uimm_exact8, uimm_exact16, "st1">;
3620 defm ST1WB_1D : NeonI_STWB_VList<0, 0b0111, 0b11, VOne1D_operand, uimm_exact8,
3621                                  "st1">;
3622
3623 defm ST2WB : STWB_VList_BHSD<0b1000, "VPair", uimm_exact16, uimm_exact32, "st2">;
3624
3625 defm ST3WB : STWB_VList_BHSD<0b0100, "VTriple", uimm_exact24, uimm_exact48,
3626                              "st3">;
3627
3628 defm ST4WB : STWB_VList_BHSD<0b0000, "VQuad", uimm_exact32, uimm_exact64, "st4">;
3629
3630 // Post-index load multiple 1-element structures from N consecutive registers
3631 // (N = 2,3,4)
3632 defm ST1WB2V : STWB_VList_BHSD<0b1010, "VPair", uimm_exact16, uimm_exact32,
3633                                "st1">;
3634 defm ST1WB2V_1D : NeonI_STWB_VList<0, 0b1010, 0b11, VPair1D_operand,
3635                                    uimm_exact16, "st1">;
3636
3637 defm ST1WB3V : STWB_VList_BHSD<0b0110, "VTriple", uimm_exact24, uimm_exact48,
3638                                "st1">;
3639 defm ST1WB3V_1D : NeonI_STWB_VList<0, 0b0110, 0b11, VTriple1D_operand,
3640                                    uimm_exact24, "st1">;
3641
3642 defm ST1WB4V : STWB_VList_BHSD<0b0010, "VQuad", uimm_exact32, uimm_exact64,
3643                                "st1">;
3644 defm ST1WB4V_1D : NeonI_STWB_VList<0, 0b0010, 0b11, VQuad1D_operand,
3645                                    uimm_exact32, "st1">;
3646
3647 // End of post-index vector load/store multiple N-element structure
3648 // (class SIMD lselem-post)
3649
3650 // Scalar Three Same
3651
3652 class NeonI_Scalar3Same_size<bit u, bits<2> size, bits<5> opcode, string asmop,
3653                              RegisterClass FPRC>
3654   : NeonI_Scalar3Same<u, size, opcode,
3655                       (outs FPRC:$Rd), (ins FPRC:$Rn, FPRC:$Rm),
3656                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3657                       [],
3658                       NoItinerary>;
3659
3660 class NeonI_Scalar3Same_D_size<bit u, bits<5> opcode, string asmop>
3661   : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
3662
3663 multiclass NeonI_Scalar3Same_HS_sizes<bit u, bits<5> opcode, string asmop,
3664                                       bit Commutable = 0> {
3665   let isCommutable = Commutable in {
3666     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
3667     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
3668   }
3669 }
3670
3671 multiclass NeonI_Scalar3Same_SD_sizes<bit u, bit size_high, bits<5> opcode,
3672                                       string asmop, bit Commutable = 0> {
3673   let isCommutable = Commutable in {
3674     def sss : NeonI_Scalar3Same_size<u, {size_high, 0b0}, opcode, asmop, FPR32>;
3675     def ddd : NeonI_Scalar3Same_size<u, {size_high, 0b1}, opcode, asmop, FPR64>;
3676   }
3677 }
3678
3679 multiclass NeonI_Scalar3Same_BHSD_sizes<bit u, bits<5> opcode,
3680                                         string asmop, bit Commutable = 0> {
3681   let isCommutable = Commutable in {
3682     def bbb : NeonI_Scalar3Same_size<u, 0b00, opcode, asmop, FPR8>;
3683     def hhh : NeonI_Scalar3Same_size<u, 0b01, opcode, asmop, FPR16>;
3684     def sss : NeonI_Scalar3Same_size<u, 0b10, opcode, asmop, FPR32>;
3685     def ddd : NeonI_Scalar3Same_size<u, 0b11, opcode, asmop, FPR64>;
3686   }
3687 }
3688
3689 multiclass Neon_Scalar3Same_D_size_patterns<SDPatternOperator opnode,
3690                                             Instruction INSTD> {
3691   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
3692             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3693 }
3694
3695 multiclass Neon_Scalar3Same_BHSD_size_patterns<SDPatternOperator opnode,
3696                                                Instruction INSTB,
3697                                                Instruction INSTH,
3698                                                Instruction INSTS,
3699                                                Instruction INSTD>
3700   : Neon_Scalar3Same_D_size_patterns<opnode, INSTD> {
3701   def: Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (v1i8 FPR8:$Rm))),
3702            (INSTB FPR8:$Rn, FPR8:$Rm)>;
3703
3704   def: Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3705            (INSTH FPR16:$Rn, FPR16:$Rm)>;
3706
3707   def: Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3708            (INSTS FPR32:$Rn, FPR32:$Rm)>;
3709 }
3710
3711 class Neon_Scalar3Same_cmp_D_size_patterns<SDPatternOperator opnode,
3712                                            Instruction INSTD>
3713   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm))),
3714         (INSTD FPR64:$Rn, FPR64:$Rm)>;
3715
3716 multiclass Neon_Scalar3Same_HS_size_patterns<SDPatternOperator opnode,
3717                                              Instruction INSTH,
3718                                              Instruction INSTS> {
3719   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3720             (INSTH FPR16:$Rn, FPR16:$Rm)>;
3721   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3722             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3723 }
3724
3725 multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
3726                                              Instruction INSTS,
3727                                              Instruction INSTD> {
3728   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
3729             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3730   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3731             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3732 }
3733
3734 multiclass Neon_Scalar3Same_cmp_SD_size_patterns<SDPatternOperator opnode,
3735                                                  Instruction INSTS,
3736                                                  Instruction INSTD> {
3737   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn), (v1f32 FPR32:$Rm))),
3738             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3739   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
3740             (INSTD FPR64:$Rn, FPR64:$Rm)>;
3741 }
3742
3743 // Scalar Three Different
3744
3745 class NeonI_Scalar3Diff_size<bit u, bits<2> size, bits<4> opcode, string asmop,
3746                              RegisterClass FPRCD, RegisterClass FPRCS>
3747   : NeonI_Scalar3Diff<u, size, opcode,
3748                       (outs FPRCD:$Rd), (ins FPRCS:$Rn, FPRCS:$Rm),
3749                       !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3750                       [],
3751                       NoItinerary>;
3752
3753 multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
3754   def shh : NeonI_Scalar3Diff_size<u, 0b01, opcode, asmop, FPR32, FPR16>;
3755   def dss : NeonI_Scalar3Diff_size<u, 0b10, opcode, asmop, FPR64, FPR32>;
3756 }
3757
3758 multiclass NeonI_Scalar3Diff_ml_HS_size<bit u, bits<4> opcode, string asmop> {
3759   let Constraints = "$Src = $Rd" in {
3760     def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
3761                        (outs FPR32:$Rd), (ins FPR32:$Src, FPR16:$Rn, FPR16:$Rm),
3762                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3763                        [],
3764                        NoItinerary>;
3765     def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
3766                        (outs FPR64:$Rd), (ins FPR64:$Src, FPR32:$Rn, FPR32:$Rm),
3767                        !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
3768                        [],
3769                        NoItinerary>;
3770   }
3771 }
3772
3773 multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
3774                                              Instruction INSTH,
3775                                              Instruction INSTS> {
3776   def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3777             (INSTH FPR16:$Rn, FPR16:$Rm)>;
3778   def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3779             (INSTS FPR32:$Rn, FPR32:$Rm)>;
3780 }
3781
3782 multiclass Neon_Scalar3Diff_ml_HS_size_patterns<SDPatternOperator opnode,
3783                                              Instruction INSTH,
3784                                              Instruction INSTS> {
3785   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
3786             (INSTH FPR32:$Src, FPR16:$Rn, FPR16:$Rm)>;
3787   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
3788             (INSTS FPR64:$Src, FPR32:$Rn, FPR32:$Rm)>;
3789 }
3790
3791 // Scalar Two Registers Miscellaneous
3792
3793 class NeonI_Scalar2SameMisc_size<bit u, bits<2> size, bits<5> opcode, string asmop,
3794                              RegisterClass FPRCD, RegisterClass FPRCS>
3795   : NeonI_Scalar2SameMisc<u, size, opcode,
3796                           (outs FPRCD:$Rd), (ins FPRCS:$Rn),
3797                           !strconcat(asmop, "\t$Rd, $Rn"),
3798                           [],
3799                           NoItinerary>;
3800
3801 multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
3802                                          string asmop> {
3803   def ss : NeonI_Scalar2SameMisc_size<u, {size_high, 0b0}, opcode, asmop, FPR32,
3804                                       FPR32>;
3805   def dd : NeonI_Scalar2SameMisc_size<u, {size_high, 0b1}, opcode, asmop, FPR64,
3806                                       FPR64>;
3807 }
3808
3809 multiclass NeonI_Scalar2SameMisc_D_size<bit u, bits<5> opcode, string asmop> {
3810   def dd: NeonI_Scalar2SameMisc_size<u, 0b11, opcode, asmop, FPR64, FPR64>;
3811 }
3812
3813 multiclass NeonI_Scalar2SameMisc_BHSD_size<bit u, bits<5> opcode, string asmop>
3814   : NeonI_Scalar2SameMisc_D_size<u, opcode, asmop> {
3815   def bb : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR8>;
3816   def hh : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR16>;
3817   def ss : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR32>;
3818 }
3819
3820 multiclass NeonI_Scalar2SameMisc_narrow_HSD_size<bit u, bits<5> opcode,
3821                                                  string asmop> {
3822   def bh : NeonI_Scalar2SameMisc_size<u, 0b00, opcode, asmop, FPR8, FPR16>;
3823   def hs : NeonI_Scalar2SameMisc_size<u, 0b01, opcode, asmop, FPR16, FPR32>;
3824   def sd : NeonI_Scalar2SameMisc_size<u, 0b10, opcode, asmop, FPR32, FPR64>;
3825 }
3826
3827 class NeonI_Scalar2SameMisc_accum_size<bit u, bits<2> size, bits<5> opcode,
3828                                        string asmop, RegisterClass FPRC>
3829   : NeonI_Scalar2SameMisc<u, size, opcode,
3830                           (outs FPRC:$Rd), (ins FPRC:$Src, FPRC:$Rn),
3831                           !strconcat(asmop, "\t$Rd, $Rn"),
3832                           [],
3833                           NoItinerary>;
3834
3835 multiclass NeonI_Scalar2SameMisc_accum_BHSD_size<bit u, bits<5> opcode,
3836                                                  string asmop> {
3837
3838   let Constraints = "$Src = $Rd" in {
3839     def bb : NeonI_Scalar2SameMisc_accum_size<u, 0b00, opcode, asmop, FPR8>;
3840     def hh : NeonI_Scalar2SameMisc_accum_size<u, 0b01, opcode, asmop, FPR16>;
3841     def ss : NeonI_Scalar2SameMisc_accum_size<u, 0b10, opcode, asmop, FPR32>;
3842     def dd : NeonI_Scalar2SameMisc_accum_size<u, 0b11, opcode, asmop, FPR64>;
3843   }
3844 }
3845
3846 multiclass Neon_Scalar2SameMisc_cvt_SD_size_patterns<SDPatternOperator Sopnode,
3847                                                      SDPatternOperator Dopnode,
3848                                                      Instruction INSTS,
3849                                                      Instruction INSTD> {
3850   def : Pat<(v1f32 (Sopnode (v1i32 FPR32:$Rn))),
3851             (INSTS FPR32:$Rn)>;
3852   def : Pat<(v1f64 (Dopnode (v1i64 FPR64:$Rn))),
3853             (INSTD FPR64:$Rn)>;
3854 }
3855
3856 multiclass Neon_Scalar2SameMisc_SD_size_patterns<SDPatternOperator opnode,
3857                                                  Instruction INSTS,
3858                                                  Instruction INSTD> {
3859   def : Pat<(v1f32 (opnode (v1f32 FPR32:$Rn))),
3860             (INSTS FPR32:$Rn)>;
3861   def : Pat<(v1f64 (opnode (v1f64 FPR64:$Rn))),
3862             (INSTD FPR64:$Rn)>;
3863 }
3864
3865 class NeonI_Scalar2SameMisc_cmpz_D_size<bit u, bits<5> opcode, string asmop>
3866   : NeonI_Scalar2SameMisc<u, 0b11, opcode,
3867                           (outs FPR64:$Rd), (ins FPR64:$Rn, neon_uimm0:$Imm),
3868                           !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3869                           [],
3870                           NoItinerary>;
3871
3872 multiclass NeonI_Scalar2SameMisc_cmpz_SD_size<bit u, bits<5> opcode,
3873                                               string asmop> {
3874   def ssi : NeonI_Scalar2SameMisc<u, 0b10, opcode,
3875                            (outs FPR32:$Rd), (ins FPR32:$Rn, fpz32:$FPImm),
3876                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
3877                            [],
3878                            NoItinerary>;
3879   def ddi : NeonI_Scalar2SameMisc<u, 0b11, opcode,
3880                            (outs FPR64:$Rd), (ins FPR64:$Rn, fpz64movi:$FPImm),
3881                            !strconcat(asmop, "\t$Rd, $Rn, $FPImm"),
3882                            [],
3883                            NoItinerary>;
3884 }
3885
3886 class Neon_Scalar2SameMisc_cmpz_D_size_patterns<SDPatternOperator opnode,
3887                                                 Instruction INSTD>
3888   : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn),
3889                        (v1i64 (bitconvert (v8i8 Neon_immAllZeros))))),
3890         (INSTD FPR64:$Rn, 0)>;
3891
3892 multiclass Neon_Scalar2SameMisc_cmpz_SD_size_patterns<SDPatternOperator opnode,
3893                                                       Instruction INSTS,
3894                                                       Instruction INSTD> {
3895   def : Pat<(v1i32 (opnode (v1f32 FPR32:$Rn),
3896                            (v1f32 (scalar_to_vector (f32 fpimm:$FPImm))))),
3897             (INSTS FPR32:$Rn, fpimm:$FPImm)>;
3898   def : Pat<(v1i64 (opnode (v1f64 FPR64:$Rn),
3899                            (v1f64 (bitconvert (v8i8 Neon_immAllZeros))))),
3900             (INSTD FPR64:$Rn, 0)>;
3901 }
3902
3903 multiclass Neon_Scalar2SameMisc_D_size_patterns<SDPatternOperator opnode,
3904                                                 Instruction INSTD> {
3905   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn))),
3906             (INSTD FPR64:$Rn)>;
3907 }
3908
3909 multiclass Neon_Scalar2SameMisc_BHSD_size_patterns<SDPatternOperator opnode,
3910                                                    Instruction INSTB,
3911                                                    Instruction INSTH,
3912                                                    Instruction INSTS,
3913                                                    Instruction INSTD>
3914   : Neon_Scalar2SameMisc_D_size_patterns<opnode, INSTD> {
3915   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn))),
3916             (INSTB FPR8:$Rn)>;
3917   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn))),
3918             (INSTH FPR16:$Rn)>;
3919   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn))),
3920             (INSTS FPR32:$Rn)>;
3921 }
3922
3923 multiclass Neon_Scalar2SameMisc_narrow_HSD_size_patterns<
3924                                                        SDPatternOperator opnode,
3925                                                        Instruction INSTH,
3926                                                        Instruction INSTS,
3927                                                        Instruction INSTD> {
3928   def : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn))),
3929             (INSTH FPR16:$Rn)>;
3930   def : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn))),
3931             (INSTS FPR32:$Rn)>;
3932   def : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn))),
3933             (INSTD FPR64:$Rn)>;
3934
3935 }
3936
3937 multiclass Neon_Scalar2SameMisc_accum_BHSD_size_patterns<
3938                                                        SDPatternOperator opnode,
3939                                                        Instruction INSTB,
3940                                                        Instruction INSTH,
3941                                                        Instruction INSTS,
3942                                                        Instruction INSTD> {
3943   def : Pat<(v1i8 (opnode (v1i8 FPR8:$Src), (v1i8 FPR8:$Rn))),
3944             (INSTB FPR8:$Src, FPR8:$Rn)>;
3945   def : Pat<(v1i16 (opnode (v1i16 FPR16:$Src), (v1i16 FPR16:$Rn))),
3946             (INSTH FPR16:$Src, FPR16:$Rn)>;
3947   def : Pat<(v1i32 (opnode (v1i32 FPR32:$Src), (v1i32 FPR32:$Rn))),
3948             (INSTS FPR32:$Src, FPR32:$Rn)>;
3949   def : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn))),
3950             (INSTD FPR64:$Src, FPR64:$Rn)>;
3951 }
3952
3953 // Scalar Shift By Immediate
3954
3955 class NeonI_ScalarShiftImm_size<bit u, bits<5> opcode, string asmop,
3956                                 RegisterClass FPRC, Operand ImmTy>
3957   : NeonI_ScalarShiftImm<u, opcode,
3958                          (outs FPRC:$Rd), (ins FPRC:$Rn, ImmTy:$Imm),
3959                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
3960                          [], NoItinerary>;
3961
3962 multiclass NeonI_ScalarShiftRightImm_D_size<bit u, bits<5> opcode,
3963                                             string asmop> {
3964   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
3965     bits<6> Imm;
3966     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
3967     let Inst{21-16} = Imm;
3968   }
3969 }
3970
3971 multiclass NeonI_ScalarShiftRightImm_BHSD_size<bit u, bits<5> opcode,
3972                                                string asmop>
3973   : NeonI_ScalarShiftRightImm_D_size<u, opcode, asmop> {
3974   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shr_imm8> {
3975     bits<3> Imm;
3976     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
3977     let Inst{18-16} = Imm;
3978   }
3979   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shr_imm16> {
3980     bits<4> Imm;
3981     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
3982     let Inst{19-16} = Imm;
3983   }
3984   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
3985     bits<5> Imm;
3986     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
3987     let Inst{20-16} = Imm;
3988   }
3989 }
3990
3991 multiclass NeonI_ScalarShiftLeftImm_D_size<bit u, bits<5> opcode,
3992                                             string asmop> {
3993   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shl_imm64> {
3994     bits<6> Imm;
3995     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
3996     let Inst{21-16} = Imm;
3997   }
3998 }
3999
4000 multiclass NeonI_ScalarShiftLeftImm_BHSD_size<bit u, bits<5> opcode,
4001                                               string asmop>
4002   : NeonI_ScalarShiftLeftImm_D_size<u, opcode, asmop> {
4003   def bbi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR8, shl_imm8> {
4004     bits<3> Imm;
4005     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4006     let Inst{18-16} = Imm;
4007   }
4008   def hhi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR16, shl_imm16> {
4009     bits<4> Imm;
4010     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4011     let Inst{19-16} = Imm;
4012   }
4013   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shl_imm32> {
4014     bits<5> Imm;
4015     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4016     let Inst{20-16} = Imm;
4017   }
4018 }
4019
4020 class NeonI_ScalarShiftImm_accum_D_size<bit u, bits<5> opcode, string asmop>
4021   : NeonI_ScalarShiftImm<u, opcode,
4022                          (outs FPR64:$Rd), (ins FPR64:$Src, FPR64:$Rn, shr_imm64:$Imm),
4023                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4024                          [], NoItinerary> {
4025     bits<6> Imm;
4026     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4027     let Inst{21-16} = Imm;
4028     let Constraints = "$Src = $Rd";
4029 }
4030
4031 class NeonI_ScalarShiftImm_narrow_size<bit u, bits<5> opcode, string asmop,
4032                                        RegisterClass FPRCD, RegisterClass FPRCS,
4033                                        Operand ImmTy>
4034   : NeonI_ScalarShiftImm<u, opcode,
4035                          (outs FPRCD:$Rd), (ins FPRCS:$Rn, ImmTy:$Imm),
4036                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
4037                          [], NoItinerary>;
4038
4039 multiclass NeonI_ScalarShiftImm_narrow_HSD_size<bit u, bits<5> opcode,
4040                                                 string asmop> {
4041   def bhi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR8, FPR16,
4042                                              shr_imm8> {
4043     bits<3> Imm;
4044     let Inst{22-19} = 0b0001; // immh:immb = 0001xxx
4045     let Inst{18-16} = Imm;
4046   }
4047   def hsi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR16, FPR32,
4048                                              shr_imm16> {
4049     bits<4> Imm;
4050     let Inst{22-20} = 0b001; // immh:immb = 001xxxx
4051     let Inst{19-16} = Imm;
4052   }
4053   def sdi : NeonI_ScalarShiftImm_narrow_size<u, opcode, asmop, FPR32, FPR64,
4054                                              shr_imm32> {
4055     bits<5> Imm;
4056     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4057     let Inst{20-16} = Imm;
4058   }
4059 }
4060
4061 multiclass NeonI_ScalarShiftImm_cvt_SD_size<bit u, bits<5> opcode, string asmop> {
4062   def ssi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR32, shr_imm32> {
4063     bits<5> Imm;
4064     let Inst{22-21} = 0b01; // immh:immb = 01xxxxx
4065     let Inst{20-16} = Imm;
4066   }
4067   def ddi : NeonI_ScalarShiftImm_size<u, opcode, asmop, FPR64, shr_imm64> {
4068     bits<6> Imm;
4069     let Inst{22} = 0b1; // immh:immb = 1xxxxxx
4070     let Inst{21-16} = Imm;
4071   }
4072 }
4073
4074 multiclass Neon_ScalarShiftImm_D_size_patterns<SDPatternOperator opnode,
4075                                                Instruction INSTD> {
4076   def ddi : Pat<(v1i64 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4077                 (INSTD FPR64:$Rn, imm:$Imm)>;
4078 }
4079
4080 multiclass Neon_ScalarShiftImm_BHSD_size_patterns<SDPatternOperator opnode,
4081                                                   Instruction INSTB,
4082                                                   Instruction INSTH,
4083                                                   Instruction INSTS,
4084                                                   Instruction INSTD>
4085   : Neon_ScalarShiftImm_D_size_patterns<opnode, INSTD> {
4086   def bbi : Pat<(v1i8 (opnode (v1i8 FPR8:$Rn), (i32 imm:$Imm))),
4087                 (INSTB FPR8:$Rn, imm:$Imm)>;
4088   def hhi : Pat<(v1i16 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4089                 (INSTH FPR16:$Rn, imm:$Imm)>;
4090   def ssi : Pat<(v1i32 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4091                 (INSTS FPR32:$Rn, imm:$Imm)>;
4092 }
4093
4094 class Neon_ScalarShiftImm_accum_D_size_patterns<SDPatternOperator opnode,
4095                                           Instruction INSTD>
4096   : Pat<(v1i64 (opnode (v1i64 FPR64:$Src), (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4097         (INSTD FPR64:$Src, FPR64:$Rn, imm:$Imm)>;
4098
4099 multiclass Neon_ScalarShiftImm_narrow_HSD_size_patterns<
4100                                                        SDPatternOperator opnode,
4101                                                        Instruction INSTH,
4102                                                        Instruction INSTS,
4103                                                        Instruction INSTD> {
4104   def bhi : Pat<(v1i8 (opnode (v1i16 FPR16:$Rn), (i32 imm:$Imm))),
4105                 (INSTH FPR16:$Rn, imm:$Imm)>;
4106   def hsi : Pat<(v1i16 (opnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4107                 (INSTS FPR32:$Rn, imm:$Imm)>;
4108   def sdi : Pat<(v1i32 (opnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4109                 (INSTD FPR64:$Rn, imm:$Imm)>;
4110 }
4111
4112 multiclass Neon_ScalarShiftImm_scvtf_SD_size_patterns<SDPatternOperator Sopnode,
4113                                                       SDPatternOperator Dopnode,
4114                                                       Instruction INSTS,
4115                                                       Instruction INSTD> {
4116   def ssi : Pat<(v1f32 (Sopnode (v1i32 FPR32:$Rn), (i32 imm:$Imm))),
4117                 (INSTS FPR32:$Rn, imm:$Imm)>;
4118   def ddi : Pat<(v1f64 (Dopnode (v1i64 FPR64:$Rn), (i32 imm:$Imm))),
4119                 (INSTD FPR64:$Rn, imm:$Imm)>;
4120 }
4121
4122 multiclass Neon_ScalarShiftImm_fcvts_SD_size_patterns<SDPatternOperator Sopnode,
4123                                                       SDPatternOperator Dopnode,
4124                                                       Instruction INSTS,
4125                                                       Instruction INSTD> {
4126   def ssi : Pat<(v1i32 (Sopnode (v1f32 FPR32:$Rn), (i32 imm:$Imm))),
4127                 (INSTS FPR32:$Rn, imm:$Imm)>;
4128   def ddi : Pat<(v1i64 (Dopnode (v1f64 FPR64:$Rn), (i32 imm:$Imm))),
4129                 (INSTD FPR64:$Rn, imm:$Imm)>;
4130 }
4131
4132 // Scalar Signed Shift Right (Immediate)
4133 defm SSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00000, "sshr">;
4134 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrds_n, SSHRddi>;
4135
4136 // Scalar Unsigned Shift Right (Immediate)
4137 defm USHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00000, "ushr">;
4138 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshrdu_n, USHRddi>;
4139
4140 // Scalar Signed Rounding Shift Right (Immediate)
4141 defm SRSHR : NeonI_ScalarShiftRightImm_D_size<0b0, 0b00100, "srshr">;
4142 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vrshrds_n, SRSHRddi>;
4143
4144 // Scalar Unigned Rounding Shift Right (Immediate)
4145 defm URSHR : NeonI_ScalarShiftRightImm_D_size<0b1, 0b00100, "urshr">;
4146 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vrshrdu_n, URSHRddi>;
4147
4148 // Scalar Signed Shift Right and Accumulate (Immediate)
4149 def SSRA : NeonI_ScalarShiftImm_accum_D_size<0b0, 0b00010, "ssra">;
4150 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsrads_n, SSRA>;
4151
4152 // Scalar Unsigned Shift Right and Accumulate (Immediate)
4153 def USRA : NeonI_ScalarShiftImm_accum_D_size<0b1, 0b00010, "usra">;
4154 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vsradu_n, USRA>;
4155
4156 // Scalar Signed Rounding Shift Right and Accumulate (Immediate)
4157 def SRSRA : NeonI_ScalarShiftImm_accum_D_size<0b0, 0b00110, "srsra">;
4158 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsrads_n, SRSRA>;
4159
4160 // Scalar Unsigned Rounding Shift Right and Accumulate (Immediate)
4161 def URSRA : NeonI_ScalarShiftImm_accum_D_size<0b1, 0b00110, "ursra">;
4162 def : Neon_ScalarShiftImm_accum_D_size_patterns<int_aarch64_neon_vrsradu_n, URSRA>;
4163
4164 // Scalar Shift Left (Immediate)
4165 defm SHL : NeonI_ScalarShiftLeftImm_D_size<0b0, 0b01010, "shl">;
4166 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vshld_n, SHLddi>;
4167
4168 // Signed Saturating Shift Left (Immediate)
4169 defm SQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b0, 0b01110, "sqshl">;
4170 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshls_n,
4171                                               SQSHLbbi, SQSHLhhi,
4172                                               SQSHLssi, SQSHLddi>;
4173
4174 // Unsigned Saturating Shift Left (Immediate)
4175 defm UQSHL : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01110, "uqshl">;
4176 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshlu_n,
4177                                               UQSHLbbi, UQSHLhhi,
4178                                               UQSHLssi, UQSHLddi>;
4179
4180 // Signed Saturating Shift Left Unsigned (Immediate)
4181 defm SQSHLU : NeonI_ScalarShiftLeftImm_BHSD_size<0b1, 0b01100, "sqshlu">;
4182 defm : Neon_ScalarShiftImm_BHSD_size_patterns<int_aarch64_neon_vqshlus_n,
4183                                               SQSHLUbbi, SQSHLUhhi,
4184                                               SQSHLUssi, SQSHLUddi>;
4185
4186 // Shift Right And Insert (Immediate)
4187 defm SRI : NeonI_ScalarShiftRightImm_D_size<0b1, 0b01000, "sri">;
4188 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vsrid_n, SRIddi>;
4189
4190 // Shift Left And Insert (Immediate)
4191 defm SLI : NeonI_ScalarShiftLeftImm_D_size<0b1, 0b01010, "sli">;
4192 defm : Neon_ScalarShiftImm_D_size_patterns<int_aarch64_neon_vslid_n, SLIddi>;
4193
4194 // Signed Saturating Shift Right Narrow (Immediate)
4195 defm SQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10010, "sqshrn">;
4196 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrn,
4197                                                     SQSHRNbhi, SQSHRNhsi,
4198                                                     SQSHRNsdi>;
4199
4200 // Unsigned Saturating Shift Right Narrow (Immediate)
4201 defm UQSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10010, "uqshrn">;
4202 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqshrn,
4203                                                     UQSHRNbhi, UQSHRNhsi,
4204                                                     UQSHRNsdi>;
4205
4206 // Signed Saturating Rounded Shift Right Narrow (Immediate)
4207 defm SQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b0, 0b10011, "sqrshrn">;
4208 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrn,
4209                                                     SQRSHRNbhi, SQRSHRNhsi,
4210                                                     SQRSHRNsdi>;
4211
4212 // Unsigned Saturating Rounded Shift Right Narrow (Immediate)
4213 defm UQRSHRN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10011, "uqrshrn">;
4214 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vuqrshrn,
4215                                                     UQRSHRNbhi, UQRSHRNhsi,
4216                                                     UQRSHRNsdi>;
4217
4218 // Signed Saturating Shift Right Unsigned Narrow (Immediate)
4219 defm SQSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10000, "sqshrun">;
4220 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqshrun,
4221                                                     SQSHRUNbhi, SQSHRUNhsi,
4222                                                     SQSHRUNsdi>;
4223
4224 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate)
4225 defm SQRSHRUN : NeonI_ScalarShiftImm_narrow_HSD_size<0b1, 0b10001, "sqrshrun">;
4226 defm : Neon_ScalarShiftImm_narrow_HSD_size_patterns<int_aarch64_neon_vsqrshrun,
4227                                                     SQRSHRUNbhi, SQRSHRUNhsi,
4228                                                     SQRSHRUNsdi>;
4229
4230 // Scalar Signed Fixed-point Convert To Floating-Point (Immediate)
4231 defm SCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11100, "scvtf">;
4232 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_s32,
4233                                                   int_aarch64_neon_vcvtf64_n_s64,
4234                                                   SCVTF_Nssi, SCVTF_Nddi>;
4235
4236 // Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate)
4237 defm UCVTF_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11100, "ucvtf">;
4238 defm : Neon_ScalarShiftImm_scvtf_SD_size_patterns<int_aarch64_neon_vcvtf32_n_u32,
4239                                                   int_aarch64_neon_vcvtf64_n_u64,
4240                                                   UCVTF_Nssi, UCVTF_Nddi>;
4241
4242 // Scalar Floating-point Convert To Signed Fixed-point (Immediate)
4243 defm FCVTZS_N : NeonI_ScalarShiftImm_cvt_SD_size<0b0, 0b11111, "fcvtzs">;
4244 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_s32_f32,
4245                                                   int_aarch64_neon_vcvtd_n_s64_f64,
4246                                                   FCVTZS_Nssi, FCVTZS_Nddi>;
4247
4248 // Scalar Floating-point Convert To Unsigned Fixed-point (Immediate)
4249 defm FCVTZU_N : NeonI_ScalarShiftImm_cvt_SD_size<0b1, 0b11111, "fcvtzu">;
4250 defm : Neon_ScalarShiftImm_fcvts_SD_size_patterns<int_aarch64_neon_vcvts_n_u32_f32,
4251                                                   int_aarch64_neon_vcvtd_n_u64_f64,
4252                                                   FCVTZU_Nssi, FCVTZU_Nddi>;
4253
4254 // Scalar Integer Add
4255 let isCommutable = 1 in {
4256 def ADDddd : NeonI_Scalar3Same_D_size<0b0, 0b10000, "add">;
4257 }
4258
4259 // Scalar Integer Sub
4260 def SUBddd : NeonI_Scalar3Same_D_size<0b1, 0b10000, "sub">;
4261
4262 // Pattern for Scalar Integer Add and Sub with D register only
4263 defm : Neon_Scalar3Same_D_size_patterns<add, ADDddd>;
4264 defm : Neon_Scalar3Same_D_size_patterns<sub, SUBddd>;
4265
4266 // Patterns to match llvm.aarch64.* intrinsic for Scalar Add, Sub
4267 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vaddds, ADDddd>;
4268 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vadddu, ADDddd>;
4269 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubds, SUBddd>;
4270 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vsubdu, SUBddd>;
4271
4272 // Scalar Integer Saturating Add (Signed, Unsigned)
4273 defm SQADD : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00001, "sqadd", 1>;
4274 defm UQADD : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00001, "uqadd", 1>;
4275
4276 // Scalar Integer Saturating Sub (Signed, Unsigned)
4277 defm SQSUB : NeonI_Scalar3Same_BHSD_sizes<0b0, 0b00101, "sqsub", 0>;
4278 defm UQSUB : NeonI_Scalar3Same_BHSD_sizes<0b1, 0b00101, "uqsub", 0>;
4279
4280 // Patterns to match llvm.arm.* intrinsic for
4281 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
4282 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqadds, SQADDddd>;
4283 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqaddu, UQADDddd>;
4284 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubs, SQSUBddd>;
4285 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqsubu, UQSUBddd>;
4286
4287 // Patterns to match llvm.aarch64.* intrinsic for
4288 // Scalar Integer Saturating Add, Sub  (Signed, Unsigned)
4289 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqadds, SQADDbbb,
4290                                            SQADDhhh, SQADDsss, SQADDddd>;
4291 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqaddu, UQADDbbb,
4292                                            UQADDhhh, UQADDsss, UQADDddd>;
4293 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubs, SQSUBbbb,
4294                                            SQSUBhhh, SQSUBsss, SQSUBddd>;
4295 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqsubu, UQSUBbbb,
4296                                            UQSUBhhh, UQSUBsss, UQSUBddd>;
4297
4298 // Scalar Integer Saturating Doubling Multiply Half High
4299 defm SQDMULH : NeonI_Scalar3Same_HS_sizes<0b0, 0b10110, "sqdmulh", 1>;
4300
4301 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4302 defm SQRDMULH : NeonI_Scalar3Same_HS_sizes<0b1, 0b10110, "sqrdmulh", 1>;
4303
4304 // Patterns to match llvm.arm.* intrinsic for
4305 // Scalar Integer Saturating Doubling Multiply Half High and
4306 // Scalar Integer Saturating Rounding Doubling Multiply Half High
4307 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqdmulh, SQDMULHhhh,
4308                                                                SQDMULHsss>;
4309 defm : Neon_Scalar3Same_HS_size_patterns<int_arm_neon_vqrdmulh, SQRDMULHhhh,
4310                                                                 SQRDMULHsss>;
4311
4312 // Scalar Floating-point Multiply Extended
4313 defm FMULX : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11011, "fmulx", 1>;
4314
4315 // Scalar Floating-point Reciprocal Step
4316 defm FRECPS : NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11111, "frecps", 0>;
4317
4318 // Scalar Floating-point Reciprocal Square Root Step
4319 defm FRSQRTS : NeonI_Scalar3Same_SD_sizes<0b0, 0b1, 0b11111, "frsqrts", 0>;
4320
4321 // Patterns to match llvm.arm.* intrinsic for
4322 // Scalar Floating-point Reciprocal Step and
4323 // Scalar Floating-point Reciprocal Square Root Step
4324 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrecps, FRECPSsss,
4325                                                               FRECPSddd>;
4326 defm : Neon_Scalar3Same_SD_size_patterns<int_arm_neon_vrsqrts, FRSQRTSsss,
4327                                                                FRSQRTSddd>;
4328
4329 // Patterns to match llvm.aarch64.* intrinsic for
4330 // Scalar Floating-point Multiply Extended,
4331 defm : Neon_Scalar3Same_SD_size_patterns<int_aarch64_neon_vmulx, FMULXsss,
4332                                          FMULXddd>;
4333
4334 // Scalar Integer Shift Left (Signed, Unsigned)
4335 def SSHLddd : NeonI_Scalar3Same_D_size<0b0, 0b01000, "sshl">;
4336 def USHLddd : NeonI_Scalar3Same_D_size<0b1, 0b01000, "ushl">;
4337
4338 // Patterns to match llvm.arm.* intrinsic for
4339 // Scalar Integer Shift Left (Signed, Unsigned)
4340 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshifts, SSHLddd>;
4341 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vshiftu, USHLddd>;
4342
4343 // Patterns to match llvm.aarch64.* intrinsic for
4344 // Scalar Integer Shift Left (Signed, Unsigned)
4345 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshlds, SSHLddd>;
4346 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vshldu, USHLddd>;
4347
4348 // Scalar Integer Saturating Shift Left (Signed, Unsigned)
4349 defm SQSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01001, "sqshl", 0>;
4350 defm UQSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01001, "uqshl", 0>;
4351
4352 // Patterns to match llvm.aarch64.* intrinsic for
4353 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4354 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshls, SQSHLbbb,
4355                                            SQSHLhhh, SQSHLsss, SQSHLddd>;
4356 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqshlu, UQSHLbbb,
4357                                            UQSHLhhh, UQSHLsss, UQSHLddd>;
4358
4359 // Patterns to match llvm.arm.* intrinsic for
4360 // Scalar  Integer Saturating Shift Letf (Signed, Unsigned)
4361 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshifts, SQSHLddd>;
4362 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqshiftu, UQSHLddd>;
4363
4364 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4365 def SRSHLddd: NeonI_Scalar3Same_D_size<0b0, 0b01010, "srshl">;
4366 def URSHLddd: NeonI_Scalar3Same_D_size<0b1, 0b01010, "urshl">;
4367
4368 // Patterns to match llvm.aarch64.* intrinsic for
4369 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4370 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshlds, SRSHLddd>;
4371 defm : Neon_Scalar3Same_D_size_patterns<int_aarch64_neon_vrshldu, URSHLddd>;
4372
4373 // Patterns to match llvm.arm.* intrinsic for
4374 // Scalar Integer Rounding Shift Left (Signed, Unsigned)
4375 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshifts, SRSHLddd>;
4376 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vrshiftu, URSHLddd>;
4377
4378 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4379 defm SQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b0, 0b01011, "sqrshl", 0>;
4380 defm UQRSHL: NeonI_Scalar3Same_BHSD_sizes<0b1, 0b01011, "uqrshl", 0>;
4381
4382 // Patterns to match llvm.aarch64.* intrinsic for
4383 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4384 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshls, SQRSHLbbb,
4385                                            SQRSHLhhh, SQRSHLsss, SQRSHLddd>;
4386 defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
4387                                            UQRSHLhhh, UQRSHLsss, UQRSHLddd>;
4388
4389 // Patterns to match llvm.arm.* intrinsic for
4390 // Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned)
4391 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
4392 defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
4393
4394 // Signed Saturating Doubling Multiply-Add Long
4395 defm SQDMLAL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1001, "sqdmlal">;
4396 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlal,
4397                                             SQDMLALshh, SQDMLALdss>;
4398
4399 // Signed Saturating Doubling Multiply-Subtract Long
4400 defm SQDMLSL : NeonI_Scalar3Diff_ml_HS_size<0b0, 0b1011, "sqdmlsl">;
4401 defm : Neon_Scalar3Diff_ml_HS_size_patterns<int_aarch64_neon_vqdmlsl,
4402                                             SQDMLSLshh, SQDMLSLdss>;
4403
4404 // Signed Saturating Doubling Multiply Long
4405 defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
4406 defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmull,
4407                                          SQDMULLshh, SQDMULLdss>;
4408
4409 // Scalar Signed Integer Convert To Floating-point
4410 defm SCVTF  : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
4411 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
4412                                                  int_aarch64_neon_vcvtf64_s64,
4413                                                  SCVTFss, SCVTFdd>;
4414
4415 // Scalar Unsigned Integer Convert To Floating-point
4416 defm UCVTF  : NeonI_Scalar2SameMisc_SD_size<0b1, 0b0, 0b11101, "ucvtf">;
4417 defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_u32,
4418                                                  int_aarch64_neon_vcvtf64_u64,
4419                                                  UCVTFss, UCVTFdd>;
4420
4421 // Scalar Floating-point Reciprocal Estimate
4422 defm FRECPE : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11101, "frecpe">;
4423 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrecpe,
4424                                              FRECPEss, FRECPEdd>;
4425
4426 // Scalar Floating-point Reciprocal Exponent
4427 defm FRECPX : NeonI_Scalar2SameMisc_SD_size<0b0, 0b1, 0b11111, "frecpx">;
4428 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_aarch64_neon_vrecpx,
4429                                              FRECPXss, FRECPXdd>;
4430
4431 // Scalar Floating-point Reciprocal Square Root Estimate
4432 defm FRSQRTE: NeonI_Scalar2SameMisc_SD_size<0b1, 0b1, 0b11101, "frsqrte">;
4433 defm : Neon_Scalar2SameMisc_SD_size_patterns<int_arm_neon_vrsqrte,
4434                                              FRSQRTEss, FRSQRTEdd>;
4435
4436 // Scalar Integer Compare
4437
4438 // Scalar Compare Bitwise Equal
4439 def CMEQddd: NeonI_Scalar3Same_D_size<0b1, 0b10001, "cmeq">;
4440 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vceq, CMEQddd>;
4441
4442 // Scalar Compare Signed Greather Than Or Equal
4443 def CMGEddd: NeonI_Scalar3Same_D_size<0b0, 0b00111, "cmge">;
4444 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcge, CMGEddd>;
4445
4446 // Scalar Compare Unsigned Higher Or Same
4447 def CMHSddd: NeonI_Scalar3Same_D_size<0b1, 0b00111, "cmhs">;
4448 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchs, CMHSddd>;
4449
4450 // Scalar Compare Unsigned Higher
4451 def CMHIddd: NeonI_Scalar3Same_D_size<0b1, 0b00110, "cmhi">;
4452 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vchi, CMHIddd>;
4453
4454 // Scalar Compare Signed Greater Than
4455 def CMGTddd: NeonI_Scalar3Same_D_size<0b0, 0b00110, "cmgt">;
4456 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vcgt, CMGTddd>;
4457
4458 // Scalar Compare Bitwise Test Bits
4459 def CMTSTddd: NeonI_Scalar3Same_D_size<0b0, 0b10001, "cmtst">;
4460 def : Neon_Scalar3Same_cmp_D_size_patterns<int_aarch64_neon_vtstd, CMTSTddd>;
4461
4462 // Scalar Compare Bitwise Equal To Zero
4463 def CMEQddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01001, "cmeq">;
4464 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vceq,
4465                                                 CMEQddi>;
4466
4467 // Scalar Compare Signed Greather Than Or Equal To Zero
4468 def CMGEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01000, "cmge">;
4469 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcge,
4470                                                 CMGEddi>;
4471
4472 // Scalar Compare Signed Greater Than Zero
4473 def CMGTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01000, "cmgt">;
4474 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcgt,
4475                                                 CMGTddi>;
4476
4477 // Scalar Compare Signed Less Than Or Equal To Zero
4478 def CMLEddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b1, 0b01001, "cmle">;
4479 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vclez,
4480                                                 CMLEddi>;
4481
4482 // Scalar Compare Less Than Zero
4483 def CMLTddi: NeonI_Scalar2SameMisc_cmpz_D_size<0b0, 0b01010, "cmlt">;
4484 def : Neon_Scalar2SameMisc_cmpz_D_size_patterns<int_aarch64_neon_vcltz,
4485                                                 CMLTddi>;
4486
4487 // Scalar Floating-point Compare
4488
4489 // Scalar Floating-point Compare Mask Equal
4490 defm FCMEQ: NeonI_Scalar3Same_SD_sizes<0b0, 0b0, 0b11100, "fcmeq">;
4491 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vceq,
4492                                              FCMEQsss, FCMEQddd>;
4493
4494 // Scalar Floating-point Compare Mask Equal To Zero
4495 defm FCMEQZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01101, "fcmeq">;
4496 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vceq,
4497                                                   FCMEQZssi, FCMEQZddi>;
4498
4499 // Scalar Floating-point Compare Mask Greater Than Or Equal
4500 defm FCMGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11100, "fcmge">;
4501 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcge,
4502                                              FCMGEsss, FCMGEddd>;
4503
4504 // Scalar Floating-point Compare Mask Greater Than Or Equal To Zero
4505 defm FCMGEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01100, "fcmge">;
4506 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcge,
4507                                                   FCMGEZssi, FCMGEZddi>;
4508
4509 // Scalar Floating-point Compare Mask Greather Than
4510 defm FCMGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11100, "fcmgt">;
4511 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcgt,
4512                                              FCMGTsss, FCMGTddd>;
4513
4514 // Scalar Floating-point Compare Mask Greather Than Zero
4515 defm FCMGTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01100, "fcmgt">;
4516 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcgt,
4517                                                   FCMGTZssi, FCMGTZddi>;
4518
4519 // Scalar Floating-point Compare Mask Less Than Or Equal To Zero
4520 defm FCMLEZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b1, 0b01101, "fcmle">;
4521 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vclez,
4522                                                   FCMLEZssi, FCMLEZddi>;
4523
4524 // Scalar Floating-point Compare Mask Less Than Zero
4525 defm FCMLTZ: NeonI_Scalar2SameMisc_cmpz_SD_size<0b0, 0b01110, "fcmlt">;
4526 defm : Neon_Scalar2SameMisc_cmpz_SD_size_patterns<int_aarch64_neon_vcltz,
4527                                                   FCMLTZssi, FCMLTZddi>;
4528
4529 // Scalar Floating-point Absolute Compare Mask Greater Than Or Equal
4530 defm FACGE: NeonI_Scalar3Same_SD_sizes<0b1, 0b0, 0b11101, "facge">;
4531 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcage,
4532                                              FACGEsss, FACGEddd>;
4533
4534 // Scalar Floating-point Absolute Compare Mask Greater Than
4535 defm FACGT: NeonI_Scalar3Same_SD_sizes<0b1, 0b1, 0b11101, "facgt">;
4536 defm : Neon_Scalar3Same_cmp_SD_size_patterns<int_aarch64_neon_vcagt,
4537                                              FACGTsss, FACGTddd>;
4538
4539 // Scalar Absolute Value
4540 defm ABS : NeonI_Scalar2SameMisc_D_size<0b0, 0b01011, "abs">;
4541 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vabs, ABSdd>;
4542
4543 // Scalar Signed Saturating Absolute Value
4544 defm SQABS : NeonI_Scalar2SameMisc_BHSD_size<0b0, 0b00111, "sqabs">;
4545 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqabs,
4546                                                SQABSbb, SQABShh, SQABSss, SQABSdd>;
4547
4548 // Scalar Negate
4549 defm NEG : NeonI_Scalar2SameMisc_D_size<0b1, 0b01011, "neg">;
4550 defm : Neon_Scalar2SameMisc_D_size_patterns<int_aarch64_neon_vneg, NEGdd>;
4551
4552 // Scalar Signed Saturating Negate
4553 defm SQNEG : NeonI_Scalar2SameMisc_BHSD_size<0b1, 0b00111, "sqneg">;
4554 defm : Neon_Scalar2SameMisc_BHSD_size_patterns<int_arm_neon_vqneg,
4555                                                SQNEGbb, SQNEGhh, SQNEGss, SQNEGdd>;
4556
4557 // Scalar Signed Saturating Accumulated of Unsigned Value
4558 defm SUQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b0, 0b00011, "suqadd">;
4559 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vuqadd,
4560                                                      SUQADDbb, SUQADDhh,
4561                                                      SUQADDss, SUQADDdd>;
4562
4563 // Scalar Unsigned Saturating Accumulated of Signed Value
4564 defm USQADD : NeonI_Scalar2SameMisc_accum_BHSD_size<0b1, 0b00011, "usqadd">;
4565 defm : Neon_Scalar2SameMisc_accum_BHSD_size_patterns<int_aarch64_neon_vsqadd,
4566                                                      USQADDbb, USQADDhh,
4567                                                      USQADDss, USQADDdd>;
4568
4569 // Scalar Signed Saturating Extract Unsigned Narrow
4570 defm SQXTUN : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10010, "sqxtun">;
4571 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnsu,
4572                                                      SQXTUNbh, SQXTUNhs,
4573                                                      SQXTUNsd>;
4574
4575 // Scalar Signed Saturating Extract Narrow
4576 defm SQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b0, 0b10100, "sqxtn">;
4577 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovns,
4578                                                      SQXTNbh, SQXTNhs,
4579                                                      SQXTNsd>;
4580
4581 // Scalar Unsigned Saturating Extract Narrow
4582 defm UQXTN  : NeonI_Scalar2SameMisc_narrow_HSD_size<0b1, 0b10100, "uqxtn">;
4583 defm : Neon_Scalar2SameMisc_narrow_HSD_size_patterns<int_arm_neon_vqmovnu,
4584                                                      UQXTNbh, UQXTNhs,
4585                                                      UQXTNsd>;
4586
4587 // Scalar Reduce Pairwise
4588
4589 multiclass NeonI_ScalarPair_D_sizes<bit u, bit size, bits<5> opcode,
4590                                      string asmop, bit Commutable = 0> {
4591   let isCommutable = Commutable in {
4592     def _D_2D : NeonI_ScalarPair<u, {size, 0b1}, opcode,
4593                                 (outs FPR64:$Rd), (ins VPR128:$Rn),
4594                                 !strconcat(asmop, "\t$Rd, $Rn.2d"),
4595                                 [],
4596                                 NoItinerary>;
4597   }
4598 }
4599
4600 multiclass NeonI_ScalarPair_SD_sizes<bit u, bit size, bits<5> opcode,
4601                                      string asmop, bit Commutable = 0>
4602   : NeonI_ScalarPair_D_sizes<u, size, opcode, asmop, Commutable> {
4603   let isCommutable = Commutable in {
4604     def _S_2S : NeonI_ScalarPair<u, {size, 0b0}, opcode,
4605                                 (outs FPR32:$Rd), (ins VPR64:$Rn),
4606                                 !strconcat(asmop, "\t$Rd, $Rn.2s"),
4607                                 [],
4608                                 NoItinerary>;
4609   }
4610 }
4611
4612 // Scalar Reduce Addition Pairwise (Integer) with
4613 // Pattern to match llvm.arm.* intrinsic
4614 defm ADDPvv : NeonI_ScalarPair_D_sizes<0b0, 0b1, 0b11011, "addp", 0>;
4615
4616 // Pattern to match llvm.aarch64.* intrinsic for
4617 // Scalar Reduce Addition Pairwise (Integer)
4618 def : Pat<(v1i64 (int_aarch64_neon_vpadd (v2i64 VPR128:$Rn))),
4619           (ADDPvv_D_2D VPR128:$Rn)>;
4620
4621 // Scalar Reduce Addition Pairwise (Floating Point)
4622 defm FADDPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01101, "faddp", 0>;
4623
4624 // Scalar Reduce Maximum Pairwise (Floating Point)
4625 defm FMAXPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01111, "fmaxp", 0>;
4626
4627 // Scalar Reduce Minimum Pairwise (Floating Point)
4628 defm FMINPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01111, "fminp", 0>;
4629
4630 // Scalar Reduce maxNum Pairwise (Floating Point)
4631 defm FMAXNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b0, 0b01100, "fmaxnmp", 0>;
4632
4633 // Scalar Reduce minNum Pairwise (Floating Point)
4634 defm FMINNMPvv : NeonI_ScalarPair_SD_sizes<0b1, 0b1, 0b01100, "fminnmp", 0>;
4635
4636 multiclass Neon_ScalarPair_SD_size_patterns<SDPatternOperator opnodeS,
4637                                             SDPatternOperator opnodeD,
4638                                             Instruction INSTS,
4639                                             Instruction INSTD> {
4640   def : Pat<(v1f32 (opnodeS (v2f32 VPR64:$Rn))),
4641             (INSTS VPR64:$Rn)>;
4642   def : Pat<(v1f64 (opnodeD (v2f64 VPR128:$Rn))),
4643             (INSTD VPR128:$Rn)>;
4644 }
4645
4646 // Patterns to match llvm.aarch64.* intrinsic for
4647 // Scalar Reduce Add, Max, Min, MaxiNum, MinNum Pairwise (Floating Point)
4648 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfadd,
4649   int_aarch64_neon_vpfaddq, FADDPvv_S_2S, FADDPvv_D_2D>;
4650
4651 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmax,
4652   int_aarch64_neon_vpmaxq, FMAXPvv_S_2S, FMAXPvv_D_2D>;
4653
4654 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpmin,
4655   int_aarch64_neon_vpminq, FMINPvv_S_2S, FMINPvv_D_2D>;
4656
4657 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfmaxnm,
4658   int_aarch64_neon_vpfmaxnmq, FMAXNMPvv_S_2S, FMAXNMPvv_D_2D>;
4659
4660 defm : Neon_ScalarPair_SD_size_patterns<int_aarch64_neon_vpfminnm,
4661   int_aarch64_neon_vpfminnmq, FMINNMPvv_S_2S, FMINNMPvv_D_2D>;
4662
4663
4664
4665 //===----------------------------------------------------------------------===//
4666 // Non-Instruction Patterns
4667 //===----------------------------------------------------------------------===//
4668
4669 // 64-bit vector bitcasts...
4670
4671 def : Pat<(v1i64 (bitconvert (v8i8  VPR64:$src))), (v1i64 VPR64:$src)>;
4672 def : Pat<(v2f32 (bitconvert (v8i8  VPR64:$src))), (v2f32 VPR64:$src)>;
4673 def : Pat<(v2i32 (bitconvert (v8i8  VPR64:$src))), (v2i32 VPR64:$src)>;
4674 def : Pat<(v4i16 (bitconvert (v8i8  VPR64:$src))), (v4i16 VPR64:$src)>;
4675
4676 def : Pat<(v1i64 (bitconvert (v4i16  VPR64:$src))), (v1i64 VPR64:$src)>;
4677 def : Pat<(v2i32 (bitconvert (v4i16  VPR64:$src))), (v2i32 VPR64:$src)>;
4678 def : Pat<(v2f32 (bitconvert (v4i16  VPR64:$src))), (v2f32 VPR64:$src)>;
4679 def : Pat<(v8i8  (bitconvert (v4i16  VPR64:$src))), (v8i8 VPR64:$src)>;
4680
4681 def : Pat<(v1i64 (bitconvert (v2i32  VPR64:$src))), (v1i64 VPR64:$src)>;
4682 def : Pat<(v2f32 (bitconvert (v2i32  VPR64:$src))), (v2f32 VPR64:$src)>;
4683 def : Pat<(v4i16 (bitconvert (v2i32  VPR64:$src))), (v4i16 VPR64:$src)>;
4684 def : Pat<(v8i8  (bitconvert (v2i32  VPR64:$src))), (v8i8 VPR64:$src)>;
4685
4686 def : Pat<(v1i64 (bitconvert (v2f32  VPR64:$src))), (v1i64 VPR64:$src)>;
4687 def : Pat<(v2i32 (bitconvert (v2f32  VPR64:$src))), (v2i32 VPR64:$src)>;
4688 def : Pat<(v4i16 (bitconvert (v2f32  VPR64:$src))), (v4i16 VPR64:$src)>;
4689 def : Pat<(v8i8  (bitconvert (v2f32  VPR64:$src))), (v8i8 VPR64:$src)>;
4690
4691 def : Pat<(v2f32 (bitconvert (v1i64  VPR64:$src))), (v2f32 VPR64:$src)>;
4692 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
4693 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
4694 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
4695
4696 // ..and 128-bit vector bitcasts...
4697
4698 def : Pat<(v2f64 (bitconvert (v16i8  VPR128:$src))), (v2f64 VPR128:$src)>;
4699 def : Pat<(v2i64 (bitconvert (v16i8  VPR128:$src))), (v2i64 VPR128:$src)>;
4700 def : Pat<(v4f32 (bitconvert (v16i8  VPR128:$src))), (v4f32 VPR128:$src)>;
4701 def : Pat<(v4i32 (bitconvert (v16i8  VPR128:$src))), (v4i32 VPR128:$src)>;
4702 def : Pat<(v8i16 (bitconvert (v16i8  VPR128:$src))), (v8i16 VPR128:$src)>;
4703
4704 def : Pat<(v2f64 (bitconvert (v8i16  VPR128:$src))), (v2f64 VPR128:$src)>;
4705 def : Pat<(v2i64 (bitconvert (v8i16  VPR128:$src))), (v2i64 VPR128:$src)>;
4706 def : Pat<(v4i32 (bitconvert (v8i16  VPR128:$src))), (v4i32 VPR128:$src)>;
4707 def : Pat<(v4f32 (bitconvert (v8i16  VPR128:$src))), (v4f32 VPR128:$src)>;
4708 def : Pat<(v16i8 (bitconvert (v8i16  VPR128:$src))), (v16i8 VPR128:$src)>;
4709
4710 def : Pat<(v2f64 (bitconvert (v4i32  VPR128:$src))), (v2f64 VPR128:$src)>;
4711 def : Pat<(v2i64 (bitconvert (v4i32  VPR128:$src))), (v2i64 VPR128:$src)>;
4712 def : Pat<(v4f32 (bitconvert (v4i32  VPR128:$src))), (v4f32 VPR128:$src)>;
4713 def : Pat<(v8i16 (bitconvert (v4i32  VPR128:$src))), (v8i16 VPR128:$src)>;
4714 def : Pat<(v16i8 (bitconvert (v4i32  VPR128:$src))), (v16i8 VPR128:$src)>;
4715
4716 def : Pat<(v2f64 (bitconvert (v4f32  VPR128:$src))), (v2f64 VPR128:$src)>;
4717 def : Pat<(v2i64 (bitconvert (v4f32  VPR128:$src))), (v2i64 VPR128:$src)>;
4718 def : Pat<(v4i32 (bitconvert (v4f32  VPR128:$src))), (v4i32 VPR128:$src)>;
4719 def : Pat<(v8i16 (bitconvert (v4f32  VPR128:$src))), (v8i16 VPR128:$src)>;
4720 def : Pat<(v16i8 (bitconvert (v4f32  VPR128:$src))), (v16i8 VPR128:$src)>;
4721
4722 def : Pat<(v2f64 (bitconvert (v2i64  VPR128:$src))), (v2f64 VPR128:$src)>;
4723 def : Pat<(v4f32 (bitconvert (v2i64  VPR128:$src))), (v4f32 VPR128:$src)>;
4724 def : Pat<(v4i32 (bitconvert (v2i64  VPR128:$src))), (v4i32 VPR128:$src)>;
4725 def : Pat<(v8i16 (bitconvert (v2i64  VPR128:$src))), (v8i16 VPR128:$src)>;
4726 def : Pat<(v16i8 (bitconvert (v2i64  VPR128:$src))), (v16i8 VPR128:$src)>;
4727
4728 def : Pat<(v2i64 (bitconvert (v2f64  VPR128:$src))), (v2i64 VPR128:$src)>;
4729 def : Pat<(v4f32 (bitconvert (v2f64  VPR128:$src))), (v4f32 VPR128:$src)>;
4730 def : Pat<(v4i32 (bitconvert (v2f64  VPR128:$src))), (v4i32 VPR128:$src)>;
4731 def : Pat<(v8i16 (bitconvert (v2f64  VPR128:$src))), (v8i16 VPR128:$src)>;
4732 def : Pat<(v16i8 (bitconvert (v2f64  VPR128:$src))), (v16i8 VPR128:$src)>;
4733
4734
4735 // ...and scalar bitcasts...
4736 def : Pat<(f16 (bitconvert (v1i16  FPR16:$src))), (f16 FPR16:$src)>;
4737 def : Pat<(f32 (bitconvert (v1i32  FPR32:$src))), (f32 FPR32:$src)>;
4738 def : Pat<(f64 (bitconvert (v1i64  FPR64:$src))), (f64 FPR64:$src)>;
4739 def : Pat<(f32 (bitconvert (v1f32  FPR32:$src))), (f32 FPR32:$src)>;
4740 def : Pat<(f64 (bitconvert (v1f64  FPR64:$src))), (f64 FPR64:$src)>;
4741
4742 def : Pat<(i64 (bitconvert (v1i64  FPR64:$src))), (FMOVxd $src)>;
4743 def : Pat<(i32 (bitconvert (v1i32  FPR32:$src))), (FMOVws $src)>;
4744
4745 def : Pat<(v8i8  (bitconvert (v1i64  VPR64:$src))), (v8i8 VPR64:$src)>;
4746 def : Pat<(v4i16 (bitconvert (v1i64  VPR64:$src))), (v4i16 VPR64:$src)>;
4747 def : Pat<(v2i32 (bitconvert (v1i64  VPR64:$src))), (v2i32 VPR64:$src)>;
4748
4749 def : Pat<(f64   (bitconvert (v8i8  VPR64:$src))), (f64 VPR64:$src)>;
4750 def : Pat<(f64   (bitconvert (v4i16  VPR64:$src))), (f64 VPR64:$src)>;
4751 def : Pat<(f64   (bitconvert (v2i32  VPR64:$src))), (f64 VPR64:$src)>;
4752 def : Pat<(f64   (bitconvert (v2f32  VPR64:$src))), (f64 VPR64:$src)>;
4753 def : Pat<(f64   (bitconvert (v1i64  VPR64:$src))), (f64 VPR64:$src)>;
4754
4755 def : Pat<(f128  (bitconvert (v16i8  VPR128:$src))), (f128 VPR128:$src)>;
4756 def : Pat<(f128  (bitconvert (v8i16  VPR128:$src))), (f128 VPR128:$src)>;
4757 def : Pat<(f128  (bitconvert (v4i32  VPR128:$src))), (f128 VPR128:$src)>;
4758 def : Pat<(f128  (bitconvert (v2i64  VPR128:$src))), (f128 VPR128:$src)>;
4759 def : Pat<(f128  (bitconvert (v4f32  VPR128:$src))), (f128 VPR128:$src)>;
4760 def : Pat<(f128  (bitconvert (v2f64  VPR128:$src))), (f128 VPR128:$src)>;
4761
4762 def : Pat<(v1i16 (bitconvert (f16  FPR16:$src))), (v1i16 FPR16:$src)>;
4763 def : Pat<(v1i32 (bitconvert (f32  FPR32:$src))), (v1i32 FPR32:$src)>;
4764 def : Pat<(v1i64 (bitconvert (f64  FPR64:$src))), (v1i64 FPR64:$src)>;
4765 def : Pat<(v1f32 (bitconvert (f32  FPR32:$src))), (v1f32 FPR32:$src)>;
4766 def : Pat<(v1f64 (bitconvert (f64  FPR64:$src))), (v1f64 FPR64:$src)>;
4767
4768 def : Pat<(v1i64 (bitconvert (i64  GPR64:$src))), (FMOVdx $src)>;
4769 def : Pat<(v1i32 (bitconvert (i32  GPR32:$src))), (FMOVsw $src)>;
4770
4771 def : Pat<(v8i8   (bitconvert (f64   FPR64:$src))), (v8i8 FPR64:$src)>;
4772 def : Pat<(v4i16  (bitconvert (f64   FPR64:$src))), (v4i16 FPR64:$src)>;
4773 def : Pat<(v2i32  (bitconvert (f64   FPR64:$src))), (v2i32 FPR64:$src)>;
4774 def : Pat<(v2f32  (bitconvert (f64   FPR64:$src))), (v2f32 FPR64:$src)>;
4775 def : Pat<(v1i64  (bitconvert (f64   FPR64:$src))), (v1i64 FPR64:$src)>;
4776
4777 def : Pat<(v16i8  (bitconvert (f128   FPR128:$src))), (v16i8 FPR128:$src)>;
4778 def : Pat<(v8i16  (bitconvert (f128   FPR128:$src))), (v8i16 FPR128:$src)>;
4779 def : Pat<(v4i32  (bitconvert (f128   FPR128:$src))), (v4i32 FPR128:$src)>;
4780 def : Pat<(v2i64  (bitconvert (f128   FPR128:$src))), (v2i64 FPR128:$src)>;
4781 def : Pat<(v4f32  (bitconvert (f128   FPR128:$src))), (v4f32 FPR128:$src)>;
4782 def : Pat<(v2f64  (bitconvert (f128   FPR128:$src))), (v2f64 FPR128:$src)>;
4783
4784 def neon_uimm0_bare : Operand<i64>,
4785                         ImmLeaf<i64, [{return Imm == 0;}]> {
4786   let ParserMatchClass = neon_uimm0_asmoperand;
4787   let PrintMethod = "printUImmBareOperand";
4788 }
4789
4790 def neon_uimm1_bare : Operand<i64>,
4791                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4792   let ParserMatchClass = neon_uimm1_asmoperand;
4793   let PrintMethod = "printUImmBareOperand";
4794 }
4795
4796 def neon_uimm2_bare : Operand<i64>,
4797                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4798   let ParserMatchClass = neon_uimm2_asmoperand;
4799   let PrintMethod = "printUImmBareOperand";
4800 }
4801
4802 def neon_uimm3_bare : Operand<i64>,
4803                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4804   let ParserMatchClass = uimm3_asmoperand;
4805   let PrintMethod = "printUImmBareOperand";
4806 }
4807
4808 def neon_uimm4_bare : Operand<i64>,
4809                         ImmLeaf<i64, [{(void)Imm; return true;}]> {
4810   let ParserMatchClass = uimm4_asmoperand;
4811   let PrintMethod = "printUImmBareOperand";
4812 }
4813
4814 def neon_uimm3 : Operand<i64>,
4815                    ImmLeaf<i64, [{(void)Imm; return true;}]> {
4816   let ParserMatchClass = uimm3_asmoperand;
4817   let PrintMethod = "printUImmHexOperand";
4818 }
4819
4820 def neon_uimm4 : Operand<i64>,
4821                    ImmLeaf<i64, [{(void)Imm; return true;}]> {
4822   let ParserMatchClass = uimm4_asmoperand;
4823   let PrintMethod = "printUImmHexOperand";
4824 }
4825
4826 class NeonI_INS_main<string asmop, string Res, ValueType ResTy,
4827                      RegisterClass OpGPR, ValueType OpTy, Operand OpImm>
4828   : NeonI_copy<0b1, 0b0, 0b0011,
4829                (outs VPR128:$Rd), (ins VPR128:$src, OpGPR:$Rn, OpImm:$Imm),
4830                asmop # "\t$Rd." # Res # "[$Imm], $Rn",
4831                [(set (ResTy VPR128:$Rd),
4832                  (ResTy (vector_insert
4833                    (ResTy VPR128:$src),
4834                    (OpTy OpGPR:$Rn),
4835                    (OpImm:$Imm))))],
4836                NoItinerary> {
4837   bits<4> Imm;
4838   let Constraints = "$src = $Rd";
4839 }
4840
4841 // Bitwise Extract
4842 class NeonI_Extract<bit q, bits<2> op2, string asmop,
4843                     string OpS, RegisterOperand OpVPR, Operand OpImm>
4844   : NeonI_BitExtract<q, op2, (outs OpVPR:$Rd),
4845                      (ins OpVPR:$Rn, OpVPR:$Rm, OpImm:$Index),
4846                      asmop # "\t$Rd." # OpS # ", $Rn." # OpS #
4847                      ", $Rm." # OpS # ", $Index",
4848                      [],
4849                      NoItinerary>{
4850   bits<4> Index;
4851 }
4852
4853 def EXTvvvi_8b : NeonI_Extract<0b0, 0b00, "ext", "8b",
4854                                VPR64, neon_uimm3> {
4855   let Inst{14-11} = {0b0, Index{2}, Index{1}, Index{0}};
4856 }
4857
4858 def EXTvvvi_16b: NeonI_Extract<0b1, 0b00, "ext", "16b",
4859                                VPR128, neon_uimm4> {
4860   let Inst{14-11} = Index;
4861 }
4862
4863 class NI_Extract<ValueType OpTy, RegisterOperand OpVPR, Instruction INST,
4864                  Operand OpImm>
4865   : Pat<(OpTy (Neon_vextract (OpTy OpVPR:$Rn), (OpTy OpVPR:$Rm),
4866                                  (i64 OpImm:$Imm))),
4867               (INST OpVPR:$Rn, OpVPR:$Rm, OpImm:$Imm)>;
4868
4869 def : NI_Extract<v8i8,  VPR64,  EXTvvvi_8b,  neon_uimm3>;
4870 def : NI_Extract<v4i16, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4871 def : NI_Extract<v2i32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4872 def : NI_Extract<v1i64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4873 def : NI_Extract<v2f32, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4874 def : NI_Extract<v1f64, VPR64,  EXTvvvi_8b,  neon_uimm3>;
4875 def : NI_Extract<v16i8, VPR128, EXTvvvi_16b, neon_uimm4>;
4876 def : NI_Extract<v8i16, VPR128, EXTvvvi_16b, neon_uimm4>;
4877 def : NI_Extract<v4i32, VPR128, EXTvvvi_16b, neon_uimm4>;
4878 def : NI_Extract<v2i64, VPR128, EXTvvvi_16b, neon_uimm4>;
4879 def : NI_Extract<v4f32, VPR128, EXTvvvi_16b, neon_uimm4>;
4880 def : NI_Extract<v2f64, VPR128, EXTvvvi_16b, neon_uimm4>;
4881
4882 // The followings are for instruction class (3V Elem)
4883
4884 // Variant 1
4885
4886 class NI_2VE<bit q, bit u, bits<2> size, bits<4> opcode,
4887              string asmop, string ResS, string OpS, string EleOpS,
4888              Operand OpImm, RegisterOperand ResVPR,
4889              RegisterOperand OpVPR, RegisterOperand EleOpVPR>
4890   : NeonI_2VElem<q, u, size, opcode,
4891                  (outs ResVPR:$Rd), (ins ResVPR:$src, OpVPR:$Rn,
4892                                          EleOpVPR:$Re, OpImm:$Index),
4893                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
4894                  ", $Re." # EleOpS # "[$Index]",
4895                  [],
4896                  NoItinerary> {
4897   bits<3> Index;
4898   bits<5> Re;
4899
4900   let Constraints = "$src = $Rd";
4901 }
4902
4903 multiclass NI_2VE_v1<bit u, bits<4> opcode, string asmop> {
4904   // vector register class for element is always 128-bit to cover the max index
4905   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
4906                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
4907     let Inst{11} = {Index{1}};
4908     let Inst{21} = {Index{0}};
4909     let Inst{20-16} = Re;
4910   }
4911
4912   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
4913                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
4914     let Inst{11} = {Index{1}};
4915     let Inst{21} = {Index{0}};
4916     let Inst{20-16} = Re;
4917   }
4918
4919   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
4920   def _4h8h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
4921                      neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
4922     let Inst{11} = {Index{2}};
4923     let Inst{21} = {Index{1}};
4924     let Inst{20} = {Index{0}};
4925     let Inst{19-16} = Re{3-0};
4926   }
4927
4928   def _8h8h : NI_2VE<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
4929                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
4930     let Inst{11} = {Index{2}};
4931     let Inst{21} = {Index{1}};
4932     let Inst{20} = {Index{0}};
4933     let Inst{19-16} = Re{3-0};
4934   }
4935 }
4936
4937 defm MLAvve : NI_2VE_v1<0b1, 0b0000, "mla">;
4938 defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">;
4939
4940 // Pattern for lane in 128-bit vector
4941 class NI_2VE_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
4942                    RegisterOperand ResVPR, RegisterOperand OpVPR,
4943                    RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
4944                    ValueType EleOpTy, SDPatternOperator coreop>
4945   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
4946           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4947         (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
4948
4949 // Pattern for lane in 64-bit vector
4950 class NI_2VE_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
4951                   RegisterOperand ResVPR, RegisterOperand OpVPR,
4952                   RegisterOperand EleOpVPR, ValueType ResTy, ValueType OpTy,
4953                   ValueType EleOpTy, SDPatternOperator coreop>
4954   : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn),
4955           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
4956         (INST ResVPR:$src, OpVPR:$Rn,
4957           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
4958
4959 multiclass NI_2VE_v1_pat<string subop, SDPatternOperator op>
4960 {
4961   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
4962                      op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32,
4963                      BinOpFrag<(Neon_vduplane
4964                                  (Neon_low4S node:$LHS), node:$RHS)>>;
4965
4966   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
4967                      op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32,
4968                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4969
4970   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
4971                      op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
4972                      BinOpFrag<(Neon_vduplane
4973                                  (Neon_low8H node:$LHS), node:$RHS)>>;
4974
4975   def : NI_2VE_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
4976                      op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
4977                      BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4978
4979   // Index can only be half of the max value for lane in 64-bit vector
4980
4981   def : NI_2VE_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
4982                     op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32,
4983                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4984
4985   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
4986                     op, VPR128, VPR128, VPR64, v4i32, v4i32, v2i32,
4987                     BinOpFrag<(Neon_vduplane
4988                                 (Neon_combine_4S node:$LHS, undef),
4989                                  node:$RHS)>>;
4990
4991   def : NI_2VE_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
4992                     op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
4993                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
4994
4995   def : NI_2VE_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
4996                     op, VPR128, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
4997                     BinOpFrag<(Neon_vduplane
4998                                 (Neon_combine_8H node:$LHS, undef),
4999                                 node:$RHS)>>;
5000 }
5001
5002 defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>;
5003 defm MLS_lane_v1 : NI_2VE_v1_pat<"MLSvve", Neon_mls>;
5004
5005 class NI_2VE_2op<bit q, bit u, bits<2> size, bits<4> opcode,
5006                  string asmop, string ResS, string OpS, string EleOpS,
5007                  Operand OpImm, RegisterOperand ResVPR,
5008                  RegisterOperand OpVPR, RegisterOperand EleOpVPR>
5009   : NeonI_2VElem<q, u, size, opcode,
5010                  (outs ResVPR:$Rd), (ins OpVPR:$Rn,
5011                                          EleOpVPR:$Re, OpImm:$Index),
5012                  asmop # "\t$Rd." # ResS # ", $Rn." # OpS #
5013                  ", $Re." # EleOpS # "[$Index]",
5014                  [],
5015                  NoItinerary> {
5016   bits<3> Index;
5017   bits<5> Re;
5018 }
5019
5020 multiclass NI_2VE_v1_2op<bit u, bits<4> opcode, string asmop> {
5021   // vector register class for element is always 128-bit to cover the max index
5022   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
5023                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
5024     let Inst{11} = {Index{1}};
5025     let Inst{21} = {Index{0}};
5026     let Inst{20-16} = Re;
5027   }
5028
5029   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
5030                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
5031     let Inst{11} = {Index{1}};
5032     let Inst{21} = {Index{0}};
5033     let Inst{20-16} = Re;
5034   }
5035
5036   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
5037   def _4h8h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4h", "4h", "h",
5038                          neon_uimm3_bare, VPR64, VPR64, VPR128Lo> {
5039     let Inst{11} = {Index{2}};
5040     let Inst{21} = {Index{1}};
5041     let Inst{20} = {Index{0}};
5042     let Inst{19-16} = Re{3-0};
5043   }
5044
5045   def _8h8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop, "8h", "8h", "h",
5046                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
5047     let Inst{11} = {Index{2}};
5048     let Inst{21} = {Index{1}};
5049     let Inst{20} = {Index{0}};
5050     let Inst{19-16} = Re{3-0};
5051   }
5052 }
5053
5054 defm MULve : NI_2VE_v1_2op<0b0, 0b1000, "mul">;
5055 defm SQDMULHve : NI_2VE_v1_2op<0b0, 0b1100, "sqdmulh">;
5056 defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">;
5057
5058 // Pattern for lane in 128-bit vector
5059 class NI_2VE_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
5060                        RegisterOperand OpVPR, RegisterOperand EleOpVPR,
5061                        ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
5062                        SDPatternOperator coreop>
5063   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
5064           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5065         (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
5066
5067 // Pattern for lane in 64-bit vector
5068 class NI_2VE_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
5069                       RegisterOperand OpVPR, RegisterOperand EleOpVPR,
5070                       ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
5071                       SDPatternOperator coreop>
5072   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
5073           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5074         (INST OpVPR:$Rn,
5075           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
5076
5077 multiclass NI_2VE_mul_v1_pat<string subop, SDPatternOperator op> {
5078   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
5079                          op, VPR64, VPR128, v2i32, v2i32, v4i32,
5080                          BinOpFrag<(Neon_vduplane
5081                                      (Neon_low4S node:$LHS), node:$RHS)>>;
5082
5083   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
5084                          op, VPR128, VPR128, v4i32, v4i32, v4i32,
5085                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5086
5087   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4h8h"), neon_uimm3_bare,
5088                          op, VPR64, VPR128Lo, v4i16, v4i16, v8i16,
5089                          BinOpFrag<(Neon_vduplane
5090                                     (Neon_low8H node:$LHS), node:$RHS)>>;
5091
5092   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_8h8h"), neon_uimm3_bare,
5093                          op, VPR128, VPR128Lo, v8i16, v8i16, v8i16,
5094                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5095
5096   // Index can only be half of the max value for lane in 64-bit vector
5097
5098   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
5099                         op, VPR64, VPR64, v2i32, v2i32, v2i32,
5100                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5101
5102   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
5103                         op, VPR128, VPR64, v4i32, v4i32, v2i32,
5104                         BinOpFrag<(Neon_vduplane
5105                                     (Neon_combine_4S node:$LHS, undef),
5106                                      node:$RHS)>>;
5107
5108   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4h8h"), neon_uimm2_bare,
5109                         op, VPR64, VPR64Lo, v4i16, v4i16, v4i16,
5110                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5111
5112   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_8h8h"), neon_uimm2_bare,
5113                         op, VPR128, VPR64Lo, v8i16, v8i16, v4i16,
5114                         BinOpFrag<(Neon_vduplane
5115                                     (Neon_combine_8H node:$LHS, undef),
5116                                     node:$RHS)>>;
5117 }
5118
5119 defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>;
5120 defm SQDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQDMULHve", int_arm_neon_vqdmulh>;
5121 defm SQRDMULH_lane_v1 : NI_2VE_mul_v1_pat<"SQRDMULHve", int_arm_neon_vqrdmulh>;
5122
5123 // Variant 2
5124
5125 multiclass NI_2VE_v2_2op<bit u, bits<4> opcode, string asmop> {
5126   // vector register class for element is always 128-bit to cover the max index
5127   def _2s4s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
5128                          neon_uimm2_bare, VPR64, VPR64, VPR128> {
5129     let Inst{11} = {Index{1}};
5130     let Inst{21} = {Index{0}};
5131     let Inst{20-16} = Re;
5132   }
5133
5134   def _4s4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
5135                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
5136     let Inst{11} = {Index{1}};
5137     let Inst{21} = {Index{0}};
5138     let Inst{20-16} = Re;
5139   }
5140
5141   // _1d2d doesn't exist!
5142
5143   def _2d2d : NI_2VE_2op<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
5144                          neon_uimm1_bare, VPR128, VPR128, VPR128> {
5145     let Inst{11} = {Index{0}};
5146     let Inst{21} = 0b0;
5147     let Inst{20-16} = Re;
5148   }
5149 }
5150
5151 defm FMULve : NI_2VE_v2_2op<0b0, 0b1001, "fmul">;
5152 defm FMULXve : NI_2VE_v2_2op<0b1, 0b1001, "fmulx">;
5153
5154 class NI_2VE_mul_lane_2d<Instruction INST, Operand OpImm, SDPatternOperator op,
5155                          RegisterOperand OpVPR, RegisterOperand EleOpVPR,
5156                          ValueType ResTy, ValueType OpTy, ValueType EleOpTy,
5157                          SDPatternOperator coreop>
5158   : Pat<(ResTy (op (OpTy OpVPR:$Rn),
5159           (OpTy (coreop (EleOpTy EleOpVPR:$Re), (EleOpTy EleOpVPR:$Re))))),
5160         (INST OpVPR:$Rn,
5161           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), 0)>;
5162
5163 multiclass NI_2VE_mul_v2_pat<string subop, SDPatternOperator op> {
5164   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2s4s"), neon_uimm2_bare,
5165                          op, VPR64, VPR128, v2f32, v2f32, v4f32,
5166                          BinOpFrag<(Neon_vduplane
5167                                      (Neon_low4f node:$LHS), node:$RHS)>>;
5168
5169   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4s"), neon_uimm2_bare,
5170                          op, VPR128, VPR128, v4f32, v4f32, v4f32,
5171                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5172
5173   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
5174                          op, VPR128, VPR128, v2f64, v2f64, v2f64,
5175                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5176
5177   // Index can only be half of the max value for lane in 64-bit vector
5178
5179   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2s4s"), neon_uimm1_bare,
5180                         op, VPR64, VPR64, v2f32, v2f32, v2f32,
5181                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5182
5183   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4s"), neon_uimm1_bare,
5184                         op, VPR128, VPR64, v4f32, v4f32, v2f32,
5185                         BinOpFrag<(Neon_vduplane
5186                                     (Neon_combine_4f node:$LHS, undef),
5187                                     node:$RHS)>>;
5188
5189   def : NI_2VE_mul_lane_2d<!cast<Instruction>(subop # "_2d2d"), neon_uimm1_bare,
5190                            op, VPR128, VPR64, v2f64, v2f64, v1f64,
5191                            BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
5192 }
5193
5194 defm FMUL_lane_v2 : NI_2VE_mul_v2_pat<"FMULve", fmul>;
5195 defm FMULX_lane_v2 : NI_2VE_mul_v2_pat<"FMULXve", int_aarch64_neon_vmulx>;
5196
5197 // The followings are patterns using fma
5198 // -ffp-contract=fast generates fma
5199
5200 multiclass NI_2VE_v2<bit u, bits<4> opcode, string asmop> {
5201   // vector register class for element is always 128-bit to cover the max index
5202   def _2s4s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2s", "2s", "s",
5203                      neon_uimm2_bare, VPR64, VPR64, VPR128> {
5204     let Inst{11} = {Index{1}};
5205     let Inst{21} = {Index{0}};
5206     let Inst{20-16} = Re;
5207   }
5208
5209   def _4s4s : NI_2VE<0b1, u, 0b10, opcode, asmop, "4s", "4s", "s",
5210                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
5211     let Inst{11} = {Index{1}};
5212     let Inst{21} = {Index{0}};
5213     let Inst{20-16} = Re;
5214   }
5215
5216   // _1d2d doesn't exist!
5217
5218   def _2d2d : NI_2VE<0b1, u, 0b11, opcode, asmop, "2d", "2d", "d",
5219                      neon_uimm1_bare, VPR128, VPR128, VPR128> {
5220     let Inst{11} = {Index{0}};
5221     let Inst{21} = 0b0;
5222     let Inst{20-16} = Re;
5223   }
5224 }
5225
5226 defm FMLAvve : NI_2VE_v2<0b0, 0b0001, "fmla">;
5227 defm FMLSvve : NI_2VE_v2<0b0, 0b0101, "fmls">;
5228
5229 // Pattern for lane in 128-bit vector
5230 class NI_2VEswap_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
5231                        RegisterOperand ResVPR, RegisterOperand OpVPR,
5232                        ValueType ResTy, ValueType OpTy,
5233                        SDPatternOperator coreop>
5234   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
5235                    (ResTy ResVPR:$src), (ResTy ResVPR:$Rn))),
5236         (INST ResVPR:$src, ResVPR:$Rn, OpVPR:$Re, OpImm:$Index)>;
5237
5238 // Pattern for lane in 64-bit vector
5239 class NI_2VEswap_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
5240                       RegisterOperand ResVPR, RegisterOperand OpVPR,
5241                       ValueType ResTy, ValueType OpTy,
5242                       SDPatternOperator coreop>
5243   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (i64 OpImm:$Index))),
5244                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
5245         (INST ResVPR:$src, ResVPR:$Rn,
5246           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), OpImm:$Index)>;
5247
5248 // Pattern for lane in 64-bit vector
5249 class NI_2VEswap_lane_2d2d<Instruction INST, Operand OpImm,
5250                            SDPatternOperator op,
5251                            RegisterOperand ResVPR, RegisterOperand OpVPR,
5252                            ValueType ResTy, ValueType OpTy,
5253                            SDPatternOperator coreop>
5254   : Pat<(ResTy (op (ResTy (coreop (OpTy OpVPR:$Re), (OpTy OpVPR:$Re))),
5255                    (ResTy ResVPR:$Rn), (ResTy ResVPR:$src))),
5256         (INST ResVPR:$src, ResVPR:$Rn,
5257           (SUBREG_TO_REG (i64 0), OpVPR:$Re, sub_64), 0)>;
5258
5259
5260 multiclass NI_2VE_fma_v2_pat<string subop, SDPatternOperator op> {
5261   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
5262                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
5263                          BinOpFrag<(Neon_vduplane
5264                                      (Neon_low4f node:$LHS), node:$RHS)>>;
5265
5266   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
5267                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
5268                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5269
5270   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
5271                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
5272                          BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5273
5274   // Index can only be half of the max value for lane in 64-bit vector
5275
5276   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
5277                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
5278                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5279
5280   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
5281                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
5282                         BinOpFrag<(Neon_vduplane
5283                                     (Neon_combine_4f node:$LHS, undef),
5284                                     node:$RHS)>>;
5285
5286   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
5287                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
5288                              BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>;
5289 }
5290
5291 defm FMLA_lane_v2_s : NI_2VE_fma_v2_pat<"FMLAvve", fma>;
5292
5293 multiclass NI_2VE_fms_v2_pat<string subop, SDPatternOperator op>
5294 {
5295   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
5296                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
5297                          BinOpFrag<(fneg (Neon_vduplane
5298                                      (Neon_low4f node:$LHS), node:$RHS))>>;
5299
5300   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2s4s"),
5301                          neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32,
5302                          BinOpFrag<(Neon_vduplane
5303                                      (Neon_low4f (fneg node:$LHS)),
5304                                      node:$RHS)>>;
5305
5306   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
5307                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
5308                          BinOpFrag<(fneg (Neon_vduplane
5309                                      node:$LHS, node:$RHS))>>;
5310
5311   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_4s4s"),
5312                          neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32,
5313                          BinOpFrag<(Neon_vduplane
5314                                      (fneg node:$LHS), node:$RHS)>>;
5315
5316   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
5317                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
5318                          BinOpFrag<(fneg (Neon_vduplane
5319                                      node:$LHS, node:$RHS))>>;
5320
5321   def : NI_2VEswap_laneq<!cast<Instruction>(subop # "_2d2d"),
5322                          neon_uimm1_bare, op, VPR128, VPR128, v2f64, v2f64,
5323                          BinOpFrag<(Neon_vduplane
5324                                      (fneg node:$LHS), node:$RHS)>>;
5325
5326   // Index can only be half of the max value for lane in 64-bit vector
5327
5328   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
5329                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
5330                         BinOpFrag<(fneg (Neon_vduplane
5331                                     node:$LHS, node:$RHS))>>;
5332
5333   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_2s4s"),
5334                         neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32,
5335                         BinOpFrag<(Neon_vduplane
5336                                     (fneg node:$LHS), node:$RHS)>>;
5337
5338   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
5339                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
5340                         BinOpFrag<(fneg (Neon_vduplane
5341                                     (Neon_combine_4f node:$LHS, undef),
5342                                     node:$RHS))>>;
5343
5344   def : NI_2VEswap_lane<!cast<Instruction>(subop # "_4s4s"),
5345                         neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32,
5346                         BinOpFrag<(Neon_vduplane
5347                                     (Neon_combine_4f (fneg node:$LHS), undef),
5348                                     node:$RHS)>>;
5349
5350   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
5351                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
5352                              BinOpFrag<(fneg (Neon_combine_2d
5353                                          node:$LHS, node:$RHS))>>;
5354
5355   def : NI_2VEswap_lane_2d2d<!cast<Instruction>(subop # "_2d2d"),
5356                              neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64,
5357                              BinOpFrag<(Neon_combine_2d
5358                                          (fneg node:$LHS), (fneg node:$RHS))>>;
5359 }
5360
5361 defm FMLS_lane_v2_s : NI_2VE_fms_v2_pat<"FMLSvve", fma>;
5362
5363 // Variant 3: Long type
5364 // E.g. SMLAL : 4S/4H/H (v0-v15), 2D/2S/S
5365 //      SMLAL2: 4S/8H/H (v0-v15), 2D/4S/S
5366
5367 multiclass NI_2VE_v3<bit u, bits<4> opcode, string asmop> {
5368   // vector register class for element is always 128-bit to cover the max index
5369   def _2d2s : NI_2VE<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
5370                      neon_uimm2_bare, VPR128, VPR64, VPR128> {
5371     let Inst{11} = {Index{1}};
5372     let Inst{21} = {Index{0}};
5373     let Inst{20-16} = Re;
5374   }
5375
5376   def _2d4s : NI_2VE<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
5377                      neon_uimm2_bare, VPR128, VPR128, VPR128> {
5378     let Inst{11} = {Index{1}};
5379     let Inst{21} = {Index{0}};
5380     let Inst{20-16} = Re;
5381   }
5382
5383   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
5384   def _4s8h : NI_2VE<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
5385                      neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
5386     let Inst{11} = {Index{2}};
5387     let Inst{21} = {Index{1}};
5388     let Inst{20} = {Index{0}};
5389     let Inst{19-16} = Re{3-0};
5390   }
5391
5392   def _4s4h : NI_2VE<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
5393                      neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
5394     let Inst{11} = {Index{2}};
5395     let Inst{21} = {Index{1}};
5396     let Inst{20} = {Index{0}};
5397     let Inst{19-16} = Re{3-0};
5398   }
5399 }
5400
5401 defm SMLALvve : NI_2VE_v3<0b0, 0b0010, "smlal">;
5402 defm UMLALvve : NI_2VE_v3<0b1, 0b0010, "umlal">;
5403 defm SMLSLvve : NI_2VE_v3<0b0, 0b0110, "smlsl">;
5404 defm UMLSLvve : NI_2VE_v3<0b1, 0b0110, "umlsl">;
5405 defm SQDMLALvve : NI_2VE_v3<0b0, 0b0011, "sqdmlal">;
5406 defm SQDMLSLvve : NI_2VE_v3<0b0, 0b0111, "sqdmlsl">;
5407
5408 multiclass NI_2VE_v3_2op<bit u, bits<4> opcode, string asmop> {
5409   // vector register class for element is always 128-bit to cover the max index
5410   def _2d2s : NI_2VE_2op<0b0, u, 0b10, opcode, asmop, "2d", "2s", "s",
5411                          neon_uimm2_bare, VPR128, VPR64, VPR128> {
5412     let Inst{11} = {Index{1}};
5413     let Inst{21} = {Index{0}};
5414     let Inst{20-16} = Re;
5415   }
5416
5417   def _2d4s : NI_2VE_2op<0b1, u, 0b10, opcode, asmop # "2", "2d", "4s", "s",
5418                          neon_uimm2_bare, VPR128, VPR128, VPR128> {
5419     let Inst{11} = {Index{1}};
5420     let Inst{21} = {Index{0}};
5421     let Inst{20-16} = Re;
5422   }
5423
5424   // Index operations on 16-bit(H) elements are restricted to using v0-v15.
5425   def _4s8h : NI_2VE_2op<0b1, u, 0b01, opcode, asmop # "2", "4s", "8h", "h",
5426                          neon_uimm3_bare, VPR128, VPR128, VPR128Lo> {
5427     let Inst{11} = {Index{2}};
5428     let Inst{21} = {Index{1}};
5429     let Inst{20} = {Index{0}};
5430     let Inst{19-16} = Re{3-0};
5431   }
5432
5433   def _4s4h : NI_2VE_2op<0b0, u, 0b01, opcode, asmop, "4s", "4h", "h",
5434                          neon_uimm3_bare, VPR128, VPR64, VPR128Lo> {
5435     let Inst{11} = {Index{2}};
5436     let Inst{21} = {Index{1}};
5437     let Inst{20} = {Index{0}};
5438     let Inst{19-16} = Re{3-0};
5439   }
5440 }
5441
5442 defm SMULLve : NI_2VE_v3_2op<0b0, 0b1010, "smull">;
5443 defm UMULLve : NI_2VE_v3_2op<0b1, 0b1010, "umull">;
5444 defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">;
5445
5446 // Pattern for lane in 128-bit vector
5447 class NI_2VEL2_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
5448                      RegisterOperand EleOpVPR, ValueType ResTy,
5449                      ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5450                      SDPatternOperator hiop, SDPatternOperator coreop>
5451   : Pat<(ResTy (op (ResTy VPR128:$src),
5452           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5453           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5454         (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
5455
5456 // Pattern for lane in 64-bit vector
5457 class NI_2VEL2_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
5458                     RegisterOperand EleOpVPR, ValueType ResTy,
5459                     ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5460                     SDPatternOperator hiop, SDPatternOperator coreop>
5461   : Pat<(ResTy (op (ResTy VPR128:$src),
5462           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5463           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5464         (INST VPR128:$src, VPR128:$Rn,
5465           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
5466
5467 multiclass NI_2VEL_v3_pat<string subop, SDPatternOperator op> {
5468   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
5469                      op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
5470                      BinOpFrag<(Neon_vduplane
5471                                  (Neon_low8H node:$LHS), node:$RHS)>>;
5472
5473   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
5474                      op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32,
5475                      BinOpFrag<(Neon_vduplane
5476                                  (Neon_low4S node:$LHS), node:$RHS)>>;
5477
5478   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
5479                        op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H,
5480                        BinOpFrag<(Neon_vduplane
5481                                    (Neon_low8H node:$LHS), node:$RHS)>>;
5482
5483   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
5484                        op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
5485                        BinOpFrag<(Neon_vduplane
5486                                    (Neon_low4S node:$LHS), node:$RHS)>>;
5487
5488   // Index can only be half of the max value for lane in 64-bit vector
5489
5490   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
5491                     op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
5492                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5493
5494   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
5495                     op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32,
5496                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5497
5498   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
5499                       op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
5500                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5501
5502   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
5503                       op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
5504                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5505 }
5506
5507 defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>;
5508 defm UMLAL_lane_v3 : NI_2VEL_v3_pat<"UMLALvve", Neon_umlal>;
5509 defm SMLSL_lane_v3 : NI_2VEL_v3_pat<"SMLSLvve", Neon_smlsl>;
5510 defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>;
5511
5512 // Pattern for lane in 128-bit vector
5513 class NI_2VEL2_mul_laneq<Instruction INST, Operand OpImm, SDPatternOperator op,
5514                          RegisterOperand EleOpVPR, ValueType ResTy,
5515                          ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5516                          SDPatternOperator hiop, SDPatternOperator coreop>
5517   : Pat<(ResTy (op
5518           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5519           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5520         (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>;
5521
5522 // Pattern for lane in 64-bit vector
5523 class NI_2VEL2_mul_lane<Instruction INST, Operand OpImm, SDPatternOperator op,
5524                         RegisterOperand EleOpVPR, ValueType ResTy,
5525                         ValueType OpTy, ValueType EleOpTy, ValueType HalfOpTy,
5526                         SDPatternOperator hiop, SDPatternOperator coreop>
5527   : Pat<(ResTy (op
5528           (HalfOpTy (hiop (OpTy VPR128:$Rn))),
5529           (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))),
5530         (INST VPR128:$Rn,
5531           (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>;
5532
5533 multiclass NI_2VEL_mul_v3_pat<string subop, SDPatternOperator op> {
5534   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
5535                          op, VPR64, VPR128Lo, v4i32, v4i16, v8i16,
5536                          BinOpFrag<(Neon_vduplane
5537                                      (Neon_low8H node:$LHS), node:$RHS)>>;
5538
5539   def : NI_2VE_mul_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
5540                          op, VPR64, VPR128, v2i64, v2i32, v4i32,
5541                          BinOpFrag<(Neon_vduplane
5542                                      (Neon_low4S node:$LHS), node:$RHS)>>;
5543
5544   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
5545                            op, VPR128Lo, v4i32, v8i16, v8i16, v4i16,
5546                            Neon_High8H,
5547                            BinOpFrag<(Neon_vduplane
5548                                        (Neon_low8H node:$LHS), node:$RHS)>>;
5549
5550   def : NI_2VEL2_mul_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
5551                            op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S,
5552                            BinOpFrag<(Neon_vduplane
5553                                        (Neon_low4S node:$LHS), node:$RHS)>>;
5554
5555   // Index can only be half of the max value for lane in 64-bit vector
5556
5557   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
5558                         op, VPR64, VPR64Lo, v4i32, v4i16, v4i16,
5559                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5560
5561   def : NI_2VE_mul_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
5562                         op, VPR64, VPR64, v2i64, v2i32, v2i32,
5563                         BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5564
5565   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
5566                           op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H,
5567                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5568
5569   def : NI_2VEL2_mul_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
5570                           op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S,
5571                           BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5572 }
5573
5574 defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>;
5575 defm UMULL_lane_v3 : NI_2VEL_mul_v3_pat<"UMULLve", int_arm_neon_vmullu>;
5576 defm SQDMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SQDMULLve", int_arm_neon_vqdmull>;
5577
5578 multiclass NI_qdma<SDPatternOperator op> {
5579   def _4s : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
5580                     (op node:$Ra,
5581                       (v4i32 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
5582
5583   def _2d : PatFrag<(ops node:$Ra, node:$Rn, node:$Rm),
5584                     (op node:$Ra,
5585                       (v2i64 (int_arm_neon_vqdmull node:$Rn, node:$Rm)))>;
5586 }
5587
5588 defm Neon_qdmlal : NI_qdma<int_arm_neon_vqadds>;
5589 defm Neon_qdmlsl : NI_qdma<int_arm_neon_vqsubs>;
5590
5591 multiclass NI_2VEL_v3_qdma_pat<string subop, string op> {
5592   def : NI_2VE_laneq<!cast<Instruction>(subop # "_4s4h"), neon_uimm3_bare,
5593                      !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR128Lo,
5594                      v4i32, v4i16, v8i16,
5595                      BinOpFrag<(Neon_vduplane
5596                                  (Neon_low8H node:$LHS), node:$RHS)>>;
5597
5598   def : NI_2VE_laneq<!cast<Instruction>(subop # "_2d2s"), neon_uimm2_bare,
5599                      !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR128,
5600                      v2i64, v2i32, v4i32,
5601                      BinOpFrag<(Neon_vduplane
5602                                  (Neon_low4S node:$LHS), node:$RHS)>>;
5603
5604   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_4s8h"), neon_uimm3_bare,
5605                        !cast<PatFrag>(op # "_4s"), VPR128Lo,
5606                        v4i32, v8i16, v8i16, v4i16, Neon_High8H,
5607                        BinOpFrag<(Neon_vduplane
5608                                    (Neon_low8H node:$LHS), node:$RHS)>>;
5609
5610   def : NI_2VEL2_laneq<!cast<Instruction>(subop # "_2d4s"), neon_uimm2_bare,
5611                        !cast<PatFrag>(op # "_2d"), VPR128,
5612                        v2i64, v4i32, v4i32, v2i32, Neon_High4S,
5613                        BinOpFrag<(Neon_vduplane
5614                                    (Neon_low4S node:$LHS), node:$RHS)>>;
5615
5616   // Index can only be half of the max value for lane in 64-bit vector
5617
5618   def : NI_2VE_lane<!cast<Instruction>(subop # "_4s4h"), neon_uimm2_bare,
5619                     !cast<PatFrag>(op # "_4s"), VPR128, VPR64, VPR64Lo,
5620                     v4i32, v4i16, v4i16,
5621                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5622
5623   def : NI_2VE_lane<!cast<Instruction>(subop # "_2d2s"), neon_uimm1_bare,
5624                     !cast<PatFrag>(op # "_2d"), VPR128, VPR64, VPR64,
5625                     v2i64, v2i32, v2i32,
5626                     BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5627
5628   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_4s8h"), neon_uimm2_bare,
5629                       !cast<PatFrag>(op # "_4s"), VPR64Lo,
5630                       v4i32, v8i16, v4i16, v4i16, Neon_High8H,
5631                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5632
5633   def : NI_2VEL2_lane<!cast<Instruction>(subop # "_2d4s"), neon_uimm1_bare,
5634                       !cast<PatFrag>(op # "_2d"), VPR64,
5635                       v2i64, v4i32, v2i32, v2i32, Neon_High4S,
5636                       BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>;
5637 }
5638
5639 defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">;
5640 defm SQDMLSL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLSLvve", "Neon_qdmlsl">;
5641
5642 // End of implementation for instruction class (3V Elem)
5643
5644 //Insert element (vector, from main)
5645 def INSbw : NeonI_INS_main<"ins", "b", v16i8, GPR32, i32,
5646                            neon_uimm4_bare> {
5647   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5648 }
5649 def INShw : NeonI_INS_main<"ins", "h", v8i16, GPR32, i32,
5650                            neon_uimm3_bare> {
5651   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5652 }
5653 def INSsw : NeonI_INS_main<"ins", "s", v4i32, GPR32, i32,
5654                            neon_uimm2_bare> {
5655   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5656 }
5657 def INSdx : NeonI_INS_main<"ins", "d", v2i64, GPR64, i64,
5658                            neon_uimm1_bare> {
5659   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5660 }
5661
5662 class Neon_INS_main_pattern <ValueType ResTy,ValueType ExtResTy,
5663                              RegisterClass OpGPR, ValueType OpTy,
5664                              Operand OpImm, Instruction INS>
5665   : Pat<(ResTy (vector_insert
5666               (ResTy VPR64:$src),
5667               (OpTy OpGPR:$Rn),
5668               (OpImm:$Imm))),
5669         (ResTy (EXTRACT_SUBREG
5670           (ExtResTy (INS (ExtResTy (SUBREG_TO_REG (i64 0), VPR64:$src, sub_64)),
5671             OpGPR:$Rn, OpImm:$Imm)), sub_64))>;
5672
5673 def INSbw_pattern : Neon_INS_main_pattern<v8i8, v16i8, GPR32, i32,
5674                                           neon_uimm3_bare, INSbw>;
5675 def INShw_pattern : Neon_INS_main_pattern<v4i16, v8i16, GPR32, i32,
5676                                           neon_uimm2_bare, INShw>;
5677 def INSsw_pattern : Neon_INS_main_pattern<v2i32, v4i32, GPR32, i32,
5678                                           neon_uimm1_bare, INSsw>;
5679 def INSdx_pattern : Neon_INS_main_pattern<v1i64, v2i64, GPR64, i64,
5680                                           neon_uimm0_bare, INSdx>;
5681
5682 class NeonI_INS_element<string asmop, string Res, Operand ResImm>
5683   : NeonI_insert<0b1, 0b1,
5684                  (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn,
5685                  ResImm:$Immd, ResImm:$Immn),
5686                  asmop # "\t$Rd." # Res # "[$Immd], $Rn." # Res # "[$Immn]",
5687                  [],
5688                  NoItinerary> {
5689   let Constraints = "$src = $Rd";
5690   bits<4> Immd;
5691   bits<4> Immn;
5692 }
5693
5694 //Insert element (vector, from element)
5695 def INSELb : NeonI_INS_element<"ins", "b", neon_uimm4_bare> {
5696   let Inst{20-16} = {Immd{3}, Immd{2}, Immd{1}, Immd{0}, 0b1};
5697   let Inst{14-11} = {Immn{3}, Immn{2}, Immn{1}, Immn{0}};
5698 }
5699 def INSELh : NeonI_INS_element<"ins", "h", neon_uimm3_bare> {
5700   let Inst{20-16} = {Immd{2}, Immd{1}, Immd{0}, 0b1, 0b0};
5701   let Inst{14-12} = {Immn{2}, Immn{1}, Immn{0}};
5702   // bit 11 is unspecified.
5703 }
5704 def INSELs : NeonI_INS_element<"ins", "s", neon_uimm2_bare> {
5705   let Inst{20-16} = {Immd{1}, Immd{0}, 0b1, 0b0, 0b0};
5706   let Inst{14-13} = {Immn{1}, Immn{0}};
5707   // bits 11-12 are unspecified.
5708 }
5709 def INSELd : NeonI_INS_element<"ins", "d", neon_uimm1_bare> {
5710   let Inst{20-16} = {Immd, 0b1, 0b0, 0b0, 0b0};
5711   let Inst{14} = Immn{0};
5712   // bits 11-13 are unspecified.
5713 }
5714
5715 multiclass Neon_INS_elt_pattern<ValueType ResTy, ValueType NaTy,
5716                                 ValueType MidTy, Operand StImm, Operand NaImm,
5717                                 Instruction INS> {
5718 def : Pat<(ResTy (vector_insert
5719             (ResTy VPR128:$src),
5720             (MidTy (vector_extract
5721               (ResTy VPR128:$Rn),
5722               (StImm:$Immn))),
5723             (StImm:$Immd))),
5724           (INS (ResTy VPR128:$src), (ResTy VPR128:$Rn),
5725               StImm:$Immd, StImm:$Immn)>;
5726
5727 def : Pat <(ResTy (vector_insert
5728              (ResTy VPR128:$src),
5729              (MidTy (vector_extract
5730                (NaTy VPR64:$Rn),
5731                (NaImm:$Immn))),
5732              (StImm:$Immd))),
5733            (INS (ResTy VPR128:$src),
5734              (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
5735              StImm:$Immd, NaImm:$Immn)>;
5736
5737 def : Pat <(NaTy (vector_insert
5738              (NaTy VPR64:$src),
5739              (MidTy (vector_extract
5740                (ResTy VPR128:$Rn),
5741                (StImm:$Immn))),
5742              (NaImm:$Immd))),
5743            (NaTy (EXTRACT_SUBREG
5744              (ResTy (INS
5745                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
5746                (ResTy VPR128:$Rn),
5747                NaImm:$Immd, StImm:$Immn)),
5748              sub_64))>;
5749
5750 def : Pat <(NaTy (vector_insert
5751              (NaTy VPR64:$src),
5752              (MidTy (vector_extract
5753                (NaTy VPR64:$Rn),
5754                (NaImm:$Immn))),
5755              (NaImm:$Immd))),
5756            (NaTy (EXTRACT_SUBREG
5757              (ResTy (INS
5758                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
5759                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$Rn), sub_64)),
5760                NaImm:$Immd, NaImm:$Immn)),
5761              sub_64))>;
5762 }
5763
5764 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, neon_uimm2_bare,
5765                             neon_uimm1_bare, INSELs>;
5766 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, neon_uimm1_bare,
5767                             neon_uimm0_bare, INSELd>;
5768 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
5769                             neon_uimm3_bare, INSELb>;
5770 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
5771                             neon_uimm2_bare, INSELh>;
5772 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
5773                             neon_uimm1_bare, INSELs>;
5774 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, neon_uimm1_bare,
5775                             neon_uimm0_bare, INSELd>;
5776
5777 multiclass Neon_INS_elt_float_pattern<ValueType ResTy, ValueType NaTy,
5778                                       ValueType MidTy,
5779                                       RegisterClass OpFPR, Operand ResImm,
5780                                       SubRegIndex SubIndex, Instruction INS> {
5781 def : Pat <(ResTy (vector_insert
5782              (ResTy VPR128:$src),
5783              (MidTy OpFPR:$Rn),
5784              (ResImm:$Imm))),
5785            (INS (ResTy VPR128:$src),
5786              (ResTy (SUBREG_TO_REG (i64 0), OpFPR:$Rn, SubIndex)),
5787              ResImm:$Imm,
5788              (i64 0))>;
5789
5790 def : Pat <(NaTy (vector_insert
5791              (NaTy VPR64:$src),
5792              (MidTy OpFPR:$Rn),
5793              (ResImm:$Imm))),
5794            (NaTy (EXTRACT_SUBREG
5795              (ResTy (INS
5796                (ResTy (SUBREG_TO_REG (i64 0), (NaTy VPR64:$src), sub_64)),
5797                (ResTy (SUBREG_TO_REG (i64 0), (MidTy OpFPR:$Rn), SubIndex)),
5798                ResImm:$Imm,
5799                (i64 0))),
5800              sub_64))>;
5801 }
5802
5803 defm : Neon_INS_elt_float_pattern<v4f32, v2f32, f32, FPR32, neon_uimm2_bare,
5804                                   sub_32, INSELs>;
5805 defm : Neon_INS_elt_float_pattern<v2f64, v1f64, f64, FPR64, neon_uimm1_bare,
5806                                   sub_64, INSELd>;
5807
5808 class NeonI_SMOV<string asmop, string Res, bit Q,
5809                  ValueType OpTy, ValueType eleTy,
5810                  Operand OpImm, RegisterClass ResGPR, ValueType ResTy>
5811   : NeonI_copy<Q, 0b0, 0b0101,
5812                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
5813                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
5814                [(set (ResTy ResGPR:$Rd),
5815                  (ResTy (sext_inreg
5816                    (ResTy (vector_extract
5817                      (OpTy VPR128:$Rn), (OpImm:$Imm))),
5818                    eleTy)))],
5819                NoItinerary> {
5820   bits<4> Imm;
5821 }
5822
5823 //Signed integer move (main, from element)
5824 def SMOVwb : NeonI_SMOV<"smov", "b", 0b0, v16i8, i8, neon_uimm4_bare,
5825                         GPR32, i32> {
5826   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5827 }
5828 def SMOVwh : NeonI_SMOV<"smov", "h", 0b0, v8i16, i16, neon_uimm3_bare,
5829                         GPR32, i32> {
5830   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5831 }
5832 def SMOVxb : NeonI_SMOV<"smov", "b", 0b1, v16i8, i8, neon_uimm4_bare,
5833                         GPR64, i64> {
5834   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5835 }
5836 def SMOVxh : NeonI_SMOV<"smov", "h", 0b1, v8i16, i16, neon_uimm3_bare,
5837                         GPR64, i64> {
5838   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5839 }
5840 def SMOVxs : NeonI_SMOV<"smov", "s", 0b1, v4i32, i32, neon_uimm2_bare,
5841                         GPR64, i64> {
5842   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5843 }
5844
5845 multiclass Neon_SMOVx_pattern <ValueType StTy, ValueType NaTy,
5846                                ValueType eleTy, Operand StImm,  Operand NaImm,
5847                                Instruction SMOVI> {
5848   def : Pat<(i64 (sext_inreg
5849               (i64 (anyext
5850                 (i32 (vector_extract
5851                   (StTy VPR128:$Rn), (StImm:$Imm))))),
5852               eleTy)),
5853             (SMOVI VPR128:$Rn, StImm:$Imm)>;
5854
5855   def : Pat<(i64 (sext
5856               (i32 (vector_extract
5857                 (StTy VPR128:$Rn), (StImm:$Imm))))),
5858             (SMOVI VPR128:$Rn, StImm:$Imm)>;
5859
5860   def : Pat<(i64 (sext_inreg
5861               (i64 (vector_extract
5862                 (NaTy VPR64:$Rn), (NaImm:$Imm))),
5863               eleTy)),
5864             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5865               NaImm:$Imm)>;
5866
5867   def : Pat<(i64 (sext_inreg
5868               (i64 (anyext
5869                 (i32 (vector_extract
5870                   (NaTy VPR64:$Rn), (NaImm:$Imm))))),
5871               eleTy)),
5872             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5873               NaImm:$Imm)>;
5874
5875   def : Pat<(i64 (sext
5876               (i32 (vector_extract
5877                 (NaTy VPR64:$Rn), (NaImm:$Imm))))),
5878             (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5879               NaImm:$Imm)>;
5880 }
5881
5882 defm : Neon_SMOVx_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
5883                           neon_uimm3_bare, SMOVxb>;
5884 defm : Neon_SMOVx_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
5885                           neon_uimm2_bare, SMOVxh>;
5886 defm : Neon_SMOVx_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
5887                           neon_uimm1_bare, SMOVxs>;
5888
5889 class Neon_SMOVw_pattern <ValueType StTy, ValueType NaTy,
5890                           ValueType eleTy, Operand StImm,  Operand NaImm,
5891                           Instruction SMOVI>
5892   : Pat<(i32 (sext_inreg
5893           (i32 (vector_extract
5894             (NaTy VPR64:$Rn), (NaImm:$Imm))),
5895           eleTy)),
5896         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5897           NaImm:$Imm)>;
5898
5899 def : Neon_SMOVw_pattern<v16i8, v8i8, i8, neon_uimm4_bare,
5900                          neon_uimm3_bare, SMOVwb>;
5901 def : Neon_SMOVw_pattern<v8i16, v4i16, i16, neon_uimm3_bare,
5902                          neon_uimm2_bare, SMOVwh>;
5903
5904 class NeonI_UMOV<string asmop, string Res, bit Q,
5905                  ValueType OpTy, Operand OpImm,
5906                  RegisterClass ResGPR, ValueType ResTy>
5907   : NeonI_copy<Q, 0b0, 0b0111,
5908                (outs ResGPR:$Rd), (ins VPR128:$Rn, OpImm:$Imm),
5909                asmop # "\t$Rd, $Rn." # Res # "[$Imm]",
5910                [(set (ResTy ResGPR:$Rd),
5911                   (ResTy (vector_extract
5912                     (OpTy VPR128:$Rn), (OpImm:$Imm))))],
5913                NoItinerary> {
5914   bits<4> Imm;
5915 }
5916
5917 //Unsigned integer move (main, from element)
5918 def UMOVwb : NeonI_UMOV<"umov", "b", 0b0, v16i8, neon_uimm4_bare,
5919                          GPR32, i32> {
5920   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
5921 }
5922 def UMOVwh : NeonI_UMOV<"umov", "h", 0b0, v8i16, neon_uimm3_bare,
5923                          GPR32, i32> {
5924   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
5925 }
5926 def UMOVws : NeonI_UMOV<"umov", "s", 0b0, v4i32, neon_uimm2_bare,
5927                          GPR32, i32> {
5928   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
5929 }
5930 def UMOVxd : NeonI_UMOV<"umov", "d", 0b1, v2i64, neon_uimm1_bare,
5931                          GPR64, i64> {
5932   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
5933 }
5934
5935 class Neon_UMOV_pattern <ValueType StTy, ValueType NaTy, ValueType ResTy,
5936                          Operand StImm,  Operand NaImm,
5937                          Instruction SMOVI>
5938   : Pat<(ResTy (vector_extract
5939           (NaTy VPR64:$Rn), NaImm:$Imm)),
5940         (SMOVI (StTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
5941           NaImm:$Imm)>;
5942
5943 def : Neon_UMOV_pattern<v16i8, v8i8, i32, neon_uimm4_bare,
5944                         neon_uimm3_bare, UMOVwb>;
5945 def : Neon_UMOV_pattern<v8i16, v4i16, i32, neon_uimm3_bare,
5946                         neon_uimm2_bare, UMOVwh>;
5947 def : Neon_UMOV_pattern<v4i32, v2i32, i32, neon_uimm2_bare,
5948                         neon_uimm1_bare, UMOVws>;
5949
5950 def : Pat<(i32 (and
5951             (i32 (vector_extract
5952               (v16i8 VPR128:$Rn), (neon_uimm4_bare:$Imm))),
5953             255)),
5954           (UMOVwb VPR128:$Rn, neon_uimm4_bare:$Imm)>;
5955
5956 def : Pat<(i32 (and
5957             (i32 (vector_extract
5958               (v8i16 VPR128:$Rn), (neon_uimm3_bare:$Imm))),
5959             65535)),
5960           (UMOVwh VPR128:$Rn, neon_uimm3_bare:$Imm)>;
5961
5962 def : Pat<(i64 (zext
5963             (i32 (vector_extract
5964               (v2i64 VPR128:$Rn), (neon_uimm1_bare:$Imm))))),
5965           (UMOVxd VPR128:$Rn, neon_uimm1_bare:$Imm)>;
5966
5967 def : Pat<(i32 (and
5968             (i32 (vector_extract
5969               (v8i8 VPR64:$Rn), (neon_uimm3_bare:$Imm))),
5970             255)),
5971           (UMOVwb (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
5972             neon_uimm3_bare:$Imm)>;
5973
5974 def : Pat<(i32 (and
5975             (i32 (vector_extract
5976               (v4i16 VPR64:$Rn), (neon_uimm2_bare:$Imm))),
5977             65535)),
5978           (UMOVwh (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
5979             neon_uimm2_bare:$Imm)>;
5980
5981 def : Pat<(i64 (zext
5982             (i32 (vector_extract
5983               (v1i64 VPR64:$Rn), (neon_uimm0_bare:$Imm))))),
5984           (UMOVxd (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64),
5985             neon_uimm0_bare:$Imm)>;
5986
5987 // Additional copy patterns for scalar types
5988 def : Pat<(i32 (vector_extract (v1i8 FPR8:$Rn), (i64 0))),
5989           (UMOVwb (v16i8
5990             (SUBREG_TO_REG (i64 0), FPR8:$Rn, sub_8)), (i64 0))>;
5991
5992 def : Pat<(i32 (vector_extract (v1i16 FPR16:$Rn), (i64 0))),
5993           (UMOVwh (v8i16
5994             (SUBREG_TO_REG (i64 0), FPR16:$Rn, sub_16)), (i64 0))>;
5995
5996 def : Pat<(i32 (vector_extract (v1i32 FPR32:$Rn), (i64 0))),
5997           (FMOVws FPR32:$Rn)>;
5998
5999 def : Pat<(i64 (vector_extract (v1i64 FPR64:$Rn), (i64 0))),
6000           (FMOVxd FPR64:$Rn)>;
6001
6002 def : Pat<(f64 (vector_extract (v1f64 FPR64:$Rn), (i64 0))),
6003           (f64 FPR64:$Rn)>;
6004
6005 def : Pat<(f32 (vector_extract (v1f32 FPR32:$Rn), (i64 0))),
6006           (f32 FPR32:$Rn)>;
6007
6008 def : Pat<(v1i8 (scalar_to_vector GPR32:$Rn)),
6009           (v1i8 (EXTRACT_SUBREG (v16i8
6010             (INSbw (v16i8 (IMPLICIT_DEF)), $Rn, (i64 0))),
6011             sub_8))>;
6012
6013 def : Pat<(v1i16 (scalar_to_vector GPR32:$Rn)),
6014           (v1i16 (EXTRACT_SUBREG (v8i16
6015             (INShw (v8i16 (IMPLICIT_DEF)), $Rn, (i64 0))),
6016             sub_16))>;
6017
6018 def : Pat<(v1i32 (scalar_to_vector GPR32:$src)),
6019           (FMOVsw $src)>;
6020
6021 def : Pat<(v1i64 (scalar_to_vector GPR64:$src)),
6022           (FMOVdx $src)>;
6023
6024 def : Pat<(v1f32 (scalar_to_vector (f32 FPR32:$Rn))),
6025           (v1f32 FPR32:$Rn)>;
6026 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Rn))),
6027           (v1f64 FPR64:$Rn)>;
6028
6029 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$src))),
6030           (FMOVdd $src)>;
6031
6032 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$src))),
6033           (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
6034                          (f64 FPR64:$src), sub_64)>;
6035
6036 class NeonI_DUP_Elt<bit Q, string asmop, string rdlane,  string rnlane,
6037                     RegisterOperand ResVPR, Operand OpImm>
6038   : NeonI_copy<Q, 0b0, 0b0000, (outs ResVPR:$Rd),
6039                (ins VPR128:$Rn, OpImm:$Imm),
6040                asmop # "\t$Rd" # rdlane # ", $Rn" # rnlane # "[$Imm]",
6041                [],
6042                NoItinerary> {
6043   bits<4> Imm;
6044 }
6045
6046 def DUPELT16b : NeonI_DUP_Elt<0b1, "dup", ".16b", ".b", VPR128,
6047                               neon_uimm4_bare> {
6048   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6049 }
6050
6051 def DUPELT8h : NeonI_DUP_Elt<0b1, "dup", ".8h", ".h", VPR128,
6052                               neon_uimm3_bare> {
6053   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6054 }
6055
6056 def DUPELT4s : NeonI_DUP_Elt<0b1, "dup", ".4s", ".s", VPR128,
6057                               neon_uimm2_bare> {
6058   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6059 }
6060
6061 def DUPELT2d : NeonI_DUP_Elt<0b1, "dup", ".2d", ".d", VPR128,
6062                               neon_uimm1_bare> {
6063   let Inst{20-16} = {Imm, 0b1, 0b0, 0b0, 0b0};
6064 }
6065
6066 def DUPELT8b : NeonI_DUP_Elt<0b0, "dup", ".8b", ".b", VPR64,
6067                               neon_uimm4_bare> {
6068   let Inst{20-16} = {Imm{3}, Imm{2}, Imm{1}, Imm{0}, 0b1};
6069 }
6070
6071 def DUPELT4h : NeonI_DUP_Elt<0b0, "dup", ".4h", ".h", VPR64,
6072                               neon_uimm3_bare> {
6073   let Inst{20-16} = {Imm{2}, Imm{1}, Imm{0}, 0b1, 0b0};
6074 }
6075
6076 def DUPELT2s : NeonI_DUP_Elt<0b0, "dup", ".2s", ".s", VPR64,
6077                               neon_uimm2_bare> {
6078   let Inst{20-16} = {Imm{1}, Imm{0}, 0b1, 0b0, 0b0};
6079 }
6080
6081 multiclass NeonI_DUP_Elt_pattern<Instruction DUPELT, ValueType ResTy,
6082                                        ValueType OpTy,ValueType NaTy,
6083                                        ValueType ExTy, Operand OpLImm,
6084                                        Operand OpNImm> {
6085 def  : Pat<(ResTy (Neon_vduplane (OpTy VPR128:$Rn), OpLImm:$Imm)),
6086         (ResTy (DUPELT (OpTy VPR128:$Rn), OpLImm:$Imm))>;
6087
6088 def : Pat<(ResTy (Neon_vduplane
6089             (NaTy VPR64:$Rn), OpNImm:$Imm)),
6090           (ResTy (DUPELT
6091             (ExTy (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)), OpNImm:$Imm))>;
6092 }
6093 defm : NeonI_DUP_Elt_pattern<DUPELT16b, v16i8, v16i8, v8i8, v16i8,
6094                              neon_uimm4_bare, neon_uimm3_bare>;
6095 defm : NeonI_DUP_Elt_pattern<DUPELT8b, v8i8, v16i8, v8i8, v16i8,
6096                              neon_uimm4_bare, neon_uimm3_bare>;
6097 defm : NeonI_DUP_Elt_pattern<DUPELT8h, v8i16, v8i16, v4i16, v8i16,
6098                              neon_uimm3_bare, neon_uimm2_bare>;
6099 defm : NeonI_DUP_Elt_pattern<DUPELT4h, v4i16, v8i16, v4i16, v8i16,
6100                              neon_uimm3_bare, neon_uimm2_bare>;
6101 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4i32, v4i32, v2i32, v4i32,
6102                              neon_uimm2_bare, neon_uimm1_bare>;
6103 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2i32, v4i32, v2i32, v4i32,
6104                              neon_uimm2_bare, neon_uimm1_bare>;
6105 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2i64, v2i64, v1i64, v2i64,
6106                              neon_uimm1_bare, neon_uimm0_bare>;
6107 defm : NeonI_DUP_Elt_pattern<DUPELT4s, v4f32, v4f32, v2f32, v4f32,
6108                              neon_uimm2_bare, neon_uimm1_bare>;
6109 defm : NeonI_DUP_Elt_pattern<DUPELT2s, v2f32, v4f32, v2f32, v4f32,
6110                              neon_uimm2_bare, neon_uimm1_bare>;
6111 defm : NeonI_DUP_Elt_pattern<DUPELT2d, v2f64, v2f64, v1f64, v2f64,
6112                              neon_uimm1_bare, neon_uimm0_bare>;
6113
6114 def : Pat<(v2f32 (Neon_vdup (f32 FPR32:$Rn))),
6115           (v2f32 (DUPELT2s
6116             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6117             (i64 0)))>;
6118 def : Pat<(v4f32 (Neon_vdup (f32 FPR32:$Rn))),
6119           (v4f32 (DUPELT4s
6120             (SUBREG_TO_REG (i64 0), FPR32:$Rn, sub_32),
6121             (i64 0)))>;
6122 def : Pat<(v2f64 (Neon_vdup (f64 FPR64:$Rn))),
6123           (v2f64 (DUPELT2d
6124             (SUBREG_TO_REG (i64 0), FPR64:$Rn, sub_64),
6125             (i64 0)))>;
6126
6127 class NeonI_DUP<bit Q, string asmop, string rdlane,
6128                 RegisterOperand ResVPR, ValueType ResTy,
6129                 RegisterClass OpGPR, ValueType OpTy>
6130   : NeonI_copy<Q, 0b0, 0b0001, (outs ResVPR:$Rd), (ins OpGPR:$Rn),
6131                asmop # "\t$Rd" # rdlane # ", $Rn",
6132                [(set (ResTy ResVPR:$Rd),
6133                  (ResTy (Neon_vdup (OpTy OpGPR:$Rn))))],
6134                NoItinerary>;
6135
6136 def DUP16b : NeonI_DUP<0b1, "dup", ".16b", VPR128, v16i8, GPR32, i32> {
6137   let Inst{16} = 0b1;
6138   // bits 17-19 are unspecified.
6139 }
6140
6141 def DUP8h : NeonI_DUP<0b1, "dup", ".8h", VPR128, v8i16, GPR32, i32> {
6142   let Inst{17-16} = 0b10;
6143   // bits 18-19 are unspecified.
6144 }
6145
6146 def DUP4s : NeonI_DUP<0b1, "dup", ".4s", VPR128, v4i32, GPR32, i32> {
6147   let Inst{18-16} = 0b100;
6148   // bit 19 is unspecified.
6149 }
6150
6151 def DUP2d : NeonI_DUP<0b1, "dup", ".2d", VPR128, v2i64, GPR64, i64> {
6152   let Inst{19-16} = 0b1000;
6153 }
6154
6155 def DUP8b : NeonI_DUP<0b0, "dup", ".8b", VPR64, v8i8, GPR32, i32> {
6156   let Inst{16} = 0b1;
6157   // bits 17-19 are unspecified.
6158 }
6159
6160 def DUP4h : NeonI_DUP<0b0, "dup", ".4h", VPR64, v4i16, GPR32, i32> {
6161   let Inst{17-16} = 0b10;
6162   // bits 18-19 are unspecified.
6163 }
6164
6165 def DUP2s : NeonI_DUP<0b0, "dup", ".2s", VPR64, v2i32, GPR32, i32> {
6166   let Inst{18-16} = 0b100;
6167   // bit 19 is unspecified.
6168 }
6169
6170 // patterns for CONCAT_VECTORS
6171 multiclass Concat_Vector_Pattern<ValueType ResTy, ValueType OpTy> {
6172 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), undef)),
6173           (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)>;
6174 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rm))),
6175           (INSELd
6176             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6177             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rm, sub_64)),
6178             (i64 1),
6179             (i64 0))>;
6180 def : Pat<(ResTy (concat_vectors (OpTy VPR64:$Rn), (OpTy VPR64:$Rn))),
6181           (DUPELT2d
6182             (v2i64 (SUBREG_TO_REG (i64 0), VPR64:$Rn, sub_64)),
6183             (i64 0))> ;
6184 }
6185
6186 defm : Concat_Vector_Pattern<v16i8, v8i8>;
6187 defm : Concat_Vector_Pattern<v8i16, v4i16>;
6188 defm : Concat_Vector_Pattern<v4i32, v2i32>;
6189 defm : Concat_Vector_Pattern<v2i64, v1i64>;
6190 defm : Concat_Vector_Pattern<v4f32, v2f32>;
6191 defm : Concat_Vector_Pattern<v2f64, v1f64>;
6192
6193 //patterns for EXTRACT_SUBVECTOR
6194 def : Pat<(v8i8 (extract_subvector (v16i8 VPR128:$Rn), (i64 0))),
6195           (v8i8 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6196 def : Pat<(v4i16 (extract_subvector (v8i16 VPR128:$Rn), (i64 0))),
6197           (v4i16 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6198 def : Pat<(v2i32 (extract_subvector (v4i32 VPR128:$Rn), (i64 0))),
6199           (v2i32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6200 def : Pat<(v1i64 (extract_subvector (v2i64 VPR128:$Rn), (i64 0))),
6201           (v1i64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6202 def : Pat<(v2f32 (extract_subvector (v4f32 VPR128:$Rn), (i64 0))),
6203           (v2f32 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6204 def : Pat<(v1f64 (extract_subvector (v2f64 VPR128:$Rn), (i64 0))),
6205           (v1f64 (EXTRACT_SUBREG VPR128:$Rn, sub_64))>;
6206
6207 // Crypto Class
6208 class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
6209                          string asmop, SDPatternOperator opnode>
6210   : NeonI_Crypto_AES<size, opcode,
6211                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
6212                      asmop # "\t$Rd.16b, $Rn.16b",
6213                      [(set (v16i8 VPR128:$Rd),
6214                         (v16i8 (opnode (v16i8 VPR128:$src),
6215                                        (v16i8 VPR128:$Rn))))],
6216                      NoItinerary>{
6217   let Constraints = "$src = $Rd";
6218 }
6219
6220 def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
6221 def AESD : NeonI_Cryptoaes_2v<0b00, 0b00101, "aesd", int_arm_neon_aesd>;
6222
6223 class NeonI_Cryptoaes<bits<2> size, bits<5> opcode,
6224                       string asmop, SDPatternOperator opnode>
6225   : NeonI_Crypto_AES<size, opcode,
6226                      (outs VPR128:$Rd), (ins VPR128:$Rn),
6227                      asmop # "\t$Rd.16b, $Rn.16b",
6228                      [(set (v16i8 VPR128:$Rd),
6229                         (v16i8 (opnode (v16i8 VPR128:$Rn))))],
6230                      NoItinerary>;
6231
6232 def AESMC : NeonI_Cryptoaes<0b00, 0b00110, "aesmc", int_arm_neon_aesmc>;
6233 def AESIMC : NeonI_Cryptoaes<0b00, 0b00111, "aesimc", int_arm_neon_aesimc>;
6234
6235 class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
6236                          string asmop, SDPatternOperator opnode>
6237   : NeonI_Crypto_SHA<size, opcode,
6238                      (outs VPR128:$Rd), (ins VPR128:$src, VPR128:$Rn),
6239                      asmop # "\t$Rd.4s, $Rn.4s",
6240                      [(set (v4i32 VPR128:$Rd),
6241                         (v4i32 (opnode (v4i32 VPR128:$src),
6242                                        (v4i32 VPR128:$Rn))))],
6243                      NoItinerary> {
6244   let Constraints = "$src = $Rd";
6245 }
6246
6247 def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
6248                                  int_arm_neon_sha1su1>;
6249 def SHA256SU0 : NeonI_Cryptosha_vv<0b00, 0b00010, "sha256su0",
6250                                    int_arm_neon_sha256su0>;
6251
6252 class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
6253                          string asmop, SDPatternOperator opnode>
6254   : NeonI_Crypto_SHA<size, opcode,
6255                      (outs FPR32:$Rd), (ins FPR32:$Rn),
6256                      asmop # "\t$Rd, $Rn",
6257                      [(set (v1i32 FPR32:$Rd),
6258                         (v1i32 (opnode (v1i32 FPR32:$Rn))))],
6259                      NoItinerary>;
6260
6261 def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
6262
6263 class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
6264                            SDPatternOperator opnode>
6265   : NeonI_Crypto_3VSHA<size, opcode,
6266                        (outs VPR128:$Rd),
6267                        (ins VPR128:$src, VPR128:$Rn, VPR128:$Rm),
6268                        asmop # "\t$Rd.4s, $Rn.4s, $Rm.4s",
6269                        [(set (v4i32 VPR128:$Rd),
6270                           (v4i32 (opnode (v4i32 VPR128:$src),
6271                                          (v4i32 VPR128:$Rn),
6272                                          (v4i32 VPR128:$Rm))))],
6273                        NoItinerary> {
6274   let Constraints = "$src = $Rd";
6275 }
6276
6277 def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
6278                                    int_arm_neon_sha1su0>;
6279 def SHA256SU1 : NeonI_Cryptosha3_vvv<0b00, 0b110, "sha256su1",
6280                                      int_arm_neon_sha256su1>;
6281
6282 class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
6283                            SDPatternOperator opnode>
6284   : NeonI_Crypto_3VSHA<size, opcode,
6285                        (outs FPR128:$Rd),
6286                        (ins FPR128:$src, FPR128:$Rn, VPR128:$Rm),
6287                        asmop # "\t$Rd, $Rn, $Rm.4s",
6288                        [(set (v4i32 FPR128:$Rd),
6289                           (v4i32 (opnode (v4i32 FPR128:$src),
6290                                          (v4i32 FPR128:$Rn),
6291                                          (v4i32 VPR128:$Rm))))],
6292                        NoItinerary> {
6293   let Constraints = "$src = $Rd";
6294 }
6295
6296 def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
6297                                    int_arm_neon_sha256h>;
6298 def SHA256H2 : NeonI_Cryptosha3_qqv<0b00, 0b101, "sha256h2",
6299                                     int_arm_neon_sha256h2>;
6300
6301 class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
6302                            SDPatternOperator opnode>
6303   : NeonI_Crypto_3VSHA<size, opcode,
6304                        (outs FPR128:$Rd),
6305                        (ins FPR128:$src, FPR32:$Rn, VPR128:$Rm),
6306                        asmop # "\t$Rd, $Rn, $Rm.4s",
6307                        [(set (v4i32 FPR128:$Rd),
6308                           (v4i32 (opnode (v4i32 FPR128:$src),
6309                                          (v1i32 FPR32:$Rn),
6310                                          (v4i32 VPR128:$Rm))))],
6311                        NoItinerary> {
6312   let Constraints = "$src = $Rd";
6313 }
6314
6315 def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
6316 def SHA1P : NeonI_Cryptosha3_qsv<0b00, 0b001, "sha1p", int_aarch64_neon_sha1p>;
6317 def SHA1M : NeonI_Cryptosha3_qsv<0b00, 0b010, "sha1m", int_aarch64_neon_sha1m>;
6318