1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe AArch64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // AArch64 Instruction Format
25 class AArch64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "AArch64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : AArch64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
94 let DiagnosticType = "InvalidMovImm32Shift";
96 def MovImm64ShifterOperand : AsmOperandClass {
97 let SuperClasses = [ShifterOperand];
98 let Name = "MovImm64Shifter";
99 let RenderMethod = "addShifterOperands";
100 let DiagnosticType = "InvalidMovImm64Shift";
103 // Shifter operand for arithmetic register shifted encodings.
104 class ArithmeticShifterOperand<int width> : AsmOperandClass {
105 let SuperClasses = [ShifterOperand];
106 let Name = "ArithmeticShifter" # width;
107 let PredicateMethod = "isArithmeticShifter<" # width # ">";
108 let RenderMethod = "addShifterOperands";
109 let DiagnosticType = "AddSubRegShift" # width;
112 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
113 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
115 // Shifter operand for logical register shifted encodings.
116 class LogicalShifterOperand<int width> : AsmOperandClass {
117 let SuperClasses = [ShifterOperand];
118 let Name = "LogicalShifter" # width;
119 let PredicateMethod = "isLogicalShifter<" # width # ">";
120 let RenderMethod = "addShifterOperands";
121 let DiagnosticType = "AddSubRegShift" # width;
124 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
125 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
127 // Shifter operand for logical vector 128/64-bit shifted encodings.
128 def LogicalVecShifterOperand : AsmOperandClass {
129 let SuperClasses = [ShifterOperand];
130 let Name = "LogicalVecShifter";
131 let RenderMethod = "addShifterOperands";
133 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
134 let SuperClasses = [LogicalVecShifterOperand];
135 let Name = "LogicalVecHalfWordShifter";
136 let RenderMethod = "addShifterOperands";
139 // The "MSL" shifter on the vector MOVI instruction.
140 def MoveVecShifterOperand : AsmOperandClass {
141 let SuperClasses = [ShifterOperand];
142 let Name = "MoveVecShifter";
143 let RenderMethod = "addShifterOperands";
146 // Extend operand for arithmetic encodings.
147 def ExtendOperand : AsmOperandClass {
149 let DiagnosticType = "AddSubRegExtendLarge";
151 def ExtendOperand64 : AsmOperandClass {
152 let SuperClasses = [ExtendOperand];
153 let Name = "Extend64";
154 let DiagnosticType = "AddSubRegExtendSmall";
156 // 'extend' that's a lsl of a 64-bit register.
157 def ExtendOperandLSL64 : AsmOperandClass {
158 let SuperClasses = [ExtendOperand];
159 let Name = "ExtendLSL64";
160 let RenderMethod = "addExtend64Operands";
161 let DiagnosticType = "AddSubRegExtendLarge";
164 // 8-bit floating-point immediate encodings.
165 def FPImmOperand : AsmOperandClass {
167 let ParserMethod = "tryParseFPImm";
168 let DiagnosticType = "InvalidFPImm";
171 def CondCode : AsmOperandClass {
172 let Name = "CondCode";
173 let DiagnosticType = "InvalidCondCode";
176 // A 32-bit register pasrsed as 64-bit
177 def GPR32as64Operand : AsmOperandClass {
178 let Name = "GPR32as64";
180 def GPR32as64 : RegisterOperand<GPR32> {
181 let ParserMatchClass = GPR32as64Operand;
184 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
185 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
186 // are encoded as the eight bit value 'abcdefgh'.
187 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
190 //===----------------------------------------------------------------------===//
191 // Operand Definitions.
194 // ADR[P] instruction labels.
195 def AdrpOperand : AsmOperandClass {
196 let Name = "AdrpLabel";
197 let ParserMethod = "tryParseAdrpLabel";
198 let DiagnosticType = "InvalidLabel";
200 def adrplabel : Operand<i64> {
201 let EncoderMethod = "getAdrLabelOpValue";
202 let PrintMethod = "printAdrpLabel";
203 let ParserMatchClass = AdrpOperand;
206 def AdrOperand : AsmOperandClass {
207 let Name = "AdrLabel";
208 let ParserMethod = "tryParseAdrLabel";
209 let DiagnosticType = "InvalidLabel";
211 def adrlabel : Operand<i64> {
212 let EncoderMethod = "getAdrLabelOpValue";
213 let ParserMatchClass = AdrOperand;
216 // simm9 predicate - True if the immediate is in the range [-256, 255].
217 def SImm9Operand : AsmOperandClass {
219 let DiagnosticType = "InvalidMemoryIndexedSImm9";
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
222 let ParserMatchClass = SImm9Operand;
225 // simm7sN predicate - True if the immediate is a multiple of N in the range
226 // [-64 * N, 63 * N].
227 class SImm7Scaled<int Scale> : AsmOperandClass {
228 let Name = "SImm7s" # Scale;
229 let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
232 def SImm7s4Operand : SImm7Scaled<4>;
233 def SImm7s8Operand : SImm7Scaled<8>;
234 def SImm7s16Operand : SImm7Scaled<16>;
236 def simm7s4 : Operand<i32> {
237 let ParserMatchClass = SImm7s4Operand;
238 let PrintMethod = "printImmScale<4>";
241 def simm7s8 : Operand<i32> {
242 let ParserMatchClass = SImm7s8Operand;
243 let PrintMethod = "printImmScale<8>";
246 def simm7s16 : Operand<i32> {
247 let ParserMatchClass = SImm7s16Operand;
248 let PrintMethod = "printImmScale<16>";
251 class AsmImmRange<int Low, int High> : AsmOperandClass {
252 let Name = "Imm" # Low # "_" # High;
253 let DiagnosticType = "InvalidImm" # Low # "_" # High;
256 def Imm1_8Operand : AsmImmRange<1, 8>;
257 def Imm1_16Operand : AsmImmRange<1, 16>;
258 def Imm1_32Operand : AsmImmRange<1, 32>;
259 def Imm1_64Operand : AsmImmRange<1, 64>;
261 def MovZSymbolG3AsmOperand : AsmOperandClass {
262 let Name = "MovZSymbolG3";
263 let RenderMethod = "addImmOperands";
266 def movz_symbol_g3 : Operand<i32> {
267 let ParserMatchClass = MovZSymbolG3AsmOperand;
270 def MovZSymbolG2AsmOperand : AsmOperandClass {
271 let Name = "MovZSymbolG2";
272 let RenderMethod = "addImmOperands";
275 def movz_symbol_g2 : Operand<i32> {
276 let ParserMatchClass = MovZSymbolG2AsmOperand;
279 def MovZSymbolG1AsmOperand : AsmOperandClass {
280 let Name = "MovZSymbolG1";
281 let RenderMethod = "addImmOperands";
284 def movz_symbol_g1 : Operand<i32> {
285 let ParserMatchClass = MovZSymbolG1AsmOperand;
288 def MovZSymbolG0AsmOperand : AsmOperandClass {
289 let Name = "MovZSymbolG0";
290 let RenderMethod = "addImmOperands";
293 def movz_symbol_g0 : Operand<i32> {
294 let ParserMatchClass = MovZSymbolG0AsmOperand;
297 def MovKSymbolG3AsmOperand : AsmOperandClass {
298 let Name = "MovKSymbolG3";
299 let RenderMethod = "addImmOperands";
302 def movk_symbol_g3 : Operand<i32> {
303 let ParserMatchClass = MovKSymbolG3AsmOperand;
306 def MovKSymbolG2AsmOperand : AsmOperandClass {
307 let Name = "MovKSymbolG2";
308 let RenderMethod = "addImmOperands";
311 def movk_symbol_g2 : Operand<i32> {
312 let ParserMatchClass = MovKSymbolG2AsmOperand;
315 def MovKSymbolG1AsmOperand : AsmOperandClass {
316 let Name = "MovKSymbolG1";
317 let RenderMethod = "addImmOperands";
320 def movk_symbol_g1 : Operand<i32> {
321 let ParserMatchClass = MovKSymbolG1AsmOperand;
324 def MovKSymbolG0AsmOperand : AsmOperandClass {
325 let Name = "MovKSymbolG0";
326 let RenderMethod = "addImmOperands";
329 def movk_symbol_g0 : Operand<i32> {
330 let ParserMatchClass = MovKSymbolG0AsmOperand;
333 class fixedpoint_i32<ValueType FloatVT>
335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
336 let EncoderMethod = "getFixedPointScaleOpValue";
337 let DecoderMethod = "DecodeFixedPointScaleImm32";
338 let ParserMatchClass = Imm1_32Operand;
341 class fixedpoint_i64<ValueType FloatVT>
343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
344 let EncoderMethod = "getFixedPointScaleOpValue";
345 let DecoderMethod = "DecodeFixedPointScaleImm64";
346 let ParserMatchClass = Imm1_64Operand;
349 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
350 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
352 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
353 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
355 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
356 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
358 let EncoderMethod = "getVecShiftR8OpValue";
359 let DecoderMethod = "DecodeVecShiftR8Imm";
360 let ParserMatchClass = Imm1_8Operand;
362 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
363 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
365 let EncoderMethod = "getVecShiftR16OpValue";
366 let DecoderMethod = "DecodeVecShiftR16Imm";
367 let ParserMatchClass = Imm1_16Operand;
369 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
370 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
372 let EncoderMethod = "getVecShiftR16OpValue";
373 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
374 let ParserMatchClass = Imm1_8Operand;
376 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
377 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
379 let EncoderMethod = "getVecShiftR32OpValue";
380 let DecoderMethod = "DecodeVecShiftR32Imm";
381 let ParserMatchClass = Imm1_32Operand;
383 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
384 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
386 let EncoderMethod = "getVecShiftR32OpValue";
387 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
388 let ParserMatchClass = Imm1_16Operand;
390 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
391 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
393 let EncoderMethod = "getVecShiftR64OpValue";
394 let DecoderMethod = "DecodeVecShiftR64Imm";
395 let ParserMatchClass = Imm1_64Operand;
397 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
398 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
400 let EncoderMethod = "getVecShiftR64OpValue";
401 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
402 let ParserMatchClass = Imm1_32Operand;
405 def Imm0_7Operand : AsmImmRange<0, 7>;
406 def Imm0_15Operand : AsmImmRange<0, 15>;
407 def Imm0_31Operand : AsmImmRange<0, 31>;
408 def Imm0_63Operand : AsmImmRange<0, 63>;
410 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
411 return (((uint32_t)Imm) < 8);
413 let EncoderMethod = "getVecShiftL8OpValue";
414 let DecoderMethod = "DecodeVecShiftL8Imm";
415 let ParserMatchClass = Imm0_7Operand;
417 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
418 return (((uint32_t)Imm) < 16);
420 let EncoderMethod = "getVecShiftL16OpValue";
421 let DecoderMethod = "DecodeVecShiftL16Imm";
422 let ParserMatchClass = Imm0_15Operand;
424 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
425 return (((uint32_t)Imm) < 32);
427 let EncoderMethod = "getVecShiftL32OpValue";
428 let DecoderMethod = "DecodeVecShiftL32Imm";
429 let ParserMatchClass = Imm0_31Operand;
431 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
432 return (((uint32_t)Imm) < 64);
434 let EncoderMethod = "getVecShiftL64OpValue";
435 let DecoderMethod = "DecodeVecShiftL64Imm";
436 let ParserMatchClass = Imm0_63Operand;
440 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
441 // instructions for splatting repeating bit patterns across the immediate.
442 def logical_imm32_XFORM : SDNodeXForm<imm, [{
443 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
444 return CurDAG->getTargetConstant(enc, MVT::i32);
446 def logical_imm64_XFORM : SDNodeXForm<imm, [{
447 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
448 return CurDAG->getTargetConstant(enc, MVT::i32);
451 let DiagnosticType = "LogicalSecondSource" in {
452 def LogicalImm32Operand : AsmOperandClass {
453 let Name = "LogicalImm32";
455 def LogicalImm64Operand : AsmOperandClass {
456 let Name = "LogicalImm64";
458 def LogicalImm32NotOperand : AsmOperandClass {
459 let Name = "LogicalImm32Not";
461 def LogicalImm64NotOperand : AsmOperandClass {
462 let Name = "LogicalImm64Not";
465 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
466 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
467 }], logical_imm32_XFORM> {
468 let PrintMethod = "printLogicalImm32";
469 let ParserMatchClass = LogicalImm32Operand;
471 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
472 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
473 }], logical_imm64_XFORM> {
474 let PrintMethod = "printLogicalImm64";
475 let ParserMatchClass = LogicalImm64Operand;
477 def logical_imm32_not : Operand<i32> {
478 let ParserMatchClass = LogicalImm32NotOperand;
480 def logical_imm64_not : Operand<i64> {
481 let ParserMatchClass = LogicalImm64NotOperand;
484 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
485 def Imm0_65535Operand : AsmImmRange<0, 65535>;
486 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
487 return ((uint32_t)Imm) < 65536;
489 let ParserMatchClass = Imm0_65535Operand;
490 let PrintMethod = "printHexImm";
493 // imm0_255 predicate - True if the immediate is in the range [0,255].
494 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
495 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
496 return ((uint32_t)Imm) < 256;
498 let ParserMatchClass = Imm0_255Operand;
499 let PrintMethod = "printHexImm";
502 // imm0_127 predicate - True if the immediate is in the range [0,127]
503 def Imm0_127Operand : AsmImmRange<0, 127>;
504 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
505 return ((uint32_t)Imm) < 128;
507 let ParserMatchClass = Imm0_127Operand;
508 let PrintMethod = "printHexImm";
511 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
512 // for all shift-amounts.
514 // imm0_63 predicate - True if the immediate is in the range [0,63]
515 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
516 return ((uint64_t)Imm) < 64;
518 let ParserMatchClass = Imm0_63Operand;
521 // imm0_31 predicate - True if the immediate is in the range [0,31]
522 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
523 return ((uint64_t)Imm) < 32;
525 let ParserMatchClass = Imm0_31Operand;
528 // imm0_15 predicate - True if the immediate is in the range [0,15]
529 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
530 return ((uint64_t)Imm) < 16;
532 let ParserMatchClass = Imm0_15Operand;
535 // imm0_7 predicate - True if the immediate is in the range [0,7]
536 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
537 return ((uint64_t)Imm) < 8;
539 let ParserMatchClass = Imm0_7Operand;
542 // imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
543 def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
544 return ((uint32_t)Imm) < 16;
547 // An arithmetic shifter operand:
548 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
550 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
551 let PrintMethod = "printShifter";
552 let ParserMatchClass = !cast<AsmOperandClass>(
553 "ArithmeticShifterOperand" # width);
556 def arith_shift32 : arith_shift<i32, 32>;
557 def arith_shift64 : arith_shift<i64, 64>;
559 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
561 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
562 let PrintMethod = "printShiftedRegister";
563 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
566 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
567 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
569 // An arithmetic shifter operand:
570 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
572 class logical_shift<int width> : Operand<i32> {
573 let PrintMethod = "printShifter";
574 let ParserMatchClass = !cast<AsmOperandClass>(
575 "LogicalShifterOperand" # width);
578 def logical_shift32 : logical_shift<32>;
579 def logical_shift64 : logical_shift<64>;
581 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
583 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
584 let PrintMethod = "printShiftedRegister";
585 let MIOperandInfo = (ops regclass, shiftop);
588 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
589 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
591 // A logical vector shifter operand:
592 // {7-6} - shift type: 00 = lsl
593 // {5-0} - imm6: #0, #8, #16, or #24
594 def logical_vec_shift : Operand<i32> {
595 let PrintMethod = "printShifter";
596 let EncoderMethod = "getVecShifterOpValue";
597 let ParserMatchClass = LogicalVecShifterOperand;
600 // A logical vector half-word shifter operand:
601 // {7-6} - shift type: 00 = lsl
602 // {5-0} - imm6: #0 or #8
603 def logical_vec_hw_shift : Operand<i32> {
604 let PrintMethod = "printShifter";
605 let EncoderMethod = "getVecShifterOpValue";
606 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
609 // A vector move shifter operand:
610 // {0} - imm1: #8 or #16
611 def move_vec_shift : Operand<i32> {
612 let PrintMethod = "printShifter";
613 let EncoderMethod = "getMoveVecShifterOpValue";
614 let ParserMatchClass = MoveVecShifterOperand;
617 def AddSubImmOperand : AsmOperandClass {
618 let Name = "AddSubImm";
619 let ParserMethod = "tryParseAddSubImm";
620 let DiagnosticType = "AddSubSecondSource";
622 // An ADD/SUB immediate shifter operand:
624 // {7-6} - shift type: 00 = lsl
625 // {5-0} - imm6: #0 or #12
626 class addsub_shifted_imm<ValueType Ty>
627 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
628 let PrintMethod = "printAddSubImm";
629 let EncoderMethod = "getAddSubImmOpValue";
630 let ParserMatchClass = AddSubImmOperand;
631 let MIOperandInfo = (ops i32imm, i32imm);
634 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
635 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
637 class neg_addsub_shifted_imm<ValueType Ty>
638 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
639 let PrintMethod = "printAddSubImm";
640 let EncoderMethod = "getAddSubImmOpValue";
641 let ParserMatchClass = AddSubImmOperand;
642 let MIOperandInfo = (ops i32imm, i32imm);
645 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
646 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
648 // An extend operand:
649 // {5-3} - extend type
651 def arith_extend : Operand<i32> {
652 let PrintMethod = "printArithExtend";
653 let ParserMatchClass = ExtendOperand;
655 def arith_extend64 : Operand<i32> {
656 let PrintMethod = "printArithExtend";
657 let ParserMatchClass = ExtendOperand64;
660 // 'extend' that's a lsl of a 64-bit register.
661 def arith_extendlsl64 : Operand<i32> {
662 let PrintMethod = "printArithExtend";
663 let ParserMatchClass = ExtendOperandLSL64;
666 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
667 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
668 let PrintMethod = "printExtendedRegister";
669 let MIOperandInfo = (ops GPR32, arith_extend);
672 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
673 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
674 let PrintMethod = "printExtendedRegister";
675 let MIOperandInfo = (ops GPR32, arith_extend64);
678 // Floating-point immediate.
679 def fpimm32 : Operand<f32>,
680 PatLeaf<(f32 fpimm), [{
681 return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1;
682 }], SDNodeXForm<fpimm, [{
683 APFloat InVal = N->getValueAPF();
684 uint32_t enc = AArch64_AM::getFP32Imm(InVal);
685 return CurDAG->getTargetConstant(enc, MVT::i32);
687 let ParserMatchClass = FPImmOperand;
688 let PrintMethod = "printFPImmOperand";
690 def fpimm64 : Operand<f64>,
691 PatLeaf<(f64 fpimm), [{
692 return AArch64_AM::getFP64Imm(N->getValueAPF()) != -1;
693 }], SDNodeXForm<fpimm, [{
694 APFloat InVal = N->getValueAPF();
695 uint32_t enc = AArch64_AM::getFP64Imm(InVal);
696 return CurDAG->getTargetConstant(enc, MVT::i32);
698 let ParserMatchClass = FPImmOperand;
699 let PrintMethod = "printFPImmOperand";
702 def fpimm8 : Operand<i32> {
703 let ParserMatchClass = FPImmOperand;
704 let PrintMethod = "printFPImmOperand";
707 def fpimm0 : PatLeaf<(fpimm), [{
708 return N->isExactlyValue(+0.0);
711 // Vector lane operands
712 class AsmVectorIndex<string Suffix> : AsmOperandClass {
713 let Name = "VectorIndex" # Suffix;
714 let DiagnosticType = "InvalidIndex" # Suffix;
716 def VectorIndex1Operand : AsmVectorIndex<"1">;
717 def VectorIndexBOperand : AsmVectorIndex<"B">;
718 def VectorIndexHOperand : AsmVectorIndex<"H">;
719 def VectorIndexSOperand : AsmVectorIndex<"S">;
720 def VectorIndexDOperand : AsmVectorIndex<"D">;
722 def VectorIndex1 : Operand<i64>, ImmLeaf<i64, [{
723 return ((uint64_t)Imm) == 1;
725 let ParserMatchClass = VectorIndex1Operand;
726 let PrintMethod = "printVectorIndex";
727 let MIOperandInfo = (ops i64imm);
729 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
730 return ((uint64_t)Imm) < 16;
732 let ParserMatchClass = VectorIndexBOperand;
733 let PrintMethod = "printVectorIndex";
734 let MIOperandInfo = (ops i64imm);
736 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
737 return ((uint64_t)Imm) < 8;
739 let ParserMatchClass = VectorIndexHOperand;
740 let PrintMethod = "printVectorIndex";
741 let MIOperandInfo = (ops i64imm);
743 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
744 return ((uint64_t)Imm) < 4;
746 let ParserMatchClass = VectorIndexSOperand;
747 let PrintMethod = "printVectorIndex";
748 let MIOperandInfo = (ops i64imm);
750 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
751 return ((uint64_t)Imm) < 2;
753 let ParserMatchClass = VectorIndexDOperand;
754 let PrintMethod = "printVectorIndex";
755 let MIOperandInfo = (ops i64imm);
758 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
759 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
760 // are encoded as the eight bit value 'abcdefgh'.
761 def simdimmtype10 : Operand<i32>,
762 PatLeaf<(f64 fpimm), [{
763 return AArch64_AM::isAdvSIMDModImmType10(N->getValueAPF()
766 }], SDNodeXForm<fpimm, [{
767 APFloat InVal = N->getValueAPF();
768 uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
771 return CurDAG->getTargetConstant(enc, MVT::i32);
773 let ParserMatchClass = SIMDImmType10Operand;
774 let PrintMethod = "printSIMDType10Operand";
782 // Base encoding for system instruction operands.
783 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
784 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
785 list<dag> pattern = []>
786 : I<oops, iops, asm, operands, "", pattern> {
787 let Inst{31-22} = 0b1101010100;
791 // System instructions which do not have an Rt register.
792 class SimpleSystemI<bit L, dag iops, string asm, string operands,
793 list<dag> pattern = []>
794 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
795 let Inst{4-0} = 0b11111;
798 // System instructions which have an Rt register.
799 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
800 : BaseSystemI<L, oops, iops, asm, operands>,
806 // Hint instructions that take both a CRm and a 3-bit immediate.
807 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
808 // model patterns with sufficiently fine granularity
809 let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
810 class HintI<string mnemonic>
811 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "",
812 [(int_aarch64_hint imm0_127:$imm)]>,
815 let Inst{20-12} = 0b000110010;
816 let Inst{11-5} = imm;
819 // System instructions taking a single literal operand which encodes into
820 // CRm. op2 differentiates the opcodes.
821 def BarrierAsmOperand : AsmOperandClass {
822 let Name = "Barrier";
823 let ParserMethod = "tryParseBarrierOperand";
825 def barrier_op : Operand<i32> {
826 let PrintMethod = "printBarrierOption";
827 let ParserMatchClass = BarrierAsmOperand;
829 class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
830 list<dag> pattern = []>
831 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
832 Sched<[WriteBarrier]> {
834 let Inst{20-12} = 0b000110011;
835 let Inst{11-8} = CRm;
839 // MRS/MSR system instructions. These have different operand classes because
840 // a different subset of registers can be accessed through each instruction.
841 def MRSSystemRegisterOperand : AsmOperandClass {
842 let Name = "MRSSystemRegister";
843 let ParserMethod = "tryParseSysReg";
844 let DiagnosticType = "MRS";
846 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
847 def mrs_sysreg_op : Operand<i32> {
848 let ParserMatchClass = MRSSystemRegisterOperand;
849 let DecoderMethod = "DecodeMRSSystemRegister";
850 let PrintMethod = "printMRSSystemRegister";
853 def MSRSystemRegisterOperand : AsmOperandClass {
854 let Name = "MSRSystemRegister";
855 let ParserMethod = "tryParseSysReg";
856 let DiagnosticType = "MSR";
858 def msr_sysreg_op : Operand<i32> {
859 let ParserMatchClass = MSRSystemRegisterOperand;
860 let DecoderMethod = "DecodeMSRSystemRegister";
861 let PrintMethod = "printMSRSystemRegister";
864 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
865 "mrs", "\t$Rt, $systemreg"> {
867 let Inst{20-5} = systemreg;
870 // FIXME: Some of these def NZCV, others don't. Best way to model that?
871 // Explicitly modeling each of the system register as a register class
872 // would do it, but feels like overkill at this point.
873 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
874 "msr", "\t$systemreg, $Rt"> {
876 let Inst{20-5} = systemreg;
879 def SystemPStateFieldOperand : AsmOperandClass {
880 let Name = "SystemPStateField";
881 let ParserMethod = "tryParseSysReg";
883 def pstatefield_op : Operand<i32> {
884 let ParserMatchClass = SystemPStateFieldOperand;
885 let PrintMethod = "printSystemPStateField";
890 : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
891 "msr", "\t$pstate_field, $imm">,
895 let Inst{20-19} = 0b00;
896 let Inst{18-16} = pstatefield{5-3};
897 let Inst{15-12} = 0b0100;
898 let Inst{11-8} = imm;
899 let Inst{7-5} = pstatefield{2-0};
901 let DecoderMethod = "DecodeSystemPStateInstruction";
904 // SYS and SYSL generic system instructions.
905 def SysCRAsmOperand : AsmOperandClass {
907 let ParserMethod = "tryParseSysCROperand";
910 def sys_cr_op : Operand<i32> {
911 let PrintMethod = "printSysCROperand";
912 let ParserMatchClass = SysCRAsmOperand;
915 class SystemXtI<bit L, string asm>
916 : RtSystemI<L, (outs),
917 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
918 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
923 let Inst{20-19} = 0b01;
924 let Inst{18-16} = op1;
925 let Inst{15-12} = Cn;
930 class SystemLXtI<bit L, string asm>
931 : RtSystemI<L, (outs),
932 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
933 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
938 let Inst{20-19} = 0b01;
939 let Inst{18-16} = op1;
940 let Inst{15-12} = Cn;
946 // Branch (register) instructions:
954 // otherwise UNDEFINED
955 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
956 string operands, list<dag> pattern>
957 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
958 let Inst{31-25} = 0b1101011;
959 let Inst{24-21} = opc;
960 let Inst{20-16} = 0b11111;
961 let Inst{15-10} = 0b000000;
962 let Inst{4-0} = 0b00000;
965 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
966 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
971 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
972 class SpecialReturn<bits<4> opc, string asm>
973 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
974 let Inst{9-5} = 0b11111;
978 // Conditional branch instruction.
982 // 4-bit immediate. Pretty-printed as <cc>
983 def ccode : Operand<i32> {
984 let PrintMethod = "printCondCode";
985 let ParserMatchClass = CondCode;
987 def inv_ccode : Operand<i32> {
988 // AL and NV are invalid in the aliases which use inv_ccode
989 let PrintMethod = "printInverseCondCode";
990 let ParserMatchClass = CondCode;
991 let MCOperandPredicate = [{
992 return MCOp.isImm() &&
993 MCOp.getImm() != AArch64CC::AL &&
994 MCOp.getImm() != AArch64CC::NV;
998 // Conditional branch target. 19-bit immediate. The low two bits of the target
999 // offset are implied zero and so are not part of the immediate.
1000 def PCRelLabel19Operand : AsmOperandClass {
1001 let Name = "PCRelLabel19";
1002 let DiagnosticType = "InvalidLabel";
1004 def am_brcond : Operand<OtherVT> {
1005 let EncoderMethod = "getCondBranchTargetOpValue";
1006 let DecoderMethod = "DecodePCRelLabel19";
1007 let PrintMethod = "printAlignedLabel";
1008 let ParserMatchClass = PCRelLabel19Operand;
1011 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
1012 "b", ".$cond\t$target", "",
1013 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
1016 let isTerminator = 1;
1021 let Inst{31-24} = 0b01010100;
1022 let Inst{23-5} = target;
1024 let Inst{3-0} = cond;
1028 // Compare-and-branch instructions.
1030 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
1031 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
1032 asm, "\t$Rt, $target", "",
1033 [(node regtype:$Rt, bb:$target)]>,
1036 let isTerminator = 1;
1040 let Inst{30-25} = 0b011010;
1042 let Inst{23-5} = target;
1046 multiclass CmpBranch<bit op, string asm, SDNode node> {
1047 def W : BaseCmpBranch<GPR32, op, asm, node> {
1050 def X : BaseCmpBranch<GPR64, op, asm, node> {
1056 // Test-bit-and-branch instructions.
1058 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
1059 // the target offset are implied zero and so are not part of the immediate.
1060 def BranchTarget14Operand : AsmOperandClass {
1061 let Name = "BranchTarget14";
1063 def am_tbrcond : Operand<OtherVT> {
1064 let EncoderMethod = "getTestBranchTargetOpValue";
1065 let PrintMethod = "printAlignedLabel";
1066 let ParserMatchClass = BranchTarget14Operand;
1069 // AsmOperand classes to emit (or not) special diagnostics
1070 def TBZImm0_31Operand : AsmOperandClass {
1071 let Name = "TBZImm0_31";
1072 let PredicateMethod = "isImm0_31";
1073 let RenderMethod = "addImm0_31Operands";
1075 def TBZImm32_63Operand : AsmOperandClass {
1076 let Name = "Imm32_63";
1077 let DiagnosticType = "InvalidImm0_63";
1080 class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
1081 return (((uint32_t)Imm) < 32);
1083 let ParserMatchClass = matcher;
1086 def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
1087 def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;
1089 def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
1090 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1092 let ParserMatchClass = TBZImm32_63Operand;
1095 class BaseTestBranch<RegisterClass regtype, Operand immtype,
1096 bit op, string asm, SDNode node>
1097 : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
1098 asm, "\t$Rt, $bit_off, $target", "",
1099 [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
1102 let isTerminator = 1;
1108 let Inst{30-25} = 0b011011;
1110 let Inst{23-19} = bit_off{4-0};
1111 let Inst{18-5} = target;
1114 let DecoderMethod = "DecodeTestAndBranch";
1117 multiclass TestBranch<bit op, string asm, SDNode node> {
1118 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1122 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1126 // Alias X-reg with 0-31 imm to W-Reg.
1127 def : InstAlias<asm # "\t$Rd, $imm, $target",
1128 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1129 tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
1130 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1131 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1132 tbz_imm0_31_diag:$imm, bb:$target)>;
1136 // Unconditional branch (immediate) instructions.
1138 def BranchTarget26Operand : AsmOperandClass {
1139 let Name = "BranchTarget26";
1140 let DiagnosticType = "InvalidLabel";
1142 def am_b_target : Operand<OtherVT> {
1143 let EncoderMethod = "getBranchTargetOpValue";
1144 let PrintMethod = "printAlignedLabel";
1145 let ParserMatchClass = BranchTarget26Operand;
1147 def am_bl_target : Operand<i64> {
1148 let EncoderMethod = "getBranchTargetOpValue";
1149 let PrintMethod = "printAlignedLabel";
1150 let ParserMatchClass = BranchTarget26Operand;
1153 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1154 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1157 let Inst{30-26} = 0b00101;
1158 let Inst{25-0} = addr;
1160 let DecoderMethod = "DecodeUnconditionalBranch";
1163 class BranchImm<bit op, string asm, list<dag> pattern>
1164 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1165 class CallImm<bit op, string asm, list<dag> pattern>
1166 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1169 // Basic one-operand data processing instructions.
1172 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1173 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1174 SDPatternOperator node>
1175 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1176 [(set regtype:$Rd, (node regtype:$Rn))]>,
1177 Sched<[WriteI, ReadI]> {
1181 let Inst{30-13} = 0b101101011000000000;
1182 let Inst{12-10} = opc;
1187 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1188 multiclass OneOperandData<bits<3> opc, string asm,
1189 SDPatternOperator node = null_frag> {
1190 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1194 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1199 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1200 : BaseOneOperandData<opc, GPR32, asm, node> {
1204 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1205 : BaseOneOperandData<opc, GPR64, asm, node> {
1210 // Basic two-operand data processing instructions.
1212 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1214 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1215 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1216 Sched<[WriteI, ReadI, ReadI]> {
1221 let Inst{30} = isSub;
1222 let Inst{28-21} = 0b11010000;
1223 let Inst{20-16} = Rm;
1224 let Inst{15-10} = 0;
1229 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1231 : BaseBaseAddSubCarry<isSub, regtype, asm,
1232 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1234 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1236 : BaseBaseAddSubCarry<isSub, regtype, asm,
1237 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1242 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1243 SDNode OpNode, SDNode OpNode_setflags> {
1244 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1248 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1254 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1259 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1266 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1267 SDPatternOperator OpNode>
1268 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1269 asm, "\t$Rd, $Rn, $Rm", "",
1270 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1274 let Inst{30-21} = 0b0011010110;
1275 let Inst{20-16} = Rm;
1276 let Inst{15-14} = 0b00;
1277 let Inst{13-10} = opc;
1282 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1283 SDPatternOperator OpNode>
1284 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1285 let Inst{10} = isSigned;
1288 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1289 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1290 Sched<[WriteID32, ReadID, ReadID]> {
1293 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1294 Sched<[WriteID64, ReadID, ReadID]> {
1299 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1300 SDPatternOperator OpNode = null_frag>
1301 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1302 Sched<[WriteIS, ReadI]> {
1303 let Inst{11-10} = shift_type;
1306 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1307 def Wr : BaseShift<shift_type, GPR32, asm> {
1311 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1315 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1316 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1317 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1319 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1320 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1322 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1323 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1325 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1326 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1329 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1330 : InstAlias<asm#" $dst, $src1, $src2",
1331 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
1333 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1334 RegisterClass addtype, string asm,
1336 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1337 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1342 let Inst{30-24} = 0b0011011;
1343 let Inst{23-21} = opc;
1344 let Inst{20-16} = Rm;
1345 let Inst{15} = isSub;
1346 let Inst{14-10} = Ra;
1351 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1352 // MADD/MSUB generation is decided by MachineCombiner.cpp
1353 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1354 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1355 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1359 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1360 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1361 Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
1366 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1367 SDNode AccNode, SDNode ExtNode>
1368 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1369 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1370 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1371 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1375 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1376 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1377 asm, "\t$Rd, $Rn, $Rm", "",
1378 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1379 Sched<[WriteIM64, ReadIM, ReadIM]> {
1383 let Inst{31-24} = 0b10011011;
1384 let Inst{23-21} = opc;
1385 let Inst{20-16} = Rm;
1390 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1391 // (i.e. all bits 1) but is ignored by the processor.
1392 let PostEncoderMethod = "fixMulHigh";
1395 class MulAccumWAlias<string asm, Instruction inst>
1396 : InstAlias<asm#" $dst, $src1, $src2",
1397 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1398 class MulAccumXAlias<string asm, Instruction inst>
1399 : InstAlias<asm#" $dst, $src1, $src2",
1400 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1401 class WideMulAccumAlias<string asm, Instruction inst>
1402 : InstAlias<asm#" $dst, $src1, $src2",
1403 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1405 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1406 SDPatternOperator OpNode, string asm>
1407 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1408 asm, "\t$Rd, $Rn, $Rm", "",
1409 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1410 Sched<[WriteISReg, ReadI, ReadISReg]> {
1416 let Inst{30-21} = 0b0011010110;
1417 let Inst{20-16} = Rm;
1418 let Inst{15-13} = 0b010;
1420 let Inst{11-10} = sz;
1423 let Predicates = [HasCRC];
1427 // Address generation.
1430 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1431 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1436 let Inst{31} = page;
1437 let Inst{30-29} = label{1-0};
1438 let Inst{28-24} = 0b10000;
1439 let Inst{23-5} = label{20-2};
1442 let DecoderMethod = "DecodeAdrInstruction";
1449 def movimm32_imm : Operand<i32> {
1450 let ParserMatchClass = Imm0_65535Operand;
1451 let EncoderMethod = "getMoveWideImmOpValue";
1452 let PrintMethod = "printHexImm";
1454 def movimm32_shift : Operand<i32> {
1455 let PrintMethod = "printShifter";
1456 let ParserMatchClass = MovImm32ShifterOperand;
1458 def movimm64_shift : Operand<i32> {
1459 let PrintMethod = "printShifter";
1460 let ParserMatchClass = MovImm64ShifterOperand;
1463 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1464 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1466 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1467 asm, "\t$Rd, $imm$shift", "", []>,
1472 let Inst{30-29} = opc;
1473 let Inst{28-23} = 0b100101;
1474 let Inst{22-21} = shift{5-4};
1475 let Inst{20-5} = imm;
1478 let DecoderMethod = "DecodeMoveImmInstruction";
1481 multiclass MoveImmediate<bits<2> opc, string asm> {
1482 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1486 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1491 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1492 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1494 : I<(outs regtype:$Rd),
1495 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1496 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1497 Sched<[WriteI, ReadI]> {
1501 let Inst{30-29} = opc;
1502 let Inst{28-23} = 0b100101;
1503 let Inst{22-21} = shift{5-4};
1504 let Inst{20-5} = imm;
1507 let DecoderMethod = "DecodeMoveImmInstruction";
1510 multiclass InsertImmediate<bits<2> opc, string asm> {
1511 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1515 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1524 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1525 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1526 string asm, SDPatternOperator OpNode>
1527 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1528 asm, "\t$Rd, $Rn, $imm", "",
1529 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1530 Sched<[WriteI, ReadI]> {
1534 let Inst{30} = isSub;
1535 let Inst{29} = setFlags;
1536 let Inst{28-24} = 0b10001;
1537 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1538 let Inst{21-10} = imm{11-0};
1541 let DecoderMethod = "DecodeBaseAddSubImm";
1544 class BaseAddSubRegPseudo<RegisterClass regtype,
1545 SDPatternOperator OpNode>
1546 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1547 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1548 Sched<[WriteI, ReadI, ReadI]>;
1550 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1551 arith_shifted_reg shifted_regtype, string asm,
1552 SDPatternOperator OpNode>
1553 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1554 asm, "\t$Rd, $Rn, $Rm", "",
1555 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1556 Sched<[WriteISReg, ReadI, ReadISReg]> {
1557 // The operands are in order to match the 'addr' MI operands, so we
1558 // don't need an encoder method and by-name matching. Just use the default
1559 // in-order handling. Since we're using by-order, make sure the names
1565 let Inst{30} = isSub;
1566 let Inst{29} = setFlags;
1567 let Inst{28-24} = 0b01011;
1568 let Inst{23-22} = shift{7-6};
1570 let Inst{20-16} = src2;
1571 let Inst{15-10} = shift{5-0};
1572 let Inst{9-5} = src1;
1573 let Inst{4-0} = dst;
1575 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1578 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1579 RegisterClass src1Regtype, Operand src2Regtype,
1580 string asm, SDPatternOperator OpNode>
1581 : I<(outs dstRegtype:$R1),
1582 (ins src1Regtype:$R2, src2Regtype:$R3),
1583 asm, "\t$R1, $R2, $R3", "",
1584 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1585 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1590 let Inst{30} = isSub;
1591 let Inst{29} = setFlags;
1592 let Inst{28-24} = 0b01011;
1593 let Inst{23-21} = 0b001;
1594 let Inst{20-16} = Rm;
1595 let Inst{15-13} = ext{5-3};
1596 let Inst{12-10} = ext{2-0};
1600 let DecoderMethod = "DecodeAddSubERegInstruction";
1603 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1604 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1605 RegisterClass src1Regtype, RegisterClass src2Regtype,
1606 Operand ext_op, string asm>
1607 : I<(outs dstRegtype:$Rd),
1608 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1609 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1610 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1615 let Inst{30} = isSub;
1616 let Inst{29} = setFlags;
1617 let Inst{28-24} = 0b01011;
1618 let Inst{23-21} = 0b001;
1619 let Inst{20-16} = Rm;
1620 let Inst{15} = ext{5};
1621 let Inst{12-10} = ext{2-0};
1625 let DecoderMethod = "DecodeAddSubERegInstruction";
1628 // Aliases for register+register add/subtract.
1629 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1630 RegisterClass src1Regtype, RegisterClass src2Regtype,
1632 : InstAlias<asm#" $dst, $src1, $src2",
1633 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1636 multiclass AddSub<bit isSub, string mnemonic,
1637 SDPatternOperator OpNode = null_frag> {
1638 let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1639 // Add/Subtract immediate
1640 // Increase the weight of the immediate variant to try to match it before
1641 // the extended register variant.
1642 // We used to match the register variant before the immediate when the
1643 // register argument could be implicitly zero-extended.
1644 let AddedComplexity = 6 in
1645 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1649 let AddedComplexity = 6 in
1650 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1655 // Add/Subtract register - Only used for CodeGen
1656 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1657 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1659 // Add/Subtract shifted register
1660 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1664 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1670 // Add/Subtract extended register
1671 let AddedComplexity = 1, hasSideEffects = 0 in {
1672 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1673 arith_extended_reg32<i32>, mnemonic, OpNode> {
1676 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1677 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1682 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1683 arith_extendlsl64, mnemonic> {
1684 // UXTX and SXTX only.
1685 let Inst{14-13} = 0b11;
1689 // Register/register aliases with no shift when SP is not used.
1690 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1691 GPR32, GPR32, GPR32, 0>;
1692 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1693 GPR64, GPR64, GPR64, 0>;
1695 // Register/register aliases with no shift when either the destination or
1696 // first source register is SP.
1697 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1698 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1699 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1700 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1701 def : AddSubRegAlias<mnemonic,
1702 !cast<Instruction>(NAME#"Xrx64"),
1703 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1704 def : AddSubRegAlias<mnemonic,
1705 !cast<Instruction>(NAME#"Xrx64"),
1706 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1709 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
1710 let isCompare = 1, Defs = [NZCV] in {
1711 // Add/Subtract immediate
1712 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1716 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1721 // Add/Subtract register
1722 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1723 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1725 // Add/Subtract shifted register
1726 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1730 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1735 // Add/Subtract extended register
1736 let AddedComplexity = 1 in {
1737 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1738 arith_extended_reg32<i32>, mnemonic, OpNode> {
1741 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1742 arith_extended_reg32<i64>, mnemonic, OpNode> {
1747 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1748 arith_extendlsl64, mnemonic> {
1749 // UXTX and SXTX only.
1750 let Inst{14-13} = 0b11;
1756 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Wri")
1757 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
1758 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Xri")
1759 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
1760 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
1761 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1762 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
1763 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1764 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
1765 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1766 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
1767 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1768 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
1769 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1771 // Compare shorthands
1772 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1773 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1774 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1775 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1776 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrx")
1777 WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
1778 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
1779 XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
1781 // Register/register aliases with no shift when SP is not used.
1782 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1783 GPR32, GPR32, GPR32, 0>;
1784 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1785 GPR64, GPR64, GPR64, 0>;
1787 // Register/register aliases with no shift when the first source register
1789 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1790 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1791 def : AddSubRegAlias<mnemonic,
1792 !cast<Instruction>(NAME#"Xrx64"),
1793 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1799 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1801 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
1803 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1805 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1806 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1807 Sched<[WriteExtr, ReadExtrHi]> {
1813 let Inst{30-23} = 0b00100111;
1815 let Inst{20-16} = Rm;
1816 let Inst{15-10} = imm;
1821 multiclass ExtractImm<string asm> {
1822 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1824 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1827 // imm<5> must be zero.
1830 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1832 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1843 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1844 class BaseBitfieldImm<bits<2> opc,
1845 RegisterClass regtype, Operand imm_type, string asm>
1846 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1847 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1848 Sched<[WriteIS, ReadI]> {
1854 let Inst{30-29} = opc;
1855 let Inst{28-23} = 0b100110;
1856 let Inst{21-16} = immr;
1857 let Inst{15-10} = imms;
1862 multiclass BitfieldImm<bits<2> opc, string asm> {
1863 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1866 // imms<5> and immr<5> must be zero, else ReservedValue().
1870 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1876 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1877 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1878 RegisterClass regtype, Operand imm_type, string asm>
1879 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1881 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1882 Sched<[WriteIS, ReadI]> {
1888 let Inst{30-29} = opc;
1889 let Inst{28-23} = 0b100110;
1890 let Inst{21-16} = immr;
1891 let Inst{15-10} = imms;
1896 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1897 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1900 // imms<5> and immr<5> must be zero, else ReservedValue().
1904 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1914 // Logical (immediate)
1915 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1916 RegisterClass sregtype, Operand imm_type, string asm,
1918 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1919 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1920 Sched<[WriteI, ReadI]> {
1924 let Inst{30-29} = opc;
1925 let Inst{28-23} = 0b100100;
1926 let Inst{22} = imm{12};
1927 let Inst{21-16} = imm{11-6};
1928 let Inst{15-10} = imm{5-0};
1932 let DecoderMethod = "DecodeLogicalImmInstruction";
1935 // Logical (shifted register)
1936 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1937 logical_shifted_reg shifted_regtype, string asm,
1939 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1940 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1941 Sched<[WriteISReg, ReadI, ReadISReg]> {
1942 // The operands are in order to match the 'addr' MI operands, so we
1943 // don't need an encoder method and by-name matching. Just use the default
1944 // in-order handling. Since we're using by-order, make sure the names
1950 let Inst{30-29} = opc;
1951 let Inst{28-24} = 0b01010;
1952 let Inst{23-22} = shift{7-6};
1954 let Inst{20-16} = src2;
1955 let Inst{15-10} = shift{5-0};
1956 let Inst{9-5} = src1;
1957 let Inst{4-0} = dst;
1959 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1962 // Aliases for register+register logical instructions.
1963 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
1964 : InstAlias<asm#" $dst, $src1, $src2",
1965 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
1967 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
1969 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1970 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
1971 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1972 logical_imm32:$imm))]> {
1974 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1976 let AddedComplexity = 6, isReMaterializable = 1, isAsCheapAsAMove = 1 in
1977 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
1978 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1979 logical_imm64:$imm))]> {
1983 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1984 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
1985 logical_imm32_not:$imm), 0>;
1986 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1987 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
1988 logical_imm64_not:$imm), 0>;
1991 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode,
1993 let isCompare = 1, Defs = [NZCV] in {
1994 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
1995 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
1997 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1999 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
2000 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2003 } // end Defs = [NZCV]
2005 def : InstAlias<Alias # " $Rd, $Rn, $imm",
2006 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2007 logical_imm32_not:$imm), 0>;
2008 def : InstAlias<Alias # " $Rd, $Rn, $imm",
2009 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2010 logical_imm64_not:$imm), 0>;
2013 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
2014 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2015 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2016 Sched<[WriteI, ReadI, ReadI]>;
2018 // Split from LogicalImm as not all instructions have both.
2019 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
2020 SDPatternOperator OpNode> {
2021 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
2022 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2023 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2026 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2027 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2028 logical_shifted_reg32:$Rm))]> {
2031 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2032 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2033 logical_shifted_reg64:$Rm))]> {
2037 def : LogicalRegAlias<mnemonic,
2038 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2039 def : LogicalRegAlias<mnemonic,
2040 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2043 // Split from LogicalReg to allow setting NZCV Defs
2044 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
2045 SDPatternOperator OpNode = null_frag> {
2046 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
2047 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2048 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2050 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2051 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2054 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2055 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2060 def : LogicalRegAlias<mnemonic,
2061 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2062 def : LogicalRegAlias<mnemonic,
2063 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2067 // Conditionally set flags
2070 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2071 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
2072 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
2073 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
2074 Sched<[WriteI, ReadI]> {
2084 let Inst{29-21} = 0b111010010;
2085 let Inst{20-16} = imm;
2086 let Inst{15-12} = cond;
2087 let Inst{11-10} = 0b10;
2090 let Inst{3-0} = nzcv;
2093 multiclass CondSetFlagsImm<bit op, string asm> {
2094 def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
2097 def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
2102 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2103 class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
2104 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
2105 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
2106 Sched<[WriteI, ReadI, ReadI]> {
2116 let Inst{29-21} = 0b111010010;
2117 let Inst{20-16} = Rm;
2118 let Inst{15-12} = cond;
2119 let Inst{11-10} = 0b00;
2122 let Inst{3-0} = nzcv;
2125 multiclass CondSetFlagsReg<bit op, string asm> {
2126 def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
2129 def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
2135 // Conditional select
2138 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
2139 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2140 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2142 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2143 Sched<[WriteI, ReadI, ReadI]> {
2152 let Inst{29-21} = 0b011010100;
2153 let Inst{20-16} = Rm;
2154 let Inst{15-12} = cond;
2155 let Inst{11-10} = op2;
2160 multiclass CondSelect<bit op, bits<2> op2, string asm> {
2161 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2164 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2169 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2171 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2172 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2174 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2175 (i32 imm:$cond), NZCV))]>,
2176 Sched<[WriteI, ReadI, ReadI]> {
2185 let Inst{29-21} = 0b011010100;
2186 let Inst{20-16} = Rm;
2187 let Inst{15-12} = cond;
2188 let Inst{11-10} = op2;
2193 def inv_cond_XFORM : SDNodeXForm<imm, [{
2194 AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
2195 return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), MVT::i32);
2198 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2199 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2202 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2206 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2207 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2208 (inv_cond_XFORM imm:$cond))>;
2210 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2211 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2212 (inv_cond_XFORM imm:$cond))>;
2216 // Special Mask Value
2218 def maski8_or_more : Operand<i32>,
2219 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2221 def maski16_or_more : Operand<i32>,
2222 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2230 // (unsigned immediate)
2231 // Indexed for 8-bit registers. offset is in range [0,4095].
2232 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2233 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
2234 def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
2235 def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
2236 def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
2238 class UImm12OffsetOperand<int Scale> : AsmOperandClass {
2239 let Name = "UImm12Offset" # Scale;
2240 let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
2241 let PredicateMethod = "isUImm12Offset<" # Scale # ">";
2242 let DiagnosticType = "InvalidMemoryIndexed" # Scale;
2245 def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>;
2246 def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>;
2247 def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>;
2248 def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>;
2249 def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>;
2251 class uimm12_scaled<int Scale> : Operand<i64> {
2252 let ParserMatchClass
2253 = !cast<AsmOperandClass>("UImm12OffsetScale" # Scale # "Operand");
2255 = "getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale" # Scale # ">";
2256 let PrintMethod = "printUImm12Offset<" # Scale # ">";
2259 def uimm12s1 : uimm12_scaled<1>;
2260 def uimm12s2 : uimm12_scaled<2>;
2261 def uimm12s4 : uimm12_scaled<4>;
2262 def uimm12s8 : uimm12_scaled<8>;
2263 def uimm12s16 : uimm12_scaled<16>;
2265 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2266 string asm, list<dag> pattern>
2267 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2273 let Inst{31-30} = sz;
2274 let Inst{29-27} = 0b111;
2276 let Inst{25-24} = 0b01;
2277 let Inst{23-22} = opc;
2278 let Inst{21-10} = offset;
2282 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2285 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2286 Operand indextype, string asm, list<dag> pattern> {
2287 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2288 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2289 (ins GPR64sp:$Rn, indextype:$offset),
2293 def : InstAlias<asm # " $Rt, [$Rn]",
2294 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2297 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2298 Operand indextype, string asm, list<dag> pattern> {
2299 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2300 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2301 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2305 def : InstAlias<asm # " $Rt, [$Rn]",
2306 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2309 def PrefetchOperand : AsmOperandClass {
2310 let Name = "Prefetch";
2311 let ParserMethod = "tryParsePrefetch";
2313 def prfop : Operand<i32> {
2314 let PrintMethod = "printPrefetchOp";
2315 let ParserMatchClass = PrefetchOperand;
2318 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2319 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2320 : BaseLoadStoreUI<sz, V, opc,
2321 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2329 // Load literal address: 19-bit immediate. The low two bits of the target
2330 // offset are implied zero and so are not part of the immediate.
2331 def am_ldrlit : Operand<OtherVT> {
2332 let EncoderMethod = "getLoadLiteralOpValue";
2333 let DecoderMethod = "DecodePCRelLabel19";
2334 let PrintMethod = "printAlignedLabel";
2335 let ParserMatchClass = PCRelLabel19Operand;
2338 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2339 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2340 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2341 asm, "\t$Rt, $label", "", []>,
2345 let Inst{31-30} = opc;
2346 let Inst{29-27} = 0b011;
2348 let Inst{25-24} = 0b00;
2349 let Inst{23-5} = label;
2353 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2354 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2355 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2356 asm, "\t$Rt, $label", "", pat>,
2360 let Inst{31-30} = opc;
2361 let Inst{29-27} = 0b011;
2363 let Inst{25-24} = 0b00;
2364 let Inst{23-5} = label;
2369 // Load/store register offset
2372 def ro_Xindexed8 : ComplexPattern<i64, 4, "SelectAddrModeXRO<8>", []>;
2373 def ro_Xindexed16 : ComplexPattern<i64, 4, "SelectAddrModeXRO<16>", []>;
2374 def ro_Xindexed32 : ComplexPattern<i64, 4, "SelectAddrModeXRO<32>", []>;
2375 def ro_Xindexed64 : ComplexPattern<i64, 4, "SelectAddrModeXRO<64>", []>;
2376 def ro_Xindexed128 : ComplexPattern<i64, 4, "SelectAddrModeXRO<128>", []>;
2378 def ro_Windexed8 : ComplexPattern<i64, 4, "SelectAddrModeWRO<8>", []>;
2379 def ro_Windexed16 : ComplexPattern<i64, 4, "SelectAddrModeWRO<16>", []>;
2380 def ro_Windexed32 : ComplexPattern<i64, 4, "SelectAddrModeWRO<32>", []>;
2381 def ro_Windexed64 : ComplexPattern<i64, 4, "SelectAddrModeWRO<64>", []>;
2382 def ro_Windexed128 : ComplexPattern<i64, 4, "SelectAddrModeWRO<128>", []>;
2384 class MemExtendOperand<string Reg, int Width> : AsmOperandClass {
2385 let Name = "Mem" # Reg # "Extend" # Width;
2386 let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">";
2387 let RenderMethod = "addMemExtendOperands";
2388 let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width;
2391 def MemWExtend8Operand : MemExtendOperand<"W", 8> {
2392 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2393 // the trivial shift.
2394 let RenderMethod = "addMemExtend8Operands";
2396 def MemWExtend16Operand : MemExtendOperand<"W", 16>;
2397 def MemWExtend32Operand : MemExtendOperand<"W", 32>;
2398 def MemWExtend64Operand : MemExtendOperand<"W", 64>;
2399 def MemWExtend128Operand : MemExtendOperand<"W", 128>;
2401 def MemXExtend8Operand : MemExtendOperand<"X", 8> {
2402 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2403 // the trivial shift.
2404 let RenderMethod = "addMemExtend8Operands";
2406 def MemXExtend16Operand : MemExtendOperand<"X", 16>;
2407 def MemXExtend32Operand : MemExtendOperand<"X", 32>;
2408 def MemXExtend64Operand : MemExtendOperand<"X", 64>;
2409 def MemXExtend128Operand : MemExtendOperand<"X", 128>;
2411 class ro_extend<AsmOperandClass ParserClass, string Reg, int Width>
2413 let ParserMatchClass = ParserClass;
2414 let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">";
2415 let DecoderMethod = "DecodeMemExtend";
2416 let EncoderMethod = "getMemExtendOpValue";
2417 let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift);
2420 def ro_Wextend8 : ro_extend<MemWExtend8Operand, "w", 8>;
2421 def ro_Wextend16 : ro_extend<MemWExtend16Operand, "w", 16>;
2422 def ro_Wextend32 : ro_extend<MemWExtend32Operand, "w", 32>;
2423 def ro_Wextend64 : ro_extend<MemWExtend64Operand, "w", 64>;
2424 def ro_Wextend128 : ro_extend<MemWExtend128Operand, "w", 128>;
2426 def ro_Xextend8 : ro_extend<MemXExtend8Operand, "x", 8>;
2427 def ro_Xextend16 : ro_extend<MemXExtend16Operand, "x", 16>;
2428 def ro_Xextend32 : ro_extend<MemXExtend32Operand, "x", 32>;
2429 def ro_Xextend64 : ro_extend<MemXExtend64Operand, "x", 64>;
2430 def ro_Xextend128 : ro_extend<MemXExtend128Operand, "x", 128>;
2432 class ROAddrMode<ComplexPattern windex, ComplexPattern xindex,
2433 Operand wextend, Operand xextend> {
2434 // CodeGen-level pattern covering the entire addressing mode.
2435 ComplexPattern Wpat = windex;
2436 ComplexPattern Xpat = xindex;
2438 // Asm-level Operand covering the valid "uxtw #3" style syntax.
2439 Operand Wext = wextend;
2440 Operand Xext = xextend;
2443 def ro8 : ROAddrMode<ro_Windexed8, ro_Xindexed8, ro_Wextend8, ro_Xextend8>;
2444 def ro16 : ROAddrMode<ro_Windexed16, ro_Xindexed16, ro_Wextend16, ro_Xextend16>;
2445 def ro32 : ROAddrMode<ro_Windexed32, ro_Xindexed32, ro_Wextend32, ro_Xextend32>;
2446 def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>;
2447 def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
2450 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2451 string asm, dag ins, dag outs, list<dag> pat>
2452 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2457 let Inst{31-30} = sz;
2458 let Inst{29-27} = 0b111;
2460 let Inst{25-24} = 0b00;
2461 let Inst{23-22} = opc;
2463 let Inst{20-16} = Rm;
2464 let Inst{15} = extend{1}; // sign extend Rm?
2466 let Inst{12} = extend{0}; // do shift?
2467 let Inst{11-10} = 0b10;
2472 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2473 : InstAlias<asm # " $Rt, [$Rn, $Rm]",
2474 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2476 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2477 string asm, ValueType Ty, SDPatternOperator loadop> {
2478 let AddedComplexity = 10 in
2479 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2481 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2482 [(set (Ty regtype:$Rt),
2483 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2484 ro_Wextend8:$extend)))]>,
2485 Sched<[WriteLDIdx, ReadAdrBase]> {
2489 let AddedComplexity = 10 in
2490 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2492 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2493 [(set (Ty regtype:$Rt),
2494 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2495 ro_Xextend8:$extend)))]>,
2496 Sched<[WriteLDIdx, ReadAdrBase]> {
2500 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2503 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2504 string asm, ValueType Ty, SDPatternOperator storeop> {
2505 let AddedComplexity = 10 in
2506 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2507 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2508 [(storeop (Ty regtype:$Rt),
2509 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2510 ro_Wextend8:$extend))]>,
2511 Sched<[WriteSTIdx, ReadAdrBase]> {
2515 let AddedComplexity = 10 in
2516 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2517 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2518 [(storeop (Ty regtype:$Rt),
2519 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2520 ro_Xextend8:$extend))]>,
2521 Sched<[WriteSTIdx, ReadAdrBase]> {
2525 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2528 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2529 string asm, dag ins, dag outs, list<dag> pat>
2530 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2535 let Inst{31-30} = sz;
2536 let Inst{29-27} = 0b111;
2538 let Inst{25-24} = 0b00;
2539 let Inst{23-22} = opc;
2541 let Inst{20-16} = Rm;
2542 let Inst{15} = extend{1}; // sign extend Rm?
2544 let Inst{12} = extend{0}; // do shift?
2545 let Inst{11-10} = 0b10;
2550 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2551 string asm, ValueType Ty, SDPatternOperator loadop> {
2552 let AddedComplexity = 10 in
2553 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2554 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2555 [(set (Ty regtype:$Rt),
2556 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2557 ro_Wextend16:$extend)))]>,
2558 Sched<[WriteLDIdx, ReadAdrBase]> {
2562 let AddedComplexity = 10 in
2563 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2564 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2565 [(set (Ty regtype:$Rt),
2566 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2567 ro_Xextend16:$extend)))]>,
2568 Sched<[WriteLDIdx, ReadAdrBase]> {
2572 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2575 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2576 string asm, ValueType Ty, SDPatternOperator storeop> {
2577 let AddedComplexity = 10 in
2578 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2579 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2580 [(storeop (Ty regtype:$Rt),
2581 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2582 ro_Wextend16:$extend))]>,
2583 Sched<[WriteSTIdx, ReadAdrBase]> {
2587 let AddedComplexity = 10 in
2588 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2589 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2590 [(storeop (Ty regtype:$Rt),
2591 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2592 ro_Xextend16:$extend))]>,
2593 Sched<[WriteSTIdx, ReadAdrBase]> {
2597 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2600 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2601 string asm, dag ins, dag outs, list<dag> pat>
2602 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2607 let Inst{31-30} = sz;
2608 let Inst{29-27} = 0b111;
2610 let Inst{25-24} = 0b00;
2611 let Inst{23-22} = opc;
2613 let Inst{20-16} = Rm;
2614 let Inst{15} = extend{1}; // sign extend Rm?
2616 let Inst{12} = extend{0}; // do shift?
2617 let Inst{11-10} = 0b10;
2622 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2623 string asm, ValueType Ty, SDPatternOperator loadop> {
2624 let AddedComplexity = 10 in
2625 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2626 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2627 [(set (Ty regtype:$Rt),
2628 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2629 ro_Wextend32:$extend)))]>,
2630 Sched<[WriteLDIdx, ReadAdrBase]> {
2634 let AddedComplexity = 10 in
2635 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2636 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2637 [(set (Ty regtype:$Rt),
2638 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2639 ro_Xextend32:$extend)))]>,
2640 Sched<[WriteLDIdx, ReadAdrBase]> {
2644 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2647 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2648 string asm, ValueType Ty, SDPatternOperator storeop> {
2649 let AddedComplexity = 10 in
2650 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2651 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2652 [(storeop (Ty regtype:$Rt),
2653 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2654 ro_Wextend32:$extend))]>,
2655 Sched<[WriteSTIdx, ReadAdrBase]> {
2659 let AddedComplexity = 10 in
2660 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2661 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2662 [(storeop (Ty regtype:$Rt),
2663 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2664 ro_Xextend32:$extend))]>,
2665 Sched<[WriteSTIdx, ReadAdrBase]> {
2669 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2672 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2673 string asm, dag ins, dag outs, list<dag> pat>
2674 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2679 let Inst{31-30} = sz;
2680 let Inst{29-27} = 0b111;
2682 let Inst{25-24} = 0b00;
2683 let Inst{23-22} = opc;
2685 let Inst{20-16} = Rm;
2686 let Inst{15} = extend{1}; // sign extend Rm?
2688 let Inst{12} = extend{0}; // do shift?
2689 let Inst{11-10} = 0b10;
2694 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2695 string asm, ValueType Ty, SDPatternOperator loadop> {
2696 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2697 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2698 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2699 [(set (Ty regtype:$Rt),
2700 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2701 ro_Wextend64:$extend)))]>,
2702 Sched<[WriteLDIdx, ReadAdrBase]> {
2706 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2707 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2708 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2709 [(set (Ty regtype:$Rt),
2710 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2711 ro_Xextend64:$extend)))]>,
2712 Sched<[WriteLDIdx, ReadAdrBase]> {
2716 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2719 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2720 string asm, ValueType Ty, SDPatternOperator storeop> {
2721 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2722 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2723 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2724 [(storeop (Ty regtype:$Rt),
2725 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2726 ro_Wextend64:$extend))]>,
2727 Sched<[WriteSTIdx, ReadAdrBase]> {
2731 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2732 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2733 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2734 [(storeop (Ty regtype:$Rt),
2735 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2736 ro_Xextend64:$extend))]>,
2737 Sched<[WriteSTIdx, ReadAdrBase]> {
2741 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2744 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2745 string asm, dag ins, dag outs, list<dag> pat>
2746 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2751 let Inst{31-30} = sz;
2752 let Inst{29-27} = 0b111;
2754 let Inst{25-24} = 0b00;
2755 let Inst{23-22} = opc;
2757 let Inst{20-16} = Rm;
2758 let Inst{15} = extend{1}; // sign extend Rm?
2760 let Inst{12} = extend{0}; // do shift?
2761 let Inst{11-10} = 0b10;
2766 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2767 string asm, ValueType Ty, SDPatternOperator loadop> {
2768 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2769 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2770 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2771 [(set (Ty regtype:$Rt),
2772 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2773 ro_Wextend128:$extend)))]>,
2774 Sched<[WriteLDIdx, ReadAdrBase]> {
2778 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2779 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2780 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2781 [(set (Ty regtype:$Rt),
2782 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2783 ro_Xextend128:$extend)))]>,
2784 Sched<[WriteLDIdx, ReadAdrBase]> {
2788 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2791 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2792 string asm, ValueType Ty, SDPatternOperator storeop> {
2793 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2794 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2795 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2796 [(storeop (Ty regtype:$Rt),
2797 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2798 ro_Wextend128:$extend))]>,
2799 Sched<[WriteSTIdx, ReadAdrBase]> {
2803 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2804 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2805 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2806 [(storeop (Ty regtype:$Rt),
2807 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2808 ro_Xextend128:$extend))]>,
2809 Sched<[WriteSTIdx, ReadAdrBase]> {
2813 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2816 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2817 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2818 string asm, list<dag> pat>
2819 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2825 let Inst{31-30} = sz;
2826 let Inst{29-27} = 0b111;
2828 let Inst{25-24} = 0b00;
2829 let Inst{23-22} = opc;
2831 let Inst{20-16} = Rm;
2832 let Inst{15} = extend{1}; // sign extend Rm?
2834 let Inst{12} = extend{0}; // do shift?
2835 let Inst{11-10} = 0b10;
2840 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2841 def roW : BasePrefetchRO<sz, V, opc, (outs),
2842 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2843 asm, [(AArch64Prefetch imm:$Rt,
2844 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2845 ro_Wextend64:$extend))]> {
2849 def roX : BasePrefetchRO<sz, V, opc, (outs),
2850 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2851 asm, [(AArch64Prefetch imm:$Rt,
2852 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2853 ro_Xextend64:$extend))]> {
2857 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2858 (!cast<Instruction>(NAME # "roX") prfop:$Rt,
2859 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2863 // Load/store unscaled immediate
2866 def am_unscaled8 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2867 def am_unscaled16 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2868 def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2869 def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2870 def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2872 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2873 string asm, list<dag> pattern>
2874 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2878 let Inst{31-30} = sz;
2879 let Inst{29-27} = 0b111;
2881 let Inst{25-24} = 0b00;
2882 let Inst{23-22} = opc;
2884 let Inst{20-12} = offset;
2885 let Inst{11-10} = 0b00;
2889 let DecoderMethod = "DecodeSignedLdStInstruction";
2892 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2893 string asm, list<dag> pattern> {
2894 let AddedComplexity = 1 in // try this before LoadUI
2895 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2896 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
2899 def : InstAlias<asm # " $Rt, [$Rn]",
2900 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2903 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2904 string asm, list<dag> pattern> {
2905 let AddedComplexity = 1 in // try this before StoreUI
2906 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2907 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2911 def : InstAlias<asm # " $Rt, [$Rn]",
2912 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2915 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
2917 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2918 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2919 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
2923 def : InstAlias<asm # " $Rt, [$Rn]",
2924 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
2928 // Load/store unscaled immediate, unprivileged
2931 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2932 dag oops, dag iops, string asm>
2933 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
2937 let Inst{31-30} = sz;
2938 let Inst{29-27} = 0b111;
2940 let Inst{25-24} = 0b00;
2941 let Inst{23-22} = opc;
2943 let Inst{20-12} = offset;
2944 let Inst{11-10} = 0b10;
2948 let DecoderMethod = "DecodeSignedLdStInstruction";
2951 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
2952 RegisterClass regtype, string asm> {
2953 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in
2954 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
2955 (ins GPR64sp:$Rn, simm9:$offset), asm>,
2958 def : InstAlias<asm # " $Rt, [$Rn]",
2959 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2962 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2963 RegisterClass regtype, string asm> {
2964 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2965 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
2966 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2970 def : InstAlias<asm # " $Rt, [$Rn]",
2971 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2975 // Load/store pre-indexed
2978 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2979 string asm, string cstr, list<dag> pat>
2980 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
2984 let Inst{31-30} = sz;
2985 let Inst{29-27} = 0b111;
2987 let Inst{25-24} = 0;
2988 let Inst{23-22} = opc;
2990 let Inst{20-12} = offset;
2991 let Inst{11-10} = 0b11;
2995 let DecoderMethod = "DecodeSignedLdStInstruction";
2998 let hasSideEffects = 0 in {
2999 let mayStore = 0, mayLoad = 1 in
3000 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3002 : BaseLoadStorePreIdx<sz, V, opc,
3003 (outs GPR64sp:$wback, regtype:$Rt),
3004 (ins GPR64sp:$Rn, simm9:$offset), asm,
3005 "$Rn = $wback,@earlyclobber $wback", []>,
3006 Sched<[WriteLD, WriteAdr]>;
3008 let mayStore = 1, mayLoad = 0 in
3009 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3010 string asm, SDPatternOperator storeop, ValueType Ty>
3011 : BaseLoadStorePreIdx<sz, V, opc,
3012 (outs GPR64sp:$wback),
3013 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3014 asm, "$Rn = $wback,@earlyclobber $wback",
3015 [(set GPR64sp:$wback,
3016 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3017 Sched<[WriteAdr, WriteST]>;
3018 } // hasSideEffects = 0
3021 // Load/store post-indexed
3024 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3025 string asm, string cstr, list<dag> pat>
3026 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
3030 let Inst{31-30} = sz;
3031 let Inst{29-27} = 0b111;
3033 let Inst{25-24} = 0b00;
3034 let Inst{23-22} = opc;
3036 let Inst{20-12} = offset;
3037 let Inst{11-10} = 0b01;
3041 let DecoderMethod = "DecodeSignedLdStInstruction";
3044 let hasSideEffects = 0 in {
3045 let mayStore = 0, mayLoad = 1 in
3046 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3048 : BaseLoadStorePostIdx<sz, V, opc,
3049 (outs GPR64sp:$wback, regtype:$Rt),
3050 (ins GPR64sp:$Rn, simm9:$offset),
3051 asm, "$Rn = $wback,@earlyclobber $wback", []>,
3052 Sched<[WriteLD, WriteI]>;
3054 let mayStore = 1, mayLoad = 0 in
3055 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3056 string asm, SDPatternOperator storeop, ValueType Ty>
3057 : BaseLoadStorePostIdx<sz, V, opc,
3058 (outs GPR64sp:$wback),
3059 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3060 asm, "$Rn = $wback,@earlyclobber $wback",
3061 [(set GPR64sp:$wback,
3062 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3063 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
3064 } // hasSideEffects = 0
3071 // (indexed, offset)
3073 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3075 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3080 let Inst{31-30} = opc;
3081 let Inst{29-27} = 0b101;
3083 let Inst{25-23} = 0b010;
3085 let Inst{21-15} = offset;
3086 let Inst{14-10} = Rt2;
3090 let DecoderMethod = "DecodePairLdStInstruction";
3093 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3094 Operand indextype, string asm> {
3095 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3096 def i : BaseLoadStorePairOffset<opc, V, 1,
3097 (outs regtype:$Rt, regtype:$Rt2),
3098 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3099 Sched<[WriteLD, WriteLDHi]>;
3101 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3102 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3107 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3108 Operand indextype, string asm> {
3109 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3110 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3111 (ins regtype:$Rt, regtype:$Rt2,
3112 GPR64sp:$Rn, indextype:$offset),
3116 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3117 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3122 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3124 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback,@earlyclobber $wback", []> {
3129 let Inst{31-30} = opc;
3130 let Inst{29-27} = 0b101;
3132 let Inst{25-23} = 0b011;
3134 let Inst{21-15} = offset;
3135 let Inst{14-10} = Rt2;
3139 let DecoderMethod = "DecodePairLdStInstruction";
3142 let hasSideEffects = 0 in {
3143 let mayStore = 0, mayLoad = 1 in
3144 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3145 Operand indextype, string asm>
3146 : BaseLoadStorePairPreIdx<opc, V, 1,
3147 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3148 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3149 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3151 let mayStore = 1, mayLoad = 0 in
3152 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3153 Operand indextype, string asm>
3154 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3155 (ins regtype:$Rt, regtype:$Rt2,
3156 GPR64sp:$Rn, indextype:$offset),
3158 Sched<[WriteAdr, WriteSTP]>;
3159 } // hasSideEffects = 0
3163 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3165 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback,@earlyclobber $wback", []> {
3170 let Inst{31-30} = opc;
3171 let Inst{29-27} = 0b101;
3173 let Inst{25-23} = 0b001;
3175 let Inst{21-15} = offset;
3176 let Inst{14-10} = Rt2;
3180 let DecoderMethod = "DecodePairLdStInstruction";
3183 let hasSideEffects = 0 in {
3184 let mayStore = 0, mayLoad = 1 in
3185 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3186 Operand idxtype, string asm>
3187 : BaseLoadStorePairPostIdx<opc, V, 1,
3188 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3189 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3190 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3192 let mayStore = 1, mayLoad = 0 in
3193 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3194 Operand idxtype, string asm>
3195 : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
3196 (ins GPR64sp:$wback, regtype:$Rt, regtype:$Rt2,
3197 GPR64sp:$Rn, idxtype:$offset),
3199 Sched<[WriteAdr, WriteSTP]>;
3200 } // hasSideEffects = 0
3204 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3206 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3211 let Inst{31-30} = opc;
3212 let Inst{29-27} = 0b101;
3214 let Inst{25-23} = 0b000;
3216 let Inst{21-15} = offset;
3217 let Inst{14-10} = Rt2;
3221 let DecoderMethod = "DecodePairLdStInstruction";
3224 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3225 Operand indextype, string asm> {
3226 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3227 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3228 (outs regtype:$Rt, regtype:$Rt2),
3229 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3230 Sched<[WriteLD, WriteLDHi]>;
3233 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3234 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3238 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3239 Operand indextype, string asm> {
3240 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in
3241 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3242 (ins regtype:$Rt, regtype:$Rt2,
3243 GPR64sp:$Rn, indextype:$offset),
3247 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3248 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3253 // Load/store exclusive
3256 // True exclusive operations write to and/or read from the system's exclusive
3257 // monitors, which as far as a compiler is concerned can be modelled as a
3258 // random shared memory address. Hence LoadExclusive mayStore.
3260 // Since these instructions have the undefined register bits set to 1 in
3261 // their canonical form, we need a post encoder method to set those bits
3262 // to 1 when encoding these instructions. We do this using the
3263 // fixLoadStoreExclusive function. This function has template parameters:
3265 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3267 // hasRs indicates that the instruction uses the Rs field, so we won't set
3268 // it to 1 (and the same for Rt2). We don't need template parameters for
3269 // the other register fields since Rt and Rn are always used.
3271 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3272 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3273 dag oops, dag iops, string asm, string operands>
3274 : I<oops, iops, asm, operands, "", []> {
3275 let Inst{31-30} = sz;
3276 let Inst{29-24} = 0b001000;
3282 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3285 // Neither Rs nor Rt2 operands.
3286 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3287 dag oops, dag iops, string asm, string operands>
3288 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3294 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3297 // Simple load acquires don't set the exclusive monitor
3298 let mayLoad = 1, mayStore = 0 in
3299 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3300 RegisterClass regtype, string asm>
3301 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3302 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3305 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3306 RegisterClass regtype, string asm>
3307 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3308 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3311 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3312 RegisterClass regtype, string asm>
3313 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3314 (outs regtype:$Rt, regtype:$Rt2),
3315 (ins GPR64sp0:$Rn), asm,
3316 "\t$Rt, $Rt2, [$Rn]">,
3317 Sched<[WriteLD, WriteLDHi]> {
3321 let Inst{14-10} = Rt2;
3325 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3328 // Simple store release operations do not check the exclusive monitor.
3329 let mayLoad = 0, mayStore = 1 in
3330 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3331 RegisterClass regtype, string asm>
3332 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3333 (ins regtype:$Rt, GPR64sp0:$Rn),
3334 asm, "\t$Rt, [$Rn]">,
3337 let mayLoad = 1, mayStore = 1 in
3338 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3339 RegisterClass regtype, string asm>
3340 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3341 (ins regtype:$Rt, GPR64sp0:$Rn),
3342 asm, "\t$Ws, $Rt, [$Rn]">,
3347 let Inst{20-16} = Ws;
3351 let Constraints = "@earlyclobber $Ws";
3352 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3355 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3356 RegisterClass regtype, string asm>
3357 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3359 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3360 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3366 let Inst{20-16} = Ws;
3367 let Inst{14-10} = Rt2;
3371 let Constraints = "@earlyclobber $Ws";
3375 // Exception generation
3378 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3379 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3380 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3383 let Inst{31-24} = 0b11010100;
3384 let Inst{23-21} = op1;
3385 let Inst{20-5} = imm;
3386 let Inst{4-2} = 0b000;
3390 let Predicates = [HasFPARMv8] in {
3393 // Floating point to integer conversion
3396 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3397 RegisterClass srcType, RegisterClass dstType,
3398 string asm, list<dag> pattern>
3399 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3400 asm, "\t$Rd, $Rn", "", pattern>,
3401 Sched<[WriteFCvt]> {
3404 let Inst{30-29} = 0b00;
3405 let Inst{28-24} = 0b11110;
3406 let Inst{23-22} = type;
3408 let Inst{20-19} = rmode;
3409 let Inst{18-16} = opcode;
3410 let Inst{15-10} = 0;
3415 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3416 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3417 RegisterClass srcType, RegisterClass dstType,
3418 Operand immType, string asm, list<dag> pattern>
3419 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3420 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3421 Sched<[WriteFCvt]> {
3425 let Inst{30-29} = 0b00;
3426 let Inst{28-24} = 0b11110;
3427 let Inst{23-22} = type;
3429 let Inst{20-19} = rmode;
3430 let Inst{18-16} = opcode;
3431 let Inst{15-10} = scale;
3436 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3437 SDPatternOperator OpN> {
3438 // Unscaled single-precision to 32-bit
3439 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3440 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3441 let Inst{31} = 0; // 32-bit GPR flag
3444 // Unscaled single-precision to 64-bit
3445 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3446 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3447 let Inst{31} = 1; // 64-bit GPR flag
3450 // Unscaled double-precision to 32-bit
3451 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3452 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3453 let Inst{31} = 0; // 32-bit GPR flag
3456 // Unscaled double-precision to 64-bit
3457 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3458 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3459 let Inst{31} = 1; // 64-bit GPR flag
3463 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3464 SDPatternOperator OpN> {
3465 // Scaled single-precision to 32-bit
3466 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3467 fixedpoint_f32_i32, asm,
3468 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3469 fixedpoint_f32_i32:$scale)))]> {
3470 let Inst{31} = 0; // 32-bit GPR flag
3474 // Scaled single-precision to 64-bit
3475 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3476 fixedpoint_f32_i64, asm,
3477 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3478 fixedpoint_f32_i64:$scale)))]> {
3479 let Inst{31} = 1; // 64-bit GPR flag
3482 // Scaled double-precision to 32-bit
3483 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3484 fixedpoint_f64_i32, asm,
3485 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3486 fixedpoint_f64_i32:$scale)))]> {
3487 let Inst{31} = 0; // 32-bit GPR flag
3491 // Scaled double-precision to 64-bit
3492 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3493 fixedpoint_f64_i64, asm,
3494 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3495 fixedpoint_f64_i64:$scale)))]> {
3496 let Inst{31} = 1; // 64-bit GPR flag
3501 // Integer to floating point conversion
3504 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3505 class BaseIntegerToFP<bit isUnsigned,
3506 RegisterClass srcType, RegisterClass dstType,
3507 Operand immType, string asm, list<dag> pattern>
3508 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3509 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3510 Sched<[WriteFCvt]> {
3514 let Inst{30-23} = 0b00111100;
3515 let Inst{21-17} = 0b00001;
3516 let Inst{16} = isUnsigned;
3517 let Inst{15-10} = scale;
3522 class BaseIntegerToFPUnscaled<bit isUnsigned,
3523 RegisterClass srcType, RegisterClass dstType,
3524 ValueType dvt, string asm, SDNode node>
3525 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3526 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3527 Sched<[WriteFCvt]> {
3531 let Inst{30-23} = 0b00111100;
3532 let Inst{21-17} = 0b10001;
3533 let Inst{16} = isUnsigned;
3534 let Inst{15-10} = 0b000000;
3539 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3541 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3542 let Inst{31} = 0; // 32-bit GPR flag
3543 let Inst{22} = 0; // 32-bit FPR flag
3546 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3547 let Inst{31} = 0; // 32-bit GPR flag
3548 let Inst{22} = 1; // 64-bit FPR flag
3551 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3552 let Inst{31} = 1; // 64-bit GPR flag
3553 let Inst{22} = 0; // 32-bit FPR flag
3556 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3557 let Inst{31} = 1; // 64-bit GPR flag
3558 let Inst{22} = 1; // 64-bit FPR flag
3562 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3564 (fdiv (node GPR32:$Rn),
3565 fixedpoint_f32_i32:$scale))]> {
3566 let Inst{31} = 0; // 32-bit GPR flag
3567 let Inst{22} = 0; // 32-bit FPR flag
3571 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3573 (fdiv (node GPR32:$Rn),
3574 fixedpoint_f64_i32:$scale))]> {
3575 let Inst{31} = 0; // 32-bit GPR flag
3576 let Inst{22} = 1; // 64-bit FPR flag
3580 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3582 (fdiv (node GPR64:$Rn),
3583 fixedpoint_f32_i64:$scale))]> {
3584 let Inst{31} = 1; // 64-bit GPR flag
3585 let Inst{22} = 0; // 32-bit FPR flag
3588 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3590 (fdiv (node GPR64:$Rn),
3591 fixedpoint_f64_i64:$scale))]> {
3592 let Inst{31} = 1; // 64-bit GPR flag
3593 let Inst{22} = 1; // 64-bit FPR flag
3598 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3601 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3602 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3603 RegisterClass srcType, RegisterClass dstType,
3605 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3606 // We use COPY_TO_REGCLASS for these bitconvert operations.
3607 // copyPhysReg() expands the resultant COPY instructions after
3608 // regalloc is done. This gives greater freedom for the allocator
3609 // and related passes (coalescing, copy propagation, et. al.) to
3610 // be more effective.
3611 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3612 Sched<[WriteFCopy]> {
3615 let Inst{30-23} = 0b00111100;
3617 let Inst{20-19} = rmode;
3618 let Inst{18-16} = opcode;
3619 let Inst{15-10} = 0b000000;
3624 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3625 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3626 RegisterClass srcType, RegisterOperand dstType, string asm,
3628 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3629 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3630 Sched<[WriteFCopy]> {
3633 let Inst{30-23} = 0b00111101;
3635 let Inst{20-19} = rmode;
3636 let Inst{18-16} = opcode;
3637 let Inst{15-10} = 0b000000;
3641 let DecoderMethod = "DecodeFMOVLaneInstruction";
3644 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3645 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3646 RegisterOperand srcType, RegisterClass dstType, string asm,
3648 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3649 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3650 Sched<[WriteFCopy]> {
3653 let Inst{30-23} = 0b00111101;
3655 let Inst{20-19} = rmode;
3656 let Inst{18-16} = opcode;
3657 let Inst{15-10} = 0b000000;
3661 let DecoderMethod = "DecodeFMOVLaneInstruction";
3666 multiclass UnscaledConversion<string asm> {
3667 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3668 let Inst{31} = 0; // 32-bit GPR flag
3669 let Inst{22} = 0; // 32-bit FPR flag
3672 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3673 let Inst{31} = 1; // 64-bit GPR flag
3674 let Inst{22} = 1; // 64-bit FPR flag
3677 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3678 let Inst{31} = 0; // 32-bit GPR flag
3679 let Inst{22} = 0; // 32-bit FPR flag
3682 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3683 let Inst{31} = 1; // 64-bit GPR flag
3684 let Inst{22} = 1; // 64-bit FPR flag
3687 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3693 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3701 // Floating point conversion
3704 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3705 RegisterClass srcType, string asm, list<dag> pattern>
3706 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3707 Sched<[WriteFCvt]> {
3710 let Inst{31-24} = 0b00011110;
3711 let Inst{23-22} = type;
3712 let Inst{21-17} = 0b10001;
3713 let Inst{16-15} = opcode;
3714 let Inst{14-10} = 0b10000;
3719 multiclass FPConversion<string asm> {
3720 // Double-precision to Half-precision
3721 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3722 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3724 // Double-precision to Single-precision
3725 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3726 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3728 // Half-precision to Double-precision
3729 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3730 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3732 // Half-precision to Single-precision
3733 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3734 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3736 // Single-precision to Double-precision
3737 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3738 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3740 // Single-precision to Half-precision
3741 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3742 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3746 // Single operand floating point data processing
3749 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3750 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3751 ValueType vt, string asm, SDPatternOperator node>
3752 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3753 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3757 let Inst{31-23} = 0b000111100;
3758 let Inst{21-19} = 0b100;
3759 let Inst{18-15} = opcode;
3760 let Inst{14-10} = 0b10000;
3765 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3766 SDPatternOperator node = null_frag> {
3767 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3768 let Inst{22} = 0; // 32-bit size flag
3771 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3772 let Inst{22} = 1; // 64-bit size flag
3777 // Two operand floating point data processing
3780 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3781 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3782 string asm, list<dag> pat>
3783 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3784 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3789 let Inst{31-23} = 0b000111100;
3791 let Inst{20-16} = Rm;
3792 let Inst{15-12} = opcode;
3793 let Inst{11-10} = 0b10;
3798 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3799 SDPatternOperator node = null_frag> {
3800 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3801 [(set (f32 FPR32:$Rd),
3802 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3803 let Inst{22} = 0; // 32-bit size flag
3806 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3807 [(set (f64 FPR64:$Rd),
3808 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3809 let Inst{22} = 1; // 64-bit size flag
3813 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3814 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3815 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3816 let Inst{22} = 0; // 32-bit size flag
3819 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3820 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3821 let Inst{22} = 1; // 64-bit size flag
3827 // Three operand floating point data processing
3830 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3831 RegisterClass regtype, string asm, list<dag> pat>
3832 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3833 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3834 Sched<[WriteFMul]> {
3839 let Inst{31-23} = 0b000111110;
3840 let Inst{21} = isNegated;
3841 let Inst{20-16} = Rm;
3842 let Inst{15} = isSub;
3843 let Inst{14-10} = Ra;
3848 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3849 SDPatternOperator node> {
3850 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3852 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3853 let Inst{22} = 0; // 32-bit size flag
3856 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3858 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3859 let Inst{22} = 1; // 64-bit size flag
3864 // Floating point data comparisons
3867 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3868 class BaseOneOperandFPComparison<bit signalAllNans,
3869 RegisterClass regtype, string asm,
3871 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3872 Sched<[WriteFCmp]> {
3874 let Inst{31-23} = 0b000111100;
3877 let Inst{15-10} = 0b001000;
3879 let Inst{4} = signalAllNans;
3880 let Inst{3-0} = 0b1000;
3882 // Rm should be 0b00000 canonically, but we need to accept any value.
3883 let PostEncoderMethod = "fixOneOperandFPComparison";
3886 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3887 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3888 string asm, list<dag> pat>
3889 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3890 Sched<[WriteFCmp]> {
3893 let Inst{31-23} = 0b000111100;
3895 let Inst{20-16} = Rm;
3896 let Inst{15-10} = 0b001000;
3898 let Inst{4} = signalAllNans;
3899 let Inst{3-0} = 0b0000;
3902 multiclass FPComparison<bit signalAllNans, string asm,
3903 SDPatternOperator OpNode = null_frag> {
3904 let Defs = [NZCV] in {
3905 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3906 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3910 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3911 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3915 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3916 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3920 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3921 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3928 // Floating point conditional comparisons
3931 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3932 class BaseFPCondComparison<bit signalAllNans,
3933 RegisterClass regtype, string asm>
3934 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3935 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3936 Sched<[WriteFCmp]> {
3942 let Inst{31-23} = 0b000111100;
3944 let Inst{20-16} = Rm;
3945 let Inst{15-12} = cond;
3946 let Inst{11-10} = 0b01;
3948 let Inst{4} = signalAllNans;
3949 let Inst{3-0} = nzcv;
3952 multiclass FPCondComparison<bit signalAllNans, string asm> {
3953 let Defs = [NZCV], Uses = [NZCV] in {
3954 def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
3958 def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
3961 } // Defs = [NZCV], Uses = [NZCV]
3965 // Floating point conditional select
3968 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
3969 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3970 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3972 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
3973 (i32 imm:$cond), NZCV))]>,
3980 let Inst{31-23} = 0b000111100;
3982 let Inst{20-16} = Rm;
3983 let Inst{15-12} = cond;
3984 let Inst{11-10} = 0b11;
3989 multiclass FPCondSelect<string asm> {
3990 let Uses = [NZCV] in {
3991 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
3995 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
4002 // Floating move immediate
4005 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
4006 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
4007 [(set regtype:$Rd, fpimmtype:$imm)]>,
4008 Sched<[WriteFImm]> {
4011 let Inst{31-23} = 0b000111100;
4013 let Inst{20-13} = imm;
4014 let Inst{12-5} = 0b10000000;
4018 multiclass FPMoveImmediate<string asm> {
4019 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
4023 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
4027 } // end of 'let Predicates = [HasFPARMv8]'
4029 //----------------------------------------------------------------------------
4031 //----------------------------------------------------------------------------
4033 let Predicates = [HasNEON] in {
4035 //----------------------------------------------------------------------------
4036 // AdvSIMD three register vector instructions
4037 //----------------------------------------------------------------------------
4039 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4040 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4041 RegisterOperand regtype, string asm, string kind,
4043 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4044 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4045 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4053 let Inst{28-24} = 0b01110;
4054 let Inst{23-22} = size;
4056 let Inst{20-16} = Rm;
4057 let Inst{15-11} = opcode;
4063 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4064 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4065 RegisterOperand regtype, string asm, string kind,
4067 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4068 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4069 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4077 let Inst{28-24} = 0b01110;
4078 let Inst{23-22} = size;
4080 let Inst{20-16} = Rm;
4081 let Inst{15-11} = opcode;
4087 // All operand sizes distinguished in the encoding.
4088 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4089 SDPatternOperator OpNode> {
4090 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4092 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4093 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4095 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4096 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4098 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4099 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4101 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4102 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4104 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4105 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4107 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4108 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
4110 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4113 // As above, but D sized elements unsupported.
4114 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4115 SDPatternOperator OpNode> {
4116 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4118 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4119 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4121 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4122 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4124 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4125 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4127 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4128 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4130 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4131 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4133 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4136 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4137 SDPatternOperator OpNode> {
4138 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4140 [(set (v8i8 V64:$dst),
4141 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4142 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4144 [(set (v16i8 V128:$dst),
4145 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4146 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
4148 [(set (v4i16 V64:$dst),
4149 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4150 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
4152 [(set (v8i16 V128:$dst),
4153 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4154 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
4156 [(set (v2i32 V64:$dst),
4157 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4158 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
4160 [(set (v4i32 V128:$dst),
4161 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4164 // As above, but only B sized elements supported.
4165 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4166 SDPatternOperator OpNode> {
4167 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4169 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4170 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4172 [(set (v16i8 V128:$Rd),
4173 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4176 // As above, but only S and D sized floating point elements supported.
4177 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
4178 string asm, SDPatternOperator OpNode> {
4179 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4181 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4182 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4184 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4185 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4187 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4190 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4192 SDPatternOperator OpNode> {
4193 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4195 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4196 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4198 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4199 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4201 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4204 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4205 string asm, SDPatternOperator OpNode> {
4206 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4208 [(set (v2f32 V64:$dst),
4209 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4210 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4212 [(set (v4f32 V128:$dst),
4213 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4214 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4216 [(set (v2f64 V128:$dst),
4217 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4220 // As above, but D and B sized elements unsupported.
4221 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4222 SDPatternOperator OpNode> {
4223 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4225 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4226 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4228 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4229 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4231 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4232 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4234 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4237 // Logical three vector ops share opcode bits, and only use B sized elements.
4238 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4239 SDPatternOperator OpNode = null_frag> {
4240 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4242 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4243 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4245 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4247 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4248 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4249 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4250 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4251 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4252 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4254 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4255 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4256 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4257 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4258 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4259 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4262 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4263 string asm, SDPatternOperator OpNode> {
4264 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4266 [(set (v8i8 V64:$dst),
4267 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4268 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4270 [(set (v16i8 V128:$dst),
4271 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4272 (v16i8 V128:$Rm)))]>;
4274 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4276 (!cast<Instruction>(NAME#"v8i8")
4277 V64:$LHS, V64:$MHS, V64:$RHS)>;
4278 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4280 (!cast<Instruction>(NAME#"v8i8")
4281 V64:$LHS, V64:$MHS, V64:$RHS)>;
4282 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4284 (!cast<Instruction>(NAME#"v8i8")
4285 V64:$LHS, V64:$MHS, V64:$RHS)>;
4287 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4288 (v8i16 V128:$RHS))),
4289 (!cast<Instruction>(NAME#"v16i8")
4290 V128:$LHS, V128:$MHS, V128:$RHS)>;
4291 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4292 (v4i32 V128:$RHS))),
4293 (!cast<Instruction>(NAME#"v16i8")
4294 V128:$LHS, V128:$MHS, V128:$RHS)>;
4295 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4296 (v2i64 V128:$RHS))),
4297 (!cast<Instruction>(NAME#"v16i8")
4298 V128:$LHS, V128:$MHS, V128:$RHS)>;
4302 //----------------------------------------------------------------------------
4303 // AdvSIMD two register vector instructions.
4304 //----------------------------------------------------------------------------
4306 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4307 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4308 RegisterOperand regtype, string asm, string dstkind,
4309 string srckind, list<dag> pattern>
4310 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4311 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4312 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4319 let Inst{28-24} = 0b01110;
4320 let Inst{23-22} = size;
4321 let Inst{21-17} = 0b10000;
4322 let Inst{16-12} = opcode;
4323 let Inst{11-10} = 0b10;
4328 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4329 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4330 RegisterOperand regtype, string asm, string dstkind,
4331 string srckind, list<dag> pattern>
4332 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4333 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4334 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4341 let Inst{28-24} = 0b01110;
4342 let Inst{23-22} = size;
4343 let Inst{21-17} = 0b10000;
4344 let Inst{16-12} = opcode;
4345 let Inst{11-10} = 0b10;
4350 // Supports B, H, and S element sizes.
4351 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4352 SDPatternOperator OpNode> {
4353 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4355 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4356 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4357 asm, ".16b", ".16b",
4358 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4359 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4361 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4362 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4364 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4365 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4367 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4368 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4370 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4373 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4374 RegisterOperand regtype, string asm, string dstkind,
4375 string srckind, string amount>
4376 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4377 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4378 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4384 let Inst{29-24} = 0b101110;
4385 let Inst{23-22} = size;
4386 let Inst{21-10} = 0b100001001110;
4391 multiclass SIMDVectorLShiftLongBySizeBHS {
4392 let hasSideEffects = 0 in {
4393 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4394 "shll", ".8h", ".8b", "8">;
4395 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4396 "shll2", ".8h", ".16b", "8">;
4397 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4398 "shll", ".4s", ".4h", "16">;
4399 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4400 "shll2", ".4s", ".8h", "16">;
4401 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4402 "shll", ".2d", ".2s", "32">;
4403 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4404 "shll2", ".2d", ".4s", "32">;
4408 // Supports all element sizes.
4409 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4410 SDPatternOperator OpNode> {
4411 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4413 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4414 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4416 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4417 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4419 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4420 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4422 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4423 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4425 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4426 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4428 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4431 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4432 SDPatternOperator OpNode> {
4433 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4435 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4437 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4439 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4440 (v16i8 V128:$Rn)))]>;
4441 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4443 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4444 (v4i16 V64:$Rn)))]>;
4445 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4447 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4448 (v8i16 V128:$Rn)))]>;
4449 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4451 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4452 (v2i32 V64:$Rn)))]>;
4453 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4455 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4456 (v4i32 V128:$Rn)))]>;
4459 // Supports all element sizes, except 1xD.
4460 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4461 SDPatternOperator OpNode> {
4462 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4464 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4465 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4466 asm, ".16b", ".16b",
4467 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4468 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4470 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4471 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4473 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4474 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4476 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4477 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4479 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4480 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4482 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4485 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4486 SDPatternOperator OpNode = null_frag> {
4487 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4489 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4490 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4491 asm, ".16b", ".16b",
4492 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4493 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4495 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4496 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4498 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4499 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4501 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4502 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4504 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4505 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4507 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4511 // Supports only B element sizes.
4512 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4513 SDPatternOperator OpNode> {
4514 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4516 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4517 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4518 asm, ".16b", ".16b",
4519 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4523 // Supports only B and H element sizes.
4524 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4525 SDPatternOperator OpNode> {
4526 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4528 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4529 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4530 asm, ".16b", ".16b",
4531 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4532 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4534 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4535 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4537 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4540 // Supports only S and D element sizes, uses high bit of the size field
4541 // as an extra opcode bit.
4542 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4543 SDPatternOperator OpNode> {
4544 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4546 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4547 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4549 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4550 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4552 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4555 // Supports only S element size.
4556 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4557 SDPatternOperator OpNode> {
4558 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4560 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4561 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4563 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4567 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4568 SDPatternOperator OpNode> {
4569 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4571 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4572 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4574 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4575 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4577 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4580 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4581 SDPatternOperator OpNode> {
4582 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4584 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4585 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4587 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4588 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4590 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4594 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4595 RegisterOperand inreg, RegisterOperand outreg,
4596 string asm, string outkind, string inkind,
4598 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4599 "{\t$Rd" # outkind # ", $Rn" # inkind #
4600 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4607 let Inst{28-24} = 0b01110;
4608 let Inst{23-22} = size;
4609 let Inst{21-17} = 0b10000;
4610 let Inst{16-12} = opcode;
4611 let Inst{11-10} = 0b10;
4616 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4617 RegisterOperand inreg, RegisterOperand outreg,
4618 string asm, string outkind, string inkind,
4620 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4621 "{\t$Rd" # outkind # ", $Rn" # inkind #
4622 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4629 let Inst{28-24} = 0b01110;
4630 let Inst{23-22} = size;
4631 let Inst{21-17} = 0b10000;
4632 let Inst{16-12} = opcode;
4633 let Inst{11-10} = 0b10;
4638 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4639 SDPatternOperator OpNode> {
4640 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4642 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4643 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4644 asm#"2", ".16b", ".8h", []>;
4645 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4647 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4648 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4649 asm#"2", ".8h", ".4s", []>;
4650 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4652 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4653 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4654 asm#"2", ".4s", ".2d", []>;
4656 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4657 (!cast<Instruction>(NAME # "v16i8")
4658 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4659 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4660 (!cast<Instruction>(NAME # "v8i16")
4661 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4662 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4663 (!cast<Instruction>(NAME # "v4i32")
4664 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4667 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4668 RegisterOperand regtype,
4669 string asm, string kind, string zero,
4670 ValueType dty, ValueType sty, SDNode OpNode>
4671 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4672 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4673 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4674 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4681 let Inst{28-24} = 0b01110;
4682 let Inst{23-22} = size;
4683 let Inst{21-17} = 0b10000;
4684 let Inst{16-12} = opcode;
4685 let Inst{11-10} = 0b10;
4690 // Comparisons support all element sizes, except 1xD.
4691 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4693 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4695 v8i8, v8i8, OpNode>;
4696 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4698 v16i8, v16i8, OpNode>;
4699 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4701 v4i16, v4i16, OpNode>;
4702 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4704 v8i16, v8i16, OpNode>;
4705 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4707 v2i32, v2i32, OpNode>;
4708 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4710 v4i32, v4i32, OpNode>;
4711 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4713 v2i64, v2i64, OpNode>;
4716 // FP Comparisons support only S and D element sizes.
4717 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4718 string asm, SDNode OpNode> {
4720 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4722 v2i32, v2f32, OpNode>;
4723 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4725 v4i32, v4f32, OpNode>;
4726 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4728 v2i64, v2f64, OpNode>;
4730 def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
4731 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4732 def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
4733 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4734 def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
4735 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4736 def : InstAlias<asm # ".2s $Vd, $Vn, #0",
4737 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4738 def : InstAlias<asm # ".4s $Vd, $Vn, #0",
4739 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4740 def : InstAlias<asm # ".2d $Vd, $Vn, #0",
4741 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4744 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4745 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4746 RegisterOperand outtype, RegisterOperand intype,
4747 string asm, string VdTy, string VnTy,
4749 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4750 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4757 let Inst{28-24} = 0b01110;
4758 let Inst{23-22} = size;
4759 let Inst{21-17} = 0b10000;
4760 let Inst{16-12} = opcode;
4761 let Inst{11-10} = 0b10;
4766 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4767 RegisterOperand outtype, RegisterOperand intype,
4768 string asm, string VdTy, string VnTy,
4770 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4771 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4778 let Inst{28-24} = 0b01110;
4779 let Inst{23-22} = size;
4780 let Inst{21-17} = 0b10000;
4781 let Inst{16-12} = opcode;
4782 let Inst{11-10} = 0b10;
4787 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4788 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4789 asm, ".4s", ".4h", []>;
4790 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4791 asm#"2", ".4s", ".8h", []>;
4792 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4793 asm, ".2d", ".2s", []>;
4794 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4795 asm#"2", ".2d", ".4s", []>;
4798 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4799 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4800 asm, ".4h", ".4s", []>;
4801 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4802 asm#"2", ".8h", ".4s", []>;
4803 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4804 asm, ".2s", ".2d", []>;
4805 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4806 asm#"2", ".4s", ".2d", []>;
4809 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4811 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4813 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4814 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4815 asm#"2", ".4s", ".2d", []>;
4817 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4818 (!cast<Instruction>(NAME # "v4f32")
4819 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4822 //----------------------------------------------------------------------------
4823 // AdvSIMD three register different-size vector instructions.
4824 //----------------------------------------------------------------------------
4826 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4827 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4828 RegisterOperand outtype, RegisterOperand intype1,
4829 RegisterOperand intype2, string asm,
4830 string outkind, string inkind1, string inkind2,
4832 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4833 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4834 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4840 let Inst{30} = size{0};
4842 let Inst{28-24} = 0b01110;
4843 let Inst{23-22} = size{2-1};
4845 let Inst{20-16} = Rm;
4846 let Inst{15-12} = opcode;
4847 let Inst{11-10} = 0b00;
4852 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4853 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4854 RegisterOperand outtype, RegisterOperand intype1,
4855 RegisterOperand intype2, string asm,
4856 string outkind, string inkind1, string inkind2,
4858 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4859 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4860 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4866 let Inst{30} = size{0};
4868 let Inst{28-24} = 0b01110;
4869 let Inst{23-22} = size{2-1};
4871 let Inst{20-16} = Rm;
4872 let Inst{15-12} = opcode;
4873 let Inst{11-10} = 0b00;
4878 // FIXME: TableGen doesn't know how to deal with expanded types that also
4879 // change the element count (in this case, placing the results in
4880 // the high elements of the result register rather than the low
4881 // elements). Until that's fixed, we can't code-gen those.
4882 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4884 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4886 asm, ".8b", ".8h", ".8h",
4887 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4888 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4890 asm#"2", ".16b", ".8h", ".8h",
4892 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4894 asm, ".4h", ".4s", ".4s",
4895 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4896 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4898 asm#"2", ".8h", ".4s", ".4s",
4900 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4902 asm, ".2s", ".2d", ".2d",
4903 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4904 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4906 asm#"2", ".4s", ".2d", ".2d",
4910 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4911 // a version attached to an instruction.
4912 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4914 (!cast<Instruction>(NAME # "v8i16_v16i8")
4915 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4916 V128:$Rn, V128:$Rm)>;
4917 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4919 (!cast<Instruction>(NAME # "v4i32_v8i16")
4920 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4921 V128:$Rn, V128:$Rm)>;
4922 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4924 (!cast<Instruction>(NAME # "v2i64_v4i32")
4925 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4926 V128:$Rn, V128:$Rm)>;
4929 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
4931 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4933 asm, ".8h", ".8b", ".8b",
4934 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4935 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4937 asm#"2", ".8h", ".16b", ".16b", []>;
4938 let Predicates = [HasCrypto] in {
4939 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
4941 asm, ".1q", ".1d", ".1d", []>;
4942 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
4944 asm#"2", ".1q", ".2d", ".2d", []>;
4947 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4948 (v8i8 (extract_high_v16i8 V128:$Rm)))),
4949 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4952 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
4953 SDPatternOperator OpNode> {
4954 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4956 asm, ".4s", ".4h", ".4h",
4957 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4958 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4960 asm#"2", ".4s", ".8h", ".8h",
4961 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4962 (extract_high_v8i16 V128:$Rm)))]>;
4963 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4965 asm, ".2d", ".2s", ".2s",
4966 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4967 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4969 asm#"2", ".2d", ".4s", ".4s",
4970 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4971 (extract_high_v4i32 V128:$Rm)))]>;
4974 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
4975 SDPatternOperator OpNode = null_frag> {
4976 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4978 asm, ".8h", ".8b", ".8b",
4979 [(set (v8i16 V128:$Rd),
4980 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4981 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4983 asm#"2", ".8h", ".16b", ".16b",
4984 [(set (v8i16 V128:$Rd),
4985 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4986 (extract_high_v16i8 V128:$Rm)))))]>;
4987 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4989 asm, ".4s", ".4h", ".4h",
4990 [(set (v4i32 V128:$Rd),
4991 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
4992 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4994 asm#"2", ".4s", ".8h", ".8h",
4995 [(set (v4i32 V128:$Rd),
4996 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4997 (extract_high_v8i16 V128:$Rm)))))]>;
4998 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5000 asm, ".2d", ".2s", ".2s",
5001 [(set (v2i64 V128:$Rd),
5002 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
5003 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5005 asm#"2", ".2d", ".4s", ".4s",
5006 [(set (v2i64 V128:$Rd),
5007 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5008 (extract_high_v4i32 V128:$Rm)))))]>;
5011 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
5013 SDPatternOperator OpNode> {
5014 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5016 asm, ".8h", ".8b", ".8b",
5017 [(set (v8i16 V128:$dst),
5018 (add (v8i16 V128:$Rd),
5019 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
5020 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5022 asm#"2", ".8h", ".16b", ".16b",
5023 [(set (v8i16 V128:$dst),
5024 (add (v8i16 V128:$Rd),
5025 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5026 (extract_high_v16i8 V128:$Rm))))))]>;
5027 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5029 asm, ".4s", ".4h", ".4h",
5030 [(set (v4i32 V128:$dst),
5031 (add (v4i32 V128:$Rd),
5032 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
5033 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5035 asm#"2", ".4s", ".8h", ".8h",
5036 [(set (v4i32 V128:$dst),
5037 (add (v4i32 V128:$Rd),
5038 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5039 (extract_high_v8i16 V128:$Rm))))))]>;
5040 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5042 asm, ".2d", ".2s", ".2s",
5043 [(set (v2i64 V128:$dst),
5044 (add (v2i64 V128:$Rd),
5045 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
5046 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5048 asm#"2", ".2d", ".4s", ".4s",
5049 [(set (v2i64 V128:$dst),
5050 (add (v2i64 V128:$Rd),
5051 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5052 (extract_high_v4i32 V128:$Rm))))))]>;
5055 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
5056 SDPatternOperator OpNode = null_frag> {
5057 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5059 asm, ".8h", ".8b", ".8b",
5060 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5061 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5063 asm#"2", ".8h", ".16b", ".16b",
5064 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5065 (extract_high_v16i8 V128:$Rm)))]>;
5066 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5068 asm, ".4s", ".4h", ".4h",
5069 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5070 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5072 asm#"2", ".4s", ".8h", ".8h",
5073 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5074 (extract_high_v8i16 V128:$Rm)))]>;
5075 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5077 asm, ".2d", ".2s", ".2s",
5078 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5079 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5081 asm#"2", ".2d", ".4s", ".4s",
5082 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5083 (extract_high_v4i32 V128:$Rm)))]>;
5086 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5088 SDPatternOperator OpNode> {
5089 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5091 asm, ".8h", ".8b", ".8b",
5092 [(set (v8i16 V128:$dst),
5093 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5094 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5096 asm#"2", ".8h", ".16b", ".16b",
5097 [(set (v8i16 V128:$dst),
5098 (OpNode (v8i16 V128:$Rd),
5099 (extract_high_v16i8 V128:$Rn),
5100 (extract_high_v16i8 V128:$Rm)))]>;
5101 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5103 asm, ".4s", ".4h", ".4h",
5104 [(set (v4i32 V128:$dst),
5105 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5106 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5108 asm#"2", ".4s", ".8h", ".8h",
5109 [(set (v4i32 V128:$dst),
5110 (OpNode (v4i32 V128:$Rd),
5111 (extract_high_v8i16 V128:$Rn),
5112 (extract_high_v8i16 V128:$Rm)))]>;
5113 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5115 asm, ".2d", ".2s", ".2s",
5116 [(set (v2i64 V128:$dst),
5117 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5118 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5120 asm#"2", ".2d", ".4s", ".4s",
5121 [(set (v2i64 V128:$dst),
5122 (OpNode (v2i64 V128:$Rd),
5123 (extract_high_v4i32 V128:$Rn),
5124 (extract_high_v4i32 V128:$Rm)))]>;
5127 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5128 SDPatternOperator Accum> {
5129 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5131 asm, ".4s", ".4h", ".4h",
5132 [(set (v4i32 V128:$dst),
5133 (Accum (v4i32 V128:$Rd),
5134 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5135 (v4i16 V64:$Rm)))))]>;
5136 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5138 asm#"2", ".4s", ".8h", ".8h",
5139 [(set (v4i32 V128:$dst),
5140 (Accum (v4i32 V128:$Rd),
5141 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5142 (extract_high_v8i16 V128:$Rm)))))]>;
5143 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5145 asm, ".2d", ".2s", ".2s",
5146 [(set (v2i64 V128:$dst),
5147 (Accum (v2i64 V128:$Rd),
5148 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5149 (v2i32 V64:$Rm)))))]>;
5150 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5152 asm#"2", ".2d", ".4s", ".4s",
5153 [(set (v2i64 V128:$dst),
5154 (Accum (v2i64 V128:$Rd),
5155 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5156 (extract_high_v4i32 V128:$Rm)))))]>;
5159 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5160 SDPatternOperator OpNode> {
5161 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5163 asm, ".8h", ".8h", ".8b",
5164 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5165 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5167 asm#"2", ".8h", ".8h", ".16b",
5168 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5169 (extract_high_v16i8 V128:$Rm)))]>;
5170 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5172 asm, ".4s", ".4s", ".4h",
5173 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5174 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5176 asm#"2", ".4s", ".4s", ".8h",
5177 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5178 (extract_high_v8i16 V128:$Rm)))]>;
5179 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5181 asm, ".2d", ".2d", ".2s",
5182 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5183 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5185 asm#"2", ".2d", ".2d", ".4s",
5186 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5187 (extract_high_v4i32 V128:$Rm)))]>;
5190 //----------------------------------------------------------------------------
5191 // AdvSIMD bitwise extract from vector
5192 //----------------------------------------------------------------------------
5194 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5195 string asm, string kind>
5196 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5197 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5198 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5199 [(set (vty regtype:$Rd),
5200 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5207 let Inst{30} = size;
5208 let Inst{29-21} = 0b101110000;
5209 let Inst{20-16} = Rm;
5211 let Inst{14-11} = imm;
5218 multiclass SIMDBitwiseExtract<string asm> {
5219 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5222 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5225 //----------------------------------------------------------------------------
5226 // AdvSIMD zip vector
5227 //----------------------------------------------------------------------------
5229 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5230 string asm, string kind, SDNode OpNode, ValueType valty>
5231 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5232 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5233 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5234 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5240 let Inst{30} = size{0};
5241 let Inst{29-24} = 0b001110;
5242 let Inst{23-22} = size{2-1};
5244 let Inst{20-16} = Rm;
5246 let Inst{14-12} = opc;
5247 let Inst{11-10} = 0b10;
5252 multiclass SIMDZipVector<bits<3>opc, string asm,
5254 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5255 asm, ".8b", OpNode, v8i8>;
5256 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5257 asm, ".16b", OpNode, v16i8>;
5258 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5259 asm, ".4h", OpNode, v4i16>;
5260 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5261 asm, ".8h", OpNode, v8i16>;
5262 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5263 asm, ".2s", OpNode, v2i32>;
5264 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5265 asm, ".4s", OpNode, v4i32>;
5266 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5267 asm, ".2d", OpNode, v2i64>;
5269 def : Pat<(v4f16 (OpNode V64:$Rn, V64:$Rm)),
5270 (!cast<Instruction>(NAME#"v4i16") V64:$Rn, V64:$Rm)>;
5271 def : Pat<(v8f16 (OpNode V128:$Rn, V128:$Rm)),
5272 (!cast<Instruction>(NAME#"v8i16") V128:$Rn, V128:$Rm)>;
5273 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5274 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5275 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5276 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5277 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5278 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5281 //----------------------------------------------------------------------------
5282 // AdvSIMD three register scalar instructions
5283 //----------------------------------------------------------------------------
5285 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5286 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5287 RegisterClass regtype, string asm,
5289 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5290 "\t$Rd, $Rn, $Rm", "", pattern>,
5295 let Inst{31-30} = 0b01;
5297 let Inst{28-24} = 0b11110;
5298 let Inst{23-22} = size;
5300 let Inst{20-16} = Rm;
5301 let Inst{15-11} = opcode;
5307 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5308 class BaseSIMDThreeScalarTied<bit U, bits<2> size, bit R, bits<5> opcode,
5309 dag oops, dag iops, string asm,
5311 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
5316 let Inst{31-30} = 0b01;
5318 let Inst{28-24} = 0b11110;
5319 let Inst{23-22} = size;
5321 let Inst{20-16} = Rm;
5322 let Inst{15-11} = opcode;
5328 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5329 SDPatternOperator OpNode> {
5330 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5331 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5334 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5335 SDPatternOperator OpNode> {
5336 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5337 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5338 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5339 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5340 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5342 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5343 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5344 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5345 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5348 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5349 SDPatternOperator OpNode> {
5350 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5351 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5352 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5355 multiclass SIMDThreeScalarHSTied<bit U, bit R, bits<5> opc, string asm,
5356 SDPatternOperator OpNode = null_frag> {
5357 def v1i32: BaseSIMDThreeScalarTied<U, 0b10, R, opc, (outs FPR32:$dst),
5358 (ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
5360 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
5361 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
5365 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5366 SDPatternOperator OpNode = null_frag> {
5367 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5368 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5369 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5370 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5371 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5374 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5375 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5378 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5379 SDPatternOperator OpNode = null_frag> {
5380 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5381 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5382 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5383 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5384 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5387 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5388 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5391 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5392 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5393 : I<oops, iops, asm,
5394 "\t$Rd, $Rn, $Rm", cstr, pat>,
5399 let Inst{31-30} = 0b01;
5401 let Inst{28-24} = 0b11110;
5402 let Inst{23-22} = size;
5404 let Inst{20-16} = Rm;
5405 let Inst{15-11} = opcode;
5411 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5412 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5413 SDPatternOperator OpNode = null_frag> {
5414 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5416 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5417 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5419 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5420 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5423 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5424 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5425 SDPatternOperator OpNode = null_frag> {
5426 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5428 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5429 asm, "$Rd = $dst", []>;
5430 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5432 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5434 [(set (i64 FPR64:$dst),
5435 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5438 //----------------------------------------------------------------------------
5439 // AdvSIMD two register scalar instructions
5440 //----------------------------------------------------------------------------
5442 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5443 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5444 RegisterClass regtype, RegisterClass regtype2,
5445 string asm, list<dag> pat>
5446 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5447 "\t$Rd, $Rn", "", pat>,
5451 let Inst{31-30} = 0b01;
5453 let Inst{28-24} = 0b11110;
5454 let Inst{23-22} = size;
5455 let Inst{21-17} = 0b10000;
5456 let Inst{16-12} = opcode;
5457 let Inst{11-10} = 0b10;
5462 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5463 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5464 RegisterClass regtype, RegisterClass regtype2,
5465 string asm, list<dag> pat>
5466 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5467 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5471 let Inst{31-30} = 0b01;
5473 let Inst{28-24} = 0b11110;
5474 let Inst{23-22} = size;
5475 let Inst{21-17} = 0b10000;
5476 let Inst{16-12} = opcode;
5477 let Inst{11-10} = 0b10;
5483 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5484 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5485 RegisterClass regtype, string asm, string zero>
5486 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5487 "\t$Rd, $Rn, #" # zero, "", []>,
5491 let Inst{31-30} = 0b01;
5493 let Inst{28-24} = 0b11110;
5494 let Inst{23-22} = size;
5495 let Inst{21-17} = 0b10000;
5496 let Inst{16-12} = opcode;
5497 let Inst{11-10} = 0b10;
5502 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5503 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5504 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5508 let Inst{31-17} = 0b011111100110000;
5509 let Inst{16-12} = opcode;
5510 let Inst{11-10} = 0b10;
5515 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5516 SDPatternOperator OpNode> {
5517 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5519 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5520 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5523 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
5524 SDPatternOperator OpNode> {
5525 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5526 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5528 def : InstAlias<asm # " $Rd, $Rn, #0",
5529 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5530 def : InstAlias<asm # " $Rd, $Rn, #0",
5531 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5533 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5534 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5537 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5538 SDPatternOperator OpNode = null_frag> {
5539 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5540 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5542 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5543 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5546 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {
5547 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5548 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5551 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5552 SDPatternOperator OpNode> {
5553 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5554 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5555 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5556 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5559 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5560 SDPatternOperator OpNode = null_frag> {
5561 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5562 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5563 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5564 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5565 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5566 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5567 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5570 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5571 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5574 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5576 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5577 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5578 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5579 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5580 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5581 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5582 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5585 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5586 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5591 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5592 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5593 SDPatternOperator OpNode = null_frag> {
5594 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5595 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5596 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5597 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5600 //----------------------------------------------------------------------------
5601 // AdvSIMD scalar pairwise instructions
5602 //----------------------------------------------------------------------------
5604 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5605 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5606 RegisterOperand regtype, RegisterOperand vectype,
5607 string asm, string kind>
5608 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5609 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5613 let Inst{31-30} = 0b01;
5615 let Inst{28-24} = 0b11110;
5616 let Inst{23-22} = size;
5617 let Inst{21-17} = 0b11000;
5618 let Inst{16-12} = opcode;
5619 let Inst{11-10} = 0b10;
5624 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5625 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5629 multiclass SIMDPairwiseScalarSD<bit U, bit S, bits<5> opc, string asm> {
5630 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5632 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5636 //----------------------------------------------------------------------------
5637 // AdvSIMD across lanes instructions
5638 //----------------------------------------------------------------------------
5640 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5641 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5642 RegisterClass regtype, RegisterOperand vectype,
5643 string asm, string kind, list<dag> pattern>
5644 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5645 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5652 let Inst{28-24} = 0b01110;
5653 let Inst{23-22} = size;
5654 let Inst{21-17} = 0b11000;
5655 let Inst{16-12} = opcode;
5656 let Inst{11-10} = 0b10;
5661 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5663 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5665 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5667 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5669 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5671 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5675 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5676 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5678 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5680 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5682 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5684 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5688 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5690 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5692 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5695 //----------------------------------------------------------------------------
5696 // AdvSIMD INS/DUP instructions
5697 //----------------------------------------------------------------------------
5699 // FIXME: There has got to be a better way to factor these. ugh.
5701 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5702 string operands, string constraints, list<dag> pattern>
5703 : I<outs, ins, asm, operands, constraints, pattern>,
5710 let Inst{28-21} = 0b01110000;
5717 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5718 RegisterOperand vecreg, RegisterClass regtype>
5719 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5720 "{\t$Rd" # size # ", $Rn" #
5721 "|" # size # "\t$Rd, $Rn}", "",
5722 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
5723 let Inst{20-16} = imm5;
5724 let Inst{14-11} = 0b0001;
5727 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5728 ValueType vectype, ValueType insreg,
5729 RegisterOperand vecreg, Operand idxtype,
5730 ValueType elttype, SDNode OpNode>
5731 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5732 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5733 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5734 [(set (vectype vecreg:$Rd),
5735 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5736 let Inst{14-11} = 0b0000;
5739 class SIMDDup64FromElement
5740 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5741 VectorIndexD, i64, AArch64duplane64> {
5744 let Inst{19-16} = 0b1000;
5747 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5748 RegisterOperand vecreg>
5749 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5750 VectorIndexS, i64, AArch64duplane32> {
5752 let Inst{20-19} = idx;
5753 let Inst{18-16} = 0b100;
5756 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5757 RegisterOperand vecreg>
5758 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5759 VectorIndexH, i64, AArch64duplane16> {
5761 let Inst{20-18} = idx;
5762 let Inst{17-16} = 0b10;
5765 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5766 RegisterOperand vecreg>
5767 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5768 VectorIndexB, i64, AArch64duplane8> {
5770 let Inst{20-17} = idx;
5774 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5775 Operand idxtype, string asm, list<dag> pattern>
5776 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5777 "{\t$Rd, $Rn" # size # "$idx" #
5778 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5779 let Inst{14-11} = imm4;
5782 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5784 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5785 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5787 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5788 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5790 class SIMDMovAlias<string asm, string size, Instruction inst,
5791 RegisterClass regtype, Operand idxtype>
5792 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5793 "|" # size # "\t$dst, $src$idx}",
5794 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5797 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5799 let Inst{20-17} = idx;
5802 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5804 let Inst{20-17} = idx;
5807 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5809 let Inst{20-18} = idx;
5810 let Inst{17-16} = 0b10;
5812 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5814 let Inst{20-18} = idx;
5815 let Inst{17-16} = 0b10;
5817 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5819 let Inst{20-19} = idx;
5820 let Inst{18-16} = 0b100;
5825 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5827 let Inst{20-17} = idx;
5830 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5832 let Inst{20-18} = idx;
5833 let Inst{17-16} = 0b10;
5835 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5837 let Inst{20-19} = idx;
5838 let Inst{18-16} = 0b100;
5840 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5843 let Inst{19-16} = 0b1000;
5845 def : SIMDMovAlias<"mov", ".s",
5846 !cast<Instruction>(NAME#"vi32"),
5847 GPR32, VectorIndexS>;
5848 def : SIMDMovAlias<"mov", ".d",
5849 !cast<Instruction>(NAME#"vi64"),
5850 GPR64, VectorIndexD>;
5853 class SIMDInsFromMain<string size, ValueType vectype,
5854 RegisterClass regtype, Operand idxtype>
5855 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5856 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5857 "{\t$Rd" # size # "$idx, $Rn" #
5858 "|" # size # "\t$Rd$idx, $Rn}",
5861 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5862 let Inst{14-11} = 0b0011;
5865 class SIMDInsFromElement<string size, ValueType vectype,
5866 ValueType elttype, Operand idxtype>
5867 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5868 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5869 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5870 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5875 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5878 class SIMDInsMainMovAlias<string size, Instruction inst,
5879 RegisterClass regtype, Operand idxtype>
5880 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5881 "|" # size #"\t$dst$idx, $src}",
5882 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5883 class SIMDInsElementMovAlias<string size, Instruction inst,
5885 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5886 # "|" # size #" $dst$idx, $src$idx2}",
5887 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5890 multiclass SIMDIns {
5891 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5893 let Inst{20-17} = idx;
5896 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5898 let Inst{20-18} = idx;
5899 let Inst{17-16} = 0b10;
5901 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5903 let Inst{20-19} = idx;
5904 let Inst{18-16} = 0b100;
5906 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5909 let Inst{19-16} = 0b1000;
5912 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5915 let Inst{20-17} = idx;
5917 let Inst{14-11} = idx2;
5919 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5922 let Inst{20-18} = idx;
5923 let Inst{17-16} = 0b10;
5924 let Inst{14-12} = idx2;
5927 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
5930 let Inst{20-19} = idx;
5931 let Inst{18-16} = 0b100;
5932 let Inst{14-13} = idx2;
5933 let Inst{12-11} = {?,?};
5935 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
5939 let Inst{19-16} = 0b1000;
5940 let Inst{14} = idx2;
5941 let Inst{13-11} = {?,?,?};
5944 // For all forms of the INS instruction, the "mov" mnemonic is the
5945 // preferred alias. Why they didn't just call the instruction "mov" in
5946 // the first place is a very good question indeed...
5947 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
5948 GPR32, VectorIndexB>;
5949 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
5950 GPR32, VectorIndexH>;
5951 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
5952 GPR32, VectorIndexS>;
5953 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
5954 GPR64, VectorIndexD>;
5956 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
5958 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
5960 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
5962 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
5966 //----------------------------------------------------------------------------
5968 //----------------------------------------------------------------------------
5970 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5971 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5972 RegisterOperand listtype, string asm, string kind>
5973 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
5974 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
5981 let Inst{29-21} = 0b001110000;
5982 let Inst{20-16} = Vm;
5984 let Inst{14-13} = len;
5986 let Inst{11-10} = 0b00;
5991 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5992 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5993 RegisterOperand listtype, string asm, string kind>
5994 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
5995 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
6002 let Inst{29-21} = 0b001110000;
6003 let Inst{20-16} = Vm;
6005 let Inst{14-13} = len;
6007 let Inst{11-10} = 0b00;
6012 class SIMDTableLookupAlias<string asm, Instruction inst,
6013 RegisterOperand vectype, RegisterOperand listtype>
6014 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
6015 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
6017 multiclass SIMDTableLookup<bit op, string asm> {
6018 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
6020 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
6022 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
6024 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
6026 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
6028 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
6030 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
6032 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
6035 def : SIMDTableLookupAlias<asm # ".8b",
6036 !cast<Instruction>(NAME#"v8i8One"),
6037 V64, VecListOne128>;
6038 def : SIMDTableLookupAlias<asm # ".8b",
6039 !cast<Instruction>(NAME#"v8i8Two"),
6040 V64, VecListTwo128>;
6041 def : SIMDTableLookupAlias<asm # ".8b",
6042 !cast<Instruction>(NAME#"v8i8Three"),
6043 V64, VecListThree128>;
6044 def : SIMDTableLookupAlias<asm # ".8b",
6045 !cast<Instruction>(NAME#"v8i8Four"),
6046 V64, VecListFour128>;
6047 def : SIMDTableLookupAlias<asm # ".16b",
6048 !cast<Instruction>(NAME#"v16i8One"),
6049 V128, VecListOne128>;
6050 def : SIMDTableLookupAlias<asm # ".16b",
6051 !cast<Instruction>(NAME#"v16i8Two"),
6052 V128, VecListTwo128>;
6053 def : SIMDTableLookupAlias<asm # ".16b",
6054 !cast<Instruction>(NAME#"v16i8Three"),
6055 V128, VecListThree128>;
6056 def : SIMDTableLookupAlias<asm # ".16b",
6057 !cast<Instruction>(NAME#"v16i8Four"),
6058 V128, VecListFour128>;
6061 multiclass SIMDTableLookupTied<bit op, string asm> {
6062 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
6064 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
6066 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
6068 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
6070 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
6072 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
6074 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
6076 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
6079 def : SIMDTableLookupAlias<asm # ".8b",
6080 !cast<Instruction>(NAME#"v8i8One"),
6081 V64, VecListOne128>;
6082 def : SIMDTableLookupAlias<asm # ".8b",
6083 !cast<Instruction>(NAME#"v8i8Two"),
6084 V64, VecListTwo128>;
6085 def : SIMDTableLookupAlias<asm # ".8b",
6086 !cast<Instruction>(NAME#"v8i8Three"),
6087 V64, VecListThree128>;
6088 def : SIMDTableLookupAlias<asm # ".8b",
6089 !cast<Instruction>(NAME#"v8i8Four"),
6090 V64, VecListFour128>;
6091 def : SIMDTableLookupAlias<asm # ".16b",
6092 !cast<Instruction>(NAME#"v16i8One"),
6093 V128, VecListOne128>;
6094 def : SIMDTableLookupAlias<asm # ".16b",
6095 !cast<Instruction>(NAME#"v16i8Two"),
6096 V128, VecListTwo128>;
6097 def : SIMDTableLookupAlias<asm # ".16b",
6098 !cast<Instruction>(NAME#"v16i8Three"),
6099 V128, VecListThree128>;
6100 def : SIMDTableLookupAlias<asm # ".16b",
6101 !cast<Instruction>(NAME#"v16i8Four"),
6102 V128, VecListFour128>;
6106 //----------------------------------------------------------------------------
6107 // AdvSIMD scalar CPY
6108 //----------------------------------------------------------------------------
6109 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6110 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
6111 string kind, Operand idxtype>
6112 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
6113 "{\t$dst, $src" # kind # "$idx" #
6114 "|\t$dst, $src$idx}", "", []>,
6118 let Inst{31-21} = 0b01011110000;
6119 let Inst{15-10} = 0b000001;
6120 let Inst{9-5} = src;
6121 let Inst{4-0} = dst;
6124 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
6125 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
6126 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
6127 # "|\t$dst, $src$index}",
6128 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
6131 multiclass SIMDScalarCPY<string asm> {
6132 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6134 let Inst{20-17} = idx;
6137 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6139 let Inst{20-18} = idx;
6140 let Inst{17-16} = 0b10;
6142 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6144 let Inst{20-19} = idx;
6145 let Inst{18-16} = 0b100;
6147 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6150 let Inst{19-16} = 0b1000;
6153 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6154 VectorIndexD:$idx)))),
6155 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6157 // 'DUP' mnemonic aliases.
6158 def : SIMDScalarCPYAlias<"dup", ".b",
6159 !cast<Instruction>(NAME#"i8"),
6160 FPR8, V128, VectorIndexB>;
6161 def : SIMDScalarCPYAlias<"dup", ".h",
6162 !cast<Instruction>(NAME#"i16"),
6163 FPR16, V128, VectorIndexH>;
6164 def : SIMDScalarCPYAlias<"dup", ".s",
6165 !cast<Instruction>(NAME#"i32"),
6166 FPR32, V128, VectorIndexS>;
6167 def : SIMDScalarCPYAlias<"dup", ".d",
6168 !cast<Instruction>(NAME#"i64"),
6169 FPR64, V128, VectorIndexD>;
6172 //----------------------------------------------------------------------------
6173 // AdvSIMD modified immediate instructions
6174 //----------------------------------------------------------------------------
6176 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
6177 string asm, string op_string,
6178 string cstr, list<dag> pattern>
6179 : I<oops, iops, asm, op_string, cstr, pattern>,
6186 let Inst{28-19} = 0b0111100000;
6187 let Inst{18-16} = imm8{7-5};
6188 let Inst{11-10} = 0b01;
6189 let Inst{9-5} = imm8{4-0};
6193 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
6194 Operand immtype, dag opt_shift_iop,
6195 string opt_shift, string asm, string kind,
6197 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
6198 !con((ins immtype:$imm8), opt_shift_iop), asm,
6199 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6200 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6202 let DecoderMethod = "DecodeModImmInstruction";
6205 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
6206 Operand immtype, dag opt_shift_iop,
6207 string opt_shift, string asm, string kind,
6209 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
6210 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6211 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6212 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6213 "$Rd = $dst", pattern> {
6214 let DecoderMethod = "DecodeModImmTiedInstruction";
6217 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6218 RegisterOperand vectype, string asm,
6219 string kind, list<dag> pattern>
6220 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6221 (ins logical_vec_shift:$shift),
6222 "$shift", asm, kind, pattern> {
6224 let Inst{15} = b15_b12{1};
6225 let Inst{14-13} = shift;
6226 let Inst{12} = b15_b12{0};
6229 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6230 RegisterOperand vectype, string asm,
6231 string kind, list<dag> pattern>
6232 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6233 (ins logical_vec_shift:$shift),
6234 "$shift", asm, kind, pattern> {
6236 let Inst{15} = b15_b12{1};
6237 let Inst{14-13} = shift;
6238 let Inst{12} = b15_b12{0};
6242 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6243 RegisterOperand vectype, string asm,
6244 string kind, list<dag> pattern>
6245 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6246 (ins logical_vec_hw_shift:$shift),
6247 "$shift", asm, kind, pattern> {
6249 let Inst{15} = b15_b12{1};
6251 let Inst{13} = shift{0};
6252 let Inst{12} = b15_b12{0};
6255 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6256 RegisterOperand vectype, string asm,
6257 string kind, list<dag> pattern>
6258 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6259 (ins logical_vec_hw_shift:$shift),
6260 "$shift", asm, kind, pattern> {
6262 let Inst{15} = b15_b12{1};
6264 let Inst{13} = shift{0};
6265 let Inst{12} = b15_b12{0};
6268 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6270 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6272 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6275 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6277 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6281 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6282 bits<2> w_cmode, string asm,
6284 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6286 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6288 (i32 imm:$shift)))]>;
6289 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6291 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6293 (i32 imm:$shift)))]>;
6295 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6297 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6299 (i32 imm:$shift)))]>;
6300 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6302 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6304 (i32 imm:$shift)))]>;
6307 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6308 RegisterOperand vectype, string asm,
6309 string kind, list<dag> pattern>
6310 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6311 (ins move_vec_shift:$shift),
6312 "$shift", asm, kind, pattern> {
6314 let Inst{15-13} = cmode{3-1};
6315 let Inst{12} = shift;
6318 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6319 RegisterOperand vectype,
6320 Operand imm_type, string asm,
6321 string kind, list<dag> pattern>
6322 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6323 asm, kind, pattern> {
6324 let Inst{15-12} = cmode;
6327 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6329 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6330 "\t$Rd, $imm8", "", pattern> {
6331 let Inst{15-12} = cmode;
6332 let DecoderMethod = "DecodeModImmInstruction";
6335 //----------------------------------------------------------------------------
6336 // AdvSIMD indexed element
6337 //----------------------------------------------------------------------------
6339 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6340 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6341 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6342 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6343 string apple_kind, string dst_kind, string lhs_kind,
6344 string rhs_kind, list<dag> pattern>
6345 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6347 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6348 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6357 let Inst{28} = Scalar;
6358 let Inst{27-24} = 0b1111;
6359 let Inst{23-22} = size;
6360 // Bit 21 must be set by the derived class.
6361 let Inst{20-16} = Rm;
6362 let Inst{15-12} = opc;
6363 // Bit 11 must be set by the derived class.
6369 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6370 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6371 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6372 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6373 string apple_kind, string dst_kind, string lhs_kind,
6374 string rhs_kind, list<dag> pattern>
6375 : I<(outs dst_reg:$dst),
6376 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6377 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6378 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6387 let Inst{28} = Scalar;
6388 let Inst{27-24} = 0b1111;
6389 let Inst{23-22} = size;
6390 // Bit 21 must be set by the derived class.
6391 let Inst{20-16} = Rm;
6392 let Inst{15-12} = opc;
6393 // Bit 11 must be set by the derived class.
6399 multiclass SIMDFPIndexedSD<bit U, bits<4> opc, string asm,
6400 SDPatternOperator OpNode> {
6401 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6404 asm, ".2s", ".2s", ".2s", ".s",
6405 [(set (v2f32 V64:$Rd),
6406 (OpNode (v2f32 V64:$Rn),
6407 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6409 let Inst{11} = idx{1};
6410 let Inst{21} = idx{0};
6413 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6416 asm, ".4s", ".4s", ".4s", ".s",
6417 [(set (v4f32 V128:$Rd),
6418 (OpNode (v4f32 V128:$Rn),
6419 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6421 let Inst{11} = idx{1};
6422 let Inst{21} = idx{0};
6425 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6428 asm, ".2d", ".2d", ".2d", ".d",
6429 [(set (v2f64 V128:$Rd),
6430 (OpNode (v2f64 V128:$Rn),
6431 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6433 let Inst{11} = idx{0};
6437 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6438 FPR32Op, FPR32Op, V128, VectorIndexS,
6439 asm, ".s", "", "", ".s",
6440 [(set (f32 FPR32Op:$Rd),
6441 (OpNode (f32 FPR32Op:$Rn),
6442 (f32 (vector_extract (v4f32 V128:$Rm),
6443 VectorIndexS:$idx))))]> {
6445 let Inst{11} = idx{1};
6446 let Inst{21} = idx{0};
6449 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6450 FPR64Op, FPR64Op, V128, VectorIndexD,
6451 asm, ".d", "", "", ".d",
6452 [(set (f64 FPR64Op:$Rd),
6453 (OpNode (f64 FPR64Op:$Rn),
6454 (f64 (vector_extract (v2f64 V128:$Rm),
6455 VectorIndexD:$idx))))]> {
6457 let Inst{11} = idx{0};
6462 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6463 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6464 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6465 (AArch64duplane32 (v4f32 V128:$Rm),
6466 VectorIndexS:$idx))),
6467 (!cast<Instruction>(INST # v2i32_indexed)
6468 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6469 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6470 (AArch64dup (f32 FPR32Op:$Rm)))),
6471 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6472 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6475 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6476 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6477 (AArch64duplane32 (v4f32 V128:$Rm),
6478 VectorIndexS:$idx))),
6479 (!cast<Instruction>(INST # "v4i32_indexed")
6480 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6481 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6482 (AArch64dup (f32 FPR32Op:$Rm)))),
6483 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6484 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6486 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6487 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6488 (AArch64duplane64 (v2f64 V128:$Rm),
6489 VectorIndexD:$idx))),
6490 (!cast<Instruction>(INST # "v2i64_indexed")
6491 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6492 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6493 (AArch64dup (f64 FPR64Op:$Rm)))),
6494 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6495 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6497 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6498 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6499 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6500 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6501 V128:$Rm, VectorIndexS:$idx)>;
6502 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6503 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6504 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6505 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6507 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6508 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6509 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6510 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6511 V128:$Rm, VectorIndexD:$idx)>;
6514 multiclass SIMDFPIndexedSDTied<bit U, bits<4> opc, string asm> {
6515 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6517 asm, ".2s", ".2s", ".2s", ".s", []> {
6519 let Inst{11} = idx{1};
6520 let Inst{21} = idx{0};
6523 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6526 asm, ".4s", ".4s", ".4s", ".s", []> {
6528 let Inst{11} = idx{1};
6529 let Inst{21} = idx{0};
6532 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6535 asm, ".2d", ".2d", ".2d", ".d", []> {
6537 let Inst{11} = idx{0};
6542 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6543 FPR32Op, FPR32Op, V128, VectorIndexS,
6544 asm, ".s", "", "", ".s", []> {
6546 let Inst{11} = idx{1};
6547 let Inst{21} = idx{0};
6550 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6551 FPR64Op, FPR64Op, V128, VectorIndexD,
6552 asm, ".d", "", "", ".d", []> {
6554 let Inst{11} = idx{0};
6559 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6560 SDPatternOperator OpNode> {
6561 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6562 V128_lo, VectorIndexH,
6563 asm, ".4h", ".4h", ".4h", ".h",
6564 [(set (v4i16 V64:$Rd),
6565 (OpNode (v4i16 V64:$Rn),
6566 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6568 let Inst{11} = idx{2};
6569 let Inst{21} = idx{1};
6570 let Inst{20} = idx{0};
6573 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6575 V128_lo, VectorIndexH,
6576 asm, ".8h", ".8h", ".8h", ".h",
6577 [(set (v8i16 V128:$Rd),
6578 (OpNode (v8i16 V128:$Rn),
6579 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6581 let Inst{11} = idx{2};
6582 let Inst{21} = idx{1};
6583 let Inst{20} = idx{0};
6586 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6589 asm, ".2s", ".2s", ".2s", ".s",
6590 [(set (v2i32 V64:$Rd),
6591 (OpNode (v2i32 V64:$Rn),
6592 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6594 let Inst{11} = idx{1};
6595 let Inst{21} = idx{0};
6598 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6601 asm, ".4s", ".4s", ".4s", ".s",
6602 [(set (v4i32 V128:$Rd),
6603 (OpNode (v4i32 V128:$Rn),
6604 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6606 let Inst{11} = idx{1};
6607 let Inst{21} = idx{0};
6610 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6611 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6612 asm, ".h", "", "", ".h", []> {
6614 let Inst{11} = idx{2};
6615 let Inst{21} = idx{1};
6616 let Inst{20} = idx{0};
6619 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6620 FPR32Op, FPR32Op, V128, VectorIndexS,
6621 asm, ".s", "", "", ".s",
6622 [(set (i32 FPR32Op:$Rd),
6623 (OpNode FPR32Op:$Rn,
6624 (i32 (vector_extract (v4i32 V128:$Rm),
6625 VectorIndexS:$idx))))]> {
6627 let Inst{11} = idx{1};
6628 let Inst{21} = idx{0};
6632 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6633 SDPatternOperator OpNode> {
6634 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6636 V128_lo, VectorIndexH,
6637 asm, ".4h", ".4h", ".4h", ".h",
6638 [(set (v4i16 V64:$Rd),
6639 (OpNode (v4i16 V64:$Rn),
6640 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6642 let Inst{11} = idx{2};
6643 let Inst{21} = idx{1};
6644 let Inst{20} = idx{0};
6647 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6649 V128_lo, VectorIndexH,
6650 asm, ".8h", ".8h", ".8h", ".h",
6651 [(set (v8i16 V128:$Rd),
6652 (OpNode (v8i16 V128:$Rn),
6653 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6655 let Inst{11} = idx{2};
6656 let Inst{21} = idx{1};
6657 let Inst{20} = idx{0};
6660 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6663 asm, ".2s", ".2s", ".2s", ".s",
6664 [(set (v2i32 V64:$Rd),
6665 (OpNode (v2i32 V64:$Rn),
6666 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6668 let Inst{11} = idx{1};
6669 let Inst{21} = idx{0};
6672 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6675 asm, ".4s", ".4s", ".4s", ".s",
6676 [(set (v4i32 V128:$Rd),
6677 (OpNode (v4i32 V128:$Rn),
6678 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6680 let Inst{11} = idx{1};
6681 let Inst{21} = idx{0};
6685 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6686 SDPatternOperator OpNode> {
6687 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6688 V128_lo, VectorIndexH,
6689 asm, ".4h", ".4h", ".4h", ".h",
6690 [(set (v4i16 V64:$dst),
6691 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6692 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6694 let Inst{11} = idx{2};
6695 let Inst{21} = idx{1};
6696 let Inst{20} = idx{0};
6699 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6701 V128_lo, VectorIndexH,
6702 asm, ".8h", ".8h", ".8h", ".h",
6703 [(set (v8i16 V128:$dst),
6704 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6705 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6707 let Inst{11} = idx{2};
6708 let Inst{21} = idx{1};
6709 let Inst{20} = idx{0};
6712 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6715 asm, ".2s", ".2s", ".2s", ".s",
6716 [(set (v2i32 V64:$dst),
6717 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6718 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6720 let Inst{11} = idx{1};
6721 let Inst{21} = idx{0};
6724 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6727 asm, ".4s", ".4s", ".4s", ".s",
6728 [(set (v4i32 V128:$dst),
6729 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6730 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6732 let Inst{11} = idx{1};
6733 let Inst{21} = idx{0};
6737 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6738 SDPatternOperator OpNode> {
6739 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6741 V128_lo, VectorIndexH,
6742 asm, ".4s", ".4s", ".4h", ".h",
6743 [(set (v4i32 V128:$Rd),
6744 (OpNode (v4i16 V64:$Rn),
6745 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6747 let Inst{11} = idx{2};
6748 let Inst{21} = idx{1};
6749 let Inst{20} = idx{0};
6752 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6754 V128_lo, VectorIndexH,
6755 asm#"2", ".4s", ".4s", ".8h", ".h",
6756 [(set (v4i32 V128:$Rd),
6757 (OpNode (extract_high_v8i16 V128:$Rn),
6758 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6759 VectorIndexH:$idx))))]> {
6762 let Inst{11} = idx{2};
6763 let Inst{21} = idx{1};
6764 let Inst{20} = idx{0};
6767 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6770 asm, ".2d", ".2d", ".2s", ".s",
6771 [(set (v2i64 V128:$Rd),
6772 (OpNode (v2i32 V64:$Rn),
6773 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6775 let Inst{11} = idx{1};
6776 let Inst{21} = idx{0};
6779 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6782 asm#"2", ".2d", ".2d", ".4s", ".s",
6783 [(set (v2i64 V128:$Rd),
6784 (OpNode (extract_high_v4i32 V128:$Rn),
6785 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6786 VectorIndexS:$idx))))]> {
6788 let Inst{11} = idx{1};
6789 let Inst{21} = idx{0};
6792 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6793 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6794 asm, ".h", "", "", ".h", []> {
6796 let Inst{11} = idx{2};
6797 let Inst{21} = idx{1};
6798 let Inst{20} = idx{0};
6801 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6802 FPR64Op, FPR32Op, V128, VectorIndexS,
6803 asm, ".s", "", "", ".s", []> {
6805 let Inst{11} = idx{1};
6806 let Inst{21} = idx{0};
6810 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6811 SDPatternOperator Accum> {
6812 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6814 V128_lo, VectorIndexH,
6815 asm, ".4s", ".4s", ".4h", ".h",
6816 [(set (v4i32 V128:$dst),
6817 (Accum (v4i32 V128:$Rd),
6818 (v4i32 (int_aarch64_neon_sqdmull
6820 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6821 VectorIndexH:$idx))))))]> {
6823 let Inst{11} = idx{2};
6824 let Inst{21} = idx{1};
6825 let Inst{20} = idx{0};
6828 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6829 // intermediate EXTRACT_SUBREG would be untyped.
6830 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6831 (i32 (vector_extract (v4i32
6832 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
6833 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6834 VectorIndexH:$idx)))),
6837 (!cast<Instruction>(NAME # v4i16_indexed)
6838 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6839 V128_lo:$Rm, VectorIndexH:$idx),
6842 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6844 V128_lo, VectorIndexH,
6845 asm#"2", ".4s", ".4s", ".8h", ".h",
6846 [(set (v4i32 V128:$dst),
6847 (Accum (v4i32 V128:$Rd),
6848 (v4i32 (int_aarch64_neon_sqdmull
6849 (extract_high_v8i16 V128:$Rn),
6851 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6852 VectorIndexH:$idx))))))]> {
6854 let Inst{11} = idx{2};
6855 let Inst{21} = idx{1};
6856 let Inst{20} = idx{0};
6859 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6862 asm, ".2d", ".2d", ".2s", ".s",
6863 [(set (v2i64 V128:$dst),
6864 (Accum (v2i64 V128:$Rd),
6865 (v2i64 (int_aarch64_neon_sqdmull
6867 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
6868 VectorIndexS:$idx))))))]> {
6870 let Inst{11} = idx{1};
6871 let Inst{21} = idx{0};
6874 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6877 asm#"2", ".2d", ".2d", ".4s", ".s",
6878 [(set (v2i64 V128:$dst),
6879 (Accum (v2i64 V128:$Rd),
6880 (v2i64 (int_aarch64_neon_sqdmull
6881 (extract_high_v4i32 V128:$Rn),
6883 (AArch64duplane32 (v4i32 V128:$Rm),
6884 VectorIndexS:$idx))))))]> {
6886 let Inst{11} = idx{1};
6887 let Inst{21} = idx{0};
6890 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6891 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6892 asm, ".h", "", "", ".h", []> {
6894 let Inst{11} = idx{2};
6895 let Inst{21} = idx{1};
6896 let Inst{20} = idx{0};
6900 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6901 FPR64Op, FPR32Op, V128, VectorIndexS,
6902 asm, ".s", "", "", ".s",
6903 [(set (i64 FPR64Op:$dst),
6904 (Accum (i64 FPR64Op:$Rd),
6905 (i64 (int_aarch64_neon_sqdmulls_scalar
6907 (i32 (vector_extract (v4i32 V128:$Rm),
6908 VectorIndexS:$idx))))))]> {
6911 let Inst{11} = idx{1};
6912 let Inst{21} = idx{0};
6916 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6917 SDPatternOperator OpNode> {
6918 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6919 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6921 V128_lo, VectorIndexH,
6922 asm, ".4s", ".4s", ".4h", ".h",
6923 [(set (v4i32 V128:$Rd),
6924 (OpNode (v4i16 V64:$Rn),
6925 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6927 let Inst{11} = idx{2};
6928 let Inst{21} = idx{1};
6929 let Inst{20} = idx{0};
6932 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6934 V128_lo, VectorIndexH,
6935 asm#"2", ".4s", ".4s", ".8h", ".h",
6936 [(set (v4i32 V128:$Rd),
6937 (OpNode (extract_high_v8i16 V128:$Rn),
6938 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6939 VectorIndexH:$idx))))]> {
6942 let Inst{11} = idx{2};
6943 let Inst{21} = idx{1};
6944 let Inst{20} = idx{0};
6947 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6950 asm, ".2d", ".2d", ".2s", ".s",
6951 [(set (v2i64 V128:$Rd),
6952 (OpNode (v2i32 V64:$Rn),
6953 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6955 let Inst{11} = idx{1};
6956 let Inst{21} = idx{0};
6959 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6962 asm#"2", ".2d", ".2d", ".4s", ".s",
6963 [(set (v2i64 V128:$Rd),
6964 (OpNode (extract_high_v4i32 V128:$Rn),
6965 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6966 VectorIndexS:$idx))))]> {
6968 let Inst{11} = idx{1};
6969 let Inst{21} = idx{0};
6974 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
6975 SDPatternOperator OpNode> {
6976 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6977 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6979 V128_lo, VectorIndexH,
6980 asm, ".4s", ".4s", ".4h", ".h",
6981 [(set (v4i32 V128:$dst),
6982 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
6983 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6985 let Inst{11} = idx{2};
6986 let Inst{21} = idx{1};
6987 let Inst{20} = idx{0};
6990 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6992 V128_lo, VectorIndexH,
6993 asm#"2", ".4s", ".4s", ".8h", ".h",
6994 [(set (v4i32 V128:$dst),
6995 (OpNode (v4i32 V128:$Rd),
6996 (extract_high_v8i16 V128:$Rn),
6997 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6998 VectorIndexH:$idx))))]> {
7000 let Inst{11} = idx{2};
7001 let Inst{21} = idx{1};
7002 let Inst{20} = idx{0};
7005 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
7008 asm, ".2d", ".2d", ".2s", ".s",
7009 [(set (v2i64 V128:$dst),
7010 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
7011 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
7013 let Inst{11} = idx{1};
7014 let Inst{21} = idx{0};
7017 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
7020 asm#"2", ".2d", ".2d", ".4s", ".s",
7021 [(set (v2i64 V128:$dst),
7022 (OpNode (v2i64 V128:$Rd),
7023 (extract_high_v4i32 V128:$Rn),
7024 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
7025 VectorIndexS:$idx))))]> {
7027 let Inst{11} = idx{1};
7028 let Inst{21} = idx{0};
7033 //----------------------------------------------------------------------------
7034 // AdvSIMD scalar shift by immediate
7035 //----------------------------------------------------------------------------
7037 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7038 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
7039 RegisterClass regtype1, RegisterClass regtype2,
7040 Operand immtype, string asm, list<dag> pattern>
7041 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
7042 asm, "\t$Rd, $Rn, $imm", "", pattern>,
7047 let Inst{31-30} = 0b01;
7049 let Inst{28-23} = 0b111110;
7050 let Inst{22-16} = fixed_imm;
7051 let Inst{15-11} = opc;
7057 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7058 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
7059 RegisterClass regtype1, RegisterClass regtype2,
7060 Operand immtype, string asm, list<dag> pattern>
7061 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7062 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7067 let Inst{31-30} = 0b01;
7069 let Inst{28-23} = 0b111110;
7070 let Inst{22-16} = fixed_imm;
7071 let Inst{15-11} = opc;
7078 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
7079 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7080 FPR32, FPR32, vecshiftR32, asm, []> {
7081 let Inst{20-16} = imm{4-0};
7084 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7085 FPR64, FPR64, vecshiftR64, asm, []> {
7086 let Inst{21-16} = imm{5-0};
7090 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
7091 SDPatternOperator OpNode> {
7092 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7093 FPR64, FPR64, vecshiftR64, asm,
7094 [(set (i64 FPR64:$Rd),
7095 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7096 let Inst{21-16} = imm{5-0};
7099 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7100 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7103 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7104 SDPatternOperator OpNode = null_frag> {
7105 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7106 FPR64, FPR64, vecshiftR64, asm,
7107 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7108 (i32 vecshiftR64:$imm)))]> {
7109 let Inst{21-16} = imm{5-0};
7112 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7113 (i32 vecshiftR64:$imm))),
7114 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7118 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7119 SDPatternOperator OpNode> {
7120 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7121 FPR64, FPR64, vecshiftL64, asm,
7122 [(set (v1i64 FPR64:$Rd),
7123 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7124 let Inst{21-16} = imm{5-0};
7128 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7129 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7130 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7131 FPR64, FPR64, vecshiftL64, asm, []> {
7132 let Inst{21-16} = imm{5-0};
7136 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7137 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7138 SDPatternOperator OpNode = null_frag> {
7139 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7140 FPR8, FPR16, vecshiftR8, asm, []> {
7141 let Inst{18-16} = imm{2-0};
7144 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7145 FPR16, FPR32, vecshiftR16, asm, []> {
7146 let Inst{19-16} = imm{3-0};
7149 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7150 FPR32, FPR64, vecshiftR32, asm,
7151 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7152 let Inst{20-16} = imm{4-0};
7156 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7157 SDPatternOperator OpNode> {
7158 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7159 FPR8, FPR8, vecshiftL8, asm, []> {
7160 let Inst{18-16} = imm{2-0};
7163 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7164 FPR16, FPR16, vecshiftL16, asm, []> {
7165 let Inst{19-16} = imm{3-0};
7168 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7169 FPR32, FPR32, vecshiftL32, asm,
7170 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7171 let Inst{20-16} = imm{4-0};
7174 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7175 FPR64, FPR64, vecshiftL64, asm,
7176 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7177 let Inst{21-16} = imm{5-0};
7180 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7181 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7184 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7185 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7186 FPR8, FPR8, vecshiftR8, asm, []> {
7187 let Inst{18-16} = imm{2-0};
7190 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7191 FPR16, FPR16, vecshiftR16, asm, []> {
7192 let Inst{19-16} = imm{3-0};
7195 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7196 FPR32, FPR32, vecshiftR32, asm, []> {
7197 let Inst{20-16} = imm{4-0};
7200 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7201 FPR64, FPR64, vecshiftR64, asm, []> {
7202 let Inst{21-16} = imm{5-0};
7206 //----------------------------------------------------------------------------
7207 // AdvSIMD vector x indexed element
7208 //----------------------------------------------------------------------------
7210 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7211 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7212 RegisterOperand dst_reg, RegisterOperand src_reg,
7214 string asm, string dst_kind, string src_kind,
7216 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7217 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7218 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7225 let Inst{28-23} = 0b011110;
7226 let Inst{22-16} = fixed_imm;
7227 let Inst{15-11} = opc;
7233 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7234 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7235 RegisterOperand vectype1, RegisterOperand vectype2,
7237 string asm, string dst_kind, string src_kind,
7239 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7240 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7241 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7248 let Inst{28-23} = 0b011110;
7249 let Inst{22-16} = fixed_imm;
7250 let Inst{15-11} = opc;
7256 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7258 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7259 V64, V64, vecshiftR32,
7261 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7263 let Inst{20-16} = imm;
7266 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7267 V128, V128, vecshiftR32,
7269 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7271 let Inst{20-16} = imm;
7274 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7275 V128, V128, vecshiftR64,
7277 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7279 let Inst{21-16} = imm;
7283 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7285 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7286 V64, V64, vecshiftR32,
7288 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7290 let Inst{20-16} = imm;
7293 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7294 V128, V128, vecshiftR32,
7296 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7298 let Inst{20-16} = imm;
7301 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7302 V128, V128, vecshiftR64,
7304 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7306 let Inst{21-16} = imm;
7310 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7311 SDPatternOperator OpNode> {
7312 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7313 V64, V128, vecshiftR16Narrow,
7315 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7317 let Inst{18-16} = imm;
7320 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7321 V128, V128, vecshiftR16Narrow,
7322 asm#"2", ".16b", ".8h", []> {
7324 let Inst{18-16} = imm;
7325 let hasSideEffects = 0;
7328 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7329 V64, V128, vecshiftR32Narrow,
7331 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7333 let Inst{19-16} = imm;
7336 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7337 V128, V128, vecshiftR32Narrow,
7338 asm#"2", ".8h", ".4s", []> {
7340 let Inst{19-16} = imm;
7341 let hasSideEffects = 0;
7344 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7345 V64, V128, vecshiftR64Narrow,
7347 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7349 let Inst{20-16} = imm;
7352 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7353 V128, V128, vecshiftR64Narrow,
7354 asm#"2", ".4s", ".2d", []> {
7356 let Inst{20-16} = imm;
7357 let hasSideEffects = 0;
7360 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7361 // themselves, so put them here instead.
7363 // Patterns involving what's effectively an insert high and a normal
7364 // intrinsic, represented by CONCAT_VECTORS.
7365 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7366 vecshiftR16Narrow:$imm)),
7367 (!cast<Instruction>(NAME # "v16i8_shift")
7368 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7369 V128:$Rn, vecshiftR16Narrow:$imm)>;
7370 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7371 vecshiftR32Narrow:$imm)),
7372 (!cast<Instruction>(NAME # "v8i16_shift")
7373 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7374 V128:$Rn, vecshiftR32Narrow:$imm)>;
7375 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7376 vecshiftR64Narrow:$imm)),
7377 (!cast<Instruction>(NAME # "v4i32_shift")
7378 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7379 V128:$Rn, vecshiftR64Narrow:$imm)>;
7382 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7383 SDPatternOperator OpNode> {
7384 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7385 V64, V64, vecshiftL8,
7387 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7388 (i32 vecshiftL8:$imm)))]> {
7390 let Inst{18-16} = imm;
7393 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7394 V128, V128, vecshiftL8,
7395 asm, ".16b", ".16b",
7396 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7397 (i32 vecshiftL8:$imm)))]> {
7399 let Inst{18-16} = imm;
7402 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7403 V64, V64, vecshiftL16,
7405 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7406 (i32 vecshiftL16:$imm)))]> {
7408 let Inst{19-16} = imm;
7411 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7412 V128, V128, vecshiftL16,
7414 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7415 (i32 vecshiftL16:$imm)))]> {
7417 let Inst{19-16} = imm;
7420 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7421 V64, V64, vecshiftL32,
7423 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7424 (i32 vecshiftL32:$imm)))]> {
7426 let Inst{20-16} = imm;
7429 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7430 V128, V128, vecshiftL32,
7432 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7433 (i32 vecshiftL32:$imm)))]> {
7435 let Inst{20-16} = imm;
7438 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7439 V128, V128, vecshiftL64,
7441 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7442 (i32 vecshiftL64:$imm)))]> {
7444 let Inst{21-16} = imm;
7448 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7449 SDPatternOperator OpNode> {
7450 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7451 V64, V64, vecshiftR8,
7453 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7454 (i32 vecshiftR8:$imm)))]> {
7456 let Inst{18-16} = imm;
7459 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7460 V128, V128, vecshiftR8,
7461 asm, ".16b", ".16b",
7462 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7463 (i32 vecshiftR8:$imm)))]> {
7465 let Inst{18-16} = imm;
7468 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7469 V64, V64, vecshiftR16,
7471 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7472 (i32 vecshiftR16:$imm)))]> {
7474 let Inst{19-16} = imm;
7477 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7478 V128, V128, vecshiftR16,
7480 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7481 (i32 vecshiftR16:$imm)))]> {
7483 let Inst{19-16} = imm;
7486 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7487 V64, V64, vecshiftR32,
7489 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7490 (i32 vecshiftR32:$imm)))]> {
7492 let Inst{20-16} = imm;
7495 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7496 V128, V128, vecshiftR32,
7498 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7499 (i32 vecshiftR32:$imm)))]> {
7501 let Inst{20-16} = imm;
7504 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7505 V128, V128, vecshiftR64,
7507 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7508 (i32 vecshiftR64:$imm)))]> {
7510 let Inst{21-16} = imm;
7514 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7515 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7516 SDPatternOperator OpNode = null_frag> {
7517 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7518 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7519 [(set (v8i8 V64:$dst),
7520 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7521 (i32 vecshiftR8:$imm)))]> {
7523 let Inst{18-16} = imm;
7526 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7527 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7528 [(set (v16i8 V128:$dst),
7529 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7530 (i32 vecshiftR8:$imm)))]> {
7532 let Inst{18-16} = imm;
7535 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7536 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7537 [(set (v4i16 V64:$dst),
7538 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7539 (i32 vecshiftR16:$imm)))]> {
7541 let Inst{19-16} = imm;
7544 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7545 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7546 [(set (v8i16 V128:$dst),
7547 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7548 (i32 vecshiftR16:$imm)))]> {
7550 let Inst{19-16} = imm;
7553 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7554 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7555 [(set (v2i32 V64:$dst),
7556 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7557 (i32 vecshiftR32:$imm)))]> {
7559 let Inst{20-16} = imm;
7562 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7563 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7564 [(set (v4i32 V128:$dst),
7565 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7566 (i32 vecshiftR32:$imm)))]> {
7568 let Inst{20-16} = imm;
7571 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7572 V128, V128, vecshiftR64,
7573 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7574 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7575 (i32 vecshiftR64:$imm)))]> {
7577 let Inst{21-16} = imm;
7581 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7582 SDPatternOperator OpNode = null_frag> {
7583 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7584 V64, V64, vecshiftL8,
7586 [(set (v8i8 V64:$dst),
7587 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7588 (i32 vecshiftL8:$imm)))]> {
7590 let Inst{18-16} = imm;
7593 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7594 V128, V128, vecshiftL8,
7595 asm, ".16b", ".16b",
7596 [(set (v16i8 V128:$dst),
7597 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7598 (i32 vecshiftL8:$imm)))]> {
7600 let Inst{18-16} = imm;
7603 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7604 V64, V64, vecshiftL16,
7606 [(set (v4i16 V64:$dst),
7607 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7608 (i32 vecshiftL16:$imm)))]> {
7610 let Inst{19-16} = imm;
7613 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7614 V128, V128, vecshiftL16,
7616 [(set (v8i16 V128:$dst),
7617 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7618 (i32 vecshiftL16:$imm)))]> {
7620 let Inst{19-16} = imm;
7623 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7624 V64, V64, vecshiftL32,
7626 [(set (v2i32 V64:$dst),
7627 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7628 (i32 vecshiftL32:$imm)))]> {
7630 let Inst{20-16} = imm;
7633 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7634 V128, V128, vecshiftL32,
7636 [(set (v4i32 V128:$dst),
7637 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7638 (i32 vecshiftL32:$imm)))]> {
7640 let Inst{20-16} = imm;
7643 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7644 V128, V128, vecshiftL64,
7646 [(set (v2i64 V128:$dst),
7647 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7648 (i32 vecshiftL64:$imm)))]> {
7650 let Inst{21-16} = imm;
7654 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7655 SDPatternOperator OpNode> {
7656 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7657 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7658 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7660 let Inst{18-16} = imm;
7663 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7664 V128, V128, vecshiftL8,
7665 asm#"2", ".8h", ".16b",
7666 [(set (v8i16 V128:$Rd),
7667 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7669 let Inst{18-16} = imm;
7672 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7673 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7674 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7676 let Inst{19-16} = imm;
7679 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7680 V128, V128, vecshiftL16,
7681 asm#"2", ".4s", ".8h",
7682 [(set (v4i32 V128:$Rd),
7683 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7686 let Inst{19-16} = imm;
7689 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7690 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7691 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7693 let Inst{20-16} = imm;
7696 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7697 V128, V128, vecshiftL32,
7698 asm#"2", ".2d", ".4s",
7699 [(set (v2i64 V128:$Rd),
7700 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7702 let Inst{20-16} = imm;
7708 // Vector load/store
7710 // SIMD ldX/stX no-index memory references don't allow the optional
7711 // ", #0" constant and handle post-indexing explicitly, so we use
7712 // a more specialized parse method for them. Otherwise, it's the same as
7713 // the general GPR64sp handling.
7715 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7716 string asm, dag oops, dag iops, list<dag> pattern>
7717 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
7722 let Inst{29-23} = 0b0011000;
7724 let Inst{21-16} = 0b000000;
7725 let Inst{15-12} = opcode;
7726 let Inst{11-10} = size;
7731 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7732 string asm, dag oops, dag iops>
7733 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
7739 let Inst{29-23} = 0b0011001;
7742 let Inst{20-16} = Xm;
7743 let Inst{15-12} = opcode;
7744 let Inst{11-10} = size;
7749 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7750 // register post-index addressing from the zero register.
7751 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7752 int Offset, int Size> {
7753 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7754 // "ld1\t$Vt, [$Rn], #16"
7755 // may get mapped to
7756 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
7757 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7758 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7760 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7763 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7764 // "ld1.8b\t$Vt, [$Rn], #16"
7765 // may get mapped to
7766 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
7767 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
7768 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7770 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7773 // E.g. "ld1.8b { v0, v1 }, [x1]"
7774 // "ld1\t$Vt, [$Rn]"
7775 // may get mapped to
7776 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
7777 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
7778 (!cast<Instruction>(NAME # Count # "v" # layout)
7779 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7782 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7783 // "ld1\t$Vt, [$Rn], $Xm"
7784 // may get mapped to
7785 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
7786 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
7787 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7789 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7790 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7793 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7794 int Offset64, bits<4> opcode> {
7795 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7796 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7797 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7798 (ins GPR64sp:$Rn), []>;
7799 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7800 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7801 (ins GPR64sp:$Rn), []>;
7802 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7803 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7804 (ins GPR64sp:$Rn), []>;
7805 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7806 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7807 (ins GPR64sp:$Rn), []>;
7808 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7809 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7810 (ins GPR64sp:$Rn), []>;
7811 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7812 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7813 (ins GPR64sp:$Rn), []>;
7814 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7815 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7816 (ins GPR64sp:$Rn), []>;
7819 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7820 (outs GPR64sp:$wback,
7821 !cast<RegisterOperand>(veclist # "16b"):$Vt),
7823 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7824 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7825 (outs GPR64sp:$wback,
7826 !cast<RegisterOperand>(veclist # "8h"):$Vt),
7828 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7829 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7830 (outs GPR64sp:$wback,
7831 !cast<RegisterOperand>(veclist # "4s"):$Vt),
7833 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7834 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7835 (outs GPR64sp:$wback,
7836 !cast<RegisterOperand>(veclist # "2d"):$Vt),
7838 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7839 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7840 (outs GPR64sp:$wback,
7841 !cast<RegisterOperand>(veclist # "8b"):$Vt),
7843 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7844 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7845 (outs GPR64sp:$wback,
7846 !cast<RegisterOperand>(veclist # "4h"):$Vt),
7848 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7849 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7850 (outs GPR64sp:$wback,
7851 !cast<RegisterOperand>(veclist # "2s"):$Vt),
7853 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7856 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7857 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7858 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7859 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7860 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7861 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7862 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7865 // Only ld1/st1 has a v1d version.
7866 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7867 int Offset64, bits<4> opcode> {
7868 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7869 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7870 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7872 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7873 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7875 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7876 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7878 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7879 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7881 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7882 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7884 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7885 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7887 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7888 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7891 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7892 (outs GPR64sp:$wback),
7893 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7895 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7896 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
7897 (outs GPR64sp:$wback),
7898 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7900 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7901 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
7902 (outs GPR64sp:$wback),
7903 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7905 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7906 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
7907 (outs GPR64sp:$wback),
7908 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7910 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7911 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
7912 (outs GPR64sp:$wback),
7913 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7915 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7916 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
7917 (outs GPR64sp:$wback),
7918 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7920 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7921 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
7922 (outs GPR64sp:$wback),
7923 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7925 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7928 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7929 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7930 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7931 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7932 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7933 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7934 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7937 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
7938 int Offset128, int Offset64, bits<4> opcode>
7939 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7941 // LD1 instructions have extra "1d" variants.
7942 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7943 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
7944 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7945 (ins GPR64sp:$Rn), []>;
7947 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
7948 (outs GPR64sp:$wback,
7949 !cast<RegisterOperand>(veclist # "1d"):$Vt),
7951 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7954 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7957 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
7958 int Offset128, int Offset64, bits<4> opcode>
7959 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7961 // ST1 instructions have extra "1d" variants.
7962 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
7963 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
7964 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7967 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
7968 (outs GPR64sp:$wback),
7969 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7971 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7974 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7977 multiclass SIMDLd1Multiple<string asm> {
7978 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7979 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7980 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7981 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7984 multiclass SIMDSt1Multiple<string asm> {
7985 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7986 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7987 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7988 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7991 multiclass SIMDLd2Multiple<string asm> {
7992 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7995 multiclass SIMDSt2Multiple<string asm> {
7996 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7999 multiclass SIMDLd3Multiple<string asm> {
8000 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8003 multiclass SIMDSt3Multiple<string asm> {
8004 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
8007 multiclass SIMDLd4Multiple<string asm> {
8008 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8011 multiclass SIMDSt4Multiple<string asm> {
8012 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
8016 // AdvSIMD Load/store single-element
8019 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
8020 string asm, string operands, string cst,
8021 dag oops, dag iops, list<dag> pattern>
8022 : I<oops, iops, asm, operands, cst, pattern> {
8026 let Inst{29-24} = 0b001101;
8029 let Inst{15-13} = opcode;
8034 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
8035 string asm, string operands, string cst,
8036 dag oops, dag iops, list<dag> pattern>
8037 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
8041 let Inst{29-24} = 0b001101;
8044 let Inst{15-13} = opcode;
8050 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8051 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
8053 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
8054 (outs listtype:$Vt), (ins GPR64sp:$Rn),
8058 let Inst{20-16} = 0b00000;
8060 let Inst{11-10} = size;
8062 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8063 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
8064 string asm, Operand listtype, Operand GPR64pi>
8065 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
8067 (outs GPR64sp:$wback, listtype:$Vt),
8068 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
8072 let Inst{20-16} = Xm;
8074 let Inst{11-10} = size;
8077 multiclass SIMDLdrAliases<string asm, string layout, string Count,
8078 int Offset, int Size> {
8079 // E.g. "ld1r { v0.8b }, [x1], #1"
8080 // "ld1r.8b\t$Vt, [$Rn], #1"
8081 // may get mapped to
8082 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8083 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8084 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8086 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8089 // E.g. "ld1r.8b { v0 }, [x1], #1"
8090 // "ld1r.8b\t$Vt, [$Rn], #1"
8091 // may get mapped to
8092 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8093 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8094 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8096 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8099 // E.g. "ld1r.8b { v0 }, [x1]"
8100 // "ld1r.8b\t$Vt, [$Rn]"
8101 // may get mapped to
8102 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8103 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8104 (!cast<Instruction>(NAME # "v" # layout)
8105 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8108 // E.g. "ld1r.8b { v0 }, [x1], x2"
8109 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8110 // may get mapped to
8111 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8112 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8113 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8115 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8116 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8119 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
8120 int Offset1, int Offset2, int Offset4, int Offset8> {
8121 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8122 !cast<Operand>("VecList" # Count # "8b")>;
8123 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8124 !cast<Operand>("VecList" # Count #"16b")>;
8125 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8126 !cast<Operand>("VecList" # Count #"4h")>;
8127 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8128 !cast<Operand>("VecList" # Count #"8h")>;
8129 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
8130 !cast<Operand>("VecList" # Count #"2s")>;
8131 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
8132 !cast<Operand>("VecList" # Count #"4s")>;
8133 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
8134 !cast<Operand>("VecList" # Count #"1d")>;
8135 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
8136 !cast<Operand>("VecList" # Count #"2d")>;
8138 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8139 !cast<Operand>("VecList" # Count # "8b"),
8140 !cast<Operand>("GPR64pi" # Offset1)>;
8141 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8142 !cast<Operand>("VecList" # Count # "16b"),
8143 !cast<Operand>("GPR64pi" # Offset1)>;
8144 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8145 !cast<Operand>("VecList" # Count # "4h"),
8146 !cast<Operand>("GPR64pi" # Offset2)>;
8147 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
8148 !cast<Operand>("VecList" # Count # "8h"),
8149 !cast<Operand>("GPR64pi" # Offset2)>;
8150 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
8151 !cast<Operand>("VecList" # Count # "2s"),
8152 !cast<Operand>("GPR64pi" # Offset4)>;
8153 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
8154 !cast<Operand>("VecList" # Count # "4s"),
8155 !cast<Operand>("GPR64pi" # Offset4)>;
8156 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
8157 !cast<Operand>("VecList" # Count # "1d"),
8158 !cast<Operand>("GPR64pi" # Offset8)>;
8159 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
8160 !cast<Operand>("VecList" # Count # "2d"),
8161 !cast<Operand>("GPR64pi" # Offset8)>;
8163 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8164 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
8165 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8166 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
8167 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
8168 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
8169 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
8170 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
8173 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
8174 dag oops, dag iops, list<dag> pattern>
8175 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8177 // idx encoded in Q:S:size fields.
8179 let Inst{30} = idx{3};
8181 let Inst{20-16} = 0b00000;
8182 let Inst{12} = idx{2};
8183 let Inst{11-10} = idx{1-0};
8185 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
8186 dag oops, dag iops, list<dag> pattern>
8187 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8188 oops, iops, pattern> {
8189 // idx encoded in Q:S:size fields.
8191 let Inst{30} = idx{3};
8193 let Inst{20-16} = 0b00000;
8194 let Inst{12} = idx{2};
8195 let Inst{11-10} = idx{1-0};
8197 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
8199 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8200 "$Rn = $wback", oops, iops, []> {
8201 // idx encoded in Q:S:size fields.
8204 let Inst{30} = idx{3};
8206 let Inst{20-16} = Xm;
8207 let Inst{12} = idx{2};
8208 let Inst{11-10} = idx{1-0};
8210 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
8212 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8213 "$Rn = $wback", oops, iops, []> {
8214 // idx encoded in Q:S:size fields.
8217 let Inst{30} = idx{3};
8219 let Inst{20-16} = Xm;
8220 let Inst{12} = idx{2};
8221 let Inst{11-10} = idx{1-0};
8224 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8225 dag oops, dag iops, list<dag> pattern>
8226 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8228 // idx encoded in Q:S:size<1> fields.
8230 let Inst{30} = idx{2};
8232 let Inst{20-16} = 0b00000;
8233 let Inst{12} = idx{1};
8234 let Inst{11} = idx{0};
8235 let Inst{10} = size;
8237 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8238 dag oops, dag iops, list<dag> pattern>
8239 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8240 oops, iops, pattern> {
8241 // idx encoded in Q:S:size<1> fields.
8243 let Inst{30} = idx{2};
8245 let Inst{20-16} = 0b00000;
8246 let Inst{12} = idx{1};
8247 let Inst{11} = idx{0};
8248 let Inst{10} = size;
8251 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8253 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8254 "$Rn = $wback", oops, iops, []> {
8255 // idx encoded in Q:S:size<1> fields.
8258 let Inst{30} = idx{2};
8260 let Inst{20-16} = Xm;
8261 let Inst{12} = idx{1};
8262 let Inst{11} = idx{0};
8263 let Inst{10} = size;
8265 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8267 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8268 "$Rn = $wback", oops, iops, []> {
8269 // idx encoded in Q:S:size<1> fields.
8272 let Inst{30} = idx{2};
8274 let Inst{20-16} = Xm;
8275 let Inst{12} = idx{1};
8276 let Inst{11} = idx{0};
8277 let Inst{10} = size;
8279 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8280 dag oops, dag iops, list<dag> pattern>
8281 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8283 // idx encoded in Q:S fields.
8285 let Inst{30} = idx{1};
8287 let Inst{20-16} = 0b00000;
8288 let Inst{12} = idx{0};
8289 let Inst{11-10} = size;
8291 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8292 dag oops, dag iops, list<dag> pattern>
8293 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8294 oops, iops, pattern> {
8295 // idx encoded in Q:S fields.
8297 let Inst{30} = idx{1};
8299 let Inst{20-16} = 0b00000;
8300 let Inst{12} = idx{0};
8301 let Inst{11-10} = size;
8303 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8304 string asm, dag oops, dag iops>
8305 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8306 "$Rn = $wback", oops, iops, []> {
8307 // idx encoded in Q:S fields.
8310 let Inst{30} = idx{1};
8312 let Inst{20-16} = Xm;
8313 let Inst{12} = idx{0};
8314 let Inst{11-10} = size;
8316 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8317 string asm, dag oops, dag iops>
8318 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8319 "$Rn = $wback", oops, iops, []> {
8320 // idx encoded in Q:S fields.
8323 let Inst{30} = idx{1};
8325 let Inst{20-16} = Xm;
8326 let Inst{12} = idx{0};
8327 let Inst{11-10} = size;
8329 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8330 dag oops, dag iops, list<dag> pattern>
8331 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8333 // idx encoded in Q field.
8337 let Inst{20-16} = 0b00000;
8339 let Inst{11-10} = size;
8341 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8342 dag oops, dag iops, list<dag> pattern>
8343 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8344 oops, iops, pattern> {
8345 // idx encoded in Q field.
8349 let Inst{20-16} = 0b00000;
8351 let Inst{11-10} = size;
8353 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8354 string asm, dag oops, dag iops>
8355 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8356 "$Rn = $wback", oops, iops, []> {
8357 // idx encoded in Q field.
8362 let Inst{20-16} = Xm;
8364 let Inst{11-10} = size;
8366 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8367 string asm, dag oops, dag iops>
8368 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8369 "$Rn = $wback", oops, iops, []> {
8370 // idx encoded in Q field.
8375 let Inst{20-16} = Xm;
8377 let Inst{11-10} = size;
8380 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8381 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8382 RegisterOperand listtype,
8383 RegisterOperand GPR64pi> {
8384 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8385 (outs listtype:$dst),
8386 (ins listtype:$Vt, VectorIndexB:$idx,
8389 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8390 (outs GPR64sp:$wback, listtype:$dst),
8391 (ins listtype:$Vt, VectorIndexB:$idx,
8392 GPR64sp:$Rn, GPR64pi:$Xm)>;
8394 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8395 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8396 RegisterOperand listtype,
8397 RegisterOperand GPR64pi> {
8398 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8399 (outs listtype:$dst),
8400 (ins listtype:$Vt, VectorIndexH:$idx,
8403 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8404 (outs GPR64sp:$wback, listtype:$dst),
8405 (ins listtype:$Vt, VectorIndexH:$idx,
8406 GPR64sp:$Rn, GPR64pi:$Xm)>;
8408 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8409 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8410 RegisterOperand listtype,
8411 RegisterOperand GPR64pi> {
8412 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8413 (outs listtype:$dst),
8414 (ins listtype:$Vt, VectorIndexS:$idx,
8417 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8418 (outs GPR64sp:$wback, listtype:$dst),
8419 (ins listtype:$Vt, VectorIndexS:$idx,
8420 GPR64sp:$Rn, GPR64pi:$Xm)>;
8422 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8423 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8424 RegisterOperand listtype, RegisterOperand GPR64pi> {
8425 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8426 (outs listtype:$dst),
8427 (ins listtype:$Vt, VectorIndexD:$idx,
8430 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8431 (outs GPR64sp:$wback, listtype:$dst),
8432 (ins listtype:$Vt, VectorIndexD:$idx,
8433 GPR64sp:$Rn, GPR64pi:$Xm)>;
8435 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8436 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8437 RegisterOperand listtype, RegisterOperand GPR64pi> {
8438 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8439 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8442 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8443 (outs GPR64sp:$wback),
8444 (ins listtype:$Vt, VectorIndexB:$idx,
8445 GPR64sp:$Rn, GPR64pi:$Xm)>;
8447 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8448 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8449 RegisterOperand listtype, RegisterOperand GPR64pi> {
8450 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8451 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8454 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8455 (outs GPR64sp:$wback),
8456 (ins listtype:$Vt, VectorIndexH:$idx,
8457 GPR64sp:$Rn, GPR64pi:$Xm)>;
8459 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8460 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8461 RegisterOperand listtype, RegisterOperand GPR64pi> {
8462 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8463 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8466 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8467 (outs GPR64sp:$wback),
8468 (ins listtype:$Vt, VectorIndexS:$idx,
8469 GPR64sp:$Rn, GPR64pi:$Xm)>;
8471 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8472 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8473 RegisterOperand listtype, RegisterOperand GPR64pi> {
8474 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8475 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8478 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8479 (outs GPR64sp:$wback),
8480 (ins listtype:$Vt, VectorIndexD:$idx,
8481 GPR64sp:$Rn, GPR64pi:$Xm)>;
8484 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8485 string Count, int Offset, Operand idxtype> {
8486 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8487 // "ld1\t$Vt, [$Rn], #1"
8488 // may get mapped to
8489 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8490 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8491 (!cast<Instruction>(NAME # Type # "_POST")
8493 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8494 idxtype:$idx, XZR), 1>;
8496 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8497 // "ld1.8b\t$Vt, [$Rn], #1"
8498 // may get mapped to
8499 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8500 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8501 (!cast<Instruction>(NAME # Type # "_POST")
8503 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8504 idxtype:$idx, XZR), 0>;
8506 // E.g. "ld1.8b { v0 }[0], [x1]"
8507 // "ld1.8b\t$Vt, [$Rn]"
8508 // may get mapped to
8509 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8510 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8511 (!cast<Instruction>(NAME # Type)
8512 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8513 idxtype:$idx, GPR64sp:$Rn), 0>;
8515 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8516 // "ld1.8b\t$Vt, [$Rn], $Xm"
8517 // may get mapped to
8518 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8519 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8520 (!cast<Instruction>(NAME # Type # "_POST")
8522 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8524 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8527 multiclass SIMDLdSt1SingleAliases<string asm> {
8528 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8529 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8530 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8531 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8534 multiclass SIMDLdSt2SingleAliases<string asm> {
8535 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8536 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8537 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8538 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8541 multiclass SIMDLdSt3SingleAliases<string asm> {
8542 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8543 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8544 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8545 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8548 multiclass SIMDLdSt4SingleAliases<string asm> {
8549 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8550 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8551 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8552 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8554 } // end of 'let Predicates = [HasNEON]'
8556 //----------------------------------------------------------------------------
8557 // AdvSIMD v8.1 Rounding Double Multiply Add/Subtract
8558 //----------------------------------------------------------------------------
8560 let Predicates = [HasNEON, HasV8_1a] in {
8562 class BaseSIMDThreeSameVectorTiedR0<bit Q, bit U, bits<2> size, bits<5> opcode,
8563 RegisterOperand regtype, string asm,
8564 string kind, list<dag> pattern>
8565 : BaseSIMDThreeSameVectorTied<Q, U, size, opcode, regtype, asm, kind,
8569 multiclass SIMDThreeSameVectorSQRDMLxHTiedHS<bit U, bits<5> opc, string asm,
8570 SDPatternOperator Accum> {
8571 def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h",
8572 [(set (v4i16 V64:$dst),
8573 (Accum (v4i16 V64:$Rd),
8574 (v4i16 (int_aarch64_neon_sqrdmulh (v4i16 V64:$Rn),
8575 (v4i16 V64:$Rm)))))]>;
8576 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
8577 [(set (v8i16 V128:$dst),
8578 (Accum (v8i16 V128:$Rd),
8579 (v8i16 (int_aarch64_neon_sqrdmulh (v8i16 V128:$Rn),
8580 (v8i16 V128:$Rm)))))]>;
8581 def v2i32 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b10, opc, V64, asm, ".2s",
8582 [(set (v2i32 V64:$dst),
8583 (Accum (v2i32 V64:$Rd),
8584 (v2i32 (int_aarch64_neon_sqrdmulh (v2i32 V64:$Rn),
8585 (v2i32 V64:$Rm)))))]>;
8586 def v4i32 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b10, opc, V128, asm, ".4s",
8587 [(set (v4i32 V128:$dst),
8588 (Accum (v4i32 V128:$Rd),
8589 (v4i32 (int_aarch64_neon_sqrdmulh (v4i32 V128:$Rn),
8590 (v4i32 V128:$Rm)))))]>;
8593 multiclass SIMDIndexedSQRDMLxHSDTied<bit U, bits<4> opc, string asm,
8594 SDPatternOperator Accum> {
8595 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
8596 V64, V64, V128_lo, VectorIndexH,
8597 asm, ".4h", ".4h", ".4h", ".h",
8598 [(set (v4i16 V64:$dst),
8599 (Accum (v4i16 V64:$Rd),
8600 (v4i16 (int_aarch64_neon_sqrdmulh
8602 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
8603 VectorIndexH:$idx))))))]> {
8605 let Inst{11} = idx{2};
8606 let Inst{21} = idx{1};
8607 let Inst{20} = idx{0};
8610 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
8611 V128, V128, V128_lo, VectorIndexH,
8612 asm, ".8h", ".8h", ".8h", ".h",
8613 [(set (v8i16 V128:$dst),
8614 (Accum (v8i16 V128:$Rd),
8615 (v8i16 (int_aarch64_neon_sqrdmulh
8617 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
8618 VectorIndexH:$idx))))))]> {
8620 let Inst{11} = idx{2};
8621 let Inst{21} = idx{1};
8622 let Inst{20} = idx{0};
8625 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
8626 V64, V64, V128, VectorIndexS,
8627 asm, ".2s", ".2s", ".2s", ".s",
8628 [(set (v2i32 V64:$dst),
8629 (Accum (v2i32 V64:$Rd),
8630 (v2i32 (int_aarch64_neon_sqrdmulh
8632 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
8633 VectorIndexS:$idx))))))]> {
8635 let Inst{11} = idx{1};
8636 let Inst{21} = idx{0};
8639 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but
8640 // an intermediate EXTRACT_SUBREG would be untyped.
8641 // FIXME: direct EXTRACT_SUBREG from v2i32 to i32 is illegal, that's why we
8642 // got it lowered here as (i32 vector_extract (v4i32 insert_subvector(..)))
8643 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
8644 (i32 (vector_extract
8645 (v4i32 (insert_subvector
8647 (v2i32 (int_aarch64_neon_sqrdmulh
8649 (v2i32 (AArch64duplane32
8651 VectorIndexS:$idx)))),
8655 (v2i32 (!cast<Instruction>(NAME # v2i32_indexed)
8656 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
8661 VectorIndexS:$idx)),
8664 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
8665 V128, V128, V128, VectorIndexS,
8666 asm, ".4s", ".4s", ".4s", ".s",
8667 [(set (v4i32 V128:$dst),
8668 (Accum (v4i32 V128:$Rd),
8669 (v4i32 (int_aarch64_neon_sqrdmulh
8671 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
8672 VectorIndexS:$idx))))))]> {
8674 let Inst{11} = idx{1};
8675 let Inst{21} = idx{0};
8678 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but
8679 // an intermediate EXTRACT_SUBREG would be untyped.
8680 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
8681 (i32 (vector_extract
8682 (v4i32 (int_aarch64_neon_sqrdmulh
8684 (v4i32 (AArch64duplane32
8686 VectorIndexS:$idx)))),
8689 (v4i32 (!cast<Instruction>(NAME # v4i32_indexed)
8690 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
8695 VectorIndexS:$idx)),
8698 def i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
8699 FPR16Op, FPR16Op, V128_lo,
8700 VectorIndexH, asm, ".h", "", "", ".h",
8703 let Inst{11} = idx{2};
8704 let Inst{21} = idx{1};
8705 let Inst{20} = idx{0};
8708 def i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
8709 FPR32Op, FPR32Op, V128, VectorIndexS,
8710 asm, ".s", "", "", ".s",
8711 [(set (i32 FPR32Op:$dst),
8712 (Accum (i32 FPR32Op:$Rd),
8713 (i32 (int_aarch64_neon_sqrdmulh
8715 (i32 (vector_extract (v4i32 V128:$Rm),
8716 VectorIndexS:$idx))))))]> {
8718 let Inst{11} = idx{1};
8719 let Inst{21} = idx{0};
8722 } // let Predicates = [HasNeon, HasV8_1a]
8724 //----------------------------------------------------------------------------
8725 // Crypto extensions
8726 //----------------------------------------------------------------------------
8728 let Predicates = [HasCrypto] in {
8729 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8730 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8732 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8736 let Inst{31-16} = 0b0100111000101000;
8737 let Inst{15-12} = opc;
8738 let Inst{11-10} = 0b10;
8743 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8744 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8745 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8747 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8748 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8750 [(set (v16i8 V128:$dst),
8751 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8753 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8754 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8755 dag oops, dag iops, list<dag> pat>
8756 : I<oops, iops, asm,
8757 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8758 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8763 let Inst{31-21} = 0b01011110000;
8764 let Inst{20-16} = Rm;
8766 let Inst{14-12} = opc;
8767 let Inst{11-10} = 0b00;
8772 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8773 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8774 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8775 [(set (v4i32 FPR128:$dst),
8776 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8777 (v4i32 V128:$Rm)))]>;
8779 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8780 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8781 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8782 [(set (v4i32 V128:$dst),
8783 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8784 (v4i32 V128:$Rm)))]>;
8786 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8787 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8788 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8789 [(set (v4i32 FPR128:$dst),
8790 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8791 (v4i32 V128:$Rm)))]>;
8793 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8794 class SHA2OpInst<bits<4> opc, string asm, string kind,
8795 string cstr, dag oops, dag iops,
8797 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8798 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8802 let Inst{31-16} = 0b0101111000101000;
8803 let Inst{15-12} = opc;
8804 let Inst{11-10} = 0b10;
8809 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8810 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8811 (ins V128:$Rd, V128:$Rn),
8812 [(set (v4i32 V128:$dst),
8813 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8815 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8816 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8817 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8818 } // end of 'let Predicates = [HasCrypto]'
8820 // Allow the size specifier tokens to be upper case, not just lower.
8821 def : TokenAlias<".8B", ".8b">;
8822 def : TokenAlias<".4H", ".4h">;
8823 def : TokenAlias<".2S", ".2s">;
8824 def : TokenAlias<".1D", ".1d">;
8825 def : TokenAlias<".16B", ".16b">;
8826 def : TokenAlias<".8H", ".8h">;
8827 def : TokenAlias<".4S", ".4s">;
8828 def : TokenAlias<".2D", ".2d">;
8829 def : TokenAlias<".1Q", ".1q">;
8830 def : TokenAlias<".B", ".b">;
8831 def : TokenAlias<".H", ".h">;
8832 def : TokenAlias<".S", ".s">;
8833 def : TokenAlias<".D", ".d">;
8834 def : TokenAlias<".Q", ".q">;