1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe AArch64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // AArch64 Instruction Format
25 class AArch64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "AArch64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : AArch64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
94 let DiagnosticType = "InvalidMovImm32Shift";
96 def MovImm64ShifterOperand : AsmOperandClass {
97 let SuperClasses = [ShifterOperand];
98 let Name = "MovImm64Shifter";
99 let RenderMethod = "addShifterOperands";
100 let DiagnosticType = "InvalidMovImm64Shift";
103 // Shifter operand for arithmetic register shifted encodings.
104 class ArithmeticShifterOperand<int width> : AsmOperandClass {
105 let SuperClasses = [ShifterOperand];
106 let Name = "ArithmeticShifter" # width;
107 let PredicateMethod = "isArithmeticShifter<" # width # ">";
108 let RenderMethod = "addShifterOperands";
109 let DiagnosticType = "AddSubRegShift" # width;
112 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
113 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
115 // Shifter operand for logical register shifted encodings.
116 class LogicalShifterOperand<int width> : AsmOperandClass {
117 let SuperClasses = [ShifterOperand];
118 let Name = "LogicalShifter" # width;
119 let PredicateMethod = "isLogicalShifter<" # width # ">";
120 let RenderMethod = "addShifterOperands";
121 let DiagnosticType = "AddSubRegShift" # width;
124 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
125 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
127 // Shifter operand for logical vector 128/64-bit shifted encodings.
128 def LogicalVecShifterOperand : AsmOperandClass {
129 let SuperClasses = [ShifterOperand];
130 let Name = "LogicalVecShifter";
131 let RenderMethod = "addShifterOperands";
133 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
134 let SuperClasses = [LogicalVecShifterOperand];
135 let Name = "LogicalVecHalfWordShifter";
136 let RenderMethod = "addShifterOperands";
139 // The "MSL" shifter on the vector MOVI instruction.
140 def MoveVecShifterOperand : AsmOperandClass {
141 let SuperClasses = [ShifterOperand];
142 let Name = "MoveVecShifter";
143 let RenderMethod = "addShifterOperands";
146 // Extend operand for arithmetic encodings.
147 def ExtendOperand : AsmOperandClass {
149 let DiagnosticType = "AddSubRegExtendLarge";
151 def ExtendOperand64 : AsmOperandClass {
152 let SuperClasses = [ExtendOperand];
153 let Name = "Extend64";
154 let DiagnosticType = "AddSubRegExtendSmall";
156 // 'extend' that's a lsl of a 64-bit register.
157 def ExtendOperandLSL64 : AsmOperandClass {
158 let SuperClasses = [ExtendOperand];
159 let Name = "ExtendLSL64";
160 let RenderMethod = "addExtend64Operands";
161 let DiagnosticType = "AddSubRegExtendLarge";
164 // 8-bit floating-point immediate encodings.
165 def FPImmOperand : AsmOperandClass {
167 let ParserMethod = "tryParseFPImm";
168 let DiagnosticType = "InvalidFPImm";
171 def CondCode : AsmOperandClass {
172 let Name = "CondCode";
173 let DiagnosticType = "InvalidCondCode";
176 // A 32-bit register pasrsed as 64-bit
177 def GPR32as64Operand : AsmOperandClass {
178 let Name = "GPR32as64";
180 def GPR32as64 : RegisterOperand<GPR32> {
181 let ParserMatchClass = GPR32as64Operand;
184 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
185 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
186 // are encoded as the eight bit value 'abcdefgh'.
187 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
190 //===----------------------------------------------------------------------===//
191 // Operand Definitions.
194 // ADR[P] instruction labels.
195 def AdrpOperand : AsmOperandClass {
196 let Name = "AdrpLabel";
197 let ParserMethod = "tryParseAdrpLabel";
198 let DiagnosticType = "InvalidLabel";
200 def adrplabel : Operand<i64> {
201 let EncoderMethod = "getAdrLabelOpValue";
202 let PrintMethod = "printAdrpLabel";
203 let ParserMatchClass = AdrpOperand;
206 def AdrOperand : AsmOperandClass {
207 let Name = "AdrLabel";
208 let ParserMethod = "tryParseAdrLabel";
209 let DiagnosticType = "InvalidLabel";
211 def adrlabel : Operand<i64> {
212 let EncoderMethod = "getAdrLabelOpValue";
213 let ParserMatchClass = AdrOperand;
216 // simm9 predicate - True if the immediate is in the range [-256, 255].
217 def SImm9Operand : AsmOperandClass {
219 let DiagnosticType = "InvalidMemoryIndexedSImm9";
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
222 let ParserMatchClass = SImm9Operand;
225 // simm7sN predicate - True if the immediate is a multiple of N in the range
226 // [-64 * N, 63 * N].
227 class SImm7Scaled<int Scale> : AsmOperandClass {
228 let Name = "SImm7s" # Scale;
229 let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
232 def SImm7s4Operand : SImm7Scaled<4>;
233 def SImm7s8Operand : SImm7Scaled<8>;
234 def SImm7s16Operand : SImm7Scaled<16>;
236 def simm7s4 : Operand<i32> {
237 let ParserMatchClass = SImm7s4Operand;
238 let PrintMethod = "printImmScale<4>";
241 def simm7s8 : Operand<i32> {
242 let ParserMatchClass = SImm7s8Operand;
243 let PrintMethod = "printImmScale<8>";
246 def simm7s16 : Operand<i32> {
247 let ParserMatchClass = SImm7s16Operand;
248 let PrintMethod = "printImmScale<16>";
251 class AsmImmRange<int Low, int High> : AsmOperandClass {
252 let Name = "Imm" # Low # "_" # High;
253 let DiagnosticType = "InvalidImm" # Low # "_" # High;
256 def Imm1_8Operand : AsmImmRange<1, 8>;
257 def Imm1_16Operand : AsmImmRange<1, 16>;
258 def Imm1_32Operand : AsmImmRange<1, 32>;
259 def Imm1_64Operand : AsmImmRange<1, 64>;
261 def MovZSymbolG3AsmOperand : AsmOperandClass {
262 let Name = "MovZSymbolG3";
263 let RenderMethod = "addImmOperands";
266 def movz_symbol_g3 : Operand<i32> {
267 let ParserMatchClass = MovZSymbolG3AsmOperand;
270 def MovZSymbolG2AsmOperand : AsmOperandClass {
271 let Name = "MovZSymbolG2";
272 let RenderMethod = "addImmOperands";
275 def movz_symbol_g2 : Operand<i32> {
276 let ParserMatchClass = MovZSymbolG2AsmOperand;
279 def MovZSymbolG1AsmOperand : AsmOperandClass {
280 let Name = "MovZSymbolG1";
281 let RenderMethod = "addImmOperands";
284 def movz_symbol_g1 : Operand<i32> {
285 let ParserMatchClass = MovZSymbolG1AsmOperand;
288 def MovZSymbolG0AsmOperand : AsmOperandClass {
289 let Name = "MovZSymbolG0";
290 let RenderMethod = "addImmOperands";
293 def movz_symbol_g0 : Operand<i32> {
294 let ParserMatchClass = MovZSymbolG0AsmOperand;
297 def MovKSymbolG3AsmOperand : AsmOperandClass {
298 let Name = "MovKSymbolG3";
299 let RenderMethod = "addImmOperands";
302 def movk_symbol_g3 : Operand<i32> {
303 let ParserMatchClass = MovKSymbolG3AsmOperand;
306 def MovKSymbolG2AsmOperand : AsmOperandClass {
307 let Name = "MovKSymbolG2";
308 let RenderMethod = "addImmOperands";
311 def movk_symbol_g2 : Operand<i32> {
312 let ParserMatchClass = MovKSymbolG2AsmOperand;
315 def MovKSymbolG1AsmOperand : AsmOperandClass {
316 let Name = "MovKSymbolG1";
317 let RenderMethod = "addImmOperands";
320 def movk_symbol_g1 : Operand<i32> {
321 let ParserMatchClass = MovKSymbolG1AsmOperand;
324 def MovKSymbolG0AsmOperand : AsmOperandClass {
325 let Name = "MovKSymbolG0";
326 let RenderMethod = "addImmOperands";
329 def movk_symbol_g0 : Operand<i32> {
330 let ParserMatchClass = MovKSymbolG0AsmOperand;
333 class fixedpoint_i32<ValueType FloatVT>
335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
336 let EncoderMethod = "getFixedPointScaleOpValue";
337 let DecoderMethod = "DecodeFixedPointScaleImm32";
338 let ParserMatchClass = Imm1_32Operand;
341 class fixedpoint_i64<ValueType FloatVT>
343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
344 let EncoderMethod = "getFixedPointScaleOpValue";
345 let DecoderMethod = "DecodeFixedPointScaleImm64";
346 let ParserMatchClass = Imm1_64Operand;
349 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
350 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
352 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
353 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
355 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
356 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
358 let EncoderMethod = "getVecShiftR8OpValue";
359 let DecoderMethod = "DecodeVecShiftR8Imm";
360 let ParserMatchClass = Imm1_8Operand;
362 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
363 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
365 let EncoderMethod = "getVecShiftR16OpValue";
366 let DecoderMethod = "DecodeVecShiftR16Imm";
367 let ParserMatchClass = Imm1_16Operand;
369 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
370 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
372 let EncoderMethod = "getVecShiftR16OpValue";
373 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
374 let ParserMatchClass = Imm1_8Operand;
376 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
377 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
379 let EncoderMethod = "getVecShiftR32OpValue";
380 let DecoderMethod = "DecodeVecShiftR32Imm";
381 let ParserMatchClass = Imm1_32Operand;
383 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
384 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
386 let EncoderMethod = "getVecShiftR32OpValue";
387 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
388 let ParserMatchClass = Imm1_16Operand;
390 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
391 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
393 let EncoderMethod = "getVecShiftR64OpValue";
394 let DecoderMethod = "DecodeVecShiftR64Imm";
395 let ParserMatchClass = Imm1_64Operand;
397 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
398 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
400 let EncoderMethod = "getVecShiftR64OpValue";
401 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
402 let ParserMatchClass = Imm1_32Operand;
405 def Imm0_7Operand : AsmImmRange<0, 7>;
406 def Imm0_15Operand : AsmImmRange<0, 15>;
407 def Imm0_31Operand : AsmImmRange<0, 31>;
408 def Imm0_63Operand : AsmImmRange<0, 63>;
410 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
411 return (((uint32_t)Imm) < 8);
413 let EncoderMethod = "getVecShiftL8OpValue";
414 let DecoderMethod = "DecodeVecShiftL8Imm";
415 let ParserMatchClass = Imm0_7Operand;
417 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
418 return (((uint32_t)Imm) < 16);
420 let EncoderMethod = "getVecShiftL16OpValue";
421 let DecoderMethod = "DecodeVecShiftL16Imm";
422 let ParserMatchClass = Imm0_15Operand;
424 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
425 return (((uint32_t)Imm) < 32);
427 let EncoderMethod = "getVecShiftL32OpValue";
428 let DecoderMethod = "DecodeVecShiftL32Imm";
429 let ParserMatchClass = Imm0_31Operand;
431 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
432 return (((uint32_t)Imm) < 64);
434 let EncoderMethod = "getVecShiftL64OpValue";
435 let DecoderMethod = "DecodeVecShiftL64Imm";
436 let ParserMatchClass = Imm0_63Operand;
440 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
441 // instructions for splatting repeating bit patterns across the immediate.
442 def logical_imm32_XFORM : SDNodeXForm<imm, [{
443 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
444 return CurDAG->getTargetConstant(enc, MVT::i32);
446 def logical_imm64_XFORM : SDNodeXForm<imm, [{
447 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
448 return CurDAG->getTargetConstant(enc, MVT::i32);
451 let DiagnosticType = "LogicalSecondSource" in {
452 def LogicalImm32Operand : AsmOperandClass {
453 let Name = "LogicalImm32";
455 def LogicalImm64Operand : AsmOperandClass {
456 let Name = "LogicalImm64";
458 def LogicalImm32NotOperand : AsmOperandClass {
459 let Name = "LogicalImm32Not";
461 def LogicalImm64NotOperand : AsmOperandClass {
462 let Name = "LogicalImm64Not";
465 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
466 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
467 }], logical_imm32_XFORM> {
468 let PrintMethod = "printLogicalImm32";
469 let ParserMatchClass = LogicalImm32Operand;
471 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
472 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
473 }], logical_imm64_XFORM> {
474 let PrintMethod = "printLogicalImm64";
475 let ParserMatchClass = LogicalImm64Operand;
477 def logical_imm32_not : Operand<i32> {
478 let ParserMatchClass = LogicalImm32NotOperand;
480 def logical_imm64_not : Operand<i64> {
481 let ParserMatchClass = LogicalImm64NotOperand;
484 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
485 def Imm0_65535Operand : AsmImmRange<0, 65535>;
486 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
487 return ((uint32_t)Imm) < 65536;
489 let ParserMatchClass = Imm0_65535Operand;
490 let PrintMethod = "printHexImm";
493 // imm0_255 predicate - True if the immediate is in the range [0,255].
494 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
495 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
496 return ((uint32_t)Imm) < 256;
498 let ParserMatchClass = Imm0_255Operand;
499 let PrintMethod = "printHexImm";
502 // imm0_127 predicate - True if the immediate is in the range [0,127]
503 def Imm0_127Operand : AsmImmRange<0, 127>;
504 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
505 return ((uint32_t)Imm) < 128;
507 let ParserMatchClass = Imm0_127Operand;
508 let PrintMethod = "printHexImm";
511 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
512 // for all shift-amounts.
514 // imm0_63 predicate - True if the immediate is in the range [0,63]
515 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
516 return ((uint64_t)Imm) < 64;
518 let ParserMatchClass = Imm0_63Operand;
521 // imm0_31 predicate - True if the immediate is in the range [0,31]
522 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
523 return ((uint64_t)Imm) < 32;
525 let ParserMatchClass = Imm0_31Operand;
528 // imm0_15 predicate - True if the immediate is in the range [0,15]
529 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
530 return ((uint64_t)Imm) < 16;
532 let ParserMatchClass = Imm0_15Operand;
535 // imm0_7 predicate - True if the immediate is in the range [0,7]
536 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
537 return ((uint64_t)Imm) < 8;
539 let ParserMatchClass = Imm0_7Operand;
542 // An arithmetic shifter operand:
543 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
545 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
546 let PrintMethod = "printShifter";
547 let ParserMatchClass = !cast<AsmOperandClass>(
548 "ArithmeticShifterOperand" # width);
551 def arith_shift32 : arith_shift<i32, 32>;
552 def arith_shift64 : arith_shift<i64, 64>;
554 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
556 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
557 let PrintMethod = "printShiftedRegister";
558 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
561 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
562 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
564 // An arithmetic shifter operand:
565 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
567 class logical_shift<int width> : Operand<i32> {
568 let PrintMethod = "printShifter";
569 let ParserMatchClass = !cast<AsmOperandClass>(
570 "LogicalShifterOperand" # width);
573 def logical_shift32 : logical_shift<32>;
574 def logical_shift64 : logical_shift<64>;
576 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
578 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
579 let PrintMethod = "printShiftedRegister";
580 let MIOperandInfo = (ops regclass, shiftop);
583 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
584 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
586 // A logical vector shifter operand:
587 // {7-6} - shift type: 00 = lsl
588 // {5-0} - imm6: #0, #8, #16, or #24
589 def logical_vec_shift : Operand<i32> {
590 let PrintMethod = "printShifter";
591 let EncoderMethod = "getVecShifterOpValue";
592 let ParserMatchClass = LogicalVecShifterOperand;
595 // A logical vector half-word shifter operand:
596 // {7-6} - shift type: 00 = lsl
597 // {5-0} - imm6: #0 or #8
598 def logical_vec_hw_shift : Operand<i32> {
599 let PrintMethod = "printShifter";
600 let EncoderMethod = "getVecShifterOpValue";
601 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
604 // A vector move shifter operand:
605 // {0} - imm1: #8 or #16
606 def move_vec_shift : Operand<i32> {
607 let PrintMethod = "printShifter";
608 let EncoderMethod = "getMoveVecShifterOpValue";
609 let ParserMatchClass = MoveVecShifterOperand;
612 def AddSubImmOperand : AsmOperandClass {
613 let Name = "AddSubImm";
614 let ParserMethod = "tryParseAddSubImm";
615 let DiagnosticType = "AddSubSecondSource";
617 // An ADD/SUB immediate shifter operand:
619 // {7-6} - shift type: 00 = lsl
620 // {5-0} - imm6: #0 or #12
621 class addsub_shifted_imm<ValueType Ty>
622 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
623 let PrintMethod = "printAddSubImm";
624 let EncoderMethod = "getAddSubImmOpValue";
625 let ParserMatchClass = AddSubImmOperand;
626 let MIOperandInfo = (ops i32imm, i32imm);
629 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
630 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
632 class neg_addsub_shifted_imm<ValueType Ty>
633 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
634 let PrintMethod = "printAddSubImm";
635 let EncoderMethod = "getAddSubImmOpValue";
636 let ParserMatchClass = AddSubImmOperand;
637 let MIOperandInfo = (ops i32imm, i32imm);
640 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
641 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
643 // An extend operand:
644 // {5-3} - extend type
646 def arith_extend : Operand<i32> {
647 let PrintMethod = "printArithExtend";
648 let ParserMatchClass = ExtendOperand;
650 def arith_extend64 : Operand<i32> {
651 let PrintMethod = "printArithExtend";
652 let ParserMatchClass = ExtendOperand64;
655 // 'extend' that's a lsl of a 64-bit register.
656 def arith_extendlsl64 : Operand<i32> {
657 let PrintMethod = "printArithExtend";
658 let ParserMatchClass = ExtendOperandLSL64;
661 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
662 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
663 let PrintMethod = "printExtendedRegister";
664 let MIOperandInfo = (ops GPR32, arith_extend);
667 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
668 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
669 let PrintMethod = "printExtendedRegister";
670 let MIOperandInfo = (ops GPR32, arith_extend64);
673 // Floating-point immediate.
674 def fpimm32 : Operand<f32>,
675 PatLeaf<(f32 fpimm), [{
676 return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1;
677 }], SDNodeXForm<fpimm, [{
678 APFloat InVal = N->getValueAPF();
679 uint32_t enc = AArch64_AM::getFP32Imm(InVal);
680 return CurDAG->getTargetConstant(enc, MVT::i32);
682 let ParserMatchClass = FPImmOperand;
683 let PrintMethod = "printFPImmOperand";
685 def fpimm64 : Operand<f64>,
686 PatLeaf<(f64 fpimm), [{
687 return AArch64_AM::getFP64Imm(N->getValueAPF()) != -1;
688 }], SDNodeXForm<fpimm, [{
689 APFloat InVal = N->getValueAPF();
690 uint32_t enc = AArch64_AM::getFP64Imm(InVal);
691 return CurDAG->getTargetConstant(enc, MVT::i32);
693 let ParserMatchClass = FPImmOperand;
694 let PrintMethod = "printFPImmOperand";
697 def fpimm8 : Operand<i32> {
698 let ParserMatchClass = FPImmOperand;
699 let PrintMethod = "printFPImmOperand";
702 def fpimm0 : PatLeaf<(fpimm), [{
703 return N->isExactlyValue(+0.0);
706 // Vector lane operands
707 class AsmVectorIndex<string Suffix> : AsmOperandClass {
708 let Name = "VectorIndex" # Suffix;
709 let DiagnosticType = "InvalidIndex" # Suffix;
711 def VectorIndex1Operand : AsmVectorIndex<"1">;
712 def VectorIndexBOperand : AsmVectorIndex<"B">;
713 def VectorIndexHOperand : AsmVectorIndex<"H">;
714 def VectorIndexSOperand : AsmVectorIndex<"S">;
715 def VectorIndexDOperand : AsmVectorIndex<"D">;
717 def VectorIndex1 : Operand<i64>, ImmLeaf<i64, [{
718 return ((uint64_t)Imm) == 1;
720 let ParserMatchClass = VectorIndex1Operand;
721 let PrintMethod = "printVectorIndex";
722 let MIOperandInfo = (ops i64imm);
724 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
725 return ((uint64_t)Imm) < 16;
727 let ParserMatchClass = VectorIndexBOperand;
728 let PrintMethod = "printVectorIndex";
729 let MIOperandInfo = (ops i64imm);
731 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
732 return ((uint64_t)Imm) < 8;
734 let ParserMatchClass = VectorIndexHOperand;
735 let PrintMethod = "printVectorIndex";
736 let MIOperandInfo = (ops i64imm);
738 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
739 return ((uint64_t)Imm) < 4;
741 let ParserMatchClass = VectorIndexSOperand;
742 let PrintMethod = "printVectorIndex";
743 let MIOperandInfo = (ops i64imm);
745 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
746 return ((uint64_t)Imm) < 2;
748 let ParserMatchClass = VectorIndexDOperand;
749 let PrintMethod = "printVectorIndex";
750 let MIOperandInfo = (ops i64imm);
753 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
754 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
755 // are encoded as the eight bit value 'abcdefgh'.
756 def simdimmtype10 : Operand<i32>,
757 PatLeaf<(f64 fpimm), [{
758 return AArch64_AM::isAdvSIMDModImmType10(N->getValueAPF()
761 }], SDNodeXForm<fpimm, [{
762 APFloat InVal = N->getValueAPF();
763 uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
766 return CurDAG->getTargetConstant(enc, MVT::i32);
768 let ParserMatchClass = SIMDImmType10Operand;
769 let PrintMethod = "printSIMDType10Operand";
777 // Base encoding for system instruction operands.
778 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
779 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands>
780 : I<oops, iops, asm, operands, "", []> {
781 let Inst{31-22} = 0b1101010100;
785 // System instructions which do not have an Rt register.
786 class SimpleSystemI<bit L, dag iops, string asm, string operands>
787 : BaseSystemI<L, (outs), iops, asm, operands> {
788 let Inst{4-0} = 0b11111;
791 // System instructions which have an Rt register.
792 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
793 : BaseSystemI<L, oops, iops, asm, operands>,
799 // Hint instructions that take both a CRm and a 3-bit immediate.
800 class HintI<string mnemonic>
801 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">,
804 let Inst{20-12} = 0b000110010;
805 let Inst{11-5} = imm;
808 // System instructions taking a single literal operand which encodes into
809 // CRm. op2 differentiates the opcodes.
810 def BarrierAsmOperand : AsmOperandClass {
811 let Name = "Barrier";
812 let ParserMethod = "tryParseBarrierOperand";
814 def barrier_op : Operand<i32> {
815 let PrintMethod = "printBarrierOption";
816 let ParserMatchClass = BarrierAsmOperand;
818 class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
819 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm">,
820 Sched<[WriteBarrier]> {
822 let Inst{20-12} = 0b000110011;
823 let Inst{11-8} = CRm;
827 // MRS/MSR system instructions. These have different operand classes because
828 // a different subset of registers can be accessed through each instruction.
829 def MRSSystemRegisterOperand : AsmOperandClass {
830 let Name = "MRSSystemRegister";
831 let ParserMethod = "tryParseSysReg";
832 let DiagnosticType = "MRS";
834 // concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
835 def mrs_sysreg_op : Operand<i32> {
836 let ParserMatchClass = MRSSystemRegisterOperand;
837 let DecoderMethod = "DecodeMRSSystemRegister";
838 let PrintMethod = "printMRSSystemRegister";
841 def MSRSystemRegisterOperand : AsmOperandClass {
842 let Name = "MSRSystemRegister";
843 let ParserMethod = "tryParseSysReg";
844 let DiagnosticType = "MSR";
846 def msr_sysreg_op : Operand<i32> {
847 let ParserMatchClass = MSRSystemRegisterOperand;
848 let DecoderMethod = "DecodeMSRSystemRegister";
849 let PrintMethod = "printMSRSystemRegister";
852 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
853 "mrs", "\t$Rt, $systemreg"> {
856 let Inst{19-5} = systemreg;
859 // FIXME: Some of these def NZCV, others don't. Best way to model that?
860 // Explicitly modeling each of the system register as a register class
861 // would do it, but feels like overkill at this point.
862 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
863 "msr", "\t$systemreg, $Rt"> {
866 let Inst{19-5} = systemreg;
869 def SystemPStateFieldOperand : AsmOperandClass {
870 let Name = "SystemPStateField";
871 let ParserMethod = "tryParseSysReg";
873 def pstatefield_op : Operand<i32> {
874 let ParserMatchClass = SystemPStateFieldOperand;
875 let PrintMethod = "printSystemPStateField";
880 : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
881 "msr", "\t$pstate_field, $imm">,
885 let Inst{20-19} = 0b00;
886 let Inst{18-16} = pstatefield{5-3};
887 let Inst{15-12} = 0b0100;
888 let Inst{11-8} = imm;
889 let Inst{7-5} = pstatefield{2-0};
891 let DecoderMethod = "DecodeSystemPStateInstruction";
894 // SYS and SYSL generic system instructions.
895 def SysCRAsmOperand : AsmOperandClass {
897 let ParserMethod = "tryParseSysCROperand";
900 def sys_cr_op : Operand<i32> {
901 let PrintMethod = "printSysCROperand";
902 let ParserMatchClass = SysCRAsmOperand;
905 class SystemXtI<bit L, string asm>
906 : RtSystemI<L, (outs),
907 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
908 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
913 let Inst{20-19} = 0b01;
914 let Inst{18-16} = op1;
915 let Inst{15-12} = Cn;
920 class SystemLXtI<bit L, string asm>
921 : RtSystemI<L, (outs),
922 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
923 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
928 let Inst{20-19} = 0b01;
929 let Inst{18-16} = op1;
930 let Inst{15-12} = Cn;
936 // Branch (register) instructions:
944 // otherwise UNDEFINED
945 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
946 string operands, list<dag> pattern>
947 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
948 let Inst{31-25} = 0b1101011;
949 let Inst{24-21} = opc;
950 let Inst{20-16} = 0b11111;
951 let Inst{15-10} = 0b000000;
952 let Inst{4-0} = 0b00000;
955 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
956 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
961 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
962 class SpecialReturn<bits<4> opc, string asm>
963 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
964 let Inst{9-5} = 0b11111;
968 // Conditional branch instruction.
972 // 4-bit immediate. Pretty-printed as <cc>
973 def ccode : Operand<i32> {
974 let PrintMethod = "printCondCode";
975 let ParserMatchClass = CondCode;
977 def inv_ccode : Operand<i32> {
978 // AL and NV are invalid in the aliases which use inv_ccode
979 let PrintMethod = "printInverseCondCode";
980 let ParserMatchClass = CondCode;
981 let MCOperandPredicate = [{
982 return MCOp.isImm() &&
983 MCOp.getImm() != AArch64CC::AL &&
984 MCOp.getImm() != AArch64CC::NV;
988 // Conditional branch target. 19-bit immediate. The low two bits of the target
989 // offset are implied zero and so are not part of the immediate.
990 def PCRelLabel19Operand : AsmOperandClass {
991 let Name = "PCRelLabel19";
992 let DiagnosticType = "InvalidLabel";
994 def am_brcond : Operand<OtherVT> {
995 let EncoderMethod = "getCondBranchTargetOpValue";
996 let DecoderMethod = "DecodePCRelLabel19";
997 let PrintMethod = "printAlignedLabel";
998 let ParserMatchClass = PCRelLabel19Operand;
1001 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
1002 "b", ".$cond\t$target", "",
1003 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
1006 let isTerminator = 1;
1011 let Inst{31-24} = 0b01010100;
1012 let Inst{23-5} = target;
1014 let Inst{3-0} = cond;
1018 // Compare-and-branch instructions.
1020 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
1021 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
1022 asm, "\t$Rt, $target", "",
1023 [(node regtype:$Rt, bb:$target)]>,
1026 let isTerminator = 1;
1030 let Inst{30-25} = 0b011010;
1032 let Inst{23-5} = target;
1036 multiclass CmpBranch<bit op, string asm, SDNode node> {
1037 def W : BaseCmpBranch<GPR32, op, asm, node> {
1040 def X : BaseCmpBranch<GPR64, op, asm, node> {
1046 // Test-bit-and-branch instructions.
1048 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
1049 // the target offset are implied zero and so are not part of the immediate.
1050 def BranchTarget14Operand : AsmOperandClass {
1051 let Name = "BranchTarget14";
1053 def am_tbrcond : Operand<OtherVT> {
1054 let EncoderMethod = "getTestBranchTargetOpValue";
1055 let PrintMethod = "printAlignedLabel";
1056 let ParserMatchClass = BranchTarget14Operand;
1059 // AsmOperand classes to emit (or not) special diagnostics
1060 def TBZImm0_31Operand : AsmOperandClass {
1061 let Name = "TBZImm0_31";
1062 let PredicateMethod = "isImm0_31";
1063 let RenderMethod = "addImm0_31Operands";
1065 def TBZImm32_63Operand : AsmOperandClass {
1066 let Name = "Imm32_63";
1067 let DiagnosticType = "InvalidImm0_63";
1070 class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
1071 return (((uint32_t)Imm) < 32);
1073 let ParserMatchClass = matcher;
1076 def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
1077 def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;
1079 def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
1080 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1082 let ParserMatchClass = TBZImm32_63Operand;
1085 class BaseTestBranch<RegisterClass regtype, Operand immtype,
1086 bit op, string asm, SDNode node>
1087 : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
1088 asm, "\t$Rt, $bit_off, $target", "",
1089 [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
1092 let isTerminator = 1;
1098 let Inst{30-25} = 0b011011;
1100 let Inst{23-19} = bit_off{4-0};
1101 let Inst{18-5} = target;
1104 let DecoderMethod = "DecodeTestAndBranch";
1107 multiclass TestBranch<bit op, string asm, SDNode node> {
1108 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1112 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1116 // Alias X-reg with 0-31 imm to W-Reg.
1117 def : InstAlias<asm # "\t$Rd, $imm, $target",
1118 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1119 tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
1120 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1121 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1122 tbz_imm0_31_diag:$imm, bb:$target)>;
1126 // Unconditional branch (immediate) instructions.
1128 def BranchTarget26Operand : AsmOperandClass {
1129 let Name = "BranchTarget26";
1130 let DiagnosticType = "InvalidLabel";
1132 def am_b_target : Operand<OtherVT> {
1133 let EncoderMethod = "getBranchTargetOpValue";
1134 let PrintMethod = "printAlignedLabel";
1135 let ParserMatchClass = BranchTarget26Operand;
1137 def am_bl_target : Operand<i64> {
1138 let EncoderMethod = "getBranchTargetOpValue";
1139 let PrintMethod = "printAlignedLabel";
1140 let ParserMatchClass = BranchTarget26Operand;
1143 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1144 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1147 let Inst{30-26} = 0b00101;
1148 let Inst{25-0} = addr;
1150 let DecoderMethod = "DecodeUnconditionalBranch";
1153 class BranchImm<bit op, string asm, list<dag> pattern>
1154 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1155 class CallImm<bit op, string asm, list<dag> pattern>
1156 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1159 // Basic one-operand data processing instructions.
1162 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1163 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1164 SDPatternOperator node>
1165 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1166 [(set regtype:$Rd, (node regtype:$Rn))]>,
1167 Sched<[WriteI, ReadI]> {
1171 let Inst{30-13} = 0b101101011000000000;
1172 let Inst{12-10} = opc;
1177 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1178 multiclass OneOperandData<bits<3> opc, string asm,
1179 SDPatternOperator node = null_frag> {
1180 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1184 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1189 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1190 : BaseOneOperandData<opc, GPR32, asm, node> {
1194 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1195 : BaseOneOperandData<opc, GPR64, asm, node> {
1200 // Basic two-operand data processing instructions.
1202 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1204 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1205 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1206 Sched<[WriteI, ReadI, ReadI]> {
1211 let Inst{30} = isSub;
1212 let Inst{28-21} = 0b11010000;
1213 let Inst{20-16} = Rm;
1214 let Inst{15-10} = 0;
1219 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1221 : BaseBaseAddSubCarry<isSub, regtype, asm,
1222 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1224 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1226 : BaseBaseAddSubCarry<isSub, regtype, asm,
1227 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1232 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1233 SDNode OpNode, SDNode OpNode_setflags> {
1234 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1238 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1244 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1249 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1256 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1257 SDPatternOperator OpNode>
1258 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1259 asm, "\t$Rd, $Rn, $Rm", "",
1260 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1264 let Inst{30-21} = 0b0011010110;
1265 let Inst{20-16} = Rm;
1266 let Inst{15-14} = 0b00;
1267 let Inst{13-10} = opc;
1272 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1273 SDPatternOperator OpNode>
1274 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1275 let Inst{10} = isSigned;
1278 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1279 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1280 Sched<[WriteID32, ReadID, ReadID]> {
1283 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1284 Sched<[WriteID64, ReadID, ReadID]> {
1289 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1290 SDPatternOperator OpNode = null_frag>
1291 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1292 Sched<[WriteIS, ReadI]> {
1293 let Inst{11-10} = shift_type;
1296 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1297 def Wr : BaseShift<shift_type, GPR32, asm> {
1301 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1305 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1306 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1307 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1309 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1310 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1312 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1313 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1315 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1316 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1319 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1320 : InstAlias<asm#" $dst, $src1, $src2",
1321 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
1323 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1324 RegisterClass addtype, string asm,
1326 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1327 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1332 let Inst{30-24} = 0b0011011;
1333 let Inst{23-21} = opc;
1334 let Inst{20-16} = Rm;
1335 let Inst{15} = isSub;
1336 let Inst{14-10} = Ra;
1341 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1342 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1343 [(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
1344 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1348 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1349 [(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
1350 Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
1355 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1356 SDNode AccNode, SDNode ExtNode>
1357 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1358 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1359 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1360 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1364 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1365 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1366 asm, "\t$Rd, $Rn, $Rm", "",
1367 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1368 Sched<[WriteIM64, ReadIM, ReadIM]> {
1372 let Inst{31-24} = 0b10011011;
1373 let Inst{23-21} = opc;
1374 let Inst{20-16} = Rm;
1379 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1380 // (i.e. all bits 1) but is ignored by the processor.
1381 let PostEncoderMethod = "fixMulHigh";
1384 class MulAccumWAlias<string asm, Instruction inst>
1385 : InstAlias<asm#" $dst, $src1, $src2",
1386 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1387 class MulAccumXAlias<string asm, Instruction inst>
1388 : InstAlias<asm#" $dst, $src1, $src2",
1389 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1390 class WideMulAccumAlias<string asm, Instruction inst>
1391 : InstAlias<asm#" $dst, $src1, $src2",
1392 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1394 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1395 SDPatternOperator OpNode, string asm>
1396 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1397 asm, "\t$Rd, $Rn, $Rm", "",
1398 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1399 Sched<[WriteISReg, ReadI, ReadISReg]> {
1405 let Inst{30-21} = 0b0011010110;
1406 let Inst{20-16} = Rm;
1407 let Inst{15-13} = 0b010;
1409 let Inst{11-10} = sz;
1412 let Predicates = [HasCRC];
1416 // Address generation.
1419 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1420 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1425 let Inst{31} = page;
1426 let Inst{30-29} = label{1-0};
1427 let Inst{28-24} = 0b10000;
1428 let Inst{23-5} = label{20-2};
1431 let DecoderMethod = "DecodeAdrInstruction";
1438 def movimm32_imm : Operand<i32> {
1439 let ParserMatchClass = Imm0_65535Operand;
1440 let EncoderMethod = "getMoveWideImmOpValue";
1441 let PrintMethod = "printHexImm";
1443 def movimm32_shift : Operand<i32> {
1444 let PrintMethod = "printShifter";
1445 let ParserMatchClass = MovImm32ShifterOperand;
1447 def movimm64_shift : Operand<i32> {
1448 let PrintMethod = "printShifter";
1449 let ParserMatchClass = MovImm64ShifterOperand;
1452 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1453 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1455 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1456 asm, "\t$Rd, $imm$shift", "", []>,
1461 let Inst{30-29} = opc;
1462 let Inst{28-23} = 0b100101;
1463 let Inst{22-21} = shift{5-4};
1464 let Inst{20-5} = imm;
1467 let DecoderMethod = "DecodeMoveImmInstruction";
1470 multiclass MoveImmediate<bits<2> opc, string asm> {
1471 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1475 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1480 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1481 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1483 : I<(outs regtype:$Rd),
1484 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1485 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1486 Sched<[WriteI, ReadI]> {
1490 let Inst{30-29} = opc;
1491 let Inst{28-23} = 0b100101;
1492 let Inst{22-21} = shift{5-4};
1493 let Inst{20-5} = imm;
1496 let DecoderMethod = "DecodeMoveImmInstruction";
1499 multiclass InsertImmediate<bits<2> opc, string asm> {
1500 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1504 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1513 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1514 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1515 string asm, SDPatternOperator OpNode>
1516 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1517 asm, "\t$Rd, $Rn, $imm", "",
1518 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1519 Sched<[WriteI, ReadI]> {
1523 let Inst{30} = isSub;
1524 let Inst{29} = setFlags;
1525 let Inst{28-24} = 0b10001;
1526 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1527 let Inst{21-10} = imm{11-0};
1530 let DecoderMethod = "DecodeBaseAddSubImm";
1533 class BaseAddSubRegPseudo<RegisterClass regtype,
1534 SDPatternOperator OpNode>
1535 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1536 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1537 Sched<[WriteI, ReadI, ReadI]>;
1539 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1540 arith_shifted_reg shifted_regtype, string asm,
1541 SDPatternOperator OpNode>
1542 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1543 asm, "\t$Rd, $Rn, $Rm", "",
1544 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1545 Sched<[WriteISReg, ReadI, ReadISReg]> {
1546 // The operands are in order to match the 'addr' MI operands, so we
1547 // don't need an encoder method and by-name matching. Just use the default
1548 // in-order handling. Since we're using by-order, make sure the names
1554 let Inst{30} = isSub;
1555 let Inst{29} = setFlags;
1556 let Inst{28-24} = 0b01011;
1557 let Inst{23-22} = shift{7-6};
1559 let Inst{20-16} = src2;
1560 let Inst{15-10} = shift{5-0};
1561 let Inst{9-5} = src1;
1562 let Inst{4-0} = dst;
1564 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1567 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1568 RegisterClass src1Regtype, Operand src2Regtype,
1569 string asm, SDPatternOperator OpNode>
1570 : I<(outs dstRegtype:$R1),
1571 (ins src1Regtype:$R2, src2Regtype:$R3),
1572 asm, "\t$R1, $R2, $R3", "",
1573 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1574 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1579 let Inst{30} = isSub;
1580 let Inst{29} = setFlags;
1581 let Inst{28-24} = 0b01011;
1582 let Inst{23-21} = 0b001;
1583 let Inst{20-16} = Rm;
1584 let Inst{15-13} = ext{5-3};
1585 let Inst{12-10} = ext{2-0};
1589 let DecoderMethod = "DecodeAddSubERegInstruction";
1592 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1593 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1594 RegisterClass src1Regtype, RegisterClass src2Regtype,
1595 Operand ext_op, string asm>
1596 : I<(outs dstRegtype:$Rd),
1597 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1598 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1599 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1604 let Inst{30} = isSub;
1605 let Inst{29} = setFlags;
1606 let Inst{28-24} = 0b01011;
1607 let Inst{23-21} = 0b001;
1608 let Inst{20-16} = Rm;
1609 let Inst{15} = ext{5};
1610 let Inst{12-10} = ext{2-0};
1614 let DecoderMethod = "DecodeAddSubERegInstruction";
1617 // Aliases for register+register add/subtract.
1618 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1619 RegisterClass src1Regtype, RegisterClass src2Regtype,
1621 : InstAlias<asm#" $dst, $src1, $src2",
1622 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1625 multiclass AddSub<bit isSub, string mnemonic,
1626 SDPatternOperator OpNode = null_frag> {
1627 let hasSideEffects = 0 in {
1628 // Add/Subtract immediate
1629 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1633 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1638 // Add/Subtract register - Only used for CodeGen
1639 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1640 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1642 // Add/Subtract shifted register
1643 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1647 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1653 // Add/Subtract extended register
1654 let AddedComplexity = 1, hasSideEffects = 0 in {
1655 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1656 arith_extended_reg32<i32>, mnemonic, OpNode> {
1659 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1660 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1665 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1666 arith_extendlsl64, mnemonic> {
1667 // UXTX and SXTX only.
1668 let Inst{14-13} = 0b11;
1672 // Register/register aliases with no shift when SP is not used.
1673 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1674 GPR32, GPR32, GPR32, 0>;
1675 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1676 GPR64, GPR64, GPR64, 0>;
1678 // Register/register aliases with no shift when either the destination or
1679 // first source register is SP.
1680 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1681 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1682 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1683 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1684 def : AddSubRegAlias<mnemonic,
1685 !cast<Instruction>(NAME#"Xrx64"),
1686 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1687 def : AddSubRegAlias<mnemonic,
1688 !cast<Instruction>(NAME#"Xrx64"),
1689 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1692 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
1693 let isCompare = 1, Defs = [NZCV] in {
1694 // Add/Subtract immediate
1695 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1699 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1704 // Add/Subtract register
1705 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1706 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1708 // Add/Subtract shifted register
1709 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1713 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1718 // Add/Subtract extended register
1719 let AddedComplexity = 1 in {
1720 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1721 arith_extended_reg32<i32>, mnemonic, OpNode> {
1724 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1725 arith_extended_reg32<i64>, mnemonic, OpNode> {
1730 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1731 arith_extendlsl64, mnemonic> {
1732 // UXTX and SXTX only.
1733 let Inst{14-13} = 0b11;
1739 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Wri")
1740 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
1741 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Xri")
1742 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
1743 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
1744 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1745 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
1746 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1747 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
1748 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1749 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
1750 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1751 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
1752 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1754 // Compare shorthands
1755 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1756 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1757 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1758 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1759 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrx")
1760 WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
1761 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
1762 XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
1764 // Register/register aliases with no shift when SP is not used.
1765 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1766 GPR32, GPR32, GPR32, 0>;
1767 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1768 GPR64, GPR64, GPR64, 0>;
1770 // Register/register aliases with no shift when the first source register
1772 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1773 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1774 def : AddSubRegAlias<mnemonic,
1775 !cast<Instruction>(NAME#"Xrx64"),
1776 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1782 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1784 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
1786 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1788 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1789 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1790 Sched<[WriteExtr, ReadExtrHi]> {
1796 let Inst{30-23} = 0b00100111;
1798 let Inst{20-16} = Rm;
1799 let Inst{15-10} = imm;
1804 multiclass ExtractImm<string asm> {
1805 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1807 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1810 // imm<5> must be zero.
1813 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1815 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1826 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1827 class BaseBitfieldImm<bits<2> opc,
1828 RegisterClass regtype, Operand imm_type, string asm>
1829 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1830 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1831 Sched<[WriteIS, ReadI]> {
1837 let Inst{30-29} = opc;
1838 let Inst{28-23} = 0b100110;
1839 let Inst{21-16} = immr;
1840 let Inst{15-10} = imms;
1845 multiclass BitfieldImm<bits<2> opc, string asm> {
1846 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1849 // imms<5> and immr<5> must be zero, else ReservedValue().
1853 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1859 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1860 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1861 RegisterClass regtype, Operand imm_type, string asm>
1862 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1864 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1865 Sched<[WriteIS, ReadI]> {
1871 let Inst{30-29} = opc;
1872 let Inst{28-23} = 0b100110;
1873 let Inst{21-16} = immr;
1874 let Inst{15-10} = imms;
1879 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1880 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1883 // imms<5> and immr<5> must be zero, else ReservedValue().
1887 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1897 // Logical (immediate)
1898 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1899 RegisterClass sregtype, Operand imm_type, string asm,
1901 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1902 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1903 Sched<[WriteI, ReadI]> {
1907 let Inst{30-29} = opc;
1908 let Inst{28-23} = 0b100100;
1909 let Inst{22} = imm{12};
1910 let Inst{21-16} = imm{11-6};
1911 let Inst{15-10} = imm{5-0};
1915 let DecoderMethod = "DecodeLogicalImmInstruction";
1918 // Logical (shifted register)
1919 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1920 logical_shifted_reg shifted_regtype, string asm,
1922 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1923 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1924 Sched<[WriteISReg, ReadI, ReadISReg]> {
1925 // The operands are in order to match the 'addr' MI operands, so we
1926 // don't need an encoder method and by-name matching. Just use the default
1927 // in-order handling. Since we're using by-order, make sure the names
1933 let Inst{30-29} = opc;
1934 let Inst{28-24} = 0b01010;
1935 let Inst{23-22} = shift{7-6};
1937 let Inst{20-16} = src2;
1938 let Inst{15-10} = shift{5-0};
1939 let Inst{9-5} = src1;
1940 let Inst{4-0} = dst;
1942 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1945 // Aliases for register+register logical instructions.
1946 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
1947 : InstAlias<asm#" $dst, $src1, $src2",
1948 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
1950 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
1952 let AddedComplexity = 6 in
1953 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
1954 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1955 logical_imm32:$imm))]> {
1957 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1959 let AddedComplexity = 6 in
1960 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
1961 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1962 logical_imm64:$imm))]> {
1966 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1967 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
1968 logical_imm32_not:$imm), 0>;
1969 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1970 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
1971 logical_imm64_not:$imm), 0>;
1974 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode,
1976 let isCompare = 1, Defs = [NZCV] in {
1977 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
1978 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
1980 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1982 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
1983 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
1986 } // end Defs = [NZCV]
1988 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1989 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
1990 logical_imm32_not:$imm), 0>;
1991 def : InstAlias<Alias # " $Rd, $Rn, $imm",
1992 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
1993 logical_imm64_not:$imm), 0>;
1996 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
1997 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1998 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1999 Sched<[WriteI, ReadI, ReadI]>;
2001 // Split from LogicalImm as not all instructions have both.
2002 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
2003 SDPatternOperator OpNode> {
2004 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2005 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2007 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2008 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2009 logical_shifted_reg32:$Rm))]> {
2012 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2013 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2014 logical_shifted_reg64:$Rm))]> {
2018 def : LogicalRegAlias<mnemonic,
2019 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2020 def : LogicalRegAlias<mnemonic,
2021 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2024 // Split from LogicalReg to allow setting NZCV Defs
2025 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
2026 SDPatternOperator OpNode = null_frag> {
2027 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
2028 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
2029 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
2031 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
2032 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2035 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2036 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2041 def : LogicalRegAlias<mnemonic,
2042 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2043 def : LogicalRegAlias<mnemonic,
2044 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2048 // Conditionally set flags
2051 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2052 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
2053 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
2054 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
2055 Sched<[WriteI, ReadI]> {
2065 let Inst{29-21} = 0b111010010;
2066 let Inst{20-16} = imm;
2067 let Inst{15-12} = cond;
2068 let Inst{11-10} = 0b10;
2071 let Inst{3-0} = nzcv;
2074 multiclass CondSetFlagsImm<bit op, string asm> {
2075 def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
2078 def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
2083 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2084 class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
2085 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
2086 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
2087 Sched<[WriteI, ReadI, ReadI]> {
2097 let Inst{29-21} = 0b111010010;
2098 let Inst{20-16} = Rm;
2099 let Inst{15-12} = cond;
2100 let Inst{11-10} = 0b00;
2103 let Inst{3-0} = nzcv;
2106 multiclass CondSetFlagsReg<bit op, string asm> {
2107 def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
2110 def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
2116 // Conditional select
2119 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
2120 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2121 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2123 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2124 Sched<[WriteI, ReadI, ReadI]> {
2133 let Inst{29-21} = 0b011010100;
2134 let Inst{20-16} = Rm;
2135 let Inst{15-12} = cond;
2136 let Inst{11-10} = op2;
2141 multiclass CondSelect<bit op, bits<2> op2, string asm> {
2142 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2145 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2150 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2152 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2153 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2155 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2156 (i32 imm:$cond), NZCV))]>,
2157 Sched<[WriteI, ReadI, ReadI]> {
2166 let Inst{29-21} = 0b011010100;
2167 let Inst{20-16} = Rm;
2168 let Inst{15-12} = cond;
2169 let Inst{11-10} = op2;
2174 def inv_cond_XFORM : SDNodeXForm<imm, [{
2175 AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
2176 return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), MVT::i32);
2179 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2180 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2183 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2187 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2188 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2189 (inv_cond_XFORM imm:$cond))>;
2191 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2192 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2193 (inv_cond_XFORM imm:$cond))>;
2197 // Special Mask Value
2199 def maski8_or_more : Operand<i32>,
2200 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2202 def maski16_or_more : Operand<i32>,
2203 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2211 // (unsigned immediate)
2212 // Indexed for 8-bit registers. offset is in range [0,4095].
2213 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2214 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
2215 def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
2216 def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
2217 def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
2219 class UImm12OffsetOperand<int Scale> : AsmOperandClass {
2220 let Name = "UImm12Offset" # Scale;
2221 let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
2222 let PredicateMethod = "isUImm12Offset<" # Scale # ">";
2223 let DiagnosticType = "InvalidMemoryIndexed" # Scale;
2226 def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>;
2227 def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>;
2228 def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>;
2229 def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>;
2230 def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>;
2232 class uimm12_scaled<int Scale> : Operand<i64> {
2233 let ParserMatchClass
2234 = !cast<AsmOperandClass>("UImm12OffsetScale" # Scale # "Operand");
2236 = "getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale" # Scale # ">";
2237 let PrintMethod = "printUImm12Offset<" # Scale # ">";
2240 def uimm12s1 : uimm12_scaled<1>;
2241 def uimm12s2 : uimm12_scaled<2>;
2242 def uimm12s4 : uimm12_scaled<4>;
2243 def uimm12s8 : uimm12_scaled<8>;
2244 def uimm12s16 : uimm12_scaled<16>;
2246 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2247 string asm, list<dag> pattern>
2248 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2254 let Inst{31-30} = sz;
2255 let Inst{29-27} = 0b111;
2257 let Inst{25-24} = 0b01;
2258 let Inst{23-22} = opc;
2259 let Inst{21-10} = offset;
2263 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2266 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2267 Operand indextype, string asm, list<dag> pattern> {
2268 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2269 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2270 (ins GPR64sp:$Rn, indextype:$offset),
2274 def : InstAlias<asm # " $Rt, [$Rn]",
2275 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2278 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2279 Operand indextype, string asm, list<dag> pattern> {
2280 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2281 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2282 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2286 def : InstAlias<asm # " $Rt, [$Rn]",
2287 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2290 def PrefetchOperand : AsmOperandClass {
2291 let Name = "Prefetch";
2292 let ParserMethod = "tryParsePrefetch";
2294 def prfop : Operand<i32> {
2295 let PrintMethod = "printPrefetchOp";
2296 let ParserMatchClass = PrefetchOperand;
2299 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2300 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2301 : BaseLoadStoreUI<sz, V, opc,
2302 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2310 // Load literal address: 19-bit immediate. The low two bits of the target
2311 // offset are implied zero and so are not part of the immediate.
2312 def am_ldrlit : Operand<OtherVT> {
2313 let EncoderMethod = "getLoadLiteralOpValue";
2314 let DecoderMethod = "DecodePCRelLabel19";
2315 let PrintMethod = "printAlignedLabel";
2316 let ParserMatchClass = PCRelLabel19Operand;
2319 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2320 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2321 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2322 asm, "\t$Rt, $label", "", []>,
2326 let Inst{31-30} = opc;
2327 let Inst{29-27} = 0b011;
2329 let Inst{25-24} = 0b00;
2330 let Inst{23-5} = label;
2334 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2335 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2336 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2337 asm, "\t$Rt, $label", "", pat>,
2341 let Inst{31-30} = opc;
2342 let Inst{29-27} = 0b011;
2344 let Inst{25-24} = 0b00;
2345 let Inst{23-5} = label;
2350 // Load/store register offset
2353 def ro_Xindexed8 : ComplexPattern<i64, 4, "SelectAddrModeXRO<8>", []>;
2354 def ro_Xindexed16 : ComplexPattern<i64, 4, "SelectAddrModeXRO<16>", []>;
2355 def ro_Xindexed32 : ComplexPattern<i64, 4, "SelectAddrModeXRO<32>", []>;
2356 def ro_Xindexed64 : ComplexPattern<i64, 4, "SelectAddrModeXRO<64>", []>;
2357 def ro_Xindexed128 : ComplexPattern<i64, 4, "SelectAddrModeXRO<128>", []>;
2359 def ro_Windexed8 : ComplexPattern<i64, 4, "SelectAddrModeWRO<8>", []>;
2360 def ro_Windexed16 : ComplexPattern<i64, 4, "SelectAddrModeWRO<16>", []>;
2361 def ro_Windexed32 : ComplexPattern<i64, 4, "SelectAddrModeWRO<32>", []>;
2362 def ro_Windexed64 : ComplexPattern<i64, 4, "SelectAddrModeWRO<64>", []>;
2363 def ro_Windexed128 : ComplexPattern<i64, 4, "SelectAddrModeWRO<128>", []>;
2365 class MemExtendOperand<string Reg, int Width> : AsmOperandClass {
2366 let Name = "Mem" # Reg # "Extend" # Width;
2367 let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">";
2368 let RenderMethod = "addMemExtendOperands";
2369 let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width;
2372 def MemWExtend8Operand : MemExtendOperand<"W", 8> {
2373 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2374 // the trivial shift.
2375 let RenderMethod = "addMemExtend8Operands";
2377 def MemWExtend16Operand : MemExtendOperand<"W", 16>;
2378 def MemWExtend32Operand : MemExtendOperand<"W", 32>;
2379 def MemWExtend64Operand : MemExtendOperand<"W", 64>;
2380 def MemWExtend128Operand : MemExtendOperand<"W", 128>;
2382 def MemXExtend8Operand : MemExtendOperand<"X", 8> {
2383 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2384 // the trivial shift.
2385 let RenderMethod = "addMemExtend8Operands";
2387 def MemXExtend16Operand : MemExtendOperand<"X", 16>;
2388 def MemXExtend32Operand : MemExtendOperand<"X", 32>;
2389 def MemXExtend64Operand : MemExtendOperand<"X", 64>;
2390 def MemXExtend128Operand : MemExtendOperand<"X", 128>;
2392 class ro_extend<AsmOperandClass ParserClass, string Reg, int Width>
2394 let ParserMatchClass = ParserClass;
2395 let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">";
2396 let DecoderMethod = "DecodeMemExtend";
2397 let EncoderMethod = "getMemExtendOpValue";
2398 let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift);
2401 def ro_Wextend8 : ro_extend<MemWExtend8Operand, "w", 8>;
2402 def ro_Wextend16 : ro_extend<MemWExtend16Operand, "w", 16>;
2403 def ro_Wextend32 : ro_extend<MemWExtend32Operand, "w", 32>;
2404 def ro_Wextend64 : ro_extend<MemWExtend64Operand, "w", 64>;
2405 def ro_Wextend128 : ro_extend<MemWExtend128Operand, "w", 128>;
2407 def ro_Xextend8 : ro_extend<MemXExtend8Operand, "x", 8>;
2408 def ro_Xextend16 : ro_extend<MemXExtend16Operand, "x", 16>;
2409 def ro_Xextend32 : ro_extend<MemXExtend32Operand, "x", 32>;
2410 def ro_Xextend64 : ro_extend<MemXExtend64Operand, "x", 64>;
2411 def ro_Xextend128 : ro_extend<MemXExtend128Operand, "x", 128>;
2413 class ROAddrMode<ComplexPattern windex, ComplexPattern xindex,
2414 Operand wextend, Operand xextend> {
2415 // CodeGen-level pattern covering the entire addressing mode.
2416 ComplexPattern Wpat = windex;
2417 ComplexPattern Xpat = xindex;
2419 // Asm-level Operand covering the valid "uxtw #3" style syntax.
2420 Operand Wext = wextend;
2421 Operand Xext = xextend;
2424 def ro8 : ROAddrMode<ro_Windexed8, ro_Xindexed8, ro_Wextend8, ro_Xextend8>;
2425 def ro16 : ROAddrMode<ro_Windexed16, ro_Xindexed16, ro_Wextend16, ro_Xextend16>;
2426 def ro32 : ROAddrMode<ro_Windexed32, ro_Xindexed32, ro_Wextend32, ro_Xextend32>;
2427 def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>;
2428 def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
2431 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2432 string asm, dag ins, dag outs, list<dag> pat>
2433 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2438 let Inst{31-30} = sz;
2439 let Inst{29-27} = 0b111;
2441 let Inst{25-24} = 0b00;
2442 let Inst{23-22} = opc;
2444 let Inst{20-16} = Rm;
2445 let Inst{15} = extend{1}; // sign extend Rm?
2447 let Inst{12} = extend{0}; // do shift?
2448 let Inst{11-10} = 0b10;
2453 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2454 : InstAlias<asm # " $Rt, [$Rn, $Rm]",
2455 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2457 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2458 string asm, ValueType Ty, SDPatternOperator loadop> {
2459 let AddedComplexity = 10 in
2460 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2462 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2463 [(set (Ty regtype:$Rt),
2464 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2465 ro_Wextend8:$extend)))]>,
2466 Sched<[WriteLDIdx, ReadAdrBase]> {
2470 let AddedComplexity = 10 in
2471 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2473 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2474 [(set (Ty regtype:$Rt),
2475 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2476 ro_Xextend8:$extend)))]>,
2477 Sched<[WriteLDIdx, ReadAdrBase]> {
2481 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2484 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2485 string asm, ValueType Ty, SDPatternOperator storeop> {
2486 let AddedComplexity = 10 in
2487 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2488 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2489 [(storeop (Ty regtype:$Rt),
2490 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2491 ro_Wextend8:$extend))]>,
2492 Sched<[WriteSTIdx, ReadAdrBase]> {
2496 let AddedComplexity = 10 in
2497 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2498 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2499 [(storeop (Ty regtype:$Rt),
2500 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2501 ro_Xextend8:$extend))]>,
2502 Sched<[WriteSTIdx, ReadAdrBase]> {
2506 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2509 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2510 string asm, dag ins, dag outs, list<dag> pat>
2511 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2516 let Inst{31-30} = sz;
2517 let Inst{29-27} = 0b111;
2519 let Inst{25-24} = 0b00;
2520 let Inst{23-22} = opc;
2522 let Inst{20-16} = Rm;
2523 let Inst{15} = extend{1}; // sign extend Rm?
2525 let Inst{12} = extend{0}; // do shift?
2526 let Inst{11-10} = 0b10;
2531 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2532 string asm, ValueType Ty, SDPatternOperator loadop> {
2533 let AddedComplexity = 10 in
2534 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2535 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2536 [(set (Ty regtype:$Rt),
2537 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2538 ro_Wextend16:$extend)))]>,
2539 Sched<[WriteLDIdx, ReadAdrBase]> {
2543 let AddedComplexity = 10 in
2544 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2545 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2546 [(set (Ty regtype:$Rt),
2547 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2548 ro_Xextend16:$extend)))]>,
2549 Sched<[WriteLDIdx, ReadAdrBase]> {
2553 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2556 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2557 string asm, ValueType Ty, SDPatternOperator storeop> {
2558 let AddedComplexity = 10 in
2559 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2560 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2561 [(storeop (Ty regtype:$Rt),
2562 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2563 ro_Wextend16:$extend))]>,
2564 Sched<[WriteSTIdx, ReadAdrBase]> {
2568 let AddedComplexity = 10 in
2569 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2570 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2571 [(storeop (Ty regtype:$Rt),
2572 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2573 ro_Xextend16:$extend))]>,
2574 Sched<[WriteSTIdx, ReadAdrBase]> {
2578 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2581 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2582 string asm, dag ins, dag outs, list<dag> pat>
2583 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2588 let Inst{31-30} = sz;
2589 let Inst{29-27} = 0b111;
2591 let Inst{25-24} = 0b00;
2592 let Inst{23-22} = opc;
2594 let Inst{20-16} = Rm;
2595 let Inst{15} = extend{1}; // sign extend Rm?
2597 let Inst{12} = extend{0}; // do shift?
2598 let Inst{11-10} = 0b10;
2603 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2604 string asm, ValueType Ty, SDPatternOperator loadop> {
2605 let AddedComplexity = 10 in
2606 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2607 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2608 [(set (Ty regtype:$Rt),
2609 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2610 ro_Wextend32:$extend)))]>,
2611 Sched<[WriteLDIdx, ReadAdrBase]> {
2615 let AddedComplexity = 10 in
2616 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2617 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2618 [(set (Ty regtype:$Rt),
2619 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2620 ro_Xextend32:$extend)))]>,
2621 Sched<[WriteLDIdx, ReadAdrBase]> {
2625 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2628 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2629 string asm, ValueType Ty, SDPatternOperator storeop> {
2630 let AddedComplexity = 10 in
2631 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2632 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2633 [(storeop (Ty regtype:$Rt),
2634 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2635 ro_Wextend32:$extend))]>,
2636 Sched<[WriteSTIdx, ReadAdrBase]> {
2640 let AddedComplexity = 10 in
2641 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2642 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2643 [(storeop (Ty regtype:$Rt),
2644 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2645 ro_Xextend32:$extend))]>,
2646 Sched<[WriteSTIdx, ReadAdrBase]> {
2650 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2653 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2654 string asm, dag ins, dag outs, list<dag> pat>
2655 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2660 let Inst{31-30} = sz;
2661 let Inst{29-27} = 0b111;
2663 let Inst{25-24} = 0b00;
2664 let Inst{23-22} = opc;
2666 let Inst{20-16} = Rm;
2667 let Inst{15} = extend{1}; // sign extend Rm?
2669 let Inst{12} = extend{0}; // do shift?
2670 let Inst{11-10} = 0b10;
2675 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2676 string asm, ValueType Ty, SDPatternOperator loadop> {
2677 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2678 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2679 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2680 [(set (Ty regtype:$Rt),
2681 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2682 ro_Wextend64:$extend)))]>,
2683 Sched<[WriteLDIdx, ReadAdrBase]> {
2687 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2688 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2689 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2690 [(set (Ty regtype:$Rt),
2691 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2692 ro_Xextend64:$extend)))]>,
2693 Sched<[WriteLDIdx, ReadAdrBase]> {
2697 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2700 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2701 string asm, ValueType Ty, SDPatternOperator storeop> {
2702 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2703 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2704 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2705 [(storeop (Ty regtype:$Rt),
2706 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2707 ro_Wextend64:$extend))]>,
2708 Sched<[WriteSTIdx, ReadAdrBase]> {
2712 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2713 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2714 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2715 [(storeop (Ty regtype:$Rt),
2716 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2717 ro_Xextend64:$extend))]>,
2718 Sched<[WriteSTIdx, ReadAdrBase]> {
2722 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2725 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2726 string asm, dag ins, dag outs, list<dag> pat>
2727 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2732 let Inst{31-30} = sz;
2733 let Inst{29-27} = 0b111;
2735 let Inst{25-24} = 0b00;
2736 let Inst{23-22} = opc;
2738 let Inst{20-16} = Rm;
2739 let Inst{15} = extend{1}; // sign extend Rm?
2741 let Inst{12} = extend{0}; // do shift?
2742 let Inst{11-10} = 0b10;
2747 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2748 string asm, ValueType Ty, SDPatternOperator loadop> {
2749 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2750 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2751 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2752 [(set (Ty regtype:$Rt),
2753 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2754 ro_Wextend128:$extend)))]>,
2755 Sched<[WriteLDIdx, ReadAdrBase]> {
2759 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2760 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2761 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2762 [(set (Ty regtype:$Rt),
2763 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2764 ro_Xextend128:$extend)))]>,
2765 Sched<[WriteLDIdx, ReadAdrBase]> {
2769 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2772 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2773 string asm, ValueType Ty, SDPatternOperator storeop> {
2774 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2775 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2776 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2777 [(storeop (Ty regtype:$Rt),
2778 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2779 ro_Wextend128:$extend))]>,
2780 Sched<[WriteSTIdx, ReadAdrBase]> {
2784 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2785 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2786 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2787 [(storeop (Ty regtype:$Rt),
2788 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2789 ro_Xextend128:$extend))]>,
2790 Sched<[WriteSTIdx, ReadAdrBase]> {
2794 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2797 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2798 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2799 string asm, list<dag> pat>
2800 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2806 let Inst{31-30} = sz;
2807 let Inst{29-27} = 0b111;
2809 let Inst{25-24} = 0b00;
2810 let Inst{23-22} = opc;
2812 let Inst{20-16} = Rm;
2813 let Inst{15} = extend{1}; // sign extend Rm?
2815 let Inst{12} = extend{0}; // do shift?
2816 let Inst{11-10} = 0b10;
2821 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2822 def roW : BasePrefetchRO<sz, V, opc, (outs),
2823 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2824 asm, [(AArch64Prefetch imm:$Rt,
2825 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2826 ro_Wextend64:$extend))]> {
2830 def roX : BasePrefetchRO<sz, V, opc, (outs),
2831 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2832 asm, [(AArch64Prefetch imm:$Rt,
2833 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2834 ro_Xextend64:$extend))]> {
2838 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2839 (!cast<Instruction>(NAME # "roX") prfop:$Rt,
2840 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2844 // Load/store unscaled immediate
2847 def am_unscaled8 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2848 def am_unscaled16 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2849 def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2850 def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2851 def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2853 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2854 string asm, list<dag> pattern>
2855 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2859 let Inst{31-30} = sz;
2860 let Inst{29-27} = 0b111;
2862 let Inst{25-24} = 0b00;
2863 let Inst{23-22} = opc;
2865 let Inst{20-12} = offset;
2866 let Inst{11-10} = 0b00;
2870 let DecoderMethod = "DecodeSignedLdStInstruction";
2873 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2874 string asm, list<dag> pattern> {
2875 let AddedComplexity = 1 in // try this before LoadUI
2876 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2877 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
2880 def : InstAlias<asm # " $Rt, [$Rn]",
2881 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2884 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2885 string asm, list<dag> pattern> {
2886 let AddedComplexity = 1 in // try this before StoreUI
2887 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2888 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2892 def : InstAlias<asm # " $Rt, [$Rn]",
2893 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2896 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
2898 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2899 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2900 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
2904 def : InstAlias<asm # " $Rt, [$Rn]",
2905 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
2909 // Load/store unscaled immediate, unprivileged
2912 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2913 dag oops, dag iops, string asm>
2914 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
2918 let Inst{31-30} = sz;
2919 let Inst{29-27} = 0b111;
2921 let Inst{25-24} = 0b00;
2922 let Inst{23-22} = opc;
2924 let Inst{20-12} = offset;
2925 let Inst{11-10} = 0b10;
2929 let DecoderMethod = "DecodeSignedLdStInstruction";
2932 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
2933 RegisterClass regtype, string asm> {
2934 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in
2935 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
2936 (ins GPR64sp:$Rn, simm9:$offset), asm>,
2939 def : InstAlias<asm # " $Rt, [$Rn]",
2940 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2943 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2944 RegisterClass regtype, string asm> {
2945 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2946 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
2947 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2951 def : InstAlias<asm # " $Rt, [$Rn]",
2952 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2956 // Load/store pre-indexed
2959 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2960 string asm, string cstr, list<dag> pat>
2961 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
2965 let Inst{31-30} = sz;
2966 let Inst{29-27} = 0b111;
2968 let Inst{25-24} = 0;
2969 let Inst{23-22} = opc;
2971 let Inst{20-12} = offset;
2972 let Inst{11-10} = 0b11;
2976 let DecoderMethod = "DecodeSignedLdStInstruction";
2979 let hasSideEffects = 0 in {
2980 let mayStore = 0, mayLoad = 1 in
2981 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2983 : BaseLoadStorePreIdx<sz, V, opc,
2984 (outs GPR64sp:$wback, regtype:$Rt),
2985 (ins GPR64sp:$Rn, simm9:$offset), asm,
2986 "$Rn = $wback", []>,
2987 Sched<[WriteLD, WriteAdr]>;
2989 let mayStore = 1, mayLoad = 0 in
2990 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2991 string asm, SDPatternOperator storeop, ValueType Ty>
2992 : BaseLoadStorePreIdx<sz, V, opc,
2993 (outs GPR64sp:$wback),
2994 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2995 asm, "$Rn = $wback",
2996 [(set GPR64sp:$wback,
2997 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
2998 Sched<[WriteAdr, WriteST]>;
2999 } // hasSideEffects = 0
3002 // Load/store post-indexed
3005 // (pre-index) load/stores.
3006 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
3007 string asm, string cstr, list<dag> pat>
3008 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
3012 let Inst{31-30} = sz;
3013 let Inst{29-27} = 0b111;
3015 let Inst{25-24} = 0b00;
3016 let Inst{23-22} = opc;
3018 let Inst{20-12} = offset;
3019 let Inst{11-10} = 0b01;
3023 let DecoderMethod = "DecodeSignedLdStInstruction";
3026 let hasSideEffects = 0 in {
3027 let mayStore = 0, mayLoad = 1 in
3028 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3030 : BaseLoadStorePostIdx<sz, V, opc,
3031 (outs GPR64sp:$wback, regtype:$Rt),
3032 (ins GPR64sp:$Rn, simm9:$offset),
3033 asm, "$Rn = $wback", []>,
3034 Sched<[WriteLD, WriteI]>;
3036 let mayStore = 1, mayLoad = 0 in
3037 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3038 string asm, SDPatternOperator storeop, ValueType Ty>
3039 : BaseLoadStorePostIdx<sz, V, opc,
3040 (outs GPR64sp:$wback),
3041 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3042 asm, "$Rn = $wback",
3043 [(set GPR64sp:$wback,
3044 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3045 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
3046 } // hasSideEffects = 0
3053 // (indexed, offset)
3055 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3057 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3062 let Inst{31-30} = opc;
3063 let Inst{29-27} = 0b101;
3065 let Inst{25-23} = 0b010;
3067 let Inst{21-15} = offset;
3068 let Inst{14-10} = Rt2;
3072 let DecoderMethod = "DecodePairLdStInstruction";
3075 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3076 Operand indextype, string asm> {
3077 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3078 def i : BaseLoadStorePairOffset<opc, V, 1,
3079 (outs regtype:$Rt, regtype:$Rt2),
3080 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3081 Sched<[WriteLD, WriteLDHi]>;
3083 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3084 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3089 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3090 Operand indextype, string asm> {
3091 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3092 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3093 (ins regtype:$Rt, regtype:$Rt2,
3094 GPR64sp:$Rn, indextype:$offset),
3098 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3099 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3104 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3106 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback", []> {
3111 let Inst{31-30} = opc;
3112 let Inst{29-27} = 0b101;
3114 let Inst{25-23} = 0b011;
3116 let Inst{21-15} = offset;
3117 let Inst{14-10} = Rt2;
3121 let DecoderMethod = "DecodePairLdStInstruction";
3124 let hasSideEffects = 0 in {
3125 let mayStore = 0, mayLoad = 1 in
3126 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3127 Operand indextype, string asm>
3128 : BaseLoadStorePairPreIdx<opc, V, 1,
3129 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3130 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3131 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3133 let mayStore = 1, mayLoad = 0 in
3134 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3135 Operand indextype, string asm>
3136 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3137 (ins regtype:$Rt, regtype:$Rt2,
3138 GPR64sp:$Rn, indextype:$offset),
3140 Sched<[WriteAdr, WriteSTP]>;
3141 } // hasSideEffects = 0
3145 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3147 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback", []> {
3152 let Inst{31-30} = opc;
3153 let Inst{29-27} = 0b101;
3155 let Inst{25-23} = 0b001;
3157 let Inst{21-15} = offset;
3158 let Inst{14-10} = Rt2;
3162 let DecoderMethod = "DecodePairLdStInstruction";
3165 let hasSideEffects = 0 in {
3166 let mayStore = 0, mayLoad = 1 in
3167 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3168 Operand idxtype, string asm>
3169 : BaseLoadStorePairPostIdx<opc, V, 1,
3170 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3171 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3172 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3174 let mayStore = 1, mayLoad = 0 in
3175 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3176 Operand idxtype, string asm>
3177 : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
3178 (ins GPR64sp:$wback, regtype:$Rt, regtype:$Rt2,
3179 GPR64sp:$Rn, idxtype:$offset),
3181 Sched<[WriteAdr, WriteSTP]>;
3182 } // hasSideEffects = 0
3186 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3188 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3193 let Inst{31-30} = opc;
3194 let Inst{29-27} = 0b101;
3196 let Inst{25-23} = 0b000;
3198 let Inst{21-15} = offset;
3199 let Inst{14-10} = Rt2;
3203 let DecoderMethod = "DecodePairLdStInstruction";
3206 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3207 Operand indextype, string asm> {
3208 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3209 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3210 (outs regtype:$Rt, regtype:$Rt2),
3211 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3212 Sched<[WriteLD, WriteLDHi]>;
3215 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3216 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3220 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3221 Operand indextype, string asm> {
3222 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in
3223 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3224 (ins regtype:$Rt, regtype:$Rt2,
3225 GPR64sp:$Rn, indextype:$offset),
3229 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3230 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3235 // Load/store exclusive
3238 // True exclusive operations write to and/or read from the system's exclusive
3239 // monitors, which as far as a compiler is concerned can be modelled as a
3240 // random shared memory address. Hence LoadExclusive mayStore.
3242 // Since these instructions have the undefined register bits set to 1 in
3243 // their canonical form, we need a post encoder method to set those bits
3244 // to 1 when encoding these instructions. We do this using the
3245 // fixLoadStoreExclusive function. This function has template parameters:
3247 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3249 // hasRs indicates that the instruction uses the Rs field, so we won't set
3250 // it to 1 (and the same for Rt2). We don't need template parameters for
3251 // the other register fields since Rt and Rn are always used.
3253 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3254 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3255 dag oops, dag iops, string asm, string operands>
3256 : I<oops, iops, asm, operands, "", []> {
3257 let Inst{31-30} = sz;
3258 let Inst{29-24} = 0b001000;
3264 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3267 // Neither Rs nor Rt2 operands.
3268 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3269 dag oops, dag iops, string asm, string operands>
3270 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3276 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3279 // Simple load acquires don't set the exclusive monitor
3280 let mayLoad = 1, mayStore = 0 in
3281 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3282 RegisterClass regtype, string asm>
3283 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3284 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3287 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3288 RegisterClass regtype, string asm>
3289 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3290 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3293 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3294 RegisterClass regtype, string asm>
3295 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3296 (outs regtype:$Rt, regtype:$Rt2),
3297 (ins GPR64sp0:$Rn), asm,
3298 "\t$Rt, $Rt2, [$Rn]">,
3299 Sched<[WriteLD, WriteLDHi]> {
3303 let Inst{14-10} = Rt2;
3307 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3310 // Simple store release operations do not check the exclusive monitor.
3311 let mayLoad = 0, mayStore = 1 in
3312 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3313 RegisterClass regtype, string asm>
3314 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3315 (ins regtype:$Rt, GPR64sp0:$Rn),
3316 asm, "\t$Rt, [$Rn]">,
3319 let mayLoad = 1, mayStore = 1 in
3320 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3321 RegisterClass regtype, string asm>
3322 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3323 (ins regtype:$Rt, GPR64sp0:$Rn),
3324 asm, "\t$Ws, $Rt, [$Rn]">,
3329 let Inst{20-16} = Ws;
3333 let Constraints = "@earlyclobber $Ws";
3334 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3337 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3338 RegisterClass regtype, string asm>
3339 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3341 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3342 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3348 let Inst{20-16} = Ws;
3349 let Inst{14-10} = Rt2;
3353 let Constraints = "@earlyclobber $Ws";
3357 // Exception generation
3360 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3361 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3362 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3365 let Inst{31-24} = 0b11010100;
3366 let Inst{23-21} = op1;
3367 let Inst{20-5} = imm;
3368 let Inst{4-2} = 0b000;
3372 let Predicates = [HasFPARMv8] in {
3375 // Floating point to integer conversion
3378 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3379 RegisterClass srcType, RegisterClass dstType,
3380 string asm, list<dag> pattern>
3381 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3382 asm, "\t$Rd, $Rn", "", pattern>,
3383 Sched<[WriteFCvt]> {
3386 let Inst{30-29} = 0b00;
3387 let Inst{28-24} = 0b11110;
3388 let Inst{23-22} = type;
3390 let Inst{20-19} = rmode;
3391 let Inst{18-16} = opcode;
3392 let Inst{15-10} = 0;
3397 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3398 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3399 RegisterClass srcType, RegisterClass dstType,
3400 Operand immType, string asm, list<dag> pattern>
3401 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3402 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3403 Sched<[WriteFCvt]> {
3407 let Inst{30-29} = 0b00;
3408 let Inst{28-24} = 0b11110;
3409 let Inst{23-22} = type;
3411 let Inst{20-19} = rmode;
3412 let Inst{18-16} = opcode;
3413 let Inst{15-10} = scale;
3418 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3419 SDPatternOperator OpN> {
3420 // Unscaled single-precision to 32-bit
3421 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3422 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3423 let Inst{31} = 0; // 32-bit GPR flag
3426 // Unscaled single-precision to 64-bit
3427 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3428 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3429 let Inst{31} = 1; // 64-bit GPR flag
3432 // Unscaled double-precision to 32-bit
3433 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3434 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3435 let Inst{31} = 0; // 32-bit GPR flag
3438 // Unscaled double-precision to 64-bit
3439 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3440 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3441 let Inst{31} = 1; // 64-bit GPR flag
3445 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3446 SDPatternOperator OpN> {
3447 // Scaled single-precision to 32-bit
3448 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3449 fixedpoint_f32_i32, asm,
3450 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3451 fixedpoint_f32_i32:$scale)))]> {
3452 let Inst{31} = 0; // 32-bit GPR flag
3456 // Scaled single-precision to 64-bit
3457 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3458 fixedpoint_f32_i64, asm,
3459 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3460 fixedpoint_f32_i64:$scale)))]> {
3461 let Inst{31} = 1; // 64-bit GPR flag
3464 // Scaled double-precision to 32-bit
3465 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3466 fixedpoint_f64_i32, asm,
3467 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3468 fixedpoint_f64_i32:$scale)))]> {
3469 let Inst{31} = 0; // 32-bit GPR flag
3473 // Scaled double-precision to 64-bit
3474 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3475 fixedpoint_f64_i64, asm,
3476 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3477 fixedpoint_f64_i64:$scale)))]> {
3478 let Inst{31} = 1; // 64-bit GPR flag
3483 // Integer to floating point conversion
3486 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3487 class BaseIntegerToFP<bit isUnsigned,
3488 RegisterClass srcType, RegisterClass dstType,
3489 Operand immType, string asm, list<dag> pattern>
3490 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3491 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3492 Sched<[WriteFCvt]> {
3496 let Inst{30-23} = 0b00111100;
3497 let Inst{21-17} = 0b00001;
3498 let Inst{16} = isUnsigned;
3499 let Inst{15-10} = scale;
3504 class BaseIntegerToFPUnscaled<bit isUnsigned,
3505 RegisterClass srcType, RegisterClass dstType,
3506 ValueType dvt, string asm, SDNode node>
3507 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3508 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3509 Sched<[WriteFCvt]> {
3513 let Inst{30-23} = 0b00111100;
3514 let Inst{21-17} = 0b10001;
3515 let Inst{16} = isUnsigned;
3516 let Inst{15-10} = 0b000000;
3521 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3523 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3524 let Inst{31} = 0; // 32-bit GPR flag
3525 let Inst{22} = 0; // 32-bit FPR flag
3528 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3529 let Inst{31} = 0; // 32-bit GPR flag
3530 let Inst{22} = 1; // 64-bit FPR flag
3533 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3534 let Inst{31} = 1; // 64-bit GPR flag
3535 let Inst{22} = 0; // 32-bit FPR flag
3538 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3539 let Inst{31} = 1; // 64-bit GPR flag
3540 let Inst{22} = 1; // 64-bit FPR flag
3544 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3546 (fdiv (node GPR32:$Rn),
3547 fixedpoint_f32_i32:$scale))]> {
3548 let Inst{31} = 0; // 32-bit GPR flag
3549 let Inst{22} = 0; // 32-bit FPR flag
3553 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3555 (fdiv (node GPR32:$Rn),
3556 fixedpoint_f64_i32:$scale))]> {
3557 let Inst{31} = 0; // 32-bit GPR flag
3558 let Inst{22} = 1; // 64-bit FPR flag
3562 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3564 (fdiv (node GPR64:$Rn),
3565 fixedpoint_f32_i64:$scale))]> {
3566 let Inst{31} = 1; // 64-bit GPR flag
3567 let Inst{22} = 0; // 32-bit FPR flag
3570 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3572 (fdiv (node GPR64:$Rn),
3573 fixedpoint_f64_i64:$scale))]> {
3574 let Inst{31} = 1; // 64-bit GPR flag
3575 let Inst{22} = 1; // 64-bit FPR flag
3580 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3583 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3584 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3585 RegisterClass srcType, RegisterClass dstType,
3587 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3588 // We use COPY_TO_REGCLASS for these bitconvert operations.
3589 // copyPhysReg() expands the resultant COPY instructions after
3590 // regalloc is done. This gives greater freedom for the allocator
3591 // and related passes (coalescing, copy propagation, et. al.) to
3592 // be more effective.
3593 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3594 Sched<[WriteFCopy]> {
3597 let Inst{30-23} = 0b00111100;
3599 let Inst{20-19} = rmode;
3600 let Inst{18-16} = opcode;
3601 let Inst{15-10} = 0b000000;
3606 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3607 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3608 RegisterClass srcType, RegisterOperand dstType, string asm,
3610 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3611 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3612 Sched<[WriteFCopy]> {
3615 let Inst{30-23} = 0b00111101;
3617 let Inst{20-19} = rmode;
3618 let Inst{18-16} = opcode;
3619 let Inst{15-10} = 0b000000;
3623 let DecoderMethod = "DecodeFMOVLaneInstruction";
3626 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3627 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3628 RegisterOperand srcType, RegisterClass dstType, string asm,
3630 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3631 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3632 Sched<[WriteFCopy]> {
3635 let Inst{30-23} = 0b00111101;
3637 let Inst{20-19} = rmode;
3638 let Inst{18-16} = opcode;
3639 let Inst{15-10} = 0b000000;
3643 let DecoderMethod = "DecodeFMOVLaneInstruction";
3648 multiclass UnscaledConversion<string asm> {
3649 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3650 let Inst{31} = 0; // 32-bit GPR flag
3651 let Inst{22} = 0; // 32-bit FPR flag
3654 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3655 let Inst{31} = 1; // 64-bit GPR flag
3656 let Inst{22} = 1; // 64-bit FPR flag
3659 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3660 let Inst{31} = 0; // 32-bit GPR flag
3661 let Inst{22} = 0; // 32-bit FPR flag
3664 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3665 let Inst{31} = 1; // 64-bit GPR flag
3666 let Inst{22} = 1; // 64-bit FPR flag
3669 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3675 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3683 // Floating point conversion
3686 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3687 RegisterClass srcType, string asm, list<dag> pattern>
3688 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3689 Sched<[WriteFCvt]> {
3692 let Inst{31-24} = 0b00011110;
3693 let Inst{23-22} = type;
3694 let Inst{21-17} = 0b10001;
3695 let Inst{16-15} = opcode;
3696 let Inst{14-10} = 0b10000;
3701 multiclass FPConversion<string asm> {
3702 // Double-precision to Half-precision
3703 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3704 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3706 // Double-precision to Single-precision
3707 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3708 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3710 // Half-precision to Double-precision
3711 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3712 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3714 // Half-precision to Single-precision
3715 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3716 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3718 // Single-precision to Double-precision
3719 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3720 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3722 // Single-precision to Half-precision
3723 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3724 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3728 // Single operand floating point data processing
3731 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3732 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3733 ValueType vt, string asm, SDPatternOperator node>
3734 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3735 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3739 let Inst{31-23} = 0b000111100;
3740 let Inst{21-19} = 0b100;
3741 let Inst{18-15} = opcode;
3742 let Inst{14-10} = 0b10000;
3747 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3748 SDPatternOperator node = null_frag> {
3749 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3750 let Inst{22} = 0; // 32-bit size flag
3753 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3754 let Inst{22} = 1; // 64-bit size flag
3759 // Two operand floating point data processing
3762 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3763 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3764 string asm, list<dag> pat>
3765 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3766 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3771 let Inst{31-23} = 0b000111100;
3773 let Inst{20-16} = Rm;
3774 let Inst{15-12} = opcode;
3775 let Inst{11-10} = 0b10;
3780 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3781 SDPatternOperator node = null_frag> {
3782 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3783 [(set (f32 FPR32:$Rd),
3784 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3785 let Inst{22} = 0; // 32-bit size flag
3788 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3789 [(set (f64 FPR64:$Rd),
3790 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3791 let Inst{22} = 1; // 64-bit size flag
3795 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3796 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3797 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3798 let Inst{22} = 0; // 32-bit size flag
3801 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3802 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3803 let Inst{22} = 1; // 64-bit size flag
3809 // Three operand floating point data processing
3812 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3813 RegisterClass regtype, string asm, list<dag> pat>
3814 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3815 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3816 Sched<[WriteFMul]> {
3821 let Inst{31-23} = 0b000111110;
3822 let Inst{21} = isNegated;
3823 let Inst{20-16} = Rm;
3824 let Inst{15} = isSub;
3825 let Inst{14-10} = Ra;
3830 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3831 SDPatternOperator node> {
3832 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3834 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3835 let Inst{22} = 0; // 32-bit size flag
3838 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3840 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3841 let Inst{22} = 1; // 64-bit size flag
3846 // Floating point data comparisons
3849 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3850 class BaseOneOperandFPComparison<bit signalAllNans,
3851 RegisterClass regtype, string asm,
3853 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3854 Sched<[WriteFCmp]> {
3856 let Inst{31-23} = 0b000111100;
3859 let Inst{15-10} = 0b001000;
3861 let Inst{4} = signalAllNans;
3862 let Inst{3-0} = 0b1000;
3864 // Rm should be 0b00000 canonically, but we need to accept any value.
3865 let PostEncoderMethod = "fixOneOperandFPComparison";
3868 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3869 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3870 string asm, list<dag> pat>
3871 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3872 Sched<[WriteFCmp]> {
3875 let Inst{31-23} = 0b000111100;
3877 let Inst{20-16} = Rm;
3878 let Inst{15-10} = 0b001000;
3880 let Inst{4} = signalAllNans;
3881 let Inst{3-0} = 0b0000;
3884 multiclass FPComparison<bit signalAllNans, string asm,
3885 SDPatternOperator OpNode = null_frag> {
3886 let Defs = [NZCV] in {
3887 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3888 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3892 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3893 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3897 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3898 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3902 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3903 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3910 // Floating point conditional comparisons
3913 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3914 class BaseFPCondComparison<bit signalAllNans,
3915 RegisterClass regtype, string asm>
3916 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3917 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3918 Sched<[WriteFCmp]> {
3924 let Inst{31-23} = 0b000111100;
3926 let Inst{20-16} = Rm;
3927 let Inst{15-12} = cond;
3928 let Inst{11-10} = 0b01;
3930 let Inst{4} = signalAllNans;
3931 let Inst{3-0} = nzcv;
3934 multiclass FPCondComparison<bit signalAllNans, string asm> {
3935 let Defs = [NZCV], Uses = [NZCV] in {
3936 def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
3940 def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
3943 } // Defs = [NZCV], Uses = [NZCV]
3947 // Floating point conditional select
3950 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
3951 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3952 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3954 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
3955 (i32 imm:$cond), NZCV))]>,
3962 let Inst{31-23} = 0b000111100;
3964 let Inst{20-16} = Rm;
3965 let Inst{15-12} = cond;
3966 let Inst{11-10} = 0b11;
3971 multiclass FPCondSelect<string asm> {
3972 let Uses = [NZCV] in {
3973 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
3977 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
3984 // Floating move immediate
3987 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
3988 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
3989 [(set regtype:$Rd, fpimmtype:$imm)]>,
3990 Sched<[WriteFImm]> {
3993 let Inst{31-23} = 0b000111100;
3995 let Inst{20-13} = imm;
3996 let Inst{12-5} = 0b10000000;
4000 multiclass FPMoveImmediate<string asm> {
4001 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
4005 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
4009 } // end of 'let Predicates = [HasFPARMv8]'
4011 //----------------------------------------------------------------------------
4013 //----------------------------------------------------------------------------
4015 let Predicates = [HasNEON] in {
4017 //----------------------------------------------------------------------------
4018 // AdvSIMD three register vector instructions
4019 //----------------------------------------------------------------------------
4021 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4022 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4023 RegisterOperand regtype, string asm, string kind,
4025 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4026 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4027 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4035 let Inst{28-24} = 0b01110;
4036 let Inst{23-22} = size;
4038 let Inst{20-16} = Rm;
4039 let Inst{15-11} = opcode;
4045 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4046 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4047 RegisterOperand regtype, string asm, string kind,
4049 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4050 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4051 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4059 let Inst{28-24} = 0b01110;
4060 let Inst{23-22} = size;
4062 let Inst{20-16} = Rm;
4063 let Inst{15-11} = opcode;
4069 // All operand sizes distinguished in the encoding.
4070 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4071 SDPatternOperator OpNode> {
4072 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4074 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4075 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4077 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4078 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4080 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4081 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4083 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4084 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4086 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4087 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4089 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4090 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
4092 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4095 // As above, but D sized elements unsupported.
4096 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4097 SDPatternOperator OpNode> {
4098 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4100 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4101 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4103 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4104 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4106 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4107 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4109 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4110 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4112 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4113 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4115 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4118 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4119 SDPatternOperator OpNode> {
4120 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4122 [(set (v8i8 V64:$dst),
4123 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4124 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4126 [(set (v16i8 V128:$dst),
4127 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4128 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
4130 [(set (v4i16 V64:$dst),
4131 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4132 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
4134 [(set (v8i16 V128:$dst),
4135 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4136 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
4138 [(set (v2i32 V64:$dst),
4139 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4140 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
4142 [(set (v4i32 V128:$dst),
4143 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4146 // As above, but only B sized elements supported.
4147 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4148 SDPatternOperator OpNode> {
4149 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4151 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4152 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4154 [(set (v16i8 V128:$Rd),
4155 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4158 // As above, but only S and D sized floating point elements supported.
4159 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
4160 string asm, SDPatternOperator OpNode> {
4161 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4163 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4164 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4166 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4167 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4169 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4172 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4174 SDPatternOperator OpNode> {
4175 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4177 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4178 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4180 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4181 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4183 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4186 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4187 string asm, SDPatternOperator OpNode> {
4188 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4190 [(set (v2f32 V64:$dst),
4191 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4192 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4194 [(set (v4f32 V128:$dst),
4195 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4196 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4198 [(set (v2f64 V128:$dst),
4199 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4202 // As above, but D and B sized elements unsupported.
4203 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4204 SDPatternOperator OpNode> {
4205 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4207 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4208 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4210 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4211 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4213 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4214 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4216 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4219 // Logical three vector ops share opcode bits, and only use B sized elements.
4220 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4221 SDPatternOperator OpNode = null_frag> {
4222 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4224 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4225 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4227 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4229 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4230 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4231 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4232 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4233 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4234 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4236 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4237 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4238 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4239 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4240 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4241 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4244 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4245 string asm, SDPatternOperator OpNode> {
4246 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4248 [(set (v8i8 V64:$dst),
4249 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4250 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4252 [(set (v16i8 V128:$dst),
4253 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4254 (v16i8 V128:$Rm)))]>;
4256 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4258 (!cast<Instruction>(NAME#"v8i8")
4259 V64:$LHS, V64:$MHS, V64:$RHS)>;
4260 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4262 (!cast<Instruction>(NAME#"v8i8")
4263 V64:$LHS, V64:$MHS, V64:$RHS)>;
4264 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4266 (!cast<Instruction>(NAME#"v8i8")
4267 V64:$LHS, V64:$MHS, V64:$RHS)>;
4269 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4270 (v8i16 V128:$RHS))),
4271 (!cast<Instruction>(NAME#"v16i8")
4272 V128:$LHS, V128:$MHS, V128:$RHS)>;
4273 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4274 (v4i32 V128:$RHS))),
4275 (!cast<Instruction>(NAME#"v16i8")
4276 V128:$LHS, V128:$MHS, V128:$RHS)>;
4277 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4278 (v2i64 V128:$RHS))),
4279 (!cast<Instruction>(NAME#"v16i8")
4280 V128:$LHS, V128:$MHS, V128:$RHS)>;
4284 //----------------------------------------------------------------------------
4285 // AdvSIMD two register vector instructions.
4286 //----------------------------------------------------------------------------
4288 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4289 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4290 RegisterOperand regtype, string asm, string dstkind,
4291 string srckind, list<dag> pattern>
4292 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4293 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4294 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4301 let Inst{28-24} = 0b01110;
4302 let Inst{23-22} = size;
4303 let Inst{21-17} = 0b10000;
4304 let Inst{16-12} = opcode;
4305 let Inst{11-10} = 0b10;
4310 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4311 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4312 RegisterOperand regtype, string asm, string dstkind,
4313 string srckind, list<dag> pattern>
4314 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4315 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4316 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4323 let Inst{28-24} = 0b01110;
4324 let Inst{23-22} = size;
4325 let Inst{21-17} = 0b10000;
4326 let Inst{16-12} = opcode;
4327 let Inst{11-10} = 0b10;
4332 // Supports B, H, and S element sizes.
4333 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4334 SDPatternOperator OpNode> {
4335 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4337 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4338 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4339 asm, ".16b", ".16b",
4340 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4341 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4343 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4344 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4346 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4347 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4349 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4350 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4352 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4355 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4356 RegisterOperand regtype, string asm, string dstkind,
4357 string srckind, string amount>
4358 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4359 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4360 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4366 let Inst{29-24} = 0b101110;
4367 let Inst{23-22} = size;
4368 let Inst{21-10} = 0b100001001110;
4373 multiclass SIMDVectorLShiftLongBySizeBHS {
4374 let neverHasSideEffects = 1 in {
4375 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4376 "shll", ".8h", ".8b", "8">;
4377 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4378 "shll2", ".8h", ".16b", "8">;
4379 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4380 "shll", ".4s", ".4h", "16">;
4381 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4382 "shll2", ".4s", ".8h", "16">;
4383 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4384 "shll", ".2d", ".2s", "32">;
4385 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4386 "shll2", ".2d", ".4s", "32">;
4390 // Supports all element sizes.
4391 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4392 SDPatternOperator OpNode> {
4393 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4395 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4396 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4398 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4399 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4401 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4402 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4404 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4405 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4407 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4408 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4410 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4413 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4414 SDPatternOperator OpNode> {
4415 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4417 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4419 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4421 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4422 (v16i8 V128:$Rn)))]>;
4423 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4425 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4426 (v4i16 V64:$Rn)))]>;
4427 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4429 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4430 (v8i16 V128:$Rn)))]>;
4431 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4433 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4434 (v2i32 V64:$Rn)))]>;
4435 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4437 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4438 (v4i32 V128:$Rn)))]>;
4441 // Supports all element sizes, except 1xD.
4442 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4443 SDPatternOperator OpNode> {
4444 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4446 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4447 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4448 asm, ".16b", ".16b",
4449 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4450 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4452 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4453 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4455 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4456 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4458 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4459 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4461 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4462 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4464 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4467 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4468 SDPatternOperator OpNode = null_frag> {
4469 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4471 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4472 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4473 asm, ".16b", ".16b",
4474 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4475 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4477 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4478 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4480 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4481 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4483 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4484 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4486 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4487 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4489 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4493 // Supports only B element sizes.
4494 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4495 SDPatternOperator OpNode> {
4496 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4498 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4499 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4500 asm, ".16b", ".16b",
4501 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4505 // Supports only B and H element sizes.
4506 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4507 SDPatternOperator OpNode> {
4508 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4510 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4511 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4512 asm, ".16b", ".16b",
4513 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4514 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4516 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4517 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4519 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4522 // Supports only S and D element sizes, uses high bit of the size field
4523 // as an extra opcode bit.
4524 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4525 SDPatternOperator OpNode> {
4526 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4528 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4529 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4531 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4532 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4534 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4537 // Supports only S element size.
4538 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4539 SDPatternOperator OpNode> {
4540 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4542 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4543 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4545 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4549 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4550 SDPatternOperator OpNode> {
4551 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4553 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4554 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4556 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4557 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4559 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4562 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4563 SDPatternOperator OpNode> {
4564 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4566 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4567 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4569 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4570 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4572 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4576 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4577 RegisterOperand inreg, RegisterOperand outreg,
4578 string asm, string outkind, string inkind,
4580 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4581 "{\t$Rd" # outkind # ", $Rn" # inkind #
4582 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4589 let Inst{28-24} = 0b01110;
4590 let Inst{23-22} = size;
4591 let Inst{21-17} = 0b10000;
4592 let Inst{16-12} = opcode;
4593 let Inst{11-10} = 0b10;
4598 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4599 RegisterOperand inreg, RegisterOperand outreg,
4600 string asm, string outkind, string inkind,
4602 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4603 "{\t$Rd" # outkind # ", $Rn" # inkind #
4604 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4611 let Inst{28-24} = 0b01110;
4612 let Inst{23-22} = size;
4613 let Inst{21-17} = 0b10000;
4614 let Inst{16-12} = opcode;
4615 let Inst{11-10} = 0b10;
4620 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4621 SDPatternOperator OpNode> {
4622 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4624 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4625 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4626 asm#"2", ".16b", ".8h", []>;
4627 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4629 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4630 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4631 asm#"2", ".8h", ".4s", []>;
4632 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4634 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4635 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4636 asm#"2", ".4s", ".2d", []>;
4638 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4639 (!cast<Instruction>(NAME # "v16i8")
4640 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4641 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4642 (!cast<Instruction>(NAME # "v8i16")
4643 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4644 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4645 (!cast<Instruction>(NAME # "v4i32")
4646 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4649 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4650 RegisterOperand regtype,
4651 string asm, string kind, string zero,
4652 ValueType dty, ValueType sty, SDNode OpNode>
4653 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4654 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4655 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4656 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4663 let Inst{28-24} = 0b01110;
4664 let Inst{23-22} = size;
4665 let Inst{21-17} = 0b10000;
4666 let Inst{16-12} = opcode;
4667 let Inst{11-10} = 0b10;
4672 // Comparisons support all element sizes, except 1xD.
4673 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4675 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4677 v8i8, v8i8, OpNode>;
4678 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4680 v16i8, v16i8, OpNode>;
4681 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4683 v4i16, v4i16, OpNode>;
4684 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4686 v8i16, v8i16, OpNode>;
4687 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4689 v2i32, v2i32, OpNode>;
4690 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4692 v4i32, v4i32, OpNode>;
4693 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4695 v2i64, v2i64, OpNode>;
4698 // FP Comparisons support only S and D element sizes.
4699 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4700 string asm, SDNode OpNode> {
4702 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4704 v2i32, v2f32, OpNode>;
4705 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4707 v4i32, v4f32, OpNode>;
4708 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4710 v2i64, v2f64, OpNode>;
4712 def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
4713 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4714 def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
4715 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4716 def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
4717 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4718 def : InstAlias<asm # ".2s $Vd, $Vn, #0",
4719 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4720 def : InstAlias<asm # ".4s $Vd, $Vn, #0",
4721 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4722 def : InstAlias<asm # ".2d $Vd, $Vn, #0",
4723 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4726 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4727 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4728 RegisterOperand outtype, RegisterOperand intype,
4729 string asm, string VdTy, string VnTy,
4731 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4732 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4739 let Inst{28-24} = 0b01110;
4740 let Inst{23-22} = size;
4741 let Inst{21-17} = 0b10000;
4742 let Inst{16-12} = opcode;
4743 let Inst{11-10} = 0b10;
4748 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4749 RegisterOperand outtype, RegisterOperand intype,
4750 string asm, string VdTy, string VnTy,
4752 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4753 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4760 let Inst{28-24} = 0b01110;
4761 let Inst{23-22} = size;
4762 let Inst{21-17} = 0b10000;
4763 let Inst{16-12} = opcode;
4764 let Inst{11-10} = 0b10;
4769 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4770 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4771 asm, ".4s", ".4h", []>;
4772 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4773 asm#"2", ".4s", ".8h", []>;
4774 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4775 asm, ".2d", ".2s", []>;
4776 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4777 asm#"2", ".2d", ".4s", []>;
4780 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4781 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4782 asm, ".4h", ".4s", []>;
4783 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4784 asm#"2", ".8h", ".4s", []>;
4785 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4786 asm, ".2s", ".2d", []>;
4787 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4788 asm#"2", ".4s", ".2d", []>;
4791 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4793 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4795 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4796 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4797 asm#"2", ".4s", ".2d", []>;
4799 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4800 (!cast<Instruction>(NAME # "v4f32")
4801 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4804 //----------------------------------------------------------------------------
4805 // AdvSIMD three register different-size vector instructions.
4806 //----------------------------------------------------------------------------
4808 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4809 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4810 RegisterOperand outtype, RegisterOperand intype1,
4811 RegisterOperand intype2, string asm,
4812 string outkind, string inkind1, string inkind2,
4814 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4815 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4816 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4822 let Inst{30} = size{0};
4824 let Inst{28-24} = 0b01110;
4825 let Inst{23-22} = size{2-1};
4827 let Inst{20-16} = Rm;
4828 let Inst{15-12} = opcode;
4829 let Inst{11-10} = 0b00;
4834 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4835 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4836 RegisterOperand outtype, RegisterOperand intype1,
4837 RegisterOperand intype2, string asm,
4838 string outkind, string inkind1, string inkind2,
4840 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4841 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4842 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4848 let Inst{30} = size{0};
4850 let Inst{28-24} = 0b01110;
4851 let Inst{23-22} = size{2-1};
4853 let Inst{20-16} = Rm;
4854 let Inst{15-12} = opcode;
4855 let Inst{11-10} = 0b00;
4860 // FIXME: TableGen doesn't know how to deal with expanded types that also
4861 // change the element count (in this case, placing the results in
4862 // the high elements of the result register rather than the low
4863 // elements). Until that's fixed, we can't code-gen those.
4864 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4866 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4868 asm, ".8b", ".8h", ".8h",
4869 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4870 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4872 asm#"2", ".16b", ".8h", ".8h",
4874 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4876 asm, ".4h", ".4s", ".4s",
4877 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4878 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4880 asm#"2", ".8h", ".4s", ".4s",
4882 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4884 asm, ".2s", ".2d", ".2d",
4885 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4886 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4888 asm#"2", ".4s", ".2d", ".2d",
4892 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4893 // a version attached to an instruction.
4894 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4896 (!cast<Instruction>(NAME # "v8i16_v16i8")
4897 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4898 V128:$Rn, V128:$Rm)>;
4899 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4901 (!cast<Instruction>(NAME # "v4i32_v8i16")
4902 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4903 V128:$Rn, V128:$Rm)>;
4904 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4906 (!cast<Instruction>(NAME # "v2i64_v4i32")
4907 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4908 V128:$Rn, V128:$Rm)>;
4911 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
4913 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4915 asm, ".8h", ".8b", ".8b",
4916 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4917 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4919 asm#"2", ".8h", ".16b", ".16b", []>;
4920 let Predicates = [HasCrypto] in {
4921 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
4923 asm, ".1q", ".1d", ".1d", []>;
4924 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
4926 asm#"2", ".1q", ".2d", ".2d", []>;
4929 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4930 (v8i8 (extract_high_v16i8 V128:$Rm)))),
4931 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4934 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
4935 SDPatternOperator OpNode> {
4936 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4938 asm, ".4s", ".4h", ".4h",
4939 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4940 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4942 asm#"2", ".4s", ".8h", ".8h",
4943 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4944 (extract_high_v8i16 V128:$Rm)))]>;
4945 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4947 asm, ".2d", ".2s", ".2s",
4948 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4949 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4951 asm#"2", ".2d", ".4s", ".4s",
4952 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4953 (extract_high_v4i32 V128:$Rm)))]>;
4956 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
4957 SDPatternOperator OpNode = null_frag> {
4958 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4960 asm, ".8h", ".8b", ".8b",
4961 [(set (v8i16 V128:$Rd),
4962 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4963 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4965 asm#"2", ".8h", ".16b", ".16b",
4966 [(set (v8i16 V128:$Rd),
4967 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4968 (extract_high_v16i8 V128:$Rm)))))]>;
4969 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4971 asm, ".4s", ".4h", ".4h",
4972 [(set (v4i32 V128:$Rd),
4973 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
4974 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4976 asm#"2", ".4s", ".8h", ".8h",
4977 [(set (v4i32 V128:$Rd),
4978 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4979 (extract_high_v8i16 V128:$Rm)))))]>;
4980 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4982 asm, ".2d", ".2s", ".2s",
4983 [(set (v2i64 V128:$Rd),
4984 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
4985 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4987 asm#"2", ".2d", ".4s", ".4s",
4988 [(set (v2i64 V128:$Rd),
4989 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4990 (extract_high_v4i32 V128:$Rm)))))]>;
4993 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
4995 SDPatternOperator OpNode> {
4996 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
4998 asm, ".8h", ".8b", ".8b",
4999 [(set (v8i16 V128:$dst),
5000 (add (v8i16 V128:$Rd),
5001 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
5002 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5004 asm#"2", ".8h", ".16b", ".16b",
5005 [(set (v8i16 V128:$dst),
5006 (add (v8i16 V128:$Rd),
5007 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
5008 (extract_high_v16i8 V128:$Rm))))))]>;
5009 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5011 asm, ".4s", ".4h", ".4h",
5012 [(set (v4i32 V128:$dst),
5013 (add (v4i32 V128:$Rd),
5014 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
5015 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5017 asm#"2", ".4s", ".8h", ".8h",
5018 [(set (v4i32 V128:$dst),
5019 (add (v4i32 V128:$Rd),
5020 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
5021 (extract_high_v8i16 V128:$Rm))))))]>;
5022 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5024 asm, ".2d", ".2s", ".2s",
5025 [(set (v2i64 V128:$dst),
5026 (add (v2i64 V128:$Rd),
5027 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
5028 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5030 asm#"2", ".2d", ".4s", ".4s",
5031 [(set (v2i64 V128:$dst),
5032 (add (v2i64 V128:$Rd),
5033 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
5034 (extract_high_v4i32 V128:$Rm))))))]>;
5037 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
5038 SDPatternOperator OpNode = null_frag> {
5039 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5041 asm, ".8h", ".8b", ".8b",
5042 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5043 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5045 asm#"2", ".8h", ".16b", ".16b",
5046 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5047 (extract_high_v16i8 V128:$Rm)))]>;
5048 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5050 asm, ".4s", ".4h", ".4h",
5051 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5052 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5054 asm#"2", ".4s", ".8h", ".8h",
5055 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5056 (extract_high_v8i16 V128:$Rm)))]>;
5057 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5059 asm, ".2d", ".2s", ".2s",
5060 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5061 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5063 asm#"2", ".2d", ".4s", ".4s",
5064 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5065 (extract_high_v4i32 V128:$Rm)))]>;
5068 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5070 SDPatternOperator OpNode> {
5071 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5073 asm, ".8h", ".8b", ".8b",
5074 [(set (v8i16 V128:$dst),
5075 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5076 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5078 asm#"2", ".8h", ".16b", ".16b",
5079 [(set (v8i16 V128:$dst),
5080 (OpNode (v8i16 V128:$Rd),
5081 (extract_high_v16i8 V128:$Rn),
5082 (extract_high_v16i8 V128:$Rm)))]>;
5083 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5085 asm, ".4s", ".4h", ".4h",
5086 [(set (v4i32 V128:$dst),
5087 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5088 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5090 asm#"2", ".4s", ".8h", ".8h",
5091 [(set (v4i32 V128:$dst),
5092 (OpNode (v4i32 V128:$Rd),
5093 (extract_high_v8i16 V128:$Rn),
5094 (extract_high_v8i16 V128:$Rm)))]>;
5095 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5097 asm, ".2d", ".2s", ".2s",
5098 [(set (v2i64 V128:$dst),
5099 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5100 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5102 asm#"2", ".2d", ".4s", ".4s",
5103 [(set (v2i64 V128:$dst),
5104 (OpNode (v2i64 V128:$Rd),
5105 (extract_high_v4i32 V128:$Rn),
5106 (extract_high_v4i32 V128:$Rm)))]>;
5109 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5110 SDPatternOperator Accum> {
5111 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5113 asm, ".4s", ".4h", ".4h",
5114 [(set (v4i32 V128:$dst),
5115 (Accum (v4i32 V128:$Rd),
5116 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5117 (v4i16 V64:$Rm)))))]>;
5118 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5120 asm#"2", ".4s", ".8h", ".8h",
5121 [(set (v4i32 V128:$dst),
5122 (Accum (v4i32 V128:$Rd),
5123 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5124 (extract_high_v8i16 V128:$Rm)))))]>;
5125 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5127 asm, ".2d", ".2s", ".2s",
5128 [(set (v2i64 V128:$dst),
5129 (Accum (v2i64 V128:$Rd),
5130 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5131 (v2i32 V64:$Rm)))))]>;
5132 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5134 asm#"2", ".2d", ".4s", ".4s",
5135 [(set (v2i64 V128:$dst),
5136 (Accum (v2i64 V128:$Rd),
5137 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5138 (extract_high_v4i32 V128:$Rm)))))]>;
5141 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5142 SDPatternOperator OpNode> {
5143 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5145 asm, ".8h", ".8h", ".8b",
5146 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5147 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5149 asm#"2", ".8h", ".8h", ".16b",
5150 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5151 (extract_high_v16i8 V128:$Rm)))]>;
5152 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5154 asm, ".4s", ".4s", ".4h",
5155 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5156 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5158 asm#"2", ".4s", ".4s", ".8h",
5159 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5160 (extract_high_v8i16 V128:$Rm)))]>;
5161 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5163 asm, ".2d", ".2d", ".2s",
5164 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5165 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5167 asm#"2", ".2d", ".2d", ".4s",
5168 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5169 (extract_high_v4i32 V128:$Rm)))]>;
5172 //----------------------------------------------------------------------------
5173 // AdvSIMD bitwise extract from vector
5174 //----------------------------------------------------------------------------
5176 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5177 string asm, string kind>
5178 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5179 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5180 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5181 [(set (vty regtype:$Rd),
5182 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5189 let Inst{30} = size;
5190 let Inst{29-21} = 0b101110000;
5191 let Inst{20-16} = Rm;
5193 let Inst{14-11} = imm;
5200 multiclass SIMDBitwiseExtract<string asm> {
5201 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5204 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5207 //----------------------------------------------------------------------------
5208 // AdvSIMD zip vector
5209 //----------------------------------------------------------------------------
5211 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5212 string asm, string kind, SDNode OpNode, ValueType valty>
5213 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5214 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5215 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5216 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5222 let Inst{30} = size{0};
5223 let Inst{29-24} = 0b001110;
5224 let Inst{23-22} = size{2-1};
5226 let Inst{20-16} = Rm;
5228 let Inst{14-12} = opc;
5229 let Inst{11-10} = 0b10;
5234 multiclass SIMDZipVector<bits<3>opc, string asm,
5236 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5237 asm, ".8b", OpNode, v8i8>;
5238 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5239 asm, ".16b", OpNode, v16i8>;
5240 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5241 asm, ".4h", OpNode, v4i16>;
5242 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5243 asm, ".8h", OpNode, v8i16>;
5244 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5245 asm, ".2s", OpNode, v2i32>;
5246 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5247 asm, ".4s", OpNode, v4i32>;
5248 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5249 asm, ".2d", OpNode, v2i64>;
5251 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5252 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5253 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5254 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5255 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5256 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5259 //----------------------------------------------------------------------------
5260 // AdvSIMD three register scalar instructions
5261 //----------------------------------------------------------------------------
5263 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5264 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5265 RegisterClass regtype, string asm,
5267 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5268 "\t$Rd, $Rn, $Rm", "", pattern>,
5273 let Inst{31-30} = 0b01;
5275 let Inst{28-24} = 0b11110;
5276 let Inst{23-22} = size;
5278 let Inst{20-16} = Rm;
5279 let Inst{15-11} = opcode;
5285 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5286 SDPatternOperator OpNode> {
5287 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5288 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5291 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5292 SDPatternOperator OpNode> {
5293 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5294 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5295 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5296 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5297 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5299 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5300 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5301 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5302 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5305 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5306 SDPatternOperator OpNode> {
5307 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5308 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5309 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5312 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5313 SDPatternOperator OpNode = null_frag> {
5314 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5315 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5316 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5317 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5318 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5321 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5322 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5325 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5326 SDPatternOperator OpNode = null_frag> {
5327 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5328 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5329 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5330 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5331 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5334 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5335 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5338 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5339 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5340 : I<oops, iops, asm,
5341 "\t$Rd, $Rn, $Rm", cstr, pat>,
5346 let Inst{31-30} = 0b01;
5348 let Inst{28-24} = 0b11110;
5349 let Inst{23-22} = size;
5351 let Inst{20-16} = Rm;
5352 let Inst{15-11} = opcode;
5358 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5359 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5360 SDPatternOperator OpNode = null_frag> {
5361 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5363 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5364 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5366 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5367 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5370 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5371 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5372 SDPatternOperator OpNode = null_frag> {
5373 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5375 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5376 asm, "$Rd = $dst", []>;
5377 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5379 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5381 [(set (i64 FPR64:$dst),
5382 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5385 //----------------------------------------------------------------------------
5386 // AdvSIMD two register scalar instructions
5387 //----------------------------------------------------------------------------
5389 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5390 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5391 RegisterClass regtype, RegisterClass regtype2,
5392 string asm, list<dag> pat>
5393 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5394 "\t$Rd, $Rn", "", pat>,
5398 let Inst{31-30} = 0b01;
5400 let Inst{28-24} = 0b11110;
5401 let Inst{23-22} = size;
5402 let Inst{21-17} = 0b10000;
5403 let Inst{16-12} = opcode;
5404 let Inst{11-10} = 0b10;
5409 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5410 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5411 RegisterClass regtype, RegisterClass regtype2,
5412 string asm, list<dag> pat>
5413 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5414 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5418 let Inst{31-30} = 0b01;
5420 let Inst{28-24} = 0b11110;
5421 let Inst{23-22} = size;
5422 let Inst{21-17} = 0b10000;
5423 let Inst{16-12} = opcode;
5424 let Inst{11-10} = 0b10;
5430 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5431 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5432 RegisterClass regtype, string asm, string zero>
5433 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5434 "\t$Rd, $Rn, #" # zero, "", []>,
5438 let Inst{31-30} = 0b01;
5440 let Inst{28-24} = 0b11110;
5441 let Inst{23-22} = size;
5442 let Inst{21-17} = 0b10000;
5443 let Inst{16-12} = opcode;
5444 let Inst{11-10} = 0b10;
5449 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5450 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5451 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5455 let Inst{31-17} = 0b011111100110000;
5456 let Inst{16-12} = opcode;
5457 let Inst{11-10} = 0b10;
5462 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5463 SDPatternOperator OpNode> {
5464 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5466 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5467 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5470 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
5471 SDPatternOperator OpNode> {
5472 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5473 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5475 def : InstAlias<asm # " $Rd, $Rn, #0",
5476 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5477 def : InstAlias<asm # " $Rd, $Rn, #0",
5478 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5480 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5481 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5484 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5485 SDPatternOperator OpNode = null_frag> {
5486 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5487 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5489 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5490 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5493 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {
5494 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5495 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5498 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5499 SDPatternOperator OpNode> {
5500 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5501 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5502 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5503 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5506 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5507 SDPatternOperator OpNode = null_frag> {
5508 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5509 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5510 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5511 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5512 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5513 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5514 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5517 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5518 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5521 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5523 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5524 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5525 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5526 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5527 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5528 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5529 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5532 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5533 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5538 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5539 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5540 SDPatternOperator OpNode = null_frag> {
5541 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5542 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5543 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5544 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5547 //----------------------------------------------------------------------------
5548 // AdvSIMD scalar pairwise instructions
5549 //----------------------------------------------------------------------------
5551 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5552 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5553 RegisterOperand regtype, RegisterOperand vectype,
5554 string asm, string kind>
5555 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5556 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5560 let Inst{31-30} = 0b01;
5562 let Inst{28-24} = 0b11110;
5563 let Inst{23-22} = size;
5564 let Inst{21-17} = 0b11000;
5565 let Inst{16-12} = opcode;
5566 let Inst{11-10} = 0b10;
5571 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5572 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5576 multiclass SIMDPairwiseScalarSD<bit U, bit S, bits<5> opc, string asm> {
5577 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5579 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5583 //----------------------------------------------------------------------------
5584 // AdvSIMD across lanes instructions
5585 //----------------------------------------------------------------------------
5587 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5588 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5589 RegisterClass regtype, RegisterOperand vectype,
5590 string asm, string kind, list<dag> pattern>
5591 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5592 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5599 let Inst{28-24} = 0b01110;
5600 let Inst{23-22} = size;
5601 let Inst{21-17} = 0b11000;
5602 let Inst{16-12} = opcode;
5603 let Inst{11-10} = 0b10;
5608 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5610 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5612 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5614 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5616 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5618 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5622 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5623 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5625 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5627 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5629 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5631 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5635 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5637 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5639 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5642 //----------------------------------------------------------------------------
5643 // AdvSIMD INS/DUP instructions
5644 //----------------------------------------------------------------------------
5646 // FIXME: There has got to be a better way to factor these. ugh.
5648 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5649 string operands, string constraints, list<dag> pattern>
5650 : I<outs, ins, asm, operands, constraints, pattern>,
5657 let Inst{28-21} = 0b01110000;
5664 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5665 RegisterOperand vecreg, RegisterClass regtype>
5666 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5667 "{\t$Rd" # size # ", $Rn" #
5668 "|" # size # "\t$Rd, $Rn}", "",
5669 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
5670 let Inst{20-16} = imm5;
5671 let Inst{14-11} = 0b0001;
5674 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5675 ValueType vectype, ValueType insreg,
5676 RegisterOperand vecreg, Operand idxtype,
5677 ValueType elttype, SDNode OpNode>
5678 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5679 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5680 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5681 [(set (vectype vecreg:$Rd),
5682 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5683 let Inst{14-11} = 0b0000;
5686 class SIMDDup64FromElement
5687 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5688 VectorIndexD, i64, AArch64duplane64> {
5691 let Inst{19-16} = 0b1000;
5694 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5695 RegisterOperand vecreg>
5696 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5697 VectorIndexS, i64, AArch64duplane32> {
5699 let Inst{20-19} = idx;
5700 let Inst{18-16} = 0b100;
5703 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5704 RegisterOperand vecreg>
5705 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5706 VectorIndexH, i64, AArch64duplane16> {
5708 let Inst{20-18} = idx;
5709 let Inst{17-16} = 0b10;
5712 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5713 RegisterOperand vecreg>
5714 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5715 VectorIndexB, i64, AArch64duplane8> {
5717 let Inst{20-17} = idx;
5721 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5722 Operand idxtype, string asm, list<dag> pattern>
5723 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5724 "{\t$Rd, $Rn" # size # "$idx" #
5725 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5726 let Inst{14-11} = imm4;
5729 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5731 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5732 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5734 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5735 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5737 class SIMDMovAlias<string asm, string size, Instruction inst,
5738 RegisterClass regtype, Operand idxtype>
5739 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5740 "|" # size # "\t$dst, $src$idx}",
5741 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5744 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5746 let Inst{20-17} = idx;
5749 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5751 let Inst{20-17} = idx;
5754 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5756 let Inst{20-18} = idx;
5757 let Inst{17-16} = 0b10;
5759 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5761 let Inst{20-18} = idx;
5762 let Inst{17-16} = 0b10;
5764 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5766 let Inst{20-19} = idx;
5767 let Inst{18-16} = 0b100;
5772 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5774 let Inst{20-17} = idx;
5777 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5779 let Inst{20-18} = idx;
5780 let Inst{17-16} = 0b10;
5782 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5784 let Inst{20-19} = idx;
5785 let Inst{18-16} = 0b100;
5787 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5790 let Inst{19-16} = 0b1000;
5792 def : SIMDMovAlias<"mov", ".s",
5793 !cast<Instruction>(NAME#"vi32"),
5794 GPR32, VectorIndexS>;
5795 def : SIMDMovAlias<"mov", ".d",
5796 !cast<Instruction>(NAME#"vi64"),
5797 GPR64, VectorIndexD>;
5800 class SIMDInsFromMain<string size, ValueType vectype,
5801 RegisterClass regtype, Operand idxtype>
5802 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5803 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5804 "{\t$Rd" # size # "$idx, $Rn" #
5805 "|" # size # "\t$Rd$idx, $Rn}",
5808 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5809 let Inst{14-11} = 0b0011;
5812 class SIMDInsFromElement<string size, ValueType vectype,
5813 ValueType elttype, Operand idxtype>
5814 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5815 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5816 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5817 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5822 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5825 class SIMDInsMainMovAlias<string size, Instruction inst,
5826 RegisterClass regtype, Operand idxtype>
5827 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5828 "|" # size #"\t$dst$idx, $src}",
5829 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5830 class SIMDInsElementMovAlias<string size, Instruction inst,
5832 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5833 # "|" # size #" $dst$idx, $src$idx2}",
5834 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5837 multiclass SIMDIns {
5838 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5840 let Inst{20-17} = idx;
5843 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5845 let Inst{20-18} = idx;
5846 let Inst{17-16} = 0b10;
5848 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5850 let Inst{20-19} = idx;
5851 let Inst{18-16} = 0b100;
5853 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5856 let Inst{19-16} = 0b1000;
5859 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5862 let Inst{20-17} = idx;
5864 let Inst{14-11} = idx2;
5866 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5869 let Inst{20-18} = idx;
5870 let Inst{17-16} = 0b10;
5871 let Inst{14-12} = idx2;
5874 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
5877 let Inst{20-19} = idx;
5878 let Inst{18-16} = 0b100;
5879 let Inst{14-13} = idx2;
5880 let Inst{12-11} = 0;
5882 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
5886 let Inst{19-16} = 0b1000;
5887 let Inst{14} = idx2;
5888 let Inst{13-11} = 0;
5891 // For all forms of the INS instruction, the "mov" mnemonic is the
5892 // preferred alias. Why they didn't just call the instruction "mov" in
5893 // the first place is a very good question indeed...
5894 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
5895 GPR32, VectorIndexB>;
5896 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
5897 GPR32, VectorIndexH>;
5898 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
5899 GPR32, VectorIndexS>;
5900 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
5901 GPR64, VectorIndexD>;
5903 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
5905 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
5907 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
5909 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
5913 //----------------------------------------------------------------------------
5915 //----------------------------------------------------------------------------
5917 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5918 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5919 RegisterOperand listtype, string asm, string kind>
5920 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
5921 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
5928 let Inst{29-21} = 0b001110000;
5929 let Inst{20-16} = Vm;
5931 let Inst{14-13} = len;
5933 let Inst{11-10} = 0b00;
5938 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5939 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5940 RegisterOperand listtype, string asm, string kind>
5941 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
5942 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
5949 let Inst{29-21} = 0b001110000;
5950 let Inst{20-16} = Vm;
5952 let Inst{14-13} = len;
5954 let Inst{11-10} = 0b00;
5959 class SIMDTableLookupAlias<string asm, Instruction inst,
5960 RegisterOperand vectype, RegisterOperand listtype>
5961 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
5962 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
5964 multiclass SIMDTableLookup<bit op, string asm> {
5965 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
5967 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
5969 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
5971 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
5973 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
5975 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
5977 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
5979 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
5982 def : SIMDTableLookupAlias<asm # ".8b",
5983 !cast<Instruction>(NAME#"v8i8One"),
5984 V64, VecListOne128>;
5985 def : SIMDTableLookupAlias<asm # ".8b",
5986 !cast<Instruction>(NAME#"v8i8Two"),
5987 V64, VecListTwo128>;
5988 def : SIMDTableLookupAlias<asm # ".8b",
5989 !cast<Instruction>(NAME#"v8i8Three"),
5990 V64, VecListThree128>;
5991 def : SIMDTableLookupAlias<asm # ".8b",
5992 !cast<Instruction>(NAME#"v8i8Four"),
5993 V64, VecListFour128>;
5994 def : SIMDTableLookupAlias<asm # ".16b",
5995 !cast<Instruction>(NAME#"v16i8One"),
5996 V128, VecListOne128>;
5997 def : SIMDTableLookupAlias<asm # ".16b",
5998 !cast<Instruction>(NAME#"v16i8Two"),
5999 V128, VecListTwo128>;
6000 def : SIMDTableLookupAlias<asm # ".16b",
6001 !cast<Instruction>(NAME#"v16i8Three"),
6002 V128, VecListThree128>;
6003 def : SIMDTableLookupAlias<asm # ".16b",
6004 !cast<Instruction>(NAME#"v16i8Four"),
6005 V128, VecListFour128>;
6008 multiclass SIMDTableLookupTied<bit op, string asm> {
6009 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
6011 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
6013 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
6015 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
6017 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
6019 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
6021 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
6023 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
6026 def : SIMDTableLookupAlias<asm # ".8b",
6027 !cast<Instruction>(NAME#"v8i8One"),
6028 V64, VecListOne128>;
6029 def : SIMDTableLookupAlias<asm # ".8b",
6030 !cast<Instruction>(NAME#"v8i8Two"),
6031 V64, VecListTwo128>;
6032 def : SIMDTableLookupAlias<asm # ".8b",
6033 !cast<Instruction>(NAME#"v8i8Three"),
6034 V64, VecListThree128>;
6035 def : SIMDTableLookupAlias<asm # ".8b",
6036 !cast<Instruction>(NAME#"v8i8Four"),
6037 V64, VecListFour128>;
6038 def : SIMDTableLookupAlias<asm # ".16b",
6039 !cast<Instruction>(NAME#"v16i8One"),
6040 V128, VecListOne128>;
6041 def : SIMDTableLookupAlias<asm # ".16b",
6042 !cast<Instruction>(NAME#"v16i8Two"),
6043 V128, VecListTwo128>;
6044 def : SIMDTableLookupAlias<asm # ".16b",
6045 !cast<Instruction>(NAME#"v16i8Three"),
6046 V128, VecListThree128>;
6047 def : SIMDTableLookupAlias<asm # ".16b",
6048 !cast<Instruction>(NAME#"v16i8Four"),
6049 V128, VecListFour128>;
6053 //----------------------------------------------------------------------------
6054 // AdvSIMD scalar CPY
6055 //----------------------------------------------------------------------------
6056 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6057 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
6058 string kind, Operand idxtype>
6059 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
6060 "{\t$dst, $src" # kind # "$idx" #
6061 "|\t$dst, $src$idx}", "", []>,
6065 let Inst{31-21} = 0b01011110000;
6066 let Inst{15-10} = 0b000001;
6067 let Inst{9-5} = src;
6068 let Inst{4-0} = dst;
6071 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
6072 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
6073 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
6074 # "|\t$dst, $src$index}",
6075 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
6078 multiclass SIMDScalarCPY<string asm> {
6079 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6081 let Inst{20-17} = idx;
6084 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6086 let Inst{20-18} = idx;
6087 let Inst{17-16} = 0b10;
6089 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6091 let Inst{20-19} = idx;
6092 let Inst{18-16} = 0b100;
6094 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6097 let Inst{19-16} = 0b1000;
6100 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6101 VectorIndexD:$idx)))),
6102 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6104 // 'DUP' mnemonic aliases.
6105 def : SIMDScalarCPYAlias<"dup", ".b",
6106 !cast<Instruction>(NAME#"i8"),
6107 FPR8, V128, VectorIndexB>;
6108 def : SIMDScalarCPYAlias<"dup", ".h",
6109 !cast<Instruction>(NAME#"i16"),
6110 FPR16, V128, VectorIndexH>;
6111 def : SIMDScalarCPYAlias<"dup", ".s",
6112 !cast<Instruction>(NAME#"i32"),
6113 FPR32, V128, VectorIndexS>;
6114 def : SIMDScalarCPYAlias<"dup", ".d",
6115 !cast<Instruction>(NAME#"i64"),
6116 FPR64, V128, VectorIndexD>;
6119 //----------------------------------------------------------------------------
6120 // AdvSIMD modified immediate instructions
6121 //----------------------------------------------------------------------------
6123 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
6124 string asm, string op_string,
6125 string cstr, list<dag> pattern>
6126 : I<oops, iops, asm, op_string, cstr, pattern>,
6133 let Inst{28-19} = 0b0111100000;
6134 let Inst{18-16} = imm8{7-5};
6135 let Inst{11-10} = 0b01;
6136 let Inst{9-5} = imm8{4-0};
6140 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
6141 Operand immtype, dag opt_shift_iop,
6142 string opt_shift, string asm, string kind,
6144 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
6145 !con((ins immtype:$imm8), opt_shift_iop), asm,
6146 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6147 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6149 let DecoderMethod = "DecodeModImmInstruction";
6152 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
6153 Operand immtype, dag opt_shift_iop,
6154 string opt_shift, string asm, string kind,
6156 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
6157 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6158 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6159 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6160 "$Rd = $dst", pattern> {
6161 let DecoderMethod = "DecodeModImmTiedInstruction";
6164 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6165 RegisterOperand vectype, string asm,
6166 string kind, list<dag> pattern>
6167 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6168 (ins logical_vec_shift:$shift),
6169 "$shift", asm, kind, pattern> {
6171 let Inst{15} = b15_b12{1};
6172 let Inst{14-13} = shift;
6173 let Inst{12} = b15_b12{0};
6176 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6177 RegisterOperand vectype, string asm,
6178 string kind, list<dag> pattern>
6179 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6180 (ins logical_vec_shift:$shift),
6181 "$shift", asm, kind, pattern> {
6183 let Inst{15} = b15_b12{1};
6184 let Inst{14-13} = shift;
6185 let Inst{12} = b15_b12{0};
6189 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6190 RegisterOperand vectype, string asm,
6191 string kind, list<dag> pattern>
6192 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6193 (ins logical_vec_hw_shift:$shift),
6194 "$shift", asm, kind, pattern> {
6196 let Inst{15} = b15_b12{1};
6198 let Inst{13} = shift{0};
6199 let Inst{12} = b15_b12{0};
6202 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6203 RegisterOperand vectype, string asm,
6204 string kind, list<dag> pattern>
6205 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6206 (ins logical_vec_hw_shift:$shift),
6207 "$shift", asm, kind, pattern> {
6209 let Inst{15} = b15_b12{1};
6211 let Inst{13} = shift{0};
6212 let Inst{12} = b15_b12{0};
6215 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6217 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6219 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6222 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6224 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6228 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6229 bits<2> w_cmode, string asm,
6231 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6233 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6235 (i32 imm:$shift)))]>;
6236 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6238 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6240 (i32 imm:$shift)))]>;
6242 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6244 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6246 (i32 imm:$shift)))]>;
6247 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6249 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6251 (i32 imm:$shift)))]>;
6254 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6255 RegisterOperand vectype, string asm,
6256 string kind, list<dag> pattern>
6257 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6258 (ins move_vec_shift:$shift),
6259 "$shift", asm, kind, pattern> {
6261 let Inst{15-13} = cmode{3-1};
6262 let Inst{12} = shift;
6265 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6266 RegisterOperand vectype,
6267 Operand imm_type, string asm,
6268 string kind, list<dag> pattern>
6269 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6270 asm, kind, pattern> {
6271 let Inst{15-12} = cmode;
6274 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6276 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6277 "\t$Rd, $imm8", "", pattern> {
6278 let Inst{15-12} = cmode;
6279 let DecoderMethod = "DecodeModImmInstruction";
6282 //----------------------------------------------------------------------------
6283 // AdvSIMD indexed element
6284 //----------------------------------------------------------------------------
6286 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6287 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6288 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6289 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6290 string apple_kind, string dst_kind, string lhs_kind,
6291 string rhs_kind, list<dag> pattern>
6292 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6294 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6295 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6304 let Inst{28} = Scalar;
6305 let Inst{27-24} = 0b1111;
6306 let Inst{23-22} = size;
6307 // Bit 21 must be set by the derived class.
6308 let Inst{20-16} = Rm;
6309 let Inst{15-12} = opc;
6310 // Bit 11 must be set by the derived class.
6316 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6317 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6318 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6319 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6320 string apple_kind, string dst_kind, string lhs_kind,
6321 string rhs_kind, list<dag> pattern>
6322 : I<(outs dst_reg:$dst),
6323 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6324 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6325 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6334 let Inst{28} = Scalar;
6335 let Inst{27-24} = 0b1111;
6336 let Inst{23-22} = size;
6337 // Bit 21 must be set by the derived class.
6338 let Inst{20-16} = Rm;
6339 let Inst{15-12} = opc;
6340 // Bit 11 must be set by the derived class.
6346 multiclass SIMDFPIndexedSD<bit U, bits<4> opc, string asm,
6347 SDPatternOperator OpNode> {
6348 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6351 asm, ".2s", ".2s", ".2s", ".s",
6352 [(set (v2f32 V64:$Rd),
6353 (OpNode (v2f32 V64:$Rn),
6354 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6356 let Inst{11} = idx{1};
6357 let Inst{21} = idx{0};
6360 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6363 asm, ".4s", ".4s", ".4s", ".s",
6364 [(set (v4f32 V128:$Rd),
6365 (OpNode (v4f32 V128:$Rn),
6366 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6368 let Inst{11} = idx{1};
6369 let Inst{21} = idx{0};
6372 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6375 asm, ".2d", ".2d", ".2d", ".d",
6376 [(set (v2f64 V128:$Rd),
6377 (OpNode (v2f64 V128:$Rn),
6378 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6380 let Inst{11} = idx{0};
6384 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6385 FPR32Op, FPR32Op, V128, VectorIndexS,
6386 asm, ".s", "", "", ".s",
6387 [(set (f32 FPR32Op:$Rd),
6388 (OpNode (f32 FPR32Op:$Rn),
6389 (f32 (vector_extract (v4f32 V128:$Rm),
6390 VectorIndexS:$idx))))]> {
6392 let Inst{11} = idx{1};
6393 let Inst{21} = idx{0};
6396 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6397 FPR64Op, FPR64Op, V128, VectorIndexD,
6398 asm, ".d", "", "", ".d",
6399 [(set (f64 FPR64Op:$Rd),
6400 (OpNode (f64 FPR64Op:$Rn),
6401 (f64 (vector_extract (v2f64 V128:$Rm),
6402 VectorIndexD:$idx))))]> {
6404 let Inst{11} = idx{0};
6409 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6410 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6411 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6412 (AArch64duplane32 (v4f32 V128:$Rm),
6413 VectorIndexS:$idx))),
6414 (!cast<Instruction>(INST # v2i32_indexed)
6415 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6416 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6417 (AArch64dup (f32 FPR32Op:$Rm)))),
6418 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6419 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6422 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6423 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6424 (AArch64duplane32 (v4f32 V128:$Rm),
6425 VectorIndexS:$idx))),
6426 (!cast<Instruction>(INST # "v4i32_indexed")
6427 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6428 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6429 (AArch64dup (f32 FPR32Op:$Rm)))),
6430 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6431 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6433 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6434 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6435 (AArch64duplane64 (v2f64 V128:$Rm),
6436 VectorIndexD:$idx))),
6437 (!cast<Instruction>(INST # "v2i64_indexed")
6438 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6439 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6440 (AArch64dup (f64 FPR64Op:$Rm)))),
6441 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6442 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6444 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6445 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6446 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6447 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6448 V128:$Rm, VectorIndexS:$idx)>;
6449 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6450 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6451 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6452 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6454 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6455 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6456 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6457 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6458 V128:$Rm, VectorIndexD:$idx)>;
6461 multiclass SIMDFPIndexedSDTied<bit U, bits<4> opc, string asm> {
6462 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6464 asm, ".2s", ".2s", ".2s", ".s", []> {
6466 let Inst{11} = idx{1};
6467 let Inst{21} = idx{0};
6470 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6473 asm, ".4s", ".4s", ".4s", ".s", []> {
6475 let Inst{11} = idx{1};
6476 let Inst{21} = idx{0};
6479 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6482 asm, ".2d", ".2d", ".2d", ".d", []> {
6484 let Inst{11} = idx{0};
6489 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6490 FPR32Op, FPR32Op, V128, VectorIndexS,
6491 asm, ".s", "", "", ".s", []> {
6493 let Inst{11} = idx{1};
6494 let Inst{21} = idx{0};
6497 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6498 FPR64Op, FPR64Op, V128, VectorIndexD,
6499 asm, ".d", "", "", ".d", []> {
6501 let Inst{11} = idx{0};
6506 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6507 SDPatternOperator OpNode> {
6508 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6509 V128_lo, VectorIndexH,
6510 asm, ".4h", ".4h", ".4h", ".h",
6511 [(set (v4i16 V64:$Rd),
6512 (OpNode (v4i16 V64:$Rn),
6513 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6515 let Inst{11} = idx{2};
6516 let Inst{21} = idx{1};
6517 let Inst{20} = idx{0};
6520 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6522 V128_lo, VectorIndexH,
6523 asm, ".8h", ".8h", ".8h", ".h",
6524 [(set (v8i16 V128:$Rd),
6525 (OpNode (v8i16 V128:$Rn),
6526 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6528 let Inst{11} = idx{2};
6529 let Inst{21} = idx{1};
6530 let Inst{20} = idx{0};
6533 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6536 asm, ".2s", ".2s", ".2s", ".s",
6537 [(set (v2i32 V64:$Rd),
6538 (OpNode (v2i32 V64:$Rn),
6539 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6541 let Inst{11} = idx{1};
6542 let Inst{21} = idx{0};
6545 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6548 asm, ".4s", ".4s", ".4s", ".s",
6549 [(set (v4i32 V128:$Rd),
6550 (OpNode (v4i32 V128:$Rn),
6551 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6553 let Inst{11} = idx{1};
6554 let Inst{21} = idx{0};
6557 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6558 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6559 asm, ".h", "", "", ".h", []> {
6561 let Inst{11} = idx{2};
6562 let Inst{21} = idx{1};
6563 let Inst{20} = idx{0};
6566 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6567 FPR32Op, FPR32Op, V128, VectorIndexS,
6568 asm, ".s", "", "", ".s",
6569 [(set (i32 FPR32Op:$Rd),
6570 (OpNode FPR32Op:$Rn,
6571 (i32 (vector_extract (v4i32 V128:$Rm),
6572 VectorIndexS:$idx))))]> {
6574 let Inst{11} = idx{1};
6575 let Inst{21} = idx{0};
6579 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6580 SDPatternOperator OpNode> {
6581 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6583 V128_lo, VectorIndexH,
6584 asm, ".4h", ".4h", ".4h", ".h",
6585 [(set (v4i16 V64:$Rd),
6586 (OpNode (v4i16 V64:$Rn),
6587 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6589 let Inst{11} = idx{2};
6590 let Inst{21} = idx{1};
6591 let Inst{20} = idx{0};
6594 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6596 V128_lo, VectorIndexH,
6597 asm, ".8h", ".8h", ".8h", ".h",
6598 [(set (v8i16 V128:$Rd),
6599 (OpNode (v8i16 V128:$Rn),
6600 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6602 let Inst{11} = idx{2};
6603 let Inst{21} = idx{1};
6604 let Inst{20} = idx{0};
6607 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6610 asm, ".2s", ".2s", ".2s", ".s",
6611 [(set (v2i32 V64:$Rd),
6612 (OpNode (v2i32 V64:$Rn),
6613 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6615 let Inst{11} = idx{1};
6616 let Inst{21} = idx{0};
6619 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6622 asm, ".4s", ".4s", ".4s", ".s",
6623 [(set (v4i32 V128:$Rd),
6624 (OpNode (v4i32 V128:$Rn),
6625 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6627 let Inst{11} = idx{1};
6628 let Inst{21} = idx{0};
6632 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6633 SDPatternOperator OpNode> {
6634 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6635 V128_lo, VectorIndexH,
6636 asm, ".4h", ".4h", ".4h", ".h",
6637 [(set (v4i16 V64:$dst),
6638 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6639 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6641 let Inst{11} = idx{2};
6642 let Inst{21} = idx{1};
6643 let Inst{20} = idx{0};
6646 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6648 V128_lo, VectorIndexH,
6649 asm, ".8h", ".8h", ".8h", ".h",
6650 [(set (v8i16 V128:$dst),
6651 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6652 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6654 let Inst{11} = idx{2};
6655 let Inst{21} = idx{1};
6656 let Inst{20} = idx{0};
6659 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6662 asm, ".2s", ".2s", ".2s", ".s",
6663 [(set (v2i32 V64:$dst),
6664 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6665 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6667 let Inst{11} = idx{1};
6668 let Inst{21} = idx{0};
6671 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6674 asm, ".4s", ".4s", ".4s", ".s",
6675 [(set (v4i32 V128:$dst),
6676 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6677 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6679 let Inst{11} = idx{1};
6680 let Inst{21} = idx{0};
6684 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6685 SDPatternOperator OpNode> {
6686 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6688 V128_lo, VectorIndexH,
6689 asm, ".4s", ".4s", ".4h", ".h",
6690 [(set (v4i32 V128:$Rd),
6691 (OpNode (v4i16 V64:$Rn),
6692 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6694 let Inst{11} = idx{2};
6695 let Inst{21} = idx{1};
6696 let Inst{20} = idx{0};
6699 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6701 V128_lo, VectorIndexH,
6702 asm#"2", ".4s", ".4s", ".8h", ".h",
6703 [(set (v4i32 V128:$Rd),
6704 (OpNode (extract_high_v8i16 V128:$Rn),
6705 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6706 VectorIndexH:$idx))))]> {
6709 let Inst{11} = idx{2};
6710 let Inst{21} = idx{1};
6711 let Inst{20} = idx{0};
6714 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6717 asm, ".2d", ".2d", ".2s", ".s",
6718 [(set (v2i64 V128:$Rd),
6719 (OpNode (v2i32 V64:$Rn),
6720 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6722 let Inst{11} = idx{1};
6723 let Inst{21} = idx{0};
6726 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6729 asm#"2", ".2d", ".2d", ".4s", ".s",
6730 [(set (v2i64 V128:$Rd),
6731 (OpNode (extract_high_v4i32 V128:$Rn),
6732 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6733 VectorIndexS:$idx))))]> {
6735 let Inst{11} = idx{1};
6736 let Inst{21} = idx{0};
6739 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6740 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6741 asm, ".h", "", "", ".h", []> {
6743 let Inst{11} = idx{2};
6744 let Inst{21} = idx{1};
6745 let Inst{20} = idx{0};
6748 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6749 FPR64Op, FPR32Op, V128, VectorIndexS,
6750 asm, ".s", "", "", ".s", []> {
6752 let Inst{11} = idx{1};
6753 let Inst{21} = idx{0};
6757 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6758 SDPatternOperator Accum> {
6759 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6761 V128_lo, VectorIndexH,
6762 asm, ".4s", ".4s", ".4h", ".h",
6763 [(set (v4i32 V128:$dst),
6764 (Accum (v4i32 V128:$Rd),
6765 (v4i32 (int_aarch64_neon_sqdmull
6767 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6768 VectorIndexH:$idx))))))]> {
6770 let Inst{11} = idx{2};
6771 let Inst{21} = idx{1};
6772 let Inst{20} = idx{0};
6775 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6776 // intermediate EXTRACT_SUBREG would be untyped.
6777 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6778 (i32 (vector_extract (v4i32
6779 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
6780 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6781 VectorIndexH:$idx)))),
6784 (!cast<Instruction>(NAME # v4i16_indexed)
6785 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6786 V128_lo:$Rm, VectorIndexH:$idx),
6789 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6791 V128_lo, VectorIndexH,
6792 asm#"2", ".4s", ".4s", ".8h", ".h",
6793 [(set (v4i32 V128:$dst),
6794 (Accum (v4i32 V128:$Rd),
6795 (v4i32 (int_aarch64_neon_sqdmull
6796 (extract_high_v8i16 V128:$Rn),
6798 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6799 VectorIndexH:$idx))))))]> {
6801 let Inst{11} = idx{2};
6802 let Inst{21} = idx{1};
6803 let Inst{20} = idx{0};
6806 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6809 asm, ".2d", ".2d", ".2s", ".s",
6810 [(set (v2i64 V128:$dst),
6811 (Accum (v2i64 V128:$Rd),
6812 (v2i64 (int_aarch64_neon_sqdmull
6814 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
6815 VectorIndexS:$idx))))))]> {
6817 let Inst{11} = idx{1};
6818 let Inst{21} = idx{0};
6821 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6824 asm#"2", ".2d", ".2d", ".4s", ".s",
6825 [(set (v2i64 V128:$dst),
6826 (Accum (v2i64 V128:$Rd),
6827 (v2i64 (int_aarch64_neon_sqdmull
6828 (extract_high_v4i32 V128:$Rn),
6830 (AArch64duplane32 (v4i32 V128:$Rm),
6831 VectorIndexS:$idx))))))]> {
6833 let Inst{11} = idx{1};
6834 let Inst{21} = idx{0};
6837 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6838 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6839 asm, ".h", "", "", ".h", []> {
6841 let Inst{11} = idx{2};
6842 let Inst{21} = idx{1};
6843 let Inst{20} = idx{0};
6847 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6848 FPR64Op, FPR32Op, V128, VectorIndexS,
6849 asm, ".s", "", "", ".s",
6850 [(set (i64 FPR64Op:$dst),
6851 (Accum (i64 FPR64Op:$Rd),
6852 (i64 (int_aarch64_neon_sqdmulls_scalar
6854 (i32 (vector_extract (v4i32 V128:$Rm),
6855 VectorIndexS:$idx))))))]> {
6858 let Inst{11} = idx{1};
6859 let Inst{21} = idx{0};
6863 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6864 SDPatternOperator OpNode> {
6865 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6866 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6868 V128_lo, VectorIndexH,
6869 asm, ".4s", ".4s", ".4h", ".h",
6870 [(set (v4i32 V128:$Rd),
6871 (OpNode (v4i16 V64:$Rn),
6872 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6874 let Inst{11} = idx{2};
6875 let Inst{21} = idx{1};
6876 let Inst{20} = idx{0};
6879 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6881 V128_lo, VectorIndexH,
6882 asm#"2", ".4s", ".4s", ".8h", ".h",
6883 [(set (v4i32 V128:$Rd),
6884 (OpNode (extract_high_v8i16 V128:$Rn),
6885 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6886 VectorIndexH:$idx))))]> {
6889 let Inst{11} = idx{2};
6890 let Inst{21} = idx{1};
6891 let Inst{20} = idx{0};
6894 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6897 asm, ".2d", ".2d", ".2s", ".s",
6898 [(set (v2i64 V128:$Rd),
6899 (OpNode (v2i32 V64:$Rn),
6900 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6902 let Inst{11} = idx{1};
6903 let Inst{21} = idx{0};
6906 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6909 asm#"2", ".2d", ".2d", ".4s", ".s",
6910 [(set (v2i64 V128:$Rd),
6911 (OpNode (extract_high_v4i32 V128:$Rn),
6912 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6913 VectorIndexS:$idx))))]> {
6915 let Inst{11} = idx{1};
6916 let Inst{21} = idx{0};
6921 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
6922 SDPatternOperator OpNode> {
6923 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6924 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6926 V128_lo, VectorIndexH,
6927 asm, ".4s", ".4s", ".4h", ".h",
6928 [(set (v4i32 V128:$dst),
6929 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
6930 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6932 let Inst{11} = idx{2};
6933 let Inst{21} = idx{1};
6934 let Inst{20} = idx{0};
6937 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6939 V128_lo, VectorIndexH,
6940 asm#"2", ".4s", ".4s", ".8h", ".h",
6941 [(set (v4i32 V128:$dst),
6942 (OpNode (v4i32 V128:$Rd),
6943 (extract_high_v8i16 V128:$Rn),
6944 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6945 VectorIndexH:$idx))))]> {
6947 let Inst{11} = idx{2};
6948 let Inst{21} = idx{1};
6949 let Inst{20} = idx{0};
6952 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6955 asm, ".2d", ".2d", ".2s", ".s",
6956 [(set (v2i64 V128:$dst),
6957 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
6958 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6960 let Inst{11} = idx{1};
6961 let Inst{21} = idx{0};
6964 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6967 asm#"2", ".2d", ".2d", ".4s", ".s",
6968 [(set (v2i64 V128:$dst),
6969 (OpNode (v2i64 V128:$Rd),
6970 (extract_high_v4i32 V128:$Rn),
6971 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6972 VectorIndexS:$idx))))]> {
6974 let Inst{11} = idx{1};
6975 let Inst{21} = idx{0};
6980 //----------------------------------------------------------------------------
6981 // AdvSIMD scalar shift by immediate
6982 //----------------------------------------------------------------------------
6984 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6985 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
6986 RegisterClass regtype1, RegisterClass regtype2,
6987 Operand immtype, string asm, list<dag> pattern>
6988 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
6989 asm, "\t$Rd, $Rn, $imm", "", pattern>,
6994 let Inst{31-30} = 0b01;
6996 let Inst{28-23} = 0b111110;
6997 let Inst{22-16} = fixed_imm;
6998 let Inst{15-11} = opc;
7004 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7005 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
7006 RegisterClass regtype1, RegisterClass regtype2,
7007 Operand immtype, string asm, list<dag> pattern>
7008 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7009 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7014 let Inst{31-30} = 0b01;
7016 let Inst{28-23} = 0b111110;
7017 let Inst{22-16} = fixed_imm;
7018 let Inst{15-11} = opc;
7025 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
7026 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7027 FPR32, FPR32, vecshiftR32, asm, []> {
7028 let Inst{20-16} = imm{4-0};
7031 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7032 FPR64, FPR64, vecshiftR64, asm, []> {
7033 let Inst{21-16} = imm{5-0};
7037 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
7038 SDPatternOperator OpNode> {
7039 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7040 FPR64, FPR64, vecshiftR64, asm,
7041 [(set (i64 FPR64:$Rd),
7042 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7043 let Inst{21-16} = imm{5-0};
7046 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7047 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7050 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7051 SDPatternOperator OpNode = null_frag> {
7052 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7053 FPR64, FPR64, vecshiftR64, asm,
7054 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7055 (i32 vecshiftR64:$imm)))]> {
7056 let Inst{21-16} = imm{5-0};
7059 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7060 (i32 vecshiftR64:$imm))),
7061 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7065 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7066 SDPatternOperator OpNode> {
7067 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7068 FPR64, FPR64, vecshiftL64, asm,
7069 [(set (v1i64 FPR64:$Rd),
7070 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7071 let Inst{21-16} = imm{5-0};
7075 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7076 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7077 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7078 FPR64, FPR64, vecshiftL64, asm, []> {
7079 let Inst{21-16} = imm{5-0};
7083 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7084 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7085 SDPatternOperator OpNode = null_frag> {
7086 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7087 FPR8, FPR16, vecshiftR8, asm, []> {
7088 let Inst{18-16} = imm{2-0};
7091 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7092 FPR16, FPR32, vecshiftR16, asm, []> {
7093 let Inst{19-16} = imm{3-0};
7096 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7097 FPR32, FPR64, vecshiftR32, asm,
7098 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7099 let Inst{20-16} = imm{4-0};
7103 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7104 SDPatternOperator OpNode> {
7105 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7106 FPR8, FPR8, vecshiftL8, asm, []> {
7107 let Inst{18-16} = imm{2-0};
7110 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7111 FPR16, FPR16, vecshiftL16, asm, []> {
7112 let Inst{19-16} = imm{3-0};
7115 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7116 FPR32, FPR32, vecshiftL32, asm,
7117 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7118 let Inst{20-16} = imm{4-0};
7121 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7122 FPR64, FPR64, vecshiftL64, asm,
7123 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7124 let Inst{21-16} = imm{5-0};
7127 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7128 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7131 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7132 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7133 FPR8, FPR8, vecshiftR8, asm, []> {
7134 let Inst{18-16} = imm{2-0};
7137 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7138 FPR16, FPR16, vecshiftR16, asm, []> {
7139 let Inst{19-16} = imm{3-0};
7142 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7143 FPR32, FPR32, vecshiftR32, asm, []> {
7144 let Inst{20-16} = imm{4-0};
7147 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7148 FPR64, FPR64, vecshiftR64, asm, []> {
7149 let Inst{21-16} = imm{5-0};
7153 //----------------------------------------------------------------------------
7154 // AdvSIMD vector x indexed element
7155 //----------------------------------------------------------------------------
7157 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7158 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7159 RegisterOperand dst_reg, RegisterOperand src_reg,
7161 string asm, string dst_kind, string src_kind,
7163 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7164 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7165 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7172 let Inst{28-23} = 0b011110;
7173 let Inst{22-16} = fixed_imm;
7174 let Inst{15-11} = opc;
7180 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7181 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7182 RegisterOperand vectype1, RegisterOperand vectype2,
7184 string asm, string dst_kind, string src_kind,
7186 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7187 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7188 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7195 let Inst{28-23} = 0b011110;
7196 let Inst{22-16} = fixed_imm;
7197 let Inst{15-11} = opc;
7203 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7205 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7206 V64, V64, vecshiftR32,
7208 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7210 let Inst{20-16} = imm;
7213 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7214 V128, V128, vecshiftR32,
7216 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7218 let Inst{20-16} = imm;
7221 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7222 V128, V128, vecshiftR64,
7224 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7226 let Inst{21-16} = imm;
7230 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7232 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7233 V64, V64, vecshiftR32,
7235 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7237 let Inst{20-16} = imm;
7240 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7241 V128, V128, vecshiftR32,
7243 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7245 let Inst{20-16} = imm;
7248 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7249 V128, V128, vecshiftR64,
7251 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7253 let Inst{21-16} = imm;
7257 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7258 SDPatternOperator OpNode> {
7259 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7260 V64, V128, vecshiftR16Narrow,
7262 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7264 let Inst{18-16} = imm;
7267 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7268 V128, V128, vecshiftR16Narrow,
7269 asm#"2", ".16b", ".8h", []> {
7271 let Inst{18-16} = imm;
7272 let hasSideEffects = 0;
7275 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7276 V64, V128, vecshiftR32Narrow,
7278 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7280 let Inst{19-16} = imm;
7283 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7284 V128, V128, vecshiftR32Narrow,
7285 asm#"2", ".8h", ".4s", []> {
7287 let Inst{19-16} = imm;
7288 let hasSideEffects = 0;
7291 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7292 V64, V128, vecshiftR64Narrow,
7294 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7296 let Inst{20-16} = imm;
7299 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7300 V128, V128, vecshiftR64Narrow,
7301 asm#"2", ".4s", ".2d", []> {
7303 let Inst{20-16} = imm;
7304 let hasSideEffects = 0;
7307 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7308 // themselves, so put them here instead.
7310 // Patterns involving what's effectively an insert high and a normal
7311 // intrinsic, represented by CONCAT_VECTORS.
7312 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7313 vecshiftR16Narrow:$imm)),
7314 (!cast<Instruction>(NAME # "v16i8_shift")
7315 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7316 V128:$Rn, vecshiftR16Narrow:$imm)>;
7317 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7318 vecshiftR32Narrow:$imm)),
7319 (!cast<Instruction>(NAME # "v8i16_shift")
7320 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7321 V128:$Rn, vecshiftR32Narrow:$imm)>;
7322 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7323 vecshiftR64Narrow:$imm)),
7324 (!cast<Instruction>(NAME # "v4i32_shift")
7325 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7326 V128:$Rn, vecshiftR64Narrow:$imm)>;
7329 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7330 SDPatternOperator OpNode> {
7331 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7332 V64, V64, vecshiftL8,
7334 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7335 (i32 vecshiftL8:$imm)))]> {
7337 let Inst{18-16} = imm;
7340 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7341 V128, V128, vecshiftL8,
7342 asm, ".16b", ".16b",
7343 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7344 (i32 vecshiftL8:$imm)))]> {
7346 let Inst{18-16} = imm;
7349 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7350 V64, V64, vecshiftL16,
7352 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7353 (i32 vecshiftL16:$imm)))]> {
7355 let Inst{19-16} = imm;
7358 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7359 V128, V128, vecshiftL16,
7361 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7362 (i32 vecshiftL16:$imm)))]> {
7364 let Inst{19-16} = imm;
7367 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7368 V64, V64, vecshiftL32,
7370 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7371 (i32 vecshiftL32:$imm)))]> {
7373 let Inst{20-16} = imm;
7376 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7377 V128, V128, vecshiftL32,
7379 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7380 (i32 vecshiftL32:$imm)))]> {
7382 let Inst{20-16} = imm;
7385 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7386 V128, V128, vecshiftL64,
7388 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7389 (i32 vecshiftL64:$imm)))]> {
7391 let Inst{21-16} = imm;
7395 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7396 SDPatternOperator OpNode> {
7397 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7398 V64, V64, vecshiftR8,
7400 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7401 (i32 vecshiftR8:$imm)))]> {
7403 let Inst{18-16} = imm;
7406 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7407 V128, V128, vecshiftR8,
7408 asm, ".16b", ".16b",
7409 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7410 (i32 vecshiftR8:$imm)))]> {
7412 let Inst{18-16} = imm;
7415 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7416 V64, V64, vecshiftR16,
7418 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7419 (i32 vecshiftR16:$imm)))]> {
7421 let Inst{19-16} = imm;
7424 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7425 V128, V128, vecshiftR16,
7427 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7428 (i32 vecshiftR16:$imm)))]> {
7430 let Inst{19-16} = imm;
7433 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7434 V64, V64, vecshiftR32,
7436 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7437 (i32 vecshiftR32:$imm)))]> {
7439 let Inst{20-16} = imm;
7442 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7443 V128, V128, vecshiftR32,
7445 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7446 (i32 vecshiftR32:$imm)))]> {
7448 let Inst{20-16} = imm;
7451 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7452 V128, V128, vecshiftR64,
7454 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7455 (i32 vecshiftR64:$imm)))]> {
7457 let Inst{21-16} = imm;
7461 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7462 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7463 SDPatternOperator OpNode = null_frag> {
7464 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7465 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7466 [(set (v8i8 V64:$dst),
7467 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7468 (i32 vecshiftR8:$imm)))]> {
7470 let Inst{18-16} = imm;
7473 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7474 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7475 [(set (v16i8 V128:$dst),
7476 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7477 (i32 vecshiftR8:$imm)))]> {
7479 let Inst{18-16} = imm;
7482 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7483 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7484 [(set (v4i16 V64:$dst),
7485 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7486 (i32 vecshiftR16:$imm)))]> {
7488 let Inst{19-16} = imm;
7491 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7492 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7493 [(set (v8i16 V128:$dst),
7494 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7495 (i32 vecshiftR16:$imm)))]> {
7497 let Inst{19-16} = imm;
7500 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7501 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7502 [(set (v2i32 V64:$dst),
7503 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7504 (i32 vecshiftR32:$imm)))]> {
7506 let Inst{20-16} = imm;
7509 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7510 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7511 [(set (v4i32 V128:$dst),
7512 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7513 (i32 vecshiftR32:$imm)))]> {
7515 let Inst{20-16} = imm;
7518 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7519 V128, V128, vecshiftR64,
7520 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7521 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7522 (i32 vecshiftR64:$imm)))]> {
7524 let Inst{21-16} = imm;
7528 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7529 SDPatternOperator OpNode = null_frag> {
7530 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7531 V64, V64, vecshiftL8,
7533 [(set (v8i8 V64:$dst),
7534 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7535 (i32 vecshiftL8:$imm)))]> {
7537 let Inst{18-16} = imm;
7540 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7541 V128, V128, vecshiftL8,
7542 asm, ".16b", ".16b",
7543 [(set (v16i8 V128:$dst),
7544 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7545 (i32 vecshiftL8:$imm)))]> {
7547 let Inst{18-16} = imm;
7550 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7551 V64, V64, vecshiftL16,
7553 [(set (v4i16 V64:$dst),
7554 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7555 (i32 vecshiftL16:$imm)))]> {
7557 let Inst{19-16} = imm;
7560 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7561 V128, V128, vecshiftL16,
7563 [(set (v8i16 V128:$dst),
7564 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7565 (i32 vecshiftL16:$imm)))]> {
7567 let Inst{19-16} = imm;
7570 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7571 V64, V64, vecshiftL32,
7573 [(set (v2i32 V64:$dst),
7574 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7575 (i32 vecshiftL32:$imm)))]> {
7577 let Inst{20-16} = imm;
7580 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7581 V128, V128, vecshiftL32,
7583 [(set (v4i32 V128:$dst),
7584 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7585 (i32 vecshiftL32:$imm)))]> {
7587 let Inst{20-16} = imm;
7590 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7591 V128, V128, vecshiftL64,
7593 [(set (v2i64 V128:$dst),
7594 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7595 (i32 vecshiftL64:$imm)))]> {
7597 let Inst{21-16} = imm;
7601 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7602 SDPatternOperator OpNode> {
7603 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7604 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7605 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7607 let Inst{18-16} = imm;
7610 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7611 V128, V128, vecshiftL8,
7612 asm#"2", ".8h", ".16b",
7613 [(set (v8i16 V128:$Rd),
7614 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7616 let Inst{18-16} = imm;
7619 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7620 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7621 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7623 let Inst{19-16} = imm;
7626 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7627 V128, V128, vecshiftL16,
7628 asm#"2", ".4s", ".8h",
7629 [(set (v4i32 V128:$Rd),
7630 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7633 let Inst{19-16} = imm;
7636 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7637 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7638 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7640 let Inst{20-16} = imm;
7643 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7644 V128, V128, vecshiftL32,
7645 asm#"2", ".2d", ".4s",
7646 [(set (v2i64 V128:$Rd),
7647 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7649 let Inst{20-16} = imm;
7655 // Vector load/store
7657 // SIMD ldX/stX no-index memory references don't allow the optional
7658 // ", #0" constant and handle post-indexing explicitly, so we use
7659 // a more specialized parse method for them. Otherwise, it's the same as
7660 // the general GPR64sp handling.
7662 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7663 string asm, dag oops, dag iops, list<dag> pattern>
7664 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
7669 let Inst{29-23} = 0b0011000;
7671 let Inst{21-16} = 0b000000;
7672 let Inst{15-12} = opcode;
7673 let Inst{11-10} = size;
7678 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7679 string asm, dag oops, dag iops>
7680 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
7686 let Inst{29-23} = 0b0011001;
7689 let Inst{20-16} = Xm;
7690 let Inst{15-12} = opcode;
7691 let Inst{11-10} = size;
7696 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7697 // register post-index addressing from the zero register.
7698 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7699 int Offset, int Size> {
7700 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7701 // "ld1\t$Vt, [$Rn], #16"
7702 // may get mapped to
7703 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
7704 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7705 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7707 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7710 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7711 // "ld1.8b\t$Vt, [$Rn], #16"
7712 // may get mapped to
7713 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
7714 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
7715 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7717 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7720 // E.g. "ld1.8b { v0, v1 }, [x1]"
7721 // "ld1\t$Vt, [$Rn]"
7722 // may get mapped to
7723 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
7724 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
7725 (!cast<Instruction>(NAME # Count # "v" # layout)
7726 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7729 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7730 // "ld1\t$Vt, [$Rn], $Xm"
7731 // may get mapped to
7732 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
7733 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
7734 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7736 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7737 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7740 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7741 int Offset64, bits<4> opcode> {
7742 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7743 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7744 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7745 (ins GPR64sp:$Rn), []>;
7746 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7747 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7748 (ins GPR64sp:$Rn), []>;
7749 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7750 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7751 (ins GPR64sp:$Rn), []>;
7752 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7753 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7754 (ins GPR64sp:$Rn), []>;
7755 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7756 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7757 (ins GPR64sp:$Rn), []>;
7758 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7759 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7760 (ins GPR64sp:$Rn), []>;
7761 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7762 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7763 (ins GPR64sp:$Rn), []>;
7766 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7767 (outs GPR64sp:$wback,
7768 !cast<RegisterOperand>(veclist # "16b"):$Vt),
7770 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7771 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7772 (outs GPR64sp:$wback,
7773 !cast<RegisterOperand>(veclist # "8h"):$Vt),
7775 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7776 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7777 (outs GPR64sp:$wback,
7778 !cast<RegisterOperand>(veclist # "4s"):$Vt),
7780 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7781 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7782 (outs GPR64sp:$wback,
7783 !cast<RegisterOperand>(veclist # "2d"):$Vt),
7785 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7786 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7787 (outs GPR64sp:$wback,
7788 !cast<RegisterOperand>(veclist # "8b"):$Vt),
7790 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7791 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7792 (outs GPR64sp:$wback,
7793 !cast<RegisterOperand>(veclist # "4h"):$Vt),
7795 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7796 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7797 (outs GPR64sp:$wback,
7798 !cast<RegisterOperand>(veclist # "2s"):$Vt),
7800 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7803 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7804 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7805 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7806 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7807 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7808 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7809 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7812 // Only ld1/st1 has a v1d version.
7813 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7814 int Offset64, bits<4> opcode> {
7815 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7816 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7817 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7819 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7820 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7822 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7823 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7825 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7826 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7828 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7829 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7831 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7832 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7834 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7835 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7838 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7839 (outs GPR64sp:$wback),
7840 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7842 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7843 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
7844 (outs GPR64sp:$wback),
7845 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7847 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7848 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
7849 (outs GPR64sp:$wback),
7850 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7852 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7853 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
7854 (outs GPR64sp:$wback),
7855 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7857 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7858 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
7859 (outs GPR64sp:$wback),
7860 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7862 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7863 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
7864 (outs GPR64sp:$wback),
7865 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7867 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7868 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
7869 (outs GPR64sp:$wback),
7870 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7872 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7875 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7876 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7877 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7878 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7879 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7880 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7881 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7884 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
7885 int Offset128, int Offset64, bits<4> opcode>
7886 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7888 // LD1 instructions have extra "1d" variants.
7889 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7890 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
7891 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7892 (ins GPR64sp:$Rn), []>;
7894 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
7895 (outs GPR64sp:$wback,
7896 !cast<RegisterOperand>(veclist # "1d"):$Vt),
7898 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7901 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7904 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
7905 int Offset128, int Offset64, bits<4> opcode>
7906 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7908 // ST1 instructions have extra "1d" variants.
7909 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
7910 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
7911 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7914 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
7915 (outs GPR64sp:$wback),
7916 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7918 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7921 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7924 multiclass SIMDLd1Multiple<string asm> {
7925 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7926 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7927 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7928 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7931 multiclass SIMDSt1Multiple<string asm> {
7932 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7933 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7934 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7935 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7938 multiclass SIMDLd2Multiple<string asm> {
7939 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7942 multiclass SIMDSt2Multiple<string asm> {
7943 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7946 multiclass SIMDLd3Multiple<string asm> {
7947 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7950 multiclass SIMDSt3Multiple<string asm> {
7951 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7954 multiclass SIMDLd4Multiple<string asm> {
7955 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7958 multiclass SIMDSt4Multiple<string asm> {
7959 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7963 // AdvSIMD Load/store single-element
7966 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
7967 string asm, string operands, string cst,
7968 dag oops, dag iops, list<dag> pattern>
7969 : I<oops, iops, asm, operands, cst, pattern> {
7973 let Inst{29-24} = 0b001101;
7976 let Inst{15-13} = opcode;
7981 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
7982 string asm, string operands, string cst,
7983 dag oops, dag iops, list<dag> pattern>
7984 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
7988 let Inst{29-24} = 0b001101;
7991 let Inst{15-13} = opcode;
7997 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7998 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
8000 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
8001 (outs listtype:$Vt), (ins GPR64sp:$Rn),
8005 let Inst{20-16} = 0b00000;
8007 let Inst{11-10} = size;
8009 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8010 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
8011 string asm, Operand listtype, Operand GPR64pi>
8012 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
8014 (outs GPR64sp:$wback, listtype:$Vt),
8015 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
8019 let Inst{20-16} = Xm;
8021 let Inst{11-10} = size;
8024 multiclass SIMDLdrAliases<string asm, string layout, string Count,
8025 int Offset, int Size> {
8026 // E.g. "ld1r { v0.8b }, [x1], #1"
8027 // "ld1r.8b\t$Vt, [$Rn], #1"
8028 // may get mapped to
8029 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8030 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
8031 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8033 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8036 // E.g. "ld1r.8b { v0 }, [x1], #1"
8037 // "ld1r.8b\t$Vt, [$Rn], #1"
8038 // may get mapped to
8039 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8040 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8041 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8043 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8046 // E.g. "ld1r.8b { v0 }, [x1]"
8047 // "ld1r.8b\t$Vt, [$Rn]"
8048 // may get mapped to
8049 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8050 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8051 (!cast<Instruction>(NAME # "v" # layout)
8052 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8055 // E.g. "ld1r.8b { v0 }, [x1], x2"
8056 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8057 // may get mapped to
8058 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8059 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8060 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8062 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8063 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8066 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
8067 int Offset1, int Offset2, int Offset4, int Offset8> {
8068 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8069 !cast<Operand>("VecList" # Count # "8b")>;
8070 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8071 !cast<Operand>("VecList" # Count #"16b")>;
8072 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8073 !cast<Operand>("VecList" # Count #"4h")>;
8074 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8075 !cast<Operand>("VecList" # Count #"8h")>;
8076 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
8077 !cast<Operand>("VecList" # Count #"2s")>;
8078 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
8079 !cast<Operand>("VecList" # Count #"4s")>;
8080 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
8081 !cast<Operand>("VecList" # Count #"1d")>;
8082 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
8083 !cast<Operand>("VecList" # Count #"2d")>;
8085 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8086 !cast<Operand>("VecList" # Count # "8b"),
8087 !cast<Operand>("GPR64pi" # Offset1)>;
8088 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8089 !cast<Operand>("VecList" # Count # "16b"),
8090 !cast<Operand>("GPR64pi" # Offset1)>;
8091 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8092 !cast<Operand>("VecList" # Count # "4h"),
8093 !cast<Operand>("GPR64pi" # Offset2)>;
8094 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
8095 !cast<Operand>("VecList" # Count # "8h"),
8096 !cast<Operand>("GPR64pi" # Offset2)>;
8097 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
8098 !cast<Operand>("VecList" # Count # "2s"),
8099 !cast<Operand>("GPR64pi" # Offset4)>;
8100 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
8101 !cast<Operand>("VecList" # Count # "4s"),
8102 !cast<Operand>("GPR64pi" # Offset4)>;
8103 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
8104 !cast<Operand>("VecList" # Count # "1d"),
8105 !cast<Operand>("GPR64pi" # Offset8)>;
8106 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
8107 !cast<Operand>("VecList" # Count # "2d"),
8108 !cast<Operand>("GPR64pi" # Offset8)>;
8110 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8111 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
8112 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8113 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
8114 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
8115 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
8116 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
8117 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
8120 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
8121 dag oops, dag iops, list<dag> pattern>
8122 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8124 // idx encoded in Q:S:size fields.
8126 let Inst{30} = idx{3};
8128 let Inst{20-16} = 0b00000;
8129 let Inst{12} = idx{2};
8130 let Inst{11-10} = idx{1-0};
8132 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
8133 dag oops, dag iops, list<dag> pattern>
8134 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8135 oops, iops, pattern> {
8136 // idx encoded in Q:S:size fields.
8138 let Inst{30} = idx{3};
8140 let Inst{20-16} = 0b00000;
8141 let Inst{12} = idx{2};
8142 let Inst{11-10} = idx{1-0};
8144 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
8146 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8147 "$Rn = $wback", oops, iops, []> {
8148 // idx encoded in Q:S:size fields.
8151 let Inst{30} = idx{3};
8153 let Inst{20-16} = Xm;
8154 let Inst{12} = idx{2};
8155 let Inst{11-10} = idx{1-0};
8157 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
8159 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8160 "$Rn = $wback", oops, iops, []> {
8161 // idx encoded in Q:S:size fields.
8164 let Inst{30} = idx{3};
8166 let Inst{20-16} = Xm;
8167 let Inst{12} = idx{2};
8168 let Inst{11-10} = idx{1-0};
8171 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8172 dag oops, dag iops, list<dag> pattern>
8173 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8175 // idx encoded in Q:S:size<1> fields.
8177 let Inst{30} = idx{2};
8179 let Inst{20-16} = 0b00000;
8180 let Inst{12} = idx{1};
8181 let Inst{11} = idx{0};
8182 let Inst{10} = size;
8184 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8185 dag oops, dag iops, list<dag> pattern>
8186 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8187 oops, iops, pattern> {
8188 // idx encoded in Q:S:size<1> fields.
8190 let Inst{30} = idx{2};
8192 let Inst{20-16} = 0b00000;
8193 let Inst{12} = idx{1};
8194 let Inst{11} = idx{0};
8195 let Inst{10} = size;
8198 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8200 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8201 "$Rn = $wback", oops, iops, []> {
8202 // idx encoded in Q:S:size<1> fields.
8205 let Inst{30} = idx{2};
8207 let Inst{20-16} = Xm;
8208 let Inst{12} = idx{1};
8209 let Inst{11} = idx{0};
8210 let Inst{10} = size;
8212 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8214 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8215 "$Rn = $wback", oops, iops, []> {
8216 // idx encoded in Q:S:size<1> fields.
8219 let Inst{30} = idx{2};
8221 let Inst{20-16} = Xm;
8222 let Inst{12} = idx{1};
8223 let Inst{11} = idx{0};
8224 let Inst{10} = size;
8226 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8227 dag oops, dag iops, list<dag> pattern>
8228 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8230 // idx encoded in Q:S fields.
8232 let Inst{30} = idx{1};
8234 let Inst{20-16} = 0b00000;
8235 let Inst{12} = idx{0};
8236 let Inst{11-10} = size;
8238 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8239 dag oops, dag iops, list<dag> pattern>
8240 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8241 oops, iops, pattern> {
8242 // idx encoded in Q:S fields.
8244 let Inst{30} = idx{1};
8246 let Inst{20-16} = 0b00000;
8247 let Inst{12} = idx{0};
8248 let Inst{11-10} = size;
8250 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8251 string asm, dag oops, dag iops>
8252 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8253 "$Rn = $wback", oops, iops, []> {
8254 // idx encoded in Q:S fields.
8257 let Inst{30} = idx{1};
8259 let Inst{20-16} = Xm;
8260 let Inst{12} = idx{0};
8261 let Inst{11-10} = size;
8263 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8264 string asm, dag oops, dag iops>
8265 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8266 "$Rn = $wback", oops, iops, []> {
8267 // idx encoded in Q:S fields.
8270 let Inst{30} = idx{1};
8272 let Inst{20-16} = Xm;
8273 let Inst{12} = idx{0};
8274 let Inst{11-10} = size;
8276 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8277 dag oops, dag iops, list<dag> pattern>
8278 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8280 // idx encoded in Q field.
8284 let Inst{20-16} = 0b00000;
8286 let Inst{11-10} = size;
8288 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8289 dag oops, dag iops, list<dag> pattern>
8290 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8291 oops, iops, pattern> {
8292 // idx encoded in Q field.
8296 let Inst{20-16} = 0b00000;
8298 let Inst{11-10} = size;
8300 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8301 string asm, dag oops, dag iops>
8302 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8303 "$Rn = $wback", oops, iops, []> {
8304 // idx encoded in Q field.
8309 let Inst{20-16} = Xm;
8311 let Inst{11-10} = size;
8313 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8314 string asm, dag oops, dag iops>
8315 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8316 "$Rn = $wback", oops, iops, []> {
8317 // idx encoded in Q field.
8322 let Inst{20-16} = Xm;
8324 let Inst{11-10} = size;
8327 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8328 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8329 RegisterOperand listtype,
8330 RegisterOperand GPR64pi> {
8331 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8332 (outs listtype:$dst),
8333 (ins listtype:$Vt, VectorIndexB:$idx,
8336 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8337 (outs GPR64sp:$wback, listtype:$dst),
8338 (ins listtype:$Vt, VectorIndexB:$idx,
8339 GPR64sp:$Rn, GPR64pi:$Xm)>;
8341 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8342 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8343 RegisterOperand listtype,
8344 RegisterOperand GPR64pi> {
8345 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8346 (outs listtype:$dst),
8347 (ins listtype:$Vt, VectorIndexH:$idx,
8350 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8351 (outs GPR64sp:$wback, listtype:$dst),
8352 (ins listtype:$Vt, VectorIndexH:$idx,
8353 GPR64sp:$Rn, GPR64pi:$Xm)>;
8355 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8356 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8357 RegisterOperand listtype,
8358 RegisterOperand GPR64pi> {
8359 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8360 (outs listtype:$dst),
8361 (ins listtype:$Vt, VectorIndexS:$idx,
8364 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8365 (outs GPR64sp:$wback, listtype:$dst),
8366 (ins listtype:$Vt, VectorIndexS:$idx,
8367 GPR64sp:$Rn, GPR64pi:$Xm)>;
8369 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8370 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8371 RegisterOperand listtype, RegisterOperand GPR64pi> {
8372 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8373 (outs listtype:$dst),
8374 (ins listtype:$Vt, VectorIndexD:$idx,
8377 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8378 (outs GPR64sp:$wback, listtype:$dst),
8379 (ins listtype:$Vt, VectorIndexD:$idx,
8380 GPR64sp:$Rn, GPR64pi:$Xm)>;
8382 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8383 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8384 RegisterOperand listtype, RegisterOperand GPR64pi> {
8385 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8386 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8389 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8390 (outs GPR64sp:$wback),
8391 (ins listtype:$Vt, VectorIndexB:$idx,
8392 GPR64sp:$Rn, GPR64pi:$Xm)>;
8394 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8395 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8396 RegisterOperand listtype, RegisterOperand GPR64pi> {
8397 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8398 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8401 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8402 (outs GPR64sp:$wback),
8403 (ins listtype:$Vt, VectorIndexH:$idx,
8404 GPR64sp:$Rn, GPR64pi:$Xm)>;
8406 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8407 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8408 RegisterOperand listtype, RegisterOperand GPR64pi> {
8409 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8410 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8413 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8414 (outs GPR64sp:$wback),
8415 (ins listtype:$Vt, VectorIndexS:$idx,
8416 GPR64sp:$Rn, GPR64pi:$Xm)>;
8418 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8419 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8420 RegisterOperand listtype, RegisterOperand GPR64pi> {
8421 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8422 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8425 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8426 (outs GPR64sp:$wback),
8427 (ins listtype:$Vt, VectorIndexD:$idx,
8428 GPR64sp:$Rn, GPR64pi:$Xm)>;
8431 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8432 string Count, int Offset, Operand idxtype> {
8433 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8434 // "ld1\t$Vt, [$Rn], #1"
8435 // may get mapped to
8436 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8437 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8438 (!cast<Instruction>(NAME # Type # "_POST")
8440 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8441 idxtype:$idx, XZR), 1>;
8443 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8444 // "ld1.8b\t$Vt, [$Rn], #1"
8445 // may get mapped to
8446 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8447 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8448 (!cast<Instruction>(NAME # Type # "_POST")
8450 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8451 idxtype:$idx, XZR), 0>;
8453 // E.g. "ld1.8b { v0 }[0], [x1]"
8454 // "ld1.8b\t$Vt, [$Rn]"
8455 // may get mapped to
8456 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8457 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8458 (!cast<Instruction>(NAME # Type)
8459 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8460 idxtype:$idx, GPR64sp:$Rn), 0>;
8462 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8463 // "ld1.8b\t$Vt, [$Rn], $Xm"
8464 // may get mapped to
8465 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8466 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8467 (!cast<Instruction>(NAME # Type # "_POST")
8469 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8471 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8474 multiclass SIMDLdSt1SingleAliases<string asm> {
8475 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8476 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8477 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8478 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8481 multiclass SIMDLdSt2SingleAliases<string asm> {
8482 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8483 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8484 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8485 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8488 multiclass SIMDLdSt3SingleAliases<string asm> {
8489 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8490 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8491 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8492 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8495 multiclass SIMDLdSt4SingleAliases<string asm> {
8496 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8497 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8498 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8499 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8501 } // end of 'let Predicates = [HasNEON]'
8503 //----------------------------------------------------------------------------
8504 // Crypto extensions
8505 //----------------------------------------------------------------------------
8507 let Predicates = [HasCrypto] in {
8508 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8509 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8511 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8515 let Inst{31-16} = 0b0100111000101000;
8516 let Inst{15-12} = opc;
8517 let Inst{11-10} = 0b10;
8522 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8523 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8524 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8526 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8527 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8529 [(set (v16i8 V128:$dst),
8530 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8532 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8533 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8534 dag oops, dag iops, list<dag> pat>
8535 : I<oops, iops, asm,
8536 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8537 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8542 let Inst{31-21} = 0b01011110000;
8543 let Inst{20-16} = Rm;
8545 let Inst{14-12} = opc;
8546 let Inst{11-10} = 0b00;
8551 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8552 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8553 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8554 [(set (v4i32 FPR128:$dst),
8555 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8556 (v4i32 V128:$Rm)))]>;
8558 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8559 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8560 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8561 [(set (v4i32 V128:$dst),
8562 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8563 (v4i32 V128:$Rm)))]>;
8565 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8566 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8567 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8568 [(set (v4i32 FPR128:$dst),
8569 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8570 (v4i32 V128:$Rm)))]>;
8572 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8573 class SHA2OpInst<bits<4> opc, string asm, string kind,
8574 string cstr, dag oops, dag iops,
8576 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8577 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8581 let Inst{31-16} = 0b0101111000101000;
8582 let Inst{15-12} = opc;
8583 let Inst{11-10} = 0b10;
8588 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8589 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8590 (ins V128:$Rd, V128:$Rn),
8591 [(set (v4i32 V128:$dst),
8592 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8594 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8595 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8596 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8597 } // end of 'let Predicates = [HasCrypto]'
8599 // Allow the size specifier tokens to be upper case, not just lower.
8600 def : TokenAlias<".8B", ".8b">;
8601 def : TokenAlias<".4H", ".4h">;
8602 def : TokenAlias<".2S", ".2s">;
8603 def : TokenAlias<".1D", ".1d">;
8604 def : TokenAlias<".16B", ".16b">;
8605 def : TokenAlias<".8H", ".8h">;
8606 def : TokenAlias<".4S", ".4s">;
8607 def : TokenAlias<".2D", ".2d">;
8608 def : TokenAlias<".1Q", ".1q">;
8609 def : TokenAlias<".B", ".b">;
8610 def : TokenAlias<".H", ".h">;
8611 def : TokenAlias<".S", ".s">;
8612 def : TokenAlias<".D", ".d">;
8613 def : TokenAlias<".Q", ".q">;