1 //===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe AArch64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // AArch64 Instruction Format
25 class AArch64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "AArch64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : AArch64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
94 let DiagnosticType = "InvalidMovImm32Shift";
96 def MovImm64ShifterOperand : AsmOperandClass {
97 let SuperClasses = [ShifterOperand];
98 let Name = "MovImm64Shifter";
99 let RenderMethod = "addShifterOperands";
100 let DiagnosticType = "InvalidMovImm64Shift";
103 // Shifter operand for arithmetic register shifted encodings.
104 class ArithmeticShifterOperand<int width> : AsmOperandClass {
105 let SuperClasses = [ShifterOperand];
106 let Name = "ArithmeticShifter" # width;
107 let PredicateMethod = "isArithmeticShifter<" # width # ">";
108 let RenderMethod = "addShifterOperands";
109 let DiagnosticType = "AddSubRegShift" # width;
112 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
113 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
115 // Shifter operand for logical register shifted encodings.
116 class LogicalShifterOperand<int width> : AsmOperandClass {
117 let SuperClasses = [ShifterOperand];
118 let Name = "LogicalShifter" # width;
119 let PredicateMethod = "isLogicalShifter<" # width # ">";
120 let RenderMethod = "addShifterOperands";
121 let DiagnosticType = "AddSubRegShift" # width;
124 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
125 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
127 // Shifter operand for logical vector 128/64-bit shifted encodings.
128 def LogicalVecShifterOperand : AsmOperandClass {
129 let SuperClasses = [ShifterOperand];
130 let Name = "LogicalVecShifter";
131 let RenderMethod = "addShifterOperands";
133 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
134 let SuperClasses = [LogicalVecShifterOperand];
135 let Name = "LogicalVecHalfWordShifter";
136 let RenderMethod = "addShifterOperands";
139 // The "MSL" shifter on the vector MOVI instruction.
140 def MoveVecShifterOperand : AsmOperandClass {
141 let SuperClasses = [ShifterOperand];
142 let Name = "MoveVecShifter";
143 let RenderMethod = "addShifterOperands";
146 // Extend operand for arithmetic encodings.
147 def ExtendOperand : AsmOperandClass {
149 let DiagnosticType = "AddSubRegExtendLarge";
151 def ExtendOperand64 : AsmOperandClass {
152 let SuperClasses = [ExtendOperand];
153 let Name = "Extend64";
154 let DiagnosticType = "AddSubRegExtendSmall";
156 // 'extend' that's a lsl of a 64-bit register.
157 def ExtendOperandLSL64 : AsmOperandClass {
158 let SuperClasses = [ExtendOperand];
159 let Name = "ExtendLSL64";
160 let RenderMethod = "addExtend64Operands";
161 let DiagnosticType = "AddSubRegExtendLarge";
164 // 8-bit floating-point immediate encodings.
165 def FPImmOperand : AsmOperandClass {
167 let ParserMethod = "tryParseFPImm";
168 let DiagnosticType = "InvalidFPImm";
171 def CondCode : AsmOperandClass {
172 let Name = "CondCode";
173 let DiagnosticType = "InvalidCondCode";
176 // A 32-bit register pasrsed as 64-bit
177 def GPR32as64Operand : AsmOperandClass {
178 let Name = "GPR32as64";
180 def GPR32as64 : RegisterOperand<GPR32> {
181 let ParserMatchClass = GPR32as64Operand;
184 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
185 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
186 // are encoded as the eight bit value 'abcdefgh'.
187 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
190 //===----------------------------------------------------------------------===//
191 // Operand Definitions.
194 // ADR[P] instruction labels.
195 def AdrpOperand : AsmOperandClass {
196 let Name = "AdrpLabel";
197 let ParserMethod = "tryParseAdrpLabel";
198 let DiagnosticType = "InvalidLabel";
200 def adrplabel : Operand<i64> {
201 let EncoderMethod = "getAdrLabelOpValue";
202 let PrintMethod = "printAdrpLabel";
203 let ParserMatchClass = AdrpOperand;
206 def AdrOperand : AsmOperandClass {
207 let Name = "AdrLabel";
208 let ParserMethod = "tryParseAdrLabel";
209 let DiagnosticType = "InvalidLabel";
211 def adrlabel : Operand<i64> {
212 let EncoderMethod = "getAdrLabelOpValue";
213 let ParserMatchClass = AdrOperand;
216 // simm9 predicate - True if the immediate is in the range [-256, 255].
217 def SImm9Operand : AsmOperandClass {
219 let DiagnosticType = "InvalidMemoryIndexedSImm9";
221 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
222 let ParserMatchClass = SImm9Operand;
225 // simm7sN predicate - True if the immediate is a multiple of N in the range
226 // [-64 * N, 63 * N].
227 class SImm7Scaled<int Scale> : AsmOperandClass {
228 let Name = "SImm7s" # Scale;
229 let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm7";
232 def SImm7s4Operand : SImm7Scaled<4>;
233 def SImm7s8Operand : SImm7Scaled<8>;
234 def SImm7s16Operand : SImm7Scaled<16>;
236 def simm7s4 : Operand<i32> {
237 let ParserMatchClass = SImm7s4Operand;
238 let PrintMethod = "printImmScale<4>";
241 def simm7s8 : Operand<i32> {
242 let ParserMatchClass = SImm7s8Operand;
243 let PrintMethod = "printImmScale<8>";
246 def simm7s16 : Operand<i32> {
247 let ParserMatchClass = SImm7s16Operand;
248 let PrintMethod = "printImmScale<16>";
251 class AsmImmRange<int Low, int High> : AsmOperandClass {
252 let Name = "Imm" # Low # "_" # High;
253 let DiagnosticType = "InvalidImm" # Low # "_" # High;
256 def Imm1_8Operand : AsmImmRange<1, 8>;
257 def Imm1_16Operand : AsmImmRange<1, 16>;
258 def Imm1_32Operand : AsmImmRange<1, 32>;
259 def Imm1_64Operand : AsmImmRange<1, 64>;
261 def MovZSymbolG3AsmOperand : AsmOperandClass {
262 let Name = "MovZSymbolG3";
263 let RenderMethod = "addImmOperands";
266 def movz_symbol_g3 : Operand<i32> {
267 let ParserMatchClass = MovZSymbolG3AsmOperand;
270 def MovZSymbolG2AsmOperand : AsmOperandClass {
271 let Name = "MovZSymbolG2";
272 let RenderMethod = "addImmOperands";
275 def movz_symbol_g2 : Operand<i32> {
276 let ParserMatchClass = MovZSymbolG2AsmOperand;
279 def MovZSymbolG1AsmOperand : AsmOperandClass {
280 let Name = "MovZSymbolG1";
281 let RenderMethod = "addImmOperands";
284 def movz_symbol_g1 : Operand<i32> {
285 let ParserMatchClass = MovZSymbolG1AsmOperand;
288 def MovZSymbolG0AsmOperand : AsmOperandClass {
289 let Name = "MovZSymbolG0";
290 let RenderMethod = "addImmOperands";
293 def movz_symbol_g0 : Operand<i32> {
294 let ParserMatchClass = MovZSymbolG0AsmOperand;
297 def MovKSymbolG3AsmOperand : AsmOperandClass {
298 let Name = "MovKSymbolG3";
299 let RenderMethod = "addImmOperands";
302 def movk_symbol_g3 : Operand<i32> {
303 let ParserMatchClass = MovKSymbolG3AsmOperand;
306 def MovKSymbolG2AsmOperand : AsmOperandClass {
307 let Name = "MovKSymbolG2";
308 let RenderMethod = "addImmOperands";
311 def movk_symbol_g2 : Operand<i32> {
312 let ParserMatchClass = MovKSymbolG2AsmOperand;
315 def MovKSymbolG1AsmOperand : AsmOperandClass {
316 let Name = "MovKSymbolG1";
317 let RenderMethod = "addImmOperands";
320 def movk_symbol_g1 : Operand<i32> {
321 let ParserMatchClass = MovKSymbolG1AsmOperand;
324 def MovKSymbolG0AsmOperand : AsmOperandClass {
325 let Name = "MovKSymbolG0";
326 let RenderMethod = "addImmOperands";
329 def movk_symbol_g0 : Operand<i32> {
330 let ParserMatchClass = MovKSymbolG0AsmOperand;
333 class fixedpoint_i32<ValueType FloatVT>
335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
336 let EncoderMethod = "getFixedPointScaleOpValue";
337 let DecoderMethod = "DecodeFixedPointScaleImm32";
338 let ParserMatchClass = Imm1_32Operand;
341 class fixedpoint_i64<ValueType FloatVT>
343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
344 let EncoderMethod = "getFixedPointScaleOpValue";
345 let DecoderMethod = "DecodeFixedPointScaleImm64";
346 let ParserMatchClass = Imm1_64Operand;
349 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
350 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
352 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
353 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
355 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
356 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
358 let EncoderMethod = "getVecShiftR8OpValue";
359 let DecoderMethod = "DecodeVecShiftR8Imm";
360 let ParserMatchClass = Imm1_8Operand;
362 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
363 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
365 let EncoderMethod = "getVecShiftR16OpValue";
366 let DecoderMethod = "DecodeVecShiftR16Imm";
367 let ParserMatchClass = Imm1_16Operand;
369 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
370 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
372 let EncoderMethod = "getVecShiftR16OpValue";
373 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
374 let ParserMatchClass = Imm1_8Operand;
376 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
377 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
379 let EncoderMethod = "getVecShiftR32OpValue";
380 let DecoderMethod = "DecodeVecShiftR32Imm";
381 let ParserMatchClass = Imm1_32Operand;
383 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
384 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
386 let EncoderMethod = "getVecShiftR32OpValue";
387 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
388 let ParserMatchClass = Imm1_16Operand;
390 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
391 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
393 let EncoderMethod = "getVecShiftR64OpValue";
394 let DecoderMethod = "DecodeVecShiftR64Imm";
395 let ParserMatchClass = Imm1_64Operand;
397 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
398 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
400 let EncoderMethod = "getVecShiftR64OpValue";
401 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
402 let ParserMatchClass = Imm1_32Operand;
405 def Imm0_7Operand : AsmImmRange<0, 7>;
406 def Imm0_15Operand : AsmImmRange<0, 15>;
407 def Imm0_31Operand : AsmImmRange<0, 31>;
408 def Imm0_63Operand : AsmImmRange<0, 63>;
410 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
411 return (((uint32_t)Imm) < 8);
413 let EncoderMethod = "getVecShiftL8OpValue";
414 let DecoderMethod = "DecodeVecShiftL8Imm";
415 let ParserMatchClass = Imm0_7Operand;
417 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
418 return (((uint32_t)Imm) < 16);
420 let EncoderMethod = "getVecShiftL16OpValue";
421 let DecoderMethod = "DecodeVecShiftL16Imm";
422 let ParserMatchClass = Imm0_15Operand;
424 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
425 return (((uint32_t)Imm) < 32);
427 let EncoderMethod = "getVecShiftL32OpValue";
428 let DecoderMethod = "DecodeVecShiftL32Imm";
429 let ParserMatchClass = Imm0_31Operand;
431 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
432 return (((uint32_t)Imm) < 64);
434 let EncoderMethod = "getVecShiftL64OpValue";
435 let DecoderMethod = "DecodeVecShiftL64Imm";
436 let ParserMatchClass = Imm0_63Operand;
440 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
441 // instructions for splatting repeating bit patterns across the immediate.
442 def logical_imm32_XFORM : SDNodeXForm<imm, [{
443 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
444 return CurDAG->getTargetConstant(enc, MVT::i32);
446 def logical_imm64_XFORM : SDNodeXForm<imm, [{
447 uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
448 return CurDAG->getTargetConstant(enc, MVT::i32);
451 def LogicalImm32Operand : AsmOperandClass {
452 let Name = "LogicalImm32";
453 let DiagnosticType = "LogicalSecondSource";
455 def LogicalImm64Operand : AsmOperandClass {
456 let Name = "LogicalImm64";
457 let DiagnosticType = "LogicalSecondSource";
459 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
460 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 32);
461 }], logical_imm32_XFORM> {
462 let PrintMethod = "printLogicalImm32";
463 let ParserMatchClass = LogicalImm32Operand;
465 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
466 return AArch64_AM::isLogicalImmediate(N->getZExtValue(), 64);
467 }], logical_imm64_XFORM> {
468 let PrintMethod = "printLogicalImm64";
469 let ParserMatchClass = LogicalImm64Operand;
472 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
473 def Imm0_65535Operand : AsmImmRange<0, 65535>;
474 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
475 return ((uint32_t)Imm) < 65536;
477 let ParserMatchClass = Imm0_65535Operand;
478 let PrintMethod = "printHexImm";
481 // imm0_255 predicate - True if the immediate is in the range [0,255].
482 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
483 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
484 return ((uint32_t)Imm) < 256;
486 let ParserMatchClass = Imm0_255Operand;
487 let PrintMethod = "printHexImm";
490 // imm0_127 predicate - True if the immediate is in the range [0,127]
491 def Imm0_127Operand : AsmImmRange<0, 127>;
492 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
493 return ((uint32_t)Imm) < 128;
495 let ParserMatchClass = Imm0_127Operand;
496 let PrintMethod = "printHexImm";
499 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
500 // for all shift-amounts.
502 // imm0_63 predicate - True if the immediate is in the range [0,63]
503 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
504 return ((uint64_t)Imm) < 64;
506 let ParserMatchClass = Imm0_63Operand;
509 // imm0_31 predicate - True if the immediate is in the range [0,31]
510 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
511 return ((uint64_t)Imm) < 32;
513 let ParserMatchClass = Imm0_31Operand;
516 // imm0_15 predicate - True if the immediate is in the range [0,15]
517 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
518 return ((uint64_t)Imm) < 16;
520 let ParserMatchClass = Imm0_15Operand;
523 // imm0_7 predicate - True if the immediate is in the range [0,7]
524 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
525 return ((uint64_t)Imm) < 8;
527 let ParserMatchClass = Imm0_7Operand;
530 // An arithmetic shifter operand:
531 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
533 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
534 let PrintMethod = "printShifter";
535 let ParserMatchClass = !cast<AsmOperandClass>(
536 "ArithmeticShifterOperand" # width);
539 def arith_shift32 : arith_shift<i32, 32>;
540 def arith_shift64 : arith_shift<i64, 64>;
542 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
544 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
545 let PrintMethod = "printShiftedRegister";
546 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
549 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
550 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
552 // An arithmetic shifter operand:
553 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
555 class logical_shift<int width> : Operand<i32> {
556 let PrintMethod = "printShifter";
557 let ParserMatchClass = !cast<AsmOperandClass>(
558 "LogicalShifterOperand" # width);
561 def logical_shift32 : logical_shift<32>;
562 def logical_shift64 : logical_shift<64>;
564 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
566 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
567 let PrintMethod = "printShiftedRegister";
568 let MIOperandInfo = (ops regclass, shiftop);
571 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
572 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
574 // A logical vector shifter operand:
575 // {7-6} - shift type: 00 = lsl
576 // {5-0} - imm6: #0, #8, #16, or #24
577 def logical_vec_shift : Operand<i32> {
578 let PrintMethod = "printShifter";
579 let EncoderMethod = "getVecShifterOpValue";
580 let ParserMatchClass = LogicalVecShifterOperand;
583 // A logical vector half-word shifter operand:
584 // {7-6} - shift type: 00 = lsl
585 // {5-0} - imm6: #0 or #8
586 def logical_vec_hw_shift : Operand<i32> {
587 let PrintMethod = "printShifter";
588 let EncoderMethod = "getVecShifterOpValue";
589 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
592 // A vector move shifter operand:
593 // {0} - imm1: #8 or #16
594 def move_vec_shift : Operand<i32> {
595 let PrintMethod = "printShifter";
596 let EncoderMethod = "getMoveVecShifterOpValue";
597 let ParserMatchClass = MoveVecShifterOperand;
600 def AddSubImmOperand : AsmOperandClass {
601 let Name = "AddSubImm";
602 let ParserMethod = "tryParseAddSubImm";
603 let DiagnosticType = "AddSubSecondSource";
605 // An ADD/SUB immediate shifter operand:
607 // {7-6} - shift type: 00 = lsl
608 // {5-0} - imm6: #0 or #12
609 class addsub_shifted_imm<ValueType Ty>
610 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
611 let PrintMethod = "printAddSubImm";
612 let EncoderMethod = "getAddSubImmOpValue";
613 let ParserMatchClass = AddSubImmOperand;
614 let MIOperandInfo = (ops i32imm, i32imm);
617 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
618 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
620 class neg_addsub_shifted_imm<ValueType Ty>
621 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
622 let PrintMethod = "printAddSubImm";
623 let EncoderMethod = "getAddSubImmOpValue";
624 let ParserMatchClass = AddSubImmOperand;
625 let MIOperandInfo = (ops i32imm, i32imm);
628 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
629 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
631 // An extend operand:
632 // {5-3} - extend type
634 def arith_extend : Operand<i32> {
635 let PrintMethod = "printArithExtend";
636 let ParserMatchClass = ExtendOperand;
638 def arith_extend64 : Operand<i32> {
639 let PrintMethod = "printArithExtend";
640 let ParserMatchClass = ExtendOperand64;
643 // 'extend' that's a lsl of a 64-bit register.
644 def arith_extendlsl64 : Operand<i32> {
645 let PrintMethod = "printArithExtend";
646 let ParserMatchClass = ExtendOperandLSL64;
649 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
650 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
651 let PrintMethod = "printExtendedRegister";
652 let MIOperandInfo = (ops GPR32, arith_extend);
655 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
656 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
657 let PrintMethod = "printExtendedRegister";
658 let MIOperandInfo = (ops GPR32, arith_extend64);
661 // Floating-point immediate.
662 def fpimm32 : Operand<f32>,
663 PatLeaf<(f32 fpimm), [{
664 return AArch64_AM::getFP32Imm(N->getValueAPF()) != -1;
665 }], SDNodeXForm<fpimm, [{
666 APFloat InVal = N->getValueAPF();
667 uint32_t enc = AArch64_AM::getFP32Imm(InVal);
668 return CurDAG->getTargetConstant(enc, MVT::i32);
670 let ParserMatchClass = FPImmOperand;
671 let PrintMethod = "printFPImmOperand";
673 def fpimm64 : Operand<f64>,
674 PatLeaf<(f64 fpimm), [{
675 return AArch64_AM::getFP64Imm(N->getValueAPF()) != -1;
676 }], SDNodeXForm<fpimm, [{
677 APFloat InVal = N->getValueAPF();
678 uint32_t enc = AArch64_AM::getFP64Imm(InVal);
679 return CurDAG->getTargetConstant(enc, MVT::i32);
681 let ParserMatchClass = FPImmOperand;
682 let PrintMethod = "printFPImmOperand";
685 def fpimm8 : Operand<i32> {
686 let ParserMatchClass = FPImmOperand;
687 let PrintMethod = "printFPImmOperand";
690 def fpimm0 : PatLeaf<(fpimm), [{
691 return N->isExactlyValue(+0.0);
694 // Vector lane operands
695 class AsmVectorIndex<string Suffix> : AsmOperandClass {
696 let Name = "VectorIndex" # Suffix;
697 let DiagnosticType = "InvalidIndex" # Suffix;
699 def VectorIndex1Operand : AsmVectorIndex<"1">;
700 def VectorIndexBOperand : AsmVectorIndex<"B">;
701 def VectorIndexHOperand : AsmVectorIndex<"H">;
702 def VectorIndexSOperand : AsmVectorIndex<"S">;
703 def VectorIndexDOperand : AsmVectorIndex<"D">;
705 def VectorIndex1 : Operand<i64>, ImmLeaf<i64, [{
706 return ((uint64_t)Imm) == 1;
708 let ParserMatchClass = VectorIndex1Operand;
709 let PrintMethod = "printVectorIndex";
710 let MIOperandInfo = (ops i64imm);
712 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
713 return ((uint64_t)Imm) < 16;
715 let ParserMatchClass = VectorIndexBOperand;
716 let PrintMethod = "printVectorIndex";
717 let MIOperandInfo = (ops i64imm);
719 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
720 return ((uint64_t)Imm) < 8;
722 let ParserMatchClass = VectorIndexHOperand;
723 let PrintMethod = "printVectorIndex";
724 let MIOperandInfo = (ops i64imm);
726 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
727 return ((uint64_t)Imm) < 4;
729 let ParserMatchClass = VectorIndexSOperand;
730 let PrintMethod = "printVectorIndex";
731 let MIOperandInfo = (ops i64imm);
733 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
734 return ((uint64_t)Imm) < 2;
736 let ParserMatchClass = VectorIndexDOperand;
737 let PrintMethod = "printVectorIndex";
738 let MIOperandInfo = (ops i64imm);
741 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
742 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
743 // are encoded as the eight bit value 'abcdefgh'.
744 def simdimmtype10 : Operand<i32>,
745 PatLeaf<(f64 fpimm), [{
746 return AArch64_AM::isAdvSIMDModImmType10(N->getValueAPF()
749 }], SDNodeXForm<fpimm, [{
750 APFloat InVal = N->getValueAPF();
751 uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
754 return CurDAG->getTargetConstant(enc, MVT::i32);
756 let ParserMatchClass = SIMDImmType10Operand;
757 let PrintMethod = "printSIMDType10Operand";
765 // Base encoding for system instruction operands.
766 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
767 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands>
768 : I<oops, iops, asm, operands, "", []> {
769 let Inst{31-22} = 0b1101010100;
773 // System instructions which do not have an Rt register.
774 class SimpleSystemI<bit L, dag iops, string asm, string operands>
775 : BaseSystemI<L, (outs), iops, asm, operands> {
776 let Inst{4-0} = 0b11111;
779 // System instructions which have an Rt register.
780 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
781 : BaseSystemI<L, oops, iops, asm, operands>,
787 // Hint instructions that take both a CRm and a 3-bit immediate.
788 class HintI<string mnemonic>
789 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">,
792 let Inst{20-12} = 0b000110010;
793 let Inst{11-5} = imm;
796 // System instructions taking a single literal operand which encodes into
797 // CRm. op2 differentiates the opcodes.
798 def BarrierAsmOperand : AsmOperandClass {
799 let Name = "Barrier";
800 let ParserMethod = "tryParseBarrierOperand";
802 def barrier_op : Operand<i32> {
803 let PrintMethod = "printBarrierOption";
804 let ParserMatchClass = BarrierAsmOperand;
806 class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
807 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm">,
808 Sched<[WriteBarrier]> {
810 let Inst{20-12} = 0b000110011;
811 let Inst{11-8} = CRm;
815 // MRS/MSR system instructions. These have different operand classes because
816 // a different subset of registers can be accessed through each instruction.
817 def MRSSystemRegisterOperand : AsmOperandClass {
818 let Name = "MRSSystemRegister";
819 let ParserMethod = "tryParseSysReg";
820 let DiagnosticType = "MRS";
822 // concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
823 def mrs_sysreg_op : Operand<i32> {
824 let ParserMatchClass = MRSSystemRegisterOperand;
825 let DecoderMethod = "DecodeMRSSystemRegister";
826 let PrintMethod = "printMRSSystemRegister";
829 def MSRSystemRegisterOperand : AsmOperandClass {
830 let Name = "MSRSystemRegister";
831 let ParserMethod = "tryParseSysReg";
832 let DiagnosticType = "MSR";
834 def msr_sysreg_op : Operand<i32> {
835 let ParserMatchClass = MSRSystemRegisterOperand;
836 let DecoderMethod = "DecodeMSRSystemRegister";
837 let PrintMethod = "printMSRSystemRegister";
840 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
841 "mrs", "\t$Rt, $systemreg"> {
844 let Inst{19-5} = systemreg;
847 // FIXME: Some of these def NZCV, others don't. Best way to model that?
848 // Explicitly modeling each of the system register as a register class
849 // would do it, but feels like overkill at this point.
850 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
851 "msr", "\t$systemreg, $Rt"> {
854 let Inst{19-5} = systemreg;
857 def SystemPStateFieldOperand : AsmOperandClass {
858 let Name = "SystemPStateField";
859 let ParserMethod = "tryParseSysReg";
861 def pstatefield_op : Operand<i32> {
862 let ParserMatchClass = SystemPStateFieldOperand;
863 let PrintMethod = "printSystemPStateField";
868 : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
869 "msr", "\t$pstate_field, $imm">,
873 let Inst{20-19} = 0b00;
874 let Inst{18-16} = pstatefield{5-3};
875 let Inst{15-12} = 0b0100;
876 let Inst{11-8} = imm;
877 let Inst{7-5} = pstatefield{2-0};
879 let DecoderMethod = "DecodeSystemPStateInstruction";
882 // SYS and SYSL generic system instructions.
883 def SysCRAsmOperand : AsmOperandClass {
885 let ParserMethod = "tryParseSysCROperand";
888 def sys_cr_op : Operand<i32> {
889 let PrintMethod = "printSysCROperand";
890 let ParserMatchClass = SysCRAsmOperand;
893 class SystemXtI<bit L, string asm>
894 : RtSystemI<L, (outs),
895 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
896 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
901 let Inst{20-19} = 0b01;
902 let Inst{18-16} = op1;
903 let Inst{15-12} = Cn;
908 class SystemLXtI<bit L, string asm>
909 : RtSystemI<L, (outs),
910 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
911 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
916 let Inst{20-19} = 0b01;
917 let Inst{18-16} = op1;
918 let Inst{15-12} = Cn;
924 // Branch (register) instructions:
932 // otherwise UNDEFINED
933 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
934 string operands, list<dag> pattern>
935 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
936 let Inst{31-25} = 0b1101011;
937 let Inst{24-21} = opc;
938 let Inst{20-16} = 0b11111;
939 let Inst{15-10} = 0b000000;
940 let Inst{4-0} = 0b00000;
943 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
944 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
949 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
950 class SpecialReturn<bits<4> opc, string asm>
951 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
952 let Inst{9-5} = 0b11111;
956 // Conditional branch instruction.
960 // 4-bit immediate. Pretty-printed as <cc>
961 def ccode : Operand<i32> {
962 let PrintMethod = "printCondCode";
963 let ParserMatchClass = CondCode;
965 def inv_ccode : Operand<i32> {
966 let PrintMethod = "printInverseCondCode";
967 let ParserMatchClass = CondCode;
970 // Conditional branch target. 19-bit immediate. The low two bits of the target
971 // offset are implied zero and so are not part of the immediate.
972 def PCRelLabel19Operand : AsmOperandClass {
973 let Name = "PCRelLabel19";
974 let DiagnosticType = "InvalidLabel";
976 def am_brcond : Operand<OtherVT> {
977 let EncoderMethod = "getCondBranchTargetOpValue";
978 let DecoderMethod = "DecodePCRelLabel19";
979 let PrintMethod = "printAlignedLabel";
980 let ParserMatchClass = PCRelLabel19Operand;
983 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
984 "b", ".$cond\t$target", "",
985 [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
988 let isTerminator = 1;
993 let Inst{31-24} = 0b01010100;
994 let Inst{23-5} = target;
996 let Inst{3-0} = cond;
1000 // Compare-and-branch instructions.
1002 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
1003 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
1004 asm, "\t$Rt, $target", "",
1005 [(node regtype:$Rt, bb:$target)]>,
1008 let isTerminator = 1;
1012 let Inst{30-25} = 0b011010;
1014 let Inst{23-5} = target;
1018 multiclass CmpBranch<bit op, string asm, SDNode node> {
1019 def W : BaseCmpBranch<GPR32, op, asm, node> {
1022 def X : BaseCmpBranch<GPR64, op, asm, node> {
1028 // Test-bit-and-branch instructions.
1030 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
1031 // the target offset are implied zero and so are not part of the immediate.
1032 def BranchTarget14Operand : AsmOperandClass {
1033 let Name = "BranchTarget14";
1035 def am_tbrcond : Operand<OtherVT> {
1036 let EncoderMethod = "getTestBranchTargetOpValue";
1037 let PrintMethod = "printAlignedLabel";
1038 let ParserMatchClass = BranchTarget14Operand;
1041 // AsmOperand classes to emit (or not) special diagnostics
1042 def TBZImm0_31Operand : AsmOperandClass {
1043 let Name = "TBZImm0_31";
1044 let PredicateMethod = "isImm0_31";
1045 let RenderMethod = "addImm0_31Operands";
1047 def TBZImm32_63Operand : AsmOperandClass {
1048 let Name = "Imm32_63";
1049 let DiagnosticType = "InvalidImm0_63";
1052 class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
1053 return (((uint32_t)Imm) < 32);
1055 let ParserMatchClass = matcher;
1058 def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
1059 def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;
1061 def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
1062 return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
1064 let ParserMatchClass = TBZImm32_63Operand;
1067 class BaseTestBranch<RegisterClass regtype, Operand immtype,
1068 bit op, string asm, SDNode node>
1069 : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
1070 asm, "\t$Rt, $bit_off, $target", "",
1071 [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
1074 let isTerminator = 1;
1080 let Inst{30-25} = 0b011011;
1082 let Inst{23-19} = bit_off{4-0};
1083 let Inst{18-5} = target;
1086 let DecoderMethod = "DecodeTestAndBranch";
1089 multiclass TestBranch<bit op, string asm, SDNode node> {
1090 def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
1094 def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
1098 // Alias X-reg with 0-31 imm to W-Reg.
1099 def : InstAlias<asm # "\t$Rd, $imm, $target",
1100 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1101 tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
1102 def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
1103 (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
1104 tbz_imm0_31_diag:$imm, bb:$target)>;
1108 // Unconditional branch (immediate) instructions.
1110 def BranchTarget26Operand : AsmOperandClass {
1111 let Name = "BranchTarget26";
1112 let DiagnosticType = "InvalidLabel";
1114 def am_b_target : Operand<OtherVT> {
1115 let EncoderMethod = "getBranchTargetOpValue";
1116 let PrintMethod = "printAlignedLabel";
1117 let ParserMatchClass = BranchTarget26Operand;
1119 def am_bl_target : Operand<i64> {
1120 let EncoderMethod = "getBranchTargetOpValue";
1121 let PrintMethod = "printAlignedLabel";
1122 let ParserMatchClass = BranchTarget26Operand;
1125 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1126 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1129 let Inst{30-26} = 0b00101;
1130 let Inst{25-0} = addr;
1132 let DecoderMethod = "DecodeUnconditionalBranch";
1135 class BranchImm<bit op, string asm, list<dag> pattern>
1136 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1137 class CallImm<bit op, string asm, list<dag> pattern>
1138 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1141 // Basic one-operand data processing instructions.
1144 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1145 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1146 SDPatternOperator node>
1147 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1148 [(set regtype:$Rd, (node regtype:$Rn))]>,
1149 Sched<[WriteI, ReadI]> {
1153 let Inst{30-13} = 0b101101011000000000;
1154 let Inst{12-10} = opc;
1159 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1160 multiclass OneOperandData<bits<3> opc, string asm,
1161 SDPatternOperator node = null_frag> {
1162 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1166 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1171 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1172 : BaseOneOperandData<opc, GPR32, asm, node> {
1176 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1177 : BaseOneOperandData<opc, GPR64, asm, node> {
1182 // Basic two-operand data processing instructions.
1184 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1186 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1187 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1188 Sched<[WriteI, ReadI, ReadI]> {
1193 let Inst{30} = isSub;
1194 let Inst{28-21} = 0b11010000;
1195 let Inst{20-16} = Rm;
1196 let Inst{15-10} = 0;
1201 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1203 : BaseBaseAddSubCarry<isSub, regtype, asm,
1204 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1206 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1208 : BaseBaseAddSubCarry<isSub, regtype, asm,
1209 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1214 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1215 SDNode OpNode, SDNode OpNode_setflags> {
1216 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1220 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1226 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1231 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1238 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1239 SDPatternOperator OpNode>
1240 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1241 asm, "\t$Rd, $Rn, $Rm", "",
1242 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1246 let Inst{30-21} = 0b0011010110;
1247 let Inst{20-16} = Rm;
1248 let Inst{15-14} = 0b00;
1249 let Inst{13-10} = opc;
1254 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1255 SDPatternOperator OpNode>
1256 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1257 let Inst{10} = isSigned;
1260 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1261 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1262 Sched<[WriteID32, ReadID, ReadID]> {
1265 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1266 Sched<[WriteID64, ReadID, ReadID]> {
1271 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1272 SDPatternOperator OpNode = null_frag>
1273 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1274 Sched<[WriteIS, ReadI]> {
1275 let Inst{11-10} = shift_type;
1278 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1279 def Wr : BaseShift<shift_type, GPR32, asm> {
1283 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1287 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1288 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1289 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1291 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1292 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1294 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1295 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1297 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1298 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1301 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1302 : InstAlias<asm#" $dst, $src1, $src2",
1303 (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;
1305 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1306 RegisterClass addtype, string asm,
1308 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1309 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1314 let Inst{30-24} = 0b0011011;
1315 let Inst{23-21} = opc;
1316 let Inst{20-16} = Rm;
1317 let Inst{15} = isSub;
1318 let Inst{14-10} = Ra;
1323 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1324 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1325 [(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
1326 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1330 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1331 [(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
1332 Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
1337 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1338 SDNode AccNode, SDNode ExtNode>
1339 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1340 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1341 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1342 Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
1346 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1347 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1348 asm, "\t$Rd, $Rn, $Rm", "",
1349 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1350 Sched<[WriteIM64, ReadIM, ReadIM]> {
1354 let Inst{31-24} = 0b10011011;
1355 let Inst{23-21} = opc;
1356 let Inst{20-16} = Rm;
1361 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1362 // (i.e. all bits 1) but is ignored by the processor.
1363 let PostEncoderMethod = "fixMulHigh";
1366 class MulAccumWAlias<string asm, Instruction inst>
1367 : InstAlias<asm#" $dst, $src1, $src2",
1368 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1369 class MulAccumXAlias<string asm, Instruction inst>
1370 : InstAlias<asm#" $dst, $src1, $src2",
1371 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1372 class WideMulAccumAlias<string asm, Instruction inst>
1373 : InstAlias<asm#" $dst, $src1, $src2",
1374 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1376 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1377 SDPatternOperator OpNode, string asm>
1378 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1379 asm, "\t$Rd, $Rn, $Rm", "",
1380 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1381 Sched<[WriteISReg, ReadI, ReadISReg]> {
1387 let Inst{30-21} = 0b0011010110;
1388 let Inst{20-16} = Rm;
1389 let Inst{15-13} = 0b010;
1391 let Inst{11-10} = sz;
1394 let Predicates = [HasCRC];
1398 // Address generation.
1401 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1402 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1407 let Inst{31} = page;
1408 let Inst{30-29} = label{1-0};
1409 let Inst{28-24} = 0b10000;
1410 let Inst{23-5} = label{20-2};
1413 let DecoderMethod = "DecodeAdrInstruction";
1420 def movimm32_imm : Operand<i32> {
1421 let ParserMatchClass = Imm0_65535Operand;
1422 let EncoderMethod = "getMoveWideImmOpValue";
1423 let PrintMethod = "printHexImm";
1425 def movimm32_shift : Operand<i32> {
1426 let PrintMethod = "printShifter";
1427 let ParserMatchClass = MovImm32ShifterOperand;
1429 def movimm64_shift : Operand<i32> {
1430 let PrintMethod = "printShifter";
1431 let ParserMatchClass = MovImm64ShifterOperand;
1434 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1435 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1437 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1438 asm, "\t$Rd, $imm$shift", "", []>,
1443 let Inst{30-29} = opc;
1444 let Inst{28-23} = 0b100101;
1445 let Inst{22-21} = shift{5-4};
1446 let Inst{20-5} = imm;
1449 let DecoderMethod = "DecodeMoveImmInstruction";
1452 multiclass MoveImmediate<bits<2> opc, string asm> {
1453 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1457 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1462 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1463 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1465 : I<(outs regtype:$Rd),
1466 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1467 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1468 Sched<[WriteI, ReadI]> {
1472 let Inst{30-29} = opc;
1473 let Inst{28-23} = 0b100101;
1474 let Inst{22-21} = shift{5-4};
1475 let Inst{20-5} = imm;
1478 let DecoderMethod = "DecodeMoveImmInstruction";
1481 multiclass InsertImmediate<bits<2> opc, string asm> {
1482 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1486 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1495 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1496 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1497 string asm, SDPatternOperator OpNode>
1498 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1499 asm, "\t$Rd, $Rn, $imm", "",
1500 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1501 Sched<[WriteI, ReadI]> {
1505 let Inst{30} = isSub;
1506 let Inst{29} = setFlags;
1507 let Inst{28-24} = 0b10001;
1508 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1509 let Inst{21-10} = imm{11-0};
1512 let DecoderMethod = "DecodeBaseAddSubImm";
1515 class BaseAddSubRegPseudo<RegisterClass regtype,
1516 SDPatternOperator OpNode>
1517 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1518 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1519 Sched<[WriteI, ReadI, ReadI]>;
1521 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1522 arith_shifted_reg shifted_regtype, string asm,
1523 SDPatternOperator OpNode>
1524 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1525 asm, "\t$Rd, $Rn, $Rm", "",
1526 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1527 Sched<[WriteISReg, ReadI, ReadISReg]> {
1528 // The operands are in order to match the 'addr' MI operands, so we
1529 // don't need an encoder method and by-name matching. Just use the default
1530 // in-order handling. Since we're using by-order, make sure the names
1536 let Inst{30} = isSub;
1537 let Inst{29} = setFlags;
1538 let Inst{28-24} = 0b01011;
1539 let Inst{23-22} = shift{7-6};
1541 let Inst{20-16} = src2;
1542 let Inst{15-10} = shift{5-0};
1543 let Inst{9-5} = src1;
1544 let Inst{4-0} = dst;
1546 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1549 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1550 RegisterClass src1Regtype, Operand src2Regtype,
1551 string asm, SDPatternOperator OpNode>
1552 : I<(outs dstRegtype:$R1),
1553 (ins src1Regtype:$R2, src2Regtype:$R3),
1554 asm, "\t$R1, $R2, $R3", "",
1555 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1556 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1561 let Inst{30} = isSub;
1562 let Inst{29} = setFlags;
1563 let Inst{28-24} = 0b01011;
1564 let Inst{23-21} = 0b001;
1565 let Inst{20-16} = Rm;
1566 let Inst{15-13} = ext{5-3};
1567 let Inst{12-10} = ext{2-0};
1571 let DecoderMethod = "DecodeAddSubERegInstruction";
1574 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1575 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1576 RegisterClass src1Regtype, RegisterClass src2Regtype,
1577 Operand ext_op, string asm>
1578 : I<(outs dstRegtype:$Rd),
1579 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1580 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1581 Sched<[WriteIEReg, ReadI, ReadIEReg]> {
1586 let Inst{30} = isSub;
1587 let Inst{29} = setFlags;
1588 let Inst{28-24} = 0b01011;
1589 let Inst{23-21} = 0b001;
1590 let Inst{20-16} = Rm;
1591 let Inst{15} = ext{5};
1592 let Inst{12-10} = ext{2-0};
1596 let DecoderMethod = "DecodeAddSubERegInstruction";
1599 // Aliases for register+register add/subtract.
1600 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1601 RegisterClass src1Regtype, RegisterClass src2Regtype,
1603 : InstAlias<asm#" $dst, $src1, $src2",
1604 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1607 multiclass AddSub<bit isSub, string mnemonic,
1608 SDPatternOperator OpNode = null_frag> {
1609 let hasSideEffects = 0 in {
1610 // Add/Subtract immediate
1611 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1615 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1620 // Add/Subtract register - Only used for CodeGen
1621 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1622 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1624 // Add/Subtract shifted register
1625 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1629 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1635 // Add/Subtract extended register
1636 let AddedComplexity = 1, hasSideEffects = 0 in {
1637 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1638 arith_extended_reg32<i32>, mnemonic, OpNode> {
1641 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1642 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1647 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1648 arith_extendlsl64, mnemonic> {
1649 // UXTX and SXTX only.
1650 let Inst{14-13} = 0b11;
1654 // Register/register aliases with no shift when SP is not used.
1655 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1656 GPR32, GPR32, GPR32, 0>;
1657 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1658 GPR64, GPR64, GPR64, 0>;
1660 // Register/register aliases with no shift when either the destination or
1661 // first source register is SP.
1662 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1663 GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
1664 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1665 GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
1666 def : AddSubRegAlias<mnemonic,
1667 !cast<Instruction>(NAME#"Xrx64"),
1668 GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
1669 def : AddSubRegAlias<mnemonic,
1670 !cast<Instruction>(NAME#"Xrx64"),
1671 GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
1674 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
1675 let isCompare = 1, Defs = [NZCV] in {
1676 // Add/Subtract immediate
1677 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1681 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1686 // Add/Subtract register
1687 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1688 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1690 // Add/Subtract shifted register
1691 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1695 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1700 // Add/Subtract extended register
1701 let AddedComplexity = 1 in {
1702 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1703 arith_extended_reg32<i32>, mnemonic, OpNode> {
1706 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1707 arith_extended_reg32<i64>, mnemonic, OpNode> {
1712 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1713 arith_extendlsl64, mnemonic> {
1714 // UXTX and SXTX only.
1715 let Inst{14-13} = 0b11;
1721 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Wri")
1722 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm), 5>;
1723 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Xri")
1724 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
1725 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
1726 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1727 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
1728 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
1729 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
1730 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
1731 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
1732 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
1733 def : InstAlias<cmp#" $src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
1734 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
1736 // Compare shorthands
1737 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1738 WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
1739 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1740 XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
1741 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrx")
1742 WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
1743 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
1744 XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
1746 // Register/register aliases with no shift when SP is not used.
1747 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1748 GPR32, GPR32, GPR32, 0>;
1749 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1750 GPR64, GPR64, GPR64, 0>;
1752 // Register/register aliases with no shift when the first source register
1754 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1755 GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
1756 def : AddSubRegAlias<mnemonic,
1757 !cast<Instruction>(NAME#"Xrx64"),
1758 GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
1764 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1766 def AArch64Extr : SDNode<"AArch64ISD::EXTR", SDTA64EXTR>;
1768 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1770 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1771 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1772 Sched<[WriteExtr, ReadExtrHi]> {
1778 let Inst{30-23} = 0b00100111;
1780 let Inst{20-16} = Rm;
1781 let Inst{15-10} = imm;
1786 multiclass ExtractImm<string asm> {
1787 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1789 (AArch64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1792 // imm<5> must be zero.
1795 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1797 (AArch64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1808 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1809 class BaseBitfieldImm<bits<2> opc,
1810 RegisterClass regtype, Operand imm_type, string asm>
1811 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1812 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1813 Sched<[WriteIS, ReadI]> {
1819 let Inst{30-29} = opc;
1820 let Inst{28-23} = 0b100110;
1821 let Inst{21-16} = immr;
1822 let Inst{15-10} = imms;
1827 multiclass BitfieldImm<bits<2> opc, string asm> {
1828 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1831 // imms<5> and immr<5> must be zero, else ReservedValue().
1835 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1841 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1842 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1843 RegisterClass regtype, Operand imm_type, string asm>
1844 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1846 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1847 Sched<[WriteIS, ReadI]> {
1853 let Inst{30-29} = opc;
1854 let Inst{28-23} = 0b100110;
1855 let Inst{21-16} = immr;
1856 let Inst{15-10} = imms;
1861 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1862 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1865 // imms<5> and immr<5> must be zero, else ReservedValue().
1869 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1879 // Logical (immediate)
1880 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1881 RegisterClass sregtype, Operand imm_type, string asm,
1883 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1884 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1885 Sched<[WriteI, ReadI]> {
1889 let Inst{30-29} = opc;
1890 let Inst{28-23} = 0b100100;
1891 let Inst{22} = imm{12};
1892 let Inst{21-16} = imm{11-6};
1893 let Inst{15-10} = imm{5-0};
1897 let DecoderMethod = "DecodeLogicalImmInstruction";
1900 // Logical (shifted register)
1901 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1902 logical_shifted_reg shifted_regtype, string asm,
1904 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1905 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1906 Sched<[WriteISReg, ReadI, ReadISReg]> {
1907 // The operands are in order to match the 'addr' MI operands, so we
1908 // don't need an encoder method and by-name matching. Just use the default
1909 // in-order handling. Since we're using by-order, make sure the names
1915 let Inst{30-29} = opc;
1916 let Inst{28-24} = 0b01010;
1917 let Inst{23-22} = shift{7-6};
1919 let Inst{20-16} = src2;
1920 let Inst{15-10} = shift{5-0};
1921 let Inst{9-5} = src1;
1922 let Inst{4-0} = dst;
1924 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1927 // Aliases for register+register logical instructions.
1928 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
1929 : InstAlias<asm#" $dst, $src1, $src2",
1930 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
1932 let AddedComplexity = 6 in
1933 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode> {
1934 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
1935 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1936 logical_imm32:$imm))]> {
1938 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1940 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
1941 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1942 logical_imm64:$imm))]> {
1947 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
1948 let isCompare = 1, Defs = [NZCV] in {
1949 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
1950 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
1952 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1954 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
1955 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
1958 } // end Defs = [NZCV]
1961 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
1962 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1963 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1964 Sched<[WriteI, ReadI, ReadI]>;
1966 // Split from LogicalImm as not all instructions have both.
1967 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
1968 SDPatternOperator OpNode> {
1969 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
1970 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
1972 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
1973 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
1974 logical_shifted_reg32:$Rm))]> {
1977 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
1978 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
1979 logical_shifted_reg64:$Rm))]> {
1983 def : LogicalRegAlias<mnemonic,
1984 !cast<Instruction>(NAME#"Wrs"), GPR32>;
1985 def : LogicalRegAlias<mnemonic,
1986 !cast<Instruction>(NAME#"Xrs"), GPR64>;
1989 // Split from LogicalReg to allow setting NZCV Defs
1990 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
1991 SDPatternOperator OpNode = null_frag> {
1992 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1993 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
1994 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
1996 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
1997 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2000 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
2001 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2006 def : LogicalRegAlias<mnemonic,
2007 !cast<Instruction>(NAME#"Wrs"), GPR32>;
2008 def : LogicalRegAlias<mnemonic,
2009 !cast<Instruction>(NAME#"Xrs"), GPR64>;
2013 // Conditionally set flags
2016 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2017 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
2018 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
2019 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
2020 Sched<[WriteI, ReadI]> {
2030 let Inst{29-21} = 0b111010010;
2031 let Inst{20-16} = imm;
2032 let Inst{15-12} = cond;
2033 let Inst{11-10} = 0b10;
2036 let Inst{3-0} = nzcv;
2039 multiclass CondSetFlagsImm<bit op, string asm> {
2040 def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
2043 def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
2048 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
2049 class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
2050 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
2051 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
2052 Sched<[WriteI, ReadI, ReadI]> {
2062 let Inst{29-21} = 0b111010010;
2063 let Inst{20-16} = Rm;
2064 let Inst{15-12} = cond;
2065 let Inst{11-10} = 0b00;
2068 let Inst{3-0} = nzcv;
2071 multiclass CondSetFlagsReg<bit op, string asm> {
2072 def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
2075 def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
2081 // Conditional select
2084 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
2085 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2086 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2088 (AArch64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
2089 Sched<[WriteI, ReadI, ReadI]> {
2098 let Inst{29-21} = 0b011010100;
2099 let Inst{20-16} = Rm;
2100 let Inst{15-12} = cond;
2101 let Inst{11-10} = op2;
2106 multiclass CondSelect<bit op, bits<2> op2, string asm> {
2107 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2110 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2115 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2117 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2118 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2120 (AArch64csel regtype:$Rn, (frag regtype:$Rm),
2121 (i32 imm:$cond), NZCV))]>,
2122 Sched<[WriteI, ReadI, ReadI]> {
2131 let Inst{29-21} = 0b011010100;
2132 let Inst{20-16} = Rm;
2133 let Inst{15-12} = cond;
2134 let Inst{11-10} = op2;
2139 def inv_cond_XFORM : SDNodeXForm<imm, [{
2140 AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
2141 return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), MVT::i32);
2144 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2145 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2148 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2152 def : Pat<(AArch64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2153 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2154 (inv_cond_XFORM imm:$cond))>;
2156 def : Pat<(AArch64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2157 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2158 (inv_cond_XFORM imm:$cond))>;
2162 // Special Mask Value
2164 def maski8_or_more : Operand<i32>,
2165 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2167 def maski16_or_more : Operand<i32>,
2168 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2176 // (unsigned immediate)
2177 // Indexed for 8-bit registers. offset is in range [0,4095].
2178 def am_indexed8 : ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []>;
2179 def am_indexed16 : ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []>;
2180 def am_indexed32 : ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []>;
2181 def am_indexed64 : ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []>;
2182 def am_indexed128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []>;
2184 class UImm12OffsetOperand<int Scale> : AsmOperandClass {
2185 let Name = "UImm12Offset" # Scale;
2186 let RenderMethod = "addUImm12OffsetOperands<" # Scale # ">";
2187 let PredicateMethod = "isUImm12Offset<" # Scale # ">";
2188 let DiagnosticType = "InvalidMemoryIndexed" # Scale;
2191 def UImm12OffsetScale1Operand : UImm12OffsetOperand<1>;
2192 def UImm12OffsetScale2Operand : UImm12OffsetOperand<2>;
2193 def UImm12OffsetScale4Operand : UImm12OffsetOperand<4>;
2194 def UImm12OffsetScale8Operand : UImm12OffsetOperand<8>;
2195 def UImm12OffsetScale16Operand : UImm12OffsetOperand<16>;
2197 class uimm12_scaled<int Scale> : Operand<i64> {
2198 let ParserMatchClass
2199 = !cast<AsmOperandClass>("UImm12OffsetScale" # Scale # "Operand");
2201 = "getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale" # Scale # ">";
2202 let PrintMethod = "printUImm12Offset<" # Scale # ">";
2205 def uimm12s1 : uimm12_scaled<1>;
2206 def uimm12s2 : uimm12_scaled<2>;
2207 def uimm12s4 : uimm12_scaled<4>;
2208 def uimm12s8 : uimm12_scaled<8>;
2209 def uimm12s16 : uimm12_scaled<16>;
2211 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2212 string asm, list<dag> pattern>
2213 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2219 let Inst{31-30} = sz;
2220 let Inst{29-27} = 0b111;
2222 let Inst{25-24} = 0b01;
2223 let Inst{23-22} = opc;
2224 let Inst{21-10} = offset;
2228 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2231 multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2232 Operand indextype, string asm, list<dag> pattern> {
2233 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2234 def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
2235 (ins GPR64sp:$Rn, indextype:$offset),
2239 def : InstAlias<asm # " $Rt, [$Rn]",
2240 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2243 multiclass StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2244 Operand indextype, string asm, list<dag> pattern> {
2245 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2246 def ui : BaseLoadStoreUI<sz, V, opc, (outs),
2247 (ins regtype:$Rt, GPR64sp:$Rn, indextype:$offset),
2251 def : InstAlias<asm # " $Rt, [$Rn]",
2252 (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
2255 def PrefetchOperand : AsmOperandClass {
2256 let Name = "Prefetch";
2257 let ParserMethod = "tryParsePrefetch";
2259 def prfop : Operand<i32> {
2260 let PrintMethod = "printPrefetchOp";
2261 let ParserMatchClass = PrefetchOperand;
2264 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2265 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2266 : BaseLoadStoreUI<sz, V, opc,
2267 (outs), (ins prfop:$Rt, GPR64sp:$Rn, uimm12s8:$offset),
2275 // Load literal address: 19-bit immediate. The low two bits of the target
2276 // offset are implied zero and so are not part of the immediate.
2277 def am_ldrlit : Operand<OtherVT> {
2278 let EncoderMethod = "getLoadLiteralOpValue";
2279 let DecoderMethod = "DecodePCRelLabel19";
2280 let PrintMethod = "printAlignedLabel";
2281 let ParserMatchClass = PCRelLabel19Operand;
2284 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2285 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2286 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2287 asm, "\t$Rt, $label", "", []>,
2291 let Inst{31-30} = opc;
2292 let Inst{29-27} = 0b011;
2294 let Inst{25-24} = 0b00;
2295 let Inst{23-5} = label;
2299 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2300 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2301 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2302 asm, "\t$Rt, $label", "", pat>,
2306 let Inst{31-30} = opc;
2307 let Inst{29-27} = 0b011;
2309 let Inst{25-24} = 0b00;
2310 let Inst{23-5} = label;
2315 // Load/store register offset
2318 def ro_Xindexed8 : ComplexPattern<i64, 4, "SelectAddrModeXRO<8>", []>;
2319 def ro_Xindexed16 : ComplexPattern<i64, 4, "SelectAddrModeXRO<16>", []>;
2320 def ro_Xindexed32 : ComplexPattern<i64, 4, "SelectAddrModeXRO<32>", []>;
2321 def ro_Xindexed64 : ComplexPattern<i64, 4, "SelectAddrModeXRO<64>", []>;
2322 def ro_Xindexed128 : ComplexPattern<i64, 4, "SelectAddrModeXRO<128>", []>;
2324 def ro_Windexed8 : ComplexPattern<i64, 4, "SelectAddrModeWRO<8>", []>;
2325 def ro_Windexed16 : ComplexPattern<i64, 4, "SelectAddrModeWRO<16>", []>;
2326 def ro_Windexed32 : ComplexPattern<i64, 4, "SelectAddrModeWRO<32>", []>;
2327 def ro_Windexed64 : ComplexPattern<i64, 4, "SelectAddrModeWRO<64>", []>;
2328 def ro_Windexed128 : ComplexPattern<i64, 4, "SelectAddrModeWRO<128>", []>;
2330 class MemExtendOperand<string Reg, int Width> : AsmOperandClass {
2331 let Name = "Mem" # Reg # "Extend" # Width;
2332 let PredicateMethod = "isMem" # Reg # "Extend<" # Width # ">";
2333 let RenderMethod = "addMemExtendOperands";
2334 let DiagnosticType = "InvalidMemory" # Reg # "Extend" # Width;
2337 def MemWExtend8Operand : MemExtendOperand<"W", 8> {
2338 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2339 // the trivial shift.
2340 let RenderMethod = "addMemExtend8Operands";
2342 def MemWExtend16Operand : MemExtendOperand<"W", 16>;
2343 def MemWExtend32Operand : MemExtendOperand<"W", 32>;
2344 def MemWExtend64Operand : MemExtendOperand<"W", 64>;
2345 def MemWExtend128Operand : MemExtendOperand<"W", 128>;
2347 def MemXExtend8Operand : MemExtendOperand<"X", 8> {
2348 // The address "[x0, x1, lsl #0]" actually maps to the variant which performs
2349 // the trivial shift.
2350 let RenderMethod = "addMemExtend8Operands";
2352 def MemXExtend16Operand : MemExtendOperand<"X", 16>;
2353 def MemXExtend32Operand : MemExtendOperand<"X", 32>;
2354 def MemXExtend64Operand : MemExtendOperand<"X", 64>;
2355 def MemXExtend128Operand : MemExtendOperand<"X", 128>;
2357 class ro_extend<AsmOperandClass ParserClass, string Reg, int Width>
2359 let ParserMatchClass = ParserClass;
2360 let PrintMethod = "printMemExtend<'" # Reg # "', " # Width # ">";
2361 let DecoderMethod = "DecodeMemExtend";
2362 let EncoderMethod = "getMemExtendOpValue";
2363 let MIOperandInfo = (ops i32imm:$signed, i32imm:$doshift);
2366 def ro_Wextend8 : ro_extend<MemWExtend8Operand, "w", 8>;
2367 def ro_Wextend16 : ro_extend<MemWExtend16Operand, "w", 16>;
2368 def ro_Wextend32 : ro_extend<MemWExtend32Operand, "w", 32>;
2369 def ro_Wextend64 : ro_extend<MemWExtend64Operand, "w", 64>;
2370 def ro_Wextend128 : ro_extend<MemWExtend128Operand, "w", 128>;
2372 def ro_Xextend8 : ro_extend<MemXExtend8Operand, "x", 8>;
2373 def ro_Xextend16 : ro_extend<MemXExtend16Operand, "x", 16>;
2374 def ro_Xextend32 : ro_extend<MemXExtend32Operand, "x", 32>;
2375 def ro_Xextend64 : ro_extend<MemXExtend64Operand, "x", 64>;
2376 def ro_Xextend128 : ro_extend<MemXExtend128Operand, "x", 128>;
2378 class ROAddrMode<ComplexPattern windex, ComplexPattern xindex,
2379 Operand wextend, Operand xextend> {
2380 // CodeGen-level pattern covering the entire addressing mode.
2381 ComplexPattern Wpat = windex;
2382 ComplexPattern Xpat = xindex;
2384 // Asm-level Operand covering the valid "uxtw #3" style syntax.
2385 Operand Wext = wextend;
2386 Operand Xext = xextend;
2389 def ro8 : ROAddrMode<ro_Windexed8, ro_Xindexed8, ro_Wextend8, ro_Xextend8>;
2390 def ro16 : ROAddrMode<ro_Windexed16, ro_Xindexed16, ro_Wextend16, ro_Xextend16>;
2391 def ro32 : ROAddrMode<ro_Windexed32, ro_Xindexed32, ro_Wextend32, ro_Xextend32>;
2392 def ro64 : ROAddrMode<ro_Windexed64, ro_Xindexed64, ro_Wextend64, ro_Xextend64>;
2393 def ro128 : ROAddrMode<ro_Windexed128, ro_Xindexed128, ro_Wextend128,
2396 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2397 string asm, dag ins, dag outs, list<dag> pat>
2398 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2403 let Inst{31-30} = sz;
2404 let Inst{29-27} = 0b111;
2406 let Inst{25-24} = 0b00;
2407 let Inst{23-22} = opc;
2409 let Inst{20-16} = Rm;
2410 let Inst{15} = extend{1}; // sign extend Rm?
2412 let Inst{12} = extend{0}; // do shift?
2413 let Inst{11-10} = 0b10;
2418 class ROInstAlias<string asm, RegisterClass regtype, Instruction INST>
2419 : InstAlias<asm # " $Rt, [$Rn, $Rm]",
2420 (INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2422 multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2423 string asm, ValueType Ty, SDPatternOperator loadop> {
2424 let AddedComplexity = 10 in
2425 def roW : LoadStore8RO<sz, V, opc, regtype, asm,
2427 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2428 [(set (Ty regtype:$Rt),
2429 (loadop (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2430 ro_Wextend8:$extend)))]>,
2431 Sched<[WriteLDIdx, ReadAdrBase]> {
2435 let AddedComplexity = 10 in
2436 def roX : LoadStore8RO<sz, V, opc, regtype, asm,
2438 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2439 [(set (Ty regtype:$Rt),
2440 (loadop (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2441 ro_Xextend8:$extend)))]>,
2442 Sched<[WriteLDIdx, ReadAdrBase]> {
2446 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2449 multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2450 string asm, ValueType Ty, SDPatternOperator storeop> {
2451 let AddedComplexity = 10 in
2452 def roW : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2453 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend8:$extend),
2454 [(storeop (Ty regtype:$Rt),
2455 (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
2456 ro_Wextend8:$extend))]>,
2457 Sched<[WriteSTIdx, ReadAdrBase]> {
2461 let AddedComplexity = 10 in
2462 def roX : LoadStore8RO<sz, V, opc, regtype, asm, (outs),
2463 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend8:$extend),
2464 [(storeop (Ty regtype:$Rt),
2465 (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
2466 ro_Xextend8:$extend))]>,
2467 Sched<[WriteSTIdx, ReadAdrBase]> {
2471 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2474 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2475 string asm, dag ins, dag outs, list<dag> pat>
2476 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2481 let Inst{31-30} = sz;
2482 let Inst{29-27} = 0b111;
2484 let Inst{25-24} = 0b00;
2485 let Inst{23-22} = opc;
2487 let Inst{20-16} = Rm;
2488 let Inst{15} = extend{1}; // sign extend Rm?
2490 let Inst{12} = extend{0}; // do shift?
2491 let Inst{11-10} = 0b10;
2496 multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2497 string asm, ValueType Ty, SDPatternOperator loadop> {
2498 let AddedComplexity = 10 in
2499 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2500 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2501 [(set (Ty regtype:$Rt),
2502 (loadop (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2503 ro_Wextend16:$extend)))]>,
2504 Sched<[WriteLDIdx, ReadAdrBase]> {
2508 let AddedComplexity = 10 in
2509 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2510 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2511 [(set (Ty regtype:$Rt),
2512 (loadop (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2513 ro_Xextend16:$extend)))]>,
2514 Sched<[WriteLDIdx, ReadAdrBase]> {
2518 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2521 multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2522 string asm, ValueType Ty, SDPatternOperator storeop> {
2523 let AddedComplexity = 10 in
2524 def roW : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2525 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend16:$extend),
2526 [(storeop (Ty regtype:$Rt),
2527 (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
2528 ro_Wextend16:$extend))]>,
2529 Sched<[WriteSTIdx, ReadAdrBase]> {
2533 let AddedComplexity = 10 in
2534 def roX : LoadStore16RO<sz, V, opc, regtype, asm, (outs),
2535 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend16:$extend),
2536 [(storeop (Ty regtype:$Rt),
2537 (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
2538 ro_Xextend16:$extend))]>,
2539 Sched<[WriteSTIdx, ReadAdrBase]> {
2543 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2546 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2547 string asm, dag ins, dag outs, list<dag> pat>
2548 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2553 let Inst{31-30} = sz;
2554 let Inst{29-27} = 0b111;
2556 let Inst{25-24} = 0b00;
2557 let Inst{23-22} = opc;
2559 let Inst{20-16} = Rm;
2560 let Inst{15} = extend{1}; // sign extend Rm?
2562 let Inst{12} = extend{0}; // do shift?
2563 let Inst{11-10} = 0b10;
2568 multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2569 string asm, ValueType Ty, SDPatternOperator loadop> {
2570 let AddedComplexity = 10 in
2571 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2572 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2573 [(set (Ty regtype:$Rt),
2574 (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2575 ro_Wextend32:$extend)))]>,
2576 Sched<[WriteLDIdx, ReadAdrBase]> {
2580 let AddedComplexity = 10 in
2581 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2582 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2583 [(set (Ty regtype:$Rt),
2584 (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2585 ro_Xextend32:$extend)))]>,
2586 Sched<[WriteLDIdx, ReadAdrBase]> {
2590 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2593 multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2594 string asm, ValueType Ty, SDPatternOperator storeop> {
2595 let AddedComplexity = 10 in
2596 def roW : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2597 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
2598 [(storeop (Ty regtype:$Rt),
2599 (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
2600 ro_Wextend32:$extend))]>,
2601 Sched<[WriteSTIdx, ReadAdrBase]> {
2605 let AddedComplexity = 10 in
2606 def roX : LoadStore32RO<sz, V, opc, regtype, asm, (outs),
2607 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
2608 [(storeop (Ty regtype:$Rt),
2609 (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
2610 ro_Xextend32:$extend))]>,
2611 Sched<[WriteSTIdx, ReadAdrBase]> {
2615 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2618 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2619 string asm, dag ins, dag outs, list<dag> pat>
2620 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2625 let Inst{31-30} = sz;
2626 let Inst{29-27} = 0b111;
2628 let Inst{25-24} = 0b00;
2629 let Inst{23-22} = opc;
2631 let Inst{20-16} = Rm;
2632 let Inst{15} = extend{1}; // sign extend Rm?
2634 let Inst{12} = extend{0}; // do shift?
2635 let Inst{11-10} = 0b10;
2640 multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2641 string asm, ValueType Ty, SDPatternOperator loadop> {
2642 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2643 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2644 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2645 [(set (Ty regtype:$Rt),
2646 (loadop (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2647 ro_Wextend64:$extend)))]>,
2648 Sched<[WriteLDIdx, ReadAdrBase]> {
2652 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2653 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2654 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2655 [(set (Ty regtype:$Rt),
2656 (loadop (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2657 ro_Xextend64:$extend)))]>,
2658 Sched<[WriteLDIdx, ReadAdrBase]> {
2662 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2665 multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2666 string asm, ValueType Ty, SDPatternOperator storeop> {
2667 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2668 def roW : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2669 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2670 [(storeop (Ty regtype:$Rt),
2671 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2672 ro_Wextend64:$extend))]>,
2673 Sched<[WriteSTIdx, ReadAdrBase]> {
2677 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2678 def roX : LoadStore64RO<sz, V, opc, regtype, asm, (outs),
2679 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2680 [(storeop (Ty regtype:$Rt),
2681 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2682 ro_Xextend64:$extend))]>,
2683 Sched<[WriteSTIdx, ReadAdrBase]> {
2687 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2690 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2691 string asm, dag ins, dag outs, list<dag> pat>
2692 : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
2697 let Inst{31-30} = sz;
2698 let Inst{29-27} = 0b111;
2700 let Inst{25-24} = 0b00;
2701 let Inst{23-22} = opc;
2703 let Inst{20-16} = Rm;
2704 let Inst{15} = extend{1}; // sign extend Rm?
2706 let Inst{12} = extend{0}; // do shift?
2707 let Inst{11-10} = 0b10;
2712 multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2713 string asm, ValueType Ty, SDPatternOperator loadop> {
2714 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2715 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2716 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2717 [(set (Ty regtype:$Rt),
2718 (loadop (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2719 ro_Wextend128:$extend)))]>,
2720 Sched<[WriteLDIdx, ReadAdrBase]> {
2724 let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2725 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs regtype:$Rt),
2726 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2727 [(set (Ty regtype:$Rt),
2728 (loadop (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2729 ro_Xextend128:$extend)))]>,
2730 Sched<[WriteLDIdx, ReadAdrBase]> {
2734 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2737 multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2738 string asm, ValueType Ty, SDPatternOperator storeop> {
2739 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2740 def roW : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2741 (ins regtype:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend128:$extend),
2742 [(storeop (Ty regtype:$Rt),
2743 (ro_Windexed128 GPR64sp:$Rn, GPR32:$Rm,
2744 ro_Wextend128:$extend))]>,
2745 Sched<[WriteSTIdx, ReadAdrBase]> {
2749 let AddedComplexity = 10, mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2750 def roX : LoadStore128RO<sz, V, opc, regtype, asm, (outs),
2751 (ins regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend128:$extend),
2752 [(storeop (Ty regtype:$Rt),
2753 (ro_Xindexed128 GPR64sp:$Rn, GPR64:$Rm,
2754 ro_Xextend128:$extend))]>,
2755 Sched<[WriteSTIdx, ReadAdrBase]> {
2759 def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
2762 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2763 class BasePrefetchRO<bits<2> sz, bit V, bits<2> opc, dag outs, dag ins,
2764 string asm, list<dag> pat>
2765 : I<outs, ins, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat>,
2771 let Inst{31-30} = sz;
2772 let Inst{29-27} = 0b111;
2774 let Inst{25-24} = 0b00;
2775 let Inst{23-22} = opc;
2777 let Inst{20-16} = Rm;
2778 let Inst{15} = extend{1}; // sign extend Rm?
2780 let Inst{12} = extend{0}; // do shift?
2781 let Inst{11-10} = 0b10;
2786 multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
2787 def roW : BasePrefetchRO<sz, V, opc, (outs),
2788 (ins prfop:$Rt, GPR64sp:$Rn, GPR32:$Rm, ro_Wextend64:$extend),
2789 asm, [(AArch64Prefetch imm:$Rt,
2790 (ro_Windexed64 GPR64sp:$Rn, GPR32:$Rm,
2791 ro_Wextend64:$extend))]> {
2795 def roX : BasePrefetchRO<sz, V, opc, (outs),
2796 (ins prfop:$Rt, GPR64sp:$Rn, GPR64:$Rm, ro_Xextend64:$extend),
2797 asm, [(AArch64Prefetch imm:$Rt,
2798 (ro_Xindexed64 GPR64sp:$Rn, GPR64:$Rm,
2799 ro_Xextend64:$extend))]> {
2803 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
2804 (!cast<Instruction>(NAME # "roX") prfop:$Rt,
2805 GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
2809 // Load/store unscaled immediate
2812 def am_unscaled8 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2813 def am_unscaled16 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2814 def am_unscaled32 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2815 def am_unscaled64 : ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2816 def am_unscaled128 :ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2818 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2819 string asm, list<dag> pattern>
2820 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
2824 let Inst{31-30} = sz;
2825 let Inst{29-27} = 0b111;
2827 let Inst{25-24} = 0b00;
2828 let Inst{23-22} = opc;
2830 let Inst{20-12} = offset;
2831 let Inst{11-10} = 0b00;
2835 let DecoderMethod = "DecodeSignedLdStInstruction";
2838 multiclass LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2839 string asm, list<dag> pattern> {
2840 let AddedComplexity = 1 in // try this before LoadUI
2841 def i : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2842 (ins GPR64sp:$Rn, simm9:$offset), asm, pattern>,
2845 def : InstAlias<asm # " $Rt, [$Rn]",
2846 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2849 multiclass StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2850 string asm, list<dag> pattern> {
2851 let AddedComplexity = 1 in // try this before StoreUI
2852 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2853 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2857 def : InstAlias<asm # " $Rt, [$Rn]",
2858 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2861 multiclass PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm,
2863 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2864 def i : BaseLoadStoreUnscale<sz, V, opc, (outs),
2865 (ins prfop:$Rt, GPR64sp:$Rn, simm9:$offset),
2869 def : InstAlias<asm # " $Rt, [$Rn]",
2870 (!cast<Instruction>(NAME # "i") prfop:$Rt, GPR64sp:$Rn, 0)>;
2874 // Load/store unscaled immediate, unprivileged
2877 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2878 dag oops, dag iops, string asm>
2879 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", []> {
2883 let Inst{31-30} = sz;
2884 let Inst{29-27} = 0b111;
2886 let Inst{25-24} = 0b00;
2887 let Inst{23-22} = opc;
2889 let Inst{20-12} = offset;
2890 let Inst{11-10} = 0b10;
2894 let DecoderMethod = "DecodeSignedLdStInstruction";
2897 multiclass LoadUnprivileged<bits<2> sz, bit V, bits<2> opc,
2898 RegisterClass regtype, string asm> {
2899 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in
2900 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs regtype:$Rt),
2901 (ins GPR64sp:$Rn, simm9:$offset), asm>,
2904 def : InstAlias<asm # " $Rt, [$Rn]",
2905 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2908 multiclass StoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2909 RegisterClass regtype, string asm> {
2910 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2911 def i : BaseLoadStoreUnprivileged<sz, V, opc, (outs),
2912 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2916 def : InstAlias<asm # " $Rt, [$Rn]",
2917 (!cast<Instruction>(NAME # "i") regtype:$Rt, GPR64sp:$Rn, 0)>;
2921 // Load/store pre-indexed
2924 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2925 string asm, string cstr, list<dag> pat>
2926 : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]!", cstr, pat> {
2930 let Inst{31-30} = sz;
2931 let Inst{29-27} = 0b111;
2933 let Inst{25-24} = 0;
2934 let Inst{23-22} = opc;
2936 let Inst{20-12} = offset;
2937 let Inst{11-10} = 0b11;
2941 let DecoderMethod = "DecodeSignedLdStInstruction";
2944 let hasSideEffects = 0 in {
2945 let mayStore = 0, mayLoad = 1 in
2946 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2948 : BaseLoadStorePreIdx<sz, V, opc,
2949 (outs GPR64sp:$wback, regtype:$Rt),
2950 (ins GPR64sp:$Rn, simm9:$offset), asm,
2951 "$Rn = $wback", []>,
2952 Sched<[WriteLD, WriteAdr]>;
2954 let mayStore = 1, mayLoad = 0 in
2955 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2956 string asm, SDPatternOperator storeop, ValueType Ty>
2957 : BaseLoadStorePreIdx<sz, V, opc,
2958 (outs GPR64sp:$wback),
2959 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
2960 asm, "$Rn = $wback",
2961 [(set GPR64sp:$wback,
2962 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
2963 Sched<[WriteAdr, WriteST]>;
2964 } // hasSideEffects = 0
2967 // Load/store post-indexed
2970 // (pre-index) load/stores.
2971 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2972 string asm, string cstr, list<dag> pat>
2973 : I<oops, iops, asm, "\t$Rt, [$Rn], $offset", cstr, pat> {
2977 let Inst{31-30} = sz;
2978 let Inst{29-27} = 0b111;
2980 let Inst{25-24} = 0b00;
2981 let Inst{23-22} = opc;
2983 let Inst{20-12} = offset;
2984 let Inst{11-10} = 0b01;
2988 let DecoderMethod = "DecodeSignedLdStInstruction";
2991 let hasSideEffects = 0 in {
2992 let mayStore = 0, mayLoad = 1 in
2993 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2995 : BaseLoadStorePostIdx<sz, V, opc,
2996 (outs GPR64sp:$wback, regtype:$Rt),
2997 (ins GPR64sp:$Rn, simm9:$offset),
2998 asm, "$Rn = $wback", []>,
2999 Sched<[WriteLD, WriteI]>;
3001 let mayStore = 1, mayLoad = 0 in
3002 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
3003 string asm, SDPatternOperator storeop, ValueType Ty>
3004 : BaseLoadStorePostIdx<sz, V, opc,
3005 (outs GPR64sp:$wback),
3006 (ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
3007 asm, "$Rn = $wback",
3008 [(set GPR64sp:$wback,
3009 (storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
3010 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
3011 } // hasSideEffects = 0
3018 // (indexed, offset)
3020 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
3022 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3027 let Inst{31-30} = opc;
3028 let Inst{29-27} = 0b101;
3030 let Inst{25-23} = 0b010;
3032 let Inst{21-15} = offset;
3033 let Inst{14-10} = Rt2;
3037 let DecoderMethod = "DecodePairLdStInstruction";
3040 multiclass LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
3041 Operand indextype, string asm> {
3042 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3043 def i : BaseLoadStorePairOffset<opc, V, 1,
3044 (outs regtype:$Rt, regtype:$Rt2),
3045 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3046 Sched<[WriteLD, WriteLDHi]>;
3048 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3049 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3054 multiclass StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
3055 Operand indextype, string asm> {
3056 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
3057 def i : BaseLoadStorePairOffset<opc, V, 0, (outs),
3058 (ins regtype:$Rt, regtype:$Rt2,
3059 GPR64sp:$Rn, indextype:$offset),
3063 def : InstAlias<asm # " $Rt, $Rt2, [$Rn]",
3064 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3069 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3071 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]!", "$Rn = $wback", []> {
3076 let Inst{31-30} = opc;
3077 let Inst{29-27} = 0b101;
3079 let Inst{25-23} = 0b011;
3081 let Inst{21-15} = offset;
3082 let Inst{14-10} = Rt2;
3086 let DecoderMethod = "DecodePairLdStInstruction";
3089 let hasSideEffects = 0 in {
3090 let mayStore = 0, mayLoad = 1 in
3091 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3092 Operand indextype, string asm>
3093 : BaseLoadStorePairPreIdx<opc, V, 1,
3094 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3095 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3096 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3098 let mayStore = 1, mayLoad = 0 in
3099 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
3100 Operand indextype, string asm>
3101 : BaseLoadStorePairPreIdx<opc, V, 0, (outs GPR64sp:$wback),
3102 (ins regtype:$Rt, regtype:$Rt2,
3103 GPR64sp:$Rn, indextype:$offset),
3105 Sched<[WriteAdr, WriteSTP]>;
3106 } // hasSideEffects = 0
3110 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
3112 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn], $offset", "$Rn = $wback", []> {
3117 let Inst{31-30} = opc;
3118 let Inst{29-27} = 0b101;
3120 let Inst{25-23} = 0b001;
3122 let Inst{21-15} = offset;
3123 let Inst{14-10} = Rt2;
3127 let DecoderMethod = "DecodePairLdStInstruction";
3130 let hasSideEffects = 0 in {
3131 let mayStore = 0, mayLoad = 1 in
3132 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3133 Operand idxtype, string asm>
3134 : BaseLoadStorePairPostIdx<opc, V, 1,
3135 (outs GPR64sp:$wback, regtype:$Rt, regtype:$Rt2),
3136 (ins GPR64sp:$Rn, idxtype:$offset), asm>,
3137 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
3139 let mayStore = 1, mayLoad = 0 in
3140 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
3141 Operand idxtype, string asm>
3142 : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
3143 (ins GPR64sp:$wback, regtype:$Rt, regtype:$Rt2,
3144 GPR64sp:$Rn, idxtype:$offset),
3146 Sched<[WriteAdr, WriteSTP]>;
3147 } // hasSideEffects = 0
3151 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
3153 : I<oops, iops, asm, "\t$Rt, $Rt2, [$Rn, $offset]", "", []> {
3158 let Inst{31-30} = opc;
3159 let Inst{29-27} = 0b101;
3161 let Inst{25-23} = 0b000;
3163 let Inst{21-15} = offset;
3164 let Inst{14-10} = Rt2;
3168 let DecoderMethod = "DecodePairLdStInstruction";
3171 multiclass LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3172 Operand indextype, string asm> {
3173 let hasSideEffects = 0, mayStore = 0, mayLoad = 1 in
3174 def i : BaseLoadStorePairNoAlloc<opc, V, 1,
3175 (outs regtype:$Rt, regtype:$Rt2),
3176 (ins GPR64sp:$Rn, indextype:$offset), asm>,
3177 Sched<[WriteLD, WriteLDHi]>;
3180 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3181 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3185 multiclass StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3186 Operand indextype, string asm> {
3187 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in
3188 def i : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3189 (ins regtype:$Rt, regtype:$Rt2,
3190 GPR64sp:$Rn, indextype:$offset),
3194 def : InstAlias<asm # "\t$Rt, $Rt2, [$Rn]",
3195 (!cast<Instruction>(NAME # "i") regtype:$Rt, regtype:$Rt2,
3200 // Load/store exclusive
3203 // True exclusive operations write to and/or read from the system's exclusive
3204 // monitors, which as far as a compiler is concerned can be modelled as a
3205 // random shared memory address. Hence LoadExclusive mayStore.
3207 // Since these instructions have the undefined register bits set to 1 in
3208 // their canonical form, we need a post encoder method to set those bits
3209 // to 1 when encoding these instructions. We do this using the
3210 // fixLoadStoreExclusive function. This function has template parameters:
3212 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3214 // hasRs indicates that the instruction uses the Rs field, so we won't set
3215 // it to 1 (and the same for Rt2). We don't need template parameters for
3216 // the other register fields since Rt and Rn are always used.
3218 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3219 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3220 dag oops, dag iops, string asm, string operands>
3221 : I<oops, iops, asm, operands, "", []> {
3222 let Inst{31-30} = sz;
3223 let Inst{29-24} = 0b001000;
3229 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3232 // Neither Rs nor Rt2 operands.
3233 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3234 dag oops, dag iops, string asm, string operands>
3235 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3241 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3244 // Simple load acquires don't set the exclusive monitor
3245 let mayLoad = 1, mayStore = 0 in
3246 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3247 RegisterClass regtype, string asm>
3248 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3249 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3252 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3253 RegisterClass regtype, string asm>
3254 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3255 (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]">,
3258 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3259 RegisterClass regtype, string asm>
3260 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3261 (outs regtype:$Rt, regtype:$Rt2),
3262 (ins GPR64sp0:$Rn), asm,
3263 "\t$Rt, $Rt2, [$Rn]">,
3264 Sched<[WriteLD, WriteLDHi]> {
3268 let Inst{14-10} = Rt2;
3272 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3275 // Simple store release operations do not check the exclusive monitor.
3276 let mayLoad = 0, mayStore = 1 in
3277 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3278 RegisterClass regtype, string asm>
3279 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3280 (ins regtype:$Rt, GPR64sp0:$Rn),
3281 asm, "\t$Rt, [$Rn]">,
3284 let mayLoad = 1, mayStore = 1 in
3285 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3286 RegisterClass regtype, string asm>
3287 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3288 (ins regtype:$Rt, GPR64sp0:$Rn),
3289 asm, "\t$Ws, $Rt, [$Rn]">,
3294 let Inst{20-16} = Ws;
3298 let Constraints = "@earlyclobber $Ws";
3299 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3302 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3303 RegisterClass regtype, string asm>
3304 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3306 (ins regtype:$Rt, regtype:$Rt2, GPR64sp0:$Rn),
3307 asm, "\t$Ws, $Rt, $Rt2, [$Rn]">,
3313 let Inst{20-16} = Ws;
3314 let Inst{14-10} = Rt2;
3318 let Constraints = "@earlyclobber $Ws";
3322 // Exception generation
3325 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3326 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3327 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3330 let Inst{31-24} = 0b11010100;
3331 let Inst{23-21} = op1;
3332 let Inst{20-5} = imm;
3333 let Inst{4-2} = 0b000;
3337 let Predicates = [HasFPARMv8] in {
3340 // Floating point to integer conversion
3343 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3344 RegisterClass srcType, RegisterClass dstType,
3345 string asm, list<dag> pattern>
3346 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3347 asm, "\t$Rd, $Rn", "", pattern>,
3348 Sched<[WriteFCvt]> {
3351 let Inst{30-29} = 0b00;
3352 let Inst{28-24} = 0b11110;
3353 let Inst{23-22} = type;
3355 let Inst{20-19} = rmode;
3356 let Inst{18-16} = opcode;
3357 let Inst{15-10} = 0;
3362 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3363 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3364 RegisterClass srcType, RegisterClass dstType,
3365 Operand immType, string asm, list<dag> pattern>
3366 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3367 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3368 Sched<[WriteFCvt]> {
3372 let Inst{30-29} = 0b00;
3373 let Inst{28-24} = 0b11110;
3374 let Inst{23-22} = type;
3376 let Inst{20-19} = rmode;
3377 let Inst{18-16} = opcode;
3378 let Inst{15-10} = scale;
3383 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3384 SDPatternOperator OpN> {
3385 // Unscaled single-precision to 32-bit
3386 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3387 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3388 let Inst{31} = 0; // 32-bit GPR flag
3391 // Unscaled single-precision to 64-bit
3392 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3393 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3394 let Inst{31} = 1; // 64-bit GPR flag
3397 // Unscaled double-precision to 32-bit
3398 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3399 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3400 let Inst{31} = 0; // 32-bit GPR flag
3403 // Unscaled double-precision to 64-bit
3404 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3405 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3406 let Inst{31} = 1; // 64-bit GPR flag
3410 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3411 SDPatternOperator OpN> {
3412 // Scaled single-precision to 32-bit
3413 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3414 fixedpoint_f32_i32, asm,
3415 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3416 fixedpoint_f32_i32:$scale)))]> {
3417 let Inst{31} = 0; // 32-bit GPR flag
3421 // Scaled single-precision to 64-bit
3422 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3423 fixedpoint_f32_i64, asm,
3424 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3425 fixedpoint_f32_i64:$scale)))]> {
3426 let Inst{31} = 1; // 64-bit GPR flag
3429 // Scaled double-precision to 32-bit
3430 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3431 fixedpoint_f64_i32, asm,
3432 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3433 fixedpoint_f64_i32:$scale)))]> {
3434 let Inst{31} = 0; // 32-bit GPR flag
3438 // Scaled double-precision to 64-bit
3439 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3440 fixedpoint_f64_i64, asm,
3441 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3442 fixedpoint_f64_i64:$scale)))]> {
3443 let Inst{31} = 1; // 64-bit GPR flag
3448 // Integer to floating point conversion
3451 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3452 class BaseIntegerToFP<bit isUnsigned,
3453 RegisterClass srcType, RegisterClass dstType,
3454 Operand immType, string asm, list<dag> pattern>
3455 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3456 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3457 Sched<[WriteFCvt]> {
3461 let Inst{30-23} = 0b00111100;
3462 let Inst{21-17} = 0b00001;
3463 let Inst{16} = isUnsigned;
3464 let Inst{15-10} = scale;
3469 class BaseIntegerToFPUnscaled<bit isUnsigned,
3470 RegisterClass srcType, RegisterClass dstType,
3471 ValueType dvt, string asm, SDNode node>
3472 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3473 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3474 Sched<[WriteFCvt]> {
3478 let Inst{30-23} = 0b00111100;
3479 let Inst{21-17} = 0b10001;
3480 let Inst{16} = isUnsigned;
3481 let Inst{15-10} = 0b000000;
3486 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3488 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3489 let Inst{31} = 0; // 32-bit GPR flag
3490 let Inst{22} = 0; // 32-bit FPR flag
3493 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3494 let Inst{31} = 0; // 32-bit GPR flag
3495 let Inst{22} = 1; // 64-bit FPR flag
3498 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3499 let Inst{31} = 1; // 64-bit GPR flag
3500 let Inst{22} = 0; // 32-bit FPR flag
3503 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3504 let Inst{31} = 1; // 64-bit GPR flag
3505 let Inst{22} = 1; // 64-bit FPR flag
3509 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3511 (fdiv (node GPR32:$Rn),
3512 fixedpoint_f32_i32:$scale))]> {
3513 let Inst{31} = 0; // 32-bit GPR flag
3514 let Inst{22} = 0; // 32-bit FPR flag
3518 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3520 (fdiv (node GPR32:$Rn),
3521 fixedpoint_f64_i32:$scale))]> {
3522 let Inst{31} = 0; // 32-bit GPR flag
3523 let Inst{22} = 1; // 64-bit FPR flag
3527 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3529 (fdiv (node GPR64:$Rn),
3530 fixedpoint_f32_i64:$scale))]> {
3531 let Inst{31} = 1; // 64-bit GPR flag
3532 let Inst{22} = 0; // 32-bit FPR flag
3535 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3537 (fdiv (node GPR64:$Rn),
3538 fixedpoint_f64_i64:$scale))]> {
3539 let Inst{31} = 1; // 64-bit GPR flag
3540 let Inst{22} = 1; // 64-bit FPR flag
3545 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3548 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3549 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3550 RegisterClass srcType, RegisterClass dstType,
3552 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3553 // We use COPY_TO_REGCLASS for these bitconvert operations.
3554 // copyPhysReg() expands the resultant COPY instructions after
3555 // regalloc is done. This gives greater freedom for the allocator
3556 // and related passes (coalescing, copy propagation, et. al.) to
3557 // be more effective.
3558 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3559 Sched<[WriteFCopy]> {
3562 let Inst{30-23} = 0b00111100;
3564 let Inst{20-19} = rmode;
3565 let Inst{18-16} = opcode;
3566 let Inst{15-10} = 0b000000;
3571 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3572 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3573 RegisterClass srcType, RegisterOperand dstType, string asm,
3575 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3576 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3577 Sched<[WriteFCopy]> {
3580 let Inst{30-23} = 0b00111101;
3582 let Inst{20-19} = rmode;
3583 let Inst{18-16} = opcode;
3584 let Inst{15-10} = 0b000000;
3588 let DecoderMethod = "DecodeFMOVLaneInstruction";
3591 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3592 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3593 RegisterOperand srcType, RegisterClass dstType, string asm,
3595 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3596 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3597 Sched<[WriteFCopy]> {
3600 let Inst{30-23} = 0b00111101;
3602 let Inst{20-19} = rmode;
3603 let Inst{18-16} = opcode;
3604 let Inst{15-10} = 0b000000;
3608 let DecoderMethod = "DecodeFMOVLaneInstruction";
3613 multiclass UnscaledConversion<string asm> {
3614 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3615 let Inst{31} = 0; // 32-bit GPR flag
3616 let Inst{22} = 0; // 32-bit FPR flag
3619 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3620 let Inst{31} = 1; // 64-bit GPR flag
3621 let Inst{22} = 1; // 64-bit FPR flag
3624 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3625 let Inst{31} = 0; // 32-bit GPR flag
3626 let Inst{22} = 0; // 32-bit FPR flag
3629 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3630 let Inst{31} = 1; // 64-bit GPR flag
3631 let Inst{22} = 1; // 64-bit FPR flag
3634 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3640 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3648 // Floating point conversion
3651 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3652 RegisterClass srcType, string asm, list<dag> pattern>
3653 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3654 Sched<[WriteFCvt]> {
3657 let Inst{31-24} = 0b00011110;
3658 let Inst{23-22} = type;
3659 let Inst{21-17} = 0b10001;
3660 let Inst{16-15} = opcode;
3661 let Inst{14-10} = 0b10000;
3666 multiclass FPConversion<string asm> {
3667 // Double-precision to Half-precision
3668 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3669 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3671 // Double-precision to Single-precision
3672 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3673 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3675 // Half-precision to Double-precision
3676 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3677 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3679 // Half-precision to Single-precision
3680 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3681 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3683 // Single-precision to Double-precision
3684 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3685 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3687 // Single-precision to Half-precision
3688 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3689 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3693 // Single operand floating point data processing
3696 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3697 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3698 ValueType vt, string asm, SDPatternOperator node>
3699 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3700 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3704 let Inst{31-23} = 0b000111100;
3705 let Inst{21-19} = 0b100;
3706 let Inst{18-15} = opcode;
3707 let Inst{14-10} = 0b10000;
3712 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3713 SDPatternOperator node = null_frag> {
3714 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3715 let Inst{22} = 0; // 32-bit size flag
3718 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3719 let Inst{22} = 1; // 64-bit size flag
3724 // Two operand floating point data processing
3727 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3728 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3729 string asm, list<dag> pat>
3730 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3731 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3736 let Inst{31-23} = 0b000111100;
3738 let Inst{20-16} = Rm;
3739 let Inst{15-12} = opcode;
3740 let Inst{11-10} = 0b10;
3745 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3746 SDPatternOperator node = null_frag> {
3747 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3748 [(set (f32 FPR32:$Rd),
3749 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3750 let Inst{22} = 0; // 32-bit size flag
3753 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3754 [(set (f64 FPR64:$Rd),
3755 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3756 let Inst{22} = 1; // 64-bit size flag
3760 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3761 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3762 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3763 let Inst{22} = 0; // 32-bit size flag
3766 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3767 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3768 let Inst{22} = 1; // 64-bit size flag
3774 // Three operand floating point data processing
3777 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3778 RegisterClass regtype, string asm, list<dag> pat>
3779 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3780 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3781 Sched<[WriteFMul]> {
3786 let Inst{31-23} = 0b000111110;
3787 let Inst{21} = isNegated;
3788 let Inst{20-16} = Rm;
3789 let Inst{15} = isSub;
3790 let Inst{14-10} = Ra;
3795 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3796 SDPatternOperator node> {
3797 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3799 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3800 let Inst{22} = 0; // 32-bit size flag
3803 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3805 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3806 let Inst{22} = 1; // 64-bit size flag
3811 // Floating point data comparisons
3814 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3815 class BaseOneOperandFPComparison<bit signalAllNans,
3816 RegisterClass regtype, string asm,
3818 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3819 Sched<[WriteFCmp]> {
3821 let Inst{31-23} = 0b000111100;
3824 let Inst{15-10} = 0b001000;
3826 let Inst{4} = signalAllNans;
3827 let Inst{3-0} = 0b1000;
3829 // Rm should be 0b00000 canonically, but we need to accept any value.
3830 let PostEncoderMethod = "fixOneOperandFPComparison";
3833 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3834 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3835 string asm, list<dag> pat>
3836 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3837 Sched<[WriteFCmp]> {
3840 let Inst{31-23} = 0b000111100;
3842 let Inst{20-16} = Rm;
3843 let Inst{15-10} = 0b001000;
3845 let Inst{4} = signalAllNans;
3846 let Inst{3-0} = 0b0000;
3849 multiclass FPComparison<bit signalAllNans, string asm,
3850 SDPatternOperator OpNode = null_frag> {
3851 let Defs = [NZCV] in {
3852 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3853 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3857 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3858 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3862 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3863 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3867 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3868 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3875 // Floating point conditional comparisons
3878 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3879 class BaseFPCondComparison<bit signalAllNans,
3880 RegisterClass regtype, string asm>
3881 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3882 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3883 Sched<[WriteFCmp]> {
3889 let Inst{31-23} = 0b000111100;
3891 let Inst{20-16} = Rm;
3892 let Inst{15-12} = cond;
3893 let Inst{11-10} = 0b01;
3895 let Inst{4} = signalAllNans;
3896 let Inst{3-0} = nzcv;
3899 multiclass FPCondComparison<bit signalAllNans, string asm> {
3900 let Defs = [NZCV], Uses = [NZCV] in {
3901 def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
3905 def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
3908 } // Defs = [NZCV], Uses = [NZCV]
3912 // Floating point conditional select
3915 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
3916 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3917 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3919 (AArch64csel (vt regtype:$Rn), regtype:$Rm,
3920 (i32 imm:$cond), NZCV))]>,
3927 let Inst{31-23} = 0b000111100;
3929 let Inst{20-16} = Rm;
3930 let Inst{15-12} = cond;
3931 let Inst{11-10} = 0b11;
3936 multiclass FPCondSelect<string asm> {
3937 let Uses = [NZCV] in {
3938 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
3942 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
3949 // Floating move immediate
3952 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
3953 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
3954 [(set regtype:$Rd, fpimmtype:$imm)]>,
3955 Sched<[WriteFImm]> {
3958 let Inst{31-23} = 0b000111100;
3960 let Inst{20-13} = imm;
3961 let Inst{12-5} = 0b10000000;
3965 multiclass FPMoveImmediate<string asm> {
3966 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
3970 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
3974 } // end of 'let Predicates = [HasFPARMv8]'
3976 //----------------------------------------------------------------------------
3978 //----------------------------------------------------------------------------
3980 let Predicates = [HasNEON] in {
3982 //----------------------------------------------------------------------------
3983 // AdvSIMD three register vector instructions
3984 //----------------------------------------------------------------------------
3986 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3987 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
3988 RegisterOperand regtype, string asm, string kind,
3990 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
3991 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
3992 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4000 let Inst{28-24} = 0b01110;
4001 let Inst{23-22} = size;
4003 let Inst{20-16} = Rm;
4004 let Inst{15-11} = opcode;
4010 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4011 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4012 RegisterOperand regtype, string asm, string kind,
4014 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4015 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4016 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4024 let Inst{28-24} = 0b01110;
4025 let Inst{23-22} = size;
4027 let Inst{20-16} = Rm;
4028 let Inst{15-11} = opcode;
4034 // All operand sizes distinguished in the encoding.
4035 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
4036 SDPatternOperator OpNode> {
4037 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4039 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4040 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4042 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4043 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4045 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4046 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4048 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4049 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4051 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4052 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4054 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4055 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
4057 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4060 // As above, but D sized elements unsupported.
4061 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
4062 SDPatternOperator OpNode> {
4063 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4065 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4066 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4068 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4069 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4071 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4072 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4074 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4075 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4077 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4078 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4080 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4083 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
4084 SDPatternOperator OpNode> {
4085 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
4087 [(set (v8i8 V64:$dst),
4088 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4089 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
4091 [(set (v16i8 V128:$dst),
4092 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4093 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
4095 [(set (v4i16 V64:$dst),
4096 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4097 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
4099 [(set (v8i16 V128:$dst),
4100 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4101 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
4103 [(set (v2i32 V64:$dst),
4104 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4105 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
4107 [(set (v4i32 V128:$dst),
4108 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4111 // As above, but only B sized elements supported.
4112 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
4113 SDPatternOperator OpNode> {
4114 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
4116 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4117 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
4119 [(set (v16i8 V128:$Rd),
4120 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4123 // As above, but only S and D sized floating point elements supported.
4124 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
4125 string asm, SDPatternOperator OpNode> {
4126 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4128 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4129 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4131 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4132 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4134 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4137 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4139 SDPatternOperator OpNode> {
4140 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4142 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4143 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4145 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4146 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4148 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4151 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4152 string asm, SDPatternOperator OpNode> {
4153 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4155 [(set (v2f32 V64:$dst),
4156 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4157 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4159 [(set (v4f32 V128:$dst),
4160 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4161 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4163 [(set (v2f64 V128:$dst),
4164 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4167 // As above, but D and B sized elements unsupported.
4168 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4169 SDPatternOperator OpNode> {
4170 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4172 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4173 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4175 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4176 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4178 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4179 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4181 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4184 // Logical three vector ops share opcode bits, and only use B sized elements.
4185 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4186 SDPatternOperator OpNode = null_frag> {
4187 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4189 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4190 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4192 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4194 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4195 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4196 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4197 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4198 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4199 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4201 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4202 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4203 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4204 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4205 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4206 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4209 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4210 string asm, SDPatternOperator OpNode> {
4211 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4213 [(set (v8i8 V64:$dst),
4214 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4215 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4217 [(set (v16i8 V128:$dst),
4218 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4219 (v16i8 V128:$Rm)))]>;
4221 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4223 (!cast<Instruction>(NAME#"v8i8")
4224 V64:$LHS, V64:$MHS, V64:$RHS)>;
4225 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4227 (!cast<Instruction>(NAME#"v8i8")
4228 V64:$LHS, V64:$MHS, V64:$RHS)>;
4229 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4231 (!cast<Instruction>(NAME#"v8i8")
4232 V64:$LHS, V64:$MHS, V64:$RHS)>;
4234 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4235 (v8i16 V128:$RHS))),
4236 (!cast<Instruction>(NAME#"v16i8")
4237 V128:$LHS, V128:$MHS, V128:$RHS)>;
4238 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4239 (v4i32 V128:$RHS))),
4240 (!cast<Instruction>(NAME#"v16i8")
4241 V128:$LHS, V128:$MHS, V128:$RHS)>;
4242 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4243 (v2i64 V128:$RHS))),
4244 (!cast<Instruction>(NAME#"v16i8")
4245 V128:$LHS, V128:$MHS, V128:$RHS)>;
4249 //----------------------------------------------------------------------------
4250 // AdvSIMD two register vector instructions.
4251 //----------------------------------------------------------------------------
4253 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4254 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4255 RegisterOperand regtype, string asm, string dstkind,
4256 string srckind, list<dag> pattern>
4257 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4258 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4259 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4266 let Inst{28-24} = 0b01110;
4267 let Inst{23-22} = size;
4268 let Inst{21-17} = 0b10000;
4269 let Inst{16-12} = opcode;
4270 let Inst{11-10} = 0b10;
4275 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4276 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4277 RegisterOperand regtype, string asm, string dstkind,
4278 string srckind, list<dag> pattern>
4279 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4280 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4281 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4288 let Inst{28-24} = 0b01110;
4289 let Inst{23-22} = size;
4290 let Inst{21-17} = 0b10000;
4291 let Inst{16-12} = opcode;
4292 let Inst{11-10} = 0b10;
4297 // Supports B, H, and S element sizes.
4298 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4299 SDPatternOperator OpNode> {
4300 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4302 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4303 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4304 asm, ".16b", ".16b",
4305 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4306 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4308 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4309 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4311 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4312 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4314 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4315 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4317 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4320 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4321 RegisterOperand regtype, string asm, string dstkind,
4322 string srckind, string amount>
4323 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4324 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4325 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4331 let Inst{29-24} = 0b101110;
4332 let Inst{23-22} = size;
4333 let Inst{21-10} = 0b100001001110;
4338 multiclass SIMDVectorLShiftLongBySizeBHS {
4339 let neverHasSideEffects = 1 in {
4340 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4341 "shll", ".8h", ".8b", "8">;
4342 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4343 "shll2", ".8h", ".16b", "8">;
4344 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4345 "shll", ".4s", ".4h", "16">;
4346 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4347 "shll2", ".4s", ".8h", "16">;
4348 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4349 "shll", ".2d", ".2s", "32">;
4350 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4351 "shll2", ".2d", ".4s", "32">;
4355 // Supports all element sizes.
4356 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4357 SDPatternOperator OpNode> {
4358 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4360 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4361 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4363 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4364 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4366 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4367 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4369 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4370 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4372 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4373 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4375 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4378 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4379 SDPatternOperator OpNode> {
4380 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4382 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4384 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4386 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4387 (v16i8 V128:$Rn)))]>;
4388 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4390 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4391 (v4i16 V64:$Rn)))]>;
4392 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4394 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4395 (v8i16 V128:$Rn)))]>;
4396 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4398 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4399 (v2i32 V64:$Rn)))]>;
4400 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4402 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4403 (v4i32 V128:$Rn)))]>;
4406 // Supports all element sizes, except 1xD.
4407 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4408 SDPatternOperator OpNode> {
4409 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4411 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4412 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4413 asm, ".16b", ".16b",
4414 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4415 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4417 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4418 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4420 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4421 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4423 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4424 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4426 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4427 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4429 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4432 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4433 SDPatternOperator OpNode = null_frag> {
4434 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4436 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4437 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4438 asm, ".16b", ".16b",
4439 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4440 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4442 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4443 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4445 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4446 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4448 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4449 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4451 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4452 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4454 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4458 // Supports only B element sizes.
4459 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4460 SDPatternOperator OpNode> {
4461 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4463 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4464 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4465 asm, ".16b", ".16b",
4466 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4470 // Supports only B and H element sizes.
4471 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4472 SDPatternOperator OpNode> {
4473 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4475 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4476 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4477 asm, ".16b", ".16b",
4478 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4479 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4481 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4482 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4484 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4487 // Supports only S and D element sizes, uses high bit of the size field
4488 // as an extra opcode bit.
4489 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4490 SDPatternOperator OpNode> {
4491 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4493 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4494 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4496 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4497 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4499 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4502 // Supports only S element size.
4503 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4504 SDPatternOperator OpNode> {
4505 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4507 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4508 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4510 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4514 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4515 SDPatternOperator OpNode> {
4516 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4518 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4519 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4521 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4522 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4524 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4527 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4528 SDPatternOperator OpNode> {
4529 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4531 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4532 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4534 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4535 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4537 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4541 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4542 RegisterOperand inreg, RegisterOperand outreg,
4543 string asm, string outkind, string inkind,
4545 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4546 "{\t$Rd" # outkind # ", $Rn" # inkind #
4547 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4554 let Inst{28-24} = 0b01110;
4555 let Inst{23-22} = size;
4556 let Inst{21-17} = 0b10000;
4557 let Inst{16-12} = opcode;
4558 let Inst{11-10} = 0b10;
4563 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4564 RegisterOperand inreg, RegisterOperand outreg,
4565 string asm, string outkind, string inkind,
4567 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4568 "{\t$Rd" # outkind # ", $Rn" # inkind #
4569 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4576 let Inst{28-24} = 0b01110;
4577 let Inst{23-22} = size;
4578 let Inst{21-17} = 0b10000;
4579 let Inst{16-12} = opcode;
4580 let Inst{11-10} = 0b10;
4585 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4586 SDPatternOperator OpNode> {
4587 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4589 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4590 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4591 asm#"2", ".16b", ".8h", []>;
4592 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4594 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4595 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4596 asm#"2", ".8h", ".4s", []>;
4597 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4599 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4600 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4601 asm#"2", ".4s", ".2d", []>;
4603 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4604 (!cast<Instruction>(NAME # "v16i8")
4605 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4606 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4607 (!cast<Instruction>(NAME # "v8i16")
4608 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4609 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4610 (!cast<Instruction>(NAME # "v4i32")
4611 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4614 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4615 RegisterOperand regtype,
4616 string asm, string kind, string zero,
4617 ValueType dty, ValueType sty, SDNode OpNode>
4618 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4619 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4620 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4621 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4628 let Inst{28-24} = 0b01110;
4629 let Inst{23-22} = size;
4630 let Inst{21-17} = 0b10000;
4631 let Inst{16-12} = opcode;
4632 let Inst{11-10} = 0b10;
4637 // Comparisons support all element sizes, except 1xD.
4638 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4640 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4642 v8i8, v8i8, OpNode>;
4643 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4645 v16i8, v16i8, OpNode>;
4646 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4648 v4i16, v4i16, OpNode>;
4649 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4651 v8i16, v8i16, OpNode>;
4652 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4654 v2i32, v2i32, OpNode>;
4655 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4657 v4i32, v4i32, OpNode>;
4658 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4660 v2i64, v2i64, OpNode>;
4663 // FP Comparisons support only S and D element sizes.
4664 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4665 string asm, SDNode OpNode> {
4667 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4669 v2i32, v2f32, OpNode>;
4670 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4672 v4i32, v4f32, OpNode>;
4673 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4675 v2i64, v2f64, OpNode>;
4677 def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
4678 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4679 def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
4680 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4681 def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
4682 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4683 def : InstAlias<asm # ".2s $Vd, $Vn, #0",
4684 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4685 def : InstAlias<asm # ".4s $Vd, $Vn, #0",
4686 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4687 def : InstAlias<asm # ".2d $Vd, $Vn, #0",
4688 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4691 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4692 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4693 RegisterOperand outtype, RegisterOperand intype,
4694 string asm, string VdTy, string VnTy,
4696 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4697 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4704 let Inst{28-24} = 0b01110;
4705 let Inst{23-22} = size;
4706 let Inst{21-17} = 0b10000;
4707 let Inst{16-12} = opcode;
4708 let Inst{11-10} = 0b10;
4713 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4714 RegisterOperand outtype, RegisterOperand intype,
4715 string asm, string VdTy, string VnTy,
4717 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4718 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4725 let Inst{28-24} = 0b01110;
4726 let Inst{23-22} = size;
4727 let Inst{21-17} = 0b10000;
4728 let Inst{16-12} = opcode;
4729 let Inst{11-10} = 0b10;
4734 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4735 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4736 asm, ".4s", ".4h", []>;
4737 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4738 asm#"2", ".4s", ".8h", []>;
4739 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4740 asm, ".2d", ".2s", []>;
4741 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4742 asm#"2", ".2d", ".4s", []>;
4745 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4746 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4747 asm, ".4h", ".4s", []>;
4748 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4749 asm#"2", ".8h", ".4s", []>;
4750 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4751 asm, ".2s", ".2d", []>;
4752 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4753 asm#"2", ".4s", ".2d", []>;
4756 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4758 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4760 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4761 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4762 asm#"2", ".4s", ".2d", []>;
4764 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4765 (!cast<Instruction>(NAME # "v4f32")
4766 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4769 //----------------------------------------------------------------------------
4770 // AdvSIMD three register different-size vector instructions.
4771 //----------------------------------------------------------------------------
4773 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4774 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4775 RegisterOperand outtype, RegisterOperand intype1,
4776 RegisterOperand intype2, string asm,
4777 string outkind, string inkind1, string inkind2,
4779 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4780 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4781 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4787 let Inst{30} = size{0};
4789 let Inst{28-24} = 0b01110;
4790 let Inst{23-22} = size{2-1};
4792 let Inst{20-16} = Rm;
4793 let Inst{15-12} = opcode;
4794 let Inst{11-10} = 0b00;
4799 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4800 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4801 RegisterOperand outtype, RegisterOperand intype1,
4802 RegisterOperand intype2, string asm,
4803 string outkind, string inkind1, string inkind2,
4805 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4806 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4807 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4813 let Inst{30} = size{0};
4815 let Inst{28-24} = 0b01110;
4816 let Inst{23-22} = size{2-1};
4818 let Inst{20-16} = Rm;
4819 let Inst{15-12} = opcode;
4820 let Inst{11-10} = 0b00;
4825 // FIXME: TableGen doesn't know how to deal with expanded types that also
4826 // change the element count (in this case, placing the results in
4827 // the high elements of the result register rather than the low
4828 // elements). Until that's fixed, we can't code-gen those.
4829 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4831 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4833 asm, ".8b", ".8h", ".8h",
4834 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4835 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4837 asm#"2", ".16b", ".8h", ".8h",
4839 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4841 asm, ".4h", ".4s", ".4s",
4842 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4843 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4845 asm#"2", ".8h", ".4s", ".4s",
4847 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4849 asm, ".2s", ".2d", ".2d",
4850 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4851 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4853 asm#"2", ".4s", ".2d", ".2d",
4857 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4858 // a version attached to an instruction.
4859 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4861 (!cast<Instruction>(NAME # "v8i16_v16i8")
4862 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4863 V128:$Rn, V128:$Rm)>;
4864 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4866 (!cast<Instruction>(NAME # "v4i32_v8i16")
4867 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4868 V128:$Rn, V128:$Rm)>;
4869 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4871 (!cast<Instruction>(NAME # "v2i64_v4i32")
4872 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4873 V128:$Rn, V128:$Rm)>;
4876 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
4878 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4880 asm, ".8h", ".8b", ".8b",
4881 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4882 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4884 asm#"2", ".8h", ".16b", ".16b", []>;
4885 let Predicates = [HasCrypto] in {
4886 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
4888 asm, ".1q", ".1d", ".1d", []>;
4889 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
4891 asm#"2", ".1q", ".2d", ".2d", []>;
4894 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4895 (v8i8 (extract_high_v16i8 V128:$Rm)))),
4896 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4899 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
4900 SDPatternOperator OpNode> {
4901 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4903 asm, ".4s", ".4h", ".4h",
4904 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4905 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4907 asm#"2", ".4s", ".8h", ".8h",
4908 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4909 (extract_high_v8i16 V128:$Rm)))]>;
4910 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4912 asm, ".2d", ".2s", ".2s",
4913 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4914 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4916 asm#"2", ".2d", ".4s", ".4s",
4917 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4918 (extract_high_v4i32 V128:$Rm)))]>;
4921 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
4922 SDPatternOperator OpNode = null_frag> {
4923 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4925 asm, ".8h", ".8b", ".8b",
4926 [(set (v8i16 V128:$Rd),
4927 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4928 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4930 asm#"2", ".8h", ".16b", ".16b",
4931 [(set (v8i16 V128:$Rd),
4932 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4933 (extract_high_v16i8 V128:$Rm)))))]>;
4934 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4936 asm, ".4s", ".4h", ".4h",
4937 [(set (v4i32 V128:$Rd),
4938 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
4939 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4941 asm#"2", ".4s", ".8h", ".8h",
4942 [(set (v4i32 V128:$Rd),
4943 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4944 (extract_high_v8i16 V128:$Rm)))))]>;
4945 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4947 asm, ".2d", ".2s", ".2s",
4948 [(set (v2i64 V128:$Rd),
4949 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
4950 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4952 asm#"2", ".2d", ".4s", ".4s",
4953 [(set (v2i64 V128:$Rd),
4954 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4955 (extract_high_v4i32 V128:$Rm)))))]>;
4958 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
4960 SDPatternOperator OpNode> {
4961 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
4963 asm, ".8h", ".8b", ".8b",
4964 [(set (v8i16 V128:$dst),
4965 (add (v8i16 V128:$Rd),
4966 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
4967 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4969 asm#"2", ".8h", ".16b", ".16b",
4970 [(set (v8i16 V128:$dst),
4971 (add (v8i16 V128:$Rd),
4972 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4973 (extract_high_v16i8 V128:$Rm))))))]>;
4974 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4976 asm, ".4s", ".4h", ".4h",
4977 [(set (v4i32 V128:$dst),
4978 (add (v4i32 V128:$Rd),
4979 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
4980 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4982 asm#"2", ".4s", ".8h", ".8h",
4983 [(set (v4i32 V128:$dst),
4984 (add (v4i32 V128:$Rd),
4985 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4986 (extract_high_v8i16 V128:$Rm))))))]>;
4987 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4989 asm, ".2d", ".2s", ".2s",
4990 [(set (v2i64 V128:$dst),
4991 (add (v2i64 V128:$Rd),
4992 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
4993 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4995 asm#"2", ".2d", ".4s", ".4s",
4996 [(set (v2i64 V128:$dst),
4997 (add (v2i64 V128:$Rd),
4998 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4999 (extract_high_v4i32 V128:$Rm))))))]>;
5002 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
5003 SDPatternOperator OpNode = null_frag> {
5004 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5006 asm, ".8h", ".8b", ".8b",
5007 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5008 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5010 asm#"2", ".8h", ".16b", ".16b",
5011 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5012 (extract_high_v16i8 V128:$Rm)))]>;
5013 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5015 asm, ".4s", ".4h", ".4h",
5016 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5017 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5019 asm#"2", ".4s", ".8h", ".8h",
5020 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5021 (extract_high_v8i16 V128:$Rm)))]>;
5022 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5024 asm, ".2d", ".2s", ".2s",
5025 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5026 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5028 asm#"2", ".2d", ".4s", ".4s",
5029 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5030 (extract_high_v4i32 V128:$Rm)))]>;
5033 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
5035 SDPatternOperator OpNode> {
5036 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
5038 asm, ".8h", ".8b", ".8b",
5039 [(set (v8i16 V128:$dst),
5040 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5041 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
5043 asm#"2", ".8h", ".16b", ".16b",
5044 [(set (v8i16 V128:$dst),
5045 (OpNode (v8i16 V128:$Rd),
5046 (extract_high_v16i8 V128:$Rn),
5047 (extract_high_v16i8 V128:$Rm)))]>;
5048 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5050 asm, ".4s", ".4h", ".4h",
5051 [(set (v4i32 V128:$dst),
5052 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5053 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5055 asm#"2", ".4s", ".8h", ".8h",
5056 [(set (v4i32 V128:$dst),
5057 (OpNode (v4i32 V128:$Rd),
5058 (extract_high_v8i16 V128:$Rn),
5059 (extract_high_v8i16 V128:$Rm)))]>;
5060 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5062 asm, ".2d", ".2s", ".2s",
5063 [(set (v2i64 V128:$dst),
5064 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5065 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5067 asm#"2", ".2d", ".4s", ".4s",
5068 [(set (v2i64 V128:$dst),
5069 (OpNode (v2i64 V128:$Rd),
5070 (extract_high_v4i32 V128:$Rn),
5071 (extract_high_v4i32 V128:$Rm)))]>;
5074 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
5075 SDPatternOperator Accum> {
5076 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
5078 asm, ".4s", ".4h", ".4h",
5079 [(set (v4i32 V128:$dst),
5080 (Accum (v4i32 V128:$Rd),
5081 (v4i32 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
5082 (v4i16 V64:$Rm)))))]>;
5083 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
5085 asm#"2", ".4s", ".8h", ".8h",
5086 [(set (v4i32 V128:$dst),
5087 (Accum (v4i32 V128:$Rd),
5088 (v4i32 (int_aarch64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
5089 (extract_high_v8i16 V128:$Rm)))))]>;
5090 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
5092 asm, ".2d", ".2s", ".2s",
5093 [(set (v2i64 V128:$dst),
5094 (Accum (v2i64 V128:$Rd),
5095 (v2i64 (int_aarch64_neon_sqdmull (v2i32 V64:$Rn),
5096 (v2i32 V64:$Rm)))))]>;
5097 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
5099 asm#"2", ".2d", ".4s", ".4s",
5100 [(set (v2i64 V128:$dst),
5101 (Accum (v2i64 V128:$Rd),
5102 (v2i64 (int_aarch64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
5103 (extract_high_v4i32 V128:$Rm)))))]>;
5106 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
5107 SDPatternOperator OpNode> {
5108 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
5110 asm, ".8h", ".8h", ".8b",
5111 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5112 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
5114 asm#"2", ".8h", ".8h", ".16b",
5115 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5116 (extract_high_v16i8 V128:$Rm)))]>;
5117 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
5119 asm, ".4s", ".4s", ".4h",
5120 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5121 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
5123 asm#"2", ".4s", ".4s", ".8h",
5124 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5125 (extract_high_v8i16 V128:$Rm)))]>;
5126 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5128 asm, ".2d", ".2d", ".2s",
5129 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5130 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5132 asm#"2", ".2d", ".2d", ".4s",
5133 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5134 (extract_high_v4i32 V128:$Rm)))]>;
5137 //----------------------------------------------------------------------------
5138 // AdvSIMD bitwise extract from vector
5139 //----------------------------------------------------------------------------
5141 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5142 string asm, string kind>
5143 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5144 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5145 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5146 [(set (vty regtype:$Rd),
5147 (AArch64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5154 let Inst{30} = size;
5155 let Inst{29-21} = 0b101110000;
5156 let Inst{20-16} = Rm;
5158 let Inst{14-11} = imm;
5165 multiclass SIMDBitwiseExtract<string asm> {
5166 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5169 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5172 //----------------------------------------------------------------------------
5173 // AdvSIMD zip vector
5174 //----------------------------------------------------------------------------
5176 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5177 string asm, string kind, SDNode OpNode, ValueType valty>
5178 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5179 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5180 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5181 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5187 let Inst{30} = size{0};
5188 let Inst{29-24} = 0b001110;
5189 let Inst{23-22} = size{2-1};
5191 let Inst{20-16} = Rm;
5193 let Inst{14-12} = opc;
5194 let Inst{11-10} = 0b10;
5199 multiclass SIMDZipVector<bits<3>opc, string asm,
5201 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5202 asm, ".8b", OpNode, v8i8>;
5203 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5204 asm, ".16b", OpNode, v16i8>;
5205 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5206 asm, ".4h", OpNode, v4i16>;
5207 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5208 asm, ".8h", OpNode, v8i16>;
5209 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5210 asm, ".2s", OpNode, v2i32>;
5211 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5212 asm, ".4s", OpNode, v4i32>;
5213 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5214 asm, ".2d", OpNode, v2i64>;
5216 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5217 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5218 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5219 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5220 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5221 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5224 //----------------------------------------------------------------------------
5225 // AdvSIMD three register scalar instructions
5226 //----------------------------------------------------------------------------
5228 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5229 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5230 RegisterClass regtype, string asm,
5232 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5233 "\t$Rd, $Rn, $Rm", "", pattern>,
5238 let Inst{31-30} = 0b01;
5240 let Inst{28-24} = 0b11110;
5241 let Inst{23-22} = size;
5243 let Inst{20-16} = Rm;
5244 let Inst{15-11} = opcode;
5250 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5251 SDPatternOperator OpNode> {
5252 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5253 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5256 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5257 SDPatternOperator OpNode> {
5258 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5259 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5260 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5261 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5262 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5264 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5265 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5266 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5267 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5270 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5271 SDPatternOperator OpNode> {
5272 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5273 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5274 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5277 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5278 SDPatternOperator OpNode = null_frag> {
5279 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5280 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5281 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5282 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5283 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5286 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5287 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5290 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5291 SDPatternOperator OpNode = null_frag> {
5292 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5293 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5294 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5295 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5296 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5299 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5300 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5303 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5304 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5305 : I<oops, iops, asm,
5306 "\t$Rd, $Rn, $Rm", cstr, pat>,
5311 let Inst{31-30} = 0b01;
5313 let Inst{28-24} = 0b11110;
5314 let Inst{23-22} = size;
5316 let Inst{20-16} = Rm;
5317 let Inst{15-11} = opcode;
5323 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5324 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5325 SDPatternOperator OpNode = null_frag> {
5326 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5328 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5329 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5331 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5332 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5335 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5336 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5337 SDPatternOperator OpNode = null_frag> {
5338 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5340 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5341 asm, "$Rd = $dst", []>;
5342 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5344 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5346 [(set (i64 FPR64:$dst),
5347 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5350 //----------------------------------------------------------------------------
5351 // AdvSIMD two register scalar instructions
5352 //----------------------------------------------------------------------------
5354 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5355 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5356 RegisterClass regtype, RegisterClass regtype2,
5357 string asm, list<dag> pat>
5358 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5359 "\t$Rd, $Rn", "", pat>,
5363 let Inst{31-30} = 0b01;
5365 let Inst{28-24} = 0b11110;
5366 let Inst{23-22} = size;
5367 let Inst{21-17} = 0b10000;
5368 let Inst{16-12} = opcode;
5369 let Inst{11-10} = 0b10;
5374 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5375 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5376 RegisterClass regtype, RegisterClass regtype2,
5377 string asm, list<dag> pat>
5378 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5379 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5383 let Inst{31-30} = 0b01;
5385 let Inst{28-24} = 0b11110;
5386 let Inst{23-22} = size;
5387 let Inst{21-17} = 0b10000;
5388 let Inst{16-12} = opcode;
5389 let Inst{11-10} = 0b10;
5395 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5396 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5397 RegisterClass regtype, string asm, string zero>
5398 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5399 "\t$Rd, $Rn, #" # zero, "", []>,
5403 let Inst{31-30} = 0b01;
5405 let Inst{28-24} = 0b11110;
5406 let Inst{23-22} = size;
5407 let Inst{21-17} = 0b10000;
5408 let Inst{16-12} = opcode;
5409 let Inst{11-10} = 0b10;
5414 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5415 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5416 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5420 let Inst{31-17} = 0b011111100110000;
5421 let Inst{16-12} = opcode;
5422 let Inst{11-10} = 0b10;
5427 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5428 SDPatternOperator OpNode> {
5429 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5431 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5432 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5435 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
5436 SDPatternOperator OpNode> {
5437 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5438 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5440 def : InstAlias<asm # " $Rd, $Rn, #0",
5441 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5442 def : InstAlias<asm # " $Rd, $Rn, #0",
5443 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5445 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5446 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5449 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5450 SDPatternOperator OpNode = null_frag> {
5451 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5452 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5454 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5455 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5458 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {
5459 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5460 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5463 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5464 SDPatternOperator OpNode> {
5465 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5466 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5467 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5468 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5471 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5472 SDPatternOperator OpNode = null_frag> {
5473 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5474 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5475 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5476 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5477 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5478 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5479 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5482 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5483 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5486 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5488 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5489 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5490 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5491 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5492 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5493 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5494 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5497 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5498 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5503 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5504 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5505 SDPatternOperator OpNode = null_frag> {
5506 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5507 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5508 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5509 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5512 //----------------------------------------------------------------------------
5513 // AdvSIMD scalar pairwise instructions
5514 //----------------------------------------------------------------------------
5516 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5517 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5518 RegisterOperand regtype, RegisterOperand vectype,
5519 string asm, string kind>
5520 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5521 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5525 let Inst{31-30} = 0b01;
5527 let Inst{28-24} = 0b11110;
5528 let Inst{23-22} = size;
5529 let Inst{21-17} = 0b11000;
5530 let Inst{16-12} = opcode;
5531 let Inst{11-10} = 0b10;
5536 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5537 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5541 multiclass SIMDPairwiseScalarSD<bit U, bit S, bits<5> opc, string asm> {
5542 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5544 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5548 //----------------------------------------------------------------------------
5549 // AdvSIMD across lanes instructions
5550 //----------------------------------------------------------------------------
5552 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5553 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5554 RegisterClass regtype, RegisterOperand vectype,
5555 string asm, string kind, list<dag> pattern>
5556 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5557 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5564 let Inst{28-24} = 0b01110;
5565 let Inst{23-22} = size;
5566 let Inst{21-17} = 0b11000;
5567 let Inst{16-12} = opcode;
5568 let Inst{11-10} = 0b10;
5573 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5575 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5577 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5579 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5581 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5583 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5587 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5588 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5590 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5592 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5594 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5596 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5600 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5602 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5604 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5607 //----------------------------------------------------------------------------
5608 // AdvSIMD INS/DUP instructions
5609 //----------------------------------------------------------------------------
5611 // FIXME: There has got to be a better way to factor these. ugh.
5613 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5614 string operands, string constraints, list<dag> pattern>
5615 : I<outs, ins, asm, operands, constraints, pattern>,
5622 let Inst{28-21} = 0b01110000;
5629 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5630 RegisterOperand vecreg, RegisterClass regtype>
5631 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5632 "{\t$Rd" # size # ", $Rn" #
5633 "|" # size # "\t$Rd, $Rn}", "",
5634 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
5635 let Inst{20-16} = imm5;
5636 let Inst{14-11} = 0b0001;
5639 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5640 ValueType vectype, ValueType insreg,
5641 RegisterOperand vecreg, Operand idxtype,
5642 ValueType elttype, SDNode OpNode>
5643 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5644 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5645 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5646 [(set (vectype vecreg:$Rd),
5647 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5648 let Inst{14-11} = 0b0000;
5651 class SIMDDup64FromElement
5652 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5653 VectorIndexD, i64, AArch64duplane64> {
5656 let Inst{19-16} = 0b1000;
5659 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5660 RegisterOperand vecreg>
5661 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5662 VectorIndexS, i64, AArch64duplane32> {
5664 let Inst{20-19} = idx;
5665 let Inst{18-16} = 0b100;
5668 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5669 RegisterOperand vecreg>
5670 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5671 VectorIndexH, i64, AArch64duplane16> {
5673 let Inst{20-18} = idx;
5674 let Inst{17-16} = 0b10;
5677 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5678 RegisterOperand vecreg>
5679 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5680 VectorIndexB, i64, AArch64duplane8> {
5682 let Inst{20-17} = idx;
5686 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5687 Operand idxtype, string asm, list<dag> pattern>
5688 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5689 "{\t$Rd, $Rn" # size # "$idx" #
5690 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5691 let Inst{14-11} = imm4;
5694 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5696 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5697 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5699 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5700 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5702 class SIMDMovAlias<string asm, string size, Instruction inst,
5703 RegisterClass regtype, Operand idxtype>
5704 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5705 "|" # size # "\t$dst, $src$idx}",
5706 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5709 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5711 let Inst{20-17} = idx;
5714 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5716 let Inst{20-17} = idx;
5719 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5721 let Inst{20-18} = idx;
5722 let Inst{17-16} = 0b10;
5724 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5726 let Inst{20-18} = idx;
5727 let Inst{17-16} = 0b10;
5729 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5731 let Inst{20-19} = idx;
5732 let Inst{18-16} = 0b100;
5737 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5739 let Inst{20-17} = idx;
5742 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5744 let Inst{20-18} = idx;
5745 let Inst{17-16} = 0b10;
5747 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5749 let Inst{20-19} = idx;
5750 let Inst{18-16} = 0b100;
5752 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5755 let Inst{19-16} = 0b1000;
5757 def : SIMDMovAlias<"mov", ".s",
5758 !cast<Instruction>(NAME#"vi32"),
5759 GPR32, VectorIndexS>;
5760 def : SIMDMovAlias<"mov", ".d",
5761 !cast<Instruction>(NAME#"vi64"),
5762 GPR64, VectorIndexD>;
5765 class SIMDInsFromMain<string size, ValueType vectype,
5766 RegisterClass regtype, Operand idxtype>
5767 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5768 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5769 "{\t$Rd" # size # "$idx, $Rn" #
5770 "|" # size # "\t$Rd$idx, $Rn}",
5773 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5774 let Inst{14-11} = 0b0011;
5777 class SIMDInsFromElement<string size, ValueType vectype,
5778 ValueType elttype, Operand idxtype>
5779 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5780 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5781 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5782 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5787 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5790 class SIMDInsMainMovAlias<string size, Instruction inst,
5791 RegisterClass regtype, Operand idxtype>
5792 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5793 "|" # size #"\t$dst$idx, $src}",
5794 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5795 class SIMDInsElementMovAlias<string size, Instruction inst,
5797 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5798 # "|" # size #" $dst$idx, $src$idx2}",
5799 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5802 multiclass SIMDIns {
5803 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5805 let Inst{20-17} = idx;
5808 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5810 let Inst{20-18} = idx;
5811 let Inst{17-16} = 0b10;
5813 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5815 let Inst{20-19} = idx;
5816 let Inst{18-16} = 0b100;
5818 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5821 let Inst{19-16} = 0b1000;
5824 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5827 let Inst{20-17} = idx;
5829 let Inst{14-11} = idx2;
5831 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5834 let Inst{20-18} = idx;
5835 let Inst{17-16} = 0b10;
5836 let Inst{14-12} = idx2;
5839 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
5842 let Inst{20-19} = idx;
5843 let Inst{18-16} = 0b100;
5844 let Inst{14-13} = idx2;
5845 let Inst{12-11} = 0;
5847 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
5851 let Inst{19-16} = 0b1000;
5852 let Inst{14} = idx2;
5853 let Inst{13-11} = 0;
5856 // For all forms of the INS instruction, the "mov" mnemonic is the
5857 // preferred alias. Why they didn't just call the instruction "mov" in
5858 // the first place is a very good question indeed...
5859 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
5860 GPR32, VectorIndexB>;
5861 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
5862 GPR32, VectorIndexH>;
5863 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
5864 GPR32, VectorIndexS>;
5865 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
5866 GPR64, VectorIndexD>;
5868 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
5870 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
5872 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
5874 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
5878 //----------------------------------------------------------------------------
5880 //----------------------------------------------------------------------------
5882 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5883 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5884 RegisterOperand listtype, string asm, string kind>
5885 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
5886 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
5893 let Inst{29-21} = 0b001110000;
5894 let Inst{20-16} = Vm;
5896 let Inst{14-13} = len;
5898 let Inst{11-10} = 0b00;
5903 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5904 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5905 RegisterOperand listtype, string asm, string kind>
5906 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
5907 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
5914 let Inst{29-21} = 0b001110000;
5915 let Inst{20-16} = Vm;
5917 let Inst{14-13} = len;
5919 let Inst{11-10} = 0b00;
5924 class SIMDTableLookupAlias<string asm, Instruction inst,
5925 RegisterOperand vectype, RegisterOperand listtype>
5926 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
5927 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
5929 multiclass SIMDTableLookup<bit op, string asm> {
5930 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
5932 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
5934 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
5936 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
5938 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
5940 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
5942 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
5944 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
5947 def : SIMDTableLookupAlias<asm # ".8b",
5948 !cast<Instruction>(NAME#"v8i8One"),
5949 V64, VecListOne128>;
5950 def : SIMDTableLookupAlias<asm # ".8b",
5951 !cast<Instruction>(NAME#"v8i8Two"),
5952 V64, VecListTwo128>;
5953 def : SIMDTableLookupAlias<asm # ".8b",
5954 !cast<Instruction>(NAME#"v8i8Three"),
5955 V64, VecListThree128>;
5956 def : SIMDTableLookupAlias<asm # ".8b",
5957 !cast<Instruction>(NAME#"v8i8Four"),
5958 V64, VecListFour128>;
5959 def : SIMDTableLookupAlias<asm # ".16b",
5960 !cast<Instruction>(NAME#"v16i8One"),
5961 V128, VecListOne128>;
5962 def : SIMDTableLookupAlias<asm # ".16b",
5963 !cast<Instruction>(NAME#"v16i8Two"),
5964 V128, VecListTwo128>;
5965 def : SIMDTableLookupAlias<asm # ".16b",
5966 !cast<Instruction>(NAME#"v16i8Three"),
5967 V128, VecListThree128>;
5968 def : SIMDTableLookupAlias<asm # ".16b",
5969 !cast<Instruction>(NAME#"v16i8Four"),
5970 V128, VecListFour128>;
5973 multiclass SIMDTableLookupTied<bit op, string asm> {
5974 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
5976 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
5978 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
5980 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
5982 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
5984 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
5986 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
5988 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
5991 def : SIMDTableLookupAlias<asm # ".8b",
5992 !cast<Instruction>(NAME#"v8i8One"),
5993 V64, VecListOne128>;
5994 def : SIMDTableLookupAlias<asm # ".8b",
5995 !cast<Instruction>(NAME#"v8i8Two"),
5996 V64, VecListTwo128>;
5997 def : SIMDTableLookupAlias<asm # ".8b",
5998 !cast<Instruction>(NAME#"v8i8Three"),
5999 V64, VecListThree128>;
6000 def : SIMDTableLookupAlias<asm # ".8b",
6001 !cast<Instruction>(NAME#"v8i8Four"),
6002 V64, VecListFour128>;
6003 def : SIMDTableLookupAlias<asm # ".16b",
6004 !cast<Instruction>(NAME#"v16i8One"),
6005 V128, VecListOne128>;
6006 def : SIMDTableLookupAlias<asm # ".16b",
6007 !cast<Instruction>(NAME#"v16i8Two"),
6008 V128, VecListTwo128>;
6009 def : SIMDTableLookupAlias<asm # ".16b",
6010 !cast<Instruction>(NAME#"v16i8Three"),
6011 V128, VecListThree128>;
6012 def : SIMDTableLookupAlias<asm # ".16b",
6013 !cast<Instruction>(NAME#"v16i8Four"),
6014 V128, VecListFour128>;
6018 //----------------------------------------------------------------------------
6019 // AdvSIMD scalar CPY
6020 //----------------------------------------------------------------------------
6021 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6022 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
6023 string kind, Operand idxtype>
6024 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
6025 "{\t$dst, $src" # kind # "$idx" #
6026 "|\t$dst, $src$idx}", "", []>,
6030 let Inst{31-21} = 0b01011110000;
6031 let Inst{15-10} = 0b000001;
6032 let Inst{9-5} = src;
6033 let Inst{4-0} = dst;
6036 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
6037 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
6038 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
6039 # "|\t$dst, $src$index}",
6040 (inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
6043 multiclass SIMDScalarCPY<string asm> {
6044 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
6046 let Inst{20-17} = idx;
6049 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
6051 let Inst{20-18} = idx;
6052 let Inst{17-16} = 0b10;
6054 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
6056 let Inst{20-19} = idx;
6057 let Inst{18-16} = 0b100;
6059 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
6062 let Inst{19-16} = 0b1000;
6065 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
6066 VectorIndexD:$idx)))),
6067 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
6069 // 'DUP' mnemonic aliases.
6070 def : SIMDScalarCPYAlias<"dup", ".b",
6071 !cast<Instruction>(NAME#"i8"),
6072 FPR8, V128, VectorIndexB>;
6073 def : SIMDScalarCPYAlias<"dup", ".h",
6074 !cast<Instruction>(NAME#"i16"),
6075 FPR16, V128, VectorIndexH>;
6076 def : SIMDScalarCPYAlias<"dup", ".s",
6077 !cast<Instruction>(NAME#"i32"),
6078 FPR32, V128, VectorIndexS>;
6079 def : SIMDScalarCPYAlias<"dup", ".d",
6080 !cast<Instruction>(NAME#"i64"),
6081 FPR64, V128, VectorIndexD>;
6084 //----------------------------------------------------------------------------
6085 // AdvSIMD modified immediate instructions
6086 //----------------------------------------------------------------------------
6088 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
6089 string asm, string op_string,
6090 string cstr, list<dag> pattern>
6091 : I<oops, iops, asm, op_string, cstr, pattern>,
6098 let Inst{28-19} = 0b0111100000;
6099 let Inst{18-16} = imm8{7-5};
6100 let Inst{11-10} = 0b01;
6101 let Inst{9-5} = imm8{4-0};
6105 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
6106 Operand immtype, dag opt_shift_iop,
6107 string opt_shift, string asm, string kind,
6109 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
6110 !con((ins immtype:$imm8), opt_shift_iop), asm,
6111 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6112 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6114 let DecoderMethod = "DecodeModImmInstruction";
6117 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
6118 Operand immtype, dag opt_shift_iop,
6119 string opt_shift, string asm, string kind,
6121 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
6122 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6123 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6124 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6125 "$Rd = $dst", pattern> {
6126 let DecoderMethod = "DecodeModImmTiedInstruction";
6129 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6130 RegisterOperand vectype, string asm,
6131 string kind, list<dag> pattern>
6132 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6133 (ins logical_vec_shift:$shift),
6134 "$shift", asm, kind, pattern> {
6136 let Inst{15} = b15_b12{1};
6137 let Inst{14-13} = shift;
6138 let Inst{12} = b15_b12{0};
6141 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6142 RegisterOperand vectype, string asm,
6143 string kind, list<dag> pattern>
6144 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6145 (ins logical_vec_shift:$shift),
6146 "$shift", asm, kind, pattern> {
6148 let Inst{15} = b15_b12{1};
6149 let Inst{14-13} = shift;
6150 let Inst{12} = b15_b12{0};
6154 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6155 RegisterOperand vectype, string asm,
6156 string kind, list<dag> pattern>
6157 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6158 (ins logical_vec_hw_shift:$shift),
6159 "$shift", asm, kind, pattern> {
6161 let Inst{15} = b15_b12{1};
6163 let Inst{13} = shift{0};
6164 let Inst{12} = b15_b12{0};
6167 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6168 RegisterOperand vectype, string asm,
6169 string kind, list<dag> pattern>
6170 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6171 (ins logical_vec_hw_shift:$shift),
6172 "$shift", asm, kind, pattern> {
6174 let Inst{15} = b15_b12{1};
6176 let Inst{13} = shift{0};
6177 let Inst{12} = b15_b12{0};
6180 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6182 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6184 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6187 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6189 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6193 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6194 bits<2> w_cmode, string asm,
6196 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6198 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6200 (i32 imm:$shift)))]>;
6201 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6203 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6205 (i32 imm:$shift)))]>;
6207 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6209 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6211 (i32 imm:$shift)))]>;
6212 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6214 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6216 (i32 imm:$shift)))]>;
6219 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6220 RegisterOperand vectype, string asm,
6221 string kind, list<dag> pattern>
6222 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6223 (ins move_vec_shift:$shift),
6224 "$shift", asm, kind, pattern> {
6226 let Inst{15-13} = cmode{3-1};
6227 let Inst{12} = shift;
6230 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6231 RegisterOperand vectype,
6232 Operand imm_type, string asm,
6233 string kind, list<dag> pattern>
6234 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6235 asm, kind, pattern> {
6236 let Inst{15-12} = cmode;
6239 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6241 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6242 "\t$Rd, $imm8", "", pattern> {
6243 let Inst{15-12} = cmode;
6244 let DecoderMethod = "DecodeModImmInstruction";
6247 //----------------------------------------------------------------------------
6248 // AdvSIMD indexed element
6249 //----------------------------------------------------------------------------
6251 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6252 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6253 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6254 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6255 string apple_kind, string dst_kind, string lhs_kind,
6256 string rhs_kind, list<dag> pattern>
6257 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6259 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6260 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6269 let Inst{28} = Scalar;
6270 let Inst{27-24} = 0b1111;
6271 let Inst{23-22} = size;
6272 // Bit 21 must be set by the derived class.
6273 let Inst{20-16} = Rm;
6274 let Inst{15-12} = opc;
6275 // Bit 11 must be set by the derived class.
6281 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6282 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6283 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6284 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6285 string apple_kind, string dst_kind, string lhs_kind,
6286 string rhs_kind, list<dag> pattern>
6287 : I<(outs dst_reg:$dst),
6288 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6289 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6290 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6299 let Inst{28} = Scalar;
6300 let Inst{27-24} = 0b1111;
6301 let Inst{23-22} = size;
6302 // Bit 21 must be set by the derived class.
6303 let Inst{20-16} = Rm;
6304 let Inst{15-12} = opc;
6305 // Bit 11 must be set by the derived class.
6311 multiclass SIMDFPIndexedSD<bit U, bits<4> opc, string asm,
6312 SDPatternOperator OpNode> {
6313 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6316 asm, ".2s", ".2s", ".2s", ".s",
6317 [(set (v2f32 V64:$Rd),
6318 (OpNode (v2f32 V64:$Rn),
6319 (v2f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6321 let Inst{11} = idx{1};
6322 let Inst{21} = idx{0};
6325 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6328 asm, ".4s", ".4s", ".4s", ".s",
6329 [(set (v4f32 V128:$Rd),
6330 (OpNode (v4f32 V128:$Rn),
6331 (v4f32 (AArch64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6333 let Inst{11} = idx{1};
6334 let Inst{21} = idx{0};
6337 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6340 asm, ".2d", ".2d", ".2d", ".d",
6341 [(set (v2f64 V128:$Rd),
6342 (OpNode (v2f64 V128:$Rn),
6343 (v2f64 (AArch64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6345 let Inst{11} = idx{0};
6349 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6350 FPR32Op, FPR32Op, V128, VectorIndexS,
6351 asm, ".s", "", "", ".s",
6352 [(set (f32 FPR32Op:$Rd),
6353 (OpNode (f32 FPR32Op:$Rn),
6354 (f32 (vector_extract (v4f32 V128:$Rm),
6355 VectorIndexS:$idx))))]> {
6357 let Inst{11} = idx{1};
6358 let Inst{21} = idx{0};
6361 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6362 FPR64Op, FPR64Op, V128, VectorIndexD,
6363 asm, ".d", "", "", ".d",
6364 [(set (f64 FPR64Op:$Rd),
6365 (OpNode (f64 FPR64Op:$Rn),
6366 (f64 (vector_extract (v2f64 V128:$Rm),
6367 VectorIndexD:$idx))))]> {
6369 let Inst{11} = idx{0};
6374 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6375 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6376 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6377 (AArch64duplane32 (v4f32 V128:$Rm),
6378 VectorIndexS:$idx))),
6379 (!cast<Instruction>(INST # v2i32_indexed)
6380 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6381 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6382 (AArch64dup (f32 FPR32Op:$Rm)))),
6383 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6384 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6387 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6388 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6389 (AArch64duplane32 (v4f32 V128:$Rm),
6390 VectorIndexS:$idx))),
6391 (!cast<Instruction>(INST # "v4i32_indexed")
6392 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6393 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6394 (AArch64dup (f32 FPR32Op:$Rm)))),
6395 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6396 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6398 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6399 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6400 (AArch64duplane64 (v2f64 V128:$Rm),
6401 VectorIndexD:$idx))),
6402 (!cast<Instruction>(INST # "v2i64_indexed")
6403 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6404 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6405 (AArch64dup (f64 FPR64Op:$Rm)))),
6406 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6407 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6409 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6410 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6411 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6412 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6413 V128:$Rm, VectorIndexS:$idx)>;
6414 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6415 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6416 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6417 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6419 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6420 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6421 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6422 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6423 V128:$Rm, VectorIndexD:$idx)>;
6426 multiclass SIMDFPIndexedSDTied<bit U, bits<4> opc, string asm> {
6427 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6429 asm, ".2s", ".2s", ".2s", ".s", []> {
6431 let Inst{11} = idx{1};
6432 let Inst{21} = idx{0};
6435 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6438 asm, ".4s", ".4s", ".4s", ".s", []> {
6440 let Inst{11} = idx{1};
6441 let Inst{21} = idx{0};
6444 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6447 asm, ".2d", ".2d", ".2d", ".d", []> {
6449 let Inst{11} = idx{0};
6454 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6455 FPR32Op, FPR32Op, V128, VectorIndexS,
6456 asm, ".s", "", "", ".s", []> {
6458 let Inst{11} = idx{1};
6459 let Inst{21} = idx{0};
6462 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6463 FPR64Op, FPR64Op, V128, VectorIndexD,
6464 asm, ".d", "", "", ".d", []> {
6466 let Inst{11} = idx{0};
6471 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6472 SDPatternOperator OpNode> {
6473 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6474 V128_lo, VectorIndexH,
6475 asm, ".4h", ".4h", ".4h", ".h",
6476 [(set (v4i16 V64:$Rd),
6477 (OpNode (v4i16 V64:$Rn),
6478 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6480 let Inst{11} = idx{2};
6481 let Inst{21} = idx{1};
6482 let Inst{20} = idx{0};
6485 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6487 V128_lo, VectorIndexH,
6488 asm, ".8h", ".8h", ".8h", ".h",
6489 [(set (v8i16 V128:$Rd),
6490 (OpNode (v8i16 V128:$Rn),
6491 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6493 let Inst{11} = idx{2};
6494 let Inst{21} = idx{1};
6495 let Inst{20} = idx{0};
6498 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6501 asm, ".2s", ".2s", ".2s", ".s",
6502 [(set (v2i32 V64:$Rd),
6503 (OpNode (v2i32 V64:$Rn),
6504 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6506 let Inst{11} = idx{1};
6507 let Inst{21} = idx{0};
6510 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6513 asm, ".4s", ".4s", ".4s", ".s",
6514 [(set (v4i32 V128:$Rd),
6515 (OpNode (v4i32 V128:$Rn),
6516 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6518 let Inst{11} = idx{1};
6519 let Inst{21} = idx{0};
6522 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6523 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6524 asm, ".h", "", "", ".h", []> {
6526 let Inst{11} = idx{2};
6527 let Inst{21} = idx{1};
6528 let Inst{20} = idx{0};
6531 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6532 FPR32Op, FPR32Op, V128, VectorIndexS,
6533 asm, ".s", "", "", ".s",
6534 [(set (i32 FPR32Op:$Rd),
6535 (OpNode FPR32Op:$Rn,
6536 (i32 (vector_extract (v4i32 V128:$Rm),
6537 VectorIndexS:$idx))))]> {
6539 let Inst{11} = idx{1};
6540 let Inst{21} = idx{0};
6544 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6545 SDPatternOperator OpNode> {
6546 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6548 V128_lo, VectorIndexH,
6549 asm, ".4h", ".4h", ".4h", ".h",
6550 [(set (v4i16 V64:$Rd),
6551 (OpNode (v4i16 V64:$Rn),
6552 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6554 let Inst{11} = idx{2};
6555 let Inst{21} = idx{1};
6556 let Inst{20} = idx{0};
6559 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6561 V128_lo, VectorIndexH,
6562 asm, ".8h", ".8h", ".8h", ".h",
6563 [(set (v8i16 V128:$Rd),
6564 (OpNode (v8i16 V128:$Rn),
6565 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6567 let Inst{11} = idx{2};
6568 let Inst{21} = idx{1};
6569 let Inst{20} = idx{0};
6572 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6575 asm, ".2s", ".2s", ".2s", ".s",
6576 [(set (v2i32 V64:$Rd),
6577 (OpNode (v2i32 V64:$Rn),
6578 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6580 let Inst{11} = idx{1};
6581 let Inst{21} = idx{0};
6584 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6587 asm, ".4s", ".4s", ".4s", ".s",
6588 [(set (v4i32 V128:$Rd),
6589 (OpNode (v4i32 V128:$Rn),
6590 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6592 let Inst{11} = idx{1};
6593 let Inst{21} = idx{0};
6597 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6598 SDPatternOperator OpNode> {
6599 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6600 V128_lo, VectorIndexH,
6601 asm, ".4h", ".4h", ".4h", ".h",
6602 [(set (v4i16 V64:$dst),
6603 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6604 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6606 let Inst{11} = idx{2};
6607 let Inst{21} = idx{1};
6608 let Inst{20} = idx{0};
6611 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6613 V128_lo, VectorIndexH,
6614 asm, ".8h", ".8h", ".8h", ".h",
6615 [(set (v8i16 V128:$dst),
6616 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6617 (v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6619 let Inst{11} = idx{2};
6620 let Inst{21} = idx{1};
6621 let Inst{20} = idx{0};
6624 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6627 asm, ".2s", ".2s", ".2s", ".s",
6628 [(set (v2i32 V64:$dst),
6629 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6630 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6632 let Inst{11} = idx{1};
6633 let Inst{21} = idx{0};
6636 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6639 asm, ".4s", ".4s", ".4s", ".s",
6640 [(set (v4i32 V128:$dst),
6641 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6642 (v4i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6644 let Inst{11} = idx{1};
6645 let Inst{21} = idx{0};
6649 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6650 SDPatternOperator OpNode> {
6651 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6653 V128_lo, VectorIndexH,
6654 asm, ".4s", ".4s", ".4h", ".h",
6655 [(set (v4i32 V128:$Rd),
6656 (OpNode (v4i16 V64:$Rn),
6657 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6659 let Inst{11} = idx{2};
6660 let Inst{21} = idx{1};
6661 let Inst{20} = idx{0};
6664 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6666 V128_lo, VectorIndexH,
6667 asm#"2", ".4s", ".4s", ".8h", ".h",
6668 [(set (v4i32 V128:$Rd),
6669 (OpNode (extract_high_v8i16 V128:$Rn),
6670 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6671 VectorIndexH:$idx))))]> {
6674 let Inst{11} = idx{2};
6675 let Inst{21} = idx{1};
6676 let Inst{20} = idx{0};
6679 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6682 asm, ".2d", ".2d", ".2s", ".s",
6683 [(set (v2i64 V128:$Rd),
6684 (OpNode (v2i32 V64:$Rn),
6685 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6687 let Inst{11} = idx{1};
6688 let Inst{21} = idx{0};
6691 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6694 asm#"2", ".2d", ".2d", ".4s", ".s",
6695 [(set (v2i64 V128:$Rd),
6696 (OpNode (extract_high_v4i32 V128:$Rn),
6697 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6698 VectorIndexS:$idx))))]> {
6700 let Inst{11} = idx{1};
6701 let Inst{21} = idx{0};
6704 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6705 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6706 asm, ".h", "", "", ".h", []> {
6708 let Inst{11} = idx{2};
6709 let Inst{21} = idx{1};
6710 let Inst{20} = idx{0};
6713 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6714 FPR64Op, FPR32Op, V128, VectorIndexS,
6715 asm, ".s", "", "", ".s", []> {
6717 let Inst{11} = idx{1};
6718 let Inst{21} = idx{0};
6722 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6723 SDPatternOperator Accum> {
6724 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6726 V128_lo, VectorIndexH,
6727 asm, ".4s", ".4s", ".4h", ".h",
6728 [(set (v4i32 V128:$dst),
6729 (Accum (v4i32 V128:$Rd),
6730 (v4i32 (int_aarch64_neon_sqdmull
6732 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6733 VectorIndexH:$idx))))))]> {
6735 let Inst{11} = idx{2};
6736 let Inst{21} = idx{1};
6737 let Inst{20} = idx{0};
6740 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6741 // intermediate EXTRACT_SUBREG would be untyped.
6742 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6743 (i32 (vector_extract (v4i32
6744 (int_aarch64_neon_sqdmull (v4i16 V64:$Rn),
6745 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6746 VectorIndexH:$idx)))),
6749 (!cast<Instruction>(NAME # v4i16_indexed)
6750 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6751 V128_lo:$Rm, VectorIndexH:$idx),
6754 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6756 V128_lo, VectorIndexH,
6757 asm#"2", ".4s", ".4s", ".8h", ".h",
6758 [(set (v4i32 V128:$dst),
6759 (Accum (v4i32 V128:$Rd),
6760 (v4i32 (int_aarch64_neon_sqdmull
6761 (extract_high_v8i16 V128:$Rn),
6763 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6764 VectorIndexH:$idx))))))]> {
6766 let Inst{11} = idx{2};
6767 let Inst{21} = idx{1};
6768 let Inst{20} = idx{0};
6771 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6774 asm, ".2d", ".2d", ".2s", ".s",
6775 [(set (v2i64 V128:$dst),
6776 (Accum (v2i64 V128:$Rd),
6777 (v2i64 (int_aarch64_neon_sqdmull
6779 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm),
6780 VectorIndexS:$idx))))))]> {
6782 let Inst{11} = idx{1};
6783 let Inst{21} = idx{0};
6786 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6789 asm#"2", ".2d", ".2d", ".4s", ".s",
6790 [(set (v2i64 V128:$dst),
6791 (Accum (v2i64 V128:$Rd),
6792 (v2i64 (int_aarch64_neon_sqdmull
6793 (extract_high_v4i32 V128:$Rn),
6795 (AArch64duplane32 (v4i32 V128:$Rm),
6796 VectorIndexS:$idx))))))]> {
6798 let Inst{11} = idx{1};
6799 let Inst{21} = idx{0};
6802 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6803 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6804 asm, ".h", "", "", ".h", []> {
6806 let Inst{11} = idx{2};
6807 let Inst{21} = idx{1};
6808 let Inst{20} = idx{0};
6812 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6813 FPR64Op, FPR32Op, V128, VectorIndexS,
6814 asm, ".s", "", "", ".s",
6815 [(set (i64 FPR64Op:$dst),
6816 (Accum (i64 FPR64Op:$Rd),
6817 (i64 (int_aarch64_neon_sqdmulls_scalar
6819 (i32 (vector_extract (v4i32 V128:$Rm),
6820 VectorIndexS:$idx))))))]> {
6823 let Inst{11} = idx{1};
6824 let Inst{21} = idx{0};
6828 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6829 SDPatternOperator OpNode> {
6830 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6831 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6833 V128_lo, VectorIndexH,
6834 asm, ".4s", ".4s", ".4h", ".h",
6835 [(set (v4i32 V128:$Rd),
6836 (OpNode (v4i16 V64:$Rn),
6837 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6839 let Inst{11} = idx{2};
6840 let Inst{21} = idx{1};
6841 let Inst{20} = idx{0};
6844 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6846 V128_lo, VectorIndexH,
6847 asm#"2", ".4s", ".4s", ".8h", ".h",
6848 [(set (v4i32 V128:$Rd),
6849 (OpNode (extract_high_v8i16 V128:$Rn),
6850 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6851 VectorIndexH:$idx))))]> {
6854 let Inst{11} = idx{2};
6855 let Inst{21} = idx{1};
6856 let Inst{20} = idx{0};
6859 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6862 asm, ".2d", ".2d", ".2s", ".s",
6863 [(set (v2i64 V128:$Rd),
6864 (OpNode (v2i32 V64:$Rn),
6865 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6867 let Inst{11} = idx{1};
6868 let Inst{21} = idx{0};
6871 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6874 asm#"2", ".2d", ".2d", ".4s", ".s",
6875 [(set (v2i64 V128:$Rd),
6876 (OpNode (extract_high_v4i32 V128:$Rn),
6877 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6878 VectorIndexS:$idx))))]> {
6880 let Inst{11} = idx{1};
6881 let Inst{21} = idx{0};
6886 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
6887 SDPatternOperator OpNode> {
6888 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6889 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6891 V128_lo, VectorIndexH,
6892 asm, ".4s", ".4s", ".4h", ".h",
6893 [(set (v4i32 V128:$dst),
6894 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
6895 (v4i16 (AArch64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6897 let Inst{11} = idx{2};
6898 let Inst{21} = idx{1};
6899 let Inst{20} = idx{0};
6902 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6904 V128_lo, VectorIndexH,
6905 asm#"2", ".4s", ".4s", ".8h", ".h",
6906 [(set (v4i32 V128:$dst),
6907 (OpNode (v4i32 V128:$Rd),
6908 (extract_high_v8i16 V128:$Rn),
6909 (extract_high_v8i16 (AArch64duplane16 (v8i16 V128_lo:$Rm),
6910 VectorIndexH:$idx))))]> {
6912 let Inst{11} = idx{2};
6913 let Inst{21} = idx{1};
6914 let Inst{20} = idx{0};
6917 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6920 asm, ".2d", ".2d", ".2s", ".s",
6921 [(set (v2i64 V128:$dst),
6922 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
6923 (v2i32 (AArch64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6925 let Inst{11} = idx{1};
6926 let Inst{21} = idx{0};
6929 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6932 asm#"2", ".2d", ".2d", ".4s", ".s",
6933 [(set (v2i64 V128:$dst),
6934 (OpNode (v2i64 V128:$Rd),
6935 (extract_high_v4i32 V128:$Rn),
6936 (extract_high_v4i32 (AArch64duplane32 (v4i32 V128:$Rm),
6937 VectorIndexS:$idx))))]> {
6939 let Inst{11} = idx{1};
6940 let Inst{21} = idx{0};
6945 //----------------------------------------------------------------------------
6946 // AdvSIMD scalar shift by immediate
6947 //----------------------------------------------------------------------------
6949 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6950 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
6951 RegisterClass regtype1, RegisterClass regtype2,
6952 Operand immtype, string asm, list<dag> pattern>
6953 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
6954 asm, "\t$Rd, $Rn, $imm", "", pattern>,
6959 let Inst{31-30} = 0b01;
6961 let Inst{28-23} = 0b111110;
6962 let Inst{22-16} = fixed_imm;
6963 let Inst{15-11} = opc;
6969 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6970 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
6971 RegisterClass regtype1, RegisterClass regtype2,
6972 Operand immtype, string asm, list<dag> pattern>
6973 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
6974 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
6979 let Inst{31-30} = 0b01;
6981 let Inst{28-23} = 0b111110;
6982 let Inst{22-16} = fixed_imm;
6983 let Inst{15-11} = opc;
6990 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
6991 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6992 FPR32, FPR32, vecshiftR32, asm, []> {
6993 let Inst{20-16} = imm{4-0};
6996 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6997 FPR64, FPR64, vecshiftR64, asm, []> {
6998 let Inst{21-16} = imm{5-0};
7002 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
7003 SDPatternOperator OpNode> {
7004 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7005 FPR64, FPR64, vecshiftR64, asm,
7006 [(set (i64 FPR64:$Rd),
7007 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
7008 let Inst{21-16} = imm{5-0};
7011 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
7012 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
7015 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
7016 SDPatternOperator OpNode = null_frag> {
7017 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7018 FPR64, FPR64, vecshiftR64, asm,
7019 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7020 (i32 vecshiftR64:$imm)))]> {
7021 let Inst{21-16} = imm{5-0};
7024 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7025 (i32 vecshiftR64:$imm))),
7026 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7030 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
7031 SDPatternOperator OpNode> {
7032 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7033 FPR64, FPR64, vecshiftL64, asm,
7034 [(set (v1i64 FPR64:$Rd),
7035 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7036 let Inst{21-16} = imm{5-0};
7040 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7041 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
7042 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
7043 FPR64, FPR64, vecshiftL64, asm, []> {
7044 let Inst{21-16} = imm{5-0};
7048 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7049 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
7050 SDPatternOperator OpNode = null_frag> {
7051 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7052 FPR8, FPR16, vecshiftR8, asm, []> {
7053 let Inst{18-16} = imm{2-0};
7056 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7057 FPR16, FPR32, vecshiftR16, asm, []> {
7058 let Inst{19-16} = imm{3-0};
7061 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7062 FPR32, FPR64, vecshiftR32, asm,
7063 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7064 let Inst{20-16} = imm{4-0};
7068 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
7069 SDPatternOperator OpNode> {
7070 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7071 FPR8, FPR8, vecshiftL8, asm, []> {
7072 let Inst{18-16} = imm{2-0};
7075 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7076 FPR16, FPR16, vecshiftL16, asm, []> {
7077 let Inst{19-16} = imm{3-0};
7080 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7081 FPR32, FPR32, vecshiftL32, asm,
7082 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7083 let Inst{20-16} = imm{4-0};
7086 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7087 FPR64, FPR64, vecshiftL64, asm,
7088 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7089 let Inst{21-16} = imm{5-0};
7092 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
7093 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
7096 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
7097 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
7098 FPR8, FPR8, vecshiftR8, asm, []> {
7099 let Inst{18-16} = imm{2-0};
7102 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
7103 FPR16, FPR16, vecshiftR16, asm, []> {
7104 let Inst{19-16} = imm{3-0};
7107 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
7108 FPR32, FPR32, vecshiftR32, asm, []> {
7109 let Inst{20-16} = imm{4-0};
7112 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
7113 FPR64, FPR64, vecshiftR64, asm, []> {
7114 let Inst{21-16} = imm{5-0};
7118 //----------------------------------------------------------------------------
7119 // AdvSIMD vector x indexed element
7120 //----------------------------------------------------------------------------
7122 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7123 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7124 RegisterOperand dst_reg, RegisterOperand src_reg,
7126 string asm, string dst_kind, string src_kind,
7128 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7129 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7130 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7137 let Inst{28-23} = 0b011110;
7138 let Inst{22-16} = fixed_imm;
7139 let Inst{15-11} = opc;
7145 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7146 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7147 RegisterOperand vectype1, RegisterOperand vectype2,
7149 string asm, string dst_kind, string src_kind,
7151 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7152 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7153 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7160 let Inst{28-23} = 0b011110;
7161 let Inst{22-16} = fixed_imm;
7162 let Inst{15-11} = opc;
7168 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7170 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7171 V64, V64, vecshiftR32,
7173 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7175 let Inst{20-16} = imm;
7178 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7179 V128, V128, vecshiftR32,
7181 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7183 let Inst{20-16} = imm;
7186 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7187 V128, V128, vecshiftR64,
7189 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7191 let Inst{21-16} = imm;
7195 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7197 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7198 V64, V64, vecshiftR32,
7200 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7202 let Inst{20-16} = imm;
7205 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7206 V128, V128, vecshiftR32,
7208 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7210 let Inst{20-16} = imm;
7213 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7214 V128, V128, vecshiftR64,
7216 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7218 let Inst{21-16} = imm;
7222 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7223 SDPatternOperator OpNode> {
7224 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7225 V64, V128, vecshiftR16Narrow,
7227 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7229 let Inst{18-16} = imm;
7232 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7233 V128, V128, vecshiftR16Narrow,
7234 asm#"2", ".16b", ".8h", []> {
7236 let Inst{18-16} = imm;
7237 let hasSideEffects = 0;
7240 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7241 V64, V128, vecshiftR32Narrow,
7243 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7245 let Inst{19-16} = imm;
7248 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7249 V128, V128, vecshiftR32Narrow,
7250 asm#"2", ".8h", ".4s", []> {
7252 let Inst{19-16} = imm;
7253 let hasSideEffects = 0;
7256 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7257 V64, V128, vecshiftR64Narrow,
7259 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7261 let Inst{20-16} = imm;
7264 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7265 V128, V128, vecshiftR64Narrow,
7266 asm#"2", ".4s", ".2d", []> {
7268 let Inst{20-16} = imm;
7269 let hasSideEffects = 0;
7272 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7273 // themselves, so put them here instead.
7275 // Patterns involving what's effectively an insert high and a normal
7276 // intrinsic, represented by CONCAT_VECTORS.
7277 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7278 vecshiftR16Narrow:$imm)),
7279 (!cast<Instruction>(NAME # "v16i8_shift")
7280 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7281 V128:$Rn, vecshiftR16Narrow:$imm)>;
7282 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7283 vecshiftR32Narrow:$imm)),
7284 (!cast<Instruction>(NAME # "v8i16_shift")
7285 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7286 V128:$Rn, vecshiftR32Narrow:$imm)>;
7287 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7288 vecshiftR64Narrow:$imm)),
7289 (!cast<Instruction>(NAME # "v4i32_shift")
7290 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7291 V128:$Rn, vecshiftR64Narrow:$imm)>;
7294 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7295 SDPatternOperator OpNode> {
7296 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7297 V64, V64, vecshiftL8,
7299 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7300 (i32 vecshiftL8:$imm)))]> {
7302 let Inst{18-16} = imm;
7305 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7306 V128, V128, vecshiftL8,
7307 asm, ".16b", ".16b",
7308 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7309 (i32 vecshiftL8:$imm)))]> {
7311 let Inst{18-16} = imm;
7314 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7315 V64, V64, vecshiftL16,
7317 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7318 (i32 vecshiftL16:$imm)))]> {
7320 let Inst{19-16} = imm;
7323 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7324 V128, V128, vecshiftL16,
7326 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7327 (i32 vecshiftL16:$imm)))]> {
7329 let Inst{19-16} = imm;
7332 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7333 V64, V64, vecshiftL32,
7335 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7336 (i32 vecshiftL32:$imm)))]> {
7338 let Inst{20-16} = imm;
7341 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7342 V128, V128, vecshiftL32,
7344 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7345 (i32 vecshiftL32:$imm)))]> {
7347 let Inst{20-16} = imm;
7350 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7351 V128, V128, vecshiftL64,
7353 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7354 (i32 vecshiftL64:$imm)))]> {
7356 let Inst{21-16} = imm;
7360 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7361 SDPatternOperator OpNode> {
7362 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7363 V64, V64, vecshiftR8,
7365 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7366 (i32 vecshiftR8:$imm)))]> {
7368 let Inst{18-16} = imm;
7371 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7372 V128, V128, vecshiftR8,
7373 asm, ".16b", ".16b",
7374 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7375 (i32 vecshiftR8:$imm)))]> {
7377 let Inst{18-16} = imm;
7380 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7381 V64, V64, vecshiftR16,
7383 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7384 (i32 vecshiftR16:$imm)))]> {
7386 let Inst{19-16} = imm;
7389 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7390 V128, V128, vecshiftR16,
7392 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7393 (i32 vecshiftR16:$imm)))]> {
7395 let Inst{19-16} = imm;
7398 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7399 V64, V64, vecshiftR32,
7401 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7402 (i32 vecshiftR32:$imm)))]> {
7404 let Inst{20-16} = imm;
7407 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7408 V128, V128, vecshiftR32,
7410 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7411 (i32 vecshiftR32:$imm)))]> {
7413 let Inst{20-16} = imm;
7416 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7417 V128, V128, vecshiftR64,
7419 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7420 (i32 vecshiftR64:$imm)))]> {
7422 let Inst{21-16} = imm;
7426 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7427 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7428 SDPatternOperator OpNode = null_frag> {
7429 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7430 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7431 [(set (v8i8 V64:$dst),
7432 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7433 (i32 vecshiftR8:$imm)))]> {
7435 let Inst{18-16} = imm;
7438 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7439 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7440 [(set (v16i8 V128:$dst),
7441 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7442 (i32 vecshiftR8:$imm)))]> {
7444 let Inst{18-16} = imm;
7447 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7448 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7449 [(set (v4i16 V64:$dst),
7450 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7451 (i32 vecshiftR16:$imm)))]> {
7453 let Inst{19-16} = imm;
7456 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7457 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7458 [(set (v8i16 V128:$dst),
7459 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7460 (i32 vecshiftR16:$imm)))]> {
7462 let Inst{19-16} = imm;
7465 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7466 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7467 [(set (v2i32 V64:$dst),
7468 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7469 (i32 vecshiftR32:$imm)))]> {
7471 let Inst{20-16} = imm;
7474 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7475 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7476 [(set (v4i32 V128:$dst),
7477 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7478 (i32 vecshiftR32:$imm)))]> {
7480 let Inst{20-16} = imm;
7483 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7484 V128, V128, vecshiftR64,
7485 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7486 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7487 (i32 vecshiftR64:$imm)))]> {
7489 let Inst{21-16} = imm;
7493 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7494 SDPatternOperator OpNode = null_frag> {
7495 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7496 V64, V64, vecshiftL8,
7498 [(set (v8i8 V64:$dst),
7499 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7500 (i32 vecshiftL8:$imm)))]> {
7502 let Inst{18-16} = imm;
7505 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7506 V128, V128, vecshiftL8,
7507 asm, ".16b", ".16b",
7508 [(set (v16i8 V128:$dst),
7509 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7510 (i32 vecshiftL8:$imm)))]> {
7512 let Inst{18-16} = imm;
7515 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7516 V64, V64, vecshiftL16,
7518 [(set (v4i16 V64:$dst),
7519 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7520 (i32 vecshiftL16:$imm)))]> {
7522 let Inst{19-16} = imm;
7525 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7526 V128, V128, vecshiftL16,
7528 [(set (v8i16 V128:$dst),
7529 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7530 (i32 vecshiftL16:$imm)))]> {
7532 let Inst{19-16} = imm;
7535 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7536 V64, V64, vecshiftL32,
7538 [(set (v2i32 V64:$dst),
7539 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7540 (i32 vecshiftL32:$imm)))]> {
7542 let Inst{20-16} = imm;
7545 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7546 V128, V128, vecshiftL32,
7548 [(set (v4i32 V128:$dst),
7549 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7550 (i32 vecshiftL32:$imm)))]> {
7552 let Inst{20-16} = imm;
7555 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7556 V128, V128, vecshiftL64,
7558 [(set (v2i64 V128:$dst),
7559 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7560 (i32 vecshiftL64:$imm)))]> {
7562 let Inst{21-16} = imm;
7566 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7567 SDPatternOperator OpNode> {
7568 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7569 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7570 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7572 let Inst{18-16} = imm;
7575 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7576 V128, V128, vecshiftL8,
7577 asm#"2", ".8h", ".16b",
7578 [(set (v8i16 V128:$Rd),
7579 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7581 let Inst{18-16} = imm;
7584 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7585 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7586 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7588 let Inst{19-16} = imm;
7591 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7592 V128, V128, vecshiftL16,
7593 asm#"2", ".4s", ".8h",
7594 [(set (v4i32 V128:$Rd),
7595 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7598 let Inst{19-16} = imm;
7601 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7602 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7603 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7605 let Inst{20-16} = imm;
7608 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7609 V128, V128, vecshiftL32,
7610 asm#"2", ".2d", ".4s",
7611 [(set (v2i64 V128:$Rd),
7612 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7614 let Inst{20-16} = imm;
7620 // Vector load/store
7622 // SIMD ldX/stX no-index memory references don't allow the optional
7623 // ", #0" constant and handle post-indexing explicitly, so we use
7624 // a more specialized parse method for them. Otherwise, it's the same as
7625 // the general GPR64sp handling.
7627 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7628 string asm, dag oops, dag iops, list<dag> pattern>
7629 : I<oops, iops, asm, "\t$Vt, [$Rn]", "", pattern> {
7634 let Inst{29-23} = 0b0011000;
7636 let Inst{21-16} = 0b000000;
7637 let Inst{15-12} = opcode;
7638 let Inst{11-10} = size;
7643 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7644 string asm, dag oops, dag iops>
7645 : I<oops, iops, asm, "\t$Vt, [$Rn], $Xm", "$Rn = $wback", []> {
7651 let Inst{29-23} = 0b0011001;
7654 let Inst{20-16} = Xm;
7655 let Inst{15-12} = opcode;
7656 let Inst{11-10} = size;
7661 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7662 // register post-index addressing from the zero register.
7663 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7664 int Offset, int Size> {
7665 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7666 // "ld1\t$Vt, [$Rn], #16"
7667 // may get mapped to
7668 // (LD1Twov8b_POST VecListTwo8b:$Vt, GPR64sp:$Rn, XZR)
7669 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7670 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7672 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7675 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7676 // "ld1.8b\t$Vt, [$Rn], #16"
7677 // may get mapped to
7678 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, XZR)
7679 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
7680 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7682 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7685 // E.g. "ld1.8b { v0, v1 }, [x1]"
7686 // "ld1\t$Vt, [$Rn]"
7687 // may get mapped to
7688 // (LD1Twov8b VecListTwo64:$Vt, GPR64sp:$Rn)
7689 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
7690 (!cast<Instruction>(NAME # Count # "v" # layout)
7691 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7694 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7695 // "ld1\t$Vt, [$Rn], $Xm"
7696 // may get mapped to
7697 // (LD1Twov8b_POST VecListTwo64:$Vt, GPR64sp:$Rn, GPR64pi8:$Xm)
7698 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
7699 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7701 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7702 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7705 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7706 int Offset64, bits<4> opcode> {
7707 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7708 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7709 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7710 (ins GPR64sp:$Rn), []>;
7711 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7712 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7713 (ins GPR64sp:$Rn), []>;
7714 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7715 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7716 (ins GPR64sp:$Rn), []>;
7717 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7718 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7719 (ins GPR64sp:$Rn), []>;
7720 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7721 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7722 (ins GPR64sp:$Rn), []>;
7723 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7724 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7725 (ins GPR64sp:$Rn), []>;
7726 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7727 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7728 (ins GPR64sp:$Rn), []>;
7731 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7732 (outs GPR64sp:$wback,
7733 !cast<RegisterOperand>(veclist # "16b"):$Vt),
7735 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7736 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7737 (outs GPR64sp:$wback,
7738 !cast<RegisterOperand>(veclist # "8h"):$Vt),
7740 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7741 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7742 (outs GPR64sp:$wback,
7743 !cast<RegisterOperand>(veclist # "4s"):$Vt),
7745 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7746 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7747 (outs GPR64sp:$wback,
7748 !cast<RegisterOperand>(veclist # "2d"):$Vt),
7750 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7751 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7752 (outs GPR64sp:$wback,
7753 !cast<RegisterOperand>(veclist # "8b"):$Vt),
7755 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7756 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7757 (outs GPR64sp:$wback,
7758 !cast<RegisterOperand>(veclist # "4h"):$Vt),
7760 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7761 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7762 (outs GPR64sp:$wback,
7763 !cast<RegisterOperand>(veclist # "2s"):$Vt),
7765 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7768 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7769 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7770 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7771 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7772 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7773 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7774 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7777 // Only ld1/st1 has a v1d version.
7778 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7779 int Offset64, bits<4> opcode> {
7780 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7781 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7782 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7784 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7785 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7787 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7788 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7790 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7791 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7793 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7794 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7796 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7797 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7799 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7800 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7803 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7804 (outs GPR64sp:$wback),
7805 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7807 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7808 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
7809 (outs GPR64sp:$wback),
7810 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7812 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7813 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
7814 (outs GPR64sp:$wback),
7815 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7817 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7818 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
7819 (outs GPR64sp:$wback),
7820 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7822 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7823 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
7824 (outs GPR64sp:$wback),
7825 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7827 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7828 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
7829 (outs GPR64sp:$wback),
7830 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7832 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7833 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
7834 (outs GPR64sp:$wback),
7835 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7837 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7840 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7841 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7842 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7843 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7844 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7845 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7846 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7849 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
7850 int Offset128, int Offset64, bits<4> opcode>
7851 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7853 // LD1 instructions have extra "1d" variants.
7854 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7855 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
7856 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7857 (ins GPR64sp:$Rn), []>;
7859 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
7860 (outs GPR64sp:$wback,
7861 !cast<RegisterOperand>(veclist # "1d"):$Vt),
7863 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7866 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7869 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
7870 int Offset128, int Offset64, bits<4> opcode>
7871 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7873 // ST1 instructions have extra "1d" variants.
7874 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
7875 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
7876 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7879 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
7880 (outs GPR64sp:$wback),
7881 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7883 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7886 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7889 multiclass SIMDLd1Multiple<string asm> {
7890 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7891 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7892 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7893 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7896 multiclass SIMDSt1Multiple<string asm> {
7897 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7898 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7899 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7900 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7903 multiclass SIMDLd2Multiple<string asm> {
7904 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7907 multiclass SIMDSt2Multiple<string asm> {
7908 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7911 multiclass SIMDLd3Multiple<string asm> {
7912 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7915 multiclass SIMDSt3Multiple<string asm> {
7916 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7919 multiclass SIMDLd4Multiple<string asm> {
7920 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7923 multiclass SIMDSt4Multiple<string asm> {
7924 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7928 // AdvSIMD Load/store single-element
7931 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
7932 string asm, string operands, string cst,
7933 dag oops, dag iops, list<dag> pattern>
7934 : I<oops, iops, asm, operands, cst, pattern> {
7938 let Inst{29-24} = 0b001101;
7941 let Inst{15-13} = opcode;
7946 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
7947 string asm, string operands, string cst,
7948 dag oops, dag iops, list<dag> pattern>
7949 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
7953 let Inst{29-24} = 0b001101;
7956 let Inst{15-13} = opcode;
7962 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7963 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
7965 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn]", "",
7966 (outs listtype:$Vt), (ins GPR64sp:$Rn),
7970 let Inst{20-16} = 0b00000;
7972 let Inst{11-10} = size;
7974 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7975 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
7976 string asm, Operand listtype, Operand GPR64pi>
7977 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, [$Rn], $Xm",
7979 (outs GPR64sp:$wback, listtype:$Vt),
7980 (ins GPR64sp:$Rn, GPR64pi:$Xm), []> {
7984 let Inst{20-16} = Xm;
7986 let Inst{11-10} = size;
7989 multiclass SIMDLdrAliases<string asm, string layout, string Count,
7990 int Offset, int Size> {
7991 // E.g. "ld1r { v0.8b }, [x1], #1"
7992 // "ld1r.8b\t$Vt, [$Rn], #1"
7993 // may get mapped to
7994 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
7995 def : InstAlias<asm # "\t$Vt, [$Rn], #" # Offset,
7996 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7998 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8001 // E.g. "ld1r.8b { v0 }, [x1], #1"
8002 // "ld1r.8b\t$Vt, [$Rn], #1"
8003 // may get mapped to
8004 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8005 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], #" # Offset,
8006 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8008 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8011 // E.g. "ld1r.8b { v0 }, [x1]"
8012 // "ld1r.8b\t$Vt, [$Rn]"
8013 // may get mapped to
8014 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8015 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn]",
8016 (!cast<Instruction>(NAME # "v" # layout)
8017 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8020 // E.g. "ld1r.8b { v0 }, [x1], x2"
8021 // "ld1r.8b\t$Vt, [$Rn], $Xm"
8022 // may get mapped to
8023 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8024 def : InstAlias<asm # "." # layout # "\t$Vt, [$Rn], $Xm",
8025 (!cast<Instruction>(NAME # "v" # layout # "_POST")
8027 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
8028 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8031 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
8032 int Offset1, int Offset2, int Offset4, int Offset8> {
8033 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
8034 !cast<Operand>("VecList" # Count # "8b")>;
8035 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
8036 !cast<Operand>("VecList" # Count #"16b")>;
8037 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
8038 !cast<Operand>("VecList" # Count #"4h")>;
8039 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
8040 !cast<Operand>("VecList" # Count #"8h")>;
8041 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
8042 !cast<Operand>("VecList" # Count #"2s")>;
8043 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
8044 !cast<Operand>("VecList" # Count #"4s")>;
8045 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
8046 !cast<Operand>("VecList" # Count #"1d")>;
8047 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
8048 !cast<Operand>("VecList" # Count #"2d")>;
8050 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
8051 !cast<Operand>("VecList" # Count # "8b"),
8052 !cast<Operand>("GPR64pi" # Offset1)>;
8053 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
8054 !cast<Operand>("VecList" # Count # "16b"),
8055 !cast<Operand>("GPR64pi" # Offset1)>;
8056 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
8057 !cast<Operand>("VecList" # Count # "4h"),
8058 !cast<Operand>("GPR64pi" # Offset2)>;
8059 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
8060 !cast<Operand>("VecList" # Count # "8h"),
8061 !cast<Operand>("GPR64pi" # Offset2)>;
8062 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
8063 !cast<Operand>("VecList" # Count # "2s"),
8064 !cast<Operand>("GPR64pi" # Offset4)>;
8065 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
8066 !cast<Operand>("VecList" # Count # "4s"),
8067 !cast<Operand>("GPR64pi" # Offset4)>;
8068 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
8069 !cast<Operand>("VecList" # Count # "1d"),
8070 !cast<Operand>("GPR64pi" # Offset8)>;
8071 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
8072 !cast<Operand>("VecList" # Count # "2d"),
8073 !cast<Operand>("GPR64pi" # Offset8)>;
8075 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
8076 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
8077 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
8078 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
8079 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
8080 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
8081 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
8082 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
8085 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
8086 dag oops, dag iops, list<dag> pattern>
8087 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8089 // idx encoded in Q:S:size fields.
8091 let Inst{30} = idx{3};
8093 let Inst{20-16} = 0b00000;
8094 let Inst{12} = idx{2};
8095 let Inst{11-10} = idx{1-0};
8097 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
8098 dag oops, dag iops, list<dag> pattern>
8099 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8100 oops, iops, pattern> {
8101 // idx encoded in Q:S:size fields.
8103 let Inst{30} = idx{3};
8105 let Inst{20-16} = 0b00000;
8106 let Inst{12} = idx{2};
8107 let Inst{11-10} = idx{1-0};
8109 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
8111 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8112 "$Rn = $wback", oops, iops, []> {
8113 // idx encoded in Q:S:size fields.
8116 let Inst{30} = idx{3};
8118 let Inst{20-16} = Xm;
8119 let Inst{12} = idx{2};
8120 let Inst{11-10} = idx{1-0};
8122 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
8124 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8125 "$Rn = $wback", oops, iops, []> {
8126 // idx encoded in Q:S:size fields.
8129 let Inst{30} = idx{3};
8131 let Inst{20-16} = Xm;
8132 let Inst{12} = idx{2};
8133 let Inst{11-10} = idx{1-0};
8136 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8137 dag oops, dag iops, list<dag> pattern>
8138 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8140 // idx encoded in Q:S:size<1> fields.
8142 let Inst{30} = idx{2};
8144 let Inst{20-16} = 0b00000;
8145 let Inst{12} = idx{1};
8146 let Inst{11} = idx{0};
8147 let Inst{10} = size;
8149 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8150 dag oops, dag iops, list<dag> pattern>
8151 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8152 oops, iops, pattern> {
8153 // idx encoded in Q:S:size<1> fields.
8155 let Inst{30} = idx{2};
8157 let Inst{20-16} = 0b00000;
8158 let Inst{12} = idx{1};
8159 let Inst{11} = idx{0};
8160 let Inst{10} = size;
8163 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8165 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8166 "$Rn = $wback", oops, iops, []> {
8167 // idx encoded in Q:S:size<1> fields.
8170 let Inst{30} = idx{2};
8172 let Inst{20-16} = Xm;
8173 let Inst{12} = idx{1};
8174 let Inst{11} = idx{0};
8175 let Inst{10} = size;
8177 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8179 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8180 "$Rn = $wback", oops, iops, []> {
8181 // idx encoded in Q:S:size<1> fields.
8184 let Inst{30} = idx{2};
8186 let Inst{20-16} = Xm;
8187 let Inst{12} = idx{1};
8188 let Inst{11} = idx{0};
8189 let Inst{10} = size;
8191 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8192 dag oops, dag iops, list<dag> pattern>
8193 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8195 // idx encoded in Q:S fields.
8197 let Inst{30} = idx{1};
8199 let Inst{20-16} = 0b00000;
8200 let Inst{12} = idx{0};
8201 let Inst{11-10} = size;
8203 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8204 dag oops, dag iops, list<dag> pattern>
8205 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8206 oops, iops, pattern> {
8207 // idx encoded in Q:S fields.
8209 let Inst{30} = idx{1};
8211 let Inst{20-16} = 0b00000;
8212 let Inst{12} = idx{0};
8213 let Inst{11-10} = size;
8215 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8216 string asm, dag oops, dag iops>
8217 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8218 "$Rn = $wback", oops, iops, []> {
8219 // idx encoded in Q:S fields.
8222 let Inst{30} = idx{1};
8224 let Inst{20-16} = Xm;
8225 let Inst{12} = idx{0};
8226 let Inst{11-10} = size;
8228 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8229 string asm, dag oops, dag iops>
8230 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8231 "$Rn = $wback", oops, iops, []> {
8232 // idx encoded in Q:S fields.
8235 let Inst{30} = idx{1};
8237 let Inst{20-16} = Xm;
8238 let Inst{12} = idx{0};
8239 let Inst{11-10} = size;
8241 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8242 dag oops, dag iops, list<dag> pattern>
8243 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "", oops, iops,
8245 // idx encoded in Q field.
8249 let Inst{20-16} = 0b00000;
8251 let Inst{11-10} = size;
8253 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8254 dag oops, dag iops, list<dag> pattern>
8255 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn]", "",
8256 oops, iops, pattern> {
8257 // idx encoded in Q field.
8261 let Inst{20-16} = 0b00000;
8263 let Inst{11-10} = size;
8265 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8266 string asm, dag oops, dag iops>
8267 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8268 "$Rn = $wback", oops, iops, []> {
8269 // idx encoded in Q field.
8274 let Inst{20-16} = Xm;
8276 let Inst{11-10} = size;
8278 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8279 string asm, dag oops, dag iops>
8280 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, [$Rn], $Xm",
8281 "$Rn = $wback", oops, iops, []> {
8282 // idx encoded in Q field.
8287 let Inst{20-16} = Xm;
8289 let Inst{11-10} = size;
8292 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8293 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8294 RegisterOperand listtype,
8295 RegisterOperand GPR64pi> {
8296 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8297 (outs listtype:$dst),
8298 (ins listtype:$Vt, VectorIndexB:$idx,
8301 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8302 (outs GPR64sp:$wback, listtype:$dst),
8303 (ins listtype:$Vt, VectorIndexB:$idx,
8304 GPR64sp:$Rn, GPR64pi:$Xm)>;
8306 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8307 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8308 RegisterOperand listtype,
8309 RegisterOperand GPR64pi> {
8310 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8311 (outs listtype:$dst),
8312 (ins listtype:$Vt, VectorIndexH:$idx,
8315 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8316 (outs GPR64sp:$wback, listtype:$dst),
8317 (ins listtype:$Vt, VectorIndexH:$idx,
8318 GPR64sp:$Rn, GPR64pi:$Xm)>;
8320 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8321 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8322 RegisterOperand listtype,
8323 RegisterOperand GPR64pi> {
8324 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8325 (outs listtype:$dst),
8326 (ins listtype:$Vt, VectorIndexS:$idx,
8329 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8330 (outs GPR64sp:$wback, listtype:$dst),
8331 (ins listtype:$Vt, VectorIndexS:$idx,
8332 GPR64sp:$Rn, GPR64pi:$Xm)>;
8334 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8335 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8336 RegisterOperand listtype, RegisterOperand GPR64pi> {
8337 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8338 (outs listtype:$dst),
8339 (ins listtype:$Vt, VectorIndexD:$idx,
8342 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8343 (outs GPR64sp:$wback, listtype:$dst),
8344 (ins listtype:$Vt, VectorIndexD:$idx,
8345 GPR64sp:$Rn, GPR64pi:$Xm)>;
8347 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8348 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8349 RegisterOperand listtype, RegisterOperand GPR64pi> {
8350 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8351 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8354 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8355 (outs GPR64sp:$wback),
8356 (ins listtype:$Vt, VectorIndexB:$idx,
8357 GPR64sp:$Rn, GPR64pi:$Xm)>;
8359 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8360 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8361 RegisterOperand listtype, RegisterOperand GPR64pi> {
8362 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8363 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8366 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8367 (outs GPR64sp:$wback),
8368 (ins listtype:$Vt, VectorIndexH:$idx,
8369 GPR64sp:$Rn, GPR64pi:$Xm)>;
8371 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8372 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8373 RegisterOperand listtype, RegisterOperand GPR64pi> {
8374 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8375 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8378 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8379 (outs GPR64sp:$wback),
8380 (ins listtype:$Vt, VectorIndexS:$idx,
8381 GPR64sp:$Rn, GPR64pi:$Xm)>;
8383 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8384 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8385 RegisterOperand listtype, RegisterOperand GPR64pi> {
8386 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8387 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8390 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8391 (outs GPR64sp:$wback),
8392 (ins listtype:$Vt, VectorIndexD:$idx,
8393 GPR64sp:$Rn, GPR64pi:$Xm)>;
8396 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8397 string Count, int Offset, Operand idxtype> {
8398 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8399 // "ld1\t$Vt, [$Rn], #1"
8400 // may get mapped to
8401 // (LD1Rv8b_POST VecListOne8b:$Vt, GPR64sp:$Rn, XZR)
8402 def : InstAlias<asm # "\t$Vt$idx, [$Rn], #" # Offset,
8403 (!cast<Instruction>(NAME # Type # "_POST")
8405 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8406 idxtype:$idx, XZR), 1>;
8408 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8409 // "ld1.8b\t$Vt, [$Rn], #1"
8410 // may get mapped to
8411 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, XZR)
8412 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], #" # Offset,
8413 (!cast<Instruction>(NAME # Type # "_POST")
8415 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8416 idxtype:$idx, XZR), 0>;
8418 // E.g. "ld1.8b { v0 }[0], [x1]"
8419 // "ld1.8b\t$Vt, [$Rn]"
8420 // may get mapped to
8421 // (LD1Rv8b VecListOne64:$Vt, GPR64sp:$Rn)
8422 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn]",
8423 (!cast<Instruction>(NAME # Type)
8424 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8425 idxtype:$idx, GPR64sp:$Rn), 0>;
8427 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8428 // "ld1.8b\t$Vt, [$Rn], $Xm"
8429 // may get mapped to
8430 // (LD1Rv8b_POST VecListOne64:$Vt, GPR64sp:$Rn, GPR64pi1:$Xm)
8431 def : InstAlias<asm # "." # layout # "\t$Vt$idx, [$Rn], $Xm",
8432 (!cast<Instruction>(NAME # Type # "_POST")
8434 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8436 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8439 multiclass SIMDLdSt1SingleAliases<string asm> {
8440 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8441 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8442 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8443 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8446 multiclass SIMDLdSt2SingleAliases<string asm> {
8447 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8448 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8449 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8450 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8453 multiclass SIMDLdSt3SingleAliases<string asm> {
8454 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8455 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8456 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8457 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8460 multiclass SIMDLdSt4SingleAliases<string asm> {
8461 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8462 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8463 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8464 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8466 } // end of 'let Predicates = [HasNEON]'
8468 //----------------------------------------------------------------------------
8469 // Crypto extensions
8470 //----------------------------------------------------------------------------
8472 let Predicates = [HasCrypto] in {
8473 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8474 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8476 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8480 let Inst{31-16} = 0b0100111000101000;
8481 let Inst{15-12} = opc;
8482 let Inst{11-10} = 0b10;
8487 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8488 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8489 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8491 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8492 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8494 [(set (v16i8 V128:$dst),
8495 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8497 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8498 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8499 dag oops, dag iops, list<dag> pat>
8500 : I<oops, iops, asm,
8501 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8502 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8507 let Inst{31-21} = 0b01011110000;
8508 let Inst{20-16} = Rm;
8510 let Inst{14-12} = opc;
8511 let Inst{11-10} = 0b00;
8516 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8517 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8518 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8519 [(set (v4i32 FPR128:$dst),
8520 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8521 (v4i32 V128:$Rm)))]>;
8523 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8524 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8525 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8526 [(set (v4i32 V128:$dst),
8527 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8528 (v4i32 V128:$Rm)))]>;
8530 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8531 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8532 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8533 [(set (v4i32 FPR128:$dst),
8534 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8535 (v4i32 V128:$Rm)))]>;
8537 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8538 class SHA2OpInst<bits<4> opc, string asm, string kind,
8539 string cstr, dag oops, dag iops,
8541 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8542 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8546 let Inst{31-16} = 0b0101111000101000;
8547 let Inst{15-12} = opc;
8548 let Inst{11-10} = 0b10;
8553 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8554 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8555 (ins V128:$Rd, V128:$Rn),
8556 [(set (v4i32 V128:$dst),
8557 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8559 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8560 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8561 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8562 } // end of 'let Predicates = [HasCrypto]'
8564 // Allow the size specifier tokens to be upper case, not just lower.
8565 def : TokenAlias<".8B", ".8b">;
8566 def : TokenAlias<".4H", ".4h">;
8567 def : TokenAlias<".2S", ".2s">;
8568 def : TokenAlias<".1D", ".1d">;
8569 def : TokenAlias<".16B", ".16b">;
8570 def : TokenAlias<".8H", ".8h">;
8571 def : TokenAlias<".4S", ".4s">;
8572 def : TokenAlias<".2D", ".2d">;
8573 def : TokenAlias<".1Q", ".1q">;
8574 def : TokenAlias<".B", ".b">;
8575 def : TokenAlias<".H", ".h">;
8576 def : TokenAlias<".S", ".s">;
8577 def : TokenAlias<".D", ".d">;
8578 def : TokenAlias<".Q", ".q">;