1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that AArch64 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
16 #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/IR/CallingConv.h"
22 #include "llvm/IR/Instruction.h"
23 #include "llvm/Target/TargetLowering.h"
27 namespace AArch64ISD {
29 enum NodeType : unsigned {
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
32 CALL, // Function call.
34 // Produces the full sequence of instructions for getting the thread pointer
35 // offset of a variable into X0, using the TLSDesc model.
37 ADRP, // Page address of a TargetGlobalAddress operand.
38 ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
39 LOADgot, // Load from automatically generated descriptor (e.g. Global
40 // Offset Table, TLS record).
41 RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
42 BRCOND, // Conditional branch instruction; "b.cond".
44 FCSEL, // Conditional move instruction.
45 CSINV, // Conditional select invert.
46 CSNEG, // Conditional select negate.
47 CSINC, // Conditional select increment.
49 // Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
53 SBC, // adc, sbc instructions
55 // Arithmetic instructions which write flags.
62 // Conditional compares. Operands: left,right,falsecc,cc,flags
67 // Floating point comparison
73 // Scalar-to-vector duplication
80 // Vector immedate moves
89 // Vector immediate ops
93 // Vector bit select: similar to ISD::VSELECT but not all bits within an
94 // element must be identical.
97 // Vector arithmetic negation
112 // Vector shift by scalar
117 // Vector shift by scalar (again)
124 // Vector comparisons
134 // Vector zero comparisons
146 // Vector across-lanes addition
147 // Only the lower result lane is defined.
151 // Vector across-lanes min/max
152 // Only the lower result lane is defined.
158 // Vector bitwise negation
161 // Vector bitwise selection
164 // Compare-and-branch
173 // Custom prefetch handling
176 // {s|u}int to FP within a FP register.
180 /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
181 /// world w.r.t vectors; which causes additional REV instructions to be
182 /// generated to compensate for the byte-swapping. But sometimes we do
183 /// need to re-interpret the data in SIMD vector registers in big-endian
184 /// mode without emitting such REV instructions.
190 // NEON Load/Store with post-increment base updates
191 LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
216 } // end namespace AArch64ISD
218 class AArch64Subtarget;
219 class AArch64TargetMachine;
221 class AArch64TargetLowering : public TargetLowering {
223 explicit AArch64TargetLowering(const TargetMachine &TM,
224 const AArch64Subtarget &STI);
226 /// Selects the correct CCAssignFn for a given CallingConvention value.
227 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
229 /// computeKnownBitsForTargetNode - Determine which of the bits specified in
230 /// Mask are known to be either zero or one and return them in the
231 /// KnownZero/KnownOne bitsets.
232 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
233 APInt &KnownOne, const SelectionDAG &DAG,
234 unsigned Depth = 0) const override;
236 MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
238 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
239 /// unaligned memory accesses of the specified type.
240 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
242 bool *Fast = nullptr) const override;
244 /// LowerOperation - Provide custom lowering hooks for some operations.
245 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
247 const char *getTargetNodeName(unsigned Opcode) const override;
249 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
251 /// getFunctionAlignment - Return the Log2 alignment of this function.
252 unsigned getFunctionAlignment(const Function *F) const;
254 /// Returns true if a cast between SrcAS and DestAS is a noop.
255 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
256 // Addrspacecasts are always noops.
260 /// createFastISel - This method returns a target specific FastISel object,
261 /// or null if the target does not support "fast" ISel.
262 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
263 const TargetLibraryInfo *libInfo) const override;
265 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
267 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
269 /// isShuffleMaskLegal - Return true if the given shuffle mask can be
270 /// codegen'd directly, or if it should be stack expanded.
271 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
273 /// getSetCCResultType - Return the ISD::SETCC ValueType
274 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
275 EVT VT) const override;
277 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
279 MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
280 MachineBasicBlock *BB) const;
283 EmitInstrWithCustomInserter(MachineInstr *MI,
284 MachineBasicBlock *MBB) const override;
286 bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
287 unsigned Intrinsic) const override;
289 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
290 bool isTruncateFree(EVT VT1, EVT VT2) const override;
292 bool isProfitableToHoist(Instruction *I) const override;
294 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
295 bool isZExtFree(EVT VT1, EVT VT2) const override;
296 bool isZExtFree(SDValue Val, EVT VT2) const override;
298 bool hasPairedLoad(Type *LoadedType,
299 unsigned &RequiredAligment) const override;
300 bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
302 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
304 bool lowerInterleavedLoad(LoadInst *LI,
305 ArrayRef<ShuffleVectorInst *> Shuffles,
306 ArrayRef<unsigned> Indices,
307 unsigned Factor) const override;
308 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
309 unsigned Factor) const override;
311 bool isLegalAddImmediate(int64_t) const override;
312 bool isLegalICmpImmediate(int64_t) const override;
314 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
315 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
316 MachineFunction &MF) const override;
318 /// isLegalAddressingMode - Return true if the addressing mode represented
319 /// by AM is legal for this target, for a load/store of the specified type.
320 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
321 unsigned AS) const override;
323 /// \brief Return the cost of the scaling factor used in the addressing
324 /// mode represented by AM for this target, for a load/store
325 /// of the specified type.
326 /// If the AM is supported, the return value must be >= 0.
327 /// If the AM is not supported, it returns a negative value.
328 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
329 unsigned AS) const override;
331 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
332 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
333 /// expanded to FMAs when this method returns true, otherwise fmuladd is
334 /// expanded to fmul + fadd.
335 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
337 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
339 /// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
340 bool isDesirableToCommuteWithShift(const SDNode *N) const override;
342 /// \brief Returns true if it is beneficial to convert a load of a constant
343 /// to just the constant itself.
344 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
345 Type *Ty) const override;
347 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
348 AtomicOrdering Ord) const override;
349 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
350 Value *Addr, AtomicOrdering Ord) const override;
352 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
354 TargetLoweringBase::AtomicExpansionKind
355 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
356 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
357 TargetLoweringBase::AtomicExpansionKind
358 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
360 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
362 bool useLoadStackGuardNode() const override;
363 TargetLoweringBase::LegalizeTypeAction
364 getPreferredVectorAction(EVT VT) const override;
366 /// If the target has a standard location for the unsafe stack pointer,
367 /// returns the address of that location. Otherwise, returns nullptr.
368 Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
370 /// If a physical register, this returns the register that receives the
371 /// exception address on entry to an EH pad.
373 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
374 // FIXME: This is a guess. Has this been defined yet?
378 /// If a physical register, this returns the register that receives the
379 /// exception typeid on entry to a landing pad.
381 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
382 // FIXME: This is a guess. Has this been defined yet?
387 bool isExtFreeImpl(const Instruction *Ext) const override;
389 /// Subtarget - Keep a pointer to the AArch64Subtarget around so that we can
390 /// make the right decision when generating code for different targets.
391 const AArch64Subtarget *Subtarget;
393 void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
394 void addDRTypeForNEON(MVT VT);
395 void addQRTypeForNEON(MVT VT);
398 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
399 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
401 SmallVectorImpl<SDValue> &InVals) const override;
403 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
404 SmallVectorImpl<SDValue> &InVals) const override;
406 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
407 CallingConv::ID CallConv, bool isVarArg,
408 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
409 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
410 bool isThisReturn, SDValue ThisVal) const;
412 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
414 bool isEligibleForTailCallOptimization(
415 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
416 bool isCalleeStructRet, bool isCallerStructRet,
417 const SmallVectorImpl<ISD::OutputArg> &Outs,
418 const SmallVectorImpl<SDValue> &OutVals,
419 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
421 /// Finds the incoming stack arguments which overlap the given fixed stack
422 /// object and incorporates their load into the current chain. This prevents
423 /// an upcoming store from clobbering the stack argument before it's used.
424 SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
425 MachineFrameInfo *MFI, int ClobberedFI) const;
427 bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
429 bool IsTailCallConvention(CallingConv::ID CallCC) const;
431 void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
432 SDValue &Chain) const;
434 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
436 const SmallVectorImpl<ISD::OutputArg> &Outs,
437 LLVMContext &Context) const override;
439 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
440 const SmallVectorImpl<ISD::OutputArg> &Outs,
441 const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
442 SelectionDAG &DAG) const override;
444 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
445 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
446 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
447 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
448 SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
449 SelectionDAG &DAG) const;
450 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
451 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
452 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
453 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
454 SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
455 SDValue TVal, SDValue FVal, SDLoc dl,
456 SelectionDAG &DAG) const;
457 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
458 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
459 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
460 SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
462 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
463 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
464 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
465 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
466 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
467 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
468 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
469 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
470 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
471 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
472 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
473 SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
474 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
475 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
476 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
479 RTLIB::Libcall Call) const;
480 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
488 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
490 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
491 std::vector<SDNode *> *Created) const override;
492 unsigned combineRepeatedFPDivisors() const override;
494 ConstraintType getConstraintType(StringRef Constraint) const override;
495 unsigned getRegisterByName(const char* RegName, EVT VT,
496 SelectionDAG &DAG) const override;
498 /// Examine constraint string and operand type and determine a weight value.
499 /// The operand object must already have been set up with the operand type.
501 getSingleConstraintMatchWeight(AsmOperandInfo &info,
502 const char *constraint) const override;
504 std::pair<unsigned, const TargetRegisterClass *>
505 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
506 StringRef Constraint, MVT VT) const override;
507 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
508 std::vector<SDValue> &Ops,
509 SelectionDAG &DAG) const override;
511 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
512 if (ConstraintCode == "Q")
513 return InlineAsm::Constraint_Q;
514 // FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
515 // followed by llvm_unreachable so we'll leave them unimplemented in
516 // the backend for now.
517 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
520 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
521 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
522 bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
523 ISD::MemIndexedMode &AM, bool &IsInc,
524 SelectionDAG &DAG) const;
525 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
526 ISD::MemIndexedMode &AM,
527 SelectionDAG &DAG) const override;
528 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
529 SDValue &Offset, ISD::MemIndexedMode &AM,
530 SelectionDAG &DAG) const override;
532 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
533 SelectionDAG &DAG) const override;
535 bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
536 CallingConv::ID CallConv,
537 bool isVarArg) const override;
539 bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
543 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
544 const TargetLibraryInfo *libInfo);
545 } // end namespace AArch64
547 } // end namespace llvm