1 //===-- AArch64AsmPrinter.cpp - Print machine code to an AArch64 .s file --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format AArch64 assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
16 #include "AArch64AsmPrinter.h"
17 #include "InstPrinter/AArch64InstPrinter.h"
18 #include "llvm/DebugInfo.h"
19 #include "llvm/ADT/SmallString.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/MC/MCAsmInfo.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCSymbol.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Target/Mangler.h"
32 AArch64AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
33 // See emitFrameIndexDebugValue in InstrInfo for where this instruction is
34 // expected to be created.
35 assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg()
36 && MI->getOperand(1).isImm() && "unexpected custom DBG_VALUE");
37 return MachineLocation(MI->getOperand(0).getReg(),
38 MI->getOperand(1).getImm());
41 /// Try to print a floating-point register as if it belonged to a specified
42 /// register-class. For example the inline asm operand modifier "b" requires its
43 /// argument to be printed as "bN".
44 static bool printModifiedFPRAsmOperand(const MachineOperand &MO,
45 const TargetRegisterInfo *TRI,
46 const TargetRegisterClass &RegClass,
51 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
52 if (RegClass.contains(*AR)) {
53 O << AArch64InstPrinter::getRegisterName(*AR);
60 /// Implements the 'w' and 'x' inline asm operand modifiers, which print a GPR
61 /// with the obvious type and an immediate 0 as either wzr or xzr.
62 static bool printModifiedGPRAsmOperand(const MachineOperand &MO,
63 const TargetRegisterInfo *TRI,
64 const TargetRegisterClass &RegClass,
66 char Prefix = &RegClass == &AArch64::GPR32RegClass ? 'w' : 'x';
68 if (MO.isImm() && MO.getImm() == 0) {
71 } else if (MO.isReg()) {
72 if (MO.getReg() == AArch64::XSP || MO.getReg() == AArch64::WSP) {
73 O << (Prefix == 'x' ? "sp" : "wsp");
77 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) {
78 if (RegClass.contains(*AR)) {
79 O << AArch64InstPrinter::getRegisterName(*AR);
88 bool AArch64AsmPrinter::printSymbolicAddress(const MachineOperand &MO,
89 bool PrintImmediatePrefix,
90 StringRef Suffix, raw_ostream &O) {
93 switch (MO.getType()) {
95 llvm_unreachable("Unexpected operand for symbolic address constraint");
96 case MachineOperand::MO_GlobalAddress:
97 Name = Mang->getSymbol(MO.getGlobal())->getName();
99 // Global variables may be accessed either via a GOT or in various fun and
100 // interesting TLS-model specific ways. Set the prefix modifier as
102 if (const GlobalVariable *GV = dyn_cast<GlobalVariable>(MO.getGlobal())) {
103 Reloc::Model RelocM = TM.getRelocationModel();
104 if (GV->isThreadLocal()) {
105 switch (TM.getTLSModel(GV)) {
106 case TLSModel::GeneralDynamic:
107 Modifier = "tlsdesc";
109 case TLSModel::LocalDynamic:
112 case TLSModel::InitialExec:
113 Modifier = "gottprel";
115 case TLSModel::LocalExec:
119 } else if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
124 case MachineOperand::MO_BlockAddress:
125 Name = GetBlockAddressSymbol(MO.getBlockAddress())->getName();
127 case MachineOperand::MO_ExternalSymbol:
128 Name = MO.getSymbolName();
130 case MachineOperand::MO_ConstantPoolIndex:
131 Name = GetCPISymbol(MO.getIndex())->getName();
135 // Some instructions (notably ADRP) don't take the # prefix for
136 // immediates. Only print it if asked to.
137 if (PrintImmediatePrefix)
140 // Only need the joining "_" if both the prefix and the suffix are
141 // non-null. This little block simply takes care of the four possibly
142 // combinations involved there.
143 if (Modifier == "" && Suffix == "")
145 else if (Modifier == "" && Suffix != "")
146 O << ":" << Suffix << ':' << Name;
147 else if (Modifier != "" && Suffix == "")
148 O << ":" << Modifier << ':' << Name;
150 O << ":" << Modifier << '_' << Suffix << ':' << Name;
155 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 const char *ExtraCode, raw_ostream &O) {
158 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
159 if (!ExtraCode || !ExtraCode[0]) {
160 // There's actually no operand modifier, which leads to a slightly eclectic
161 // set of behaviour which we have to handle here.
162 const MachineOperand &MO = MI->getOperand(OpNum);
163 switch (MO.getType()) {
165 llvm_unreachable("Unexpected operand for inline assembly");
166 case MachineOperand::MO_Register:
167 // GCC prints the unmodified operand of a 'w' constraint as the vector
168 // register. Technically, we could allocate the argument as a VPR128, but
169 // that leads to extremely dodgy copies being generated to get the data
171 if (printModifiedFPRAsmOperand(MO, TRI, AArch64::VPR128RegClass, O))
172 O << AArch64InstPrinter::getRegisterName(MO.getReg());
174 case MachineOperand::MO_Immediate:
175 O << '#' << MO.getImm();
177 case MachineOperand::MO_FPImmediate:
178 assert(MO.getFPImm()->isExactlyValue(0.0) && "Only FP 0.0 expected");
181 case MachineOperand::MO_BlockAddress:
182 case MachineOperand::MO_ConstantPoolIndex:
183 case MachineOperand::MO_GlobalAddress:
184 case MachineOperand::MO_ExternalSymbol:
185 return printSymbolicAddress(MO, false, "", O);
190 // We have a real modifier to handle.
191 switch(ExtraCode[0]) {
193 // See if this is a generic operand
194 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
195 case 'c': // Don't print "#" before an immediate operand.
196 if (!MI->getOperand(OpNum).isImm())
198 O << MI->getOperand(OpNum).getImm();
201 // Output 32-bit general register operand, constant zero as wzr, or stack
202 // pointer as wsp. Ignored when used with other operand types.
203 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
204 AArch64::GPR32RegClass, O);
206 // Output 64-bit general register operand, constant zero as xzr, or stack
207 // pointer as sp. Ignored when used with other operand types.
208 return printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI,
209 AArch64::GPR64RegClass, O);
211 // Output higher numbered of a 64-bit general register pair
213 // Output least significant register of a 64-bit general register pair
215 // Output most significant register of a 64-bit general register pair
217 // FIXME note: these three operand modifiers will require, to some extent,
218 // adding a paired GPR64 register class. Initial investigation suggests that
219 // assertions are hit unless it has a type and is made legal for that type
220 // in ISelLowering. After that step is made, the number of modifications
221 // needed explodes (operation legality, calling conventions, stores, reg
223 llvm_unreachable("FIXME: Unimplemented register pairs");
225 // Output 8-bit FP/SIMD scalar register operand, prefixed with b.
226 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
227 AArch64::FPR8RegClass, O);
229 // Output 16-bit FP/SIMD scalar register operand, prefixed with h.
230 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
231 AArch64::FPR16RegClass, O);
233 // Output 32-bit FP/SIMD scalar register operand, prefixed with s.
234 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
235 AArch64::FPR32RegClass, O);
237 // Output 64-bit FP/SIMD scalar register operand, prefixed with d.
238 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
239 AArch64::FPR64RegClass, O);
241 // Output 128-bit FP/SIMD scalar register operand, prefixed with q.
242 return printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI,
243 AArch64::FPR128RegClass, O);
245 // Output symbolic address with appropriate relocation modifier (also
246 // suitable for ADRP).
247 return printSymbolicAddress(MI->getOperand(OpNum), false, "", O);
249 // Output bits 11:0 of symbolic address with appropriate :lo12: relocation
251 return printSymbolicAddress(MI->getOperand(OpNum), true, "lo12", O);
253 // Output bits 23:12 of symbolic address with appropriate :hi12: relocation
254 // modifier (currently only for TLS local exec).
255 return printSymbolicAddress(MI->getOperand(OpNum), true, "hi12", O);
261 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
264 const char *ExtraCode,
266 // Currently both the memory constraints (m and Q) behave the same and amount
267 // to the address as a single register. In future, we may allow "m" to provide
268 // both a base and an offset.
269 const MachineOperand &MO = MI->getOperand(OpNum);
270 assert(MO.isReg() && "unexpected inline assembly memory operand");
271 O << '[' << AArch64InstPrinter::getRegisterName(MO.getReg()) << ']';
275 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
277 unsigned NOps = MI->getNumOperands();
279 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
280 // cast away const; DIetc do not take const operands for some reason.
281 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
284 // Frame address. Currently handles register +- offset only.
285 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
286 OS << '[' << AArch64InstPrinter::getRegisterName(MI->getOperand(0).getReg());
287 OS << '+' << MI->getOperand(1).getImm();
289 OS << "+" << MI->getOperand(NOps - 2).getImm();
293 #include "AArch64GenMCPseudoLowering.inc"
295 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
296 // Do any auto-generated pseudo lowerings.
297 if (emitPseudoExpansionLowering(OutStreamer, MI))
300 switch (MI->getOpcode()) {
301 case AArch64::CONSTPOOL_ENTRY: {
302 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
303 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
305 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
307 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
308 if (MCPE.isMachineConstantPoolEntry())
309 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
311 EmitGlobalConstant(MCPE.Val.ConstVal);
315 case AArch64::DBG_VALUE: {
316 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
317 SmallString<128> TmpStr;
318 raw_svector_ostream OS(TmpStr);
319 PrintDebugValueComment(MI, OS);
320 OutStreamer.EmitRawText(StringRef(OS.str()));
327 LowerAArch64MachineInstrToMCInst(MI, TmpInst, *this);
328 OutStreamer.EmitInstruction(TmpInst);
331 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
332 if (Subtarget->isTargetELF()) {
333 const TargetLoweringObjectFileELF &TLOFELF =
334 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
336 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
338 // Output stubs for external and common global variables.
339 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
340 if (!Stubs.empty()) {
341 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
342 const DataLayout *TD = TM.getDataLayout();
344 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
345 OutStreamer.EmitLabel(Stubs[i].first);
346 OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
347 TD->getPointerSize(0), 0);
354 bool AArch64AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
355 MCP = MF.getConstantPool();
356 return AsmPrinter::runOnMachineFunction(MF);
359 // Force static initialization.
360 extern "C" void LLVMInitializeAArch64AsmPrinter() {
361 RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64Target);