1 //===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to the AArch64 assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "MCTargetDesc/AArch64AddressingModes.h"
16 #include "MCTargetDesc/AArch64MCExpr.h"
18 #include "AArch64MCInstLower.h"
19 #include "AArch64MachineFunctionInfo.h"
20 #include "AArch64RegisterInfo.h"
21 #include "AArch64Subtarget.h"
22 #include "InstPrinter/AArch64InstPrinter.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/ADT/StringSwitch.h"
25 #include "llvm/ADT/Twine.h"
26 #include "llvm/CodeGen/AsmPrinter.h"
27 #include "llvm/CodeGen/MachineInstr.h"
28 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
29 #include "llvm/CodeGen/StackMaps.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 #include "llvm/IR/DataLayout.h"
32 #include "llvm/IR/DebugInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCInstBuilder.h"
37 #include "llvm/MC/MCLinkerOptimizationHint.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSymbol.h"
40 #include "llvm/Support/Debug.h"
41 #include "llvm/Support/TargetRegistry.h"
44 #define DEBUG_TYPE "asm-printer"
48 class AArch64AsmPrinter : public AsmPrinter {
49 AArch64MCInstLower MCInstLowering;
53 AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
54 : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
55 SM(*this), AArch64FI(nullptr) {}
57 const char *getPassName() const override {
58 return "AArch64 Assembly Printer";
61 /// \brief Wrapper for MCInstLowering.lowerOperand() for the
62 /// tblgen'erated pseudo lowering.
63 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
64 return MCInstLowering.lowerOperand(MO, MCOp);
67 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
68 const MachineInstr &MI);
69 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
70 const MachineInstr &MI);
71 /// \brief tblgen'erated driver function for lowering simple MI->MC
72 /// pseudo instructions.
73 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
74 const MachineInstr *MI);
76 void EmitInstruction(const MachineInstr *MI) override;
78 void getAnalysisUsage(AnalysisUsage &AU) const override {
79 AsmPrinter::getAnalysisUsage(AU);
83 bool runOnMachineFunction(MachineFunction &F) override {
84 AArch64FI = F.getInfo<AArch64FunctionInfo>();
85 return AsmPrinter::runOnMachineFunction(F);
89 MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
90 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
91 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
92 bool printAsmRegInClass(const MachineOperand &MO,
93 const TargetRegisterClass *RC, bool isVector,
96 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
97 unsigned AsmVariant, const char *ExtraCode,
98 raw_ostream &O) override;
99 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
100 unsigned AsmVariant, const char *ExtraCode,
101 raw_ostream &O) override;
103 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
105 void EmitFunctionBodyEnd() override;
107 MCSymbol *GetCPISymbol(unsigned CPID) const override;
108 void EmitEndOfAsmFile(Module &M) override;
109 AArch64FunctionInfo *AArch64FI;
111 /// \brief Emit the LOHs contained in AArch64FI.
114 typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
115 MInstToMCSymbol LOHInstToLabel;
118 } // end of anonymous namespace
120 //===----------------------------------------------------------------------===//
122 void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
123 Triple TT(TM.getTargetTriple());
124 if (TT.isOSBinFormatMachO()) {
125 // Funny Darwin hack: This flag tells the linker that no global symbols
126 // contain code that falls through to other global symbols (e.g. the obvious
127 // implementation of multiple entry points). If this doesn't occur, the
128 // linker can safely perform dead code stripping. Since LLVM never
129 // generates code that does this, it is always safe to set.
130 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
131 SM.serializeToStackMapSection();
134 // Emit a .data.rel section containing any stubs that were created.
135 if (TT.isOSBinFormatELF()) {
136 const TargetLoweringObjectFileELF &TLOFELF =
137 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
139 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
141 // Output stubs for external and common global variables.
142 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
143 if (!Stubs.empty()) {
144 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
145 const DataLayout *TD = TM.getDataLayout();
147 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
148 OutStreamer.EmitLabel(Stubs[i].first);
149 OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
150 TD->getPointerSize(0));
159 AArch64AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
160 MachineLocation Location;
161 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
162 // Frame address. Currently handles register +- offset only.
163 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
164 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
166 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
171 void AArch64AsmPrinter::EmitLOHs() {
172 SmallVector<MCSymbol *, 3> MCArgs;
174 for (const auto &D : AArch64FI->getLOHContainer()) {
175 for (const MachineInstr *MI : D.getArgs()) {
176 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
177 assert(LabelIt != LOHInstToLabel.end() &&
178 "Label hasn't been inserted for LOH related instruction");
179 MCArgs.push_back(LabelIt->second);
181 OutStreamer.EmitLOHDirective(D.getKind(), MCArgs);
186 void AArch64AsmPrinter::EmitFunctionBodyEnd() {
187 if (!AArch64FI->getLOHRelated().empty())
191 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
192 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
193 // Darwin uses a linker-private symbol name for constant-pools (to
194 // avoid addends on the relocation?), ELF has no such concept and
195 // uses a normal private symbol.
196 if (getDataLayout().getLinkerPrivateGlobalPrefix()[0])
197 return OutContext.GetOrCreateSymbol(
198 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
199 Twine(getFunctionNumber()) + "_" + Twine(CPID));
201 return OutContext.GetOrCreateSymbol(
202 Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
203 Twine(getFunctionNumber()) + "_" + Twine(CPID));
206 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
208 const MachineOperand &MO = MI->getOperand(OpNum);
209 switch (MO.getType()) {
211 llvm_unreachable("<unknown operand type>");
212 case MachineOperand::MO_Register: {
213 unsigned Reg = MO.getReg();
214 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
215 assert(!MO.getSubReg() && "Subregs should be eliminated!");
216 O << AArch64InstPrinter::getRegisterName(Reg);
219 case MachineOperand::MO_Immediate: {
220 int64_t Imm = MO.getImm();
224 case MachineOperand::MO_GlobalAddress: {
225 const GlobalValue *GV = MO.getGlobal();
226 MCSymbol *Sym = getSymbol(GV);
228 // FIXME: Can we get anything other than a plain symbol here?
229 assert(!MO.getTargetFlags() && "Unknown operand target flag!");
232 printOffset(MO.getOffset(), O);
238 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
240 unsigned Reg = MO.getReg();
243 return true; // Unknown mode.
245 Reg = getWRegFromXReg(Reg);
248 Reg = getXRegFromWReg(Reg);
252 O << AArch64InstPrinter::getRegisterName(Reg);
256 // Prints the register in MO using class RC using the offset in the
257 // new register class. This should not be used for cross class
259 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
260 const TargetRegisterClass *RC,
261 bool isVector, raw_ostream &O) {
262 assert(MO.isReg() && "Should only get here with a register!");
263 const AArch64RegisterInfo *RI =
264 MF->getSubtarget<AArch64Subtarget>().getRegisterInfo();
265 unsigned Reg = MO.getReg();
266 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
267 assert(RI->regsOverlap(RegToPrint, Reg));
268 O << AArch64InstPrinter::getRegisterName(
269 RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
273 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
275 const char *ExtraCode, raw_ostream &O) {
276 const MachineOperand &MO = MI->getOperand(OpNum);
278 // First try the generic code, which knows about modifiers like 'c' and 'n'.
279 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
282 // Does this asm operand have a single letter operand modifier?
283 if (ExtraCode && ExtraCode[0]) {
284 if (ExtraCode[1] != 0)
285 return true; // Unknown modifier.
287 switch (ExtraCode[0]) {
289 return true; // Unknown modifier.
290 case 'w': // Print W register
291 case 'x': // Print X register
293 return printAsmMRegister(MO, ExtraCode[0], O);
294 if (MO.isImm() && MO.getImm() == 0) {
295 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
296 O << AArch64InstPrinter::getRegisterName(Reg);
299 printOperand(MI, OpNum, O);
301 case 'b': // Print B register.
302 case 'h': // Print H register.
303 case 's': // Print S register.
304 case 'd': // Print D register.
305 case 'q': // Print Q register.
307 const TargetRegisterClass *RC;
308 switch (ExtraCode[0]) {
310 RC = &AArch64::FPR8RegClass;
313 RC = &AArch64::FPR16RegClass;
316 RC = &AArch64::FPR32RegClass;
319 RC = &AArch64::FPR64RegClass;
322 RC = &AArch64::FPR128RegClass;
327 return printAsmRegInClass(MO, RC, false /* vector */, O);
329 printOperand(MI, OpNum, O);
334 // According to ARM, we should emit x and v registers unless we have a
337 unsigned Reg = MO.getReg();
339 // If this is a w or x register, print an x register.
340 if (AArch64::GPR32allRegClass.contains(Reg) ||
341 AArch64::GPR64allRegClass.contains(Reg))
342 return printAsmMRegister(MO, 'x', O);
344 // If this is a b, h, s, d, or q register, print it as a v register.
345 return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */,
349 printOperand(MI, OpNum, O);
353 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
356 const char *ExtraCode,
358 if (ExtraCode && ExtraCode[0])
359 return true; // Unknown modifier.
361 const MachineOperand &MO = MI->getOperand(OpNum);
362 assert(MO.isReg() && "unexpected inline asm memory operand");
363 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
367 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
369 unsigned NOps = MI->getNumOperands();
371 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
372 // cast away const; DIetc do not take const operands for some reason.
373 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps - 1).getMetadata()));
376 // Frame address. Currently handles register +- offset only.
377 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
379 printOperand(MI, 0, OS);
381 printOperand(MI, 1, OS);
384 printOperand(MI, NOps - 2, OS);
387 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
388 const MachineInstr &MI) {
389 unsigned NumNOPBytes = MI.getOperand(1).getImm();
391 SM.recordStackMap(MI);
392 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
394 // Scan ahead to trim the shadow.
395 const MachineBasicBlock &MBB = *MI.getParent();
396 MachineBasicBlock::const_iterator MII(MI);
398 while (NumNOPBytes > 0) {
399 if (MII == MBB.end() || MII->isCall() ||
400 MII->getOpcode() == AArch64::DBG_VALUE ||
401 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
402 MII->getOpcode() == TargetOpcode::STACKMAP)
409 for (unsigned i = 0; i < NumNOPBytes; i += 4)
410 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
413 // Lower a patchpoint of the form:
414 // [<def>], <id>, <numBytes>, <target>, <numArgs>
415 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
416 const MachineInstr &MI) {
417 SM.recordPatchPoint(MI);
419 PatchPointOpers Opers(&MI);
421 int64_t CallTarget = Opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
422 unsigned EncodedBytes = 0;
424 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
425 "High 16 bits of call target should be zero.");
426 unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
428 // Materialize the jump address:
429 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZWi)
431 .addImm((CallTarget >> 32) & 0xFFFF)
433 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
436 .addImm((CallTarget >> 16) & 0xFFFF)
438 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
441 .addImm(CallTarget & 0xFFFF)
443 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
446 unsigned NumBytes = Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
447 assert(NumBytes >= EncodedBytes &&
448 "Patchpoint can't request size less than the length of a call.");
449 assert((NumBytes - EncodedBytes) % 4 == 0 &&
450 "Invalid number of NOP bytes requested!");
451 for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
452 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
455 // Simple pseudo-instructions have their lowering (with expansion to real
456 // instructions) auto-generated.
457 #include "AArch64GenMCPseudoLowering.inc"
459 void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
460 // Do any auto-generated pseudo lowerings.
461 if (emitPseudoExpansionLowering(OutStreamer, MI))
464 if (AArch64FI->getLOHRelated().count(MI)) {
465 // Generate a label for LOH related instruction
466 MCSymbol *LOHLabel = createTempSymbol("loh");
467 // Associate the instruction with the label
468 LOHInstToLabel[MI] = LOHLabel;
469 OutStreamer.EmitLabel(LOHLabel);
472 // Do any manual lowerings.
473 switch (MI->getOpcode()) {
476 case AArch64::DBG_VALUE: {
477 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
478 SmallString<128> TmpStr;
479 raw_svector_ostream OS(TmpStr);
480 PrintDebugValueComment(MI, OS);
481 OutStreamer.EmitRawText(StringRef(OS.str()));
486 // Tail calls use pseudo instructions so they have the proper code-gen
487 // attributes (isCall, isReturn, etc.). We lower them to the real
489 case AArch64::TCRETURNri: {
491 TmpInst.setOpcode(AArch64::BR);
492 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
493 EmitToStreamer(OutStreamer, TmpInst);
496 case AArch64::TCRETURNdi: {
498 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
500 TmpInst.setOpcode(AArch64::B);
501 TmpInst.addOperand(Dest);
502 EmitToStreamer(OutStreamer, TmpInst);
505 case AArch64::TLSDESC_CALLSEQ: {
507 /// adrp x0, :tlsdesc:var
508 /// ldr x1, [x0, #:tlsdesc_lo12:var]
509 /// add x0, x0, #:tlsdesc_lo12:var
512 /// (TPIDR_EL0 offset now in x0)
513 const MachineOperand &MO_Sym = MI->getOperand(0);
514 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
515 MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
516 MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |
518 MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
519 MCInstLowering.lowerOperand(MO_Sym, Sym);
520 MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
521 MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
524 Adrp.setOpcode(AArch64::ADRP);
525 Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
526 Adrp.addOperand(SymTLSDesc);
527 EmitToStreamer(OutStreamer, Adrp);
530 Ldr.setOpcode(AArch64::LDRXui);
531 Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
532 Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
533 Ldr.addOperand(SymTLSDescLo12);
534 Ldr.addOperand(MCOperand::CreateImm(0));
535 EmitToStreamer(OutStreamer, Ldr);
538 Add.setOpcode(AArch64::ADDXri);
539 Add.addOperand(MCOperand::CreateReg(AArch64::X0));
540 Add.addOperand(MCOperand::CreateReg(AArch64::X0));
541 Add.addOperand(SymTLSDescLo12);
542 Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
543 EmitToStreamer(OutStreamer, Add);
545 // Emit a relocation-annotation. This expands to no code, but requests
546 // the following instruction gets an R_AARCH64_TLSDESC_CALL.
548 TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
549 TLSDescCall.addOperand(Sym);
550 EmitToStreamer(OutStreamer, TLSDescCall);
553 Blr.setOpcode(AArch64::BLR);
554 Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
555 EmitToStreamer(OutStreamer, Blr);
560 case TargetOpcode::STACKMAP:
561 return LowerSTACKMAP(OutStreamer, SM, *MI);
563 case TargetOpcode::PATCHPOINT:
564 return LowerPATCHPOINT(OutStreamer, SM, *MI);
567 // Finally, do the automated lowerings for everything else.
569 MCInstLowering.Lower(MI, TmpInst);
570 EmitToStreamer(OutStreamer, TmpInst);
573 // Force static initialization.
574 extern "C" void LLVMInitializeAArch64AsmPrinter() {
575 RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget);
576 RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget);
577 RegisterAsmPrinter<AArch64AsmPrinter> Z(TheARM64Target);