Remove extra whitespace. NFC.
[oota-llvm.git] / lib / Target / AArch64 / AArch64.td
1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 //
11 //===----------------------------------------------------------------------===//
12
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
16
17 include "llvm/Target/Target.td"
18
19 //===----------------------------------------------------------------------===//
20 // AArch64 Subtarget features.
21 //
22
23 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
24                                        "Enable ARMv8 FP">;
25
26 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
27   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
28
29 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
30   "Enable cryptographic instructions">;
31
32 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
33   "Enable ARMv8 CRC-32 checksum instructions">;
34
35 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
36   "Enable ARMv8 PMUv3 Performance Monitors extension">;
37
38 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
39   "Full FP16", [FeatureFPARMv8]>;
40
41 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
42   "Enable Statistical Profiling extension">;
43
44 /// Cyclone has register move instructions which are "free".
45 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
46                                         "Has zero-cycle register moves">;
47
48 /// Cyclone has instructions which zero registers for "free".
49 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
50                                         "Has zero-cycle zeroing instructions">;
51
52 def FeatureStrictAlign : SubtargetFeature<"strict-align",
53                                           "StrictAlign", "true",
54                                           "Disallow all unaligned memory "
55                                           "access">;
56
57 def FeatureReserveX18 : SubtargetFeature<"reserve-x18", "ReserveX18", "true",
58                                          "Reserve X18, making it unavailable "
59                                          "as a GPR">;
60
61 //===----------------------------------------------------------------------===//
62 // Architectures.
63 //
64
65 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
66   "Support ARM v8.1a instructions", [FeatureCRC]>;
67
68 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
69   "Support ARM v8.2a instructions", [HasV8_1aOps]>;
70
71 //===----------------------------------------------------------------------===//
72 // Register File Description
73 //===----------------------------------------------------------------------===//
74
75 include "AArch64RegisterInfo.td"
76 include "AArch64CallingConvention.td"
77
78 //===----------------------------------------------------------------------===//
79 // Instruction Descriptions
80 //===----------------------------------------------------------------------===//
81
82 include "AArch64Schedule.td"
83 include "AArch64InstrInfo.td"
84
85 def AArch64InstrInfo : InstrInfo;
86
87 //===----------------------------------------------------------------------===//
88 // AArch64 Processors supported.
89 //
90 include "AArch64SchedA53.td"
91 include "AArch64SchedA57.td"
92 include "AArch64SchedCyclone.td"
93
94 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
95                                    "Cortex-A35 ARM processors",
96                                    [FeatureFPARMv8,
97                                    FeatureNEON,
98                                    FeatureCrypto,
99                                    FeatureCRC,
100                                    FeaturePerfMon]>;
101
102 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
103                                    "Cortex-A53 ARM processors",
104                                    [FeatureFPARMv8,
105                                    FeatureNEON,
106                                    FeatureCrypto,
107                                    FeatureCRC,
108                                    FeaturePerfMon]>;
109
110 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
111                                    "Cortex-A57 ARM processors",
112                                    [FeatureFPARMv8,
113                                    FeatureNEON,
114                                    FeatureCrypto,
115                                    FeatureCRC,
116                                    FeaturePerfMon]>;
117
118 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
119                                    "Cyclone",
120                                    [FeatureFPARMv8,
121                                    FeatureNEON,
122                                    FeatureCrypto,
123                                    FeatureCRC,
124                                    FeaturePerfMon,
125                                    FeatureZCRegMove, FeatureZCZeroing]>;
126
127 def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
128                                               FeatureNEON,
129                                               FeatureCRC,
130                                               FeaturePerfMon]>;
131
132 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53
133 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
134 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
135 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
136 // FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
137 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
138 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
139
140 //===----------------------------------------------------------------------===//
141 // Assembly parser
142 //===----------------------------------------------------------------------===//
143
144 def GenericAsmParserVariant : AsmParserVariant {
145   int Variant = 0;
146   string Name = "generic";
147   string BreakCharacters = ".";
148 }
149
150 def AppleAsmParserVariant : AsmParserVariant {
151   int Variant = 1;
152   string Name = "apple-neon";
153   string BreakCharacters = ".";
154 }
155
156 //===----------------------------------------------------------------------===//
157 // Assembly printer
158 //===----------------------------------------------------------------------===//
159 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
160 // AsmWriter bits get associated with the correct class.
161 def GenericAsmWriter : AsmWriter {
162   string AsmWriterClassName  = "InstPrinter";
163   int PassSubtarget = 1;
164   int Variant = 0;
165   bit isMCAsmWriter = 1;
166 }
167
168 def AppleAsmWriter : AsmWriter {
169   let AsmWriterClassName = "AppleInstPrinter";
170   int PassSubtarget = 1;
171   int Variant = 1;
172   int isMCAsmWriter = 1;
173 }
174
175 //===----------------------------------------------------------------------===//
176 // Target Declaration
177 //===----------------------------------------------------------------------===//
178
179 def AArch64 : Target {
180   let InstructionSet = AArch64InstrInfo;
181   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
182   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
183 }