lib/MC/MCSubtargetInfo.cpp

   1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #include "llvm/MC/MCSubtargetInfo.h"
  11 #include "llvm/MC/MCInstrItineraries.h"
  12 #include "llvm/MC/SubtargetFeature.h"
  13 #include "llvm/ADT/StringRef.h"
  14 #include "llvm/ADT/Triple.h"
  15 #include "llvm/Support/raw_ostream.h"
  16 #include <algorithm>
  17
  18 using namespace llvm;
  19
  20 MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
  21
  22 void
  23 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
  24                                      const SubtargetFeatureKV *PF,
  25                                      const SubtargetFeatureKV *PD,
  26                                      const SubtargetInfoKV *ProcSched,
  27                                      const MCWriteProcResEntry *WPR,
  28                                      const MCWriteLatencyEntry *WL,
  29                                      const MCReadAdvanceEntry *RA,
  30                                      const InstrStage *IS,
  31                                      const unsigned *OC,
  32                                      const unsigned *FP,
  33                                      unsigned NF, unsigned NP) {
  34   TargetTriple = TT;
  35   ProcFeatures = PF;
  36   ProcDesc = PD;
  37   ProcSchedModels = ProcSched;
  38   WriteProcResTable = WPR;
  39   WriteLatencyTable = WL;
  40   ReadAdvanceTable = RA;
  41
  42   Stages = IS;
  43   OperandCycles = OC;
  44   ForwardingPaths = FP;
  45   NumFeatures = NF;
  46   NumProcs = NP;
  47
  48   SubtargetFeatures Features(FS);
  49   FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
  50                                         ProcFeatures, NumFeatures);
  51
  52   CPUSchedModel = getSchedModelForCPU(CPU);
  53 }
  54
  55 /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
  56 /// feature string) and recompute feature bits.
  57 uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
  58   SubtargetFeatures Features(FS);
  59   FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
  60                                         ProcFeatures, NumFeatures);
  61   return FeatureBits;
  62 }
  63
  64 /// ToggleFeature - Toggle a feature and returns the re-computed feature
  65 /// bits. This version does not change the implied bits.
  66 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
  67   FeatureBits ^= FB;
  68   return FeatureBits;
  69 }
  70
  71 /// ToggleFeature - Toggle a feature and returns the re-computed feature
  72 /// bits. This version will also change all implied bits.
  73 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
  74   SubtargetFeatures Features;
  75   FeatureBits = Features.ToggleFeature(FeatureBits, FS,
  76                                        ProcFeatures, NumFeatures);
  77   return FeatureBits;
  78 }
  79
  80
  81 const MCSchedModel *
  82 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
  83   assert(ProcSchedModels && "Processor machine model not available!");
  84
  85 #ifndef NDEBUG
  86   for (size_t i = 1; i < NumProcs; i++) {
  87     assert(strcmp(ProcSchedModels[i - 1].Key, ProcSchedModels[i].Key) < 0 &&
  88            "Processor machine model table is not sorted");
  89   }
  90 #endif
  91
  92   // Find entry
  93   SubtargetInfoKV KV;
  94   KV.Key = CPU.data();
  95   const SubtargetInfoKV *Found =
  96     std::lower_bound(ProcSchedModels, ProcSchedModels+NumProcs, KV);
  97   if (Found == ProcSchedModels+NumProcs || StringRef(Found->Key) != CPU) {
  98     errs() << "'" << CPU
  99            << "' is not a recognized processor for this target"
 100            << " (ignoring processor)\n";
 101     return &MCSchedModel::DefaultSchedModel;
 102   }
 103   assert(Found->Value && "Missing processor SchedModel value");
 104   return (const MCSchedModel *)Found->Value;
 105 }
 106
 107 InstrItineraryData
 108 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
 109   const MCSchedModel *SchedModel = getSchedModelForCPU(CPU);
 110   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
 111 }
 112
 113 /// Initialize an InstrItineraryData instance.
 114 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
 115   InstrItins =
 116     InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
 117 }