1 //===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the VirtRegMap class.
12 // It also contains implementations of the the Spiller interface, which, given a
13 // virtual register map and a machine function, eliminates all virtual
14 // references by replacing them with physical register references - adding spill
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "virtregmap"
20 #include "VirtRegMap.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/DepthFirstIterator.h"
36 #include "llvm/ADT/Statistic.h"
37 #include "llvm/ADT/STLExtras.h"
38 #include "llvm/ADT/SmallSet.h"
42 STATISTIC(NumSpills , "Number of register spills");
44 //===----------------------------------------------------------------------===//
45 // VirtRegMap implementation
46 //===----------------------------------------------------------------------===//
48 char VirtRegMap::ID = 0;
50 static RegisterPass<VirtRegMap>
51 X("virtregmap", "Virtual Register Map");
53 bool VirtRegMap::runOnMachineFunction(MachineFunction &mf) {
54 MRI = &mf.getRegInfo();
55 TII = mf.getTarget().getInstrInfo();
56 TRI = mf.getTarget().getRegisterInfo();
59 ReMatId = MAX_STACK_SLOT+1;
60 LowSpillSlot = HighSpillSlot = NO_STACK_SLOT;
63 Virt2StackSlotMap.clear();
64 Virt2ReMatIdMap.clear();
65 Virt2SplitMap.clear();
66 Virt2SplitKillMap.clear();
68 ImplicitDefed.clear();
69 SpillSlotToUsesMap.clear();
71 SpillPt2VirtMap.clear();
72 RestorePt2VirtMap.clear();
73 EmergencySpillMap.clear();
74 EmergencySpillSlots.clear();
76 SpillSlotToUsesMap.resize(8);
77 ImplicitDefed.resize(MF->getRegInfo().getLastVirtReg()+1-
78 TargetRegisterInfo::FirstVirtualRegister);
80 allocatableRCRegs.clear();
81 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
82 E = TRI->regclass_end(); I != E; ++I)
83 allocatableRCRegs.insert(std::make_pair(*I,
84 TRI->getAllocatableSet(mf, *I)));
91 void VirtRegMap::grow() {
92 unsigned LastVirtReg = MF->getRegInfo().getLastVirtReg();
93 Virt2PhysMap.grow(LastVirtReg);
94 Virt2StackSlotMap.grow(LastVirtReg);
95 Virt2ReMatIdMap.grow(LastVirtReg);
96 Virt2SplitMap.grow(LastVirtReg);
97 Virt2SplitKillMap.grow(LastVirtReg);
98 ReMatMap.grow(LastVirtReg);
99 ImplicitDefed.resize(LastVirtReg-TargetRegisterInfo::FirstVirtualRegister+1);
102 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
103 std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> Hint =
104 MRI->getRegAllocationHint(virtReg);
105 switch (Hint.first) {
107 case MachineRegisterInfo::RA_None:
109 case MachineRegisterInfo::RA_Preference:
110 if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
112 if (hasPhys(Hint.second))
113 return getPhys(Hint.second);
114 case MachineRegisterInfo::RA_PairEven: {
115 unsigned physReg = Hint.second;
116 if (TargetRegisterInfo::isPhysicalRegister(physReg))
117 return TRI->getRegisterPairEven(*MF, physReg);
118 else if (hasPhys(physReg))
119 return TRI->getRegisterPairEven(*MF, getPhys(physReg));
122 case MachineRegisterInfo::RA_PairOdd: {
123 unsigned physReg = Hint.second;
124 if (TargetRegisterInfo::isPhysicalRegister(physReg))
125 return TRI->getRegisterPairOdd(*MF, physReg);
126 else if (hasPhys(physReg))
127 return TRI->getRegisterPairOdd(*MF, getPhys(physReg));
131 // Shouldn't reach here.
135 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
136 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
137 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
138 "attempt to assign stack slot to already spilled register");
139 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
140 int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
142 if (LowSpillSlot == NO_STACK_SLOT)
144 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
146 unsigned Idx = SS-LowSpillSlot;
147 while (Idx >= SpillSlotToUsesMap.size())
148 SpillSlotToUsesMap.resize(SpillSlotToUsesMap.size()*2);
149 Virt2StackSlotMap[virtReg] = SS;
154 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
155 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
156 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
157 "attempt to assign stack slot to already spilled register");
159 (SS >= MF->getFrameInfo()->getObjectIndexBegin())) &&
160 "illegal fixed frame index");
161 Virt2StackSlotMap[virtReg] = SS;
164 int VirtRegMap::assignVirtReMatId(unsigned virtReg) {
165 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
166 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
167 "attempt to assign re-mat id to already spilled register");
168 Virt2ReMatIdMap[virtReg] = ReMatId;
172 void VirtRegMap::assignVirtReMatId(unsigned virtReg, int id) {
173 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
174 assert(Virt2ReMatIdMap[virtReg] == NO_STACK_SLOT &&
175 "attempt to assign re-mat id to already spilled register");
176 Virt2ReMatIdMap[virtReg] = id;
179 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
180 std::map<const TargetRegisterClass*, int>::iterator I =
181 EmergencySpillSlots.find(RC);
182 if (I != EmergencySpillSlots.end())
184 int SS = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
186 if (LowSpillSlot == NO_STACK_SLOT)
188 if (HighSpillSlot == NO_STACK_SLOT || SS > HighSpillSlot)
190 EmergencySpillSlots[RC] = SS;
194 void VirtRegMap::addSpillSlotUse(int FI, MachineInstr *MI) {
195 if (!MF->getFrameInfo()->isFixedObjectIndex(FI)) {
196 // If FI < LowSpillSlot, this stack reference was produced by
197 // instruction selection and is not a spill
198 if (FI >= LowSpillSlot) {
199 assert(FI >= 0 && "Spill slot index should not be negative!");
200 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
201 && "Invalid spill slot");
202 SpillSlotToUsesMap[FI-LowSpillSlot].insert(MI);
207 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
208 MachineInstr *NewMI, ModRef MRInfo) {
209 // Move previous memory references folded to new instruction.
210 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
211 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
212 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
213 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
214 MI2VirtMap.erase(I++);
217 // add new memory reference
218 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
221 void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *MI, ModRef MRInfo) {
222 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(MI);
223 MI2VirtMap.insert(IP, std::make_pair(MI, std::make_pair(VirtReg, MRInfo)));
226 void VirtRegMap::RemoveMachineInstrFromMaps(MachineInstr *MI) {
227 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228 MachineOperand &MO = MI->getOperand(i);
231 int FI = MO.getIndex();
232 if (MF->getFrameInfo()->isFixedObjectIndex(FI))
234 // This stack reference was produced by instruction selection and
236 if (FI < LowSpillSlot)
238 assert((unsigned)FI-LowSpillSlot < SpillSlotToUsesMap.size()
239 && "Invalid spill slot");
240 SpillSlotToUsesMap[FI-LowSpillSlot].erase(MI);
242 MI2VirtMap.erase(MI);
243 SpillPt2VirtMap.erase(MI);
244 RestorePt2VirtMap.erase(MI);
245 EmergencySpillMap.erase(MI);
248 /// FindUnusedRegisters - Gather a list of allocatable registers that
249 /// have not been allocated to any virtual register.
250 bool VirtRegMap::FindUnusedRegisters(LiveIntervals* LIs) {
251 unsigned NumRegs = TRI->getNumRegs();
253 UnusedRegs.resize(NumRegs);
255 BitVector Used(NumRegs);
256 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
257 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
258 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
259 Used.set(Virt2PhysMap[i]);
261 BitVector Allocatable = TRI->getAllocatableSet(*MF);
262 bool AnyUnused = false;
263 for (unsigned Reg = 1; Reg < NumRegs; ++Reg) {
264 if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) {
265 bool ReallyUnused = true;
266 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) {
267 if (Used[*AS] || LIs->hasInterval(*AS)) {
268 ReallyUnused = false;
282 void VirtRegMap::print(std::ostream &OS, const Module* M) const {
283 const TargetRegisterInfo* TRI = MF->getTarget().getRegisterInfo();
285 OS << "********** REGISTER MAP **********\n";
286 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
287 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i) {
288 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
289 OS << "[reg" << i << " -> " << TRI->getName(Virt2PhysMap[i])
293 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
294 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
295 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
296 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
300 void VirtRegMap::dump() const {