1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/RegisterCoalescer.h"
20 #include "llvm/ADT/BitVector.h"
23 class SimpleRegisterCoalescing;
25 class TargetRegisterInfo;
26 class TargetInstrInfo;
28 class MachineLoopInfo;
30 /// CopyRec - Representation for copy instructions in coalescer queue.
35 CopyRec(MachineInstr *mi, unsigned depth)
36 : MI(mi), LoopDepth(depth) {};
39 class SimpleRegisterCoalescing : public MachineFunctionPass,
40 public RegisterCoalescer {
42 MachineRegisterInfo* mri_;
43 const TargetMachine* tm_;
44 const TargetRegisterInfo* tri_;
45 const TargetInstrInfo* tii_;
47 const MachineLoopInfo* loopInfo;
49 BitVector allocatableRegs_;
50 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
52 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
54 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
56 /// ReMatCopies - Keep track of copies eliminated due to remat.
58 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
60 /// ReMatDefs - Keep track of definition instructions which have
62 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
65 static char ID; // Pass identifcation, replacement for typeid
66 SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
78 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
79 virtual void releaseMemory();
81 /// runOnMachineFunction - pass entry point
82 virtual bool runOnMachineFunction(MachineFunction&);
84 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
85 // This runs as an independent pass, so don't do anything.
89 /// print - Implement the dump method.
90 virtual void print(raw_ostream &O, const Module* = 0) const;
93 /// joinIntervals - join compatible live intervals
96 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
97 /// copies that cannot yet be coalesced into the "TryAgain" list.
98 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
99 std::vector<CopyRec> &TryAgain);
101 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
102 /// which are the src/dst of the copy instruction CopyMI. This returns true
103 /// if the copy was successfully coalesced away. If it is not currently
104 /// possible to coalesce this interval, but it may be possible if other
105 /// things get coalesced, then it returns true by reference in 'Again'.
106 bool JoinCopy(CopyRec &TheCopy, bool &Again);
108 /// JoinIntervals - Attempt to join these two intervals. On failure, this
109 /// returns false. Otherwise, if one of the intervals being joined is a
110 /// physreg, this method always canonicalizes DestInt to be it. The output
111 /// "SrcInt" will not have been modified, so we can use this information
112 /// below to update aliases.
113 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped);
115 /// SimpleJoin - Attempt to join the specified interval into this one. The
116 /// caller of this method must guarantee that the RHS only contains a single
117 /// value number and that the RHS is not defined by a copy from this
118 /// interval. This returns false if the intervals are not joinable, or it
119 /// joins them and returns true.
120 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS);
122 /// Return true if the two specified registers belong to different register
123 /// classes. The registers may be either phys or virt regs.
124 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
126 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
127 /// the source value number is defined by a copy from the destination reg
128 /// see if we can merge these two destination reg valno# into a single
129 /// value number, eliminating a copy.
130 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
131 MachineInstr *CopyMI);
133 /// HasOtherReachingDefs - Return true if there are definitions of IntB
134 /// other than BValNo val# that can reach uses of AValno val# of IntA.
135 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
136 VNInfo *AValNo, VNInfo *BValNo);
138 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
139 /// If the source value number is defined by a commutable instruction and
140 /// its other operand is coalesced to the copy dest register, see if we
141 /// can transform the copy into a noop by commuting the definition.
142 bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
143 MachineInstr *CopyMI);
145 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic
146 /// block as the copy instruction, trim the ive interval to the last use
148 bool TrimLiveIntervalToLastUse(MachineInstrIndex CopyIdx,
149 MachineBasicBlock *CopyMBB,
150 LiveInterval &li, const LiveRange *LR);
152 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
153 /// computation, replace the copy by rematerialize the definition.
154 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
155 unsigned DstSubIdx, MachineInstr *CopyMI);
157 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
158 /// from an implicit def to another register can be coalesced away.
159 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
160 LiveInterval &li, LiveInterval &ImpLi) const;
162 /// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
163 /// implicit_def and it is being removed. Turn all copies from this value#
164 /// into implicit_defs.
165 void TurnCopiesFromValNoToImpDefs(LiveInterval &li, VNInfo *VNI);
167 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
168 /// a virtual destination register with physical source register.
169 bool isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
170 MachineBasicBlock *CopyMBB,
171 LiveInterval &DstInt, LiveInterval &SrcInt);
173 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
174 /// copy from a virtual source register to a physical destination register.
175 bool isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
176 MachineBasicBlock *CopyMBB,
177 LiveInterval &DstInt, LiveInterval &SrcInt);
179 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
180 /// two virtual registers from different register classes.
181 bool isWinToJoinCrossClass(unsigned LargeReg, unsigned SmallReg,
184 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
185 /// register with a physical register, check if any of the virtual register
186 /// operand is a sub-register use or def. If so, make sure it won't result
187 /// in an illegal extract_subreg or insert_subreg instruction.
188 bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
189 unsigned VirtReg, unsigned PhysReg);
191 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
192 /// an extract_subreg where dst is a physical register, e.g.
193 /// cl = EXTRACT_SUBREG reg1024, 1
194 bool CanJoinExtractSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
195 unsigned SubIdx, unsigned &RealDstReg);
197 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
198 /// an insert_subreg where src is a physical register, e.g.
199 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
200 bool CanJoinInsertSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
201 unsigned SubIdx, unsigned &RealDstReg);
203 /// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
204 /// the specified live interval is defined by a copy from the specified
206 bool RangeIsDefinedByCopyFromReg(LiveInterval &li, LiveRange *LR,
209 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
210 /// update the subregister number if it is not zero. If DstReg is a
211 /// physical register and the existing subregister number of the def / use
212 /// being updated is not zero, make sure to set it to the correct physical
214 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
216 /// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
217 /// due to live range lengthening as the result of coalescing.
218 void RemoveUnnecessaryKills(unsigned Reg, LiveInterval &LI);
220 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
221 /// Return true if live interval is removed.
222 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
224 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
225 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
226 /// as ends the live range there. If there isn't another use, then this
227 /// live range is dead. Return true if live interval is removed.
228 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
230 /// RemoveDeadDef - If a def of a live interval is now determined dead,
231 /// remove the val# it defines. If the live interval becomes empty, remove
233 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
235 /// lastRegisterUse - Returns the last use of the specific register between
236 /// cycles Start and End or NULL if there are no uses.
237 MachineOperand *lastRegisterUse(MachineInstrIndex Start,
238 MachineInstrIndex End, unsigned Reg,
239 MachineInstrIndex &LastUseIdx) const;
241 /// CalculateSpillWeights - Compute spill weights for all virtual register
243 void CalculateSpillWeights();
245 void printRegName(unsigned reg) const;
248 } // End llvm namespace