1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/RegisterCoalescer.h"
20 #include "llvm/ADT/BitVector.h"
23 class SimpleRegisterCoalescing;
25 class TargetRegisterInfo;
26 class TargetInstrInfo;
28 class MachineLoopInfo;
30 /// CopyRec - Representation for copy instructions in coalescer queue.
35 CopyRec(MachineInstr *mi, unsigned depth)
36 : MI(mi), LoopDepth(depth) {}
39 class SimpleRegisterCoalescing : public MachineFunctionPass,
40 public RegisterCoalescer {
42 MachineRegisterInfo* mri_;
43 const TargetMachine* tm_;
44 const TargetRegisterInfo* tri_;
45 const TargetInstrInfo* tii_;
47 const MachineLoopInfo* loopInfo;
50 BitVector allocatableRegs_;
51 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
53 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
55 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
57 /// ReMatCopies - Keep track of copies eliminated due to remat.
59 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
61 /// ReMatDefs - Keep track of definition instructions which have
63 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
66 static char ID; // Pass identifcation, replacement for typeid
67 SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
79 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
80 virtual void releaseMemory();
82 /// runOnMachineFunction - pass entry point
83 virtual bool runOnMachineFunction(MachineFunction&);
85 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
86 // This runs as an independent pass, so don't do anything.
90 /// print - Implement the dump method.
91 virtual void print(raw_ostream &O, const Module* = 0) const;
94 /// joinIntervals - join compatible live intervals
97 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
98 /// copies that cannot yet be coalesced into the "TryAgain" list.
99 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
100 std::vector<CopyRec> &TryAgain);
102 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
103 /// which are the src/dst of the copy instruction CopyMI. This returns true
104 /// if the copy was successfully coalesced away. If it is not currently
105 /// possible to coalesce this interval, but it may be possible if other
106 /// things get coalesced, then it returns true by reference in 'Again'.
107 bool JoinCopy(CopyRec &TheCopy, bool &Again);
109 /// JoinIntervals - Attempt to join these two intervals. On failure, this
110 /// returns false. Otherwise, if one of the intervals being joined is a
111 /// physreg, this method always canonicalizes DestInt to be it. The output
112 /// "SrcInt" will not have been modified, so we can use this information
113 /// below to update aliases.
114 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped,
117 /// Return true if the two specified registers belong to different register
118 /// classes. The registers may be either phys or virt regs.
119 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
121 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
122 /// the source value number is defined by a copy from the destination reg
123 /// see if we can merge these two destination reg valno# into a single
124 /// value number, eliminating a copy.
125 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
126 MachineInstr *CopyMI);
128 /// HasOtherReachingDefs - Return true if there are definitions of IntB
129 /// other than BValNo val# that can reach uses of AValno val# of IntA.
130 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
131 VNInfo *AValNo, VNInfo *BValNo);
133 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
134 /// If the source value number is defined by a commutable instruction and
135 /// its other operand is coalesced to the copy dest register, see if we
136 /// can transform the copy into a noop by commuting the definition.
137 bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
138 MachineInstr *CopyMI);
140 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic
141 /// block as the copy instruction, trim the ive interval to the last use
143 bool TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
144 MachineBasicBlock *CopyMBB,
145 LiveInterval &li, const LiveRange *LR);
147 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
148 /// computation, replace the copy by rematerialize the definition.
149 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
150 unsigned DstSubIdx, MachineInstr *CopyMI);
152 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
153 /// from an implicit def to another register can be coalesced away.
154 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
155 LiveInterval &li, LiveInterval &ImpLi) const;
157 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
158 /// two virtual registers from different register classes.
159 bool isWinToJoinCrossClass(unsigned SrcReg,
161 const TargetRegisterClass *SrcRC,
162 const TargetRegisterClass *DstRC,
163 const TargetRegisterClass *NewRC);
165 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
166 /// register with a physical register, check if any of the virtual register
167 /// operand is a sub-register use or def. If so, make sure it won't result
168 /// in an illegal extract_subreg or insert_subreg instruction.
169 bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
170 unsigned VirtReg, unsigned PhysReg);
172 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
173 /// an extract_subreg where dst is a physical register, e.g.
174 /// cl = EXTRACT_SUBREG reg1024, 1
175 bool CanJoinExtractSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
176 unsigned SubIdx, unsigned &RealDstReg);
178 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
179 /// an insert_subreg where src is a physical register, e.g.
180 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
181 bool CanJoinInsertSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
182 unsigned SubIdx, unsigned &RealDstReg);
184 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
185 /// update the subregister number if it is not zero. If DstReg is a
186 /// physical register and the existing subregister number of the def / use
187 /// being updated is not zero, make sure to set it to the correct physical
189 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
191 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
192 /// Return true if live interval is removed.
193 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
195 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
196 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
197 /// as ends the live range there. If there isn't another use, then this
198 /// live range is dead. Return true if live interval is removed.
199 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
201 /// RemoveDeadDef - If a def of a live interval is now determined dead,
202 /// remove the val# it defines. If the live interval becomes empty, remove
204 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
206 /// lastRegisterUse - Returns the last use of the specific register between
207 /// cycles Start and End or NULL if there are no uses.
208 MachineOperand *lastRegisterUse(SlotIndex Start, SlotIndex End,
209 unsigned Reg, SlotIndex &LastUseIdx) const;
212 } // End llvm namespace