1 //===-- SimpleRegisterCoalescing.h - Register Coalescing --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register copy coalescing phase.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
15 #define LLVM_CODEGEN_SIMPLE_REGISTER_COALESCING_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/RegisterCoalescer.h"
20 #include "llvm/ADT/BitVector.h"
23 class SimpleRegisterCoalescing;
25 class TargetRegisterInfo;
26 class TargetInstrInfo;
28 class MachineLoopInfo;
30 /// CopyRec - Representation for copy instructions in coalescer queue.
35 CopyRec(MachineInstr *mi, unsigned depth)
36 : MI(mi), LoopDepth(depth) {}
39 class SimpleRegisterCoalescing : public MachineFunctionPass,
40 public RegisterCoalescer {
42 MachineRegisterInfo* mri_;
43 const TargetMachine* tm_;
44 const TargetRegisterInfo* tri_;
45 const TargetInstrInfo* tii_;
47 const MachineLoopInfo* loopInfo;
50 BitVector allocatableRegs_;
51 DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;
53 /// JoinedCopies - Keep track of copies eliminated due to coalescing.
55 SmallPtrSet<MachineInstr*, 32> JoinedCopies;
57 /// ReMatCopies - Keep track of copies eliminated due to remat.
59 SmallPtrSet<MachineInstr*, 32> ReMatCopies;
61 /// ReMatDefs - Keep track of definition instructions which have
63 SmallPtrSet<MachineInstr*, 8> ReMatDefs;
66 static char ID; // Pass identifcation, replacement for typeid
67 SimpleRegisterCoalescing() : MachineFunctionPass(&ID) {}
79 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
80 virtual void releaseMemory();
82 /// runOnMachineFunction - pass entry point
83 virtual bool runOnMachineFunction(MachineFunction&);
85 bool coalesceFunction(MachineFunction &mf, RegallocQuery &) {
86 // This runs as an independent pass, so don't do anything.
90 /// print - Implement the dump method.
91 virtual void print(raw_ostream &O, const Module* = 0) const;
94 /// joinIntervals - join compatible live intervals
97 /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
98 /// copies that cannot yet be coalesced into the "TryAgain" list.
99 void CopyCoalesceInMBB(MachineBasicBlock *MBB,
100 std::vector<CopyRec> &TryAgain);
102 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
103 /// which are the src/dst of the copy instruction CopyMI. This returns true
104 /// if the copy was successfully coalesced away. If it is not currently
105 /// possible to coalesce this interval, but it may be possible if other
106 /// things get coalesced, then it returns true by reference in 'Again'.
107 bool JoinCopy(CopyRec &TheCopy, bool &Again);
109 /// JoinIntervals - Attempt to join these two intervals. On failure, this
110 /// returns false. Otherwise, if one of the intervals being joined is a
111 /// physreg, this method always canonicalizes DestInt to be it. The output
112 /// "SrcInt" will not have been modified, so we can use this information
113 /// below to update aliases.
114 bool JoinIntervals(LiveInterval &LHS, LiveInterval &RHS, bool &Swapped,
117 /// SimpleJoin - Attempt to join the specified interval into this one. The
118 /// caller of this method must guarantee that the RHS only contains a single
119 /// value number and that the RHS is not defined by a copy from this
120 /// interval. This returns false if the intervals are not joinable, or it
121 /// joins them and returns true.
122 bool SimpleJoin(LiveInterval &LHS, LiveInterval &RHS, CoalescerPair &CP);
124 /// Return true if the two specified registers belong to different register
125 /// classes. The registers may be either phys or virt regs.
126 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
128 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If
129 /// the source value number is defined by a copy from the destination reg
130 /// see if we can merge these two destination reg valno# into a single
131 /// value number, eliminating a copy.
132 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
133 MachineInstr *CopyMI);
135 /// HasOtherReachingDefs - Return true if there are definitions of IntB
136 /// other than BValNo val# that can reach uses of AValno val# of IntA.
137 bool HasOtherReachingDefs(LiveInterval &IntA, LiveInterval &IntB,
138 VNInfo *AValNo, VNInfo *BValNo);
140 /// RemoveCopyByCommutingDef - We found a non-trivially-coalescable copy.
141 /// If the source value number is defined by a commutable instruction and
142 /// its other operand is coalesced to the copy dest register, see if we
143 /// can transform the copy into a noop by commuting the definition.
144 bool RemoveCopyByCommutingDef(LiveInterval &IntA, LiveInterval &IntB,
145 MachineInstr *CopyMI);
147 /// TrimLiveIntervalToLastUse - If there is a last use in the same basic
148 /// block as the copy instruction, trim the ive interval to the last use
150 bool TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
151 MachineBasicBlock *CopyMBB,
152 LiveInterval &li, const LiveRange *LR);
154 /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial
155 /// computation, replace the copy by rematerialize the definition.
156 bool ReMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg,
157 unsigned DstSubIdx, MachineInstr *CopyMI);
159 /// CanCoalesceWithImpDef - Returns true if the specified copy instruction
160 /// from an implicit def to another register can be coalesced away.
161 bool CanCoalesceWithImpDef(MachineInstr *CopyMI,
162 LiveInterval &li, LiveInterval &ImpLi) const;
164 /// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
165 /// implicit_def and it is being removed. Turn all copies from this value#
166 /// into implicit_defs.
167 void TurnCopiesFromValNoToImpDefs(LiveInterval &li, VNInfo *VNI);
169 /// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
170 /// a virtual destination register with physical source register.
171 bool isWinToJoinVRWithSrcPhysReg(MachineInstr *CopyMI,
172 MachineBasicBlock *CopyMBB,
173 LiveInterval &DstInt, LiveInterval &SrcInt);
175 /// isWinToJoinVRWithDstPhysReg - Return true if it's worth while to join a
176 /// copy from a virtual source register to a physical destination register.
177 bool isWinToJoinVRWithDstPhysReg(MachineInstr *CopyMI,
178 MachineBasicBlock *CopyMBB,
179 LiveInterval &DstInt, LiveInterval &SrcInt);
181 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
182 /// two virtual registers from different register classes.
183 bool isWinToJoinCrossClass(unsigned SrcReg,
185 const TargetRegisterClass *SrcRC,
186 const TargetRegisterClass *DstRC,
187 const TargetRegisterClass *NewRC);
189 /// HasIncompatibleSubRegDefUse - If we are trying to coalesce a virtual
190 /// register with a physical register, check if any of the virtual register
191 /// operand is a sub-register use or def. If so, make sure it won't result
192 /// in an illegal extract_subreg or insert_subreg instruction.
193 bool HasIncompatibleSubRegDefUse(MachineInstr *CopyMI,
194 unsigned VirtReg, unsigned PhysReg);
196 /// CanJoinExtractSubRegToPhysReg - Return true if it's possible to coalesce
197 /// an extract_subreg where dst is a physical register, e.g.
198 /// cl = EXTRACT_SUBREG reg1024, 1
199 bool CanJoinExtractSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
200 unsigned SubIdx, unsigned &RealDstReg);
202 /// CanJoinInsertSubRegToPhysReg - Return true if it's possible to coalesce
203 /// an insert_subreg where src is a physical register, e.g.
204 /// reg1024 = INSERT_SUBREG reg1024, c1, 0
205 bool CanJoinInsertSubRegToPhysReg(unsigned DstReg, unsigned SrcReg,
206 unsigned SubIdx, unsigned &RealDstReg);
208 /// ValueLiveAt - Return true if the LiveRange pointed to by the given
209 /// iterator, or any subsequent range with the same value number,
210 /// is live at the given point.
211 bool ValueLiveAt(LiveInterval::iterator LRItr, LiveInterval::iterator LREnd,
212 SlotIndex defPoint) const;
214 /// RangeIsDefinedByCopy - Return true if the specified live range of the
215 /// specified live interval is defined by a coalescable copy.
216 bool RangeIsDefinedByCopy(LiveInterval &li, LiveRange *LR,
219 /// UpdateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and
220 /// update the subregister number if it is not zero. If DstReg is a
221 /// physical register and the existing subregister number of the def / use
222 /// being updated is not zero, make sure to set it to the correct physical
224 void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
226 /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy.
227 /// Return true if live interval is removed.
228 bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI);
230 /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially
231 /// extended by a dead copy. Mark the last use (if any) of the val# as kill
232 /// as ends the live range there. If there isn't another use, then this
233 /// live range is dead. Return true if live interval is removed.
234 bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI);
236 /// RemoveDeadDef - If a def of a live interval is now determined dead,
237 /// remove the val# it defines. If the live interval becomes empty, remove
239 bool RemoveDeadDef(LiveInterval &li, MachineInstr *DefMI);
241 /// lastRegisterUse - Returns the last use of the specific register between
242 /// cycles Start and End or NULL if there are no uses.
243 MachineOperand *lastRegisterUse(SlotIndex Start, SlotIndex End,
244 unsigned Reg, SlotIndex &LastUseIdx) const;
247 } // End llvm namespace