1 //===-- SimpleRegisterCoalescing.cpp - Register Coalescing ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements a simple register coalescing pass that attempts to
11 // aggressively coalesce every register copy that it can.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "regcoalescing"
16 #include "llvm/CodeGen/SimpleRegisterCoalescing.h"
17 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
18 #include "VirtRegMap.h"
19 #include "llvm/Value.h"
20 #include "llvm/Analysis/LoopInfo.h"
21 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/CodeGen/RegisterCoalescer.h"
27 #include "llvm/Target/MRegisterInfo.h"
28 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/ADT/SmallSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/ADT/STLExtras.h"
39 STATISTIC(numJoins , "Number of interval joins performed");
40 STATISTIC(numPeep , "Number of identity moves eliminated after coalescing");
41 STATISTIC(numAborts , "Number of times interval joining aborted");
43 char SimpleRegisterCoalescing::ID = 0;
46 EnableJoining("join-liveintervals",
47 cl::desc("Coalesce copies (default=true)"),
50 RegisterPass<SimpleRegisterCoalescing>
51 X("simple-register-coalescing", "Simple Register Coalescing");
53 // Declare that we implement the RegisterCoalescer interface
54 RegisterAnalysisGroup<RegisterCoalescer, true/*The Default*/> V(X);
57 const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
59 void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
60 //AU.addPreserved<LiveVariables>();
61 AU.addPreserved<LiveIntervals>();
62 AU.addPreservedID(PHIEliminationID);
63 AU.addPreservedID(TwoAddressInstructionPassID);
64 AU.addRequired<LiveVariables>();
65 AU.addRequired<LiveIntervals>();
66 AU.addRequired<LoopInfo>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy with IntA
71 /// being the source and IntB being the dest, thus this defines a value number
72 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
73 /// see if we can merge these two pieces of B into a single value number,
74 /// eliminating a copy. For example:
78 /// B1 = A3 <- this copy
80 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
81 /// value number to be replaced with B0 (which simplifies the B liveinterval).
83 /// This returns true if an interval was modified.
85 bool SimpleRegisterCoalescing::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
86 MachineInstr *CopyMI) {
87 unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
89 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
91 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
92 VNInfo *BValNo = BLR->valno;
94 // Get the location that B is defined at. Two options: either this value has
95 // an unknown definition point or it is defined at CopyIdx. If unknown, we
97 if (!BValNo->reg) return false;
98 assert(BValNo->def == CopyIdx &&
99 "Copy doesn't define the value?");
101 // AValNo is the value number in A that defines the copy, A0 in the example.
102 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
103 VNInfo *AValNo = AValLR->valno;
105 // If AValNo is defined as a copy from IntB, we can potentially process this.
107 // Get the instruction that defines this value number.
108 unsigned SrcReg = AValNo->reg;
109 if (!SrcReg) return false; // Not defined by a copy.
111 // If the value number is not defined by a copy instruction, ignore it.
113 // If the source register comes from an interval other than IntB, we can't
115 if (rep(SrcReg) != IntB.reg) return false;
117 // Get the LiveRange in IntB that this value number starts with.
118 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNo->def-1);
120 // Make sure that the end of the live range is inside the same block as
122 MachineInstr *ValLREndInst = li_->getInstructionFromIndex(ValLR->end-1);
124 ValLREndInst->getParent() != CopyMI->getParent()) return false;
126 // Okay, we now know that ValLR ends in the same block that the CopyMI
127 // live-range starts. If there are no intervening live ranges between them in
128 // IntB, we can merge them.
129 if (ValLR+1 != BLR) return false;
131 // If a live interval is a physical register, conservatively check if any
132 // of its sub-registers is overlapping the live interval of the virtual
133 // register. If so, do not coalesce.
134 if (MRegisterInfo::isPhysicalRegister(IntB.reg) &&
135 *mri_->getSubRegisters(IntB.reg)) {
136 for (const unsigned* SR = mri_->getSubRegisters(IntB.reg); *SR; ++SR)
137 if (li_->hasInterval(*SR) && IntA.overlaps(li_->getInterval(*SR))) {
138 DOUT << "Interfere with sub-register ";
139 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
144 DOUT << "\nExtending: "; IntB.print(DOUT, mri_);
146 unsigned FillerStart = ValLR->end, FillerEnd = BLR->start;
147 // We are about to delete CopyMI, so need to remove it as the 'instruction
148 // that defines this value #'. Update the the valnum with the new defining
150 BValNo->def = FillerStart;
153 // Okay, we can merge them. We need to insert a new liverange:
154 // [ValLR.end, BLR.begin) of either value number, then we merge the
155 // two value numbers.
156 IntB.addRange(LiveRange(FillerStart, FillerEnd, BValNo));
158 // If the IntB live range is assigned to a physical register, and if that
159 // physreg has aliases,
160 if (MRegisterInfo::isPhysicalRegister(IntB.reg)) {
161 // Update the liveintervals of sub-registers.
162 for (const unsigned *AS = mri_->getSubRegisters(IntB.reg); *AS; ++AS) {
163 LiveInterval &AliasLI = li_->getInterval(*AS);
164 AliasLI.addRange(LiveRange(FillerStart, FillerEnd,
165 AliasLI.getNextValue(FillerStart, 0, li_->getVNInfoAllocator())));
169 // Okay, merge "B1" into the same value number as "B0".
170 if (BValNo != ValLR->valno)
171 IntB.MergeValueNumberInto(BValNo, ValLR->valno);
172 DOUT << " result = "; IntB.print(DOUT, mri_);
175 // If the source instruction was killing the source register before the
176 // merge, unset the isKill marker given the live range has been extended.
177 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
179 ValLREndInst->getOperand(UIdx).unsetIsKill();
181 // Finally, delete the copy instruction.
182 li_->RemoveMachineInstrFromMaps(CopyMI);
183 CopyMI->eraseFromParent();
188 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
189 /// which are the src/dst of the copy instruction CopyMI. This returns true
190 /// if the copy was successfully coalesced away, or if it is never possible
191 /// to coalesce this copy, due to register constraints. It returns
192 /// false if it is not currently possible to coalesce this interval, but
193 /// it may be possible if other things get coalesced.
194 bool SimpleRegisterCoalescing::JoinCopy(MachineInstr *CopyMI,
195 unsigned SrcReg, unsigned DstReg, bool PhysOnly) {
196 DOUT << li_->getInstructionIndex(CopyMI) << '\t' << *CopyMI;
198 // Get representative registers.
199 unsigned repSrcReg = rep(SrcReg);
200 unsigned repDstReg = rep(DstReg);
202 // If they are already joined we continue.
203 if (repSrcReg == repDstReg) {
204 DOUT << "\tCopy already coalesced.\n";
205 return true; // Not coalescable.
208 bool SrcIsPhys = MRegisterInfo::isPhysicalRegister(repSrcReg);
209 bool DstIsPhys = MRegisterInfo::isPhysicalRegister(repDstReg);
210 if (PhysOnly && !SrcIsPhys && !DstIsPhys)
211 // Only joining physical registers with virtual registers in this round.
214 // If they are both physical registers, we cannot join them.
215 if (SrcIsPhys && DstIsPhys) {
216 DOUT << "\tCan not coalesce physregs.\n";
217 return true; // Not coalescable.
220 // We only join virtual registers with allocatable physical registers.
221 if (SrcIsPhys && !allocatableRegs_[repSrcReg]) {
222 DOUT << "\tSrc reg is unallocatable physreg.\n";
223 return true; // Not coalescable.
225 if (DstIsPhys && !allocatableRegs_[repDstReg]) {
226 DOUT << "\tDst reg is unallocatable physreg.\n";
227 return true; // Not coalescable.
230 bool isExtSubReg = CopyMI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG;
231 unsigned RealDstReg = 0;
233 unsigned SubIdx = CopyMI->getOperand(2).getImm();
235 // r1024 = EXTRACT_SUBREG EAX, 0 then r1024 is really going to be
236 // coalesced with AX.
237 repSrcReg = mri_->getSubReg(repSrcReg, SubIdx);
238 else if (DstIsPhys) {
239 // If this is a extract_subreg where dst is a physical register, e.g.
240 // cl = EXTRACT_SUBREG reg1024, 1
241 // then create and update the actual physical register allocated to RHS.
242 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(SrcReg);
243 for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg);
244 unsigned SR = *SRs; ++SRs) {
245 if (repDstReg == mri_->getSubReg(SR, SubIdx) &&
251 assert(RealDstReg && "Invalid extra_subreg instruction!");
253 // For this type of EXTRACT_SUBREG, conservatively
254 // check if the live interval of the source register interfere with the
255 // actual super physical register we are trying to coalesce with.
256 LiveInterval &RHS = li_->getInterval(repSrcReg);
257 if (li_->hasInterval(RealDstReg) &&
258 RHS.overlaps(li_->getInterval(RealDstReg))) {
259 DOUT << "Interfere with register ";
260 DEBUG(li_->getInterval(RealDstReg).print(DOUT, mri_));
261 return true; // Not coalescable
263 for (const unsigned* SR = mri_->getSubRegisters(RealDstReg); *SR; ++SR)
264 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
265 DOUT << "Interfere with sub-register ";
266 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
270 } else if (differingRegisterClasses(repSrcReg, repDstReg)) {
271 // If they are not of the same register class, we cannot join them.
272 DOUT << "\tSrc/Dest are different register classes.\n";
273 // Allow the coalescer to try again in case either side gets coalesced to
274 // a physical register that's compatible with the other side. e.g.
275 // r1024 = MOV32to32_ r1025
276 // but later r1024 is assigned EAX then r1025 may be coalesced with EAX.
280 LiveInterval &SrcInt = li_->getInterval(repSrcReg);
281 LiveInterval &DstInt = li_->getInterval(repDstReg);
282 assert(SrcInt.reg == repSrcReg && DstInt.reg == repDstReg &&
283 "Register mapping is horribly broken!");
285 DOUT << "\t\tInspecting "; SrcInt.print(DOUT, mri_);
286 DOUT << " and "; DstInt.print(DOUT, mri_);
289 // Check if it is necessary to propagate "isDead" property before intervals
291 MachineOperand *mopd = CopyMI->findRegisterDefOperand(DstReg);
292 bool isDead = mopd->isDead();
293 bool isShorten = false;
294 unsigned SrcStart = 0, RemoveStart = 0;
295 unsigned SrcEnd = 0, RemoveEnd = 0;
297 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
298 LiveInterval::iterator SrcLR =
299 SrcInt.FindLiveRangeContaining(li_->getUseIndex(CopyIdx));
300 RemoveStart = SrcStart = SrcLR->start;
301 RemoveEnd = SrcEnd = SrcLR->end;
302 // The instruction which defines the src is only truly dead if there are
303 // no intermediate uses and there isn't a use beyond the copy.
304 // FIXME: find the last use, mark is kill and shorten the live range.
305 if (SrcEnd > li_->getDefIndex(CopyIdx)) {
309 MachineInstr *LastUse= lastRegisterUse(SrcStart, CopyIdx, repSrcReg, MOU);
311 // Shorten the liveinterval to the end of last use.
315 RemoveStart = li_->getDefIndex(li_->getInstructionIndex(LastUse));
318 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
320 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
322 // A dead def should have a single cycle interval.
329 // We need to be careful about coalescing a source physical register with a
330 // virtual register. Once the coalescing is done, it cannot be broken and
331 // these are not spillable! If the destination interval uses are far away,
332 // think twice about coalescing them!
333 if (!mopd->isDead() && (SrcIsPhys || DstIsPhys) && !isExtSubReg) {
334 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
335 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
336 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
337 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
338 unsigned Threshold = allocatableRCRegs_[RC].count();
340 // If the virtual register live interval is long but it has low use desity,
341 // do not join them, instead mark the physical register as its allocation
343 unsigned Length = JoinVInt.getSize() / InstrSlots::NUM;
344 LiveVariables::VarInfo &vi = lv_->getVarInfo(JoinVReg);
345 if (Length > Threshold &&
346 (((float)vi.NumUses / Length) < (1.0 / Threshold))) {
347 JoinVInt.preference = JoinPReg;
349 DOUT << "\tMay tie down a physical register, abort!\n";
354 // Okay, attempt to join these two intervals. On failure, this returns false.
355 // Otherwise, if one of the intervals being joined is a physreg, this method
356 // always canonicalizes DstInt to be it. The output "SrcInt" will not have
357 // been modified, so we can use this information below to update aliases.
358 bool Swapped = false;
359 if (JoinIntervals(DstInt, SrcInt, Swapped)) {
361 // Result of the copy is dead. Propagate this property.
363 assert(MRegisterInfo::isPhysicalRegister(repSrcReg) &&
364 "Live-in must be a physical register!");
365 // Live-in to the function but dead. Remove it from entry live-in set.
366 // JoinIntervals may end up swapping the two intervals.
367 mf_->begin()->removeLiveIn(repSrcReg);
369 MachineInstr *SrcMI = li_->getInstructionFromIndex(SrcStart);
371 MachineOperand *mops = findDefOperand(SrcMI, repSrcReg);
378 if (isShorten || isDead) {
379 // Shorten the destination live interval.
381 SrcInt.removeRange(RemoveStart, RemoveEnd);
384 // Coalescing failed.
386 // If we can eliminate the copy without merging the live ranges, do so now.
387 if (!isExtSubReg && AdjustCopiesBackFrom(SrcInt, DstInt, CopyMI))
390 // Otherwise, we are unable to join the intervals.
391 DOUT << "Interference!\n";
395 LiveInterval *ResSrcInt = &SrcInt;
396 LiveInterval *ResDstInt = &DstInt;
398 std::swap(repSrcReg, repDstReg);
399 std::swap(ResSrcInt, ResDstInt);
401 assert(MRegisterInfo::isVirtualRegister(repSrcReg) &&
402 "LiveInterval::join didn't work right!");
404 // If we're about to merge live ranges into a physical register live range,
405 // we have to update any aliased register's live ranges to indicate that they
406 // have clobbered values for this range.
407 if (MRegisterInfo::isPhysicalRegister(repDstReg)) {
408 // Unset unnecessary kills.
409 if (!ResDstInt->containsOneValue()) {
410 for (LiveInterval::Ranges::const_iterator I = ResSrcInt->begin(),
411 E = ResSrcInt->end(); I != E; ++I)
412 unsetRegisterKills(I->start, I->end, repDstReg);
415 // If this is a extract_subreg where dst is a physical register, e.g.
416 // cl = EXTRACT_SUBREG reg1024, 1
417 // then create and update the actual physical register allocated to RHS.
419 unsigned CopyIdx = li_->getInstructionIndex(CopyMI);
421 ResDstInt->getLiveRangeContaining(li_->getUseIndex(CopyIdx))->valno;
422 LiveInterval &RealDstInt = li_->getOrCreateInterval(RealDstReg);
423 VNInfo *ValNo = RealDstInt.getNextValue(DstValNo->def, DstValNo->reg,
424 li_->getVNInfoAllocator());
425 RealDstInt.addKills(ValNo, DstValNo->kills);
426 RealDstInt.MergeValueInAsValue(*ResDstInt, DstValNo, ValNo);
427 repDstReg = RealDstReg;
430 // Update the liveintervals of sub-registers.
431 for (const unsigned *AS = mri_->getSubRegisters(repDstReg); *AS; ++AS)
432 li_->getOrCreateInterval(*AS).MergeInClobberRanges(*ResSrcInt,
433 li_->getVNInfoAllocator());
435 // Merge use info if the destination is a virtual register.
436 LiveVariables::VarInfo& dVI = lv_->getVarInfo(repDstReg);
437 LiveVariables::VarInfo& sVI = lv_->getVarInfo(repSrcReg);
438 dVI.NumUses += sVI.NumUses;
441 // Remember these liveintervals have been joined.
442 JoinedLIs.set(repSrcReg - MRegisterInfo::FirstVirtualRegister);
443 if (MRegisterInfo::isVirtualRegister(repDstReg))
444 JoinedLIs.set(repDstReg - MRegisterInfo::FirstVirtualRegister);
446 if (isExtSubReg && !SrcIsPhys && !DstIsPhys) {
448 // Make sure we allocate the larger super-register.
449 ResSrcInt->Copy(*ResDstInt, li_->getVNInfoAllocator());
450 std::swap(repSrcReg, repDstReg);
451 std::swap(ResSrcInt, ResDstInt);
453 SubRegIdxes.push_back(std::make_pair(repSrcReg,
454 CopyMI->getOperand(2).getImm()));
457 DOUT << "\n\t\tJoined. Result = "; ResDstInt->print(DOUT, mri_);
460 // repSrcReg is guarateed to be the register whose live interval that is
462 li_->removeInterval(repSrcReg);
463 r2rMap_[repSrcReg] = repDstReg;
465 // Finally, delete the copy instruction.
466 li_->RemoveMachineInstrFromMaps(CopyMI);
467 CopyMI->eraseFromParent();
473 /// ComputeUltimateVN - Assuming we are going to join two live intervals,
474 /// compute what the resultant value numbers for each value in the input two
475 /// ranges will be. This is complicated by copies between the two which can
476 /// and will commonly cause multiple value numbers to be merged into one.
478 /// VN is the value number that we're trying to resolve. InstDefiningValue
479 /// keeps track of the new InstDefiningValue assignment for the result
480 /// LiveInterval. ThisFromOther/OtherFromThis are sets that keep track of
481 /// whether a value in this or other is a copy from the opposite set.
482 /// ThisValNoAssignments/OtherValNoAssignments keep track of value #'s that have
483 /// already been assigned.
485 /// ThisFromOther[x] - If x is defined as a copy from the other interval, this
486 /// contains the value number the copy is from.
488 static unsigned ComputeUltimateVN(VNInfo *VNI,
489 SmallVector<VNInfo*, 16> &NewVNInfo,
490 DenseMap<VNInfo*, VNInfo*> &ThisFromOther,
491 DenseMap<VNInfo*, VNInfo*> &OtherFromThis,
492 SmallVector<int, 16> &ThisValNoAssignments,
493 SmallVector<int, 16> &OtherValNoAssignments) {
494 unsigned VN = VNI->id;
496 // If the VN has already been computed, just return it.
497 if (ThisValNoAssignments[VN] >= 0)
498 return ThisValNoAssignments[VN];
499 // assert(ThisValNoAssignments[VN] != -2 && "Cyclic case?");
501 // If this val is not a copy from the other val, then it must be a new value
502 // number in the destination.
503 DenseMap<VNInfo*, VNInfo*>::iterator I = ThisFromOther.find(VNI);
504 if (I == ThisFromOther.end()) {
505 NewVNInfo.push_back(VNI);
506 return ThisValNoAssignments[VN] = NewVNInfo.size()-1;
508 VNInfo *OtherValNo = I->second;
510 // Otherwise, this *is* a copy from the RHS. If the other side has already
511 // been computed, return it.
512 if (OtherValNoAssignments[OtherValNo->id] >= 0)
513 return ThisValNoAssignments[VN] = OtherValNoAssignments[OtherValNo->id];
515 // Mark this value number as currently being computed, then ask what the
516 // ultimate value # of the other value is.
517 ThisValNoAssignments[VN] = -2;
518 unsigned UltimateVN =
519 ComputeUltimateVN(OtherValNo, NewVNInfo, OtherFromThis, ThisFromOther,
520 OtherValNoAssignments, ThisValNoAssignments);
521 return ThisValNoAssignments[VN] = UltimateVN;
524 static bool InVector(VNInfo *Val, const SmallVector<VNInfo*, 8> &V) {
525 return std::find(V.begin(), V.end(), Val) != V.end();
528 /// SimpleJoin - Attempt to joint the specified interval into this one. The
529 /// caller of this method must guarantee that the RHS only contains a single
530 /// value number and that the RHS is not defined by a copy from this
531 /// interval. This returns false if the intervals are not joinable, or it
532 /// joins them and returns true.
533 bool SimpleRegisterCoalescing::SimpleJoin(LiveInterval &LHS, LiveInterval &RHS) {
534 assert(RHS.containsOneValue());
536 // Some number (potentially more than one) value numbers in the current
537 // interval may be defined as copies from the RHS. Scan the overlapping
538 // portions of the LHS and RHS, keeping track of this and looking for
539 // overlapping live ranges that are NOT defined as copies. If these exist, we
542 LiveInterval::iterator LHSIt = LHS.begin(), LHSEnd = LHS.end();
543 LiveInterval::iterator RHSIt = RHS.begin(), RHSEnd = RHS.end();
545 if (LHSIt->start < RHSIt->start) {
546 LHSIt = std::upper_bound(LHSIt, LHSEnd, RHSIt->start);
547 if (LHSIt != LHS.begin()) --LHSIt;
548 } else if (RHSIt->start < LHSIt->start) {
549 RHSIt = std::upper_bound(RHSIt, RHSEnd, LHSIt->start);
550 if (RHSIt != RHS.begin()) --RHSIt;
553 SmallVector<VNInfo*, 8> EliminatedLHSVals;
556 // Determine if these live intervals overlap.
557 bool Overlaps = false;
558 if (LHSIt->start <= RHSIt->start)
559 Overlaps = LHSIt->end > RHSIt->start;
561 Overlaps = RHSIt->end > LHSIt->start;
563 // If the live intervals overlap, there are two interesting cases: if the
564 // LHS interval is defined by a copy from the RHS, it's ok and we record
565 // that the LHS value # is the same as the RHS. If it's not, then we cannot
566 // coalesce these live ranges and we bail out.
568 // If we haven't already recorded that this value # is safe, check it.
569 if (!InVector(LHSIt->valno, EliminatedLHSVals)) {
570 // Copy from the RHS?
571 unsigned SrcReg = LHSIt->valno->reg;
572 if (rep(SrcReg) != RHS.reg)
573 return false; // Nope, bail out.
575 EliminatedLHSVals.push_back(LHSIt->valno);
578 // We know this entire LHS live range is okay, so skip it now.
579 if (++LHSIt == LHSEnd) break;
583 if (LHSIt->end < RHSIt->end) {
584 if (++LHSIt == LHSEnd) break;
586 // One interesting case to check here. It's possible that we have
587 // something like "X3 = Y" which defines a new value number in the LHS,
588 // and is the last use of this liverange of the RHS. In this case, we
589 // want to notice this copy (so that it gets coalesced away) even though
590 // the live ranges don't actually overlap.
591 if (LHSIt->start == RHSIt->end) {
592 if (InVector(LHSIt->valno, EliminatedLHSVals)) {
593 // We already know that this value number is going to be merged in
594 // if coalescing succeeds. Just skip the liverange.
595 if (++LHSIt == LHSEnd) break;
597 // Otherwise, if this is a copy from the RHS, mark it as being merged
599 if (rep(LHSIt->valno->reg) == RHS.reg) {
600 EliminatedLHSVals.push_back(LHSIt->valno);
602 // We know this entire LHS live range is okay, so skip it now.
603 if (++LHSIt == LHSEnd) break;
608 if (++RHSIt == RHSEnd) break;
612 // If we got here, we know that the coalescing will be successful and that
613 // the value numbers in EliminatedLHSVals will all be merged together. Since
614 // the most common case is that EliminatedLHSVals has a single number, we
615 // optimize for it: if there is more than one value, we merge them all into
616 // the lowest numbered one, then handle the interval as if we were merging
617 // with one value number.
619 if (EliminatedLHSVals.size() > 1) {
620 // Loop through all the equal value numbers merging them into the smallest
622 VNInfo *Smallest = EliminatedLHSVals[0];
623 for (unsigned i = 1, e = EliminatedLHSVals.size(); i != e; ++i) {
624 if (EliminatedLHSVals[i]->id < Smallest->id) {
625 // Merge the current notion of the smallest into the smaller one.
626 LHS.MergeValueNumberInto(Smallest, EliminatedLHSVals[i]);
627 Smallest = EliminatedLHSVals[i];
629 // Merge into the smallest.
630 LHS.MergeValueNumberInto(EliminatedLHSVals[i], Smallest);
635 assert(!EliminatedLHSVals.empty() && "No copies from the RHS?");
636 LHSValNo = EliminatedLHSVals[0];
639 // Okay, now that there is a single LHS value number that we're merging the
640 // RHS into, update the value number info for the LHS to indicate that the
641 // value number is defined where the RHS value number was.
642 const VNInfo *VNI = RHS.getValNumInfo(0);
643 LHSValNo->def = VNI->def;
644 LHSValNo->reg = VNI->reg;
646 // Okay, the final step is to loop over the RHS live intervals, adding them to
648 LHS.addKills(LHSValNo, VNI->kills);
649 LHS.MergeRangesInAsValue(RHS, LHSValNo);
650 LHS.weight += RHS.weight;
651 if (RHS.preference && !LHS.preference)
652 LHS.preference = RHS.preference;
657 /// JoinIntervals - Attempt to join these two intervals. On failure, this
658 /// returns false. Otherwise, if one of the intervals being joined is a
659 /// physreg, this method always canonicalizes LHS to be it. The output
660 /// "RHS" will not have been modified, so we can use this information
661 /// below to update aliases.
662 bool SimpleRegisterCoalescing::JoinIntervals(LiveInterval &LHS,
663 LiveInterval &RHS, bool &Swapped) {
664 // Compute the final value assignment, assuming that the live ranges can be
666 SmallVector<int, 16> LHSValNoAssignments;
667 SmallVector<int, 16> RHSValNoAssignments;
668 DenseMap<VNInfo*, VNInfo*> LHSValsDefinedFromRHS;
669 DenseMap<VNInfo*, VNInfo*> RHSValsDefinedFromLHS;
670 SmallVector<VNInfo*, 16> NewVNInfo;
672 // If a live interval is a physical register, conservatively check if any
673 // of its sub-registers is overlapping the live interval of the virtual
674 // register. If so, do not coalesce.
675 if (MRegisterInfo::isPhysicalRegister(LHS.reg) &&
676 *mri_->getSubRegisters(LHS.reg)) {
677 for (const unsigned* SR = mri_->getSubRegisters(LHS.reg); *SR; ++SR)
678 if (li_->hasInterval(*SR) && RHS.overlaps(li_->getInterval(*SR))) {
679 DOUT << "Interfere with sub-register ";
680 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
683 } else if (MRegisterInfo::isPhysicalRegister(RHS.reg) &&
684 *mri_->getSubRegisters(RHS.reg)) {
685 for (const unsigned* SR = mri_->getSubRegisters(RHS.reg); *SR; ++SR)
686 if (li_->hasInterval(*SR) && LHS.overlaps(li_->getInterval(*SR))) {
687 DOUT << "Interfere with sub-register ";
688 DEBUG(li_->getInterval(*SR).print(DOUT, mri_));
693 // Compute ultimate value numbers for the LHS and RHS values.
694 if (RHS.containsOneValue()) {
695 // Copies from a liveinterval with a single value are simple to handle and
696 // very common, handle the special case here. This is important, because
697 // often RHS is small and LHS is large (e.g. a physreg).
699 // Find out if the RHS is defined as a copy from some value in the LHS.
700 int RHSVal0DefinedFromLHS = -1;
702 VNInfo *RHSValNoInfo = NULL;
703 VNInfo *RHSValNoInfo0 = RHS.getValNumInfo(0);
704 unsigned RHSSrcReg = RHSValNoInfo0->reg;
705 if ((RHSSrcReg == 0 || rep(RHSSrcReg) != LHS.reg)) {
706 // If RHS is not defined as a copy from the LHS, we can use simpler and
707 // faster checks to see if the live ranges are coalescable. This joiner
708 // can't swap the LHS/RHS intervals though.
709 if (!MRegisterInfo::isPhysicalRegister(RHS.reg)) {
710 return SimpleJoin(LHS, RHS);
712 RHSValNoInfo = RHSValNoInfo0;
715 // It was defined as a copy from the LHS, find out what value # it is.
716 RHSValNoInfo = LHS.getLiveRangeContaining(RHSValNoInfo0->def-1)->valno;
717 RHSValID = RHSValNoInfo->id;
718 RHSVal0DefinedFromLHS = RHSValID;
721 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
722 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
723 NewVNInfo.resize(LHS.getNumValNums(), NULL);
725 // Okay, *all* of the values in LHS that are defined as a copy from RHS
726 // should now get updated.
727 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
730 unsigned VN = VNI->id;
731 if (unsigned LHSSrcReg = VNI->reg) {
732 if (rep(LHSSrcReg) != RHS.reg) {
733 // If this is not a copy from the RHS, its value number will be
734 // unmodified by the coalescing.
736 LHSValNoAssignments[VN] = VN;
737 } else if (RHSValID == -1) {
738 // Otherwise, it is a copy from the RHS, and we don't already have a
739 // value# for it. Keep the current value number, but remember it.
740 LHSValNoAssignments[VN] = RHSValID = VN;
741 NewVNInfo[VN] = RHSValNoInfo;
742 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
744 // Otherwise, use the specified value #.
745 LHSValNoAssignments[VN] = RHSValID;
746 if (VN == (unsigned)RHSValID) { // Else this val# is dead.
747 NewVNInfo[VN] = RHSValNoInfo;
748 LHSValsDefinedFromRHS[VNI] = RHSValNoInfo0;
753 LHSValNoAssignments[VN] = VN;
757 assert(RHSValID != -1 && "Didn't find value #?");
758 RHSValNoAssignments[0] = RHSValID;
759 if (RHSVal0DefinedFromLHS != -1) {
760 // This path doesn't go through ComputeUltimateVN so just set
762 RHSValsDefinedFromLHS[RHSValNoInfo0] = (VNInfo*)1;
765 // Loop over the value numbers of the LHS, seeing if any are defined from
767 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
770 unsigned ValSrcReg = VNI->reg;
771 if (ValSrcReg == 0) // Src not defined by a copy?
774 // DstReg is known to be a register in the LHS interval. If the src is
775 // from the RHS interval, we can use its value #.
776 if (rep(ValSrcReg) != RHS.reg)
779 // Figure out the value # from the RHS.
780 LHSValsDefinedFromRHS[VNI] = RHS.getLiveRangeContaining(VNI->def-1)->valno;
783 // Loop over the value numbers of the RHS, seeing if any are defined from
785 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
788 unsigned ValSrcReg = VNI->reg;
789 if (ValSrcReg == 0) // Src not defined by a copy?
792 // DstReg is known to be a register in the RHS interval. If the src is
793 // from the LHS interval, we can use its value #.
794 if (rep(ValSrcReg) != LHS.reg)
797 // Figure out the value # from the LHS.
798 RHSValsDefinedFromLHS[VNI]= LHS.getLiveRangeContaining(VNI->def-1)->valno;
801 LHSValNoAssignments.resize(LHS.getNumValNums(), -1);
802 RHSValNoAssignments.resize(RHS.getNumValNums(), -1);
803 NewVNInfo.reserve(LHS.getNumValNums() + RHS.getNumValNums());
805 for (LiveInterval::vni_iterator i = LHS.vni_begin(), e = LHS.vni_end();
808 unsigned VN = VNI->id;
809 if (LHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
811 ComputeUltimateVN(VNI, NewVNInfo,
812 LHSValsDefinedFromRHS, RHSValsDefinedFromLHS,
813 LHSValNoAssignments, RHSValNoAssignments);
815 for (LiveInterval::vni_iterator i = RHS.vni_begin(), e = RHS.vni_end();
818 unsigned VN = VNI->id;
819 if (RHSValNoAssignments[VN] >= 0 || VNI->def == ~1U)
821 // If this value number isn't a copy from the LHS, it's a new number.
822 if (RHSValsDefinedFromLHS.find(VNI) == RHSValsDefinedFromLHS.end()) {
823 NewVNInfo.push_back(VNI);
824 RHSValNoAssignments[VN] = NewVNInfo.size()-1;
828 ComputeUltimateVN(VNI, NewVNInfo,
829 RHSValsDefinedFromLHS, LHSValsDefinedFromRHS,
830 RHSValNoAssignments, LHSValNoAssignments);
834 // Armed with the mappings of LHS/RHS values to ultimate values, walk the
835 // interval lists to see if these intervals are coalescable.
836 LiveInterval::const_iterator I = LHS.begin();
837 LiveInterval::const_iterator IE = LHS.end();
838 LiveInterval::const_iterator J = RHS.begin();
839 LiveInterval::const_iterator JE = RHS.end();
841 // Skip ahead until the first place of potential sharing.
842 if (I->start < J->start) {
843 I = std::upper_bound(I, IE, J->start);
844 if (I != LHS.begin()) --I;
845 } else if (J->start < I->start) {
846 J = std::upper_bound(J, JE, I->start);
847 if (J != RHS.begin()) --J;
851 // Determine if these two live ranges overlap.
853 if (I->start < J->start) {
854 Overlaps = I->end > J->start;
856 Overlaps = J->end > I->start;
859 // If so, check value # info to determine if they are really different.
861 // If the live range overlap will map to the same value number in the
862 // result liverange, we can still coalesce them. If not, we can't.
863 if (LHSValNoAssignments[I->valno->id] !=
864 RHSValNoAssignments[J->valno->id])
868 if (I->end < J->end) {
877 // If we get here, we know that we can coalesce the live ranges. Ask the
878 // intervals to coalesce themselves now.
879 if ((RHS.ranges.size() > LHS.ranges.size() &&
880 MRegisterInfo::isVirtualRegister(LHS.reg)) ||
881 MRegisterInfo::isPhysicalRegister(RHS.reg)) {
882 // Update kill info. Some live ranges are extended due to copy coalescing.
883 for (DenseMap<VNInfo*, VNInfo*>::iterator I = LHSValsDefinedFromRHS.begin(),
884 E = LHSValsDefinedFromRHS.end(); I != E; ++I) {
885 VNInfo *VNI = I->first;
886 unsigned LHSValID = LHSValNoAssignments[VNI->id];
887 LiveInterval::removeKill(NewVNInfo[LHSValID], VNI->def);
888 RHS.addKills(NewVNInfo[LHSValID], VNI->kills);
891 RHS.join(LHS, &RHSValNoAssignments[0], &LHSValNoAssignments[0], NewVNInfo);
894 // Update kill info. Some live ranges are extended due to copy coalescing.
895 for (DenseMap<VNInfo*, VNInfo*>::iterator I = RHSValsDefinedFromLHS.begin(),
896 E = RHSValsDefinedFromLHS.end(); I != E; ++I) {
897 VNInfo *VNI = I->first;
898 unsigned RHSValID = RHSValNoAssignments[VNI->id];
899 LiveInterval::removeKill(NewVNInfo[RHSValID], VNI->def);
900 LHS.addKills(NewVNInfo[RHSValID], VNI->kills);
903 LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo);
910 // DepthMBBCompare - Comparison predicate that sort first based on the loop
911 // depth of the basic block (the unsigned), and then on the MBB number.
912 struct DepthMBBCompare {
913 typedef std::pair<unsigned, MachineBasicBlock*> DepthMBBPair;
914 bool operator()(const DepthMBBPair &LHS, const DepthMBBPair &RHS) const {
915 if (LHS.first > RHS.first) return true; // Deeper loops first
916 return LHS.first == RHS.first &&
917 LHS.second->getNumber() < RHS.second->getNumber();
922 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
923 std::vector<CopyRec> *TryAgain, bool PhysOnly) {
924 DOUT << ((Value*)MBB->getBasicBlock())->getName() << ":\n";
926 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
928 MachineInstr *Inst = MII++;
930 // If this isn't a copy nor a extract_subreg, we can't join intervals.
931 unsigned SrcReg, DstReg;
932 if (Inst->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
933 DstReg = Inst->getOperand(0).getReg();
934 SrcReg = Inst->getOperand(1).getReg();
935 } else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg))
938 bool Done = JoinCopy(Inst, SrcReg, DstReg, PhysOnly);
939 if (TryAgain && !Done)
940 TryAgain->push_back(getCopyRec(Inst, SrcReg, DstReg));
944 void SimpleRegisterCoalescing::joinIntervals() {
945 DOUT << "********** JOINING INTERVALS ***********\n";
947 JoinedLIs.resize(li_->getNumIntervals());
950 std::vector<CopyRec> TryAgainList;
951 const LoopInfo &LI = getAnalysis<LoopInfo>();
952 if (LI.begin() == LI.end()) {
953 // If there are no loops in the function, join intervals in function order.
954 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
956 CopyCoalesceInMBB(I, &TryAgainList);
958 // Otherwise, join intervals in inner loops before other intervals.
959 // Unfortunately we can't just iterate over loop hierarchy here because
960 // there may be more MBB's than BB's. Collect MBB's for sorting.
962 // Join intervals in the function prolog first. We want to join physical
963 // registers with virtual registers before the intervals got too long.
964 std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
965 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I)
966 MBBs.push_back(std::make_pair(LI.getLoopDepth(I->getBasicBlock()), I));
968 // Sort by loop depth.
969 std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
971 // Finally, join intervals in loop nest order.
972 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
973 CopyCoalesceInMBB(MBBs[i].second, NULL, true);
974 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
975 CopyCoalesceInMBB(MBBs[i].second, &TryAgainList, false);
978 // Joining intervals can allow other intervals to be joined. Iteratively join
979 // until we make no progress.
980 bool ProgressMade = true;
981 while (ProgressMade) {
982 ProgressMade = false;
984 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
985 CopyRec &TheCopy = TryAgainList[i];
987 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
988 TheCopy.MI = 0; // Mark this one as done.
994 // Some live range has been lengthened due to colaescing, eliminate the
995 // unnecessary kills.
996 int RegNum = JoinedLIs.find_first();
997 while (RegNum != -1) {
998 unsigned Reg = RegNum + MRegisterInfo::FirstVirtualRegister;
999 unsigned repReg = rep(Reg);
1000 LiveInterval &LI = li_->getInterval(repReg);
1001 LiveVariables::VarInfo& svi = lv_->getVarInfo(Reg);
1002 for (unsigned i = 0, e = svi.Kills.size(); i != e; ++i) {
1003 MachineInstr *Kill = svi.Kills[i];
1004 // Suppose vr1 = op vr2, x
1005 // and vr1 and vr2 are coalesced. vr2 should still be marked kill
1006 // unless it is a two-address operand.
1007 if (li_->isRemoved(Kill) || hasRegisterDef(Kill, repReg))
1009 if (LI.liveAt(li_->getInstructionIndex(Kill) + InstrSlots::NUM))
1010 unsetRegisterKill(Kill, repReg);
1012 RegNum = JoinedLIs.find_next(RegNum);
1015 DOUT << "*** Register mapping ***\n";
1016 for (int i = 0, e = r2rMap_.size(); i != e; ++i)
1018 DOUT << " reg " << i << " -> ";
1019 DEBUG(printRegName(r2rMap_[i]));
1024 /// Return true if the two specified registers belong to different register
1025 /// classes. The registers may be either phys or virt regs.
1026 bool SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA,
1027 unsigned RegB) const {
1029 // Get the register classes for the first reg.
1030 if (MRegisterInfo::isPhysicalRegister(RegA)) {
1031 assert(MRegisterInfo::isVirtualRegister(RegB) &&
1032 "Shouldn't consider two physregs!");
1033 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1036 // Compare against the regclass for the second reg.
1037 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1038 if (MRegisterInfo::isVirtualRegister(RegB))
1039 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1041 return !RegClass->contains(RegB);
1044 /// lastRegisterUse - Returns the last use of the specific register between
1045 /// cycles Start and End. It also returns the use operand by reference. It
1046 /// returns NULL if there are no uses.
1048 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
1049 MachineOperand *&MOU) {
1050 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1053 // Skip deleted instructions
1054 MachineInstr *MI = li_->getInstructionFromIndex(e);
1055 while ((e - InstrSlots::NUM) >= s && !MI) {
1056 e -= InstrSlots::NUM;
1057 MI = li_->getInstructionFromIndex(e);
1059 if (e < s || MI == NULL)
1062 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1063 MachineOperand &MO = MI->getOperand(i);
1064 if (MO.isRegister() && MO.isUse() && MO.getReg() &&
1065 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1071 e -= InstrSlots::NUM;
1078 /// findDefOperand - Returns the MachineOperand that is a def of the specific
1079 /// register. It returns NULL if the def is not found.
1080 MachineOperand *SimpleRegisterCoalescing::findDefOperand(MachineInstr *MI, unsigned Reg) {
1081 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1082 MachineOperand &MO = MI->getOperand(i);
1083 if (MO.isRegister() && MO.isDef() &&
1084 mri_->regsOverlap(rep(MO.getReg()), Reg))
1090 /// unsetRegisterKill - Unset IsKill property of all uses of specific register
1091 /// of the specific instruction.
1092 void SimpleRegisterCoalescing::unsetRegisterKill(MachineInstr *MI, unsigned Reg) {
1093 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1094 MachineOperand &MO = MI->getOperand(i);
1095 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1096 mri_->regsOverlap(rep(MO.getReg()), Reg))
1101 /// unsetRegisterKills - Unset IsKill property of all uses of specific register
1102 /// between cycles Start and End.
1103 void SimpleRegisterCoalescing::unsetRegisterKills(unsigned Start, unsigned End,
1105 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
1108 // Skip deleted instructions
1109 MachineInstr *MI = li_->getInstructionFromIndex(e);
1110 while ((e - InstrSlots::NUM) >= s && !MI) {
1111 e -= InstrSlots::NUM;
1112 MI = li_->getInstructionFromIndex(e);
1114 if (e < s || MI == NULL)
1117 for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
1118 MachineOperand &MO = MI->getOperand(i);
1119 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
1120 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1125 e -= InstrSlots::NUM;
1129 /// hasRegisterDef - True if the instruction defines the specific register.
1131 bool SimpleRegisterCoalescing::hasRegisterDef(MachineInstr *MI, unsigned Reg) {
1132 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1133 MachineOperand &MO = MI->getOperand(i);
1134 if (MO.isRegister() && MO.isDef() &&
1135 mri_->regsOverlap(rep(MO.getReg()), Reg))
1141 void SimpleRegisterCoalescing::printRegName(unsigned reg) const {
1142 if (MRegisterInfo::isPhysicalRegister(reg))
1143 cerr << mri_->getName(reg);
1145 cerr << "%reg" << reg;
1148 void SimpleRegisterCoalescing::releaseMemory() {
1151 SubRegIdxes.clear();
1154 static bool isZeroLengthInterval(LiveInterval *li) {
1155 for (LiveInterval::Ranges::const_iterator
1156 i = li->ranges.begin(), e = li->ranges.end(); i != e; ++i)
1157 if (i->end - i->start > LiveIntervals::InstrSlots::NUM)
1162 bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
1164 tm_ = &fn.getTarget();
1165 mri_ = tm_->getRegisterInfo();
1166 tii_ = tm_->getInstrInfo();
1167 li_ = &getAnalysis<LiveIntervals>();
1168 lv_ = &getAnalysis<LiveVariables>();
1170 DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
1171 << "********** Function: "
1172 << ((Value*)mf_->getFunction())->getName() << '\n';
1174 allocatableRegs_ = mri_->getAllocatableSet(fn);
1175 for (MRegisterInfo::regclass_iterator I = mri_->regclass_begin(),
1176 E = mri_->regclass_end(); I != E; ++I)
1177 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
1179 SSARegMap *RegMap = mf_->getSSARegMap();
1180 r2rMap_.grow(RegMap->getLastVirtReg());
1182 // Join (coalesce) intervals if requested.
1183 if (EnableJoining) {
1185 DOUT << "********** INTERVALS POST JOINING **********\n";
1186 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1187 I->second.print(DOUT, mri_);
1191 // Track coalesced sub-registers.
1192 while (!SubRegIdxes.empty()) {
1193 std::pair<unsigned, unsigned> RI = SubRegIdxes.back();
1194 SubRegIdxes.pop_back();
1195 mf_->getSSARegMap()->setIsSubRegister(RI.first, rep(RI.first), RI.second);
1199 // perform a final pass over the instructions and compute spill
1200 // weights, coalesce virtual registers and remove identity moves.
1201 const LoopInfo &loopInfo = getAnalysis<LoopInfo>();
1203 for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
1204 mbbi != mbbe; ++mbbi) {
1205 MachineBasicBlock* mbb = mbbi;
1206 unsigned loopDepth = loopInfo.getLoopDepth(mbb->getBasicBlock());
1208 for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
1210 // if the move will be an identity move delete it
1211 unsigned srcReg, dstReg, RegRep;
1212 if (tii_->isMoveInstr(*mii, srcReg, dstReg) &&
1213 (RegRep = rep(srcReg)) == rep(dstReg)) {
1214 // remove from def list
1215 LiveInterval &RegInt = li_->getOrCreateInterval(RegRep);
1216 MachineOperand *MO = mii->findRegisterDefOperand(dstReg);
1217 // If def of this move instruction is dead, remove its live range from
1218 // the dstination register's live interval.
1220 unsigned MoveIdx = li_->getDefIndex(li_->getInstructionIndex(mii));
1221 LiveInterval::iterator MLR = RegInt.FindLiveRangeContaining(MoveIdx);
1222 RegInt.removeRange(MLR->start, MoveIdx+1);
1224 li_->removeInterval(RegRep);
1226 li_->RemoveMachineInstrFromMaps(mii);
1227 mii = mbbi->erase(mii);
1230 SmallSet<unsigned, 4> UniqueUses;
1231 for (unsigned i = 0, e = mii->getNumOperands(); i != e; ++i) {
1232 const MachineOperand &mop = mii->getOperand(i);
1233 if (mop.isRegister() && mop.getReg() &&
1234 MRegisterInfo::isVirtualRegister(mop.getReg())) {
1235 // replace register with representative register
1236 unsigned OrigReg = mop.getReg();
1237 unsigned reg = rep(OrigReg);
1238 // Don't rewrite if it is a sub-register of a virtual register.
1239 if (!RegMap->isSubRegister(OrigReg))
1240 mii->getOperand(i).setReg(reg);
1241 else if (MRegisterInfo::isPhysicalRegister(reg))
1242 mii->getOperand(i).setReg(mri_->getSubReg(reg,
1243 RegMap->getSubRegisterIndex(OrigReg)));
1245 // Multiple uses of reg by the same instruction. It should not
1246 // contribute to spill weight again.
1247 if (UniqueUses.count(reg) != 0)
1249 LiveInterval &RegInt = li_->getInterval(reg);
1250 float w = (mop.isUse()+mop.isDef()) * powf(10.0F, (float)loopDepth);
1252 UniqueUses.insert(reg);
1260 for (LiveIntervals::iterator I = li_->begin(), E = li_->end(); I != E; ++I) {
1261 LiveInterval &LI = I->second;
1262 if (MRegisterInfo::isVirtualRegister(LI.reg)) {
1263 // If the live interval length is essentially zero, i.e. in every live
1264 // range the use follows def immediately, it doesn't make sense to spill
1265 // it and hope it will be easier to allocate for this li.
1266 if (isZeroLengthInterval(&LI))
1267 LI.weight = HUGE_VALF;
1269 // Slightly prefer live interval that has been assigned a preferred reg.
1273 // Divide the weight of the interval by its size. This encourages
1274 // spilling of intervals that are large and have few uses, and
1275 // discourages spilling of small intervals with many uses.
1276 LI.weight /= LI.getSize();
1284 /// print - Implement the dump method.
1285 void SimpleRegisterCoalescing::print(std::ostream &O, const Module* m) const {
1289 RegisterCoalescer* llvm::createSimpleRegisterCoalescer() {
1290 return new SimpleRegisterCoalescing();
1293 // Make sure that anything that uses RegisterCoalescer pulls in this file...
1294 DEFINING_FILE_FOR(SimpleRegisterCoalescing)