1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
36 /// InitLibcallNames - Set default libcall names.
38 static void InitLibcallNames(const char **Names) {
39 Names[RTLIB::SHL_I16] = "__ashlhi3";
40 Names[RTLIB::SHL_I32] = "__ashlsi3";
41 Names[RTLIB::SHL_I64] = "__ashldi3";
42 Names[RTLIB::SHL_I128] = "__ashlti3";
43 Names[RTLIB::SRL_I16] = "__lshrhi3";
44 Names[RTLIB::SRL_I32] = "__lshrsi3";
45 Names[RTLIB::SRL_I64] = "__lshrdi3";
46 Names[RTLIB::SRL_I128] = "__lshrti3";
47 Names[RTLIB::SRA_I16] = "__ashrhi3";
48 Names[RTLIB::SRA_I32] = "__ashrsi3";
49 Names[RTLIB::SRA_I64] = "__ashrdi3";
50 Names[RTLIB::SRA_I128] = "__ashrti3";
51 Names[RTLIB::MUL_I8] = "__mulqi3";
52 Names[RTLIB::MUL_I16] = "__mulhi3";
53 Names[RTLIB::MUL_I32] = "__mulsi3";
54 Names[RTLIB::MUL_I64] = "__muldi3";
55 Names[RTLIB::MUL_I128] = "__multi3";
56 Names[RTLIB::MULO_I32] = "__mulosi4";
57 Names[RTLIB::MULO_I64] = "__mulodi4";
58 Names[RTLIB::MULO_I128] = "__muloti4";
59 Names[RTLIB::SDIV_I8] = "__divqi3";
60 Names[RTLIB::SDIV_I16] = "__divhi3";
61 Names[RTLIB::SDIV_I32] = "__divsi3";
62 Names[RTLIB::SDIV_I64] = "__divdi3";
63 Names[RTLIB::SDIV_I128] = "__divti3";
64 Names[RTLIB::UDIV_I8] = "__udivqi3";
65 Names[RTLIB::UDIV_I16] = "__udivhi3";
66 Names[RTLIB::UDIV_I32] = "__udivsi3";
67 Names[RTLIB::UDIV_I64] = "__udivdi3";
68 Names[RTLIB::UDIV_I128] = "__udivti3";
69 Names[RTLIB::SREM_I8] = "__modqi3";
70 Names[RTLIB::SREM_I16] = "__modhi3";
71 Names[RTLIB::SREM_I32] = "__modsi3";
72 Names[RTLIB::SREM_I64] = "__moddi3";
73 Names[RTLIB::SREM_I128] = "__modti3";
74 Names[RTLIB::UREM_I8] = "__umodqi3";
75 Names[RTLIB::UREM_I16] = "__umodhi3";
76 Names[RTLIB::UREM_I32] = "__umodsi3";
77 Names[RTLIB::UREM_I64] = "__umoddi3";
78 Names[RTLIB::UREM_I128] = "__umodti3";
80 // These are generally not available.
81 Names[RTLIB::SDIVREM_I8] = 0;
82 Names[RTLIB::SDIVREM_I16] = 0;
83 Names[RTLIB::SDIVREM_I32] = 0;
84 Names[RTLIB::SDIVREM_I64] = 0;
85 Names[RTLIB::SDIVREM_I128] = 0;
86 Names[RTLIB::UDIVREM_I8] = 0;
87 Names[RTLIB::UDIVREM_I16] = 0;
88 Names[RTLIB::UDIVREM_I32] = 0;
89 Names[RTLIB::UDIVREM_I64] = 0;
90 Names[RTLIB::UDIVREM_I128] = 0;
92 Names[RTLIB::NEG_I32] = "__negsi2";
93 Names[RTLIB::NEG_I64] = "__negdi2";
94 Names[RTLIB::ADD_F32] = "__addsf3";
95 Names[RTLIB::ADD_F64] = "__adddf3";
96 Names[RTLIB::ADD_F80] = "__addxf3";
97 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
98 Names[RTLIB::SUB_F32] = "__subsf3";
99 Names[RTLIB::SUB_F64] = "__subdf3";
100 Names[RTLIB::SUB_F80] = "__subxf3";
101 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
102 Names[RTLIB::MUL_F32] = "__mulsf3";
103 Names[RTLIB::MUL_F64] = "__muldf3";
104 Names[RTLIB::MUL_F80] = "__mulxf3";
105 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
106 Names[RTLIB::DIV_F32] = "__divsf3";
107 Names[RTLIB::DIV_F64] = "__divdf3";
108 Names[RTLIB::DIV_F80] = "__divxf3";
109 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
110 Names[RTLIB::REM_F32] = "fmodf";
111 Names[RTLIB::REM_F64] = "fmod";
112 Names[RTLIB::REM_F80] = "fmodl";
113 Names[RTLIB::REM_PPCF128] = "fmodl";
114 Names[RTLIB::FMA_F32] = "fmaf";
115 Names[RTLIB::FMA_F64] = "fma";
116 Names[RTLIB::FMA_F80] = "fmal";
117 Names[RTLIB::FMA_PPCF128] = "fmal";
118 Names[RTLIB::POWI_F32] = "__powisf2";
119 Names[RTLIB::POWI_F64] = "__powidf2";
120 Names[RTLIB::POWI_F80] = "__powixf2";
121 Names[RTLIB::POWI_PPCF128] = "__powitf2";
122 Names[RTLIB::SQRT_F32] = "sqrtf";
123 Names[RTLIB::SQRT_F64] = "sqrt";
124 Names[RTLIB::SQRT_F80] = "sqrtl";
125 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
126 Names[RTLIB::LOG_F32] = "logf";
127 Names[RTLIB::LOG_F64] = "log";
128 Names[RTLIB::LOG_F80] = "logl";
129 Names[RTLIB::LOG_PPCF128] = "logl";
130 Names[RTLIB::LOG2_F32] = "log2f";
131 Names[RTLIB::LOG2_F64] = "log2";
132 Names[RTLIB::LOG2_F80] = "log2l";
133 Names[RTLIB::LOG2_PPCF128] = "log2l";
134 Names[RTLIB::LOG10_F32] = "log10f";
135 Names[RTLIB::LOG10_F64] = "log10";
136 Names[RTLIB::LOG10_F80] = "log10l";
137 Names[RTLIB::LOG10_PPCF128] = "log10l";
138 Names[RTLIB::EXP_F32] = "expf";
139 Names[RTLIB::EXP_F64] = "exp";
140 Names[RTLIB::EXP_F80] = "expl";
141 Names[RTLIB::EXP_PPCF128] = "expl";
142 Names[RTLIB::EXP2_F32] = "exp2f";
143 Names[RTLIB::EXP2_F64] = "exp2";
144 Names[RTLIB::EXP2_F80] = "exp2l";
145 Names[RTLIB::EXP2_PPCF128] = "exp2l";
146 Names[RTLIB::SIN_F32] = "sinf";
147 Names[RTLIB::SIN_F64] = "sin";
148 Names[RTLIB::SIN_F80] = "sinl";
149 Names[RTLIB::SIN_PPCF128] = "sinl";
150 Names[RTLIB::COS_F32] = "cosf";
151 Names[RTLIB::COS_F64] = "cos";
152 Names[RTLIB::COS_F80] = "cosl";
153 Names[RTLIB::COS_PPCF128] = "cosl";
154 Names[RTLIB::POW_F32] = "powf";
155 Names[RTLIB::POW_F64] = "pow";
156 Names[RTLIB::POW_F80] = "powl";
157 Names[RTLIB::POW_PPCF128] = "powl";
158 Names[RTLIB::CEIL_F32] = "ceilf";
159 Names[RTLIB::CEIL_F64] = "ceil";
160 Names[RTLIB::CEIL_F80] = "ceill";
161 Names[RTLIB::CEIL_PPCF128] = "ceill";
162 Names[RTLIB::TRUNC_F32] = "truncf";
163 Names[RTLIB::TRUNC_F64] = "trunc";
164 Names[RTLIB::TRUNC_F80] = "truncl";
165 Names[RTLIB::TRUNC_PPCF128] = "truncl";
166 Names[RTLIB::RINT_F32] = "rintf";
167 Names[RTLIB::RINT_F64] = "rint";
168 Names[RTLIB::RINT_F80] = "rintl";
169 Names[RTLIB::RINT_PPCF128] = "rintl";
170 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
171 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
172 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
173 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
174 Names[RTLIB::FLOOR_F32] = "floorf";
175 Names[RTLIB::FLOOR_F64] = "floor";
176 Names[RTLIB::FLOOR_F80] = "floorl";
177 Names[RTLIB::FLOOR_PPCF128] = "floorl";
178 Names[RTLIB::COPYSIGN_F32] = "copysignf";
179 Names[RTLIB::COPYSIGN_F64] = "copysign";
180 Names[RTLIB::COPYSIGN_F80] = "copysignl";
181 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
182 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
183 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
184 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
185 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
186 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
187 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
188 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
189 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
190 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
191 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
192 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
193 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
194 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
195 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
196 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
197 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
198 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
199 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
200 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
201 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
202 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
203 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
204 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
205 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
206 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
207 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
208 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
209 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
210 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
211 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
212 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
213 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
214 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
215 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
216 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
217 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
218 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
219 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
220 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
221 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
222 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
223 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
224 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
225 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
226 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
227 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
228 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
229 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
230 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
231 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
232 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
233 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
234 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
235 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
236 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
237 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
238 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
239 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
240 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
241 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
242 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
243 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
244 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
245 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
246 Names[RTLIB::OEQ_F32] = "__eqsf2";
247 Names[RTLIB::OEQ_F64] = "__eqdf2";
248 Names[RTLIB::UNE_F32] = "__nesf2";
249 Names[RTLIB::UNE_F64] = "__nedf2";
250 Names[RTLIB::OGE_F32] = "__gesf2";
251 Names[RTLIB::OGE_F64] = "__gedf2";
252 Names[RTLIB::OLT_F32] = "__ltsf2";
253 Names[RTLIB::OLT_F64] = "__ltdf2";
254 Names[RTLIB::OLE_F32] = "__lesf2";
255 Names[RTLIB::OLE_F64] = "__ledf2";
256 Names[RTLIB::OGT_F32] = "__gtsf2";
257 Names[RTLIB::OGT_F64] = "__gtdf2";
258 Names[RTLIB::UO_F32] = "__unordsf2";
259 Names[RTLIB::UO_F64] = "__unorddf2";
260 Names[RTLIB::O_F32] = "__unordsf2";
261 Names[RTLIB::O_F64] = "__unorddf2";
262 Names[RTLIB::MEMCPY] = "memcpy";
263 Names[RTLIB::MEMMOVE] = "memmove";
264 Names[RTLIB::MEMSET] = "memset";
265 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
266 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
267 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
268 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
269 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
270 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
271 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
272 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
273 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
274 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
275 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
276 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
277 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
278 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
279 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
280 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
281 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
282 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
283 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
284 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
285 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
286 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
287 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
288 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
289 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
290 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
291 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
292 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
293 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
294 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
295 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
296 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
297 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
300 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
302 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
303 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
304 CCs[i] = CallingConv::C;
308 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
309 /// UNKNOWN_LIBCALL if there is none.
310 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
311 if (OpVT == MVT::f32) {
312 if (RetVT == MVT::f64)
313 return FPEXT_F32_F64;
316 return UNKNOWN_LIBCALL;
319 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
320 /// UNKNOWN_LIBCALL if there is none.
321 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
322 if (RetVT == MVT::f32) {
323 if (OpVT == MVT::f64)
324 return FPROUND_F64_F32;
325 if (OpVT == MVT::f80)
326 return FPROUND_F80_F32;
327 if (OpVT == MVT::ppcf128)
328 return FPROUND_PPCF128_F32;
329 } else if (RetVT == MVT::f64) {
330 if (OpVT == MVT::f80)
331 return FPROUND_F80_F64;
332 if (OpVT == MVT::ppcf128)
333 return FPROUND_PPCF128_F64;
336 return UNKNOWN_LIBCALL;
339 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
340 /// UNKNOWN_LIBCALL if there is none.
341 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
342 if (OpVT == MVT::f32) {
343 if (RetVT == MVT::i8)
344 return FPTOSINT_F32_I8;
345 if (RetVT == MVT::i16)
346 return FPTOSINT_F32_I16;
347 if (RetVT == MVT::i32)
348 return FPTOSINT_F32_I32;
349 if (RetVT == MVT::i64)
350 return FPTOSINT_F32_I64;
351 if (RetVT == MVT::i128)
352 return FPTOSINT_F32_I128;
353 } else if (OpVT == MVT::f64) {
354 if (RetVT == MVT::i8)
355 return FPTOSINT_F64_I8;
356 if (RetVT == MVT::i16)
357 return FPTOSINT_F64_I16;
358 if (RetVT == MVT::i32)
359 return FPTOSINT_F64_I32;
360 if (RetVT == MVT::i64)
361 return FPTOSINT_F64_I64;
362 if (RetVT == MVT::i128)
363 return FPTOSINT_F64_I128;
364 } else if (OpVT == MVT::f80) {
365 if (RetVT == MVT::i32)
366 return FPTOSINT_F80_I32;
367 if (RetVT == MVT::i64)
368 return FPTOSINT_F80_I64;
369 if (RetVT == MVT::i128)
370 return FPTOSINT_F80_I128;
371 } else if (OpVT == MVT::ppcf128) {
372 if (RetVT == MVT::i32)
373 return FPTOSINT_PPCF128_I32;
374 if (RetVT == MVT::i64)
375 return FPTOSINT_PPCF128_I64;
376 if (RetVT == MVT::i128)
377 return FPTOSINT_PPCF128_I128;
379 return UNKNOWN_LIBCALL;
382 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
383 /// UNKNOWN_LIBCALL if there is none.
384 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
385 if (OpVT == MVT::f32) {
386 if (RetVT == MVT::i8)
387 return FPTOUINT_F32_I8;
388 if (RetVT == MVT::i16)
389 return FPTOUINT_F32_I16;
390 if (RetVT == MVT::i32)
391 return FPTOUINT_F32_I32;
392 if (RetVT == MVT::i64)
393 return FPTOUINT_F32_I64;
394 if (RetVT == MVT::i128)
395 return FPTOUINT_F32_I128;
396 } else if (OpVT == MVT::f64) {
397 if (RetVT == MVT::i8)
398 return FPTOUINT_F64_I8;
399 if (RetVT == MVT::i16)
400 return FPTOUINT_F64_I16;
401 if (RetVT == MVT::i32)
402 return FPTOUINT_F64_I32;
403 if (RetVT == MVT::i64)
404 return FPTOUINT_F64_I64;
405 if (RetVT == MVT::i128)
406 return FPTOUINT_F64_I128;
407 } else if (OpVT == MVT::f80) {
408 if (RetVT == MVT::i32)
409 return FPTOUINT_F80_I32;
410 if (RetVT == MVT::i64)
411 return FPTOUINT_F80_I64;
412 if (RetVT == MVT::i128)
413 return FPTOUINT_F80_I128;
414 } else if (OpVT == MVT::ppcf128) {
415 if (RetVT == MVT::i32)
416 return FPTOUINT_PPCF128_I32;
417 if (RetVT == MVT::i64)
418 return FPTOUINT_PPCF128_I64;
419 if (RetVT == MVT::i128)
420 return FPTOUINT_PPCF128_I128;
422 return UNKNOWN_LIBCALL;
425 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
426 /// UNKNOWN_LIBCALL if there is none.
427 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
428 if (OpVT == MVT::i32) {
429 if (RetVT == MVT::f32)
430 return SINTTOFP_I32_F32;
431 else if (RetVT == MVT::f64)
432 return SINTTOFP_I32_F64;
433 else if (RetVT == MVT::f80)
434 return SINTTOFP_I32_F80;
435 else if (RetVT == MVT::ppcf128)
436 return SINTTOFP_I32_PPCF128;
437 } else if (OpVT == MVT::i64) {
438 if (RetVT == MVT::f32)
439 return SINTTOFP_I64_F32;
440 else if (RetVT == MVT::f64)
441 return SINTTOFP_I64_F64;
442 else if (RetVT == MVT::f80)
443 return SINTTOFP_I64_F80;
444 else if (RetVT == MVT::ppcf128)
445 return SINTTOFP_I64_PPCF128;
446 } else if (OpVT == MVT::i128) {
447 if (RetVT == MVT::f32)
448 return SINTTOFP_I128_F32;
449 else if (RetVT == MVT::f64)
450 return SINTTOFP_I128_F64;
451 else if (RetVT == MVT::f80)
452 return SINTTOFP_I128_F80;
453 else if (RetVT == MVT::ppcf128)
454 return SINTTOFP_I128_PPCF128;
456 return UNKNOWN_LIBCALL;
459 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
460 /// UNKNOWN_LIBCALL if there is none.
461 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
462 if (OpVT == MVT::i32) {
463 if (RetVT == MVT::f32)
464 return UINTTOFP_I32_F32;
465 else if (RetVT == MVT::f64)
466 return UINTTOFP_I32_F64;
467 else if (RetVT == MVT::f80)
468 return UINTTOFP_I32_F80;
469 else if (RetVT == MVT::ppcf128)
470 return UINTTOFP_I32_PPCF128;
471 } else if (OpVT == MVT::i64) {
472 if (RetVT == MVT::f32)
473 return UINTTOFP_I64_F32;
474 else if (RetVT == MVT::f64)
475 return UINTTOFP_I64_F64;
476 else if (RetVT == MVT::f80)
477 return UINTTOFP_I64_F80;
478 else if (RetVT == MVT::ppcf128)
479 return UINTTOFP_I64_PPCF128;
480 } else if (OpVT == MVT::i128) {
481 if (RetVT == MVT::f32)
482 return UINTTOFP_I128_F32;
483 else if (RetVT == MVT::f64)
484 return UINTTOFP_I128_F64;
485 else if (RetVT == MVT::f80)
486 return UINTTOFP_I128_F80;
487 else if (RetVT == MVT::ppcf128)
488 return UINTTOFP_I128_PPCF128;
490 return UNKNOWN_LIBCALL;
493 /// InitCmpLibcallCCs - Set default comparison libcall CC.
495 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
496 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
497 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
498 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
499 CCs[RTLIB::UNE_F32] = ISD::SETNE;
500 CCs[RTLIB::UNE_F64] = ISD::SETNE;
501 CCs[RTLIB::OGE_F32] = ISD::SETGE;
502 CCs[RTLIB::OGE_F64] = ISD::SETGE;
503 CCs[RTLIB::OLT_F32] = ISD::SETLT;
504 CCs[RTLIB::OLT_F64] = ISD::SETLT;
505 CCs[RTLIB::OLE_F32] = ISD::SETLE;
506 CCs[RTLIB::OLE_F64] = ISD::SETLE;
507 CCs[RTLIB::OGT_F32] = ISD::SETGT;
508 CCs[RTLIB::OGT_F64] = ISD::SETGT;
509 CCs[RTLIB::UO_F32] = ISD::SETNE;
510 CCs[RTLIB::UO_F64] = ISD::SETNE;
511 CCs[RTLIB::O_F32] = ISD::SETEQ;
512 CCs[RTLIB::O_F64] = ISD::SETEQ;
515 /// NOTE: The constructor takes ownership of TLOF.
516 TargetLowering::TargetLowering(const TargetMachine &tm,
517 const TargetLoweringObjectFile *tlof)
518 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) {
519 // All operations default to being supported.
520 memset(OpActions, 0, sizeof(OpActions));
521 memset(LoadExtActions, 0, sizeof(LoadExtActions));
522 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
523 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
524 memset(CondCodeActions, 0, sizeof(CondCodeActions));
526 // Set default actions for various operations.
527 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
528 // Default all indexed load / store to expand.
529 for (unsigned IM = (unsigned)ISD::PRE_INC;
530 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
531 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
532 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
535 // These operations default to expand.
536 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
540 // Most targets ignore the @llvm.prefetch intrinsic.
541 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
543 // ConstantFP nodes default to expand. Targets can either change this to
544 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
545 // to optimize expansions for certain constants.
546 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
547 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
548 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
549 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
551 // These library functions default to expand.
552 setOperationAction(ISD::FLOG , MVT::f16, Expand);
553 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
554 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
555 setOperationAction(ISD::FEXP , MVT::f16, Expand);
556 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
557 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
558 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
559 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
560 setOperationAction(ISD::FRINT, MVT::f16, Expand);
561 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
562 setOperationAction(ISD::FLOG , MVT::f32, Expand);
563 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
564 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
565 setOperationAction(ISD::FEXP , MVT::f32, Expand);
566 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
567 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
568 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
569 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
570 setOperationAction(ISD::FRINT, MVT::f32, Expand);
571 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
572 setOperationAction(ISD::FLOG , MVT::f64, Expand);
573 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
574 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
575 setOperationAction(ISD::FEXP , MVT::f64, Expand);
576 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
577 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
578 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
579 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
580 setOperationAction(ISD::FRINT, MVT::f64, Expand);
581 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
583 // Default ISD::TRAP to expand (which turns it into abort).
584 setOperationAction(ISD::TRAP, MVT::Other, Expand);
586 IsLittleEndian = TD->isLittleEndian();
587 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
588 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
589 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
590 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
591 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
592 = maxStoresPerMemmoveOptSize = 4;
593 benefitFromCodePlacementOpt = false;
594 UseUnderscoreSetJmp = false;
595 UseUnderscoreLongJmp = false;
596 SelectIsExpensive = false;
597 IntDivIsCheap = false;
598 Pow2DivIsCheap = false;
599 JumpIsExpensive = false;
600 predictableSelectIsExpensive = false;
601 StackPointerRegisterToSaveRestore = 0;
602 ExceptionPointerRegister = 0;
603 ExceptionSelectorRegister = 0;
604 BooleanContents = UndefinedBooleanContent;
605 BooleanVectorContents = UndefinedBooleanContent;
606 SchedPreferenceInfo = Sched::ILP;
608 JumpBufAlignment = 0;
609 MinFunctionAlignment = 0;
610 PrefFunctionAlignment = 0;
611 PrefLoopAlignment = 0;
612 MinStackArgumentAlignment = 1;
613 ShouldFoldAtomicFences = false;
614 InsertFencesForAtomic = false;
616 InitLibcallNames(LibcallRoutineNames);
617 InitCmpLibcallCCs(CmpLibcallCCs);
618 InitLibcallCallingConvs(LibcallCallingConvs);
621 TargetLowering::~TargetLowering() {
625 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
626 return MVT::getIntegerVT(8*TD->getPointerSize());
629 /// canOpTrap - Returns true if the operation can trap for the value type.
630 /// VT must be a legal type.
631 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
632 assert(isTypeLegal(VT));
647 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
648 unsigned &NumIntermediates,
650 TargetLowering *TLI) {
651 // Figure out the right, legal destination reg to copy into.
652 unsigned NumElts = VT.getVectorNumElements();
653 MVT EltTy = VT.getVectorElementType();
655 unsigned NumVectorRegs = 1;
657 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
658 // could break down into LHS/RHS like LegalizeDAG does.
659 if (!isPowerOf2_32(NumElts)) {
660 NumVectorRegs = NumElts;
664 // Divide the input until we get to a supported size. This will always
665 // end with a scalar if the target doesn't support vectors.
666 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
671 NumIntermediates = NumVectorRegs;
673 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
674 if (!TLI->isTypeLegal(NewVT))
676 IntermediateVT = NewVT;
678 unsigned NewVTSize = NewVT.getSizeInBits();
680 // Convert sizes such as i33 to i64.
681 if (!isPowerOf2_32(NewVTSize))
682 NewVTSize = NextPowerOf2(NewVTSize);
684 EVT DestVT = TLI->getRegisterType(NewVT);
686 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
687 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
689 // Otherwise, promotion or legal types use the same number of registers as
690 // the vector decimated to the appropriate level.
691 return NumVectorRegs;
694 /// isLegalRC - Return true if the value types that can be represented by the
695 /// specified register class are all legal.
696 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
697 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
705 /// findRepresentativeClass - Return the largest legal super-reg register class
706 /// of the register class for the specified type and its associated "cost".
707 std::pair<const TargetRegisterClass*, uint8_t>
708 TargetLowering::findRepresentativeClass(EVT VT) const {
709 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
710 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
712 return std::make_pair(RC, 0);
714 // Compute the set of all super-register classes.
715 BitVector SuperRegRC(TRI->getNumRegClasses());
716 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
717 SuperRegRC.setBitsInMask(RCI.getMask());
719 // Find the first legal register class with the largest spill size.
720 const TargetRegisterClass *BestRC = RC;
721 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
722 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
723 // We want the largest possible spill size.
724 if (SuperRC->getSize() <= BestRC->getSize())
726 if (!isLegalRC(SuperRC))
730 return std::make_pair(BestRC, 1);
733 /// computeRegisterProperties - Once all of the register classes are added,
734 /// this allows us to compute derived properties we expose.
735 void TargetLowering::computeRegisterProperties() {
736 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
737 "Too many value types for ValueTypeActions to hold!");
739 // Everything defaults to needing one register.
740 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
741 NumRegistersForVT[i] = 1;
742 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
744 // ...except isVoid, which doesn't need any registers.
745 NumRegistersForVT[MVT::isVoid] = 0;
747 // Find the largest integer register class.
748 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
749 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
750 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
752 // Every integer value type larger than this largest register takes twice as
753 // many registers to represent as the previous ValueType.
754 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
755 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
756 if (!ExpandedVT.isInteger())
758 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
759 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
760 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
761 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
764 // Inspect all of the ValueType's smaller than the largest integer
765 // register to see which ones need promotion.
766 unsigned LegalIntReg = LargestIntReg;
767 for (unsigned IntReg = LargestIntReg - 1;
768 IntReg >= (unsigned)MVT::i1; --IntReg) {
769 EVT IVT = (MVT::SimpleValueType)IntReg;
770 if (isTypeLegal(IVT)) {
771 LegalIntReg = IntReg;
773 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
774 (MVT::SimpleValueType)LegalIntReg;
775 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
779 // ppcf128 type is really two f64's.
780 if (!isTypeLegal(MVT::ppcf128)) {
781 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
782 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
783 TransformToType[MVT::ppcf128] = MVT::f64;
784 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
787 // Decide how to handle f64. If the target does not have native f64 support,
788 // expand it to i64 and we will be generating soft float library calls.
789 if (!isTypeLegal(MVT::f64)) {
790 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
791 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
792 TransformToType[MVT::f64] = MVT::i64;
793 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
796 // Decide how to handle f32. If the target does not have native support for
797 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
798 if (!isTypeLegal(MVT::f32)) {
799 if (isTypeLegal(MVT::f64)) {
800 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
801 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
802 TransformToType[MVT::f32] = MVT::f64;
803 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
805 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
806 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
807 TransformToType[MVT::f32] = MVT::i32;
808 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
812 // Loop over all of the vector value types to see which need transformations.
813 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
814 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
815 MVT VT = (MVT::SimpleValueType)i;
816 if (isTypeLegal(VT)) continue;
818 // Determine if there is a legal wider type. If so, we should promote to
819 // that wider vector type.
820 EVT EltVT = VT.getVectorElementType();
821 unsigned NElts = VT.getVectorNumElements();
823 bool IsLegalWiderType = false;
824 // First try to promote the elements of integer vectors. If no legal
825 // promotion was found, fallback to the widen-vector method.
826 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
827 EVT SVT = (MVT::SimpleValueType)nVT;
828 // Promote vectors of integers to vectors with the same number
829 // of elements, with a wider element type.
830 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
831 && SVT.getVectorNumElements() == NElts &&
832 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
833 TransformToType[i] = SVT;
834 RegisterTypeForVT[i] = SVT;
835 NumRegistersForVT[i] = 1;
836 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
837 IsLegalWiderType = true;
842 if (IsLegalWiderType) continue;
844 // Try to widen the vector.
845 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
846 EVT SVT = (MVT::SimpleValueType)nVT;
847 if (SVT.getVectorElementType() == EltVT &&
848 SVT.getVectorNumElements() > NElts &&
850 TransformToType[i] = SVT;
851 RegisterTypeForVT[i] = SVT;
852 NumRegistersForVT[i] = 1;
853 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
854 IsLegalWiderType = true;
858 if (IsLegalWiderType) continue;
863 unsigned NumIntermediates;
864 NumRegistersForVT[i] =
865 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
867 RegisterTypeForVT[i] = RegisterVT;
869 EVT NVT = VT.getPow2VectorType();
871 // Type is already a power of 2. The default action is to split.
872 TransformToType[i] = MVT::Other;
873 unsigned NumElts = VT.getVectorNumElements();
874 ValueTypeActions.setTypeAction(VT,
875 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
877 TransformToType[i] = NVT;
878 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
882 // Determine the 'representative' register class for each value type.
883 // An representative register class is the largest (meaning one which is
884 // not a sub-register class / subreg register class) legal register class for
885 // a group of value types. For example, on i386, i8, i16, and i32
886 // representative would be GR32; while on x86_64 it's GR64.
887 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
888 const TargetRegisterClass* RRC;
890 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
891 RepRegClassForVT[i] = RRC;
892 RepRegClassCostForVT[i] = Cost;
896 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
901 EVT TargetLowering::getSetCCResultType(EVT VT) const {
902 assert(!VT.isVector() && "No default SetCC type for vectors!");
903 return PointerTy.SimpleTy;
906 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
907 return MVT::i32; // return the default value
910 /// getVectorTypeBreakdown - Vector types are broken down into some number of
911 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
912 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
913 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
915 /// This method returns the number of registers needed, and the VT for each
916 /// register. It also returns the VT and quantity of the intermediate values
917 /// before they are promoted/expanded.
919 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
921 unsigned &NumIntermediates,
922 EVT &RegisterVT) const {
923 unsigned NumElts = VT.getVectorNumElements();
925 // If there is a wider vector type with the same element type as this one,
926 // or a promoted vector type that has the same number of elements which
927 // are wider, then we should convert to that legal vector type.
928 // This handles things like <2 x float> -> <4 x float> and
929 // <4 x i1> -> <4 x i32>.
930 LegalizeTypeAction TA = getTypeAction(Context, VT);
931 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
932 RegisterVT = getTypeToTransformTo(Context, VT);
933 if (isTypeLegal(RegisterVT)) {
934 IntermediateVT = RegisterVT;
935 NumIntermediates = 1;
940 // Figure out the right, legal destination reg to copy into.
941 EVT EltTy = VT.getVectorElementType();
943 unsigned NumVectorRegs = 1;
945 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
946 // could break down into LHS/RHS like LegalizeDAG does.
947 if (!isPowerOf2_32(NumElts)) {
948 NumVectorRegs = NumElts;
952 // Divide the input until we get to a supported size. This will always
953 // end with a scalar if the target doesn't support vectors.
954 while (NumElts > 1 && !isTypeLegal(
955 EVT::getVectorVT(Context, EltTy, NumElts))) {
960 NumIntermediates = NumVectorRegs;
962 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
963 if (!isTypeLegal(NewVT))
965 IntermediateVT = NewVT;
967 EVT DestVT = getRegisterType(Context, NewVT);
969 unsigned NewVTSize = NewVT.getSizeInBits();
971 // Convert sizes such as i33 to i64.
972 if (!isPowerOf2_32(NewVTSize))
973 NewVTSize = NextPowerOf2(NewVTSize);
975 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
976 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
978 // Otherwise, promotion or legal types use the same number of registers as
979 // the vector decimated to the appropriate level.
980 return NumVectorRegs;
983 /// Get the EVTs and ArgFlags collections that represent the legalized return
984 /// type of the given function. This does not require a DAG or a return value,
985 /// and is suitable for use before any DAGs for the function are constructed.
986 /// TODO: Move this out of TargetLowering.cpp.
987 void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
988 SmallVectorImpl<ISD::OutputArg> &Outs,
989 const TargetLowering &TLI) {
990 SmallVector<EVT, 4> ValueVTs;
991 ComputeValueVTs(TLI, ReturnType, ValueVTs);
992 unsigned NumValues = ValueVTs.size();
993 if (NumValues == 0) return;
995 for (unsigned j = 0, f = NumValues; j != f; ++j) {
996 EVT VT = ValueVTs[j];
997 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
999 if (attr & Attribute::SExt)
1000 ExtendKind = ISD::SIGN_EXTEND;
1001 else if (attr & Attribute::ZExt)
1002 ExtendKind = ISD::ZERO_EXTEND;
1004 // FIXME: C calling convention requires the return type to be promoted to
1005 // at least 32-bit. But this is not necessary for non-C calling
1006 // conventions. The frontend should mark functions whose return values
1007 // require promoting with signext or zeroext attributes.
1008 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1009 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1010 if (VT.bitsLT(MinVT))
1014 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1015 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1017 // 'inreg' on function refers to return value
1018 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1019 if (attr & Attribute::InReg)
1022 // Propagate extension type if any
1023 if (attr & Attribute::SExt)
1025 else if (attr & Attribute::ZExt)
1028 for (unsigned i = 0; i < NumParts; ++i) {
1029 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1034 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1035 /// function arguments in the caller parameter area. This is the actual
1036 /// alignment, not its logarithm.
1037 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1038 return TD->getCallFrameTypeAlignment(Ty);
1041 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1042 /// current function. The returned value is a member of the
1043 /// MachineJumpTableInfo::JTEntryKind enum.
1044 unsigned TargetLowering::getJumpTableEncoding() const {
1045 // In non-pic modes, just use the address of a block.
1046 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1047 return MachineJumpTableInfo::EK_BlockAddress;
1049 // In PIC mode, if the target supports a GPRel32 directive, use it.
1050 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1051 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1053 // Otherwise, use a label difference.
1054 return MachineJumpTableInfo::EK_LabelDifference32;
1057 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1058 SelectionDAG &DAG) const {
1059 // If our PIC model is GP relative, use the global offset table as the base.
1060 unsigned JTEncoding = getJumpTableEncoding();
1062 if ((JTEncoding == MachineJumpTableInfo::EK_GPRel64BlockAddress) ||
1063 (JTEncoding == MachineJumpTableInfo::EK_GPRel32BlockAddress))
1064 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1069 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1070 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1073 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1074 unsigned JTI,MCContext &Ctx) const{
1075 // The normal PIC reloc base is the label at the start of the jump table.
1076 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1080 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1081 // Assume that everything is safe in static mode.
1082 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1085 // In dynamic-no-pic mode, assume that known defined values are safe.
1086 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1088 !GA->getGlobal()->isDeclaration() &&
1089 !GA->getGlobal()->isWeakForLinker())
1092 // Otherwise assume nothing is safe.
1096 //===----------------------------------------------------------------------===//
1097 // Optimization Methods
1098 //===----------------------------------------------------------------------===//
1100 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1101 /// specified instruction is a constant integer. If so, check to see if there
1102 /// are any bits set in the constant that are not demanded. If so, shrink the
1103 /// constant and return true.
1104 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1105 const APInt &Demanded) {
1106 DebugLoc dl = Op.getDebugLoc();
1108 // FIXME: ISD::SELECT, ISD::SELECT_CC
1109 switch (Op.getOpcode()) {
1114 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1115 if (!C) return false;
1117 if (Op.getOpcode() == ISD::XOR &&
1118 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1121 // if we can expand it to have all bits set, do it
1122 if (C->getAPIntValue().intersects(~Demanded)) {
1123 EVT VT = Op.getValueType();
1124 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1125 DAG.getConstant(Demanded &
1128 return CombineTo(Op, New);
1138 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1139 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1140 /// cast, but it could be generalized for targets with other types of
1141 /// implicit widening casts.
1143 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1145 const APInt &Demanded,
1147 assert(Op.getNumOperands() == 2 &&
1148 "ShrinkDemandedOp only supports binary operators!");
1149 assert(Op.getNode()->getNumValues() == 1 &&
1150 "ShrinkDemandedOp only supports nodes with one result!");
1152 // Don't do this if the node has another user, which may require the
1154 if (!Op.getNode()->hasOneUse())
1157 // Search for the smallest integer type with free casts to and from
1158 // Op's type. For expedience, just check power-of-2 integer types.
1159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1160 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1161 if (!isPowerOf2_32(SmallVTBits))
1162 SmallVTBits = NextPowerOf2(SmallVTBits);
1163 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1164 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1165 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1166 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1167 // We found a type with free casts.
1168 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1169 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1170 Op.getNode()->getOperand(0)),
1171 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1172 Op.getNode()->getOperand(1)));
1173 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1174 return CombineTo(Op, Z);
1180 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1181 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1182 /// use this information to simplify Op, create a new simplified DAG node and
1183 /// return true, returning the original and new nodes in Old and New. Otherwise,
1184 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
1185 /// the expression (used to simplify the caller). The KnownZero/One bits may
1186 /// only be accurate for those bits in the DemandedMask.
1187 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1188 const APInt &DemandedMask,
1191 TargetLoweringOpt &TLO,
1192 unsigned Depth) const {
1193 unsigned BitWidth = DemandedMask.getBitWidth();
1194 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1195 "Mask size mismatches value type size!");
1196 APInt NewMask = DemandedMask;
1197 DebugLoc dl = Op.getDebugLoc();
1199 // Don't know anything.
1200 KnownZero = KnownOne = APInt(BitWidth, 0);
1202 // Other users may use these bits.
1203 if (!Op.getNode()->hasOneUse()) {
1205 // If not at the root, Just compute the KnownZero/KnownOne bits to
1206 // simplify things downstream.
1207 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1210 // If this is the root being simplified, allow it to have multiple uses,
1211 // just set the NewMask to all bits.
1212 NewMask = APInt::getAllOnesValue(BitWidth);
1213 } else if (DemandedMask == 0) {
1214 // Not demanding any bits from Op.
1215 if (Op.getOpcode() != ISD::UNDEF)
1216 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1218 } else if (Depth == 6) { // Limit search depth.
1222 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1223 switch (Op.getOpcode()) {
1225 // We know all of the bits for a constant!
1226 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1227 KnownZero = ~KnownOne;
1228 return false; // Don't fall through, will infinitely loop.
1230 // If the RHS is a constant, check to see if the LHS would be zero without
1231 // using the bits from the RHS. Below, we use knowledge about the RHS to
1232 // simplify the LHS, here we're using information from the LHS to simplify
1234 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1235 APInt LHSZero, LHSOne;
1236 // Do not increment Depth here; that can cause an infinite loop.
1237 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1238 // If the LHS already has zeros where RHSC does, this and is dead.
1239 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1240 return TLO.CombineTo(Op, Op.getOperand(0));
1241 // If any of the set bits in the RHS are known zero on the LHS, shrink
1243 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1247 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1248 KnownOne, TLO, Depth+1))
1250 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1251 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1252 KnownZero2, KnownOne2, TLO, Depth+1))
1254 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1256 // If all of the demanded bits are known one on one side, return the other.
1257 // These bits cannot contribute to the result of the 'and'.
1258 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1259 return TLO.CombineTo(Op, Op.getOperand(0));
1260 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1261 return TLO.CombineTo(Op, Op.getOperand(1));
1262 // If all of the demanded bits in the inputs are known zeros, return zero.
1263 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1264 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1265 // If the RHS is a constant, see if we can simplify it.
1266 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1268 // If the operation can be done in a smaller type, do so.
1269 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1272 // Output known-1 bits are only known if set in both the LHS & RHS.
1273 KnownOne &= KnownOne2;
1274 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1275 KnownZero |= KnownZero2;
1278 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1279 KnownOne, TLO, Depth+1))
1281 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1282 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1283 KnownZero2, KnownOne2, TLO, Depth+1))
1285 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1287 // If all of the demanded bits are known zero on one side, return the other.
1288 // These bits cannot contribute to the result of the 'or'.
1289 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1290 return TLO.CombineTo(Op, Op.getOperand(0));
1291 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1292 return TLO.CombineTo(Op, Op.getOperand(1));
1293 // If all of the potentially set bits on one side are known to be set on
1294 // the other side, just use the 'other' side.
1295 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1296 return TLO.CombineTo(Op, Op.getOperand(0));
1297 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1298 return TLO.CombineTo(Op, Op.getOperand(1));
1299 // If the RHS is a constant, see if we can simplify it.
1300 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1302 // If the operation can be done in a smaller type, do so.
1303 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1306 // Output known-0 bits are only known if clear in both the LHS & RHS.
1307 KnownZero &= KnownZero2;
1308 // Output known-1 are known to be set if set in either the LHS | RHS.
1309 KnownOne |= KnownOne2;
1312 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1313 KnownOne, TLO, Depth+1))
1315 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1316 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1317 KnownOne2, TLO, Depth+1))
1319 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1321 // If all of the demanded bits are known zero on one side, return the other.
1322 // These bits cannot contribute to the result of the 'xor'.
1323 if ((KnownZero & NewMask) == NewMask)
1324 return TLO.CombineTo(Op, Op.getOperand(0));
1325 if ((KnownZero2 & NewMask) == NewMask)
1326 return TLO.CombineTo(Op, Op.getOperand(1));
1327 // If the operation can be done in a smaller type, do so.
1328 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1331 // If all of the unknown bits are known to be zero on one side or the other
1332 // (but not both) turn this into an *inclusive* or.
1333 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1334 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1335 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1339 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1340 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1341 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1342 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1344 // If all of the demanded bits on one side are known, and all of the set
1345 // bits on that side are also known to be set on the other side, turn this
1346 // into an AND, as we know the bits will be cleared.
1347 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1348 // NB: it is okay if more bits are known than are requested
1349 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side
1350 if (KnownOne == KnownOne2) { // set bits are the same on both sides
1351 EVT VT = Op.getValueType();
1352 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1353 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1354 Op.getOperand(0), ANDC));
1358 // If the RHS is a constant, see if we can simplify it.
1359 // for XOR, we prefer to force bits to 1 if they will make a -1.
1360 // if we can't force bits, try to shrink constant
1361 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1362 APInt Expanded = C->getAPIntValue() | (~NewMask);
1363 // if we can expand it to have all bits set, do it
1364 if (Expanded.isAllOnesValue()) {
1365 if (Expanded != C->getAPIntValue()) {
1366 EVT VT = Op.getValueType();
1367 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1368 TLO.DAG.getConstant(Expanded, VT));
1369 return TLO.CombineTo(Op, New);
1371 // if it already has all the bits set, nothing to change
1372 // but don't shrink either!
1373 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1378 KnownZero = KnownZeroOut;
1379 KnownOne = KnownOneOut;
1382 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1383 KnownOne, TLO, Depth+1))
1385 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1386 KnownOne2, TLO, Depth+1))
1388 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1389 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1391 // If the operands are constants, see if we can simplify them.
1392 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1395 // Only known if known in both the LHS and RHS.
1396 KnownOne &= KnownOne2;
1397 KnownZero &= KnownZero2;
1399 case ISD::SELECT_CC:
1400 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1401 KnownOne, TLO, Depth+1))
1403 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1404 KnownOne2, TLO, Depth+1))
1406 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1407 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1409 // If the operands are constants, see if we can simplify them.
1410 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1413 // Only known if known in both the LHS and RHS.
1414 KnownOne &= KnownOne2;
1415 KnownZero &= KnownZero2;
1418 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1419 unsigned ShAmt = SA->getZExtValue();
1420 SDValue InOp = Op.getOperand(0);
1422 // If the shift count is an invalid immediate, don't do anything.
1423 if (ShAmt >= BitWidth)
1426 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1427 // single shift. We can do this if the bottom bits (which are shifted
1428 // out) are never demanded.
1429 if (InOp.getOpcode() == ISD::SRL &&
1430 isa<ConstantSDNode>(InOp.getOperand(1))) {
1431 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1432 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1433 unsigned Opc = ISD::SHL;
1434 int Diff = ShAmt-C1;
1441 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1442 EVT VT = Op.getValueType();
1443 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1444 InOp.getOperand(0), NewSA));
1448 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1449 KnownZero, KnownOne, TLO, Depth+1))
1452 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1453 // are not demanded. This will likely allow the anyext to be folded away.
1454 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1455 SDValue InnerOp = InOp.getNode()->getOperand(0);
1456 EVT InnerVT = InnerOp.getValueType();
1457 unsigned InnerBits = InnerVT.getSizeInBits();
1458 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1459 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1460 EVT ShTy = getShiftAmountTy(InnerVT);
1461 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1464 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1465 TLO.DAG.getConstant(ShAmt, ShTy));
1468 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1473 KnownZero <<= SA->getZExtValue();
1474 KnownOne <<= SA->getZExtValue();
1475 // low bits known zero.
1476 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1480 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1481 EVT VT = Op.getValueType();
1482 unsigned ShAmt = SA->getZExtValue();
1483 unsigned VTSize = VT.getSizeInBits();
1484 SDValue InOp = Op.getOperand(0);
1486 // If the shift count is an invalid immediate, don't do anything.
1487 if (ShAmt >= BitWidth)
1490 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1491 // single shift. We can do this if the top bits (which are shifted out)
1492 // are never demanded.
1493 if (InOp.getOpcode() == ISD::SHL &&
1494 isa<ConstantSDNode>(InOp.getOperand(1))) {
1495 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1496 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1497 unsigned Opc = ISD::SRL;
1498 int Diff = ShAmt-C1;
1505 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1506 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1507 InOp.getOperand(0), NewSA));
1511 // Compute the new bits that are at the top now.
1512 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1513 KnownZero, KnownOne, TLO, Depth+1))
1515 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1516 KnownZero = KnownZero.lshr(ShAmt);
1517 KnownOne = KnownOne.lshr(ShAmt);
1519 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1520 KnownZero |= HighBits; // High bits known zero.
1524 // If this is an arithmetic shift right and only the low-bit is set, we can
1525 // always convert this into a logical shr, even if the shift amount is
1526 // variable. The low bit of the shift cannot be an input sign bit unless
1527 // the shift amount is >= the size of the datatype, which is undefined.
1529 return TLO.CombineTo(Op,
1530 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1531 Op.getOperand(0), Op.getOperand(1)));
1533 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1534 EVT VT = Op.getValueType();
1535 unsigned ShAmt = SA->getZExtValue();
1537 // If the shift count is an invalid immediate, don't do anything.
1538 if (ShAmt >= BitWidth)
1541 APInt InDemandedMask = (NewMask << ShAmt);
1543 // If any of the demanded bits are produced by the sign extension, we also
1544 // demand the input sign bit.
1545 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1546 if (HighBits.intersects(NewMask))
1547 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1549 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1550 KnownZero, KnownOne, TLO, Depth+1))
1552 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1553 KnownZero = KnownZero.lshr(ShAmt);
1554 KnownOne = KnownOne.lshr(ShAmt);
1556 // Handle the sign bit, adjusted to where it is now in the mask.
1557 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1559 // If the input sign bit is known to be zero, or if none of the top bits
1560 // are demanded, turn this into an unsigned shift right.
1561 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1562 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1565 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1566 KnownOne |= HighBits;
1570 case ISD::SIGN_EXTEND_INREG: {
1571 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1573 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1574 // If we only care about the highest bit, don't bother shifting right.
1575 if (MsbMask == DemandedMask) {
1576 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1577 SDValue InOp = Op.getOperand(0);
1579 // Compute the correct shift amount type, which must be getShiftAmountTy
1580 // for scalar types after legalization.
1581 EVT ShiftAmtTy = Op.getValueType();
1582 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1583 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1585 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1586 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1587 Op.getValueType(), InOp, ShiftAmt));
1590 // Sign extension. Compute the demanded bits in the result that are not
1591 // present in the input.
1593 APInt::getHighBitsSet(BitWidth,
1594 BitWidth - ExVT.getScalarType().getSizeInBits());
1596 // If none of the extended bits are demanded, eliminate the sextinreg.
1597 if ((NewBits & NewMask) == 0)
1598 return TLO.CombineTo(Op, Op.getOperand(0));
1601 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1602 APInt InputDemandedBits =
1603 APInt::getLowBitsSet(BitWidth,
1604 ExVT.getScalarType().getSizeInBits()) &
1607 // Since the sign extended bits are demanded, we know that the sign
1609 InputDemandedBits |= InSignBit;
1611 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1612 KnownZero, KnownOne, TLO, Depth+1))
1614 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1616 // If the sign bit of the input is known set or clear, then we know the
1617 // top bits of the result.
1619 // If the input sign bit is known zero, convert this into a zero extension.
1620 if (KnownZero.intersects(InSignBit))
1621 return TLO.CombineTo(Op,
1622 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1624 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1625 KnownOne |= NewBits;
1626 KnownZero &= ~NewBits;
1627 } else { // Input sign bit unknown
1628 KnownZero &= ~NewBits;
1629 KnownOne &= ~NewBits;
1633 case ISD::ZERO_EXTEND: {
1634 unsigned OperandBitWidth =
1635 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1636 APInt InMask = NewMask.trunc(OperandBitWidth);
1638 // If none of the top bits are demanded, convert this into an any_extend.
1640 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1641 if (!NewBits.intersects(NewMask))
1642 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1646 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1647 KnownZero, KnownOne, TLO, Depth+1))
1649 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1650 KnownZero = KnownZero.zext(BitWidth);
1651 KnownOne = KnownOne.zext(BitWidth);
1652 KnownZero |= NewBits;
1655 case ISD::SIGN_EXTEND: {
1656 EVT InVT = Op.getOperand(0).getValueType();
1657 unsigned InBits = InVT.getScalarType().getSizeInBits();
1658 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1659 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1660 APInt NewBits = ~InMask & NewMask;
1662 // If none of the top bits are demanded, convert this into an any_extend.
1664 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1668 // Since some of the sign extended bits are demanded, we know that the sign
1670 APInt InDemandedBits = InMask & NewMask;
1671 InDemandedBits |= InSignBit;
1672 InDemandedBits = InDemandedBits.trunc(InBits);
1674 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1675 KnownOne, TLO, Depth+1))
1677 KnownZero = KnownZero.zext(BitWidth);
1678 KnownOne = KnownOne.zext(BitWidth);
1680 // If the sign bit is known zero, convert this to a zero extend.
1681 if (KnownZero.intersects(InSignBit))
1682 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1686 // If the sign bit is known one, the top bits match.
1687 if (KnownOne.intersects(InSignBit)) {
1688 KnownOne |= NewBits;
1689 assert((KnownZero & NewBits) == 0);
1690 } else { // Otherwise, top bits aren't known.
1691 assert((KnownOne & NewBits) == 0);
1692 assert((KnownZero & NewBits) == 0);
1696 case ISD::ANY_EXTEND: {
1697 unsigned OperandBitWidth =
1698 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1699 APInt InMask = NewMask.trunc(OperandBitWidth);
1700 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1701 KnownZero, KnownOne, TLO, Depth+1))
1703 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1704 KnownZero = KnownZero.zext(BitWidth);
1705 KnownOne = KnownOne.zext(BitWidth);
1708 case ISD::TRUNCATE: {
1709 // Simplify the input, using demanded bit information, and compute the known
1710 // zero/one bits live out.
1711 unsigned OperandBitWidth =
1712 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1713 APInt TruncMask = NewMask.zext(OperandBitWidth);
1714 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1715 KnownZero, KnownOne, TLO, Depth+1))
1717 KnownZero = KnownZero.trunc(BitWidth);
1718 KnownOne = KnownOne.trunc(BitWidth);
1720 // If the input is only used by this truncate, see if we can shrink it based
1721 // on the known demanded bits.
1722 if (Op.getOperand(0).getNode()->hasOneUse()) {
1723 SDValue In = Op.getOperand(0);
1724 switch (In.getOpcode()) {
1727 // Shrink SRL by a constant if none of the high bits shifted in are
1729 if (TLO.LegalTypes() &&
1730 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1731 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1734 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1737 SDValue Shift = In.getOperand(1);
1738 if (TLO.LegalTypes()) {
1739 uint64_t ShVal = ShAmt->getZExtValue();
1741 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1744 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1745 OperandBitWidth - BitWidth);
1746 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1748 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1749 // None of the shifted in bits are needed. Add a truncate of the
1750 // shift input, then shift it.
1751 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1754 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1763 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1766 case ISD::AssertZext: {
1767 // AssertZext demands all of the high bits, plus any of the low bits
1768 // demanded by its users.
1769 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1770 APInt InMask = APInt::getLowBitsSet(BitWidth,
1771 VT.getSizeInBits());
1772 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1773 KnownZero, KnownOne, TLO, Depth+1))
1775 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1777 KnownZero |= ~InMask & NewMask;
1781 // If this is an FP->Int bitcast and if the sign bit is the only
1782 // thing demanded, turn this into a FGETSIGN.
1783 if (!TLO.LegalOperations() &&
1784 !Op.getValueType().isVector() &&
1785 !Op.getOperand(0).getValueType().isVector() &&
1786 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1787 Op.getOperand(0).getValueType().isFloatingPoint()) {
1788 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1789 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1790 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1791 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1792 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1793 // place. We expect the SHL to be eliminated by other optimizations.
1794 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1795 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1796 if (!OpVTLegal && OpVTSizeInBits > 32)
1797 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1798 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1799 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1800 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1809 // Add, Sub, and Mul don't demand any bits in positions beyond that
1810 // of the highest bit demanded of them.
1811 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1812 BitWidth - NewMask.countLeadingZeros());
1813 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1814 KnownOne2, TLO, Depth+1))
1816 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1817 KnownOne2, TLO, Depth+1))
1819 // See if the operation should be performed at a smaller bit width.
1820 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1825 // Just use ComputeMaskedBits to compute output bits.
1826 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1830 // If we know the value of all of the demanded bits, return this as a
1832 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1833 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1838 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1839 /// in Mask are known to be either zero or one and return them in the
1840 /// KnownZero/KnownOne bitsets.
1841 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1844 const SelectionDAG &DAG,
1845 unsigned Depth) const {
1846 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1847 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1848 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1849 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1850 "Should use MaskedValueIsZero if you don't know whether Op"
1851 " is a target node!");
1852 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1855 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1856 /// targets that want to expose additional information about sign bits to the
1858 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1859 unsigned Depth) const {
1860 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1861 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1862 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1863 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1864 "Should use ComputeNumSignBits if you don't know whether Op"
1865 " is a target node!");
1869 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1870 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1871 /// determine which bit is set.
1873 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1874 // A left-shift of a constant one will have exactly one bit set, because
1875 // shifting the bit off the end is undefined.
1876 if (Val.getOpcode() == ISD::SHL)
1877 if (ConstantSDNode *C =
1878 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1879 if (C->getAPIntValue() == 1)
1882 // Similarly, a right-shift of a constant sign-bit will have exactly
1884 if (Val.getOpcode() == ISD::SRL)
1885 if (ConstantSDNode *C =
1886 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1887 if (C->getAPIntValue().isSignBit())
1890 // More could be done here, though the above checks are enough
1891 // to handle some common cases.
1893 // Fall back to ComputeMaskedBits to catch other known cases.
1894 EVT OpVT = Val.getValueType();
1895 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1896 APInt KnownZero, KnownOne;
1897 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1898 return (KnownZero.countPopulation() == BitWidth - 1) &&
1899 (KnownOne.countPopulation() == 1);
1902 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1903 /// and cc. If it is unable to simplify it, return a null SDValue.
1905 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1906 ISD::CondCode Cond, bool foldBooleans,
1907 DAGCombinerInfo &DCI, DebugLoc dl) const {
1908 SelectionDAG &DAG = DCI.DAG;
1910 // These setcc operations always fold.
1914 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1916 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1919 // Ensure that the constant occurs on the RHS, and fold constant
1921 if (isa<ConstantSDNode>(N0.getNode()))
1922 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1924 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1925 const APInt &C1 = N1C->getAPIntValue();
1927 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1928 // equality comparison, then we're just comparing whether X itself is
1930 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1931 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1932 N0.getOperand(1).getOpcode() == ISD::Constant) {
1934 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1935 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1936 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1937 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1938 // (srl (ctlz x), 5) == 0 -> X != 0
1939 // (srl (ctlz x), 5) != 1 -> X != 0
1942 // (srl (ctlz x), 5) != 0 -> X == 0
1943 // (srl (ctlz x), 5) == 1 -> X == 0
1946 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1947 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1953 // Look through truncs that don't change the value of a ctpop.
1954 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1955 CTPOP = N0.getOperand(0);
1957 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1958 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1959 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1960 EVT CTVT = CTPOP.getValueType();
1961 SDValue CTOp = CTPOP.getOperand(0);
1963 // (ctpop x) u< 2 -> (x & x-1) == 0
1964 // (ctpop x) u> 1 -> (x & x-1) != 0
1965 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1966 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1967 DAG.getConstant(1, CTVT));
1968 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1969 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1970 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1973 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1976 // (zext x) == C --> x == (trunc C)
1977 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1978 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1979 unsigned MinBits = N0.getValueSizeInBits();
1981 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
1983 MinBits = N0->getOperand(0).getValueSizeInBits();
1984 PreZExt = N0->getOperand(0);
1985 } else if (N0->getOpcode() == ISD::AND) {
1986 // DAGCombine turns costly ZExts into ANDs
1987 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
1988 if ((C->getAPIntValue()+1).isPowerOf2()) {
1989 MinBits = C->getAPIntValue().countTrailingOnes();
1990 PreZExt = N0->getOperand(0);
1992 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
1994 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
1995 MinBits = LN0->getMemoryVT().getSizeInBits();
2000 // Make sure we're not losing bits from the constant.
2001 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2002 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2003 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2004 // Will get folded away.
2005 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2006 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2007 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2012 // If the LHS is '(and load, const)', the RHS is 0,
2013 // the test is for equality or unsigned, and all 1 bits of the const are
2014 // in the same partial word, see if we can shorten the load.
2015 if (DCI.isBeforeLegalize() &&
2016 N0.getOpcode() == ISD::AND && C1 == 0 &&
2017 N0.getNode()->hasOneUse() &&
2018 isa<LoadSDNode>(N0.getOperand(0)) &&
2019 N0.getOperand(0).getNode()->hasOneUse() &&
2020 isa<ConstantSDNode>(N0.getOperand(1))) {
2021 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2023 unsigned bestWidth = 0, bestOffset = 0;
2024 if (!Lod->isVolatile() && Lod->isUnindexed()) {
2025 unsigned origWidth = N0.getValueType().getSizeInBits();
2026 unsigned maskWidth = origWidth;
2027 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2028 // 8 bits, but have to be careful...
2029 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2030 origWidth = Lod->getMemoryVT().getSizeInBits();
2032 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2033 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2034 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2035 for (unsigned offset=0; offset<origWidth/width; offset++) {
2036 if ((newMask & Mask) == Mask) {
2037 if (!TD->isLittleEndian())
2038 bestOffset = (origWidth/width - offset - 1) * (width/8);
2040 bestOffset = (uint64_t)offset * (width/8);
2041 bestMask = Mask.lshr(offset * (width/8) * 8);
2045 newMask = newMask << width;
2050 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2051 if (newVT.isRound()) {
2052 EVT PtrType = Lod->getOperand(1).getValueType();
2053 SDValue Ptr = Lod->getBasePtr();
2054 if (bestOffset != 0)
2055 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2056 DAG.getConstant(bestOffset, PtrType));
2057 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2058 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2059 Lod->getPointerInfo().getWithOffset(bestOffset),
2060 false, false, false, NewAlign);
2061 return DAG.getSetCC(dl, VT,
2062 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2063 DAG.getConstant(bestMask.trunc(bestWidth),
2065 DAG.getConstant(0LL, newVT), Cond);
2070 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2071 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2072 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2074 // If the comparison constant has bits in the upper part, the
2075 // zero-extended value could never match.
2076 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2077 C1.getBitWidth() - InSize))) {
2081 case ISD::SETEQ: return DAG.getConstant(0, VT);
2084 case ISD::SETNE: return DAG.getConstant(1, VT);
2087 // True if the sign bit of C1 is set.
2088 return DAG.getConstant(C1.isNegative(), VT);
2091 // True if the sign bit of C1 isn't set.
2092 return DAG.getConstant(C1.isNonNegative(), VT);
2098 // Otherwise, we can perform the comparison with the low bits.
2106 EVT newVT = N0.getOperand(0).getValueType();
2107 if (DCI.isBeforeLegalizeOps() ||
2108 (isOperationLegal(ISD::SETCC, newVT) &&
2109 getCondCodeAction(Cond, newVT)==Legal))
2110 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2111 DAG.getConstant(C1.trunc(InSize), newVT),
2116 break; // todo, be more careful with signed comparisons
2118 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2119 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2120 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2121 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2122 EVT ExtDstTy = N0.getValueType();
2123 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2125 // If the constant doesn't fit into the number of bits for the source of
2126 // the sign extension, it is impossible for both sides to be equal.
2127 if (C1.getMinSignedBits() > ExtSrcTyBits)
2128 return DAG.getConstant(Cond == ISD::SETNE, VT);
2131 EVT Op0Ty = N0.getOperand(0).getValueType();
2132 if (Op0Ty == ExtSrcTy) {
2133 ZextOp = N0.getOperand(0);
2135 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2136 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2137 DAG.getConstant(Imm, Op0Ty));
2139 if (!DCI.isCalledByLegalizer())
2140 DCI.AddToWorklist(ZextOp.getNode());
2141 // Otherwise, make this a use of a zext.
2142 return DAG.getSetCC(dl, VT, ZextOp,
2143 DAG.getConstant(C1 & APInt::getLowBitsSet(
2148 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2149 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2150 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2151 if (N0.getOpcode() == ISD::SETCC &&
2152 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2153 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2155 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2156 // Invert the condition.
2157 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2158 CC = ISD::getSetCCInverse(CC,
2159 N0.getOperand(0).getValueType().isInteger());
2160 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2163 if ((N0.getOpcode() == ISD::XOR ||
2164 (N0.getOpcode() == ISD::AND &&
2165 N0.getOperand(0).getOpcode() == ISD::XOR &&
2166 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2167 isa<ConstantSDNode>(N0.getOperand(1)) &&
2168 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2169 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2170 // can only do this if the top bits are known zero.
2171 unsigned BitWidth = N0.getValueSizeInBits();
2172 if (DAG.MaskedValueIsZero(N0,
2173 APInt::getHighBitsSet(BitWidth,
2175 // Okay, get the un-inverted input value.
2177 if (N0.getOpcode() == ISD::XOR)
2178 Val = N0.getOperand(0);
2180 assert(N0.getOpcode() == ISD::AND &&
2181 N0.getOperand(0).getOpcode() == ISD::XOR);
2182 // ((X^1)&1)^1 -> X & 1
2183 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2184 N0.getOperand(0).getOperand(0),
2188 return DAG.getSetCC(dl, VT, Val, N1,
2189 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2191 } else if (N1C->getAPIntValue() == 1 &&
2193 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2195 if (Op0.getOpcode() == ISD::TRUNCATE)
2196 Op0 = Op0.getOperand(0);
2198 if ((Op0.getOpcode() == ISD::XOR) &&
2199 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2200 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2201 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2202 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2203 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2205 } else if (Op0.getOpcode() == ISD::AND &&
2206 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2207 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2208 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2209 if (Op0.getValueType().bitsGT(VT))
2210 Op0 = DAG.getNode(ISD::AND, dl, VT,
2211 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2212 DAG.getConstant(1, VT));
2213 else if (Op0.getValueType().bitsLT(VT))
2214 Op0 = DAG.getNode(ISD::AND, dl, VT,
2215 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2216 DAG.getConstant(1, VT));
2218 return DAG.getSetCC(dl, VT, Op0,
2219 DAG.getConstant(0, Op0.getValueType()),
2220 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2225 APInt MinVal, MaxVal;
2226 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2227 if (ISD::isSignedIntSetCC(Cond)) {
2228 MinVal = APInt::getSignedMinValue(OperandBitSize);
2229 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2231 MinVal = APInt::getMinValue(OperandBitSize);
2232 MaxVal = APInt::getMaxValue(OperandBitSize);
2235 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2236 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2237 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2238 // X >= C0 --> X > (C0-1)
2239 return DAG.getSetCC(dl, VT, N0,
2240 DAG.getConstant(C1-1, N1.getValueType()),
2241 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2244 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2245 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2246 // X <= C0 --> X < (C0+1)
2247 return DAG.getSetCC(dl, VT, N0,
2248 DAG.getConstant(C1+1, N1.getValueType()),
2249 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2252 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2253 return DAG.getConstant(0, VT); // X < MIN --> false
2254 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2255 return DAG.getConstant(1, VT); // X >= MIN --> true
2256 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2257 return DAG.getConstant(0, VT); // X > MAX --> false
2258 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2259 return DAG.getConstant(1, VT); // X <= MAX --> true
2261 // Canonicalize setgt X, Min --> setne X, Min
2262 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2263 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2264 // Canonicalize setlt X, Max --> setne X, Max
2265 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2266 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2268 // If we have setult X, 1, turn it into seteq X, 0
2269 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2270 return DAG.getSetCC(dl, VT, N0,
2271 DAG.getConstant(MinVal, N0.getValueType()),
2273 // If we have setugt X, Max-1, turn it into seteq X, Max
2274 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2275 return DAG.getSetCC(dl, VT, N0,
2276 DAG.getConstant(MaxVal, N0.getValueType()),
2279 // If we have "setcc X, C0", check to see if we can shrink the immediate
2282 // SETUGT X, SINTMAX -> SETLT X, 0
2283 if (Cond == ISD::SETUGT &&
2284 C1 == APInt::getSignedMaxValue(OperandBitSize))
2285 return DAG.getSetCC(dl, VT, N0,
2286 DAG.getConstant(0, N1.getValueType()),
2289 // SETULT X, SINTMIN -> SETGT X, -1
2290 if (Cond == ISD::SETULT &&
2291 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2292 SDValue ConstMinusOne =
2293 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2295 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2298 // Fold bit comparisons when we can.
2299 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2300 (VT == N0.getValueType() ||
2301 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2302 N0.getOpcode() == ISD::AND)
2303 if (ConstantSDNode *AndRHS =
2304 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2305 EVT ShiftTy = DCI.isBeforeLegalize() ?
2306 getPointerTy() : getShiftAmountTy(N0.getValueType());
2307 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2308 // Perform the xform if the AND RHS is a single bit.
2309 if (AndRHS->getAPIntValue().isPowerOf2()) {
2310 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2311 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2312 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2314 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2315 // (X & 8) == 8 --> (X & 8) >> 3
2316 // Perform the xform if C1 is a single bit.
2317 if (C1.isPowerOf2()) {
2318 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2319 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2320 DAG.getConstant(C1.logBase2(), ShiftTy)));
2326 if (isa<ConstantFPSDNode>(N0.getNode())) {
2327 // Constant fold or commute setcc.
2328 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2329 if (O.getNode()) return O;
2330 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2331 // If the RHS of an FP comparison is a constant, simplify it away in
2333 if (CFP->getValueAPF().isNaN()) {
2334 // If an operand is known to be a nan, we can fold it.
2335 switch (ISD::getUnorderedFlavor(Cond)) {
2336 default: llvm_unreachable("Unknown flavor!");
2337 case 0: // Known false.
2338 return DAG.getConstant(0, VT);
2339 case 1: // Known true.
2340 return DAG.getConstant(1, VT);
2341 case 2: // Undefined.
2342 return DAG.getUNDEF(VT);
2346 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2347 // constant if knowing that the operand is non-nan is enough. We prefer to
2348 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2350 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2351 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2353 // If the condition is not legal, see if we can find an equivalent one
2355 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2356 // If the comparison was an awkward floating-point == or != and one of
2357 // the comparison operands is infinity or negative infinity, convert the
2358 // condition to a less-awkward <= or >=.
2359 if (CFP->getValueAPF().isInfinity()) {
2360 if (CFP->getValueAPF().isNegative()) {
2361 if (Cond == ISD::SETOEQ &&
2362 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2363 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2364 if (Cond == ISD::SETUEQ &&
2365 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2366 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2367 if (Cond == ISD::SETUNE &&
2368 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2369 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2370 if (Cond == ISD::SETONE &&
2371 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2372 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2374 if (Cond == ISD::SETOEQ &&
2375 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2376 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2377 if (Cond == ISD::SETUEQ &&
2378 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2379 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2380 if (Cond == ISD::SETUNE &&
2381 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2382 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2383 if (Cond == ISD::SETONE &&
2384 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2385 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2392 // We can always fold X == X for integer setcc's.
2393 if (N0.getValueType().isInteger()) {
2394 switch (getBooleanContents(N0.getValueType().isVector())) {
2395 case UndefinedBooleanContent:
2396 case ZeroOrOneBooleanContent:
2397 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2398 case ZeroOrNegativeOneBooleanContent:
2399 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
2402 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2403 if (UOF == 2) // FP operators that are undefined on NaNs.
2404 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2405 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2406 return DAG.getConstant(UOF, VT);
2407 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2408 // if it is not already.
2409 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2410 if (NewCond != Cond)
2411 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2414 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2415 N0.getValueType().isInteger()) {
2416 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2417 N0.getOpcode() == ISD::XOR) {
2418 // Simplify (X+Y) == (X+Z) --> Y == Z
2419 if (N0.getOpcode() == N1.getOpcode()) {
2420 if (N0.getOperand(0) == N1.getOperand(0))
2421 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2422 if (N0.getOperand(1) == N1.getOperand(1))
2423 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2424 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2425 // If X op Y == Y op X, try other combinations.
2426 if (N0.getOperand(0) == N1.getOperand(1))
2427 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2429 if (N0.getOperand(1) == N1.getOperand(0))
2430 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2435 // If RHS is a legal immediate value for a compare instruction, we need
2436 // to be careful about increasing register pressure needlessly.
2437 bool LegalRHSImm = false;
2439 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2440 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2441 // Turn (X+C1) == C2 --> X == C2-C1
2442 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2443 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2444 DAG.getConstant(RHSC->getAPIntValue()-
2445 LHSR->getAPIntValue(),
2446 N0.getValueType()), Cond);
2449 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2450 if (N0.getOpcode() == ISD::XOR)
2451 // If we know that all of the inverted bits are zero, don't bother
2452 // performing the inversion.
2453 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2455 DAG.getSetCC(dl, VT, N0.getOperand(0),
2456 DAG.getConstant(LHSR->getAPIntValue() ^
2457 RHSC->getAPIntValue(),
2462 // Turn (C1-X) == C2 --> X == C1-C2
2463 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2464 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2466 DAG.getSetCC(dl, VT, N0.getOperand(1),
2467 DAG.getConstant(SUBC->getAPIntValue() -
2468 RHSC->getAPIntValue(),
2474 // Could RHSC fold directly into a compare?
2475 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2476 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2479 // Simplify (X+Z) == X --> Z == 0
2480 // Don't do this if X is an immediate that can fold into a cmp
2481 // instruction and X+Z has other uses. It could be an induction variable
2482 // chain, and the transform would increase register pressure.
2483 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2484 if (N0.getOperand(0) == N1)
2485 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2486 DAG.getConstant(0, N0.getValueType()), Cond);
2487 if (N0.getOperand(1) == N1) {
2488 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2489 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2490 DAG.getConstant(0, N0.getValueType()), Cond);
2491 else if (N0.getNode()->hasOneUse()) {
2492 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2493 // (Z-X) == X --> Z == X<<1
2494 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2495 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2496 if (!DCI.isCalledByLegalizer())
2497 DCI.AddToWorklist(SH.getNode());
2498 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2504 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2505 N1.getOpcode() == ISD::XOR) {
2506 // Simplify X == (X+Z) --> Z == 0
2507 if (N1.getOperand(0) == N0) {
2508 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2509 DAG.getConstant(0, N1.getValueType()), Cond);
2510 } else if (N1.getOperand(1) == N0) {
2511 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2512 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2513 DAG.getConstant(0, N1.getValueType()), Cond);
2514 } else if (N1.getNode()->hasOneUse()) {
2515 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2516 // X == (Z-X) --> X<<1 == Z
2517 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2518 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2519 if (!DCI.isCalledByLegalizer())
2520 DCI.AddToWorklist(SH.getNode());
2521 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2526 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2527 // Note that where y is variable and is known to have at most
2528 // one bit set (for example, if it is z&1) we cannot do this;
2529 // the expressions are not equivalent when y==0.
2530 if (N0.getOpcode() == ISD::AND)
2531 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2532 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2533 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2534 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2535 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2538 if (N1.getOpcode() == ISD::AND)
2539 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2540 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2541 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2542 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2543 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2548 // Fold away ALL boolean setcc's.
2550 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2552 default: llvm_unreachable("Unknown integer setcc!");
2553 case ISD::SETEQ: // X == Y -> ~(X^Y)
2554 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2555 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2556 if (!DCI.isCalledByLegalizer())
2557 DCI.AddToWorklist(Temp.getNode());
2559 case ISD::SETNE: // X != Y --> (X^Y)
2560 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2562 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2563 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2564 Temp = DAG.getNOT(dl, N0, MVT::i1);
2565 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2566 if (!DCI.isCalledByLegalizer())
2567 DCI.AddToWorklist(Temp.getNode());
2569 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2570 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2571 Temp = DAG.getNOT(dl, N1, MVT::i1);
2572 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2573 if (!DCI.isCalledByLegalizer())
2574 DCI.AddToWorklist(Temp.getNode());
2576 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2577 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2578 Temp = DAG.getNOT(dl, N0, MVT::i1);
2579 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2580 if (!DCI.isCalledByLegalizer())
2581 DCI.AddToWorklist(Temp.getNode());
2583 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2584 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2585 Temp = DAG.getNOT(dl, N1, MVT::i1);
2586 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2589 if (VT != MVT::i1) {
2590 if (!DCI.isCalledByLegalizer())
2591 DCI.AddToWorklist(N0.getNode());
2592 // FIXME: If running after legalize, we probably can't do this.
2593 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2598 // Could not fold it.
2602 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2603 /// node is a GlobalAddress + offset.
2604 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2605 int64_t &Offset) const {
2606 if (isa<GlobalAddressSDNode>(N)) {
2607 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2608 GA = GASD->getGlobal();
2609 Offset += GASD->getOffset();
2613 if (N->getOpcode() == ISD::ADD) {
2614 SDValue N1 = N->getOperand(0);
2615 SDValue N2 = N->getOperand(1);
2616 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2617 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2619 Offset += V->getSExtValue();
2622 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2623 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2625 Offset += V->getSExtValue();
2635 SDValue TargetLowering::
2636 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2637 // Default implementation: no optimization.
2641 //===----------------------------------------------------------------------===//
2642 // Inline Assembler Implementation Methods
2643 //===----------------------------------------------------------------------===//
2646 TargetLowering::ConstraintType
2647 TargetLowering::getConstraintType(const std::string &Constraint) const {
2648 if (Constraint.size() == 1) {
2649 switch (Constraint[0]) {
2651 case 'r': return C_RegisterClass;
2653 case 'o': // offsetable
2654 case 'V': // not offsetable
2656 case 'i': // Simple Integer or Relocatable Constant
2657 case 'n': // Simple Integer
2658 case 'E': // Floating Point Constant
2659 case 'F': // Floating Point Constant
2660 case 's': // Relocatable Constant
2661 case 'p': // Address.
2662 case 'X': // Allow ANY value.
2663 case 'I': // Target registers.
2677 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2678 Constraint[Constraint.size()-1] == '}')
2683 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2684 /// with another that has more specific requirements based on the type of the
2685 /// corresponding operand.
2686 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2687 if (ConstraintVT.isInteger())
2689 if (ConstraintVT.isFloatingPoint())
2690 return "f"; // works for many targets
2694 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2695 /// vector. If it is invalid, don't add anything to Ops.
2696 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2697 std::string &Constraint,
2698 std::vector<SDValue> &Ops,
2699 SelectionDAG &DAG) const {
2701 if (Constraint.length() > 1) return;
2703 char ConstraintLetter = Constraint[0];
2704 switch (ConstraintLetter) {
2706 case 'X': // Allows any operand; labels (basic block) use this.
2707 if (Op.getOpcode() == ISD::BasicBlock) {
2712 case 'i': // Simple Integer or Relocatable Constant
2713 case 'n': // Simple Integer
2714 case 's': { // Relocatable Constant
2715 // These operands are interested in values of the form (GV+C), where C may
2716 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2717 // is possible and fine if either GV or C are missing.
2718 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2719 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2721 // If we have "(add GV, C)", pull out GV/C
2722 if (Op.getOpcode() == ISD::ADD) {
2723 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2724 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2725 if (C == 0 || GA == 0) {
2726 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2727 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2729 if (C == 0 || GA == 0)
2733 // If we find a valid operand, map to the TargetXXX version so that the
2734 // value itself doesn't get selected.
2735 if (GA) { // Either &GV or &GV+C
2736 if (ConstraintLetter != 'n') {
2737 int64_t Offs = GA->getOffset();
2738 if (C) Offs += C->getZExtValue();
2739 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2740 C ? C->getDebugLoc() : DebugLoc(),
2741 Op.getValueType(), Offs));
2745 if (C) { // just C, no GV.
2746 // Simple constants are not allowed for 's'.
2747 if (ConstraintLetter != 's') {
2748 // gcc prints these as sign extended. Sign extend value to 64 bits
2749 // now; without this it would get ZExt'd later in
2750 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2751 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2761 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2762 getRegForInlineAsmConstraint(const std::string &Constraint,
2764 if (Constraint[0] != '{')
2765 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2766 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2768 // Remove the braces from around the name.
2769 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2771 // Figure out which register class contains this reg.
2772 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2773 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2774 E = RI->regclass_end(); RCI != E; ++RCI) {
2775 const TargetRegisterClass *RC = *RCI;
2777 // If none of the value types for this register class are valid, we
2778 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2782 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2784 if (RegName.equals_lower(RI->getName(*I)))
2785 return std::make_pair(*I, RC);
2789 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2792 //===----------------------------------------------------------------------===//
2793 // Constraint Selection.
2795 /// isMatchingInputConstraint - Return true of this is an input operand that is
2796 /// a matching constraint like "4".
2797 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2798 assert(!ConstraintCode.empty() && "No known constraint!");
2799 return isdigit(ConstraintCode[0]);
2802 /// getMatchedOperand - If this is an input matching constraint, this method
2803 /// returns the output operand it matches.
2804 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2805 assert(!ConstraintCode.empty() && "No known constraint!");
2806 return atoi(ConstraintCode.c_str());
2810 /// ParseConstraints - Split up the constraint string from the inline
2811 /// assembly value into the specific constraints and their prefixes,
2812 /// and also tie in the associated operand values.
2813 /// If this returns an empty vector, and if the constraint string itself
2814 /// isn't empty, there was an error parsing.
2815 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2816 ImmutableCallSite CS) const {
2817 /// ConstraintOperands - Information about all of the constraints.
2818 AsmOperandInfoVector ConstraintOperands;
2819 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2820 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2822 // Do a prepass over the constraints, canonicalizing them, and building up the
2823 // ConstraintOperands list.
2824 InlineAsm::ConstraintInfoVector
2825 ConstraintInfos = IA->ParseConstraints();
2827 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2828 unsigned ResNo = 0; // ResNo - The result number of the next output.
2830 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2831 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2832 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2834 // Update multiple alternative constraint count.
2835 if (OpInfo.multipleAlternatives.size() > maCount)
2836 maCount = OpInfo.multipleAlternatives.size();
2838 OpInfo.ConstraintVT = MVT::Other;
2840 // Compute the value type for each operand.
2841 switch (OpInfo.Type) {
2842 case InlineAsm::isOutput:
2843 // Indirect outputs just consume an argument.
2844 if (OpInfo.isIndirect) {
2845 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2849 // The return value of the call is this value. As such, there is no
2850 // corresponding argument.
2851 assert(!CS.getType()->isVoidTy() &&
2853 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2854 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2856 assert(ResNo == 0 && "Asm only has one result!");
2857 OpInfo.ConstraintVT = getValueType(CS.getType());
2861 case InlineAsm::isInput:
2862 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2864 case InlineAsm::isClobber:
2869 if (OpInfo.CallOperandVal) {
2870 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2871 if (OpInfo.isIndirect) {
2872 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2874 report_fatal_error("Indirect operand for inline asm not a pointer!");
2875 OpTy = PtrTy->getElementType();
2878 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2879 if (StructType *STy = dyn_cast<StructType>(OpTy))
2880 if (STy->getNumElements() == 1)
2881 OpTy = STy->getElementType(0);
2883 // If OpTy is not a single value, it may be a struct/union that we
2884 // can tile with integers.
2885 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2886 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2895 OpInfo.ConstraintVT =
2896 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2899 } else if (dyn_cast<PointerType>(OpTy)) {
2900 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2902 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2907 // If we have multiple alternative constraints, select the best alternative.
2908 if (ConstraintInfos.size()) {
2910 unsigned bestMAIndex = 0;
2911 int bestWeight = -1;
2912 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2915 // Compute the sums of the weights for each alternative, keeping track
2916 // of the best (highest weight) one so far.
2917 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2919 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2920 cIndex != eIndex; ++cIndex) {
2921 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2922 if (OpInfo.Type == InlineAsm::isClobber)
2925 // If this is an output operand with a matching input operand,
2926 // look up the matching input. If their types mismatch, e.g. one
2927 // is an integer, the other is floating point, or their sizes are
2928 // different, flag it as an maCantMatch.
2929 if (OpInfo.hasMatchingInput()) {
2930 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2931 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2932 if ((OpInfo.ConstraintVT.isInteger() !=
2933 Input.ConstraintVT.isInteger()) ||
2934 (OpInfo.ConstraintVT.getSizeInBits() !=
2935 Input.ConstraintVT.getSizeInBits())) {
2936 weightSum = -1; // Can't match.
2941 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2946 weightSum += weight;
2949 if (weightSum > bestWeight) {
2950 bestWeight = weightSum;
2951 bestMAIndex = maIndex;
2955 // Now select chosen alternative in each constraint.
2956 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2957 cIndex != eIndex; ++cIndex) {
2958 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2959 if (cInfo.Type == InlineAsm::isClobber)
2961 cInfo.selectAlternative(bestMAIndex);
2966 // Check and hook up tied operands, choose constraint code to use.
2967 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2968 cIndex != eIndex; ++cIndex) {
2969 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2971 // If this is an output operand with a matching input operand, look up the
2972 // matching input. If their types mismatch, e.g. one is an integer, the
2973 // other is floating point, or their sizes are different, flag it as an
2975 if (OpInfo.hasMatchingInput()) {
2976 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2978 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2979 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2980 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
2981 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2982 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
2983 if ((OpInfo.ConstraintVT.isInteger() !=
2984 Input.ConstraintVT.isInteger()) ||
2985 (MatchRC.second != InputRC.second)) {
2986 report_fatal_error("Unsupported asm: input constraint"
2987 " with a matching output constraint of"
2988 " incompatible type!");
2995 return ConstraintOperands;
2999 /// getConstraintGenerality - Return an integer indicating how general CT
3001 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3003 case TargetLowering::C_Other:
3004 case TargetLowering::C_Unknown:
3006 case TargetLowering::C_Register:
3008 case TargetLowering::C_RegisterClass:
3010 case TargetLowering::C_Memory:
3013 llvm_unreachable("Invalid constraint type");
3016 /// Examine constraint type and operand type and determine a weight value.
3017 /// This object must already have been set up with the operand type
3018 /// and the current alternative constraint selected.
3019 TargetLowering::ConstraintWeight
3020 TargetLowering::getMultipleConstraintMatchWeight(
3021 AsmOperandInfo &info, int maIndex) const {
3022 InlineAsm::ConstraintCodeVector *rCodes;
3023 if (maIndex >= (int)info.multipleAlternatives.size())
3024 rCodes = &info.Codes;
3026 rCodes = &info.multipleAlternatives[maIndex].Codes;
3027 ConstraintWeight BestWeight = CW_Invalid;
3029 // Loop over the options, keeping track of the most general one.
3030 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3031 ConstraintWeight weight =
3032 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3033 if (weight > BestWeight)
3034 BestWeight = weight;
3040 /// Examine constraint type and operand type and determine a weight value.
3041 /// This object must already have been set up with the operand type
3042 /// and the current alternative constraint selected.
3043 TargetLowering::ConstraintWeight
3044 TargetLowering::getSingleConstraintMatchWeight(
3045 AsmOperandInfo &info, const char *constraint) const {
3046 ConstraintWeight weight = CW_Invalid;
3047 Value *CallOperandVal = info.CallOperandVal;
3048 // If we don't have a value, we can't do a match,
3049 // but allow it at the lowest weight.
3050 if (CallOperandVal == NULL)
3052 // Look at the constraint type.
3053 switch (*constraint) {
3054 case 'i': // immediate integer.
3055 case 'n': // immediate integer with a known value.
3056 if (isa<ConstantInt>(CallOperandVal))
3057 weight = CW_Constant;
3059 case 's': // non-explicit intregal immediate.
3060 if (isa<GlobalValue>(CallOperandVal))
3061 weight = CW_Constant;
3063 case 'E': // immediate float if host format.
3064 case 'F': // immediate float.
3065 if (isa<ConstantFP>(CallOperandVal))
3066 weight = CW_Constant;
3068 case '<': // memory operand with autodecrement.
3069 case '>': // memory operand with autoincrement.
3070 case 'm': // memory operand.
3071 case 'o': // offsettable memory operand
3072 case 'V': // non-offsettable memory operand
3075 case 'r': // general register.
3076 case 'g': // general register, memory operand or immediate integer.
3077 // note: Clang converts "g" to "imr".
3078 if (CallOperandVal->getType()->isIntegerTy())
3079 weight = CW_Register;
3081 case 'X': // any operand.
3083 weight = CW_Default;
3089 /// ChooseConstraint - If there are multiple different constraints that we
3090 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3091 /// This is somewhat tricky: constraints fall into four classes:
3092 /// Other -> immediates and magic values
3093 /// Register -> one specific register
3094 /// RegisterClass -> a group of regs
3095 /// Memory -> memory
3096 /// Ideally, we would pick the most specific constraint possible: if we have
3097 /// something that fits into a register, we would pick it. The problem here
3098 /// is that if we have something that could either be in a register or in
3099 /// memory that use of the register could cause selection of *other*
3100 /// operands to fail: they might only succeed if we pick memory. Because of
3101 /// this the heuristic we use is:
3103 /// 1) If there is an 'other' constraint, and if the operand is valid for
3104 /// that constraint, use it. This makes us take advantage of 'i'
3105 /// constraints when available.
3106 /// 2) Otherwise, pick the most general constraint present. This prefers
3107 /// 'm' over 'r', for example.
3109 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3110 const TargetLowering &TLI,
3111 SDValue Op, SelectionDAG *DAG) {
3112 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3113 unsigned BestIdx = 0;
3114 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3115 int BestGenerality = -1;
3117 // Loop over the options, keeping track of the most general one.
3118 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3119 TargetLowering::ConstraintType CType =
3120 TLI.getConstraintType(OpInfo.Codes[i]);
3122 // If this is an 'other' constraint, see if the operand is valid for it.
3123 // For example, on X86 we might have an 'rI' constraint. If the operand
3124 // is an integer in the range [0..31] we want to use I (saving a load
3125 // of a register), otherwise we must use 'r'.
3126 if (CType == TargetLowering::C_Other && Op.getNode()) {
3127 assert(OpInfo.Codes[i].size() == 1 &&
3128 "Unhandled multi-letter 'other' constraint");
3129 std::vector<SDValue> ResultOps;
3130 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3132 if (!ResultOps.empty()) {
3139 // Things with matching constraints can only be registers, per gcc
3140 // documentation. This mainly affects "g" constraints.
3141 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3144 // This constraint letter is more general than the previous one, use it.
3145 int Generality = getConstraintGenerality(CType);
3146 if (Generality > BestGenerality) {
3149 BestGenerality = Generality;
3153 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3154 OpInfo.ConstraintType = BestType;
3157 /// ComputeConstraintToUse - Determines the constraint code and constraint
3158 /// type to use for the specific AsmOperandInfo, setting
3159 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3160 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3162 SelectionDAG *DAG) const {
3163 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3165 // Single-letter constraints ('r') are very common.
3166 if (OpInfo.Codes.size() == 1) {
3167 OpInfo.ConstraintCode = OpInfo.Codes[0];
3168 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3170 ChooseConstraint(OpInfo, *this, Op, DAG);
3173 // 'X' matches anything.
3174 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3175 // Labels and constants are handled elsewhere ('X' is the only thing
3176 // that matches labels). For Functions, the type here is the type of
3177 // the result, which is not what we want to look at; leave them alone.
3178 Value *v = OpInfo.CallOperandVal;
3179 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3180 OpInfo.CallOperandVal = v;
3184 // Otherwise, try to resolve it to something we know about by looking at
3185 // the actual operand type.
3186 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3187 OpInfo.ConstraintCode = Repl;
3188 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3193 //===----------------------------------------------------------------------===//
3194 // Loop Strength Reduction hooks
3195 //===----------------------------------------------------------------------===//
3197 /// isLegalAddressingMode - Return true if the addressing mode represented
3198 /// by AM is legal for this target, for a load/store of the specified type.
3199 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3201 // The default implementation of this implements a conservative RISCy, r+r and
3204 // Allows a sign-extended 16-bit immediate field.
3205 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3208 // No global is ever allowed as a base.
3212 // Only support r+r,
3214 case 0: // "r+i" or just "i", depending on HasBaseReg.
3217 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3219 // Otherwise we have r+r or r+i.
3222 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3224 // Allow 2*r as r+r.
3231 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3232 /// with the multiplicative inverse of the constant.
3233 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3234 SelectionDAG &DAG) const {
3235 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3236 APInt d = C->getAPIntValue();
3237 assert(d != 0 && "Division by zero!");
3239 // Shift the value upfront if it is even, so the LSB is one.
3240 unsigned ShAmt = d.countTrailingZeros();
3242 // TODO: For UDIV use SRL instead of SRA.
3243 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3244 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3248 // Calculate the multiplicative inverse, using Newton's method.
3250 while ((t = d*xn) != 1)
3251 xn *= APInt(d.getBitWidth(), 2) - t;
3253 Op2 = DAG.getConstant(xn, Op1.getValueType());
3254 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3257 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3258 /// return a DAG expression to select that will generate the same value by
3259 /// multiplying by a magic number. See:
3260 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3261 SDValue TargetLowering::
3262 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3263 std::vector<SDNode*>* Created) const {
3264 EVT VT = N->getValueType(0);
3265 DebugLoc dl= N->getDebugLoc();
3267 // Check to see if we can do this.
3268 // FIXME: We should be more aggressive here.
3269 if (!isTypeLegal(VT))
3272 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3273 APInt::ms magics = d.magic();
3275 // Multiply the numerator (operand 0) by the magic value
3276 // FIXME: We should support doing a MUL in a wider type
3278 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3279 isOperationLegalOrCustom(ISD::MULHS, VT))
3280 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3281 DAG.getConstant(magics.m, VT));
3282 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3283 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3284 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3286 DAG.getConstant(magics.m, VT)).getNode(), 1);
3288 return SDValue(); // No mulhs or equvialent
3289 // If d > 0 and m < 0, add the numerator
3290 if (d.isStrictlyPositive() && magics.m.isNegative()) {
3291 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3293 Created->push_back(Q.getNode());
3295 // If d < 0 and m > 0, subtract the numerator.
3296 if (d.isNegative() && magics.m.isStrictlyPositive()) {
3297 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3299 Created->push_back(Q.getNode());
3301 // Shift right algebraic if shift value is nonzero
3303 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3304 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3306 Created->push_back(Q.getNode());
3308 // Extract the sign bit and add it to the quotient
3310 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3311 getShiftAmountTy(Q.getValueType())));
3313 Created->push_back(T.getNode());
3314 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3317 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3318 /// return a DAG expression to select that will generate the same value by
3319 /// multiplying by a magic number. See:
3320 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3321 SDValue TargetLowering::
3322 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3323 std::vector<SDNode*>* Created) const {
3324 EVT VT = N->getValueType(0);
3325 DebugLoc dl = N->getDebugLoc();
3327 // Check to see if we can do this.
3328 // FIXME: We should be more aggressive here.
3329 if (!isTypeLegal(VT))
3332 // FIXME: We should use a narrower constant when the upper
3333 // bits are known to be zero.
3334 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3335 APInt::mu magics = N1C.magicu();
3337 SDValue Q = N->getOperand(0);
3339 // If the divisor is even, we can avoid using the expensive fixup by shifting
3340 // the divided value upfront.
3341 if (magics.a != 0 && !N1C[0]) {
3342 unsigned Shift = N1C.countTrailingZeros();
3343 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3344 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3346 Created->push_back(Q.getNode());
3348 // Get magic number for the shifted divisor.
3349 magics = N1C.lshr(Shift).magicu(Shift);
3350 assert(magics.a == 0 && "Should use cheap fixup now");
3353 // Multiply the numerator (operand 0) by the magic value
3354 // FIXME: We should support doing a MUL in a wider type
3355 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3356 isOperationLegalOrCustom(ISD::MULHU, VT))
3357 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3358 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3359 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3360 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3361 DAG.getConstant(magics.m, VT)).getNode(), 1);
3363 return SDValue(); // No mulhu or equvialent
3365 Created->push_back(Q.getNode());
3367 if (magics.a == 0) {
3368 assert(magics.s < N1C.getBitWidth() &&
3369 "We shouldn't generate an undefined shift!");
3370 return DAG.getNode(ISD::SRL, dl, VT, Q,
3371 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3373 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3375 Created->push_back(NPQ.getNode());
3376 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3377 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3379 Created->push_back(NPQ.getNode());
3380 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3382 Created->push_back(NPQ.getNode());
3383 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3384 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));