1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
35 /// We are in the process of implementing a new TypeLegalization action
36 /// - the promotion of vector elements. This feature is disabled by default
37 /// and only enabled using this flag.
39 AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
40 cl::desc("Allow promotion of integer vector element types"));
43 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) {
44 bool isLocal = GV->hasLocalLinkage();
45 bool isDeclaration = GV->isDeclaration();
46 // FIXME: what should we do for protected and internal visibility?
47 // For variables, is internal different from hidden?
48 bool isHidden = GV->hasHiddenVisibility();
50 if (reloc == Reloc::PIC_) {
51 if (isLocal || isHidden)
52 return TLSModel::LocalDynamic;
54 return TLSModel::GeneralDynamic;
56 if (!isDeclaration || isHidden)
57 return TLSModel::LocalExec;
59 return TLSModel::InitialExec;
64 /// InitLibcallNames - Set default libcall names.
66 static void InitLibcallNames(const char **Names) {
67 Names[RTLIB::SHL_I16] = "__ashlhi3";
68 Names[RTLIB::SHL_I32] = "__ashlsi3";
69 Names[RTLIB::SHL_I64] = "__ashldi3";
70 Names[RTLIB::SHL_I128] = "__ashlti3";
71 Names[RTLIB::SRL_I16] = "__lshrhi3";
72 Names[RTLIB::SRL_I32] = "__lshrsi3";
73 Names[RTLIB::SRL_I64] = "__lshrdi3";
74 Names[RTLIB::SRL_I128] = "__lshrti3";
75 Names[RTLIB::SRA_I16] = "__ashrhi3";
76 Names[RTLIB::SRA_I32] = "__ashrsi3";
77 Names[RTLIB::SRA_I64] = "__ashrdi3";
78 Names[RTLIB::SRA_I128] = "__ashrti3";
79 Names[RTLIB::MUL_I8] = "__mulqi3";
80 Names[RTLIB::MUL_I16] = "__mulhi3";
81 Names[RTLIB::MUL_I32] = "__mulsi3";
82 Names[RTLIB::MUL_I64] = "__muldi3";
83 Names[RTLIB::MUL_I128] = "__multi3";
84 Names[RTLIB::MULO_I32] = "__mulosi4";
85 Names[RTLIB::MULO_I64] = "__mulodi4";
86 Names[RTLIB::MULO_I128] = "__muloti4";
87 Names[RTLIB::SDIV_I8] = "__divqi3";
88 Names[RTLIB::SDIV_I16] = "__divhi3";
89 Names[RTLIB::SDIV_I32] = "__divsi3";
90 Names[RTLIB::SDIV_I64] = "__divdi3";
91 Names[RTLIB::SDIV_I128] = "__divti3";
92 Names[RTLIB::UDIV_I8] = "__udivqi3";
93 Names[RTLIB::UDIV_I16] = "__udivhi3";
94 Names[RTLIB::UDIV_I32] = "__udivsi3";
95 Names[RTLIB::UDIV_I64] = "__udivdi3";
96 Names[RTLIB::UDIV_I128] = "__udivti3";
97 Names[RTLIB::SREM_I8] = "__modqi3";
98 Names[RTLIB::SREM_I16] = "__modhi3";
99 Names[RTLIB::SREM_I32] = "__modsi3";
100 Names[RTLIB::SREM_I64] = "__moddi3";
101 Names[RTLIB::SREM_I128] = "__modti3";
102 Names[RTLIB::UREM_I8] = "__umodqi3";
103 Names[RTLIB::UREM_I16] = "__umodhi3";
104 Names[RTLIB::UREM_I32] = "__umodsi3";
105 Names[RTLIB::UREM_I64] = "__umoddi3";
106 Names[RTLIB::UREM_I128] = "__umodti3";
108 // These are generally not available.
109 Names[RTLIB::SDIVREM_I8] = 0;
110 Names[RTLIB::SDIVREM_I16] = 0;
111 Names[RTLIB::SDIVREM_I32] = 0;
112 Names[RTLIB::SDIVREM_I64] = 0;
113 Names[RTLIB::SDIVREM_I128] = 0;
114 Names[RTLIB::UDIVREM_I8] = 0;
115 Names[RTLIB::UDIVREM_I16] = 0;
116 Names[RTLIB::UDIVREM_I32] = 0;
117 Names[RTLIB::UDIVREM_I64] = 0;
118 Names[RTLIB::UDIVREM_I128] = 0;
120 Names[RTLIB::NEG_I32] = "__negsi2";
121 Names[RTLIB::NEG_I64] = "__negdi2";
122 Names[RTLIB::ADD_F32] = "__addsf3";
123 Names[RTLIB::ADD_F64] = "__adddf3";
124 Names[RTLIB::ADD_F80] = "__addxf3";
125 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
126 Names[RTLIB::SUB_F32] = "__subsf3";
127 Names[RTLIB::SUB_F64] = "__subdf3";
128 Names[RTLIB::SUB_F80] = "__subxf3";
129 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
130 Names[RTLIB::MUL_F32] = "__mulsf3";
131 Names[RTLIB::MUL_F64] = "__muldf3";
132 Names[RTLIB::MUL_F80] = "__mulxf3";
133 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
134 Names[RTLIB::DIV_F32] = "__divsf3";
135 Names[RTLIB::DIV_F64] = "__divdf3";
136 Names[RTLIB::DIV_F80] = "__divxf3";
137 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
138 Names[RTLIB::REM_F32] = "fmodf";
139 Names[RTLIB::REM_F64] = "fmod";
140 Names[RTLIB::REM_F80] = "fmodl";
141 Names[RTLIB::REM_PPCF128] = "fmodl";
142 Names[RTLIB::FMA_F32] = "fmaf";
143 Names[RTLIB::FMA_F64] = "fma";
144 Names[RTLIB::FMA_F80] = "fmal";
145 Names[RTLIB::FMA_PPCF128] = "fmal";
146 Names[RTLIB::POWI_F32] = "__powisf2";
147 Names[RTLIB::POWI_F64] = "__powidf2";
148 Names[RTLIB::POWI_F80] = "__powixf2";
149 Names[RTLIB::POWI_PPCF128] = "__powitf2";
150 Names[RTLIB::SQRT_F32] = "sqrtf";
151 Names[RTLIB::SQRT_F64] = "sqrt";
152 Names[RTLIB::SQRT_F80] = "sqrtl";
153 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
154 Names[RTLIB::LOG_F32] = "logf";
155 Names[RTLIB::LOG_F64] = "log";
156 Names[RTLIB::LOG_F80] = "logl";
157 Names[RTLIB::LOG_PPCF128] = "logl";
158 Names[RTLIB::LOG2_F32] = "log2f";
159 Names[RTLIB::LOG2_F64] = "log2";
160 Names[RTLIB::LOG2_F80] = "log2l";
161 Names[RTLIB::LOG2_PPCF128] = "log2l";
162 Names[RTLIB::LOG10_F32] = "log10f";
163 Names[RTLIB::LOG10_F64] = "log10";
164 Names[RTLIB::LOG10_F80] = "log10l";
165 Names[RTLIB::LOG10_PPCF128] = "log10l";
166 Names[RTLIB::EXP_F32] = "expf";
167 Names[RTLIB::EXP_F64] = "exp";
168 Names[RTLIB::EXP_F80] = "expl";
169 Names[RTLIB::EXP_PPCF128] = "expl";
170 Names[RTLIB::EXP2_F32] = "exp2f";
171 Names[RTLIB::EXP2_F64] = "exp2";
172 Names[RTLIB::EXP2_F80] = "exp2l";
173 Names[RTLIB::EXP2_PPCF128] = "exp2l";
174 Names[RTLIB::SIN_F32] = "sinf";
175 Names[RTLIB::SIN_F64] = "sin";
176 Names[RTLIB::SIN_F80] = "sinl";
177 Names[RTLIB::SIN_PPCF128] = "sinl";
178 Names[RTLIB::COS_F32] = "cosf";
179 Names[RTLIB::COS_F64] = "cos";
180 Names[RTLIB::COS_F80] = "cosl";
181 Names[RTLIB::COS_PPCF128] = "cosl";
182 Names[RTLIB::POW_F32] = "powf";
183 Names[RTLIB::POW_F64] = "pow";
184 Names[RTLIB::POW_F80] = "powl";
185 Names[RTLIB::POW_PPCF128] = "powl";
186 Names[RTLIB::CEIL_F32] = "ceilf";
187 Names[RTLIB::CEIL_F64] = "ceil";
188 Names[RTLIB::CEIL_F80] = "ceill";
189 Names[RTLIB::CEIL_PPCF128] = "ceill";
190 Names[RTLIB::TRUNC_F32] = "truncf";
191 Names[RTLIB::TRUNC_F64] = "trunc";
192 Names[RTLIB::TRUNC_F80] = "truncl";
193 Names[RTLIB::TRUNC_PPCF128] = "truncl";
194 Names[RTLIB::RINT_F32] = "rintf";
195 Names[RTLIB::RINT_F64] = "rint";
196 Names[RTLIB::RINT_F80] = "rintl";
197 Names[RTLIB::RINT_PPCF128] = "rintl";
198 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
199 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
200 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
201 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
202 Names[RTLIB::FLOOR_F32] = "floorf";
203 Names[RTLIB::FLOOR_F64] = "floor";
204 Names[RTLIB::FLOOR_F80] = "floorl";
205 Names[RTLIB::FLOOR_PPCF128] = "floorl";
206 Names[RTLIB::COPYSIGN_F32] = "copysignf";
207 Names[RTLIB::COPYSIGN_F64] = "copysign";
208 Names[RTLIB::COPYSIGN_F80] = "copysignl";
209 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
210 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
211 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
212 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
213 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
214 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
215 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
216 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
217 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
218 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
219 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
220 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
221 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
222 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
223 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
224 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
225 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
226 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
227 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
228 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
229 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
230 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
231 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
232 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
233 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
234 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
235 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
236 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
237 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
238 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
239 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
240 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
241 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
242 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
243 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
244 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
245 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
246 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
247 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
248 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
249 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
250 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
251 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
252 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
253 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
254 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
255 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
256 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
257 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
258 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
259 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
260 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
261 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
262 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
263 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
264 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
265 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
266 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
267 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
268 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
269 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
270 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
271 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
272 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
273 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
274 Names[RTLIB::OEQ_F32] = "__eqsf2";
275 Names[RTLIB::OEQ_F64] = "__eqdf2";
276 Names[RTLIB::UNE_F32] = "__nesf2";
277 Names[RTLIB::UNE_F64] = "__nedf2";
278 Names[RTLIB::OGE_F32] = "__gesf2";
279 Names[RTLIB::OGE_F64] = "__gedf2";
280 Names[RTLIB::OLT_F32] = "__ltsf2";
281 Names[RTLIB::OLT_F64] = "__ltdf2";
282 Names[RTLIB::OLE_F32] = "__lesf2";
283 Names[RTLIB::OLE_F64] = "__ledf2";
284 Names[RTLIB::OGT_F32] = "__gtsf2";
285 Names[RTLIB::OGT_F64] = "__gtdf2";
286 Names[RTLIB::UO_F32] = "__unordsf2";
287 Names[RTLIB::UO_F64] = "__unorddf2";
288 Names[RTLIB::O_F32] = "__unordsf2";
289 Names[RTLIB::O_F64] = "__unorddf2";
290 Names[RTLIB::MEMCPY] = "memcpy";
291 Names[RTLIB::MEMMOVE] = "memmove";
292 Names[RTLIB::MEMSET] = "memset";
293 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
294 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
295 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
296 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
297 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
298 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
299 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
300 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
301 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
302 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
303 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
304 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
305 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
306 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
307 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
308 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
309 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
310 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
311 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
312 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
313 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
314 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
315 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
316 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
317 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
318 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
319 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
320 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
321 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
322 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
323 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
324 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
325 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
328 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
330 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
331 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
332 CCs[i] = CallingConv::C;
336 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
337 /// UNKNOWN_LIBCALL if there is none.
338 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
339 if (OpVT == MVT::f32) {
340 if (RetVT == MVT::f64)
341 return FPEXT_F32_F64;
344 return UNKNOWN_LIBCALL;
347 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
348 /// UNKNOWN_LIBCALL if there is none.
349 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
350 if (RetVT == MVT::f32) {
351 if (OpVT == MVT::f64)
352 return FPROUND_F64_F32;
353 if (OpVT == MVT::f80)
354 return FPROUND_F80_F32;
355 if (OpVT == MVT::ppcf128)
356 return FPROUND_PPCF128_F32;
357 } else if (RetVT == MVT::f64) {
358 if (OpVT == MVT::f80)
359 return FPROUND_F80_F64;
360 if (OpVT == MVT::ppcf128)
361 return FPROUND_PPCF128_F64;
364 return UNKNOWN_LIBCALL;
367 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
368 /// UNKNOWN_LIBCALL if there is none.
369 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
370 if (OpVT == MVT::f32) {
371 if (RetVT == MVT::i8)
372 return FPTOSINT_F32_I8;
373 if (RetVT == MVT::i16)
374 return FPTOSINT_F32_I16;
375 if (RetVT == MVT::i32)
376 return FPTOSINT_F32_I32;
377 if (RetVT == MVT::i64)
378 return FPTOSINT_F32_I64;
379 if (RetVT == MVT::i128)
380 return FPTOSINT_F32_I128;
381 } else if (OpVT == MVT::f64) {
382 if (RetVT == MVT::i8)
383 return FPTOSINT_F64_I8;
384 if (RetVT == MVT::i16)
385 return FPTOSINT_F64_I16;
386 if (RetVT == MVT::i32)
387 return FPTOSINT_F64_I32;
388 if (RetVT == MVT::i64)
389 return FPTOSINT_F64_I64;
390 if (RetVT == MVT::i128)
391 return FPTOSINT_F64_I128;
392 } else if (OpVT == MVT::f80) {
393 if (RetVT == MVT::i32)
394 return FPTOSINT_F80_I32;
395 if (RetVT == MVT::i64)
396 return FPTOSINT_F80_I64;
397 if (RetVT == MVT::i128)
398 return FPTOSINT_F80_I128;
399 } else if (OpVT == MVT::ppcf128) {
400 if (RetVT == MVT::i32)
401 return FPTOSINT_PPCF128_I32;
402 if (RetVT == MVT::i64)
403 return FPTOSINT_PPCF128_I64;
404 if (RetVT == MVT::i128)
405 return FPTOSINT_PPCF128_I128;
407 return UNKNOWN_LIBCALL;
410 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
411 /// UNKNOWN_LIBCALL if there is none.
412 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
413 if (OpVT == MVT::f32) {
414 if (RetVT == MVT::i8)
415 return FPTOUINT_F32_I8;
416 if (RetVT == MVT::i16)
417 return FPTOUINT_F32_I16;
418 if (RetVT == MVT::i32)
419 return FPTOUINT_F32_I32;
420 if (RetVT == MVT::i64)
421 return FPTOUINT_F32_I64;
422 if (RetVT == MVT::i128)
423 return FPTOUINT_F32_I128;
424 } else if (OpVT == MVT::f64) {
425 if (RetVT == MVT::i8)
426 return FPTOUINT_F64_I8;
427 if (RetVT == MVT::i16)
428 return FPTOUINT_F64_I16;
429 if (RetVT == MVT::i32)
430 return FPTOUINT_F64_I32;
431 if (RetVT == MVT::i64)
432 return FPTOUINT_F64_I64;
433 if (RetVT == MVT::i128)
434 return FPTOUINT_F64_I128;
435 } else if (OpVT == MVT::f80) {
436 if (RetVT == MVT::i32)
437 return FPTOUINT_F80_I32;
438 if (RetVT == MVT::i64)
439 return FPTOUINT_F80_I64;
440 if (RetVT == MVT::i128)
441 return FPTOUINT_F80_I128;
442 } else if (OpVT == MVT::ppcf128) {
443 if (RetVT == MVT::i32)
444 return FPTOUINT_PPCF128_I32;
445 if (RetVT == MVT::i64)
446 return FPTOUINT_PPCF128_I64;
447 if (RetVT == MVT::i128)
448 return FPTOUINT_PPCF128_I128;
450 return UNKNOWN_LIBCALL;
453 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
454 /// UNKNOWN_LIBCALL if there is none.
455 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
456 if (OpVT == MVT::i32) {
457 if (RetVT == MVT::f32)
458 return SINTTOFP_I32_F32;
459 else if (RetVT == MVT::f64)
460 return SINTTOFP_I32_F64;
461 else if (RetVT == MVT::f80)
462 return SINTTOFP_I32_F80;
463 else if (RetVT == MVT::ppcf128)
464 return SINTTOFP_I32_PPCF128;
465 } else if (OpVT == MVT::i64) {
466 if (RetVT == MVT::f32)
467 return SINTTOFP_I64_F32;
468 else if (RetVT == MVT::f64)
469 return SINTTOFP_I64_F64;
470 else if (RetVT == MVT::f80)
471 return SINTTOFP_I64_F80;
472 else if (RetVT == MVT::ppcf128)
473 return SINTTOFP_I64_PPCF128;
474 } else if (OpVT == MVT::i128) {
475 if (RetVT == MVT::f32)
476 return SINTTOFP_I128_F32;
477 else if (RetVT == MVT::f64)
478 return SINTTOFP_I128_F64;
479 else if (RetVT == MVT::f80)
480 return SINTTOFP_I128_F80;
481 else if (RetVT == MVT::ppcf128)
482 return SINTTOFP_I128_PPCF128;
484 return UNKNOWN_LIBCALL;
487 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
488 /// UNKNOWN_LIBCALL if there is none.
489 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
490 if (OpVT == MVT::i32) {
491 if (RetVT == MVT::f32)
492 return UINTTOFP_I32_F32;
493 else if (RetVT == MVT::f64)
494 return UINTTOFP_I32_F64;
495 else if (RetVT == MVT::f80)
496 return UINTTOFP_I32_F80;
497 else if (RetVT == MVT::ppcf128)
498 return UINTTOFP_I32_PPCF128;
499 } else if (OpVT == MVT::i64) {
500 if (RetVT == MVT::f32)
501 return UINTTOFP_I64_F32;
502 else if (RetVT == MVT::f64)
503 return UINTTOFP_I64_F64;
504 else if (RetVT == MVT::f80)
505 return UINTTOFP_I64_F80;
506 else if (RetVT == MVT::ppcf128)
507 return UINTTOFP_I64_PPCF128;
508 } else if (OpVT == MVT::i128) {
509 if (RetVT == MVT::f32)
510 return UINTTOFP_I128_F32;
511 else if (RetVT == MVT::f64)
512 return UINTTOFP_I128_F64;
513 else if (RetVT == MVT::f80)
514 return UINTTOFP_I128_F80;
515 else if (RetVT == MVT::ppcf128)
516 return UINTTOFP_I128_PPCF128;
518 return UNKNOWN_LIBCALL;
521 /// InitCmpLibcallCCs - Set default comparison libcall CC.
523 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
525 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
526 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
527 CCs[RTLIB::UNE_F32] = ISD::SETNE;
528 CCs[RTLIB::UNE_F64] = ISD::SETNE;
529 CCs[RTLIB::OGE_F32] = ISD::SETGE;
530 CCs[RTLIB::OGE_F64] = ISD::SETGE;
531 CCs[RTLIB::OLT_F32] = ISD::SETLT;
532 CCs[RTLIB::OLT_F64] = ISD::SETLT;
533 CCs[RTLIB::OLE_F32] = ISD::SETLE;
534 CCs[RTLIB::OLE_F64] = ISD::SETLE;
535 CCs[RTLIB::OGT_F32] = ISD::SETGT;
536 CCs[RTLIB::OGT_F64] = ISD::SETGT;
537 CCs[RTLIB::UO_F32] = ISD::SETNE;
538 CCs[RTLIB::UO_F64] = ISD::SETNE;
539 CCs[RTLIB::O_F32] = ISD::SETEQ;
540 CCs[RTLIB::O_F64] = ISD::SETEQ;
543 /// NOTE: The constructor takes ownership of TLOF.
544 TargetLowering::TargetLowering(const TargetMachine &tm,
545 const TargetLoweringObjectFile *tlof)
546 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
547 mayPromoteElements(AllowPromoteIntElem) {
548 // All operations default to being supported.
549 memset(OpActions, 0, sizeof(OpActions));
550 memset(LoadExtActions, 0, sizeof(LoadExtActions));
551 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
552 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
553 memset(CondCodeActions, 0, sizeof(CondCodeActions));
555 // Set default actions for various operations.
556 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
557 // Default all indexed load / store to expand.
558 for (unsigned IM = (unsigned)ISD::PRE_INC;
559 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
560 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
561 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
564 // These operations default to expand.
565 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
569 // Most targets ignore the @llvm.prefetch intrinsic.
570 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
572 // ConstantFP nodes default to expand. Targets can either change this to
573 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
574 // to optimize expansions for certain constants.
575 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
576 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
577 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
578 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
580 // These library functions default to expand.
581 setOperationAction(ISD::FLOG , MVT::f16, Expand);
582 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
583 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
584 setOperationAction(ISD::FEXP , MVT::f16, Expand);
585 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
586 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
587 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
588 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
589 setOperationAction(ISD::FRINT, MVT::f16, Expand);
590 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
591 setOperationAction(ISD::FLOG , MVT::f32, Expand);
592 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
593 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
594 setOperationAction(ISD::FEXP , MVT::f32, Expand);
595 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
596 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
597 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
598 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
599 setOperationAction(ISD::FRINT, MVT::f32, Expand);
600 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
601 setOperationAction(ISD::FLOG , MVT::f64, Expand);
602 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
603 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
604 setOperationAction(ISD::FEXP , MVT::f64, Expand);
605 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
606 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
607 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
608 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
609 setOperationAction(ISD::FRINT, MVT::f64, Expand);
610 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
612 // Default ISD::TRAP to expand (which turns it into abort).
613 setOperationAction(ISD::TRAP, MVT::Other, Expand);
615 IsLittleEndian = TD->isLittleEndian();
616 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
617 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
618 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
619 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
620 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
621 = maxStoresPerMemmoveOptSize = 4;
622 benefitFromCodePlacementOpt = false;
623 UseUnderscoreSetJmp = false;
624 UseUnderscoreLongJmp = false;
625 SelectIsExpensive = false;
626 IntDivIsCheap = false;
627 Pow2DivIsCheap = false;
628 JumpIsExpensive = false;
629 StackPointerRegisterToSaveRestore = 0;
630 ExceptionPointerRegister = 0;
631 ExceptionSelectorRegister = 0;
632 BooleanContents = UndefinedBooleanContent;
633 BooleanVectorContents = UndefinedBooleanContent;
634 SchedPreferenceInfo = Sched::ILP;
636 JumpBufAlignment = 0;
637 MinFunctionAlignment = 0;
638 PrefFunctionAlignment = 0;
639 PrefLoopAlignment = 0;
640 MinStackArgumentAlignment = 1;
641 ShouldFoldAtomicFences = false;
642 InsertFencesForAtomic = false;
644 InitLibcallNames(LibcallRoutineNames);
645 InitCmpLibcallCCs(CmpLibcallCCs);
646 InitLibcallCallingConvs(LibcallCallingConvs);
649 TargetLowering::~TargetLowering() {
653 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
654 return MVT::getIntegerVT(8*TD->getPointerSize());
657 /// canOpTrap - Returns true if the operation can trap for the value type.
658 /// VT must be a legal type.
659 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
660 assert(isTypeLegal(VT));
675 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
676 unsigned &NumIntermediates,
678 TargetLowering *TLI) {
679 // Figure out the right, legal destination reg to copy into.
680 unsigned NumElts = VT.getVectorNumElements();
681 MVT EltTy = VT.getVectorElementType();
683 unsigned NumVectorRegs = 1;
685 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
686 // could break down into LHS/RHS like LegalizeDAG does.
687 if (!isPowerOf2_32(NumElts)) {
688 NumVectorRegs = NumElts;
692 // Divide the input until we get to a supported size. This will always
693 // end with a scalar if the target doesn't support vectors.
694 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
699 NumIntermediates = NumVectorRegs;
701 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
702 if (!TLI->isTypeLegal(NewVT))
704 IntermediateVT = NewVT;
706 unsigned NewVTSize = NewVT.getSizeInBits();
708 // Convert sizes such as i33 to i64.
709 if (!isPowerOf2_32(NewVTSize))
710 NewVTSize = NextPowerOf2(NewVTSize);
712 EVT DestVT = TLI->getRegisterType(NewVT);
714 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
715 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
717 // Otherwise, promotion or legal types use the same number of registers as
718 // the vector decimated to the appropriate level.
719 return NumVectorRegs;
722 /// isLegalRC - Return true if the value types that can be represented by the
723 /// specified register class are all legal.
724 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
725 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
733 /// hasLegalSuperRegRegClasses - Return true if the specified register class
734 /// has one or more super-reg register classes that are legal.
736 TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
737 if (*RC->superregclasses_begin() == 0)
739 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
740 E = RC->superregclasses_end(); I != E; ++I) {
741 const TargetRegisterClass *RRC = *I;
748 /// findRepresentativeClass - Return the largest legal super-reg register class
749 /// of the register class for the specified type and its associated "cost".
750 std::pair<const TargetRegisterClass*, uint8_t>
751 TargetLowering::findRepresentativeClass(EVT VT) const {
752 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
754 return std::make_pair(RC, 0);
755 const TargetRegisterClass *BestRC = RC;
756 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
757 E = RC->superregclasses_end(); I != E; ++I) {
758 const TargetRegisterClass *RRC = *I;
759 if (RRC->isASubClass() || !isLegalRC(RRC))
761 if (!hasLegalSuperRegRegClasses(RRC))
762 return std::make_pair(RRC, 1);
765 return std::make_pair(BestRC, 1);
769 /// computeRegisterProperties - Once all of the register classes are added,
770 /// this allows us to compute derived properties we expose.
771 void TargetLowering::computeRegisterProperties() {
772 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
773 "Too many value types for ValueTypeActions to hold!");
775 // Everything defaults to needing one register.
776 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
777 NumRegistersForVT[i] = 1;
778 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
780 // ...except isVoid, which doesn't need any registers.
781 NumRegistersForVT[MVT::isVoid] = 0;
783 // Find the largest integer register class.
784 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
785 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
786 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
788 // Every integer value type larger than this largest register takes twice as
789 // many registers to represent as the previous ValueType.
790 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
791 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
792 if (!ExpandedVT.isInteger())
794 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
795 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
796 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
797 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
800 // Inspect all of the ValueType's smaller than the largest integer
801 // register to see which ones need promotion.
802 unsigned LegalIntReg = LargestIntReg;
803 for (unsigned IntReg = LargestIntReg - 1;
804 IntReg >= (unsigned)MVT::i1; --IntReg) {
805 EVT IVT = (MVT::SimpleValueType)IntReg;
806 if (isTypeLegal(IVT)) {
807 LegalIntReg = IntReg;
809 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
810 (MVT::SimpleValueType)LegalIntReg;
811 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
815 // ppcf128 type is really two f64's.
816 if (!isTypeLegal(MVT::ppcf128)) {
817 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
818 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
819 TransformToType[MVT::ppcf128] = MVT::f64;
820 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
823 // Decide how to handle f64. If the target does not have native f64 support,
824 // expand it to i64 and we will be generating soft float library calls.
825 if (!isTypeLegal(MVT::f64)) {
826 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
827 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
828 TransformToType[MVT::f64] = MVT::i64;
829 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
832 // Decide how to handle f32. If the target does not have native support for
833 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
834 if (!isTypeLegal(MVT::f32)) {
835 if (isTypeLegal(MVT::f64)) {
836 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
837 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
838 TransformToType[MVT::f32] = MVT::f64;
839 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
841 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
842 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
843 TransformToType[MVT::f32] = MVT::i32;
844 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
848 // Loop over all of the vector value types to see which need transformations.
849 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
850 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
851 MVT VT = (MVT::SimpleValueType)i;
852 if (isTypeLegal(VT)) continue;
854 // Determine if there is a legal wider type. If so, we should promote to
855 // that wider vector type.
856 EVT EltVT = VT.getVectorElementType();
857 unsigned NElts = VT.getVectorNumElements();
859 bool IsLegalWiderType = false;
860 // If we allow the promotion of vector elements using a flag,
861 // then return TypePromoteInteger on vector elements.
862 // First try to promote the elements of integer vectors. If no legal
863 // promotion was found, fallback to the widen-vector method.
864 if (mayPromoteElements)
865 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
866 EVT SVT = (MVT::SimpleValueType)nVT;
867 // Promote vectors of integers to vectors with the same number
868 // of elements, with a wider element type.
869 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
870 && SVT.getVectorNumElements() == NElts &&
871 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
872 TransformToType[i] = SVT;
873 RegisterTypeForVT[i] = SVT;
874 NumRegistersForVT[i] = 1;
875 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
876 IsLegalWiderType = true;
881 if (IsLegalWiderType) continue;
883 // Try to widen the vector.
884 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
885 EVT SVT = (MVT::SimpleValueType)nVT;
886 if (SVT.getVectorElementType() == EltVT &&
887 SVT.getVectorNumElements() > NElts &&
889 TransformToType[i] = SVT;
890 RegisterTypeForVT[i] = SVT;
891 NumRegistersForVT[i] = 1;
892 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
893 IsLegalWiderType = true;
897 if (IsLegalWiderType) continue;
902 unsigned NumIntermediates;
903 NumRegistersForVT[i] =
904 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
906 RegisterTypeForVT[i] = RegisterVT;
908 EVT NVT = VT.getPow2VectorType();
910 // Type is already a power of 2. The default action is to split.
911 TransformToType[i] = MVT::Other;
912 unsigned NumElts = VT.getVectorNumElements();
913 ValueTypeActions.setTypeAction(VT,
914 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
916 TransformToType[i] = NVT;
917 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
921 // Determine the 'representative' register class for each value type.
922 // An representative register class is the largest (meaning one which is
923 // not a sub-register class / subreg register class) legal register class for
924 // a group of value types. For example, on i386, i8, i16, and i32
925 // representative would be GR32; while on x86_64 it's GR64.
926 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
927 const TargetRegisterClass* RRC;
929 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
930 RepRegClassForVT[i] = RRC;
931 RepRegClassCostForVT[i] = Cost;
935 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
940 EVT TargetLowering::getSetCCResultType(EVT VT) const {
941 assert(!VT.isVector() && "No default SetCC type for vectors!");
942 return PointerTy.SimpleTy;
945 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
946 return MVT::i32; // return the default value
949 /// getVectorTypeBreakdown - Vector types are broken down into some number of
950 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
951 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
952 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
954 /// This method returns the number of registers needed, and the VT for each
955 /// register. It also returns the VT and quantity of the intermediate values
956 /// before they are promoted/expanded.
958 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
960 unsigned &NumIntermediates,
961 EVT &RegisterVT) const {
962 unsigned NumElts = VT.getVectorNumElements();
964 // If there is a wider vector type with the same element type as this one,
965 // we should widen to that legal vector type. This handles things like
966 // <2 x float> -> <4 x float>.
967 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
968 RegisterVT = getTypeToTransformTo(Context, VT);
969 if (isTypeLegal(RegisterVT)) {
970 IntermediateVT = RegisterVT;
971 NumIntermediates = 1;
976 // Figure out the right, legal destination reg to copy into.
977 EVT EltTy = VT.getVectorElementType();
979 unsigned NumVectorRegs = 1;
981 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
982 // could break down into LHS/RHS like LegalizeDAG does.
983 if (!isPowerOf2_32(NumElts)) {
984 NumVectorRegs = NumElts;
988 // Divide the input until we get to a supported size. This will always
989 // end with a scalar if the target doesn't support vectors.
990 while (NumElts > 1 && !isTypeLegal(
991 EVT::getVectorVT(Context, EltTy, NumElts))) {
996 NumIntermediates = NumVectorRegs;
998 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
999 if (!isTypeLegal(NewVT))
1001 IntermediateVT = NewVT;
1003 EVT DestVT = getRegisterType(Context, NewVT);
1004 RegisterVT = DestVT;
1005 unsigned NewVTSize = NewVT.getSizeInBits();
1007 // Convert sizes such as i33 to i64.
1008 if (!isPowerOf2_32(NewVTSize))
1009 NewVTSize = NextPowerOf2(NewVTSize);
1011 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1012 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1014 // Otherwise, promotion or legal types use the same number of registers as
1015 // the vector decimated to the appropriate level.
1016 return NumVectorRegs;
1019 /// Get the EVTs and ArgFlags collections that represent the legalized return
1020 /// type of the given function. This does not require a DAG or a return value,
1021 /// and is suitable for use before any DAGs for the function are constructed.
1022 /// TODO: Move this out of TargetLowering.cpp.
1023 void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
1024 SmallVectorImpl<ISD::OutputArg> &Outs,
1025 const TargetLowering &TLI,
1026 SmallVectorImpl<uint64_t> *Offsets) {
1027 SmallVector<EVT, 4> ValueVTs;
1028 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1029 unsigned NumValues = ValueVTs.size();
1030 if (NumValues == 0) return;
1031 unsigned Offset = 0;
1033 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1034 EVT VT = ValueVTs[j];
1035 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1037 if (attr & Attribute::SExt)
1038 ExtendKind = ISD::SIGN_EXTEND;
1039 else if (attr & Attribute::ZExt)
1040 ExtendKind = ISD::ZERO_EXTEND;
1042 // FIXME: C calling convention requires the return type to be promoted to
1043 // at least 32-bit. But this is not necessary for non-C calling
1044 // conventions. The frontend should mark functions whose return values
1045 // require promoting with signext or zeroext attributes.
1046 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1047 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1048 if (VT.bitsLT(MinVT))
1052 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1053 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1054 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1055 PartVT.getTypeForEVT(ReturnType->getContext()));
1057 // 'inreg' on function refers to return value
1058 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1059 if (attr & Attribute::InReg)
1062 // Propagate extension type if any
1063 if (attr & Attribute::SExt)
1065 else if (attr & Attribute::ZExt)
1068 for (unsigned i = 0; i < NumParts; ++i) {
1069 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1071 Offsets->push_back(Offset);
1078 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1079 /// function arguments in the caller parameter area. This is the actual
1080 /// alignment, not its logarithm.
1081 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1082 return TD->getCallFrameTypeAlignment(Ty);
1085 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1086 /// current function. The returned value is a member of the
1087 /// MachineJumpTableInfo::JTEntryKind enum.
1088 unsigned TargetLowering::getJumpTableEncoding() const {
1089 // In non-pic modes, just use the address of a block.
1090 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1091 return MachineJumpTableInfo::EK_BlockAddress;
1093 // In PIC mode, if the target supports a GPRel32 directive, use it.
1094 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1095 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1097 // Otherwise, use a label difference.
1098 return MachineJumpTableInfo::EK_LabelDifference32;
1101 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1102 SelectionDAG &DAG) const {
1103 // If our PIC model is GP relative, use the global offset table as the base.
1104 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
1105 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1109 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1110 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1113 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1114 unsigned JTI,MCContext &Ctx) const{
1115 // The normal PIC reloc base is the label at the start of the jump table.
1116 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1120 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1121 // Assume that everything is safe in static mode.
1122 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1125 // In dynamic-no-pic mode, assume that known defined values are safe.
1126 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1128 !GA->getGlobal()->isDeclaration() &&
1129 !GA->getGlobal()->isWeakForLinker())
1132 // Otherwise assume nothing is safe.
1136 //===----------------------------------------------------------------------===//
1137 // Optimization Methods
1138 //===----------------------------------------------------------------------===//
1140 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1141 /// specified instruction is a constant integer. If so, check to see if there
1142 /// are any bits set in the constant that are not demanded. If so, shrink the
1143 /// constant and return true.
1144 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1145 const APInt &Demanded) {
1146 DebugLoc dl = Op.getDebugLoc();
1148 // FIXME: ISD::SELECT, ISD::SELECT_CC
1149 switch (Op.getOpcode()) {
1154 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1155 if (!C) return false;
1157 if (Op.getOpcode() == ISD::XOR &&
1158 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1161 // if we can expand it to have all bits set, do it
1162 if (C->getAPIntValue().intersects(~Demanded)) {
1163 EVT VT = Op.getValueType();
1164 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1165 DAG.getConstant(Demanded &
1168 return CombineTo(Op, New);
1178 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1179 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1180 /// cast, but it could be generalized for targets with other types of
1181 /// implicit widening casts.
1183 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1185 const APInt &Demanded,
1187 assert(Op.getNumOperands() == 2 &&
1188 "ShrinkDemandedOp only supports binary operators!");
1189 assert(Op.getNode()->getNumValues() == 1 &&
1190 "ShrinkDemandedOp only supports nodes with one result!");
1192 // Don't do this if the node has another user, which may require the
1194 if (!Op.getNode()->hasOneUse())
1197 // Search for the smallest integer type with free casts to and from
1198 // Op's type. For expedience, just check power-of-2 integer types.
1199 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1200 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1201 if (!isPowerOf2_32(SmallVTBits))
1202 SmallVTBits = NextPowerOf2(SmallVTBits);
1203 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1204 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1205 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1206 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1207 // We found a type with free casts.
1208 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1209 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1210 Op.getNode()->getOperand(0)),
1211 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1212 Op.getNode()->getOperand(1)));
1213 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1214 return CombineTo(Op, Z);
1220 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1221 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1222 /// use this information to simplify Op, create a new simplified DAG node and
1223 /// return true, returning the original and new nodes in Old and New. Otherwise,
1224 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
1225 /// the expression (used to simplify the caller). The KnownZero/One bits may
1226 /// only be accurate for those bits in the DemandedMask.
1227 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1228 const APInt &DemandedMask,
1231 TargetLoweringOpt &TLO,
1232 unsigned Depth) const {
1233 unsigned BitWidth = DemandedMask.getBitWidth();
1234 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1235 "Mask size mismatches value type size!");
1236 APInt NewMask = DemandedMask;
1237 DebugLoc dl = Op.getDebugLoc();
1239 // Don't know anything.
1240 KnownZero = KnownOne = APInt(BitWidth, 0);
1242 // Other users may use these bits.
1243 if (!Op.getNode()->hasOneUse()) {
1245 // If not at the root, Just compute the KnownZero/KnownOne bits to
1246 // simplify things downstream.
1247 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1250 // If this is the root being simplified, allow it to have multiple uses,
1251 // just set the NewMask to all bits.
1252 NewMask = APInt::getAllOnesValue(BitWidth);
1253 } else if (DemandedMask == 0) {
1254 // Not demanding any bits from Op.
1255 if (Op.getOpcode() != ISD::UNDEF)
1256 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1258 } else if (Depth == 6) { // Limit search depth.
1262 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1263 switch (Op.getOpcode()) {
1265 // We know all of the bits for a constant!
1266 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1267 KnownZero = ~KnownOne;
1268 return false; // Don't fall through, will infinitely loop.
1270 // If the RHS is a constant, check to see if the LHS would be zero without
1271 // using the bits from the RHS. Below, we use knowledge about the RHS to
1272 // simplify the LHS, here we're using information from the LHS to simplify
1274 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1275 APInt LHSZero, LHSOne;
1276 // Do not increment Depth here; that can cause an infinite loop.
1277 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1278 // If the LHS already has zeros where RHSC does, this and is dead.
1279 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1280 return TLO.CombineTo(Op, Op.getOperand(0));
1281 // If any of the set bits in the RHS are known zero on the LHS, shrink
1283 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1287 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1288 KnownOne, TLO, Depth+1))
1290 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1291 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1292 KnownZero2, KnownOne2, TLO, Depth+1))
1294 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1296 // If all of the demanded bits are known one on one side, return the other.
1297 // These bits cannot contribute to the result of the 'and'.
1298 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1299 return TLO.CombineTo(Op, Op.getOperand(0));
1300 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1301 return TLO.CombineTo(Op, Op.getOperand(1));
1302 // If all of the demanded bits in the inputs are known zeros, return zero.
1303 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1304 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1305 // If the RHS is a constant, see if we can simplify it.
1306 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1308 // If the operation can be done in a smaller type, do so.
1309 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1312 // Output known-1 bits are only known if set in both the LHS & RHS.
1313 KnownOne &= KnownOne2;
1314 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1315 KnownZero |= KnownZero2;
1318 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1319 KnownOne, TLO, Depth+1))
1321 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1322 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1323 KnownZero2, KnownOne2, TLO, Depth+1))
1325 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1327 // If all of the demanded bits are known zero on one side, return the other.
1328 // These bits cannot contribute to the result of the 'or'.
1329 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1330 return TLO.CombineTo(Op, Op.getOperand(0));
1331 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1332 return TLO.CombineTo(Op, Op.getOperand(1));
1333 // If all of the potentially set bits on one side are known to be set on
1334 // the other side, just use the 'other' side.
1335 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1336 return TLO.CombineTo(Op, Op.getOperand(0));
1337 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1338 return TLO.CombineTo(Op, Op.getOperand(1));
1339 // If the RHS is a constant, see if we can simplify it.
1340 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1342 // If the operation can be done in a smaller type, do so.
1343 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1346 // Output known-0 bits are only known if clear in both the LHS & RHS.
1347 KnownZero &= KnownZero2;
1348 // Output known-1 are known to be set if set in either the LHS | RHS.
1349 KnownOne |= KnownOne2;
1352 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1353 KnownOne, TLO, Depth+1))
1355 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1356 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1357 KnownOne2, TLO, Depth+1))
1359 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1361 // If all of the demanded bits are known zero on one side, return the other.
1362 // These bits cannot contribute to the result of the 'xor'.
1363 if ((KnownZero & NewMask) == NewMask)
1364 return TLO.CombineTo(Op, Op.getOperand(0));
1365 if ((KnownZero2 & NewMask) == NewMask)
1366 return TLO.CombineTo(Op, Op.getOperand(1));
1367 // If the operation can be done in a smaller type, do so.
1368 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1371 // If all of the unknown bits are known to be zero on one side or the other
1372 // (but not both) turn this into an *inclusive* or.
1373 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1374 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1375 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1379 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1380 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1381 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1382 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1384 // If all of the demanded bits on one side are known, and all of the set
1385 // bits on that side are also known to be set on the other side, turn this
1386 // into an AND, as we know the bits will be cleared.
1387 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1388 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1389 if ((KnownOne & KnownOne2) == KnownOne) {
1390 EVT VT = Op.getValueType();
1391 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1392 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1393 Op.getOperand(0), ANDC));
1397 // If the RHS is a constant, see if we can simplify it.
1398 // for XOR, we prefer to force bits to 1 if they will make a -1.
1399 // if we can't force bits, try to shrink constant
1400 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1401 APInt Expanded = C->getAPIntValue() | (~NewMask);
1402 // if we can expand it to have all bits set, do it
1403 if (Expanded.isAllOnesValue()) {
1404 if (Expanded != C->getAPIntValue()) {
1405 EVT VT = Op.getValueType();
1406 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1407 TLO.DAG.getConstant(Expanded, VT));
1408 return TLO.CombineTo(Op, New);
1410 // if it already has all the bits set, nothing to change
1411 // but don't shrink either!
1412 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1417 KnownZero = KnownZeroOut;
1418 KnownOne = KnownOneOut;
1421 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1422 KnownOne, TLO, Depth+1))
1424 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1425 KnownOne2, TLO, Depth+1))
1427 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1428 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1430 // If the operands are constants, see if we can simplify them.
1431 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1434 // Only known if known in both the LHS and RHS.
1435 KnownOne &= KnownOne2;
1436 KnownZero &= KnownZero2;
1438 case ISD::SELECT_CC:
1439 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1440 KnownOne, TLO, Depth+1))
1442 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1443 KnownOne2, TLO, Depth+1))
1445 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1446 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1448 // If the operands are constants, see if we can simplify them.
1449 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1452 // Only known if known in both the LHS and RHS.
1453 KnownOne &= KnownOne2;
1454 KnownZero &= KnownZero2;
1457 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1458 unsigned ShAmt = SA->getZExtValue();
1459 SDValue InOp = Op.getOperand(0);
1461 // If the shift count is an invalid immediate, don't do anything.
1462 if (ShAmt >= BitWidth)
1465 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1466 // single shift. We can do this if the bottom bits (which are shifted
1467 // out) are never demanded.
1468 if (InOp.getOpcode() == ISD::SRL &&
1469 isa<ConstantSDNode>(InOp.getOperand(1))) {
1470 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1471 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1472 unsigned Opc = ISD::SHL;
1473 int Diff = ShAmt-C1;
1480 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1481 EVT VT = Op.getValueType();
1482 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1483 InOp.getOperand(0), NewSA));
1487 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1488 KnownZero, KnownOne, TLO, Depth+1))
1491 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1492 // are not demanded. This will likely allow the anyext to be folded away.
1493 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1494 SDValue InnerOp = InOp.getNode()->getOperand(0);
1495 EVT InnerVT = InnerOp.getValueType();
1496 unsigned InnerBits = InnerVT.getSizeInBits();
1497 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1498 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1499 EVT ShTy = getShiftAmountTy(InnerVT);
1500 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1503 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1504 TLO.DAG.getConstant(ShAmt, ShTy));
1507 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1512 KnownZero <<= SA->getZExtValue();
1513 KnownOne <<= SA->getZExtValue();
1514 // low bits known zero.
1515 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1519 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1520 EVT VT = Op.getValueType();
1521 unsigned ShAmt = SA->getZExtValue();
1522 unsigned VTSize = VT.getSizeInBits();
1523 SDValue InOp = Op.getOperand(0);
1525 // If the shift count is an invalid immediate, don't do anything.
1526 if (ShAmt >= BitWidth)
1529 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1530 // single shift. We can do this if the top bits (which are shifted out)
1531 // are never demanded.
1532 if (InOp.getOpcode() == ISD::SHL &&
1533 isa<ConstantSDNode>(InOp.getOperand(1))) {
1534 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1535 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1536 unsigned Opc = ISD::SRL;
1537 int Diff = ShAmt-C1;
1544 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1545 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1546 InOp.getOperand(0), NewSA));
1550 // Compute the new bits that are at the top now.
1551 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1552 KnownZero, KnownOne, TLO, Depth+1))
1554 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1555 KnownZero = KnownZero.lshr(ShAmt);
1556 KnownOne = KnownOne.lshr(ShAmt);
1558 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1559 KnownZero |= HighBits; // High bits known zero.
1563 // If this is an arithmetic shift right and only the low-bit is set, we can
1564 // always convert this into a logical shr, even if the shift amount is
1565 // variable. The low bit of the shift cannot be an input sign bit unless
1566 // the shift amount is >= the size of the datatype, which is undefined.
1568 return TLO.CombineTo(Op,
1569 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1570 Op.getOperand(0), Op.getOperand(1)));
1572 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1573 EVT VT = Op.getValueType();
1574 unsigned ShAmt = SA->getZExtValue();
1576 // If the shift count is an invalid immediate, don't do anything.
1577 if (ShAmt >= BitWidth)
1580 APInt InDemandedMask = (NewMask << ShAmt);
1582 // If any of the demanded bits are produced by the sign extension, we also
1583 // demand the input sign bit.
1584 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1585 if (HighBits.intersects(NewMask))
1586 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1588 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1589 KnownZero, KnownOne, TLO, Depth+1))
1591 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1592 KnownZero = KnownZero.lshr(ShAmt);
1593 KnownOne = KnownOne.lshr(ShAmt);
1595 // Handle the sign bit, adjusted to where it is now in the mask.
1596 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1598 // If the input sign bit is known to be zero, or if none of the top bits
1599 // are demanded, turn this into an unsigned shift right.
1600 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1601 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1604 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1605 KnownOne |= HighBits;
1609 case ISD::SIGN_EXTEND_INREG: {
1610 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1612 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1613 // If we only care about the highest bit, don't bother shifting right.
1614 if (MsbMask == DemandedMask) {
1615 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1616 SDValue InOp = Op.getOperand(0);
1618 // Compute the correct shift amount type, which must be getShiftAmountTy
1619 // for scalar types after legalization.
1620 EVT ShiftAmtTy = Op.getValueType();
1621 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1622 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1624 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1625 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1626 Op.getValueType(), InOp, ShiftAmt));
1629 // Sign extension. Compute the demanded bits in the result that are not
1630 // present in the input.
1632 APInt::getHighBitsSet(BitWidth,
1633 BitWidth - ExVT.getScalarType().getSizeInBits());
1635 // If none of the extended bits are demanded, eliminate the sextinreg.
1636 if ((NewBits & NewMask) == 0)
1637 return TLO.CombineTo(Op, Op.getOperand(0));
1640 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1641 APInt InputDemandedBits =
1642 APInt::getLowBitsSet(BitWidth,
1643 ExVT.getScalarType().getSizeInBits()) &
1646 // Since the sign extended bits are demanded, we know that the sign
1648 InputDemandedBits |= InSignBit;
1650 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1651 KnownZero, KnownOne, TLO, Depth+1))
1653 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1655 // If the sign bit of the input is known set or clear, then we know the
1656 // top bits of the result.
1658 // If the input sign bit is known zero, convert this into a zero extension.
1659 if (KnownZero.intersects(InSignBit))
1660 return TLO.CombineTo(Op,
1661 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1663 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1664 KnownOne |= NewBits;
1665 KnownZero &= ~NewBits;
1666 } else { // Input sign bit unknown
1667 KnownZero &= ~NewBits;
1668 KnownOne &= ~NewBits;
1672 case ISD::ZERO_EXTEND: {
1673 unsigned OperandBitWidth =
1674 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1675 APInt InMask = NewMask.trunc(OperandBitWidth);
1677 // If none of the top bits are demanded, convert this into an any_extend.
1679 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1680 if (!NewBits.intersects(NewMask))
1681 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1685 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1686 KnownZero, KnownOne, TLO, Depth+1))
1688 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1689 KnownZero = KnownZero.zext(BitWidth);
1690 KnownOne = KnownOne.zext(BitWidth);
1691 KnownZero |= NewBits;
1694 case ISD::SIGN_EXTEND: {
1695 EVT InVT = Op.getOperand(0).getValueType();
1696 unsigned InBits = InVT.getScalarType().getSizeInBits();
1697 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1698 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1699 APInt NewBits = ~InMask & NewMask;
1701 // If none of the top bits are demanded, convert this into an any_extend.
1703 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1707 // Since some of the sign extended bits are demanded, we know that the sign
1709 APInt InDemandedBits = InMask & NewMask;
1710 InDemandedBits |= InSignBit;
1711 InDemandedBits = InDemandedBits.trunc(InBits);
1713 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1714 KnownOne, TLO, Depth+1))
1716 KnownZero = KnownZero.zext(BitWidth);
1717 KnownOne = KnownOne.zext(BitWidth);
1719 // If the sign bit is known zero, convert this to a zero extend.
1720 if (KnownZero.intersects(InSignBit))
1721 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1725 // If the sign bit is known one, the top bits match.
1726 if (KnownOne.intersects(InSignBit)) {
1727 KnownOne |= NewBits;
1728 assert((KnownZero & NewBits) == 0);
1729 } else { // Otherwise, top bits aren't known.
1730 assert((KnownOne & NewBits) == 0);
1731 assert((KnownZero & NewBits) == 0);
1735 case ISD::ANY_EXTEND: {
1736 unsigned OperandBitWidth =
1737 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1738 APInt InMask = NewMask.trunc(OperandBitWidth);
1739 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1740 KnownZero, KnownOne, TLO, Depth+1))
1742 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1743 KnownZero = KnownZero.zext(BitWidth);
1744 KnownOne = KnownOne.zext(BitWidth);
1747 case ISD::TRUNCATE: {
1748 // Simplify the input, using demanded bit information, and compute the known
1749 // zero/one bits live out.
1750 unsigned OperandBitWidth =
1751 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1752 APInt TruncMask = NewMask.zext(OperandBitWidth);
1753 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1754 KnownZero, KnownOne, TLO, Depth+1))
1756 KnownZero = KnownZero.trunc(BitWidth);
1757 KnownOne = KnownOne.trunc(BitWidth);
1759 // If the input is only used by this truncate, see if we can shrink it based
1760 // on the known demanded bits.
1761 if (Op.getOperand(0).getNode()->hasOneUse()) {
1762 SDValue In = Op.getOperand(0);
1763 switch (In.getOpcode()) {
1766 // Shrink SRL by a constant if none of the high bits shifted in are
1768 if (TLO.LegalTypes() &&
1769 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1770 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1773 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1776 SDValue Shift = In.getOperand(1);
1777 if (TLO.LegalTypes()) {
1778 uint64_t ShVal = ShAmt->getZExtValue();
1780 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1783 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1784 OperandBitWidth - BitWidth);
1785 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1787 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1788 // None of the shifted in bits are needed. Add a truncate of the
1789 // shift input, then shift it.
1790 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1793 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1802 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1805 case ISD::AssertZext: {
1806 // AssertZext demands all of the high bits, plus any of the low bits
1807 // demanded by its users.
1808 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1809 APInt InMask = APInt::getLowBitsSet(BitWidth,
1810 VT.getSizeInBits());
1811 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1812 KnownZero, KnownOne, TLO, Depth+1))
1814 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1816 KnownZero |= ~InMask & NewMask;
1820 // If this is an FP->Int bitcast and if the sign bit is the only
1821 // thing demanded, turn this into a FGETSIGN.
1822 if (!TLO.LegalOperations() &&
1823 !Op.getValueType().isVector() &&
1824 !Op.getOperand(0).getValueType().isVector() &&
1825 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1826 Op.getOperand(0).getValueType().isFloatingPoint()) {
1827 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1828 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1829 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1830 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1831 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1832 // place. We expect the SHL to be eliminated by other optimizations.
1833 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1834 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1835 if (!OpVTLegal && OpVTSizeInBits > 32)
1836 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1837 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1838 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1839 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1848 // Add, Sub, and Mul don't demand any bits in positions beyond that
1849 // of the highest bit demanded of them.
1850 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1851 BitWidth - NewMask.countLeadingZeros());
1852 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1853 KnownOne2, TLO, Depth+1))
1855 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1856 KnownOne2, TLO, Depth+1))
1858 // See if the operation should be performed at a smaller bit width.
1859 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1864 // Just use ComputeMaskedBits to compute output bits.
1865 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1869 // If we know the value of all of the demanded bits, return this as a
1871 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1872 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1877 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1878 /// in Mask are known to be either zero or one and return them in the
1879 /// KnownZero/KnownOne bitsets.
1880 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1883 const SelectionDAG &DAG,
1884 unsigned Depth) const {
1885 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1886 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1887 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1888 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1889 "Should use MaskedValueIsZero if you don't know whether Op"
1890 " is a target node!");
1891 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1894 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1895 /// targets that want to expose additional information about sign bits to the
1897 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1898 unsigned Depth) const {
1899 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1900 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1901 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1902 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1903 "Should use ComputeNumSignBits if you don't know whether Op"
1904 " is a target node!");
1908 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1909 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1910 /// determine which bit is set.
1912 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1913 // A left-shift of a constant one will have exactly one bit set, because
1914 // shifting the bit off the end is undefined.
1915 if (Val.getOpcode() == ISD::SHL)
1916 if (ConstantSDNode *C =
1917 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1918 if (C->getAPIntValue() == 1)
1921 // Similarly, a right-shift of a constant sign-bit will have exactly
1923 if (Val.getOpcode() == ISD::SRL)
1924 if (ConstantSDNode *C =
1925 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1926 if (C->getAPIntValue().isSignBit())
1929 // More could be done here, though the above checks are enough
1930 // to handle some common cases.
1932 // Fall back to ComputeMaskedBits to catch other known cases.
1933 EVT OpVT = Val.getValueType();
1934 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1935 APInt KnownZero, KnownOne;
1936 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1937 return (KnownZero.countPopulation() == BitWidth - 1) &&
1938 (KnownOne.countPopulation() == 1);
1941 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1942 /// and cc. If it is unable to simplify it, return a null SDValue.
1944 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1945 ISD::CondCode Cond, bool foldBooleans,
1946 DAGCombinerInfo &DCI, DebugLoc dl) const {
1947 SelectionDAG &DAG = DCI.DAG;
1949 // These setcc operations always fold.
1953 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1955 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1958 // Ensure that the constant occurs on the RHS, and fold constant
1960 if (isa<ConstantSDNode>(N0.getNode()))
1961 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1963 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1964 const APInt &C1 = N1C->getAPIntValue();
1966 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1967 // equality comparison, then we're just comparing whether X itself is
1969 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1970 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1971 N0.getOperand(1).getOpcode() == ISD::Constant) {
1973 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1974 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1975 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1976 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1977 // (srl (ctlz x), 5) == 0 -> X != 0
1978 // (srl (ctlz x), 5) != 1 -> X != 0
1981 // (srl (ctlz x), 5) != 0 -> X == 0
1982 // (srl (ctlz x), 5) == 1 -> X == 0
1985 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1986 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1992 // Look through truncs that don't change the value of a ctpop.
1993 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1994 CTPOP = N0.getOperand(0);
1996 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1997 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1998 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1999 EVT CTVT = CTPOP.getValueType();
2000 SDValue CTOp = CTPOP.getOperand(0);
2002 // (ctpop x) u< 2 -> (x & x-1) == 0
2003 // (ctpop x) u> 1 -> (x & x-1) != 0
2004 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
2005 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
2006 DAG.getConstant(1, CTVT));
2007 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2008 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
2009 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
2012 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
2015 // (zext x) == C --> x == (trunc C)
2016 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
2017 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2018 unsigned MinBits = N0.getValueSizeInBits();
2020 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2022 MinBits = N0->getOperand(0).getValueSizeInBits();
2023 PreZExt = N0->getOperand(0);
2024 } else if (N0->getOpcode() == ISD::AND) {
2025 // DAGCombine turns costly ZExts into ANDs
2026 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2027 if ((C->getAPIntValue()+1).isPowerOf2()) {
2028 MinBits = C->getAPIntValue().countTrailingOnes();
2029 PreZExt = N0->getOperand(0);
2031 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2033 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2034 MinBits = LN0->getMemoryVT().getSizeInBits();
2039 // Make sure we're not loosing bits from the constant.
2040 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2041 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2042 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2043 // Will get folded away.
2044 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2045 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2046 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2051 // If the LHS is '(and load, const)', the RHS is 0,
2052 // the test is for equality or unsigned, and all 1 bits of the const are
2053 // in the same partial word, see if we can shorten the load.
2054 if (DCI.isBeforeLegalize() &&
2055 N0.getOpcode() == ISD::AND && C1 == 0 &&
2056 N0.getNode()->hasOneUse() &&
2057 isa<LoadSDNode>(N0.getOperand(0)) &&
2058 N0.getOperand(0).getNode()->hasOneUse() &&
2059 isa<ConstantSDNode>(N0.getOperand(1))) {
2060 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2062 unsigned bestWidth = 0, bestOffset = 0;
2063 if (!Lod->isVolatile() && Lod->isUnindexed()) {
2064 unsigned origWidth = N0.getValueType().getSizeInBits();
2065 unsigned maskWidth = origWidth;
2066 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2067 // 8 bits, but have to be careful...
2068 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2069 origWidth = Lod->getMemoryVT().getSizeInBits();
2071 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2072 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2073 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2074 for (unsigned offset=0; offset<origWidth/width; offset++) {
2075 if ((newMask & Mask) == Mask) {
2076 if (!TD->isLittleEndian())
2077 bestOffset = (origWidth/width - offset - 1) * (width/8);
2079 bestOffset = (uint64_t)offset * (width/8);
2080 bestMask = Mask.lshr(offset * (width/8) * 8);
2084 newMask = newMask << width;
2089 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2090 if (newVT.isRound()) {
2091 EVT PtrType = Lod->getOperand(1).getValueType();
2092 SDValue Ptr = Lod->getBasePtr();
2093 if (bestOffset != 0)
2094 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2095 DAG.getConstant(bestOffset, PtrType));
2096 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2097 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2098 Lod->getPointerInfo().getWithOffset(bestOffset),
2099 false, false, false, NewAlign);
2100 return DAG.getSetCC(dl, VT,
2101 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2102 DAG.getConstant(bestMask.trunc(bestWidth),
2104 DAG.getConstant(0LL, newVT), Cond);
2109 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2110 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2111 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2113 // If the comparison constant has bits in the upper part, the
2114 // zero-extended value could never match.
2115 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2116 C1.getBitWidth() - InSize))) {
2120 case ISD::SETEQ: return DAG.getConstant(0, VT);
2123 case ISD::SETNE: return DAG.getConstant(1, VT);
2126 // True if the sign bit of C1 is set.
2127 return DAG.getConstant(C1.isNegative(), VT);
2130 // True if the sign bit of C1 isn't set.
2131 return DAG.getConstant(C1.isNonNegative(), VT);
2137 // Otherwise, we can perform the comparison with the low bits.
2145 EVT newVT = N0.getOperand(0).getValueType();
2146 if (DCI.isBeforeLegalizeOps() ||
2147 (isOperationLegal(ISD::SETCC, newVT) &&
2148 getCondCodeAction(Cond, newVT)==Legal))
2149 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2150 DAG.getConstant(C1.trunc(InSize), newVT),
2155 break; // todo, be more careful with signed comparisons
2157 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2158 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2159 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2160 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2161 EVT ExtDstTy = N0.getValueType();
2162 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2164 // If the constant doesn't fit into the number of bits for the source of
2165 // the sign extension, it is impossible for both sides to be equal.
2166 if (C1.getMinSignedBits() > ExtSrcTyBits)
2167 return DAG.getConstant(Cond == ISD::SETNE, VT);
2170 EVT Op0Ty = N0.getOperand(0).getValueType();
2171 if (Op0Ty == ExtSrcTy) {
2172 ZextOp = N0.getOperand(0);
2174 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2175 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2176 DAG.getConstant(Imm, Op0Ty));
2178 if (!DCI.isCalledByLegalizer())
2179 DCI.AddToWorklist(ZextOp.getNode());
2180 // Otherwise, make this a use of a zext.
2181 return DAG.getSetCC(dl, VT, ZextOp,
2182 DAG.getConstant(C1 & APInt::getLowBitsSet(
2187 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2188 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2189 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2190 if (N0.getOpcode() == ISD::SETCC &&
2191 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2192 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2194 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2195 // Invert the condition.
2196 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2197 CC = ISD::getSetCCInverse(CC,
2198 N0.getOperand(0).getValueType().isInteger());
2199 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2202 if ((N0.getOpcode() == ISD::XOR ||
2203 (N0.getOpcode() == ISD::AND &&
2204 N0.getOperand(0).getOpcode() == ISD::XOR &&
2205 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2206 isa<ConstantSDNode>(N0.getOperand(1)) &&
2207 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2208 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2209 // can only do this if the top bits are known zero.
2210 unsigned BitWidth = N0.getValueSizeInBits();
2211 if (DAG.MaskedValueIsZero(N0,
2212 APInt::getHighBitsSet(BitWidth,
2214 // Okay, get the un-inverted input value.
2216 if (N0.getOpcode() == ISD::XOR)
2217 Val = N0.getOperand(0);
2219 assert(N0.getOpcode() == ISD::AND &&
2220 N0.getOperand(0).getOpcode() == ISD::XOR);
2221 // ((X^1)&1)^1 -> X & 1
2222 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2223 N0.getOperand(0).getOperand(0),
2227 return DAG.getSetCC(dl, VT, Val, N1,
2228 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2230 } else if (N1C->getAPIntValue() == 1 &&
2232 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2234 if (Op0.getOpcode() == ISD::TRUNCATE)
2235 Op0 = Op0.getOperand(0);
2237 if ((Op0.getOpcode() == ISD::XOR) &&
2238 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2239 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2240 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2241 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2242 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2244 } else if (Op0.getOpcode() == ISD::AND &&
2245 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2246 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2247 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2248 if (Op0.getValueType().bitsGT(VT))
2249 Op0 = DAG.getNode(ISD::AND, dl, VT,
2250 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2251 DAG.getConstant(1, VT));
2252 else if (Op0.getValueType().bitsLT(VT))
2253 Op0 = DAG.getNode(ISD::AND, dl, VT,
2254 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2255 DAG.getConstant(1, VT));
2257 return DAG.getSetCC(dl, VT, Op0,
2258 DAG.getConstant(0, Op0.getValueType()),
2259 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2264 APInt MinVal, MaxVal;
2265 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2266 if (ISD::isSignedIntSetCC(Cond)) {
2267 MinVal = APInt::getSignedMinValue(OperandBitSize);
2268 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2270 MinVal = APInt::getMinValue(OperandBitSize);
2271 MaxVal = APInt::getMaxValue(OperandBitSize);
2274 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2275 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2276 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2277 // X >= C0 --> X > (C0-1)
2278 return DAG.getSetCC(dl, VT, N0,
2279 DAG.getConstant(C1-1, N1.getValueType()),
2280 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2283 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2284 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2285 // X <= C0 --> X < (C0+1)
2286 return DAG.getSetCC(dl, VT, N0,
2287 DAG.getConstant(C1+1, N1.getValueType()),
2288 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2291 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2292 return DAG.getConstant(0, VT); // X < MIN --> false
2293 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2294 return DAG.getConstant(1, VT); // X >= MIN --> true
2295 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2296 return DAG.getConstant(0, VT); // X > MAX --> false
2297 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2298 return DAG.getConstant(1, VT); // X <= MAX --> true
2300 // Canonicalize setgt X, Min --> setne X, Min
2301 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2302 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2303 // Canonicalize setlt X, Max --> setne X, Max
2304 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2305 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2307 // If we have setult X, 1, turn it into seteq X, 0
2308 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2309 return DAG.getSetCC(dl, VT, N0,
2310 DAG.getConstant(MinVal, N0.getValueType()),
2312 // If we have setugt X, Max-1, turn it into seteq X, Max
2313 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2314 return DAG.getSetCC(dl, VT, N0,
2315 DAG.getConstant(MaxVal, N0.getValueType()),
2318 // If we have "setcc X, C0", check to see if we can shrink the immediate
2321 // SETUGT X, SINTMAX -> SETLT X, 0
2322 if (Cond == ISD::SETUGT &&
2323 C1 == APInt::getSignedMaxValue(OperandBitSize))
2324 return DAG.getSetCC(dl, VT, N0,
2325 DAG.getConstant(0, N1.getValueType()),
2328 // SETULT X, SINTMIN -> SETGT X, -1
2329 if (Cond == ISD::SETULT &&
2330 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2331 SDValue ConstMinusOne =
2332 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2334 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2337 // Fold bit comparisons when we can.
2338 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2339 (VT == N0.getValueType() ||
2340 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2341 N0.getOpcode() == ISD::AND)
2342 if (ConstantSDNode *AndRHS =
2343 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2344 EVT ShiftTy = DCI.isBeforeLegalize() ?
2345 getPointerTy() : getShiftAmountTy(N0.getValueType());
2346 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2347 // Perform the xform if the AND RHS is a single bit.
2348 if (AndRHS->getAPIntValue().isPowerOf2()) {
2349 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2350 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2351 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2353 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2354 // (X & 8) == 8 --> (X & 8) >> 3
2355 // Perform the xform if C1 is a single bit.
2356 if (C1.isPowerOf2()) {
2357 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2358 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2359 DAG.getConstant(C1.logBase2(), ShiftTy)));
2365 if (isa<ConstantFPSDNode>(N0.getNode())) {
2366 // Constant fold or commute setcc.
2367 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2368 if (O.getNode()) return O;
2369 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2370 // If the RHS of an FP comparison is a constant, simplify it away in
2372 if (CFP->getValueAPF().isNaN()) {
2373 // If an operand is known to be a nan, we can fold it.
2374 switch (ISD::getUnorderedFlavor(Cond)) {
2375 default: llvm_unreachable("Unknown flavor!");
2376 case 0: // Known false.
2377 return DAG.getConstant(0, VT);
2378 case 1: // Known true.
2379 return DAG.getConstant(1, VT);
2380 case 2: // Undefined.
2381 return DAG.getUNDEF(VT);
2385 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2386 // constant if knowing that the operand is non-nan is enough. We prefer to
2387 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2389 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2390 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2392 // If the condition is not legal, see if we can find an equivalent one
2394 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2395 // If the comparison was an awkward floating-point == or != and one of
2396 // the comparison operands is infinity or negative infinity, convert the
2397 // condition to a less-awkward <= or >=.
2398 if (CFP->getValueAPF().isInfinity()) {
2399 if (CFP->getValueAPF().isNegative()) {
2400 if (Cond == ISD::SETOEQ &&
2401 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2402 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2403 if (Cond == ISD::SETUEQ &&
2404 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2405 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2406 if (Cond == ISD::SETUNE &&
2407 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2408 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2409 if (Cond == ISD::SETONE &&
2410 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2411 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2413 if (Cond == ISD::SETOEQ &&
2414 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2415 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2416 if (Cond == ISD::SETUEQ &&
2417 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2418 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2419 if (Cond == ISD::SETUNE &&
2420 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2421 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2422 if (Cond == ISD::SETONE &&
2423 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2424 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2431 // We can always fold X == X for integer setcc's.
2432 if (N0.getValueType().isInteger()) {
2433 switch (getBooleanContents(N0.getValueType().isVector())) {
2434 case UndefinedBooleanContent:
2435 case ZeroOrOneBooleanContent:
2436 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2437 case ZeroOrNegativeOneBooleanContent:
2438 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
2441 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2442 if (UOF == 2) // FP operators that are undefined on NaNs.
2443 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2444 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2445 return DAG.getConstant(UOF, VT);
2446 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2447 // if it is not already.
2448 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2449 if (NewCond != Cond)
2450 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2453 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2454 N0.getValueType().isInteger()) {
2455 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2456 N0.getOpcode() == ISD::XOR) {
2457 // Simplify (X+Y) == (X+Z) --> Y == Z
2458 if (N0.getOpcode() == N1.getOpcode()) {
2459 if (N0.getOperand(0) == N1.getOperand(0))
2460 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2461 if (N0.getOperand(1) == N1.getOperand(1))
2462 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2463 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2464 // If X op Y == Y op X, try other combinations.
2465 if (N0.getOperand(0) == N1.getOperand(1))
2466 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2468 if (N0.getOperand(1) == N1.getOperand(0))
2469 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2474 // If RHS is a legal immediate value for a compare instruction, we need
2475 // to be careful about increasing register pressure needlessly.
2476 bool LegalRHSImm = false;
2478 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2479 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2480 // Turn (X+C1) == C2 --> X == C2-C1
2481 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2482 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2483 DAG.getConstant(RHSC->getAPIntValue()-
2484 LHSR->getAPIntValue(),
2485 N0.getValueType()), Cond);
2488 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2489 if (N0.getOpcode() == ISD::XOR)
2490 // If we know that all of the inverted bits are zero, don't bother
2491 // performing the inversion.
2492 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2494 DAG.getSetCC(dl, VT, N0.getOperand(0),
2495 DAG.getConstant(LHSR->getAPIntValue() ^
2496 RHSC->getAPIntValue(),
2501 // Turn (C1-X) == C2 --> X == C1-C2
2502 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2503 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2505 DAG.getSetCC(dl, VT, N0.getOperand(1),
2506 DAG.getConstant(SUBC->getAPIntValue() -
2507 RHSC->getAPIntValue(),
2513 // Could RHSC fold directly into a compare?
2514 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2515 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2518 // Simplify (X+Z) == X --> Z == 0
2519 // Don't do this if X is an immediate that can fold into a cmp
2520 // instruction and X+Z has other uses. It could be an induction variable
2521 // chain, and the transform would increase register pressure.
2522 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2523 if (N0.getOperand(0) == N1)
2524 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2525 DAG.getConstant(0, N0.getValueType()), Cond);
2526 if (N0.getOperand(1) == N1) {
2527 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2528 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2529 DAG.getConstant(0, N0.getValueType()), Cond);
2530 else if (N0.getNode()->hasOneUse()) {
2531 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2532 // (Z-X) == X --> Z == X<<1
2533 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2534 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2535 if (!DCI.isCalledByLegalizer())
2536 DCI.AddToWorklist(SH.getNode());
2537 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2543 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2544 N1.getOpcode() == ISD::XOR) {
2545 // Simplify X == (X+Z) --> Z == 0
2546 if (N1.getOperand(0) == N0) {
2547 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2548 DAG.getConstant(0, N1.getValueType()), Cond);
2549 } else if (N1.getOperand(1) == N0) {
2550 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2551 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2552 DAG.getConstant(0, N1.getValueType()), Cond);
2553 } else if (N1.getNode()->hasOneUse()) {
2554 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2555 // X == (Z-X) --> X<<1 == Z
2556 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2557 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2558 if (!DCI.isCalledByLegalizer())
2559 DCI.AddToWorklist(SH.getNode());
2560 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2565 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2566 // Note that where y is variable and is known to have at most
2567 // one bit set (for example, if it is z&1) we cannot do this;
2568 // the expressions are not equivalent when y==0.
2569 if (N0.getOpcode() == ISD::AND)
2570 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2571 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2572 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2573 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2574 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2577 if (N1.getOpcode() == ISD::AND)
2578 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2579 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2580 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2581 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2582 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2587 // Fold away ALL boolean setcc's.
2589 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2591 default: llvm_unreachable("Unknown integer setcc!");
2592 case ISD::SETEQ: // X == Y -> ~(X^Y)
2593 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2594 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2595 if (!DCI.isCalledByLegalizer())
2596 DCI.AddToWorklist(Temp.getNode());
2598 case ISD::SETNE: // X != Y --> (X^Y)
2599 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2601 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2602 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2603 Temp = DAG.getNOT(dl, N0, MVT::i1);
2604 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2605 if (!DCI.isCalledByLegalizer())
2606 DCI.AddToWorklist(Temp.getNode());
2608 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2609 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2610 Temp = DAG.getNOT(dl, N1, MVT::i1);
2611 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2612 if (!DCI.isCalledByLegalizer())
2613 DCI.AddToWorklist(Temp.getNode());
2615 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2616 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2617 Temp = DAG.getNOT(dl, N0, MVT::i1);
2618 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2619 if (!DCI.isCalledByLegalizer())
2620 DCI.AddToWorklist(Temp.getNode());
2622 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2623 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2624 Temp = DAG.getNOT(dl, N1, MVT::i1);
2625 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2628 if (VT != MVT::i1) {
2629 if (!DCI.isCalledByLegalizer())
2630 DCI.AddToWorklist(N0.getNode());
2631 // FIXME: If running after legalize, we probably can't do this.
2632 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2637 // Could not fold it.
2641 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2642 /// node is a GlobalAddress + offset.
2643 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2644 int64_t &Offset) const {
2645 if (isa<GlobalAddressSDNode>(N)) {
2646 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2647 GA = GASD->getGlobal();
2648 Offset += GASD->getOffset();
2652 if (N->getOpcode() == ISD::ADD) {
2653 SDValue N1 = N->getOperand(0);
2654 SDValue N2 = N->getOperand(1);
2655 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2656 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2658 Offset += V->getSExtValue();
2661 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2662 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2664 Offset += V->getSExtValue();
2674 SDValue TargetLowering::
2675 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2676 // Default implementation: no optimization.
2680 //===----------------------------------------------------------------------===//
2681 // Inline Assembler Implementation Methods
2682 //===----------------------------------------------------------------------===//
2685 TargetLowering::ConstraintType
2686 TargetLowering::getConstraintType(const std::string &Constraint) const {
2687 if (Constraint.size() == 1) {
2688 switch (Constraint[0]) {
2690 case 'r': return C_RegisterClass;
2692 case 'o': // offsetable
2693 case 'V': // not offsetable
2695 case 'i': // Simple Integer or Relocatable Constant
2696 case 'n': // Simple Integer
2697 case 'E': // Floating Point Constant
2698 case 'F': // Floating Point Constant
2699 case 's': // Relocatable Constant
2700 case 'p': // Address.
2701 case 'X': // Allow ANY value.
2702 case 'I': // Target registers.
2716 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2717 Constraint[Constraint.size()-1] == '}')
2722 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2723 /// with another that has more specific requirements based on the type of the
2724 /// corresponding operand.
2725 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2726 if (ConstraintVT.isInteger())
2728 if (ConstraintVT.isFloatingPoint())
2729 return "f"; // works for many targets
2733 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2734 /// vector. If it is invalid, don't add anything to Ops.
2735 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2736 std::string &Constraint,
2737 std::vector<SDValue> &Ops,
2738 SelectionDAG &DAG) const {
2740 if (Constraint.length() > 1) return;
2742 char ConstraintLetter = Constraint[0];
2743 switch (ConstraintLetter) {
2745 case 'X': // Allows any operand; labels (basic block) use this.
2746 if (Op.getOpcode() == ISD::BasicBlock) {
2751 case 'i': // Simple Integer or Relocatable Constant
2752 case 'n': // Simple Integer
2753 case 's': { // Relocatable Constant
2754 // These operands are interested in values of the form (GV+C), where C may
2755 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2756 // is possible and fine if either GV or C are missing.
2757 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2758 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2760 // If we have "(add GV, C)", pull out GV/C
2761 if (Op.getOpcode() == ISD::ADD) {
2762 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2763 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2764 if (C == 0 || GA == 0) {
2765 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2766 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2768 if (C == 0 || GA == 0)
2772 // If we find a valid operand, map to the TargetXXX version so that the
2773 // value itself doesn't get selected.
2774 if (GA) { // Either &GV or &GV+C
2775 if (ConstraintLetter != 'n') {
2776 int64_t Offs = GA->getOffset();
2777 if (C) Offs += C->getZExtValue();
2778 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2779 C ? C->getDebugLoc() : DebugLoc(),
2780 Op.getValueType(), Offs));
2784 if (C) { // just C, no GV.
2785 // Simple constants are not allowed for 's'.
2786 if (ConstraintLetter != 's') {
2787 // gcc prints these as sign extended. Sign extend value to 64 bits
2788 // now; without this it would get ZExt'd later in
2789 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2790 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2800 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2801 getRegForInlineAsmConstraint(const std::string &Constraint,
2803 if (Constraint[0] != '{')
2804 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2805 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2807 // Remove the braces from around the name.
2808 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2810 // Figure out which register class contains this reg.
2811 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2812 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2813 E = RI->regclass_end(); RCI != E; ++RCI) {
2814 const TargetRegisterClass *RC = *RCI;
2816 // If none of the value types for this register class are valid, we
2817 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2821 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2823 if (RegName.equals_lower(RI->getName(*I)))
2824 return std::make_pair(*I, RC);
2828 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2831 //===----------------------------------------------------------------------===//
2832 // Constraint Selection.
2834 /// isMatchingInputConstraint - Return true of this is an input operand that is
2835 /// a matching constraint like "4".
2836 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2837 assert(!ConstraintCode.empty() && "No known constraint!");
2838 return isdigit(ConstraintCode[0]);
2841 /// getMatchedOperand - If this is an input matching constraint, this method
2842 /// returns the output operand it matches.
2843 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2844 assert(!ConstraintCode.empty() && "No known constraint!");
2845 return atoi(ConstraintCode.c_str());
2849 /// ParseConstraints - Split up the constraint string from the inline
2850 /// assembly value into the specific constraints and their prefixes,
2851 /// and also tie in the associated operand values.
2852 /// If this returns an empty vector, and if the constraint string itself
2853 /// isn't empty, there was an error parsing.
2854 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2855 ImmutableCallSite CS) const {
2856 /// ConstraintOperands - Information about all of the constraints.
2857 AsmOperandInfoVector ConstraintOperands;
2858 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2859 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2861 // Do a prepass over the constraints, canonicalizing them, and building up the
2862 // ConstraintOperands list.
2863 InlineAsm::ConstraintInfoVector
2864 ConstraintInfos = IA->ParseConstraints();
2866 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2867 unsigned ResNo = 0; // ResNo - The result number of the next output.
2869 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2870 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2871 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2873 // Update multiple alternative constraint count.
2874 if (OpInfo.multipleAlternatives.size() > maCount)
2875 maCount = OpInfo.multipleAlternatives.size();
2877 OpInfo.ConstraintVT = MVT::Other;
2879 // Compute the value type for each operand.
2880 switch (OpInfo.Type) {
2881 case InlineAsm::isOutput:
2882 // Indirect outputs just consume an argument.
2883 if (OpInfo.isIndirect) {
2884 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2888 // The return value of the call is this value. As such, there is no
2889 // corresponding argument.
2890 assert(!CS.getType()->isVoidTy() &&
2892 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2893 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2895 assert(ResNo == 0 && "Asm only has one result!");
2896 OpInfo.ConstraintVT = getValueType(CS.getType());
2900 case InlineAsm::isInput:
2901 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2903 case InlineAsm::isClobber:
2908 if (OpInfo.CallOperandVal) {
2909 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2910 if (OpInfo.isIndirect) {
2911 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2913 report_fatal_error("Indirect operand for inline asm not a pointer!");
2914 OpTy = PtrTy->getElementType();
2917 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2918 if (StructType *STy = dyn_cast<StructType>(OpTy))
2919 if (STy->getNumElements() == 1)
2920 OpTy = STy->getElementType(0);
2922 // If OpTy is not a single value, it may be a struct/union that we
2923 // can tile with integers.
2924 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2925 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2934 OpInfo.ConstraintVT =
2935 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2938 } else if (dyn_cast<PointerType>(OpTy)) {
2939 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2941 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2946 // If we have multiple alternative constraints, select the best alternative.
2947 if (ConstraintInfos.size()) {
2949 unsigned bestMAIndex = 0;
2950 int bestWeight = -1;
2951 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2954 // Compute the sums of the weights for each alternative, keeping track
2955 // of the best (highest weight) one so far.
2956 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2958 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2959 cIndex != eIndex; ++cIndex) {
2960 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2961 if (OpInfo.Type == InlineAsm::isClobber)
2964 // If this is an output operand with a matching input operand,
2965 // look up the matching input. If their types mismatch, e.g. one
2966 // is an integer, the other is floating point, or their sizes are
2967 // different, flag it as an maCantMatch.
2968 if (OpInfo.hasMatchingInput()) {
2969 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2970 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2971 if ((OpInfo.ConstraintVT.isInteger() !=
2972 Input.ConstraintVT.isInteger()) ||
2973 (OpInfo.ConstraintVT.getSizeInBits() !=
2974 Input.ConstraintVT.getSizeInBits())) {
2975 weightSum = -1; // Can't match.
2980 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2985 weightSum += weight;
2988 if (weightSum > bestWeight) {
2989 bestWeight = weightSum;
2990 bestMAIndex = maIndex;
2994 // Now select chosen alternative in each constraint.
2995 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2996 cIndex != eIndex; ++cIndex) {
2997 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2998 if (cInfo.Type == InlineAsm::isClobber)
3000 cInfo.selectAlternative(bestMAIndex);
3005 // Check and hook up tied operands, choose constraint code to use.
3006 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
3007 cIndex != eIndex; ++cIndex) {
3008 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
3010 // If this is an output operand with a matching input operand, look up the
3011 // matching input. If their types mismatch, e.g. one is an integer, the
3012 // other is floating point, or their sizes are different, flag it as an
3014 if (OpInfo.hasMatchingInput()) {
3015 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
3017 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
3018 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
3019 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
3020 std::pair<unsigned, const TargetRegisterClass*> InputRC =
3021 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
3022 if ((OpInfo.ConstraintVT.isInteger() !=
3023 Input.ConstraintVT.isInteger()) ||
3024 (MatchRC.second != InputRC.second)) {
3025 report_fatal_error("Unsupported asm: input constraint"
3026 " with a matching output constraint of"
3027 " incompatible type!");
3034 return ConstraintOperands;
3038 /// getConstraintGenerality - Return an integer indicating how general CT
3040 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3042 case TargetLowering::C_Other:
3043 case TargetLowering::C_Unknown:
3045 case TargetLowering::C_Register:
3047 case TargetLowering::C_RegisterClass:
3049 case TargetLowering::C_Memory:
3052 llvm_unreachable("Invalid constraint type");
3055 /// Examine constraint type and operand type and determine a weight value.
3056 /// This object must already have been set up with the operand type
3057 /// and the current alternative constraint selected.
3058 TargetLowering::ConstraintWeight
3059 TargetLowering::getMultipleConstraintMatchWeight(
3060 AsmOperandInfo &info, int maIndex) const {
3061 InlineAsm::ConstraintCodeVector *rCodes;
3062 if (maIndex >= (int)info.multipleAlternatives.size())
3063 rCodes = &info.Codes;
3065 rCodes = &info.multipleAlternatives[maIndex].Codes;
3066 ConstraintWeight BestWeight = CW_Invalid;
3068 // Loop over the options, keeping track of the most general one.
3069 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3070 ConstraintWeight weight =
3071 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3072 if (weight > BestWeight)
3073 BestWeight = weight;
3079 /// Examine constraint type and operand type and determine a weight value.
3080 /// This object must already have been set up with the operand type
3081 /// and the current alternative constraint selected.
3082 TargetLowering::ConstraintWeight
3083 TargetLowering::getSingleConstraintMatchWeight(
3084 AsmOperandInfo &info, const char *constraint) const {
3085 ConstraintWeight weight = CW_Invalid;
3086 Value *CallOperandVal = info.CallOperandVal;
3087 // If we don't have a value, we can't do a match,
3088 // but allow it at the lowest weight.
3089 if (CallOperandVal == NULL)
3091 // Look at the constraint type.
3092 switch (*constraint) {
3093 case 'i': // immediate integer.
3094 case 'n': // immediate integer with a known value.
3095 if (isa<ConstantInt>(CallOperandVal))
3096 weight = CW_Constant;
3098 case 's': // non-explicit intregal immediate.
3099 if (isa<GlobalValue>(CallOperandVal))
3100 weight = CW_Constant;
3102 case 'E': // immediate float if host format.
3103 case 'F': // immediate float.
3104 if (isa<ConstantFP>(CallOperandVal))
3105 weight = CW_Constant;
3107 case '<': // memory operand with autodecrement.
3108 case '>': // memory operand with autoincrement.
3109 case 'm': // memory operand.
3110 case 'o': // offsettable memory operand
3111 case 'V': // non-offsettable memory operand
3114 case 'r': // general register.
3115 case 'g': // general register, memory operand or immediate integer.
3116 // note: Clang converts "g" to "imr".
3117 if (CallOperandVal->getType()->isIntegerTy())
3118 weight = CW_Register;
3120 case 'X': // any operand.
3122 weight = CW_Default;
3128 /// ChooseConstraint - If there are multiple different constraints that we
3129 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3130 /// This is somewhat tricky: constraints fall into four classes:
3131 /// Other -> immediates and magic values
3132 /// Register -> one specific register
3133 /// RegisterClass -> a group of regs
3134 /// Memory -> memory
3135 /// Ideally, we would pick the most specific constraint possible: if we have
3136 /// something that fits into a register, we would pick it. The problem here
3137 /// is that if we have something that could either be in a register or in
3138 /// memory that use of the register could cause selection of *other*
3139 /// operands to fail: they might only succeed if we pick memory. Because of
3140 /// this the heuristic we use is:
3142 /// 1) If there is an 'other' constraint, and if the operand is valid for
3143 /// that constraint, use it. This makes us take advantage of 'i'
3144 /// constraints when available.
3145 /// 2) Otherwise, pick the most general constraint present. This prefers
3146 /// 'm' over 'r', for example.
3148 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3149 const TargetLowering &TLI,
3150 SDValue Op, SelectionDAG *DAG) {
3151 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3152 unsigned BestIdx = 0;
3153 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3154 int BestGenerality = -1;
3156 // Loop over the options, keeping track of the most general one.
3157 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3158 TargetLowering::ConstraintType CType =
3159 TLI.getConstraintType(OpInfo.Codes[i]);
3161 // If this is an 'other' constraint, see if the operand is valid for it.
3162 // For example, on X86 we might have an 'rI' constraint. If the operand
3163 // is an integer in the range [0..31] we want to use I (saving a load
3164 // of a register), otherwise we must use 'r'.
3165 if (CType == TargetLowering::C_Other && Op.getNode()) {
3166 assert(OpInfo.Codes[i].size() == 1 &&
3167 "Unhandled multi-letter 'other' constraint");
3168 std::vector<SDValue> ResultOps;
3169 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3171 if (!ResultOps.empty()) {
3178 // Things with matching constraints can only be registers, per gcc
3179 // documentation. This mainly affects "g" constraints.
3180 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3183 // This constraint letter is more general than the previous one, use it.
3184 int Generality = getConstraintGenerality(CType);
3185 if (Generality > BestGenerality) {
3188 BestGenerality = Generality;
3192 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3193 OpInfo.ConstraintType = BestType;
3196 /// ComputeConstraintToUse - Determines the constraint code and constraint
3197 /// type to use for the specific AsmOperandInfo, setting
3198 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3199 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3201 SelectionDAG *DAG) const {
3202 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3204 // Single-letter constraints ('r') are very common.
3205 if (OpInfo.Codes.size() == 1) {
3206 OpInfo.ConstraintCode = OpInfo.Codes[0];
3207 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3209 ChooseConstraint(OpInfo, *this, Op, DAG);
3212 // 'X' matches anything.
3213 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3214 // Labels and constants are handled elsewhere ('X' is the only thing
3215 // that matches labels). For Functions, the type here is the type of
3216 // the result, which is not what we want to look at; leave them alone.
3217 Value *v = OpInfo.CallOperandVal;
3218 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3219 OpInfo.CallOperandVal = v;
3223 // Otherwise, try to resolve it to something we know about by looking at
3224 // the actual operand type.
3225 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3226 OpInfo.ConstraintCode = Repl;
3227 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3232 //===----------------------------------------------------------------------===//
3233 // Loop Strength Reduction hooks
3234 //===----------------------------------------------------------------------===//
3236 /// isLegalAddressingMode - Return true if the addressing mode represented
3237 /// by AM is legal for this target, for a load/store of the specified type.
3238 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3240 // The default implementation of this implements a conservative RISCy, r+r and
3243 // Allows a sign-extended 16-bit immediate field.
3244 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3247 // No global is ever allowed as a base.
3251 // Only support r+r,
3253 case 0: // "r+i" or just "i", depending on HasBaseReg.
3256 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3258 // Otherwise we have r+r or r+i.
3261 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3263 // Allow 2*r as r+r.
3270 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3271 /// with the multiplicative inverse of the constant.
3272 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3273 SelectionDAG &DAG) const {
3274 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3275 APInt d = C->getAPIntValue();
3276 assert(d != 0 && "Division by zero!");
3278 // Shift the value upfront if it is even, so the LSB is one.
3279 unsigned ShAmt = d.countTrailingZeros();
3281 // TODO: For UDIV use SRL instead of SRA.
3282 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3283 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3287 // Calculate the multiplicative inverse, using Newton's method.
3289 while ((t = d*xn) != 1)
3290 xn *= APInt(d.getBitWidth(), 2) - t;
3292 Op2 = DAG.getConstant(xn, Op1.getValueType());
3293 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3296 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3297 /// return a DAG expression to select that will generate the same value by
3298 /// multiplying by a magic number. See:
3299 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3300 SDValue TargetLowering::
3301 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3302 std::vector<SDNode*>* Created) const {
3303 EVT VT = N->getValueType(0);
3304 DebugLoc dl= N->getDebugLoc();
3306 // Check to see if we can do this.
3307 // FIXME: We should be more aggressive here.
3308 if (!isTypeLegal(VT))
3311 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3312 APInt::ms magics = d.magic();
3314 // Multiply the numerator (operand 0) by the magic value
3315 // FIXME: We should support doing a MUL in a wider type
3317 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3318 isOperationLegalOrCustom(ISD::MULHS, VT))
3319 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3320 DAG.getConstant(magics.m, VT));
3321 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3322 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3323 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3325 DAG.getConstant(magics.m, VT)).getNode(), 1);
3327 return SDValue(); // No mulhs or equvialent
3328 // If d > 0 and m < 0, add the numerator
3329 if (d.isStrictlyPositive() && magics.m.isNegative()) {
3330 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3332 Created->push_back(Q.getNode());
3334 // If d < 0 and m > 0, subtract the numerator.
3335 if (d.isNegative() && magics.m.isStrictlyPositive()) {
3336 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3338 Created->push_back(Q.getNode());
3340 // Shift right algebraic if shift value is nonzero
3342 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3343 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3345 Created->push_back(Q.getNode());
3347 // Extract the sign bit and add it to the quotient
3349 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3350 getShiftAmountTy(Q.getValueType())));
3352 Created->push_back(T.getNode());
3353 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3356 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3357 /// return a DAG expression to select that will generate the same value by
3358 /// multiplying by a magic number. See:
3359 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3360 SDValue TargetLowering::
3361 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3362 std::vector<SDNode*>* Created) const {
3363 EVT VT = N->getValueType(0);
3364 DebugLoc dl = N->getDebugLoc();
3366 // Check to see if we can do this.
3367 // FIXME: We should be more aggressive here.
3368 if (!isTypeLegal(VT))
3371 // FIXME: We should use a narrower constant when the upper
3372 // bits are known to be zero.
3373 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3374 APInt::mu magics = N1C.magicu();
3376 SDValue Q = N->getOperand(0);
3378 // If the divisor is even, we can avoid using the expensive fixup by shifting
3379 // the divided value upfront.
3380 if (magics.a != 0 && !N1C[0]) {
3381 unsigned Shift = N1C.countTrailingZeros();
3382 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3383 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3385 Created->push_back(Q.getNode());
3387 // Get magic number for the shifted divisor.
3388 magics = N1C.lshr(Shift).magicu(Shift);
3389 assert(magics.a == 0 && "Should use cheap fixup now");
3392 // Multiply the numerator (operand 0) by the magic value
3393 // FIXME: We should support doing a MUL in a wider type
3394 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3395 isOperationLegalOrCustom(ISD::MULHU, VT))
3396 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3397 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3398 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3399 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3400 DAG.getConstant(magics.m, VT)).getNode(), 1);
3402 return SDValue(); // No mulhu or equvialent
3404 Created->push_back(Q.getNode());
3406 if (magics.a == 0) {
3407 assert(magics.s < N1C.getBitWidth() &&
3408 "We shouldn't generate an undefined shift!");
3409 return DAG.getNode(ISD::SRL, dl, VT, Q,
3410 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3412 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3414 Created->push_back(NPQ.getNode());
3415 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3416 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3418 Created->push_back(NPQ.getNode());
3419 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3421 Created->push_back(NPQ.getNode());
3422 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3423 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));