1 //===-- TargetLowering.cpp - Implement the TargetLowering class -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the TargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Target/TargetLowering.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCExpr.h"
17 #include "llvm/Target/TargetData.h"
18 #include "llvm/Target/TargetLoweringObjectFile.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/GlobalVariable.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineJumpTableInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
35 /// We are in the process of implementing a new TypeLegalization action
36 /// - the promotion of vector elements. This feature is disabled by default
37 /// and only enabled using this flag.
39 AllowPromoteIntElem("promote-elements", cl::Hidden, cl::init(true),
40 cl::desc("Allow promotion of integer vector element types"));
42 /// InitLibcallNames - Set default libcall names.
44 static void InitLibcallNames(const char **Names) {
45 Names[RTLIB::SHL_I16] = "__ashlhi3";
46 Names[RTLIB::SHL_I32] = "__ashlsi3";
47 Names[RTLIB::SHL_I64] = "__ashldi3";
48 Names[RTLIB::SHL_I128] = "__ashlti3";
49 Names[RTLIB::SRL_I16] = "__lshrhi3";
50 Names[RTLIB::SRL_I32] = "__lshrsi3";
51 Names[RTLIB::SRL_I64] = "__lshrdi3";
52 Names[RTLIB::SRL_I128] = "__lshrti3";
53 Names[RTLIB::SRA_I16] = "__ashrhi3";
54 Names[RTLIB::SRA_I32] = "__ashrsi3";
55 Names[RTLIB::SRA_I64] = "__ashrdi3";
56 Names[RTLIB::SRA_I128] = "__ashrti3";
57 Names[RTLIB::MUL_I8] = "__mulqi3";
58 Names[RTLIB::MUL_I16] = "__mulhi3";
59 Names[RTLIB::MUL_I32] = "__mulsi3";
60 Names[RTLIB::MUL_I64] = "__muldi3";
61 Names[RTLIB::MUL_I128] = "__multi3";
62 Names[RTLIB::MULO_I32] = "__mulosi4";
63 Names[RTLIB::MULO_I64] = "__mulodi4";
64 Names[RTLIB::MULO_I128] = "__muloti4";
65 Names[RTLIB::SDIV_I8] = "__divqi3";
66 Names[RTLIB::SDIV_I16] = "__divhi3";
67 Names[RTLIB::SDIV_I32] = "__divsi3";
68 Names[RTLIB::SDIV_I64] = "__divdi3";
69 Names[RTLIB::SDIV_I128] = "__divti3";
70 Names[RTLIB::UDIV_I8] = "__udivqi3";
71 Names[RTLIB::UDIV_I16] = "__udivhi3";
72 Names[RTLIB::UDIV_I32] = "__udivsi3";
73 Names[RTLIB::UDIV_I64] = "__udivdi3";
74 Names[RTLIB::UDIV_I128] = "__udivti3";
75 Names[RTLIB::SREM_I8] = "__modqi3";
76 Names[RTLIB::SREM_I16] = "__modhi3";
77 Names[RTLIB::SREM_I32] = "__modsi3";
78 Names[RTLIB::SREM_I64] = "__moddi3";
79 Names[RTLIB::SREM_I128] = "__modti3";
80 Names[RTLIB::UREM_I8] = "__umodqi3";
81 Names[RTLIB::UREM_I16] = "__umodhi3";
82 Names[RTLIB::UREM_I32] = "__umodsi3";
83 Names[RTLIB::UREM_I64] = "__umoddi3";
84 Names[RTLIB::UREM_I128] = "__umodti3";
86 // These are generally not available.
87 Names[RTLIB::SDIVREM_I8] = 0;
88 Names[RTLIB::SDIVREM_I16] = 0;
89 Names[RTLIB::SDIVREM_I32] = 0;
90 Names[RTLIB::SDIVREM_I64] = 0;
91 Names[RTLIB::SDIVREM_I128] = 0;
92 Names[RTLIB::UDIVREM_I8] = 0;
93 Names[RTLIB::UDIVREM_I16] = 0;
94 Names[RTLIB::UDIVREM_I32] = 0;
95 Names[RTLIB::UDIVREM_I64] = 0;
96 Names[RTLIB::UDIVREM_I128] = 0;
98 Names[RTLIB::NEG_I32] = "__negsi2";
99 Names[RTLIB::NEG_I64] = "__negdi2";
100 Names[RTLIB::ADD_F32] = "__addsf3";
101 Names[RTLIB::ADD_F64] = "__adddf3";
102 Names[RTLIB::ADD_F80] = "__addxf3";
103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
104 Names[RTLIB::SUB_F32] = "__subsf3";
105 Names[RTLIB::SUB_F64] = "__subdf3";
106 Names[RTLIB::SUB_F80] = "__subxf3";
107 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
108 Names[RTLIB::MUL_F32] = "__mulsf3";
109 Names[RTLIB::MUL_F64] = "__muldf3";
110 Names[RTLIB::MUL_F80] = "__mulxf3";
111 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
112 Names[RTLIB::DIV_F32] = "__divsf3";
113 Names[RTLIB::DIV_F64] = "__divdf3";
114 Names[RTLIB::DIV_F80] = "__divxf3";
115 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
116 Names[RTLIB::REM_F32] = "fmodf";
117 Names[RTLIB::REM_F64] = "fmod";
118 Names[RTLIB::REM_F80] = "fmodl";
119 Names[RTLIB::REM_PPCF128] = "fmodl";
120 Names[RTLIB::FMA_F32] = "fmaf";
121 Names[RTLIB::FMA_F64] = "fma";
122 Names[RTLIB::FMA_F80] = "fmal";
123 Names[RTLIB::FMA_PPCF128] = "fmal";
124 Names[RTLIB::POWI_F32] = "__powisf2";
125 Names[RTLIB::POWI_F64] = "__powidf2";
126 Names[RTLIB::POWI_F80] = "__powixf2";
127 Names[RTLIB::POWI_PPCF128] = "__powitf2";
128 Names[RTLIB::SQRT_F32] = "sqrtf";
129 Names[RTLIB::SQRT_F64] = "sqrt";
130 Names[RTLIB::SQRT_F80] = "sqrtl";
131 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
132 Names[RTLIB::LOG_F32] = "logf";
133 Names[RTLIB::LOG_F64] = "log";
134 Names[RTLIB::LOG_F80] = "logl";
135 Names[RTLIB::LOG_PPCF128] = "logl";
136 Names[RTLIB::LOG2_F32] = "log2f";
137 Names[RTLIB::LOG2_F64] = "log2";
138 Names[RTLIB::LOG2_F80] = "log2l";
139 Names[RTLIB::LOG2_PPCF128] = "log2l";
140 Names[RTLIB::LOG10_F32] = "log10f";
141 Names[RTLIB::LOG10_F64] = "log10";
142 Names[RTLIB::LOG10_F80] = "log10l";
143 Names[RTLIB::LOG10_PPCF128] = "log10l";
144 Names[RTLIB::EXP_F32] = "expf";
145 Names[RTLIB::EXP_F64] = "exp";
146 Names[RTLIB::EXP_F80] = "expl";
147 Names[RTLIB::EXP_PPCF128] = "expl";
148 Names[RTLIB::EXP2_F32] = "exp2f";
149 Names[RTLIB::EXP2_F64] = "exp2";
150 Names[RTLIB::EXP2_F80] = "exp2l";
151 Names[RTLIB::EXP2_PPCF128] = "exp2l";
152 Names[RTLIB::SIN_F32] = "sinf";
153 Names[RTLIB::SIN_F64] = "sin";
154 Names[RTLIB::SIN_F80] = "sinl";
155 Names[RTLIB::SIN_PPCF128] = "sinl";
156 Names[RTLIB::COS_F32] = "cosf";
157 Names[RTLIB::COS_F64] = "cos";
158 Names[RTLIB::COS_F80] = "cosl";
159 Names[RTLIB::COS_PPCF128] = "cosl";
160 Names[RTLIB::POW_F32] = "powf";
161 Names[RTLIB::POW_F64] = "pow";
162 Names[RTLIB::POW_F80] = "powl";
163 Names[RTLIB::POW_PPCF128] = "powl";
164 Names[RTLIB::CEIL_F32] = "ceilf";
165 Names[RTLIB::CEIL_F64] = "ceil";
166 Names[RTLIB::CEIL_F80] = "ceill";
167 Names[RTLIB::CEIL_PPCF128] = "ceill";
168 Names[RTLIB::TRUNC_F32] = "truncf";
169 Names[RTLIB::TRUNC_F64] = "trunc";
170 Names[RTLIB::TRUNC_F80] = "truncl";
171 Names[RTLIB::TRUNC_PPCF128] = "truncl";
172 Names[RTLIB::RINT_F32] = "rintf";
173 Names[RTLIB::RINT_F64] = "rint";
174 Names[RTLIB::RINT_F80] = "rintl";
175 Names[RTLIB::RINT_PPCF128] = "rintl";
176 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
177 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
178 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
179 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
180 Names[RTLIB::FLOOR_F32] = "floorf";
181 Names[RTLIB::FLOOR_F64] = "floor";
182 Names[RTLIB::FLOOR_F80] = "floorl";
183 Names[RTLIB::FLOOR_PPCF128] = "floorl";
184 Names[RTLIB::COPYSIGN_F32] = "copysignf";
185 Names[RTLIB::COPYSIGN_F64] = "copysign";
186 Names[RTLIB::COPYSIGN_F80] = "copysignl";
187 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
188 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
189 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
190 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
191 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
192 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
193 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
194 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
195 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
196 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
197 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
198 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
199 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
200 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
201 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
202 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
203 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
204 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
205 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
206 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
207 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
208 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
209 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
210 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
211 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
212 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
213 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
214 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
215 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
216 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
217 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
218 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
219 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
220 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
221 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
222 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
223 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
224 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
225 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
226 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
227 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
228 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
229 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
230 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
231 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
232 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
233 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
234 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
235 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
236 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
237 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
238 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
239 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
240 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
241 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
242 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
243 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
244 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
245 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
246 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
247 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
248 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
249 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
250 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
251 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
252 Names[RTLIB::OEQ_F32] = "__eqsf2";
253 Names[RTLIB::OEQ_F64] = "__eqdf2";
254 Names[RTLIB::UNE_F32] = "__nesf2";
255 Names[RTLIB::UNE_F64] = "__nedf2";
256 Names[RTLIB::OGE_F32] = "__gesf2";
257 Names[RTLIB::OGE_F64] = "__gedf2";
258 Names[RTLIB::OLT_F32] = "__ltsf2";
259 Names[RTLIB::OLT_F64] = "__ltdf2";
260 Names[RTLIB::OLE_F32] = "__lesf2";
261 Names[RTLIB::OLE_F64] = "__ledf2";
262 Names[RTLIB::OGT_F32] = "__gtsf2";
263 Names[RTLIB::OGT_F64] = "__gtdf2";
264 Names[RTLIB::UO_F32] = "__unordsf2";
265 Names[RTLIB::UO_F64] = "__unorddf2";
266 Names[RTLIB::O_F32] = "__unordsf2";
267 Names[RTLIB::O_F64] = "__unorddf2";
268 Names[RTLIB::MEMCPY] = "memcpy";
269 Names[RTLIB::MEMMOVE] = "memmove";
270 Names[RTLIB::MEMSET] = "memset";
271 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
272 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
273 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
274 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
275 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
276 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
277 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
278 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
279 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
280 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
281 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
282 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
283 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
284 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
285 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
286 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
287 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
288 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
289 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
290 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
291 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
292 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
293 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
294 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
295 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
296 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
297 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
298 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
299 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
300 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
301 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
302 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
303 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
306 /// InitLibcallCallingConvs - Set default libcall CallingConvs.
308 static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
309 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
310 CCs[i] = CallingConv::C;
314 /// getFPEXT - Return the FPEXT_*_* value for the given types, or
315 /// UNKNOWN_LIBCALL if there is none.
316 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
317 if (OpVT == MVT::f32) {
318 if (RetVT == MVT::f64)
319 return FPEXT_F32_F64;
322 return UNKNOWN_LIBCALL;
325 /// getFPROUND - Return the FPROUND_*_* value for the given types, or
326 /// UNKNOWN_LIBCALL if there is none.
327 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
328 if (RetVT == MVT::f32) {
329 if (OpVT == MVT::f64)
330 return FPROUND_F64_F32;
331 if (OpVT == MVT::f80)
332 return FPROUND_F80_F32;
333 if (OpVT == MVT::ppcf128)
334 return FPROUND_PPCF128_F32;
335 } else if (RetVT == MVT::f64) {
336 if (OpVT == MVT::f80)
337 return FPROUND_F80_F64;
338 if (OpVT == MVT::ppcf128)
339 return FPROUND_PPCF128_F64;
342 return UNKNOWN_LIBCALL;
345 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
346 /// UNKNOWN_LIBCALL if there is none.
347 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
348 if (OpVT == MVT::f32) {
349 if (RetVT == MVT::i8)
350 return FPTOSINT_F32_I8;
351 if (RetVT == MVT::i16)
352 return FPTOSINT_F32_I16;
353 if (RetVT == MVT::i32)
354 return FPTOSINT_F32_I32;
355 if (RetVT == MVT::i64)
356 return FPTOSINT_F32_I64;
357 if (RetVT == MVT::i128)
358 return FPTOSINT_F32_I128;
359 } else if (OpVT == MVT::f64) {
360 if (RetVT == MVT::i8)
361 return FPTOSINT_F64_I8;
362 if (RetVT == MVT::i16)
363 return FPTOSINT_F64_I16;
364 if (RetVT == MVT::i32)
365 return FPTOSINT_F64_I32;
366 if (RetVT == MVT::i64)
367 return FPTOSINT_F64_I64;
368 if (RetVT == MVT::i128)
369 return FPTOSINT_F64_I128;
370 } else if (OpVT == MVT::f80) {
371 if (RetVT == MVT::i32)
372 return FPTOSINT_F80_I32;
373 if (RetVT == MVT::i64)
374 return FPTOSINT_F80_I64;
375 if (RetVT == MVT::i128)
376 return FPTOSINT_F80_I128;
377 } else if (OpVT == MVT::ppcf128) {
378 if (RetVT == MVT::i32)
379 return FPTOSINT_PPCF128_I32;
380 if (RetVT == MVT::i64)
381 return FPTOSINT_PPCF128_I64;
382 if (RetVT == MVT::i128)
383 return FPTOSINT_PPCF128_I128;
385 return UNKNOWN_LIBCALL;
388 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
389 /// UNKNOWN_LIBCALL if there is none.
390 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
391 if (OpVT == MVT::f32) {
392 if (RetVT == MVT::i8)
393 return FPTOUINT_F32_I8;
394 if (RetVT == MVT::i16)
395 return FPTOUINT_F32_I16;
396 if (RetVT == MVT::i32)
397 return FPTOUINT_F32_I32;
398 if (RetVT == MVT::i64)
399 return FPTOUINT_F32_I64;
400 if (RetVT == MVT::i128)
401 return FPTOUINT_F32_I128;
402 } else if (OpVT == MVT::f64) {
403 if (RetVT == MVT::i8)
404 return FPTOUINT_F64_I8;
405 if (RetVT == MVT::i16)
406 return FPTOUINT_F64_I16;
407 if (RetVT == MVT::i32)
408 return FPTOUINT_F64_I32;
409 if (RetVT == MVT::i64)
410 return FPTOUINT_F64_I64;
411 if (RetVT == MVT::i128)
412 return FPTOUINT_F64_I128;
413 } else if (OpVT == MVT::f80) {
414 if (RetVT == MVT::i32)
415 return FPTOUINT_F80_I32;
416 if (RetVT == MVT::i64)
417 return FPTOUINT_F80_I64;
418 if (RetVT == MVT::i128)
419 return FPTOUINT_F80_I128;
420 } else if (OpVT == MVT::ppcf128) {
421 if (RetVT == MVT::i32)
422 return FPTOUINT_PPCF128_I32;
423 if (RetVT == MVT::i64)
424 return FPTOUINT_PPCF128_I64;
425 if (RetVT == MVT::i128)
426 return FPTOUINT_PPCF128_I128;
428 return UNKNOWN_LIBCALL;
431 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
432 /// UNKNOWN_LIBCALL if there is none.
433 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
434 if (OpVT == MVT::i32) {
435 if (RetVT == MVT::f32)
436 return SINTTOFP_I32_F32;
437 else if (RetVT == MVT::f64)
438 return SINTTOFP_I32_F64;
439 else if (RetVT == MVT::f80)
440 return SINTTOFP_I32_F80;
441 else if (RetVT == MVT::ppcf128)
442 return SINTTOFP_I32_PPCF128;
443 } else if (OpVT == MVT::i64) {
444 if (RetVT == MVT::f32)
445 return SINTTOFP_I64_F32;
446 else if (RetVT == MVT::f64)
447 return SINTTOFP_I64_F64;
448 else if (RetVT == MVT::f80)
449 return SINTTOFP_I64_F80;
450 else if (RetVT == MVT::ppcf128)
451 return SINTTOFP_I64_PPCF128;
452 } else if (OpVT == MVT::i128) {
453 if (RetVT == MVT::f32)
454 return SINTTOFP_I128_F32;
455 else if (RetVT == MVT::f64)
456 return SINTTOFP_I128_F64;
457 else if (RetVT == MVT::f80)
458 return SINTTOFP_I128_F80;
459 else if (RetVT == MVT::ppcf128)
460 return SINTTOFP_I128_PPCF128;
462 return UNKNOWN_LIBCALL;
465 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
466 /// UNKNOWN_LIBCALL if there is none.
467 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
468 if (OpVT == MVT::i32) {
469 if (RetVT == MVT::f32)
470 return UINTTOFP_I32_F32;
471 else if (RetVT == MVT::f64)
472 return UINTTOFP_I32_F64;
473 else if (RetVT == MVT::f80)
474 return UINTTOFP_I32_F80;
475 else if (RetVT == MVT::ppcf128)
476 return UINTTOFP_I32_PPCF128;
477 } else if (OpVT == MVT::i64) {
478 if (RetVT == MVT::f32)
479 return UINTTOFP_I64_F32;
480 else if (RetVT == MVT::f64)
481 return UINTTOFP_I64_F64;
482 else if (RetVT == MVT::f80)
483 return UINTTOFP_I64_F80;
484 else if (RetVT == MVT::ppcf128)
485 return UINTTOFP_I64_PPCF128;
486 } else if (OpVT == MVT::i128) {
487 if (RetVT == MVT::f32)
488 return UINTTOFP_I128_F32;
489 else if (RetVT == MVT::f64)
490 return UINTTOFP_I128_F64;
491 else if (RetVT == MVT::f80)
492 return UINTTOFP_I128_F80;
493 else if (RetVT == MVT::ppcf128)
494 return UINTTOFP_I128_PPCF128;
496 return UNKNOWN_LIBCALL;
499 /// InitCmpLibcallCCs - Set default comparison libcall CC.
501 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
502 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
503 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
504 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
505 CCs[RTLIB::UNE_F32] = ISD::SETNE;
506 CCs[RTLIB::UNE_F64] = ISD::SETNE;
507 CCs[RTLIB::OGE_F32] = ISD::SETGE;
508 CCs[RTLIB::OGE_F64] = ISD::SETGE;
509 CCs[RTLIB::OLT_F32] = ISD::SETLT;
510 CCs[RTLIB::OLT_F64] = ISD::SETLT;
511 CCs[RTLIB::OLE_F32] = ISD::SETLE;
512 CCs[RTLIB::OLE_F64] = ISD::SETLE;
513 CCs[RTLIB::OGT_F32] = ISD::SETGT;
514 CCs[RTLIB::OGT_F64] = ISD::SETGT;
515 CCs[RTLIB::UO_F32] = ISD::SETNE;
516 CCs[RTLIB::UO_F64] = ISD::SETNE;
517 CCs[RTLIB::O_F32] = ISD::SETEQ;
518 CCs[RTLIB::O_F64] = ISD::SETEQ;
521 /// NOTE: The constructor takes ownership of TLOF.
522 TargetLowering::TargetLowering(const TargetMachine &tm,
523 const TargetLoweringObjectFile *tlof)
524 : TM(tm), TD(TM.getTargetData()), TLOF(*tlof),
525 mayPromoteElements(AllowPromoteIntElem) {
526 // All operations default to being supported.
527 memset(OpActions, 0, sizeof(OpActions));
528 memset(LoadExtActions, 0, sizeof(LoadExtActions));
529 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
530 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
531 memset(CondCodeActions, 0, sizeof(CondCodeActions));
533 // Set default actions for various operations.
534 for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
535 // Default all indexed load / store to expand.
536 for (unsigned IM = (unsigned)ISD::PRE_INC;
537 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
538 setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
539 setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
542 // These operations default to expand.
543 setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
547 // Most targets ignore the @llvm.prefetch intrinsic.
548 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
550 // ConstantFP nodes default to expand. Targets can either change this to
551 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
552 // to optimize expansions for certain constants.
553 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
554 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
555 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
556 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
558 // These library functions default to expand.
559 setOperationAction(ISD::FLOG , MVT::f16, Expand);
560 setOperationAction(ISD::FLOG2, MVT::f16, Expand);
561 setOperationAction(ISD::FLOG10, MVT::f16, Expand);
562 setOperationAction(ISD::FEXP , MVT::f16, Expand);
563 setOperationAction(ISD::FEXP2, MVT::f16, Expand);
564 setOperationAction(ISD::FFLOOR, MVT::f16, Expand);
565 setOperationAction(ISD::FNEARBYINT, MVT::f16, Expand);
566 setOperationAction(ISD::FCEIL, MVT::f16, Expand);
567 setOperationAction(ISD::FRINT, MVT::f16, Expand);
568 setOperationAction(ISD::FTRUNC, MVT::f16, Expand);
569 setOperationAction(ISD::FLOG , MVT::f32, Expand);
570 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
571 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
572 setOperationAction(ISD::FEXP , MVT::f32, Expand);
573 setOperationAction(ISD::FEXP2, MVT::f32, Expand);
574 setOperationAction(ISD::FFLOOR, MVT::f32, Expand);
575 setOperationAction(ISD::FNEARBYINT, MVT::f32, Expand);
576 setOperationAction(ISD::FCEIL, MVT::f32, Expand);
577 setOperationAction(ISD::FRINT, MVT::f32, Expand);
578 setOperationAction(ISD::FTRUNC, MVT::f32, Expand);
579 setOperationAction(ISD::FLOG , MVT::f64, Expand);
580 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
581 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
582 setOperationAction(ISD::FEXP , MVT::f64, Expand);
583 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
584 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
585 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
586 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
587 setOperationAction(ISD::FRINT, MVT::f64, Expand);
588 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
590 // Default ISD::TRAP to expand (which turns it into abort).
591 setOperationAction(ISD::TRAP, MVT::Other, Expand);
593 IsLittleEndian = TD->isLittleEndian();
594 PointerTy = MVT::getIntegerVT(8*TD->getPointerSize());
595 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
596 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
597 maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
598 maxStoresPerMemsetOptSize = maxStoresPerMemcpyOptSize
599 = maxStoresPerMemmoveOptSize = 4;
600 benefitFromCodePlacementOpt = false;
601 UseUnderscoreSetJmp = false;
602 UseUnderscoreLongJmp = false;
603 SelectIsExpensive = false;
604 IntDivIsCheap = false;
605 Pow2DivIsCheap = false;
606 JumpIsExpensive = false;
607 StackPointerRegisterToSaveRestore = 0;
608 ExceptionPointerRegister = 0;
609 ExceptionSelectorRegister = 0;
610 BooleanContents = UndefinedBooleanContent;
611 BooleanVectorContents = UndefinedBooleanContent;
612 SchedPreferenceInfo = Sched::ILP;
614 JumpBufAlignment = 0;
615 MinFunctionAlignment = 0;
616 PrefFunctionAlignment = 0;
617 PrefLoopAlignment = 0;
618 MinStackArgumentAlignment = 1;
619 ShouldFoldAtomicFences = false;
620 InsertFencesForAtomic = false;
622 InitLibcallNames(LibcallRoutineNames);
623 InitCmpLibcallCCs(CmpLibcallCCs);
624 InitLibcallCallingConvs(LibcallCallingConvs);
627 TargetLowering::~TargetLowering() {
631 MVT TargetLowering::getShiftAmountTy(EVT LHSTy) const {
632 return MVT::getIntegerVT(8*TD->getPointerSize());
635 /// canOpTrap - Returns true if the operation can trap for the value type.
636 /// VT must be a legal type.
637 bool TargetLowering::canOpTrap(unsigned Op, EVT VT) const {
638 assert(isTypeLegal(VT));
653 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
654 unsigned &NumIntermediates,
656 TargetLowering *TLI) {
657 // Figure out the right, legal destination reg to copy into.
658 unsigned NumElts = VT.getVectorNumElements();
659 MVT EltTy = VT.getVectorElementType();
661 unsigned NumVectorRegs = 1;
663 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
664 // could break down into LHS/RHS like LegalizeDAG does.
665 if (!isPowerOf2_32(NumElts)) {
666 NumVectorRegs = NumElts;
670 // Divide the input until we get to a supported size. This will always
671 // end with a scalar if the target doesn't support vectors.
672 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
677 NumIntermediates = NumVectorRegs;
679 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
680 if (!TLI->isTypeLegal(NewVT))
682 IntermediateVT = NewVT;
684 unsigned NewVTSize = NewVT.getSizeInBits();
686 // Convert sizes such as i33 to i64.
687 if (!isPowerOf2_32(NewVTSize))
688 NewVTSize = NextPowerOf2(NewVTSize);
690 EVT DestVT = TLI->getRegisterType(NewVT);
692 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
693 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
695 // Otherwise, promotion or legal types use the same number of registers as
696 // the vector decimated to the appropriate level.
697 return NumVectorRegs;
700 /// isLegalRC - Return true if the value types that can be represented by the
701 /// specified register class are all legal.
702 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
703 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
711 /// hasLegalSuperRegRegClasses - Return true if the specified register class
712 /// has one or more super-reg register classes that are legal.
714 TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
715 if (*RC->superregclasses_begin() == 0)
717 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
718 E = RC->superregclasses_end(); I != E; ++I) {
719 const TargetRegisterClass *RRC = *I;
726 /// findRepresentativeClass - Return the largest legal super-reg register class
727 /// of the register class for the specified type and its associated "cost".
728 std::pair<const TargetRegisterClass*, uint8_t>
729 TargetLowering::findRepresentativeClass(EVT VT) const {
730 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
732 return std::make_pair(RC, 0);
733 const TargetRegisterClass *BestRC = RC;
734 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
735 E = RC->superregclasses_end(); I != E; ++I) {
736 const TargetRegisterClass *RRC = *I;
737 if (RRC->isASubClass() || !isLegalRC(RRC))
739 if (!hasLegalSuperRegRegClasses(RRC))
740 return std::make_pair(RRC, 1);
743 return std::make_pair(BestRC, 1);
747 /// computeRegisterProperties - Once all of the register classes are added,
748 /// this allows us to compute derived properties we expose.
749 void TargetLowering::computeRegisterProperties() {
750 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
751 "Too many value types for ValueTypeActions to hold!");
753 // Everything defaults to needing one register.
754 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
755 NumRegistersForVT[i] = 1;
756 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
758 // ...except isVoid, which doesn't need any registers.
759 NumRegistersForVT[MVT::isVoid] = 0;
761 // Find the largest integer register class.
762 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
763 for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
764 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
766 // Every integer value type larger than this largest register takes twice as
767 // many registers to represent as the previous ValueType.
768 for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
769 EVT ExpandedVT = (MVT::SimpleValueType)ExpandedReg;
770 if (!ExpandedVT.isInteger())
772 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
773 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
774 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
775 ValueTypeActions.setTypeAction(ExpandedVT, TypeExpandInteger);
778 // Inspect all of the ValueType's smaller than the largest integer
779 // register to see which ones need promotion.
780 unsigned LegalIntReg = LargestIntReg;
781 for (unsigned IntReg = LargestIntReg - 1;
782 IntReg >= (unsigned)MVT::i1; --IntReg) {
783 EVT IVT = (MVT::SimpleValueType)IntReg;
784 if (isTypeLegal(IVT)) {
785 LegalIntReg = IntReg;
787 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
788 (MVT::SimpleValueType)LegalIntReg;
789 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
793 // ppcf128 type is really two f64's.
794 if (!isTypeLegal(MVT::ppcf128)) {
795 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
796 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
797 TransformToType[MVT::ppcf128] = MVT::f64;
798 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
801 // Decide how to handle f64. If the target does not have native f64 support,
802 // expand it to i64 and we will be generating soft float library calls.
803 if (!isTypeLegal(MVT::f64)) {
804 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
805 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
806 TransformToType[MVT::f64] = MVT::i64;
807 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
810 // Decide how to handle f32. If the target does not have native support for
811 // f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
812 if (!isTypeLegal(MVT::f32)) {
813 if (isTypeLegal(MVT::f64)) {
814 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
815 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
816 TransformToType[MVT::f32] = MVT::f64;
817 ValueTypeActions.setTypeAction(MVT::f32, TypePromoteInteger);
819 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
820 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
821 TransformToType[MVT::f32] = MVT::i32;
822 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
826 // Loop over all of the vector value types to see which need transformations.
827 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
828 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
829 MVT VT = (MVT::SimpleValueType)i;
830 if (isTypeLegal(VT)) continue;
832 // Determine if there is a legal wider type. If so, we should promote to
833 // that wider vector type.
834 EVT EltVT = VT.getVectorElementType();
835 unsigned NElts = VT.getVectorNumElements();
837 bool IsLegalWiderType = false;
838 // If we allow the promotion of vector elements using a flag,
839 // then return TypePromoteInteger on vector elements.
840 // First try to promote the elements of integer vectors. If no legal
841 // promotion was found, fallback to the widen-vector method.
842 if (mayPromoteElements)
843 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
844 EVT SVT = (MVT::SimpleValueType)nVT;
845 // Promote vectors of integers to vectors with the same number
846 // of elements, with a wider element type.
847 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
848 && SVT.getVectorNumElements() == NElts &&
849 isTypeLegal(SVT) && SVT.getScalarType().isInteger()) {
850 TransformToType[i] = SVT;
851 RegisterTypeForVT[i] = SVT;
852 NumRegistersForVT[i] = 1;
853 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
854 IsLegalWiderType = true;
859 if (IsLegalWiderType) continue;
861 // Try to widen the vector.
862 for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
863 EVT SVT = (MVT::SimpleValueType)nVT;
864 if (SVT.getVectorElementType() == EltVT &&
865 SVT.getVectorNumElements() > NElts &&
867 TransformToType[i] = SVT;
868 RegisterTypeForVT[i] = SVT;
869 NumRegistersForVT[i] = 1;
870 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
871 IsLegalWiderType = true;
875 if (IsLegalWiderType) continue;
880 unsigned NumIntermediates;
881 NumRegistersForVT[i] =
882 getVectorTypeBreakdownMVT(VT, IntermediateVT, NumIntermediates,
884 RegisterTypeForVT[i] = RegisterVT;
886 EVT NVT = VT.getPow2VectorType();
888 // Type is already a power of 2. The default action is to split.
889 TransformToType[i] = MVT::Other;
890 unsigned NumElts = VT.getVectorNumElements();
891 ValueTypeActions.setTypeAction(VT,
892 NumElts > 1 ? TypeSplitVector : TypeScalarizeVector);
894 TransformToType[i] = NVT;
895 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
899 // Determine the 'representative' register class for each value type.
900 // An representative register class is the largest (meaning one which is
901 // not a sub-register class / subreg register class) legal register class for
902 // a group of value types. For example, on i386, i8, i16, and i32
903 // representative would be GR32; while on x86_64 it's GR64.
904 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
905 const TargetRegisterClass* RRC;
907 tie(RRC, Cost) = findRepresentativeClass((MVT::SimpleValueType)i);
908 RepRegClassForVT[i] = RRC;
909 RepRegClassCostForVT[i] = Cost;
913 const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
918 EVT TargetLowering::getSetCCResultType(EVT VT) const {
919 assert(!VT.isVector() && "No default SetCC type for vectors!");
920 return PointerTy.SimpleTy;
923 MVT::SimpleValueType TargetLowering::getCmpLibcallReturnType() const {
924 return MVT::i32; // return the default value
927 /// getVectorTypeBreakdown - Vector types are broken down into some number of
928 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
929 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
930 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
932 /// This method returns the number of registers needed, and the VT for each
933 /// register. It also returns the VT and quantity of the intermediate values
934 /// before they are promoted/expanded.
936 unsigned TargetLowering::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
938 unsigned &NumIntermediates,
939 EVT &RegisterVT) const {
940 unsigned NumElts = VT.getVectorNumElements();
942 // If there is a wider vector type with the same element type as this one,
943 // we should widen to that legal vector type. This handles things like
944 // <2 x float> -> <4 x float>.
945 if (NumElts != 1 && getTypeAction(Context, VT) == TypeWidenVector) {
946 RegisterVT = getTypeToTransformTo(Context, VT);
947 if (isTypeLegal(RegisterVT)) {
948 IntermediateVT = RegisterVT;
949 NumIntermediates = 1;
954 // Figure out the right, legal destination reg to copy into.
955 EVT EltTy = VT.getVectorElementType();
957 unsigned NumVectorRegs = 1;
959 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
960 // could break down into LHS/RHS like LegalizeDAG does.
961 if (!isPowerOf2_32(NumElts)) {
962 NumVectorRegs = NumElts;
966 // Divide the input until we get to a supported size. This will always
967 // end with a scalar if the target doesn't support vectors.
968 while (NumElts > 1 && !isTypeLegal(
969 EVT::getVectorVT(Context, EltTy, NumElts))) {
974 NumIntermediates = NumVectorRegs;
976 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
977 if (!isTypeLegal(NewVT))
979 IntermediateVT = NewVT;
981 EVT DestVT = getRegisterType(Context, NewVT);
983 unsigned NewVTSize = NewVT.getSizeInBits();
985 // Convert sizes such as i33 to i64.
986 if (!isPowerOf2_32(NewVTSize))
987 NewVTSize = NextPowerOf2(NewVTSize);
989 if (DestVT.bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
990 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
992 // Otherwise, promotion or legal types use the same number of registers as
993 // the vector decimated to the appropriate level.
994 return NumVectorRegs;
997 /// Get the EVTs and ArgFlags collections that represent the legalized return
998 /// type of the given function. This does not require a DAG or a return value,
999 /// and is suitable for use before any DAGs for the function are constructed.
1000 /// TODO: Move this out of TargetLowering.cpp.
1001 void llvm::GetReturnInfo(Type* ReturnType, Attributes attr,
1002 SmallVectorImpl<ISD::OutputArg> &Outs,
1003 const TargetLowering &TLI,
1004 SmallVectorImpl<uint64_t> *Offsets) {
1005 SmallVector<EVT, 4> ValueVTs;
1006 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1007 unsigned NumValues = ValueVTs.size();
1008 if (NumValues == 0) return;
1009 unsigned Offset = 0;
1011 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1012 EVT VT = ValueVTs[j];
1013 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1015 if (attr & Attribute::SExt)
1016 ExtendKind = ISD::SIGN_EXTEND;
1017 else if (attr & Attribute::ZExt)
1018 ExtendKind = ISD::ZERO_EXTEND;
1020 // FIXME: C calling convention requires the return type to be promoted to
1021 // at least 32-bit. But this is not necessary for non-C calling
1022 // conventions. The frontend should mark functions whose return values
1023 // require promoting with signext or zeroext attributes.
1024 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1025 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1026 if (VT.bitsLT(MinVT))
1030 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1031 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1032 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1033 PartVT.getTypeForEVT(ReturnType->getContext()));
1035 // 'inreg' on function refers to return value
1036 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1037 if (attr & Attribute::InReg)
1040 // Propagate extension type if any
1041 if (attr & Attribute::SExt)
1043 else if (attr & Attribute::ZExt)
1046 for (unsigned i = 0; i < NumParts; ++i) {
1047 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
1049 Offsets->push_back(Offset);
1056 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1057 /// function arguments in the caller parameter area. This is the actual
1058 /// alignment, not its logarithm.
1059 unsigned TargetLowering::getByValTypeAlignment(Type *Ty) const {
1060 return TD->getCallFrameTypeAlignment(Ty);
1063 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1064 /// current function. The returned value is a member of the
1065 /// MachineJumpTableInfo::JTEntryKind enum.
1066 unsigned TargetLowering::getJumpTableEncoding() const {
1067 // In non-pic modes, just use the address of a block.
1068 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1069 return MachineJumpTableInfo::EK_BlockAddress;
1071 // In PIC mode, if the target supports a GPRel32 directive, use it.
1072 if (getTargetMachine().getMCAsmInfo()->getGPRel32Directive() != 0)
1073 return MachineJumpTableInfo::EK_GPRel32BlockAddress;
1075 // Otherwise, use a label difference.
1076 return MachineJumpTableInfo::EK_LabelDifference32;
1079 SDValue TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1080 SelectionDAG &DAG) const {
1081 // If our PIC model is GP relative, use the global offset table as the base.
1082 if (getJumpTableEncoding() == MachineJumpTableInfo::EK_GPRel32BlockAddress)
1083 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1087 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1088 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1091 TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1092 unsigned JTI,MCContext &Ctx) const{
1093 // The normal PIC reloc base is the label at the start of the jump table.
1094 return MCSymbolRefExpr::Create(MF->getJTISymbol(JTI, Ctx), Ctx);
1098 TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1099 // Assume that everything is safe in static mode.
1100 if (getTargetMachine().getRelocationModel() == Reloc::Static)
1103 // In dynamic-no-pic mode, assume that known defined values are safe.
1104 if (getTargetMachine().getRelocationModel() == Reloc::DynamicNoPIC &&
1106 !GA->getGlobal()->isDeclaration() &&
1107 !GA->getGlobal()->isWeakForLinker())
1110 // Otherwise assume nothing is safe.
1114 //===----------------------------------------------------------------------===//
1115 // Optimization Methods
1116 //===----------------------------------------------------------------------===//
1118 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1119 /// specified instruction is a constant integer. If so, check to see if there
1120 /// are any bits set in the constant that are not demanded. If so, shrink the
1121 /// constant and return true.
1122 bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
1123 const APInt &Demanded) {
1124 DebugLoc dl = Op.getDebugLoc();
1126 // FIXME: ISD::SELECT, ISD::SELECT_CC
1127 switch (Op.getOpcode()) {
1132 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
1133 if (!C) return false;
1135 if (Op.getOpcode() == ISD::XOR &&
1136 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
1139 // if we can expand it to have all bits set, do it
1140 if (C->getAPIntValue().intersects(~Demanded)) {
1141 EVT VT = Op.getValueType();
1142 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
1143 DAG.getConstant(Demanded &
1146 return CombineTo(Op, New);
1156 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1157 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1158 /// cast, but it could be generalized for targets with other types of
1159 /// implicit widening casts.
1161 TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op,
1163 const APInt &Demanded,
1165 assert(Op.getNumOperands() == 2 &&
1166 "ShrinkDemandedOp only supports binary operators!");
1167 assert(Op.getNode()->getNumValues() == 1 &&
1168 "ShrinkDemandedOp only supports nodes with one result!");
1170 // Don't do this if the node has another user, which may require the
1172 if (!Op.getNode()->hasOneUse())
1175 // Search for the smallest integer type with free casts to and from
1176 // Op's type. For expedience, just check power-of-2 integer types.
1177 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1178 unsigned SmallVTBits = BitWidth - Demanded.countLeadingZeros();
1179 if (!isPowerOf2_32(SmallVTBits))
1180 SmallVTBits = NextPowerOf2(SmallVTBits);
1181 for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
1182 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
1183 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
1184 TLI.isZExtFree(SmallVT, Op.getValueType())) {
1185 // We found a type with free casts.
1186 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT,
1187 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1188 Op.getNode()->getOperand(0)),
1189 DAG.getNode(ISD::TRUNCATE, dl, SmallVT,
1190 Op.getNode()->getOperand(1)));
1191 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X);
1192 return CombineTo(Op, Z);
1198 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1199 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1200 /// use this information to simplify Op, create a new simplified DAG node and
1201 /// return true, returning the original and new nodes in Old and New. Otherwise,
1202 /// analyze the expression and return a mask of KnownOne and KnownZero bits for
1203 /// the expression (used to simplify the caller). The KnownZero/One bits may
1204 /// only be accurate for those bits in the DemandedMask.
1205 bool TargetLowering::SimplifyDemandedBits(SDValue Op,
1206 const APInt &DemandedMask,
1209 TargetLoweringOpt &TLO,
1210 unsigned Depth) const {
1211 unsigned BitWidth = DemandedMask.getBitWidth();
1212 assert(Op.getValueType().getScalarType().getSizeInBits() == BitWidth &&
1213 "Mask size mismatches value type size!");
1214 APInt NewMask = DemandedMask;
1215 DebugLoc dl = Op.getDebugLoc();
1217 // Don't know anything.
1218 KnownZero = KnownOne = APInt(BitWidth, 0);
1220 // Other users may use these bits.
1221 if (!Op.getNode()->hasOneUse()) {
1223 // If not at the root, Just compute the KnownZero/KnownOne bits to
1224 // simplify things downstream.
1225 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1228 // If this is the root being simplified, allow it to have multiple uses,
1229 // just set the NewMask to all bits.
1230 NewMask = APInt::getAllOnesValue(BitWidth);
1231 } else if (DemandedMask == 0) {
1232 // Not demanding any bits from Op.
1233 if (Op.getOpcode() != ISD::UNDEF)
1234 return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType()));
1236 } else if (Depth == 6) { // Limit search depth.
1240 APInt KnownZero2, KnownOne2, KnownZeroOut, KnownOneOut;
1241 switch (Op.getOpcode()) {
1243 // We know all of the bits for a constant!
1244 KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
1245 KnownZero = ~KnownOne;
1246 return false; // Don't fall through, will infinitely loop.
1248 // If the RHS is a constant, check to see if the LHS would be zero without
1249 // using the bits from the RHS. Below, we use knowledge about the RHS to
1250 // simplify the LHS, here we're using information from the LHS to simplify
1252 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1253 APInt LHSZero, LHSOne;
1254 // Do not increment Depth here; that can cause an infinite loop.
1255 TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
1256 // If the LHS already has zeros where RHSC does, this and is dead.
1257 if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
1258 return TLO.CombineTo(Op, Op.getOperand(0));
1259 // If any of the set bits in the RHS are known zero on the LHS, shrink
1261 if (TLO.ShrinkDemandedConstant(Op, ~LHSZero & NewMask))
1265 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1266 KnownOne, TLO, Depth+1))
1268 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1269 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask,
1270 KnownZero2, KnownOne2, TLO, Depth+1))
1272 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1274 // If all of the demanded bits are known one on one side, return the other.
1275 // These bits cannot contribute to the result of the 'and'.
1276 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1277 return TLO.CombineTo(Op, Op.getOperand(0));
1278 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1279 return TLO.CombineTo(Op, Op.getOperand(1));
1280 // If all of the demanded bits in the inputs are known zeros, return zero.
1281 if ((NewMask & (KnownZero|KnownZero2)) == NewMask)
1282 return TLO.CombineTo(Op, TLO.DAG.getConstant(0, Op.getValueType()));
1283 // If the RHS is a constant, see if we can simplify it.
1284 if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask))
1286 // If the operation can be done in a smaller type, do so.
1287 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1290 // Output known-1 bits are only known if set in both the LHS & RHS.
1291 KnownOne &= KnownOne2;
1292 // Output known-0 are known to be clear if zero in either the LHS | RHS.
1293 KnownZero |= KnownZero2;
1296 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1297 KnownOne, TLO, Depth+1))
1299 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1300 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask,
1301 KnownZero2, KnownOne2, TLO, Depth+1))
1303 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1305 // If all of the demanded bits are known zero on one side, return the other.
1306 // These bits cannot contribute to the result of the 'or'.
1307 if ((NewMask & ~KnownOne2 & KnownZero) == (~KnownOne2 & NewMask))
1308 return TLO.CombineTo(Op, Op.getOperand(0));
1309 if ((NewMask & ~KnownOne & KnownZero2) == (~KnownOne & NewMask))
1310 return TLO.CombineTo(Op, Op.getOperand(1));
1311 // If all of the potentially set bits on one side are known to be set on
1312 // the other side, just use the 'other' side.
1313 if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask))
1314 return TLO.CombineTo(Op, Op.getOperand(0));
1315 if ((NewMask & ~KnownZero2 & KnownOne) == (~KnownZero2 & NewMask))
1316 return TLO.CombineTo(Op, Op.getOperand(1));
1317 // If the RHS is a constant, see if we can simplify it.
1318 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1320 // If the operation can be done in a smaller type, do so.
1321 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1324 // Output known-0 bits are only known if clear in both the LHS & RHS.
1325 KnownZero &= KnownZero2;
1326 // Output known-1 are known to be set if set in either the LHS | RHS.
1327 KnownOne |= KnownOne2;
1330 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero,
1331 KnownOne, TLO, Depth+1))
1333 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1334 if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2,
1335 KnownOne2, TLO, Depth+1))
1337 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1339 // If all of the demanded bits are known zero on one side, return the other.
1340 // These bits cannot contribute to the result of the 'xor'.
1341 if ((KnownZero & NewMask) == NewMask)
1342 return TLO.CombineTo(Op, Op.getOperand(0));
1343 if ((KnownZero2 & NewMask) == NewMask)
1344 return TLO.CombineTo(Op, Op.getOperand(1));
1345 // If the operation can be done in a smaller type, do so.
1346 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1349 // If all of the unknown bits are known to be zero on one side or the other
1350 // (but not both) turn this into an *inclusive* or.
1351 // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
1352 if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
1353 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
1357 // Output known-0 bits are known if clear or set in both the LHS & RHS.
1358 KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2);
1359 // Output known-1 are known to be set if set in only one of the LHS, RHS.
1360 KnownOneOut = (KnownZero & KnownOne2) | (KnownOne & KnownZero2);
1362 // If all of the demanded bits on one side are known, and all of the set
1363 // bits on that side are also known to be set on the other side, turn this
1364 // into an AND, as we know the bits will be cleared.
1365 // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
1366 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
1367 if ((KnownOne & KnownOne2) == KnownOne) {
1368 EVT VT = Op.getValueType();
1369 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
1370 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
1371 Op.getOperand(0), ANDC));
1375 // If the RHS is a constant, see if we can simplify it.
1376 // for XOR, we prefer to force bits to 1 if they will make a -1.
1377 // if we can't force bits, try to shrink constant
1378 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1379 APInt Expanded = C->getAPIntValue() | (~NewMask);
1380 // if we can expand it to have all bits set, do it
1381 if (Expanded.isAllOnesValue()) {
1382 if (Expanded != C->getAPIntValue()) {
1383 EVT VT = Op.getValueType();
1384 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
1385 TLO.DAG.getConstant(Expanded, VT));
1386 return TLO.CombineTo(Op, New);
1388 // if it already has all the bits set, nothing to change
1389 // but don't shrink either!
1390 } else if (TLO.ShrinkDemandedConstant(Op, NewMask)) {
1395 KnownZero = KnownZeroOut;
1396 KnownOne = KnownOneOut;
1399 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero,
1400 KnownOne, TLO, Depth+1))
1402 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2,
1403 KnownOne2, TLO, Depth+1))
1405 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1406 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1408 // If the operands are constants, see if we can simplify them.
1409 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1412 // Only known if known in both the LHS and RHS.
1413 KnownOne &= KnownOne2;
1414 KnownZero &= KnownZero2;
1416 case ISD::SELECT_CC:
1417 if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero,
1418 KnownOne, TLO, Depth+1))
1420 if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2,
1421 KnownOne2, TLO, Depth+1))
1423 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1424 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
1426 // If the operands are constants, see if we can simplify them.
1427 if (TLO.ShrinkDemandedConstant(Op, NewMask))
1430 // Only known if known in both the LHS and RHS.
1431 KnownOne &= KnownOne2;
1432 KnownZero &= KnownZero2;
1435 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1436 unsigned ShAmt = SA->getZExtValue();
1437 SDValue InOp = Op.getOperand(0);
1439 // If the shift count is an invalid immediate, don't do anything.
1440 if (ShAmt >= BitWidth)
1443 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
1444 // single shift. We can do this if the bottom bits (which are shifted
1445 // out) are never demanded.
1446 if (InOp.getOpcode() == ISD::SRL &&
1447 isa<ConstantSDNode>(InOp.getOperand(1))) {
1448 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
1449 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1450 unsigned Opc = ISD::SHL;
1451 int Diff = ShAmt-C1;
1458 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1459 EVT VT = Op.getValueType();
1460 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1461 InOp.getOperand(0), NewSA));
1465 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
1466 KnownZero, KnownOne, TLO, Depth+1))
1469 // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
1470 // are not demanded. This will likely allow the anyext to be folded away.
1471 if (InOp.getNode()->getOpcode() == ISD::ANY_EXTEND) {
1472 SDValue InnerOp = InOp.getNode()->getOperand(0);
1473 EVT InnerVT = InnerOp.getValueType();
1474 unsigned InnerBits = InnerVT.getSizeInBits();
1475 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
1476 isTypeDesirableForOp(ISD::SHL, InnerVT)) {
1477 EVT ShTy = getShiftAmountTy(InnerVT);
1478 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
1481 TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp,
1482 TLO.DAG.getConstant(ShAmt, ShTy));
1485 TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(),
1490 KnownZero <<= SA->getZExtValue();
1491 KnownOne <<= SA->getZExtValue();
1492 // low bits known zero.
1493 KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue());
1497 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1498 EVT VT = Op.getValueType();
1499 unsigned ShAmt = SA->getZExtValue();
1500 unsigned VTSize = VT.getSizeInBits();
1501 SDValue InOp = Op.getOperand(0);
1503 // If the shift count is an invalid immediate, don't do anything.
1504 if (ShAmt >= BitWidth)
1507 // If this is ((X << C1) >>u ShAmt), see if we can simplify this into a
1508 // single shift. We can do this if the top bits (which are shifted out)
1509 // are never demanded.
1510 if (InOp.getOpcode() == ISD::SHL &&
1511 isa<ConstantSDNode>(InOp.getOperand(1))) {
1512 if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
1513 unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
1514 unsigned Opc = ISD::SRL;
1515 int Diff = ShAmt-C1;
1522 TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
1523 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
1524 InOp.getOperand(0), NewSA));
1528 // Compute the new bits that are at the top now.
1529 if (SimplifyDemandedBits(InOp, (NewMask << ShAmt),
1530 KnownZero, KnownOne, TLO, Depth+1))
1532 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1533 KnownZero = KnownZero.lshr(ShAmt);
1534 KnownOne = KnownOne.lshr(ShAmt);
1536 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1537 KnownZero |= HighBits; // High bits known zero.
1541 // If this is an arithmetic shift right and only the low-bit is set, we can
1542 // always convert this into a logical shr, even if the shift amount is
1543 // variable. The low bit of the shift cannot be an input sign bit unless
1544 // the shift amount is >= the size of the datatype, which is undefined.
1546 return TLO.CombineTo(Op,
1547 TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
1548 Op.getOperand(0), Op.getOperand(1)));
1550 if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1551 EVT VT = Op.getValueType();
1552 unsigned ShAmt = SA->getZExtValue();
1554 // If the shift count is an invalid immediate, don't do anything.
1555 if (ShAmt >= BitWidth)
1558 APInt InDemandedMask = (NewMask << ShAmt);
1560 // If any of the demanded bits are produced by the sign extension, we also
1561 // demand the input sign bit.
1562 APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
1563 if (HighBits.intersects(NewMask))
1564 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
1566 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask,
1567 KnownZero, KnownOne, TLO, Depth+1))
1569 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1570 KnownZero = KnownZero.lshr(ShAmt);
1571 KnownOne = KnownOne.lshr(ShAmt);
1573 // Handle the sign bit, adjusted to where it is now in the mask.
1574 APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt);
1576 // If the input sign bit is known to be zero, or if none of the top bits
1577 // are demanded, turn this into an unsigned shift right.
1578 if (KnownZero.intersects(SignBit) || (HighBits & ~NewMask) == HighBits) {
1579 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
1582 } else if (KnownOne.intersects(SignBit)) { // New bits are known one.
1583 KnownOne |= HighBits;
1587 case ISD::SIGN_EXTEND_INREG: {
1588 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1590 APInt MsbMask = APInt::getHighBitsSet(BitWidth, 1);
1591 // If we only care about the highest bit, don't bother shifting right.
1592 if (MsbMask == DemandedMask) {
1593 unsigned ShAmt = ExVT.getScalarType().getSizeInBits();
1594 SDValue InOp = Op.getOperand(0);
1596 // Compute the correct shift amount type, which must be getShiftAmountTy
1597 // for scalar types after legalization.
1598 EVT ShiftAmtTy = Op.getValueType();
1599 if (TLO.LegalTypes() && !ShiftAmtTy.isVector())
1600 ShiftAmtTy = getShiftAmountTy(ShiftAmtTy);
1602 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy);
1603 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1604 Op.getValueType(), InOp, ShiftAmt));
1607 // Sign extension. Compute the demanded bits in the result that are not
1608 // present in the input.
1610 APInt::getHighBitsSet(BitWidth,
1611 BitWidth - ExVT.getScalarType().getSizeInBits());
1613 // If none of the extended bits are demanded, eliminate the sextinreg.
1614 if ((NewBits & NewMask) == 0)
1615 return TLO.CombineTo(Op, Op.getOperand(0));
1618 APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth);
1619 APInt InputDemandedBits =
1620 APInt::getLowBitsSet(BitWidth,
1621 ExVT.getScalarType().getSizeInBits()) &
1624 // Since the sign extended bits are demanded, we know that the sign
1626 InputDemandedBits |= InSignBit;
1628 if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits,
1629 KnownZero, KnownOne, TLO, Depth+1))
1631 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1633 // If the sign bit of the input is known set or clear, then we know the
1634 // top bits of the result.
1636 // If the input sign bit is known zero, convert this into a zero extension.
1637 if (KnownZero.intersects(InSignBit))
1638 return TLO.CombineTo(Op,
1639 TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT));
1641 if (KnownOne.intersects(InSignBit)) { // Input sign bit known set
1642 KnownOne |= NewBits;
1643 KnownZero &= ~NewBits;
1644 } else { // Input sign bit unknown
1645 KnownZero &= ~NewBits;
1646 KnownOne &= ~NewBits;
1650 case ISD::ZERO_EXTEND: {
1651 unsigned OperandBitWidth =
1652 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1653 APInt InMask = NewMask.trunc(OperandBitWidth);
1655 // If none of the top bits are demanded, convert this into an any_extend.
1657 APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask;
1658 if (!NewBits.intersects(NewMask))
1659 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1663 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1664 KnownZero, KnownOne, TLO, Depth+1))
1666 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1667 KnownZero = KnownZero.zext(BitWidth);
1668 KnownOne = KnownOne.zext(BitWidth);
1669 KnownZero |= NewBits;
1672 case ISD::SIGN_EXTEND: {
1673 EVT InVT = Op.getOperand(0).getValueType();
1674 unsigned InBits = InVT.getScalarType().getSizeInBits();
1675 APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
1676 APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
1677 APInt NewBits = ~InMask & NewMask;
1679 // If none of the top bits are demanded, convert this into an any_extend.
1681 return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl,
1685 // Since some of the sign extended bits are demanded, we know that the sign
1687 APInt InDemandedBits = InMask & NewMask;
1688 InDemandedBits |= InSignBit;
1689 InDemandedBits = InDemandedBits.trunc(InBits);
1691 if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero,
1692 KnownOne, TLO, Depth+1))
1694 KnownZero = KnownZero.zext(BitWidth);
1695 KnownOne = KnownOne.zext(BitWidth);
1697 // If the sign bit is known zero, convert this to a zero extend.
1698 if (KnownZero.intersects(InSignBit))
1699 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl,
1703 // If the sign bit is known one, the top bits match.
1704 if (KnownOne.intersects(InSignBit)) {
1705 KnownOne |= NewBits;
1706 assert((KnownZero & NewBits) == 0);
1707 } else { // Otherwise, top bits aren't known.
1708 assert((KnownOne & NewBits) == 0);
1709 assert((KnownZero & NewBits) == 0);
1713 case ISD::ANY_EXTEND: {
1714 unsigned OperandBitWidth =
1715 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1716 APInt InMask = NewMask.trunc(OperandBitWidth);
1717 if (SimplifyDemandedBits(Op.getOperand(0), InMask,
1718 KnownZero, KnownOne, TLO, Depth+1))
1720 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1721 KnownZero = KnownZero.zext(BitWidth);
1722 KnownOne = KnownOne.zext(BitWidth);
1725 case ISD::TRUNCATE: {
1726 // Simplify the input, using demanded bit information, and compute the known
1727 // zero/one bits live out.
1728 unsigned OperandBitWidth =
1729 Op.getOperand(0).getValueType().getScalarType().getSizeInBits();
1730 APInt TruncMask = NewMask.zext(OperandBitWidth);
1731 if (SimplifyDemandedBits(Op.getOperand(0), TruncMask,
1732 KnownZero, KnownOne, TLO, Depth+1))
1734 KnownZero = KnownZero.trunc(BitWidth);
1735 KnownOne = KnownOne.trunc(BitWidth);
1737 // If the input is only used by this truncate, see if we can shrink it based
1738 // on the known demanded bits.
1739 if (Op.getOperand(0).getNode()->hasOneUse()) {
1740 SDValue In = Op.getOperand(0);
1741 switch (In.getOpcode()) {
1744 // Shrink SRL by a constant if none of the high bits shifted in are
1746 if (TLO.LegalTypes() &&
1747 !isTypeDesirableForOp(ISD::SRL, Op.getValueType()))
1748 // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
1751 ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
1754 SDValue Shift = In.getOperand(1);
1755 if (TLO.LegalTypes()) {
1756 uint64_t ShVal = ShAmt->getZExtValue();
1758 TLO.DAG.getConstant(ShVal, getShiftAmountTy(Op.getValueType()));
1761 APInt HighBits = APInt::getHighBitsSet(OperandBitWidth,
1762 OperandBitWidth - BitWidth);
1763 HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth);
1765 if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) {
1766 // None of the shifted in bits are needed. Add a truncate of the
1767 // shift input, then shift it.
1768 SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl,
1771 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl,
1780 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1783 case ISD::AssertZext: {
1784 // AssertZext demands all of the high bits, plus any of the low bits
1785 // demanded by its users.
1786 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1787 APInt InMask = APInt::getLowBitsSet(BitWidth,
1788 VT.getSizeInBits());
1789 if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask,
1790 KnownZero, KnownOne, TLO, Depth+1))
1792 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
1794 KnownZero |= ~InMask & NewMask;
1798 // If this is an FP->Int bitcast and if the sign bit is the only
1799 // thing demanded, turn this into a FGETSIGN.
1800 if (!TLO.LegalOperations() &&
1801 !Op.getValueType().isVector() &&
1802 !Op.getOperand(0).getValueType().isVector() &&
1803 NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) &&
1804 Op.getOperand(0).getValueType().isFloatingPoint()) {
1805 bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType());
1806 bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);
1807 if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple()) {
1808 EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32;
1809 // Make a FGETSIGN + SHL to move the sign bit into the appropriate
1810 // place. We expect the SHL to be eliminated by other optimizations.
1811 SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0));
1812 unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits();
1813 if (!OpVTLegal && OpVTSizeInBits > 32)
1814 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign);
1815 unsigned ShVal = Op.getValueType().getSizeInBits()-1;
1816 SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType());
1817 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl,
1826 // Add, Sub, and Mul don't demand any bits in positions beyond that
1827 // of the highest bit demanded of them.
1828 APInt LoMask = APInt::getLowBitsSet(BitWidth,
1829 BitWidth - NewMask.countLeadingZeros());
1830 if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2,
1831 KnownOne2, TLO, Depth+1))
1833 if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2,
1834 KnownOne2, TLO, Depth+1))
1836 // See if the operation should be performed at a smaller bit width.
1837 if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl))
1842 // Just use ComputeMaskedBits to compute output bits.
1843 TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth);
1847 // If we know the value of all of the demanded bits, return this as a
1849 if ((NewMask & (KnownZero|KnownOne)) == NewMask)
1850 return TLO.CombineTo(Op, TLO.DAG.getConstant(KnownOne, Op.getValueType()));
1855 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
1856 /// in Mask are known to be either zero or one and return them in the
1857 /// KnownZero/KnownOne bitsets.
1858 void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1861 const SelectionDAG &DAG,
1862 unsigned Depth) const {
1863 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1864 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1865 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1866 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1867 "Should use MaskedValueIsZero if you don't know whether Op"
1868 " is a target node!");
1869 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
1872 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1873 /// targets that want to expose additional information about sign bits to the
1875 unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
1876 unsigned Depth) const {
1877 assert((Op.getOpcode() >= ISD::BUILTIN_OP_END ||
1878 Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
1879 Op.getOpcode() == ISD::INTRINSIC_W_CHAIN ||
1880 Op.getOpcode() == ISD::INTRINSIC_VOID) &&
1881 "Should use ComputeNumSignBits if you don't know whether Op"
1882 " is a target node!");
1886 /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
1887 /// one bit set. This differs from ComputeMaskedBits in that it doesn't need to
1888 /// determine which bit is set.
1890 static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
1891 // A left-shift of a constant one will have exactly one bit set, because
1892 // shifting the bit off the end is undefined.
1893 if (Val.getOpcode() == ISD::SHL)
1894 if (ConstantSDNode *C =
1895 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1896 if (C->getAPIntValue() == 1)
1899 // Similarly, a right-shift of a constant sign-bit will have exactly
1901 if (Val.getOpcode() == ISD::SRL)
1902 if (ConstantSDNode *C =
1903 dyn_cast<ConstantSDNode>(Val.getNode()->getOperand(0)))
1904 if (C->getAPIntValue().isSignBit())
1907 // More could be done here, though the above checks are enough
1908 // to handle some common cases.
1910 // Fall back to ComputeMaskedBits to catch other known cases.
1911 EVT OpVT = Val.getValueType();
1912 unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
1913 APInt KnownZero, KnownOne;
1914 DAG.ComputeMaskedBits(Val, KnownZero, KnownOne);
1915 return (KnownZero.countPopulation() == BitWidth - 1) &&
1916 (KnownOne.countPopulation() == 1);
1919 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1920 /// and cc. If it is unable to simplify it, return a null SDValue.
1922 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1923 ISD::CondCode Cond, bool foldBooleans,
1924 DAGCombinerInfo &DCI, DebugLoc dl) const {
1925 SelectionDAG &DAG = DCI.DAG;
1927 // These setcc operations always fold.
1931 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1933 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1936 // Ensure that the constant occurs on the RHS, and fold constant
1938 if (isa<ConstantSDNode>(N0.getNode()))
1939 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1941 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
1942 const APInt &C1 = N1C->getAPIntValue();
1944 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
1945 // equality comparison, then we're just comparing whether X itself is
1947 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
1948 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
1949 N0.getOperand(1).getOpcode() == ISD::Constant) {
1951 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
1952 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
1953 ShAmt == Log2_32(N0.getValueType().getSizeInBits())) {
1954 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
1955 // (srl (ctlz x), 5) == 0 -> X != 0
1956 // (srl (ctlz x), 5) != 1 -> X != 0
1959 // (srl (ctlz x), 5) != 0 -> X == 0
1960 // (srl (ctlz x), 5) == 1 -> X == 0
1963 SDValue Zero = DAG.getConstant(0, N0.getValueType());
1964 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1970 // Look through truncs that don't change the value of a ctpop.
1971 if (N0.hasOneUse() && N0.getOpcode() == ISD::TRUNCATE)
1972 CTPOP = N0.getOperand(0);
1974 if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP &&
1975 (N0 == CTPOP || N0.getValueType().getSizeInBits() >
1976 Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) {
1977 EVT CTVT = CTPOP.getValueType();
1978 SDValue CTOp = CTPOP.getOperand(0);
1980 // (ctpop x) u< 2 -> (x & x-1) == 0
1981 // (ctpop x) u> 1 -> (x & x-1) != 0
1982 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){
1983 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1984 DAG.getConstant(1, CTVT));
1985 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
1986 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE;
1987 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1990 // TODO: (ctpop x) == 1 -> x && (x & x-1) == 0 iff ctpop is illegal.
1993 // (zext x) == C --> x == (trunc C)
1994 if (DCI.isBeforeLegalize() && N0->hasOneUse() &&
1995 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1996 unsigned MinBits = N0.getValueSizeInBits();
1998 if (N0->getOpcode() == ISD::ZERO_EXTEND) {
2000 MinBits = N0->getOperand(0).getValueSizeInBits();
2001 PreZExt = N0->getOperand(0);
2002 } else if (N0->getOpcode() == ISD::AND) {
2003 // DAGCombine turns costly ZExts into ANDs
2004 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
2005 if ((C->getAPIntValue()+1).isPowerOf2()) {
2006 MinBits = C->getAPIntValue().countTrailingOnes();
2007 PreZExt = N0->getOperand(0);
2009 } else if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(N0)) {
2011 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
2012 MinBits = LN0->getMemoryVT().getSizeInBits();
2017 // Make sure we're not loosing bits from the constant.
2018 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
2019 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
2020 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
2021 // Will get folded away.
2022 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MinVT, PreZExt);
2023 SDValue C = DAG.getConstant(C1.trunc(MinBits), MinVT);
2024 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
2029 // If the LHS is '(and load, const)', the RHS is 0,
2030 // the test is for equality or unsigned, and all 1 bits of the const are
2031 // in the same partial word, see if we can shorten the load.
2032 if (DCI.isBeforeLegalize() &&
2033 N0.getOpcode() == ISD::AND && C1 == 0 &&
2034 N0.getNode()->hasOneUse() &&
2035 isa<LoadSDNode>(N0.getOperand(0)) &&
2036 N0.getOperand(0).getNode()->hasOneUse() &&
2037 isa<ConstantSDNode>(N0.getOperand(1))) {
2038 LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
2040 unsigned bestWidth = 0, bestOffset = 0;
2041 if (!Lod->isVolatile() && Lod->isUnindexed()) {
2042 unsigned origWidth = N0.getValueType().getSizeInBits();
2043 unsigned maskWidth = origWidth;
2044 // We can narrow (e.g.) 16-bit extending loads on 32-bit target to
2045 // 8 bits, but have to be careful...
2046 if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
2047 origWidth = Lod->getMemoryVT().getSizeInBits();
2049 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2050 for (unsigned width = origWidth / 2; width>=8; width /= 2) {
2051 APInt newMask = APInt::getLowBitsSet(maskWidth, width);
2052 for (unsigned offset=0; offset<origWidth/width; offset++) {
2053 if ((newMask & Mask) == Mask) {
2054 if (!TD->isLittleEndian())
2055 bestOffset = (origWidth/width - offset - 1) * (width/8);
2057 bestOffset = (uint64_t)offset * (width/8);
2058 bestMask = Mask.lshr(offset * (width/8) * 8);
2062 newMask = newMask << width;
2067 EVT newVT = EVT::getIntegerVT(*DAG.getContext(), bestWidth);
2068 if (newVT.isRound()) {
2069 EVT PtrType = Lod->getOperand(1).getValueType();
2070 SDValue Ptr = Lod->getBasePtr();
2071 if (bestOffset != 0)
2072 Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
2073 DAG.getConstant(bestOffset, PtrType));
2074 unsigned NewAlign = MinAlign(Lod->getAlignment(), bestOffset);
2075 SDValue NewLoad = DAG.getLoad(newVT, dl, Lod->getChain(), Ptr,
2076 Lod->getPointerInfo().getWithOffset(bestOffset),
2077 false, false, false, NewAlign);
2078 return DAG.getSetCC(dl, VT,
2079 DAG.getNode(ISD::AND, dl, newVT, NewLoad,
2080 DAG.getConstant(bestMask.trunc(bestWidth),
2082 DAG.getConstant(0LL, newVT), Cond);
2087 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2088 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2089 unsigned InSize = N0.getOperand(0).getValueType().getSizeInBits();
2091 // If the comparison constant has bits in the upper part, the
2092 // zero-extended value could never match.
2093 if (C1.intersects(APInt::getHighBitsSet(C1.getBitWidth(),
2094 C1.getBitWidth() - InSize))) {
2098 case ISD::SETEQ: return DAG.getConstant(0, VT);
2101 case ISD::SETNE: return DAG.getConstant(1, VT);
2104 // True if the sign bit of C1 is set.
2105 return DAG.getConstant(C1.isNegative(), VT);
2108 // True if the sign bit of C1 isn't set.
2109 return DAG.getConstant(C1.isNonNegative(), VT);
2115 // Otherwise, we can perform the comparison with the low bits.
2123 EVT newVT = N0.getOperand(0).getValueType();
2124 if (DCI.isBeforeLegalizeOps() ||
2125 (isOperationLegal(ISD::SETCC, newVT) &&
2126 getCondCodeAction(Cond, newVT)==Legal))
2127 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2128 DAG.getConstant(C1.trunc(InSize), newVT),
2133 break; // todo, be more careful with signed comparisons
2135 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2136 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2137 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2138 unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
2139 EVT ExtDstTy = N0.getValueType();
2140 unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
2142 // If the constant doesn't fit into the number of bits for the source of
2143 // the sign extension, it is impossible for both sides to be equal.
2144 if (C1.getMinSignedBits() > ExtSrcTyBits)
2145 return DAG.getConstant(Cond == ISD::SETNE, VT);
2148 EVT Op0Ty = N0.getOperand(0).getValueType();
2149 if (Op0Ty == ExtSrcTy) {
2150 ZextOp = N0.getOperand(0);
2152 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits);
2153 ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0),
2154 DAG.getConstant(Imm, Op0Ty));
2156 if (!DCI.isCalledByLegalizer())
2157 DCI.AddToWorklist(ZextOp.getNode());
2158 // Otherwise, make this a use of a zext.
2159 return DAG.getSetCC(dl, VT, ZextOp,
2160 DAG.getConstant(C1 & APInt::getLowBitsSet(
2165 } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) &&
2166 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2167 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
2168 if (N0.getOpcode() == ISD::SETCC &&
2169 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
2170 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1);
2172 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
2173 // Invert the condition.
2174 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
2175 CC = ISD::getSetCCInverse(CC,
2176 N0.getOperand(0).getValueType().isInteger());
2177 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
2180 if ((N0.getOpcode() == ISD::XOR ||
2181 (N0.getOpcode() == ISD::AND &&
2182 N0.getOperand(0).getOpcode() == ISD::XOR &&
2183 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2184 isa<ConstantSDNode>(N0.getOperand(1)) &&
2185 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
2186 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
2187 // can only do this if the top bits are known zero.
2188 unsigned BitWidth = N0.getValueSizeInBits();
2189 if (DAG.MaskedValueIsZero(N0,
2190 APInt::getHighBitsSet(BitWidth,
2192 // Okay, get the un-inverted input value.
2194 if (N0.getOpcode() == ISD::XOR)
2195 Val = N0.getOperand(0);
2197 assert(N0.getOpcode() == ISD::AND &&
2198 N0.getOperand(0).getOpcode() == ISD::XOR);
2199 // ((X^1)&1)^1 -> X & 1
2200 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(),
2201 N0.getOperand(0).getOperand(0),
2205 return DAG.getSetCC(dl, VT, Val, N1,
2206 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2208 } else if (N1C->getAPIntValue() == 1 &&
2210 getBooleanContents(false) == ZeroOrOneBooleanContent)) {
2212 if (Op0.getOpcode() == ISD::TRUNCATE)
2213 Op0 = Op0.getOperand(0);
2215 if ((Op0.getOpcode() == ISD::XOR) &&
2216 Op0.getOperand(0).getOpcode() == ISD::SETCC &&
2217 Op0.getOperand(1).getOpcode() == ISD::SETCC) {
2218 // (xor (setcc), (setcc)) == / != 1 -> (setcc) != / == (setcc)
2219 Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
2220 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
2222 } else if (Op0.getOpcode() == ISD::AND &&
2223 isa<ConstantSDNode>(Op0.getOperand(1)) &&
2224 cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
2225 // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
2226 if (Op0.getValueType().bitsGT(VT))
2227 Op0 = DAG.getNode(ISD::AND, dl, VT,
2228 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
2229 DAG.getConstant(1, VT));
2230 else if (Op0.getValueType().bitsLT(VT))
2231 Op0 = DAG.getNode(ISD::AND, dl, VT,
2232 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
2233 DAG.getConstant(1, VT));
2235 return DAG.getSetCC(dl, VT, Op0,
2236 DAG.getConstant(0, Op0.getValueType()),
2237 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2242 APInt MinVal, MaxVal;
2243 unsigned OperandBitSize = N1C->getValueType(0).getSizeInBits();
2244 if (ISD::isSignedIntSetCC(Cond)) {
2245 MinVal = APInt::getSignedMinValue(OperandBitSize);
2246 MaxVal = APInt::getSignedMaxValue(OperandBitSize);
2248 MinVal = APInt::getMinValue(OperandBitSize);
2249 MaxVal = APInt::getMaxValue(OperandBitSize);
2252 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2253 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2254 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2255 // X >= C0 --> X > (C0-1)
2256 return DAG.getSetCC(dl, VT, N0,
2257 DAG.getConstant(C1-1, N1.getValueType()),
2258 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2261 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2262 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2263 // X <= C0 --> X < (C0+1)
2264 return DAG.getSetCC(dl, VT, N0,
2265 DAG.getConstant(C1+1, N1.getValueType()),
2266 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2269 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2270 return DAG.getConstant(0, VT); // X < MIN --> false
2271 if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal)
2272 return DAG.getConstant(1, VT); // X >= MIN --> true
2273 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal)
2274 return DAG.getConstant(0, VT); // X > MAX --> false
2275 if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal)
2276 return DAG.getConstant(1, VT); // X <= MAX --> true
2278 // Canonicalize setgt X, Min --> setne X, Min
2279 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2280 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2281 // Canonicalize setlt X, Max --> setne X, Max
2282 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2283 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
2285 // If we have setult X, 1, turn it into seteq X, 0
2286 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2287 return DAG.getSetCC(dl, VT, N0,
2288 DAG.getConstant(MinVal, N0.getValueType()),
2290 // If we have setugt X, Max-1, turn it into seteq X, Max
2291 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2292 return DAG.getSetCC(dl, VT, N0,
2293 DAG.getConstant(MaxVal, N0.getValueType()),
2296 // If we have "setcc X, C0", check to see if we can shrink the immediate
2299 // SETUGT X, SINTMAX -> SETLT X, 0
2300 if (Cond == ISD::SETUGT &&
2301 C1 == APInt::getSignedMaxValue(OperandBitSize))
2302 return DAG.getSetCC(dl, VT, N0,
2303 DAG.getConstant(0, N1.getValueType()),
2306 // SETULT X, SINTMIN -> SETGT X, -1
2307 if (Cond == ISD::SETULT &&
2308 C1 == APInt::getSignedMinValue(OperandBitSize)) {
2309 SDValue ConstMinusOne =
2310 DAG.getConstant(APInt::getAllOnesValue(OperandBitSize),
2312 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
2315 // Fold bit comparisons when we can.
2316 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2317 (VT == N0.getValueType() ||
2318 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
2319 N0.getOpcode() == ISD::AND)
2320 if (ConstantSDNode *AndRHS =
2321 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2322 EVT ShiftTy = DCI.isBeforeLegalize() ?
2323 getPointerTy() : getShiftAmountTy(N0.getValueType());
2324 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2325 // Perform the xform if the AND RHS is a single bit.
2326 if (AndRHS->getAPIntValue().isPowerOf2()) {
2327 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2328 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2329 DAG.getConstant(AndRHS->getAPIntValue().logBase2(), ShiftTy)));
2331 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
2332 // (X & 8) == 8 --> (X & 8) >> 3
2333 // Perform the xform if C1 is a single bit.
2334 if (C1.isPowerOf2()) {
2335 return DAG.getNode(ISD::TRUNCATE, dl, VT,
2336 DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0,
2337 DAG.getConstant(C1.logBase2(), ShiftTy)));
2343 if (isa<ConstantFPSDNode>(N0.getNode())) {
2344 // Constant fold or commute setcc.
2345 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
2346 if (O.getNode()) return O;
2347 } else if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
2348 // If the RHS of an FP comparison is a constant, simplify it away in
2350 if (CFP->getValueAPF().isNaN()) {
2351 // If an operand is known to be a nan, we can fold it.
2352 switch (ISD::getUnorderedFlavor(Cond)) {
2353 default: llvm_unreachable("Unknown flavor!");
2354 case 0: // Known false.
2355 return DAG.getConstant(0, VT);
2356 case 1: // Known true.
2357 return DAG.getConstant(1, VT);
2358 case 2: // Undefined.
2359 return DAG.getUNDEF(VT);
2363 // Otherwise, we know the RHS is not a NaN. Simplify the node to drop the
2364 // constant if knowing that the operand is non-nan is enough. We prefer to
2365 // have SETO(x,x) instead of SETO(x, 0.0) because this avoids having to
2367 if (Cond == ISD::SETO || Cond == ISD::SETUO)
2368 return DAG.getSetCC(dl, VT, N0, N0, Cond);
2370 // If the condition is not legal, see if we can find an equivalent one
2372 if (!isCondCodeLegal(Cond, N0.getValueType())) {
2373 // If the comparison was an awkward floating-point == or != and one of
2374 // the comparison operands is infinity or negative infinity, convert the
2375 // condition to a less-awkward <= or >=.
2376 if (CFP->getValueAPF().isInfinity()) {
2377 if (CFP->getValueAPF().isNegative()) {
2378 if (Cond == ISD::SETOEQ &&
2379 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2380 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
2381 if (Cond == ISD::SETUEQ &&
2382 isCondCodeLegal(ISD::SETOLE, N0.getValueType()))
2383 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
2384 if (Cond == ISD::SETUNE &&
2385 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2386 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
2387 if (Cond == ISD::SETONE &&
2388 isCondCodeLegal(ISD::SETUGT, N0.getValueType()))
2389 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
2391 if (Cond == ISD::SETOEQ &&
2392 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2393 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
2394 if (Cond == ISD::SETUEQ &&
2395 isCondCodeLegal(ISD::SETOGE, N0.getValueType()))
2396 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
2397 if (Cond == ISD::SETUNE &&
2398 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2399 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
2400 if (Cond == ISD::SETONE &&
2401 isCondCodeLegal(ISD::SETULT, N0.getValueType()))
2402 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
2409 // We can always fold X == X for integer setcc's.
2410 if (N0.getValueType().isInteger()) {
2411 switch (getBooleanContents(N0.getValueType().isVector())) {
2412 case UndefinedBooleanContent:
2413 case ZeroOrOneBooleanContent:
2414 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2415 case ZeroOrNegativeOneBooleanContent:
2416 return DAG.getConstant(ISD::isTrueWhenEqual(Cond) ? -1 : 0, VT);
2419 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2420 if (UOF == 2) // FP operators that are undefined on NaNs.
2421 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2422 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2423 return DAG.getConstant(UOF, VT);
2424 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2425 // if it is not already.
2426 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2427 if (NewCond != Cond)
2428 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
2431 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2432 N0.getValueType().isInteger()) {
2433 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2434 N0.getOpcode() == ISD::XOR) {
2435 // Simplify (X+Y) == (X+Z) --> Y == Z
2436 if (N0.getOpcode() == N1.getOpcode()) {
2437 if (N0.getOperand(0) == N1.getOperand(0))
2438 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
2439 if (N0.getOperand(1) == N1.getOperand(1))
2440 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
2441 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
2442 // If X op Y == Y op X, try other combinations.
2443 if (N0.getOperand(0) == N1.getOperand(1))
2444 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
2446 if (N0.getOperand(1) == N1.getOperand(0))
2447 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
2452 // If RHS is a legal immediate value for a compare instruction, we need
2453 // to be careful about increasing register pressure needlessly.
2454 bool LegalRHSImm = false;
2456 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2457 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2458 // Turn (X+C1) == C2 --> X == C2-C1
2459 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
2460 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2461 DAG.getConstant(RHSC->getAPIntValue()-
2462 LHSR->getAPIntValue(),
2463 N0.getValueType()), Cond);
2466 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2467 if (N0.getOpcode() == ISD::XOR)
2468 // If we know that all of the inverted bits are zero, don't bother
2469 // performing the inversion.
2470 if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
2472 DAG.getSetCC(dl, VT, N0.getOperand(0),
2473 DAG.getConstant(LHSR->getAPIntValue() ^
2474 RHSC->getAPIntValue(),
2479 // Turn (C1-X) == C2 --> X == C1-C2
2480 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2481 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2483 DAG.getSetCC(dl, VT, N0.getOperand(1),
2484 DAG.getConstant(SUBC->getAPIntValue() -
2485 RHSC->getAPIntValue(),
2491 // Could RHSC fold directly into a compare?
2492 if (RHSC->getValueType(0).getSizeInBits() <= 64)
2493 LegalRHSImm = isLegalICmpImmediate(RHSC->getSExtValue());
2496 // Simplify (X+Z) == X --> Z == 0
2497 // Don't do this if X is an immediate that can fold into a cmp
2498 // instruction and X+Z has other uses. It could be an induction variable
2499 // chain, and the transform would increase register pressure.
2500 if (!LegalRHSImm || N0.getNode()->hasOneUse()) {
2501 if (N0.getOperand(0) == N1)
2502 return DAG.getSetCC(dl, VT, N0.getOperand(1),
2503 DAG.getConstant(0, N0.getValueType()), Cond);
2504 if (N0.getOperand(1) == N1) {
2505 if (DAG.isCommutativeBinOp(N0.getOpcode()))
2506 return DAG.getSetCC(dl, VT, N0.getOperand(0),
2507 DAG.getConstant(0, N0.getValueType()), Cond);
2508 else if (N0.getNode()->hasOneUse()) {
2509 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2510 // (Z-X) == X --> Z == X<<1
2511 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N1,
2512 DAG.getConstant(1, getShiftAmountTy(N1.getValueType())));
2513 if (!DCI.isCalledByLegalizer())
2514 DCI.AddToWorklist(SH.getNode());
2515 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
2521 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2522 N1.getOpcode() == ISD::XOR) {
2523 // Simplify X == (X+Z) --> Z == 0
2524 if (N1.getOperand(0) == N0) {
2525 return DAG.getSetCC(dl, VT, N1.getOperand(1),
2526 DAG.getConstant(0, N1.getValueType()), Cond);
2527 } else if (N1.getOperand(1) == N0) {
2528 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
2529 return DAG.getSetCC(dl, VT, N1.getOperand(0),
2530 DAG.getConstant(0, N1.getValueType()), Cond);
2531 } else if (N1.getNode()->hasOneUse()) {
2532 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2533 // X == (Z-X) --> X<<1 == Z
2534 SDValue SH = DAG.getNode(ISD::SHL, dl, N1.getValueType(), N0,
2535 DAG.getConstant(1, getShiftAmountTy(N0.getValueType())));
2536 if (!DCI.isCalledByLegalizer())
2537 DCI.AddToWorklist(SH.getNode());
2538 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
2543 // Simplify x&y == y to x&y != 0 if y has exactly one bit set.
2544 // Note that where y is variable and is known to have at most
2545 // one bit set (for example, if it is z&1) we cannot do this;
2546 // the expressions are not equivalent when y==0.
2547 if (N0.getOpcode() == ISD::AND)
2548 if (N0.getOperand(0) == N1 || N0.getOperand(1) == N1) {
2549 if (ValueHasExactlyOneBitSet(N1, DAG)) {
2550 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2551 SDValue Zero = DAG.getConstant(0, N1.getValueType());
2552 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
2555 if (N1.getOpcode() == ISD::AND)
2556 if (N1.getOperand(0) == N0 || N1.getOperand(1) == N0) {
2557 if (ValueHasExactlyOneBitSet(N0, DAG)) {
2558 Cond = ISD::getSetCCInverse(Cond, /*isInteger=*/true);
2559 SDValue Zero = DAG.getConstant(0, N0.getValueType());
2560 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
2565 // Fold away ALL boolean setcc's.
2567 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2569 default: llvm_unreachable("Unknown integer setcc!");
2570 case ISD::SETEQ: // X == Y -> ~(X^Y)
2571 Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2572 N0 = DAG.getNOT(dl, Temp, MVT::i1);
2573 if (!DCI.isCalledByLegalizer())
2574 DCI.AddToWorklist(Temp.getNode());
2576 case ISD::SETNE: // X != Y --> (X^Y)
2577 N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
2579 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
2580 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
2581 Temp = DAG.getNOT(dl, N0, MVT::i1);
2582 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
2583 if (!DCI.isCalledByLegalizer())
2584 DCI.AddToWorklist(Temp.getNode());
2586 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
2587 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
2588 Temp = DAG.getNOT(dl, N1, MVT::i1);
2589 N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
2590 if (!DCI.isCalledByLegalizer())
2591 DCI.AddToWorklist(Temp.getNode());
2593 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
2594 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
2595 Temp = DAG.getNOT(dl, N0, MVT::i1);
2596 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
2597 if (!DCI.isCalledByLegalizer())
2598 DCI.AddToWorklist(Temp.getNode());
2600 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
2601 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
2602 Temp = DAG.getNOT(dl, N1, MVT::i1);
2603 N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
2606 if (VT != MVT::i1) {
2607 if (!DCI.isCalledByLegalizer())
2608 DCI.AddToWorklist(N0.getNode());
2609 // FIXME: If running after legalize, we probably can't do this.
2610 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
2615 // Could not fold it.
2619 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
2620 /// node is a GlobalAddress + offset.
2621 bool TargetLowering::isGAPlusOffset(SDNode *N, const GlobalValue *&GA,
2622 int64_t &Offset) const {
2623 if (isa<GlobalAddressSDNode>(N)) {
2624 GlobalAddressSDNode *GASD = cast<GlobalAddressSDNode>(N);
2625 GA = GASD->getGlobal();
2626 Offset += GASD->getOffset();
2630 if (N->getOpcode() == ISD::ADD) {
2631 SDValue N1 = N->getOperand(0);
2632 SDValue N2 = N->getOperand(1);
2633 if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
2634 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2);
2636 Offset += V->getSExtValue();
2639 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
2640 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N1);
2642 Offset += V->getSExtValue();
2652 SDValue TargetLowering::
2653 PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
2654 // Default implementation: no optimization.
2658 //===----------------------------------------------------------------------===//
2659 // Inline Assembler Implementation Methods
2660 //===----------------------------------------------------------------------===//
2663 TargetLowering::ConstraintType
2664 TargetLowering::getConstraintType(const std::string &Constraint) const {
2665 if (Constraint.size() == 1) {
2666 switch (Constraint[0]) {
2668 case 'r': return C_RegisterClass;
2670 case 'o': // offsetable
2671 case 'V': // not offsetable
2673 case 'i': // Simple Integer or Relocatable Constant
2674 case 'n': // Simple Integer
2675 case 'E': // Floating Point Constant
2676 case 'F': // Floating Point Constant
2677 case 's': // Relocatable Constant
2678 case 'p': // Address.
2679 case 'X': // Allow ANY value.
2680 case 'I': // Target registers.
2694 if (Constraint.size() > 1 && Constraint[0] == '{' &&
2695 Constraint[Constraint.size()-1] == '}')
2700 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2701 /// with another that has more specific requirements based on the type of the
2702 /// corresponding operand.
2703 const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
2704 if (ConstraintVT.isInteger())
2706 if (ConstraintVT.isFloatingPoint())
2707 return "f"; // works for many targets
2711 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2712 /// vector. If it is invalid, don't add anything to Ops.
2713 void TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
2714 std::string &Constraint,
2715 std::vector<SDValue> &Ops,
2716 SelectionDAG &DAG) const {
2718 if (Constraint.length() > 1) return;
2720 char ConstraintLetter = Constraint[0];
2721 switch (ConstraintLetter) {
2723 case 'X': // Allows any operand; labels (basic block) use this.
2724 if (Op.getOpcode() == ISD::BasicBlock) {
2729 case 'i': // Simple Integer or Relocatable Constant
2730 case 'n': // Simple Integer
2731 case 's': { // Relocatable Constant
2732 // These operands are interested in values of the form (GV+C), where C may
2733 // be folded in as an offset of GV, or it may be explicitly added. Also, it
2734 // is possible and fine if either GV or C are missing.
2735 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2736 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
2738 // If we have "(add GV, C)", pull out GV/C
2739 if (Op.getOpcode() == ISD::ADD) {
2740 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2741 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
2742 if (C == 0 || GA == 0) {
2743 C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
2744 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
2746 if (C == 0 || GA == 0)
2750 // If we find a valid operand, map to the TargetXXX version so that the
2751 // value itself doesn't get selected.
2752 if (GA) { // Either &GV or &GV+C
2753 if (ConstraintLetter != 'n') {
2754 int64_t Offs = GA->getOffset();
2755 if (C) Offs += C->getZExtValue();
2756 Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(),
2757 C ? C->getDebugLoc() : DebugLoc(),
2758 Op.getValueType(), Offs));
2762 if (C) { // just C, no GV.
2763 // Simple constants are not allowed for 's'.
2764 if (ConstraintLetter != 's') {
2765 // gcc prints these as sign extended. Sign extend value to 64 bits
2766 // now; without this it would get ZExt'd later in
2767 // ScheduleDAGSDNodes::EmitNode, which is very generic.
2768 Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
2778 std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
2779 getRegForInlineAsmConstraint(const std::string &Constraint,
2781 if (Constraint[0] != '{')
2782 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
2783 assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
2785 // Remove the braces from around the name.
2786 StringRef RegName(Constraint.data()+1, Constraint.size()-2);
2788 // Figure out which register class contains this reg.
2789 const TargetRegisterInfo *RI = TM.getRegisterInfo();
2790 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2791 E = RI->regclass_end(); RCI != E; ++RCI) {
2792 const TargetRegisterClass *RC = *RCI;
2794 // If none of the value types for this register class are valid, we
2795 // can't use it. For example, 64-bit reg classes on 32-bit targets.
2799 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
2801 if (RegName.equals_lower(RI->getName(*I)))
2802 return std::make_pair(*I, RC);
2806 return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0));
2809 //===----------------------------------------------------------------------===//
2810 // Constraint Selection.
2812 /// isMatchingInputConstraint - Return true of this is an input operand that is
2813 /// a matching constraint like "4".
2814 bool TargetLowering::AsmOperandInfo::isMatchingInputConstraint() const {
2815 assert(!ConstraintCode.empty() && "No known constraint!");
2816 return isdigit(ConstraintCode[0]);
2819 /// getMatchedOperand - If this is an input matching constraint, this method
2820 /// returns the output operand it matches.
2821 unsigned TargetLowering::AsmOperandInfo::getMatchedOperand() const {
2822 assert(!ConstraintCode.empty() && "No known constraint!");
2823 return atoi(ConstraintCode.c_str());
2827 /// ParseConstraints - Split up the constraint string from the inline
2828 /// assembly value into the specific constraints and their prefixes,
2829 /// and also tie in the associated operand values.
2830 /// If this returns an empty vector, and if the constraint string itself
2831 /// isn't empty, there was an error parsing.
2832 TargetLowering::AsmOperandInfoVector TargetLowering::ParseConstraints(
2833 ImmutableCallSite CS) const {
2834 /// ConstraintOperands - Information about all of the constraints.
2835 AsmOperandInfoVector ConstraintOperands;
2836 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
2837 unsigned maCount = 0; // Largest number of multiple alternative constraints.
2839 // Do a prepass over the constraints, canonicalizing them, and building up the
2840 // ConstraintOperands list.
2841 InlineAsm::ConstraintInfoVector
2842 ConstraintInfos = IA->ParseConstraints();
2844 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
2845 unsigned ResNo = 0; // ResNo - The result number of the next output.
2847 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
2848 ConstraintOperands.push_back(AsmOperandInfo(ConstraintInfos[i]));
2849 AsmOperandInfo &OpInfo = ConstraintOperands.back();
2851 // Update multiple alternative constraint count.
2852 if (OpInfo.multipleAlternatives.size() > maCount)
2853 maCount = OpInfo.multipleAlternatives.size();
2855 OpInfo.ConstraintVT = MVT::Other;
2857 // Compute the value type for each operand.
2858 switch (OpInfo.Type) {
2859 case InlineAsm::isOutput:
2860 // Indirect outputs just consume an argument.
2861 if (OpInfo.isIndirect) {
2862 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2866 // The return value of the call is this value. As such, there is no
2867 // corresponding argument.
2868 assert(!CS.getType()->isVoidTy() &&
2870 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
2871 OpInfo.ConstraintVT = getValueType(STy->getElementType(ResNo));
2873 assert(ResNo == 0 && "Asm only has one result!");
2874 OpInfo.ConstraintVT = getValueType(CS.getType());
2878 case InlineAsm::isInput:
2879 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
2881 case InlineAsm::isClobber:
2886 if (OpInfo.CallOperandVal) {
2887 llvm::Type *OpTy = OpInfo.CallOperandVal->getType();
2888 if (OpInfo.isIndirect) {
2889 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
2891 report_fatal_error("Indirect operand for inline asm not a pointer!");
2892 OpTy = PtrTy->getElementType();
2895 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
2896 if (StructType *STy = dyn_cast<StructType>(OpTy))
2897 if (STy->getNumElements() == 1)
2898 OpTy = STy->getElementType(0);
2900 // If OpTy is not a single value, it may be a struct/union that we
2901 // can tile with integers.
2902 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
2903 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
2912 OpInfo.ConstraintVT =
2913 EVT::getEVT(IntegerType::get(OpTy->getContext(), BitSize), true);
2916 } else if (dyn_cast<PointerType>(OpTy)) {
2917 OpInfo.ConstraintVT = MVT::getIntegerVT(8*TD->getPointerSize());
2919 OpInfo.ConstraintVT = EVT::getEVT(OpTy, true);
2924 // If we have multiple alternative constraints, select the best alternative.
2925 if (ConstraintInfos.size()) {
2927 unsigned bestMAIndex = 0;
2928 int bestWeight = -1;
2929 // weight: -1 = invalid match, and 0 = so-so match to 5 = good match.
2932 // Compute the sums of the weights for each alternative, keeping track
2933 // of the best (highest weight) one so far.
2934 for (maIndex = 0; maIndex < maCount; ++maIndex) {
2936 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2937 cIndex != eIndex; ++cIndex) {
2938 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2939 if (OpInfo.Type == InlineAsm::isClobber)
2942 // If this is an output operand with a matching input operand,
2943 // look up the matching input. If their types mismatch, e.g. one
2944 // is an integer, the other is floating point, or their sizes are
2945 // different, flag it as an maCantMatch.
2946 if (OpInfo.hasMatchingInput()) {
2947 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2948 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2949 if ((OpInfo.ConstraintVT.isInteger() !=
2950 Input.ConstraintVT.isInteger()) ||
2951 (OpInfo.ConstraintVT.getSizeInBits() !=
2952 Input.ConstraintVT.getSizeInBits())) {
2953 weightSum = -1; // Can't match.
2958 weight = getMultipleConstraintMatchWeight(OpInfo, maIndex);
2963 weightSum += weight;
2966 if (weightSum > bestWeight) {
2967 bestWeight = weightSum;
2968 bestMAIndex = maIndex;
2972 // Now select chosen alternative in each constraint.
2973 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2974 cIndex != eIndex; ++cIndex) {
2975 AsmOperandInfo& cInfo = ConstraintOperands[cIndex];
2976 if (cInfo.Type == InlineAsm::isClobber)
2978 cInfo.selectAlternative(bestMAIndex);
2983 // Check and hook up tied operands, choose constraint code to use.
2984 for (unsigned cIndex = 0, eIndex = ConstraintOperands.size();
2985 cIndex != eIndex; ++cIndex) {
2986 AsmOperandInfo& OpInfo = ConstraintOperands[cIndex];
2988 // If this is an output operand with a matching input operand, look up the
2989 // matching input. If their types mismatch, e.g. one is an integer, the
2990 // other is floating point, or their sizes are different, flag it as an
2992 if (OpInfo.hasMatchingInput()) {
2993 AsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
2995 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
2996 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
2997 getRegForInlineAsmConstraint(OpInfo.ConstraintCode, OpInfo.ConstraintVT);
2998 std::pair<unsigned, const TargetRegisterClass*> InputRC =
2999 getRegForInlineAsmConstraint(Input.ConstraintCode, Input.ConstraintVT);
3000 if ((OpInfo.ConstraintVT.isInteger() !=
3001 Input.ConstraintVT.isInteger()) ||
3002 (MatchRC.second != InputRC.second)) {
3003 report_fatal_error("Unsupported asm: input constraint"
3004 " with a matching output constraint of"
3005 " incompatible type!");
3012 return ConstraintOperands;
3016 /// getConstraintGenerality - Return an integer indicating how general CT
3018 static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) {
3020 case TargetLowering::C_Other:
3021 case TargetLowering::C_Unknown:
3023 case TargetLowering::C_Register:
3025 case TargetLowering::C_RegisterClass:
3027 case TargetLowering::C_Memory:
3030 llvm_unreachable("Invalid constraint type");
3033 /// Examine constraint type and operand type and determine a weight value.
3034 /// This object must already have been set up with the operand type
3035 /// and the current alternative constraint selected.
3036 TargetLowering::ConstraintWeight
3037 TargetLowering::getMultipleConstraintMatchWeight(
3038 AsmOperandInfo &info, int maIndex) const {
3039 InlineAsm::ConstraintCodeVector *rCodes;
3040 if (maIndex >= (int)info.multipleAlternatives.size())
3041 rCodes = &info.Codes;
3043 rCodes = &info.multipleAlternatives[maIndex].Codes;
3044 ConstraintWeight BestWeight = CW_Invalid;
3046 // Loop over the options, keeping track of the most general one.
3047 for (unsigned i = 0, e = rCodes->size(); i != e; ++i) {
3048 ConstraintWeight weight =
3049 getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str());
3050 if (weight > BestWeight)
3051 BestWeight = weight;
3057 /// Examine constraint type and operand type and determine a weight value.
3058 /// This object must already have been set up with the operand type
3059 /// and the current alternative constraint selected.
3060 TargetLowering::ConstraintWeight
3061 TargetLowering::getSingleConstraintMatchWeight(
3062 AsmOperandInfo &info, const char *constraint) const {
3063 ConstraintWeight weight = CW_Invalid;
3064 Value *CallOperandVal = info.CallOperandVal;
3065 // If we don't have a value, we can't do a match,
3066 // but allow it at the lowest weight.
3067 if (CallOperandVal == NULL)
3069 // Look at the constraint type.
3070 switch (*constraint) {
3071 case 'i': // immediate integer.
3072 case 'n': // immediate integer with a known value.
3073 if (isa<ConstantInt>(CallOperandVal))
3074 weight = CW_Constant;
3076 case 's': // non-explicit intregal immediate.
3077 if (isa<GlobalValue>(CallOperandVal))
3078 weight = CW_Constant;
3080 case 'E': // immediate float if host format.
3081 case 'F': // immediate float.
3082 if (isa<ConstantFP>(CallOperandVal))
3083 weight = CW_Constant;
3085 case '<': // memory operand with autodecrement.
3086 case '>': // memory operand with autoincrement.
3087 case 'm': // memory operand.
3088 case 'o': // offsettable memory operand
3089 case 'V': // non-offsettable memory operand
3092 case 'r': // general register.
3093 case 'g': // general register, memory operand or immediate integer.
3094 // note: Clang converts "g" to "imr".
3095 if (CallOperandVal->getType()->isIntegerTy())
3096 weight = CW_Register;
3098 case 'X': // any operand.
3100 weight = CW_Default;
3106 /// ChooseConstraint - If there are multiple different constraints that we
3107 /// could pick for this operand (e.g. "imr") try to pick the 'best' one.
3108 /// This is somewhat tricky: constraints fall into four classes:
3109 /// Other -> immediates and magic values
3110 /// Register -> one specific register
3111 /// RegisterClass -> a group of regs
3112 /// Memory -> memory
3113 /// Ideally, we would pick the most specific constraint possible: if we have
3114 /// something that fits into a register, we would pick it. The problem here
3115 /// is that if we have something that could either be in a register or in
3116 /// memory that use of the register could cause selection of *other*
3117 /// operands to fail: they might only succeed if we pick memory. Because of
3118 /// this the heuristic we use is:
3120 /// 1) If there is an 'other' constraint, and if the operand is valid for
3121 /// that constraint, use it. This makes us take advantage of 'i'
3122 /// constraints when available.
3123 /// 2) Otherwise, pick the most general constraint present. This prefers
3124 /// 'm' over 'r', for example.
3126 static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo,
3127 const TargetLowering &TLI,
3128 SDValue Op, SelectionDAG *DAG) {
3129 assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options");
3130 unsigned BestIdx = 0;
3131 TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown;
3132 int BestGenerality = -1;
3134 // Loop over the options, keeping track of the most general one.
3135 for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) {
3136 TargetLowering::ConstraintType CType =
3137 TLI.getConstraintType(OpInfo.Codes[i]);
3139 // If this is an 'other' constraint, see if the operand is valid for it.
3140 // For example, on X86 we might have an 'rI' constraint. If the operand
3141 // is an integer in the range [0..31] we want to use I (saving a load
3142 // of a register), otherwise we must use 'r'.
3143 if (CType == TargetLowering::C_Other && Op.getNode()) {
3144 assert(OpInfo.Codes[i].size() == 1 &&
3145 "Unhandled multi-letter 'other' constraint");
3146 std::vector<SDValue> ResultOps;
3147 TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i],
3149 if (!ResultOps.empty()) {
3156 // Things with matching constraints can only be registers, per gcc
3157 // documentation. This mainly affects "g" constraints.
3158 if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput())
3161 // This constraint letter is more general than the previous one, use it.
3162 int Generality = getConstraintGenerality(CType);
3163 if (Generality > BestGenerality) {
3166 BestGenerality = Generality;
3170 OpInfo.ConstraintCode = OpInfo.Codes[BestIdx];
3171 OpInfo.ConstraintType = BestType;
3174 /// ComputeConstraintToUse - Determines the constraint code and constraint
3175 /// type to use for the specific AsmOperandInfo, setting
3176 /// OpInfo.ConstraintCode and OpInfo.ConstraintType.
3177 void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo,
3179 SelectionDAG *DAG) const {
3180 assert(!OpInfo.Codes.empty() && "Must have at least one constraint");
3182 // Single-letter constraints ('r') are very common.
3183 if (OpInfo.Codes.size() == 1) {
3184 OpInfo.ConstraintCode = OpInfo.Codes[0];
3185 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3187 ChooseConstraint(OpInfo, *this, Op, DAG);
3190 // 'X' matches anything.
3191 if (OpInfo.ConstraintCode == "X" && OpInfo.CallOperandVal) {
3192 // Labels and constants are handled elsewhere ('X' is the only thing
3193 // that matches labels). For Functions, the type here is the type of
3194 // the result, which is not what we want to look at; leave them alone.
3195 Value *v = OpInfo.CallOperandVal;
3196 if (isa<BasicBlock>(v) || isa<ConstantInt>(v) || isa<Function>(v)) {
3197 OpInfo.CallOperandVal = v;
3201 // Otherwise, try to resolve it to something we know about by looking at
3202 // the actual operand type.
3203 if (const char *Repl = LowerXConstraint(OpInfo.ConstraintVT)) {
3204 OpInfo.ConstraintCode = Repl;
3205 OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode);
3210 //===----------------------------------------------------------------------===//
3211 // Loop Strength Reduction hooks
3212 //===----------------------------------------------------------------------===//
3214 /// isLegalAddressingMode - Return true if the addressing mode represented
3215 /// by AM is legal for this target, for a load/store of the specified type.
3216 bool TargetLowering::isLegalAddressingMode(const AddrMode &AM,
3218 // The default implementation of this implements a conservative RISCy, r+r and
3221 // Allows a sign-extended 16-bit immediate field.
3222 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3225 // No global is ever allowed as a base.
3229 // Only support r+r,
3231 case 0: // "r+i" or just "i", depending on HasBaseReg.
3234 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3236 // Otherwise we have r+r or r+i.
3239 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3241 // Allow 2*r as r+r.
3248 /// BuildExactDiv - Given an exact SDIV by a constant, create a multiplication
3249 /// with the multiplicative inverse of the constant.
3250 SDValue TargetLowering::BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl,
3251 SelectionDAG &DAG) const {
3252 ConstantSDNode *C = cast<ConstantSDNode>(Op2);
3253 APInt d = C->getAPIntValue();
3254 assert(d != 0 && "Division by zero!");
3256 // Shift the value upfront if it is even, so the LSB is one.
3257 unsigned ShAmt = d.countTrailingZeros();
3259 // TODO: For UDIV use SRL instead of SRA.
3260 SDValue Amt = DAG.getConstant(ShAmt, getShiftAmountTy(Op1.getValueType()));
3261 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt);
3265 // Calculate the multiplicative inverse, using Newton's method.
3267 while ((t = d*xn) != 1)
3268 xn *= APInt(d.getBitWidth(), 2) - t;
3270 Op2 = DAG.getConstant(xn, Op1.getValueType());
3271 return DAG.getNode(ISD::MUL, dl, Op1.getValueType(), Op1, Op2);
3274 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3275 /// return a DAG expression to select that will generate the same value by
3276 /// multiplying by a magic number. See:
3277 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3278 SDValue TargetLowering::
3279 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3280 std::vector<SDNode*>* Created) const {
3281 EVT VT = N->getValueType(0);
3282 DebugLoc dl= N->getDebugLoc();
3284 // Check to see if we can do this.
3285 // FIXME: We should be more aggressive here.
3286 if (!isTypeLegal(VT))
3289 APInt d = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3290 APInt::ms magics = d.magic();
3292 // Multiply the numerator (operand 0) by the magic value
3293 // FIXME: We should support doing a MUL in a wider type
3295 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
3296 isOperationLegalOrCustom(ISD::MULHS, VT))
3297 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
3298 DAG.getConstant(magics.m, VT));
3299 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
3300 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
3301 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
3303 DAG.getConstant(magics.m, VT)).getNode(), 1);
3305 return SDValue(); // No mulhs or equvialent
3306 // If d > 0 and m < 0, add the numerator
3307 if (d.isStrictlyPositive() && magics.m.isNegative()) {
3308 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
3310 Created->push_back(Q.getNode());
3312 // If d < 0 and m > 0, subtract the numerator.
3313 if (d.isNegative() && magics.m.isStrictlyPositive()) {
3314 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
3316 Created->push_back(Q.getNode());
3318 // Shift right algebraic if shift value is nonzero
3320 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
3321 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3323 Created->push_back(Q.getNode());
3325 // Extract the sign bit and add it to the quotient
3327 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
3328 getShiftAmountTy(Q.getValueType())));
3330 Created->push_back(T.getNode());
3331 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
3334 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3335 /// return a DAG expression to select that will generate the same value by
3336 /// multiplying by a magic number. See:
3337 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3338 SDValue TargetLowering::
3339 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
3340 std::vector<SDNode*>* Created) const {
3341 EVT VT = N->getValueType(0);
3342 DebugLoc dl = N->getDebugLoc();
3344 // Check to see if we can do this.
3345 // FIXME: We should be more aggressive here.
3346 if (!isTypeLegal(VT))
3349 // FIXME: We should use a narrower constant when the upper
3350 // bits are known to be zero.
3351 const APInt &N1C = cast<ConstantSDNode>(N->getOperand(1))->getAPIntValue();
3352 APInt::mu magics = N1C.magicu();
3354 SDValue Q = N->getOperand(0);
3356 // If the divisor is even, we can avoid using the expensive fixup by shifting
3357 // the divided value upfront.
3358 if (magics.a != 0 && !N1C[0]) {
3359 unsigned Shift = N1C.countTrailingZeros();
3360 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
3361 DAG.getConstant(Shift, getShiftAmountTy(Q.getValueType())));
3363 Created->push_back(Q.getNode());
3365 // Get magic number for the shifted divisor.
3366 magics = N1C.lshr(Shift).magicu(Shift);
3367 assert(magics.a == 0 && "Should use cheap fixup now");
3370 // Multiply the numerator (operand 0) by the magic value
3371 // FIXME: We should support doing a MUL in a wider type
3372 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
3373 isOperationLegalOrCustom(ISD::MULHU, VT))
3374 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
3375 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
3376 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
3377 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
3378 DAG.getConstant(magics.m, VT)).getNode(), 1);
3380 return SDValue(); // No mulhu or equvialent
3382 Created->push_back(Q.getNode());
3384 if (magics.a == 0) {
3385 assert(magics.s < N1C.getBitWidth() &&
3386 "We shouldn't generate an undefined shift!");
3387 return DAG.getNode(ISD::SRL, dl, VT, Q,
3388 DAG.getConstant(magics.s, getShiftAmountTy(Q.getValueType())));
3390 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3392 Created->push_back(NPQ.getNode());
3393 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
3394 DAG.getConstant(1, getShiftAmountTy(NPQ.getValueType())));
3396 Created->push_back(NPQ.getNode());
3397 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
3399 Created->push_back(NPQ.getNode());
3400 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
3401 DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType())));