1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(),
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
523 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
525 bool Smaller = ValueVT.bitsLE(PartVT);
526 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
534 // Handle a multi-element vector.
537 unsigned NumIntermediates;
538 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
540 NumIntermediates, RegisterVT);
541 unsigned NumElements = ValueVT.getVectorNumElements();
543 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
544 NumParts = NumRegs; // Silence a compiler warning.
545 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
547 // Split the vector into intermediate operands.
548 SmallVector<SDValue, 8> Ops(NumIntermediates);
549 for (unsigned i = 0; i != NumIntermediates; ++i) {
550 if (IntermediateVT.isVector())
551 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
553 DAG.getConstant(i * (NumElements / NumIntermediates),
554 TLI.getVectorIdxTy()));
556 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
558 DAG.getConstant(i, TLI.getVectorIdxTy()));
561 // Split the intermediate operands into legal parts.
562 if (NumParts == NumIntermediates) {
563 // If the register was not expanded, promote or copy the value,
565 for (unsigned i = 0; i != NumParts; ++i)
566 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
567 } else if (NumParts > 0) {
568 // If the intermediate type was expanded, split each the value into
570 assert(NumIntermediates != 0 && "division by zero");
571 assert(NumParts % NumIntermediates == 0 &&
572 "Must expand into a divisible number of parts!");
573 unsigned Factor = NumParts / NumIntermediates;
574 for (unsigned i = 0; i != NumIntermediates; ++i)
575 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 /// RegsForValue - This struct represents the registers (physical or virtual)
581 /// that a particular set of values is assigned, and the type information
582 /// about the value. The most common situation is to represent one value at a
583 /// time, but struct or array values are handled element-wise as multiple
584 /// values. The splitting of aggregates is performed recursively, so that we
585 /// never have aggregate-typed registers. The values at this point do not
586 /// necessarily have legal types, so each value may require one or more
587 /// registers of some legal type.
589 struct RegsForValue {
590 /// ValueVTs - The value types of the values, which may not be legal, and
591 /// may need be promoted or synthesized from one or more registers.
593 SmallVector<EVT, 4> ValueVTs;
595 /// RegVTs - The value types of the registers. This is the same size as
596 /// ValueVTs and it records, for each value, what the type of the assigned
597 /// register or registers are. (Individual values are never synthesized
598 /// from more than one type of register.)
600 /// With virtual registers, the contents of RegVTs is redundant with TLI's
601 /// getRegisterType member function, however when with physical registers
602 /// it is necessary to have a separate record of the types.
604 SmallVector<MVT, 4> RegVTs;
606 /// Regs - This list holds the registers assigned to the values.
607 /// Each legal or promoted value requires one register, and each
608 /// expanded value requires multiple registers.
610 SmallVector<unsigned, 4> Regs;
614 RegsForValue(const SmallVector<unsigned, 4> ®s,
615 MVT regvt, EVT valuevt)
616 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
618 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
619 unsigned Reg, Type *Ty) {
620 ComputeValueVTs(tli, Ty, ValueVTs);
622 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 EVT ValueVT = ValueVTs[Value];
624 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
625 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
626 for (unsigned i = 0; i != NumRegs; ++i)
627 Regs.push_back(Reg + i);
628 RegVTs.push_back(RegisterVT);
633 /// append - Add the specified values to this one.
634 void append(const RegsForValue &RHS) {
635 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
636 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
637 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
640 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
641 /// this value and returns the result as a ValueVTs value. This uses
642 /// Chain/Flag as the input and updates them for the output Chain/Flag.
643 /// If the Flag pointer is NULL, no flag is used.
644 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
646 SDValue &Chain, SDValue *Flag,
647 const Value *V = nullptr) const;
649 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
650 /// specified value into the registers specified by this object. This uses
651 /// Chain/Flag as the input and updates them for the output Chain/Flag.
652 /// If the Flag pointer is NULL, no flag is used.
654 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
655 SDValue *Flag, const Value *V,
656 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
658 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
659 /// operand list. This adds the code marker, matching input operand index
660 /// (if applicable), and includes the number of values added into it.
661 void AddInlineAsmOperands(unsigned Kind,
662 bool HasMatching, unsigned MatchingIdx,
664 std::vector<SDValue> &Ops) const;
668 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
669 /// this value and returns the result as a ValueVT value. This uses
670 /// Chain/Flag as the input and updates them for the output Chain/Flag.
671 /// If the Flag pointer is NULL, no flag is used.
672 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
673 FunctionLoweringInfo &FuncInfo,
675 SDValue &Chain, SDValue *Flag,
676 const Value *V) const {
677 // A Value with type {} or [0 x %t] needs no registers.
678 if (ValueVTs.empty())
681 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
683 // Assemble the legal parts into the final values.
684 SmallVector<SDValue, 4> Values(ValueVTs.size());
685 SmallVector<SDValue, 8> Parts;
686 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
687 // Copy the legal parts from the registers.
688 EVT ValueVT = ValueVTs[Value];
689 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
690 MVT RegisterVT = RegVTs[Value];
692 Parts.resize(NumRegs);
693 for (unsigned i = 0; i != NumRegs; ++i) {
696 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
698 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
699 *Flag = P.getValue(2);
702 Chain = P.getValue(1);
705 // If the source register was virtual and if we know something about it,
706 // add an assert node.
707 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
708 !RegisterVT.isInteger() || RegisterVT.isVector())
711 const FunctionLoweringInfo::LiveOutInfo *LOI =
712 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
716 unsigned RegSize = RegisterVT.getSizeInBits();
717 unsigned NumSignBits = LOI->NumSignBits;
718 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
720 if (NumZeroBits == RegSize) {
721 // The current value is a zero.
722 // Explicitly express that as it would be easier for
723 // optimizations to kick in.
724 Parts[i] = DAG.getConstant(0, RegisterVT);
728 // FIXME: We capture more information than the dag can represent. For
729 // now, just use the tightest assertzext/assertsext possible.
731 EVT FromVT(MVT::Other);
732 if (NumSignBits == RegSize)
733 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
734 else if (NumZeroBits >= RegSize-1)
735 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
736 else if (NumSignBits > RegSize-8)
737 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
738 else if (NumZeroBits >= RegSize-8)
739 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
740 else if (NumSignBits > RegSize-16)
741 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
742 else if (NumZeroBits >= RegSize-16)
743 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
744 else if (NumSignBits > RegSize-32)
745 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
746 else if (NumZeroBits >= RegSize-32)
747 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
751 // Add an assertion node.
752 assert(FromVT != MVT::Other);
753 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
754 RegisterVT, P, DAG.getValueType(FromVT));
757 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
758 NumRegs, RegisterVT, ValueVT, V);
763 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
766 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
767 /// specified value into the registers specified by this object. This uses
768 /// Chain/Flag as the input and updates them for the output Chain/Flag.
769 /// If the Flag pointer is NULL, no flag is used.
770 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
771 SDValue &Chain, SDValue *Flag, const Value *V,
772 ISD::NodeType PreferredExtendType) const {
773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
774 ISD::NodeType ExtendKind = PreferredExtendType;
776 // Get the list of the values's legal parts.
777 unsigned NumRegs = Regs.size();
778 SmallVector<SDValue, 8> Parts(NumRegs);
779 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
780 EVT ValueVT = ValueVTs[Value];
781 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
782 MVT RegisterVT = RegVTs[Value];
784 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
785 ExtendKind = ISD::ZERO_EXTEND;
787 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
788 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
792 // Copy the parts into the registers.
793 SmallVector<SDValue, 8> Chains(NumRegs);
794 for (unsigned i = 0; i != NumRegs; ++i) {
797 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
799 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
800 *Flag = Part.getValue(1);
803 Chains[i] = Part.getValue(0);
806 if (NumRegs == 1 || Flag)
807 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
808 // flagged to it. That is the CopyToReg nodes and the user are considered
809 // a single scheduling unit. If we create a TokenFactor and return it as
810 // chain, then the TokenFactor is both a predecessor (operand) of the
811 // user as well as a successor (the TF operands are flagged to the user).
812 // c1, f1 = CopyToReg
813 // c2, f2 = CopyToReg
814 // c3 = TokenFactor c1, c2
817 Chain = Chains[NumRegs-1];
819 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
822 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
823 /// operand list. This adds the code marker and includes the number of
824 /// values added into it.
825 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
826 unsigned MatchingIdx,
828 std::vector<SDValue> &Ops) const {
829 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
831 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
833 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
834 else if (!Regs.empty() &&
835 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
836 // Put the register class of the virtual registers in the flag word. That
837 // way, later passes can recompute register class constraints for inline
838 // assembly as well as normal instructions.
839 // Don't do this for tied operands that can use the regclass information
841 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
842 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
843 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
846 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
849 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
850 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
851 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
852 MVT RegisterVT = RegVTs[Value];
853 for (unsigned i = 0; i != NumRegs; ++i) {
854 assert(Reg < Regs.size() && "Mismatch in # registers expected");
855 unsigned TheReg = Regs[Reg++];
856 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
858 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
859 // If we clobbered the stack pointer, MFI should know about it.
860 assert(DAG.getMachineFunction().getFrameInfo()->
861 hasInlineAsmWithSPAdjust());
867 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
868 const TargetLibraryInfo *li) {
872 DL = DAG.getTarget().getDataLayout();
873 Context = DAG.getContext();
874 LPadToCallSiteMap.clear();
877 /// clear - Clear out the current SelectionDAG and the associated
878 /// state and prepare this SelectionDAGBuilder object to be used
879 /// for a new block. This doesn't clear out information about
880 /// additional blocks that are needed to complete switch lowering
881 /// or PHI node updating; that information is cleared out as it is
883 void SelectionDAGBuilder::clear() {
885 UnusedArgNodeMap.clear();
886 PendingLoads.clear();
887 PendingExports.clear();
890 SDNodeOrder = LowestSDNodeOrder;
891 StatepointLowering.clear();
894 /// clearDanglingDebugInfo - Clear the dangling debug information
895 /// map. This function is separated from the clear so that debug
896 /// information that is dangling in a basic block can be properly
897 /// resolved in a different basic block. This allows the
898 /// SelectionDAG to resolve dangling debug information attached
900 void SelectionDAGBuilder::clearDanglingDebugInfo() {
901 DanglingDebugInfoMap.clear();
904 /// getRoot - Return the current virtual root of the Selection DAG,
905 /// flushing any PendingLoad items. This must be done before emitting
906 /// a store or any other node that may need to be ordered after any
907 /// prior load instructions.
909 SDValue SelectionDAGBuilder::getRoot() {
910 if (PendingLoads.empty())
911 return DAG.getRoot();
913 if (PendingLoads.size() == 1) {
914 SDValue Root = PendingLoads[0];
916 PendingLoads.clear();
920 // Otherwise, we have to make a token factor node.
921 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
923 PendingLoads.clear();
928 /// getControlRoot - Similar to getRoot, but instead of flushing all the
929 /// PendingLoad items, flush all the PendingExports items. It is necessary
930 /// to do this before emitting a terminator instruction.
932 SDValue SelectionDAGBuilder::getControlRoot() {
933 SDValue Root = DAG.getRoot();
935 if (PendingExports.empty())
938 // Turn all of the CopyToReg chains into one factored node.
939 if (Root.getOpcode() != ISD::EntryToken) {
940 unsigned i = 0, e = PendingExports.size();
941 for (; i != e; ++i) {
942 assert(PendingExports[i].getNode()->getNumOperands() > 1);
943 if (PendingExports[i].getNode()->getOperand(0) == Root)
944 break; // Don't add the root if we already indirectly depend on it.
948 PendingExports.push_back(Root);
951 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
953 PendingExports.clear();
958 void SelectionDAGBuilder::visit(const Instruction &I) {
959 // Set up outgoing PHI node register values before emitting the terminator.
960 if (isa<TerminatorInst>(&I))
961 HandlePHINodesInSuccessorBlocks(I.getParent());
967 visit(I.getOpcode(), I);
969 if (!isa<TerminatorInst>(&I) && !HasTailCall)
970 CopyToExportRegsIfNeeded(&I);
975 void SelectionDAGBuilder::visitPHI(const PHINode &) {
976 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
979 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
980 // Note: this doesn't use InstVisitor, because it has to work with
981 // ConstantExpr's in addition to instructions.
983 default: llvm_unreachable("Unknown instruction type encountered!");
984 // Build the switch statement using the Instruction.def file.
985 #define HANDLE_INST(NUM, OPCODE, CLASS) \
986 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
987 #include "llvm/IR/Instruction.def"
991 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
992 // generate the debug data structures now that we've seen its definition.
993 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
995 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
997 const DbgValueInst *DI = DDI.getDI();
998 DebugLoc dl = DDI.getdl();
999 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1000 MDNode *Variable = DI->getVariable();
1001 MDNode *Expr = DI->getExpression();
1002 uint64_t Offset = DI->getOffset();
1003 // A dbg.value for an alloca is always indirect.
1004 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1006 if (Val.getNode()) {
1007 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1009 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1010 IsIndirect, Offset, dl, DbgSDNodeOrder);
1011 DAG.AddDbgValue(SDV, Val.getNode(), false);
1014 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1015 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1019 /// getCopyFromRegs - If there was virtual register allocated for the value V
1020 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1021 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1022 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1029 SDValue Chain = DAG.getEntryNode();
1030 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1031 resolveDanglingDebugInfo(V, res);
1037 /// getValue - Return an SDValue for the given Value.
1038 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1039 // If we already have an SDValue for this value, use it. It's important
1040 // to do this first, so that we don't create a CopyFromReg if we already
1041 // have a regular SDValue.
1042 SDValue &N = NodeMap[V];
1043 if (N.getNode()) return N;
1045 // If there's a virtual register allocated and initialized for this
1047 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1048 if (copyFromReg.getNode()) {
1052 // Otherwise create a new SDValue and remember it.
1053 SDValue Val = getValueImpl(V);
1055 resolveDanglingDebugInfo(V, Val);
1059 /// getNonRegisterValue - Return an SDValue for the given Value, but
1060 /// don't look in FuncInfo.ValueMap for a virtual register.
1061 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1062 // If we already have an SDValue for this value, use it.
1063 SDValue &N = NodeMap[V];
1064 if (N.getNode()) return N;
1066 // Otherwise create a new SDValue and remember it.
1067 SDValue Val = getValueImpl(V);
1069 resolveDanglingDebugInfo(V, Val);
1073 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1074 /// Create an SDValue for the given value.
1075 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1078 if (const Constant *C = dyn_cast<Constant>(V)) {
1079 EVT VT = TLI.getValueType(V->getType(), true);
1081 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1082 return DAG.getConstant(*CI, VT);
1084 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1085 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1087 if (isa<ConstantPointerNull>(C)) {
1088 unsigned AS = V->getType()->getPointerAddressSpace();
1089 return DAG.getConstant(0, TLI.getPointerTy(AS));
1092 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1093 return DAG.getConstantFP(*CFP, VT);
1095 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1096 return DAG.getUNDEF(VT);
1098 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1099 visit(CE->getOpcode(), *CE);
1100 SDValue N1 = NodeMap[V];
1101 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1105 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1106 SmallVector<SDValue, 4> Constants;
1107 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1109 SDNode *Val = getValue(*OI).getNode();
1110 // If the operand is an empty aggregate, there are no values.
1112 // Add each leaf value from the operand to the Constants list
1113 // to form a flattened list of all the values.
1114 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1115 Constants.push_back(SDValue(Val, i));
1118 return DAG.getMergeValues(Constants, getCurSDLoc());
1121 if (const ConstantDataSequential *CDS =
1122 dyn_cast<ConstantDataSequential>(C)) {
1123 SmallVector<SDValue, 4> Ops;
1124 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1125 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1126 // Add each leaf value from the operand to the Constants list
1127 // to form a flattened list of all the values.
1128 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1129 Ops.push_back(SDValue(Val, i));
1132 if (isa<ArrayType>(CDS->getType()))
1133 return DAG.getMergeValues(Ops, getCurSDLoc());
1134 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1138 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1139 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1140 "Unknown struct or array constant!");
1142 SmallVector<EVT, 4> ValueVTs;
1143 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1144 unsigned NumElts = ValueVTs.size();
1146 return SDValue(); // empty struct
1147 SmallVector<SDValue, 4> Constants(NumElts);
1148 for (unsigned i = 0; i != NumElts; ++i) {
1149 EVT EltVT = ValueVTs[i];
1150 if (isa<UndefValue>(C))
1151 Constants[i] = DAG.getUNDEF(EltVT);
1152 else if (EltVT.isFloatingPoint())
1153 Constants[i] = DAG.getConstantFP(0, EltVT);
1155 Constants[i] = DAG.getConstant(0, EltVT);
1158 return DAG.getMergeValues(Constants, getCurSDLoc());
1161 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1162 return DAG.getBlockAddress(BA, VT);
1164 VectorType *VecTy = cast<VectorType>(V->getType());
1165 unsigned NumElements = VecTy->getNumElements();
1167 // Now that we know the number and type of the elements, get that number of
1168 // elements into the Ops array based on what kind of constant it is.
1169 SmallVector<SDValue, 16> Ops;
1170 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1171 for (unsigned i = 0; i != NumElements; ++i)
1172 Ops.push_back(getValue(CV->getOperand(i)));
1174 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1175 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1178 if (EltVT.isFloatingPoint())
1179 Op = DAG.getConstantFP(0, EltVT);
1181 Op = DAG.getConstant(0, EltVT);
1182 Ops.assign(NumElements, Op);
1185 // Create a BUILD_VECTOR node.
1186 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1189 // If this is a static alloca, generate it as the frameindex instead of
1191 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1192 DenseMap<const AllocaInst*, int>::iterator SI =
1193 FuncInfo.StaticAllocaMap.find(AI);
1194 if (SI != FuncInfo.StaticAllocaMap.end())
1195 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1198 // If this is an instruction which fast-isel has deferred, select it now.
1199 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1200 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1201 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1202 SDValue Chain = DAG.getEntryNode();
1203 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1206 llvm_unreachable("Can't get register for value!");
1209 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1210 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1211 SDValue Chain = getControlRoot();
1212 SmallVector<ISD::OutputArg, 8> Outs;
1213 SmallVector<SDValue, 8> OutVals;
1215 if (!FuncInfo.CanLowerReturn) {
1216 unsigned DemoteReg = FuncInfo.DemoteRegister;
1217 const Function *F = I.getParent()->getParent();
1219 // Emit a store of the return value through the virtual register.
1220 // Leave Outs empty so that LowerReturn won't try to load return
1221 // registers the usual way.
1222 SmallVector<EVT, 1> PtrValueVTs;
1223 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1226 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1227 SDValue RetOp = getValue(I.getOperand(0));
1229 SmallVector<EVT, 4> ValueVTs;
1230 SmallVector<uint64_t, 4> Offsets;
1231 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1232 unsigned NumValues = ValueVTs.size();
1234 SmallVector<SDValue, 4> Chains(NumValues);
1235 for (unsigned i = 0; i != NumValues; ++i) {
1236 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1237 RetPtr.getValueType(), RetPtr,
1238 DAG.getIntPtrConstant(Offsets[i]));
1240 DAG.getStore(Chain, getCurSDLoc(),
1241 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1242 // FIXME: better loc info would be nice.
1243 Add, MachinePointerInfo(), false, false, 0);
1246 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1247 MVT::Other, Chains);
1248 } else if (I.getNumOperands() != 0) {
1249 SmallVector<EVT, 4> ValueVTs;
1250 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1251 unsigned NumValues = ValueVTs.size();
1253 SDValue RetOp = getValue(I.getOperand(0));
1255 const Function *F = I.getParent()->getParent();
1257 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1258 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1260 ExtendKind = ISD::SIGN_EXTEND;
1261 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 ExtendKind = ISD::ZERO_EXTEND;
1265 LLVMContext &Context = F->getContext();
1266 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1269 for (unsigned j = 0; j != NumValues; ++j) {
1270 EVT VT = ValueVTs[j];
1272 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1273 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1275 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1276 MVT PartVT = TLI.getRegisterType(Context, VT);
1277 SmallVector<SDValue, 4> Parts(NumParts);
1278 getCopyToParts(DAG, getCurSDLoc(),
1279 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1280 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1282 // 'inreg' on function refers to return value
1283 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1287 // Propagate extension type if any
1288 if (ExtendKind == ISD::SIGN_EXTEND)
1290 else if (ExtendKind == ISD::ZERO_EXTEND)
1293 for (unsigned i = 0; i < NumParts; ++i) {
1294 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1295 VT, /*isfixed=*/true, 0, 0));
1296 OutVals.push_back(Parts[i]);
1302 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1303 CallingConv::ID CallConv =
1304 DAG.getMachineFunction().getFunction()->getCallingConv();
1305 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1306 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1308 // Verify that the target's LowerReturn behaved as expected.
1309 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1310 "LowerReturn didn't return a valid chain!");
1312 // Update the DAG with the new chain value resulting from return lowering.
1316 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1317 /// created for it, emit nodes to copy the value into the virtual
1319 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1321 if (V->getType()->isEmptyTy())
1324 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1325 if (VMI != FuncInfo.ValueMap.end()) {
1326 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1327 CopyValueToVirtualRegister(V, VMI->second);
1331 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1332 /// the current basic block, add it to ValueMap now so that we'll get a
1334 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1335 // No need to export constants.
1336 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1338 // Already exported?
1339 if (FuncInfo.isExportedInst(V)) return;
1341 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1342 CopyValueToVirtualRegister(V, Reg);
1345 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1346 const BasicBlock *FromBB) {
1347 // The operands of the setcc have to be in this block. We don't know
1348 // how to export them from some other block.
1349 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1350 // Can export from current BB.
1351 if (VI->getParent() == FromBB)
1354 // Is already exported, noop.
1355 return FuncInfo.isExportedInst(V);
1358 // If this is an argument, we can export it if the BB is the entry block or
1359 // if it is already exported.
1360 if (isa<Argument>(V)) {
1361 if (FromBB == &FromBB->getParent()->getEntryBlock())
1364 // Otherwise, can only export this if it is already exported.
1365 return FuncInfo.isExportedInst(V);
1368 // Otherwise, constants can always be exported.
1372 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1373 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1374 const MachineBasicBlock *Dst) const {
1375 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1378 const BasicBlock *SrcBB = Src->getBasicBlock();
1379 const BasicBlock *DstBB = Dst->getBasicBlock();
1380 return BPI->getEdgeWeight(SrcBB, DstBB);
1383 void SelectionDAGBuilder::
1384 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1385 uint32_t Weight /* = 0 */) {
1387 Weight = getEdgeWeight(Src, Dst);
1388 Src->addSuccessor(Dst, Weight);
1392 static bool InBlock(const Value *V, const BasicBlock *BB) {
1393 if (const Instruction *I = dyn_cast<Instruction>(V))
1394 return I->getParent() == BB;
1398 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1399 /// This function emits a branch and is used at the leaves of an OR or an
1400 /// AND operator tree.
1403 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1404 MachineBasicBlock *TBB,
1405 MachineBasicBlock *FBB,
1406 MachineBasicBlock *CurBB,
1407 MachineBasicBlock *SwitchBB,
1410 const BasicBlock *BB = CurBB->getBasicBlock();
1412 // If the leaf of the tree is a comparison, merge the condition into
1414 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1415 // The operands of the cmp have to be in this block. We don't know
1416 // how to export them from some other block. If this is the first block
1417 // of the sequence, no exporting is needed.
1418 if (CurBB == SwitchBB ||
1419 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1420 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1421 ISD::CondCode Condition;
1422 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1423 Condition = getICmpCondCode(IC->getPredicate());
1424 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1425 Condition = getFCmpCondCode(FC->getPredicate());
1426 if (TM.Options.NoNaNsFPMath)
1427 Condition = getFCmpCodeWithoutNaN(Condition);
1429 (void)Condition; // silence warning.
1430 llvm_unreachable("Unknown compare instruction");
1433 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1434 TBB, FBB, CurBB, TWeight, FWeight);
1435 SwitchCases.push_back(CB);
1440 // Create a CaseBlock record representing this branch.
1441 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1442 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1443 SwitchCases.push_back(CB);
1446 /// Scale down both weights to fit into uint32_t.
1447 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1448 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1449 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1450 NewTrue = NewTrue / Scale;
1451 NewFalse = NewFalse / Scale;
1454 /// FindMergedConditions - If Cond is an expression like
1455 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1456 MachineBasicBlock *TBB,
1457 MachineBasicBlock *FBB,
1458 MachineBasicBlock *CurBB,
1459 MachineBasicBlock *SwitchBB,
1460 unsigned Opc, uint32_t TWeight,
1462 // If this node is not part of the or/and tree, emit it as a branch.
1463 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1464 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1465 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1466 BOp->getParent() != CurBB->getBasicBlock() ||
1467 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1468 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1469 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1474 // Create TmpBB after CurBB.
1475 MachineFunction::iterator BBI = CurBB;
1476 MachineFunction &MF = DAG.getMachineFunction();
1477 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1478 CurBB->getParent()->insert(++BBI, TmpBB);
1480 if (Opc == Instruction::Or) {
1481 // Codegen X | Y as:
1490 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1491 // The requirement is that
1492 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1493 // = TrueProb for orignal BB.
1494 // Assuming the orignal weights are A and B, one choice is to set BB1's
1495 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1497 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1498 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1499 // TmpBB, but the math is more complicated.
1501 uint64_t NewTrueWeight = TWeight;
1502 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1503 ScaleWeights(NewTrueWeight, NewFalseWeight);
1504 // Emit the LHS condition.
1505 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1506 NewTrueWeight, NewFalseWeight);
1508 NewTrueWeight = TWeight;
1509 NewFalseWeight = 2 * (uint64_t)FWeight;
1510 ScaleWeights(NewTrueWeight, NewFalseWeight);
1511 // Emit the RHS condition into TmpBB.
1512 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1513 NewTrueWeight, NewFalseWeight);
1515 assert(Opc == Instruction::And && "Unknown merge op!");
1516 // Codegen X & Y as:
1524 // This requires creation of TmpBB after CurBB.
1526 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1527 // The requirement is that
1528 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1529 // = FalseProb for orignal BB.
1530 // Assuming the orignal weights are A and B, one choice is to set BB1's
1531 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1533 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1535 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1536 uint64_t NewFalseWeight = FWeight;
1537 ScaleWeights(NewTrueWeight, NewFalseWeight);
1538 // Emit the LHS condition.
1539 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1540 NewTrueWeight, NewFalseWeight);
1542 NewTrueWeight = 2 * (uint64_t)TWeight;
1543 NewFalseWeight = FWeight;
1544 ScaleWeights(NewTrueWeight, NewFalseWeight);
1545 // Emit the RHS condition into TmpBB.
1546 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1547 NewTrueWeight, NewFalseWeight);
1551 /// If the set of cases should be emitted as a series of branches, return true.
1552 /// If we should emit this as a bunch of and/or'd together conditions, return
1555 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1556 if (Cases.size() != 2) return true;
1558 // If this is two comparisons of the same values or'd or and'd together, they
1559 // will get folded into a single comparison, so don't emit two blocks.
1560 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1561 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1562 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1563 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1567 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1568 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1569 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1570 Cases[0].CC == Cases[1].CC &&
1571 isa<Constant>(Cases[0].CmpRHS) &&
1572 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1573 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1575 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1582 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1583 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1585 // Update machine-CFG edges.
1586 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1588 if (I.isUnconditional()) {
1589 // Update machine-CFG edges.
1590 BrMBB->addSuccessor(Succ0MBB);
1592 // If this is not a fall-through branch or optimizations are switched off,
1594 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1595 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1596 MVT::Other, getControlRoot(),
1597 DAG.getBasicBlock(Succ0MBB)));
1602 // If this condition is one of the special cases we handle, do special stuff
1604 const Value *CondVal = I.getCondition();
1605 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1607 // If this is a series of conditions that are or'd or and'd together, emit
1608 // this as a sequence of branches instead of setcc's with and/or operations.
1609 // As long as jumps are not expensive, this should improve performance.
1610 // For example, instead of something like:
1623 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1624 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1625 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1626 BOp->getOpcode() == Instruction::Or)) {
1627 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1628 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1629 getEdgeWeight(BrMBB, Succ1MBB));
1630 // If the compares in later blocks need to use values not currently
1631 // exported from this block, export them now. This block should always
1632 // be the first entry.
1633 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1635 // Allow some cases to be rejected.
1636 if (ShouldEmitAsBranches(SwitchCases)) {
1637 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1638 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1639 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1642 // Emit the branch for this block.
1643 visitSwitchCase(SwitchCases[0], BrMBB);
1644 SwitchCases.erase(SwitchCases.begin());
1648 // Okay, we decided not to do this, remove any inserted MBB's and clear
1650 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1651 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1653 SwitchCases.clear();
1657 // Create a CaseBlock record representing this branch.
1658 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1659 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1661 // Use visitSwitchCase to actually insert the fast branch sequence for this
1663 visitSwitchCase(CB, BrMBB);
1666 /// visitSwitchCase - Emits the necessary code to represent a single node in
1667 /// the binary search tree resulting from lowering a switch instruction.
1668 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1669 MachineBasicBlock *SwitchBB) {
1671 SDValue CondLHS = getValue(CB.CmpLHS);
1672 SDLoc dl = getCurSDLoc();
1674 // Build the setcc now.
1676 // Fold "(X == true)" to X and "(X == false)" to !X to
1677 // handle common cases produced by branch lowering.
1678 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1679 CB.CC == ISD::SETEQ)
1681 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1682 CB.CC == ISD::SETEQ) {
1683 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1684 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1686 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1688 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1690 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1691 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1693 SDValue CmpOp = getValue(CB.CmpMHS);
1694 EVT VT = CmpOp.getValueType();
1696 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1697 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1700 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1701 VT, CmpOp, DAG.getConstant(Low, VT));
1702 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1703 DAG.getConstant(High-Low, VT), ISD::SETULE);
1707 // Update successor info
1708 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1709 // TrueBB and FalseBB are always different unless the incoming IR is
1710 // degenerate. This only happens when running llc on weird IR.
1711 if (CB.TrueBB != CB.FalseBB)
1712 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1714 // If the lhs block is the next block, invert the condition so that we can
1715 // fall through to the lhs instead of the rhs block.
1716 if (CB.TrueBB == NextBlock(SwitchBB)) {
1717 std::swap(CB.TrueBB, CB.FalseBB);
1718 SDValue True = DAG.getConstant(1, Cond.getValueType());
1719 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1722 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1723 MVT::Other, getControlRoot(), Cond,
1724 DAG.getBasicBlock(CB.TrueBB));
1726 // Insert the false branch. Do this even if it's a fall through branch,
1727 // this makes it easier to do DAG optimizations which require inverting
1728 // the branch condition.
1729 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1730 DAG.getBasicBlock(CB.FalseBB));
1732 DAG.setRoot(BrCond);
1735 /// visitJumpTable - Emit JumpTable node in the current MBB
1736 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1737 // Emit the code for the jump table
1738 assert(JT.Reg != -1U && "Should lower JT Header first!");
1739 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1740 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1742 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1743 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1744 MVT::Other, Index.getValue(1),
1746 DAG.setRoot(BrJumpTable);
1749 /// visitJumpTableHeader - This function emits necessary code to produce index
1750 /// in the JumpTable from switch case.
1751 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1752 JumpTableHeader &JTH,
1753 MachineBasicBlock *SwitchBB) {
1754 // Subtract the lowest switch case value from the value being switched on and
1755 // conditional branch to default mbb if the result is greater than the
1756 // difference between smallest and largest cases.
1757 SDValue SwitchOp = getValue(JTH.SValue);
1758 EVT VT = SwitchOp.getValueType();
1759 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1760 DAG.getConstant(JTH.First, VT));
1762 // The SDNode we just created, which holds the value being switched on minus
1763 // the smallest case value, needs to be copied to a virtual register so it
1764 // can be used as an index into the jump table in a subsequent basic block.
1765 // This value may be smaller or larger than the target's pointer type, and
1766 // therefore require extension or truncating.
1767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1768 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1770 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1771 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1772 JumpTableReg, SwitchOp);
1773 JT.Reg = JumpTableReg;
1775 // Emit the range check for the jump table, and branch to the default block
1776 // for the switch statement if the value being switched on exceeds the largest
1777 // case in the switch.
1779 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1780 Sub.getValueType()),
1781 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1783 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1784 MVT::Other, CopyTo, CMP,
1785 DAG.getBasicBlock(JT.Default));
1787 // Avoid emitting unnecessary branches to the next block.
1788 if (JT.MBB != NextBlock(SwitchBB))
1789 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1790 DAG.getBasicBlock(JT.MBB));
1792 DAG.setRoot(BrCond);
1795 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1796 /// tail spliced into a stack protector check success bb.
1798 /// For a high level explanation of how this fits into the stack protector
1799 /// generation see the comment on the declaration of class
1800 /// StackProtectorDescriptor.
1801 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1802 MachineBasicBlock *ParentBB) {
1804 // First create the loads to the guard/stack slot for the comparison.
1805 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1806 EVT PtrTy = TLI.getPointerTy();
1808 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1809 int FI = MFI->getStackProtectorIndex();
1811 const Value *IRGuard = SPD.getGuard();
1812 SDValue GuardPtr = getValue(IRGuard);
1813 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1816 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1820 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1821 // guard value from the virtual register holding the value. Otherwise, emit a
1822 // volatile load to retrieve the stack guard value.
1823 unsigned GuardReg = SPD.getGuardReg();
1825 if (GuardReg && TLI.useLoadStackGuardNode())
1826 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1829 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1830 GuardPtr, MachinePointerInfo(IRGuard, 0),
1831 true, false, false, Align);
1833 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1835 MachinePointerInfo::getFixedStack(FI),
1836 true, false, false, Align);
1838 // Perform the comparison via a subtract/getsetcc.
1839 EVT VT = Guard.getValueType();
1840 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1843 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1844 Sub.getValueType()),
1845 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1847 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1848 // branch to failure MBB.
1849 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1850 MVT::Other, StackSlot.getOperand(0),
1851 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1852 // Otherwise branch to success MBB.
1853 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1855 DAG.getBasicBlock(SPD.getSuccessMBB()));
1860 /// Codegen the failure basic block for a stack protector check.
1862 /// A failure stack protector machine basic block consists simply of a call to
1863 /// __stack_chk_fail().
1865 /// For a high level explanation of how this fits into the stack protector
1866 /// generation see the comment on the declaration of class
1867 /// StackProtectorDescriptor.
1869 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1870 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1872 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1873 nullptr, 0, false, getCurSDLoc(), false, false).second;
1877 /// visitBitTestHeader - This function emits necessary code to produce value
1878 /// suitable for "bit tests"
1879 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1880 MachineBasicBlock *SwitchBB) {
1881 // Subtract the minimum value
1882 SDValue SwitchOp = getValue(B.SValue);
1883 EVT VT = SwitchOp.getValueType();
1884 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1885 DAG.getConstant(B.First, VT));
1888 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1890 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1891 Sub.getValueType()),
1892 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1894 // Determine the type of the test operands.
1895 bool UsePtrType = false;
1896 if (!TLI.isTypeLegal(VT))
1899 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1900 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1901 // Switch table case range are encoded into series of masks.
1902 // Just use pointer type, it's guaranteed to fit.
1908 VT = TLI.getPointerTy();
1909 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1912 B.RegVT = VT.getSimpleVT();
1913 B.Reg = FuncInfo.CreateReg(B.RegVT);
1914 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1917 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1919 addSuccessorWithWeight(SwitchBB, B.Default);
1920 addSuccessorWithWeight(SwitchBB, MBB);
1922 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1923 MVT::Other, CopyTo, RangeCmp,
1924 DAG.getBasicBlock(B.Default));
1926 // Avoid emitting unnecessary branches to the next block.
1927 if (MBB != NextBlock(SwitchBB))
1928 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1929 DAG.getBasicBlock(MBB));
1931 DAG.setRoot(BrRange);
1934 /// visitBitTestCase - this function produces one "bit test"
1935 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1936 MachineBasicBlock* NextMBB,
1937 uint32_t BranchWeightToNext,
1940 MachineBasicBlock *SwitchBB) {
1942 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1945 unsigned PopCount = countPopulation(B.Mask);
1946 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1947 if (PopCount == 1) {
1948 // Testing for a single bit; just compare the shift count with what it
1949 // would need to be to shift a 1 bit in that position.
1951 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1952 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1953 } else if (PopCount == BB.Range) {
1954 // There is only one zero bit in the range, test for it directly.
1956 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1957 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1959 // Make desired shift
1960 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1961 DAG.getConstant(1, VT), ShiftOp);
1963 // Emit bit tests and jumps
1964 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1965 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1966 Cmp = DAG.getSetCC(getCurSDLoc(),
1967 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1968 DAG.getConstant(0, VT), ISD::SETNE);
1971 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1972 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1973 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1974 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1976 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1977 MVT::Other, getControlRoot(),
1978 Cmp, DAG.getBasicBlock(B.TargetBB));
1980 // Avoid emitting unnecessary branches to the next block.
1981 if (NextMBB != NextBlock(SwitchBB))
1982 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1983 DAG.getBasicBlock(NextMBB));
1988 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1989 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1991 // Retrieve successors.
1992 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1993 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1995 const Value *Callee(I.getCalledValue());
1996 const Function *Fn = dyn_cast<Function>(Callee);
1997 if (isa<InlineAsm>(Callee))
1999 else if (Fn && Fn->isIntrinsic()) {
2000 switch (Fn->getIntrinsicID()) {
2002 llvm_unreachable("Cannot invoke this intrinsic");
2003 case Intrinsic::donothing:
2004 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2006 case Intrinsic::experimental_patchpoint_void:
2007 case Intrinsic::experimental_patchpoint_i64:
2008 visitPatchpoint(&I, LandingPad);
2010 case Intrinsic::experimental_gc_statepoint:
2011 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2015 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2017 // If the value of the invoke is used outside of its defining block, make it
2018 // available as a virtual register.
2019 // We already took care of the exported value for the statepoint instruction
2020 // during call to the LowerStatepoint.
2021 if (!isStatepoint(I)) {
2022 CopyToExportRegsIfNeeded(&I);
2025 // Update successor info
2026 addSuccessorWithWeight(InvokeMBB, Return);
2027 addSuccessorWithWeight(InvokeMBB, LandingPad);
2029 // Drop into normal successor.
2030 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2031 MVT::Other, getControlRoot(),
2032 DAG.getBasicBlock(Return)));
2035 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2036 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2039 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2040 assert(FuncInfo.MBB->isLandingPad() &&
2041 "Call to landingpad not in landing pad!");
2043 MachineBasicBlock *MBB = FuncInfo.MBB;
2044 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2045 AddLandingPadInfo(LP, MMI, MBB);
2047 // If there aren't registers to copy the values into (e.g., during SjLj
2048 // exceptions), then don't bother to create these DAG nodes.
2049 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2050 if (TLI.getExceptionPointerRegister() == 0 &&
2051 TLI.getExceptionSelectorRegister() == 0)
2054 SmallVector<EVT, 2> ValueVTs;
2055 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2056 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2058 // Get the two live-in registers as SDValues. The physregs have already been
2059 // copied into virtual registers.
2061 if (FuncInfo.ExceptionPointerVirtReg) {
2062 Ops[0] = DAG.getZExtOrTrunc(
2063 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2064 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2065 getCurSDLoc(), ValueVTs[0]);
2067 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2069 Ops[1] = DAG.getZExtOrTrunc(
2070 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2071 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2072 getCurSDLoc(), ValueVTs[1]);
2075 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2076 DAG.getVTList(ValueVTs), Ops);
2081 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2082 MachineBasicBlock *LPadBB) {
2083 SDValue Chain = getControlRoot();
2085 // Get the typeid that we will dispatch on later.
2086 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2087 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2088 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2089 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2090 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2091 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2093 // Branch to the main landing pad block.
2094 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2095 ClauseMBB->addSuccessor(LPadBB);
2096 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2097 DAG.getBasicBlock(LPadBB)));
2101 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2102 /// small case ranges).
2103 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2104 CaseRecVector& WorkList,
2106 MachineBasicBlock *Default,
2107 MachineBasicBlock *SwitchBB) {
2108 // Size is the number of Cases represented by this range.
2109 size_t Size = CR.Range.second - CR.Range.first;
2113 // Get the MachineFunction which holds the current MBB. This is used when
2114 // inserting any additional MBBs necessary to represent the switch.
2115 MachineFunction *CurMF = FuncInfo.MF;
2117 // Figure out which block is immediately after the current one.
2118 MachineBasicBlock *NextMBB = nullptr;
2119 MachineFunction::iterator BBI = CR.CaseBB;
2120 if (++BBI != FuncInfo.MF->end())
2123 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2124 // If any two of the cases has the same destination, and if one value
2125 // is the same as the other, but has one bit unset that the other has set,
2126 // use bit manipulation to do two compares at once. For example:
2127 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2128 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2129 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2130 if (Size == 2 && CR.CaseBB == SwitchBB) {
2131 Case &Small = *CR.Range.first;
2132 Case &Big = *(CR.Range.second-1);
2134 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2135 const APInt& SmallValue = Small.Low->getValue();
2136 const APInt& BigValue = Big.Low->getValue();
2138 // Check that there is only one bit different.
2139 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2140 (SmallValue | BigValue) == BigValue) {
2141 // Isolate the common bit.
2142 APInt CommonBit = BigValue & ~SmallValue;
2143 assert((SmallValue | CommonBit) == BigValue &&
2144 CommonBit.countPopulation() == 1 && "Not a common bit?");
2146 SDValue CondLHS = getValue(SV);
2147 EVT VT = CondLHS.getValueType();
2148 SDLoc DL = getCurSDLoc();
2150 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2151 DAG.getConstant(CommonBit, VT));
2152 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2153 Or, DAG.getConstant(BigValue, VT),
2156 // Update successor info.
2157 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2158 addSuccessorWithWeight(SwitchBB, Small.BB,
2159 Small.ExtraWeight + Big.ExtraWeight);
2160 addSuccessorWithWeight(SwitchBB, Default,
2161 // The default destination is the first successor in IR.
2162 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2164 // Insert the true branch.
2165 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2166 getControlRoot(), Cond,
2167 DAG.getBasicBlock(Small.BB));
2169 // Insert the false branch.
2170 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2171 DAG.getBasicBlock(Default));
2173 DAG.setRoot(BrCond);
2179 // Order cases by weight so the most likely case will be checked first.
2180 uint32_t UnhandledWeights = 0;
2182 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2183 uint32_t IWeight = I->ExtraWeight;
2184 UnhandledWeights += IWeight;
2185 for (CaseItr J = CR.Range.first; J < I; ++J) {
2186 uint32_t JWeight = J->ExtraWeight;
2187 if (IWeight > JWeight)
2192 // Rearrange the case blocks so that the last one falls through if possible.
2193 Case &BackCase = *(CR.Range.second-1);
2194 if (Size > 1 && NextMBB && Default != NextMBB && BackCase.BB != NextMBB) {
2195 // The last case block won't fall through into 'NextMBB' if we emit the
2196 // branches in this order. See if rearranging a case value would help.
2197 // We start at the bottom as it's the case with the least weight.
2198 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2199 if (I->BB == NextMBB) {
2200 std::swap(*I, BackCase);
2205 // Create a CaseBlock record representing a conditional branch to
2206 // the Case's target mbb if the value being switched on SV is equal
2208 MachineBasicBlock *CurBlock = CR.CaseBB;
2209 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2210 MachineBasicBlock *FallThrough;
2212 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2213 CurMF->insert(BBI, FallThrough);
2215 // Put SV in a virtual register to make it available from the new blocks.
2216 ExportFromCurrentBlock(SV);
2218 // If the last case doesn't match, go to the default block.
2219 FallThrough = Default;
2222 const Value *RHS, *LHS, *MHS;
2224 if (I->High == I->Low) {
2225 // This is just small small case range :) containing exactly 1 case
2227 LHS = SV; RHS = I->High; MHS = nullptr;
2230 LHS = I->Low; MHS = SV; RHS = I->High;
2233 // The false weight should be sum of all un-handled cases.
2234 UnhandledWeights -= I->ExtraWeight;
2235 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2237 /* trueweight */ I->ExtraWeight,
2238 /* falseweight */ UnhandledWeights);
2240 // If emitting the first comparison, just call visitSwitchCase to emit the
2241 // code into the current block. Otherwise, push the CaseBlock onto the
2242 // vector to be later processed by SDISel, and insert the node's MBB
2243 // before the next MBB.
2244 if (CurBlock == SwitchBB)
2245 visitSwitchCase(CB, SwitchBB);
2247 SwitchCases.push_back(CB);
2249 CurBlock = FallThrough;
2255 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2256 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2257 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2260 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2261 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2262 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2263 return (LastExt - FirstExt + 1ULL);
2266 /// handleJTSwitchCase - Emit jumptable for current switch case range
2267 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2268 CaseRecVector &WorkList,
2270 MachineBasicBlock *Default,
2271 MachineBasicBlock *SwitchBB) {
2272 Case& FrontCase = *CR.Range.first;
2273 Case& BackCase = *(CR.Range.second-1);
2275 const APInt &First = FrontCase.Low->getValue();
2276 const APInt &Last = BackCase.High->getValue();
2278 APInt TSize(First.getBitWidth(), 0);
2279 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2282 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2283 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2286 APInt Range = ComputeRange(First, Last);
2287 // The density is TSize / Range. Require at least 40%.
2288 // It should not be possible for IntTSize to saturate for sane code, but make
2289 // sure we handle Range saturation correctly.
2290 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2291 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2292 if (IntTSize * 10 < IntRange * 4)
2295 DEBUG(dbgs() << "Lowering jump table\n"
2296 << "First entry: " << First << ". Last entry: " << Last << '\n'
2297 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2299 // Get the MachineFunction which holds the current MBB. This is used when
2300 // inserting any additional MBBs necessary to represent the switch.
2301 MachineFunction *CurMF = FuncInfo.MF;
2303 // Figure out which block is immediately after the current one.
2304 MachineFunction::iterator BBI = CR.CaseBB;
2307 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2309 // Create a new basic block to hold the code for loading the address
2310 // of the jump table, and jumping to it. Update successor information;
2311 // we will either branch to the default case for the switch, or the jump
2313 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2314 CurMF->insert(BBI, JumpTableBB);
2316 addSuccessorWithWeight(CR.CaseBB, Default);
2317 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2319 // Build a vector of destination BBs, corresponding to each target
2320 // of the jump table. If the value of the jump table slot corresponds to
2321 // a case statement, push the case's BB onto the vector, otherwise, push
2323 std::vector<MachineBasicBlock*> DestBBs;
2325 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2326 const APInt &Low = I->Low->getValue();
2327 const APInt &High = I->High->getValue();
2329 if (Low.sle(TEI) && TEI.sle(High)) {
2330 DestBBs.push_back(I->BB);
2334 DestBBs.push_back(Default);
2338 // Calculate weight for each unique destination in CR.
2339 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2341 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2342 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2343 DestWeights.find(I->BB);
2344 if (Itr != DestWeights.end())
2345 Itr->second += I->ExtraWeight;
2347 DestWeights[I->BB] = I->ExtraWeight;
2350 // Update successor info. Add one edge to each unique successor.
2351 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2352 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2353 E = DestBBs.end(); I != E; ++I) {
2354 if (!SuccsHandled[(*I)->getNumber()]) {
2355 SuccsHandled[(*I)->getNumber()] = true;
2356 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2357 DestWeights.find(*I);
2358 addSuccessorWithWeight(JumpTableBB, *I,
2359 Itr != DestWeights.end() ? Itr->second : 0);
2363 // Create a jump table index for this jump table.
2364 unsigned JTEncoding = TLI.getJumpTableEncoding();
2365 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2366 ->createJumpTableIndex(DestBBs);
2368 // Set the jump table information so that we can codegen it as a second
2369 // MachineBasicBlock
2370 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2371 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2372 if (CR.CaseBB == SwitchBB)
2373 visitJumpTableHeader(JT, JTH, SwitchBB);
2375 JTCases.push_back(JumpTableBlock(JTH, JT));
2379 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2381 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2382 CaseRecVector& WorkList,
2384 MachineBasicBlock* SwitchBB) {
2385 Case& FrontCase = *CR.Range.first;
2386 Case& BackCase = *(CR.Range.second-1);
2388 // Size is the number of Cases represented by this range.
2389 unsigned Size = CR.Range.second - CR.Range.first;
2391 const APInt &First = FrontCase.Low->getValue();
2392 const APInt &Last = BackCase.High->getValue();
2394 CaseItr Pivot = CR.Range.first + Size/2;
2396 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2397 // (heuristically) allow us to emit JumpTable's later.
2398 APInt TSize(First.getBitWidth(), 0);
2399 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2403 APInt LSize = FrontCase.size();
2404 APInt RSize = TSize-LSize;
2405 DEBUG(dbgs() << "Selecting best pivot: \n"
2406 << "First: " << First << ", Last: " << Last <<'\n'
2407 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2408 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2409 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2411 const APInt &LEnd = I->High->getValue();
2412 const APInt &RBegin = J->Low->getValue();
2413 APInt Range = ComputeRange(LEnd, RBegin);
2414 assert((Range - 2ULL).isNonNegative() &&
2415 "Invalid case distance");
2416 // Use volatile double here to avoid excess precision issues on some hosts,
2417 // e.g. that use 80-bit X87 registers.
2418 // Only consider the density of sub-ranges that actually have sufficient
2419 // entries to be lowered as a jump table.
2420 volatile double LDensity =
2421 LSize.ult(TLI.getMinimumJumpTableEntries())
2423 : LSize.roundToDouble() / (LEnd - First + 1ULL).roundToDouble();
2424 volatile double RDensity =
2425 RSize.ult(TLI.getMinimumJumpTableEntries())
2427 : RSize.roundToDouble() / (Last - RBegin + 1ULL).roundToDouble();
2428 volatile double Metric = Range.logBase2() * (LDensity + RDensity);
2429 // Should always split in some non-trivial place
2430 DEBUG(dbgs() <<"=>Step\n"
2431 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2432 << "LDensity: " << LDensity
2433 << ", RDensity: " << RDensity << '\n'
2434 << "Metric: " << Metric << '\n');
2435 if (FMetric < Metric) {
2438 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2445 if (FMetric == 0 || !areJTsAllowed(TLI))
2446 Pivot = CR.Range.first + Size/2;
2447 splitSwitchCase(CR, Pivot, WorkList, SV, SwitchBB);
2451 void SelectionDAGBuilder::splitSwitchCase(CaseRec &CR, CaseItr Pivot,
2452 CaseRecVector &WorkList,
2454 MachineBasicBlock *SwitchBB) {
2455 // Get the MachineFunction which holds the current MBB. This is used when
2456 // inserting any additional MBBs necessary to represent the switch.
2457 MachineFunction *CurMF = FuncInfo.MF;
2459 // Figure out which block is immediately after the current one.
2460 MachineFunction::iterator BBI = CR.CaseBB;
2463 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2465 CaseRange LHSR(CR.Range.first, Pivot);
2466 CaseRange RHSR(Pivot, CR.Range.second);
2467 const ConstantInt *C = Pivot->Low;
2468 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2470 // We know that we branch to the LHS if the Value being switched on is
2471 // less than the Pivot value, C. We use this to optimize our binary
2472 // tree a bit, by recognizing that if SV is greater than or equal to the
2473 // LHS's Case Value, and that Case Value is exactly one less than the
2474 // Pivot's Value, then we can branch directly to the LHS's Target,
2475 // rather than creating a leaf node for it.
2476 if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE &&
2477 C->getValue() == (CR.GE->getValue() + 1LL)) {
2478 TrueBB = LHSR.first->BB;
2480 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2481 CurMF->insert(BBI, TrueBB);
2482 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2484 // Put SV in a virtual register to make it available from the new blocks.
2485 ExportFromCurrentBlock(SV);
2488 // Similar to the optimization above, if the Value being switched on is
2489 // known to be less than the Constant CR.LT, and the current Case Value
2490 // is CR.LT - 1, then we can branch directly to the target block for
2491 // the current Case Value, rather than emitting a RHS leaf node for it.
2492 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2493 RHSR.first->Low->getValue() == (CR.LT->getValue() - 1LL)) {
2494 FalseBB = RHSR.first->BB;
2496 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2497 CurMF->insert(BBI, FalseBB);
2498 WorkList.push_back(CaseRec(FalseBB, CR.LT, C, RHSR));
2500 // Put SV in a virtual register to make it available from the new blocks.
2501 ExportFromCurrentBlock(SV);
2504 // Create a CaseBlock record representing a conditional branch to
2505 // the LHS node if the value being switched on SV is less than C.
2506 // Otherwise, branch to LHS.
2507 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2509 if (CR.CaseBB == SwitchBB)
2510 visitSwitchCase(CB, SwitchBB);
2512 SwitchCases.push_back(CB);
2515 /// handleBitTestsSwitchCase - if current case range has few destination and
2516 /// range span less, than machine word bitwidth, encode case range into series
2517 /// of masks and emit bit tests with these masks.
2518 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2519 CaseRecVector& WorkList,
2521 MachineBasicBlock* Default,
2522 MachineBasicBlock* SwitchBB) {
2523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2524 EVT PTy = TLI.getPointerTy();
2525 unsigned IntPtrBits = PTy.getSizeInBits();
2527 Case& FrontCase = *CR.Range.first;
2528 Case& BackCase = *(CR.Range.second-1);
2530 // Get the MachineFunction which holds the current MBB. This is used when
2531 // inserting any additional MBBs necessary to represent the switch.
2532 MachineFunction *CurMF = FuncInfo.MF;
2534 // If target does not have legal shift left, do not emit bit tests at all.
2535 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2539 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2540 // Single case counts one, case range - two.
2541 numCmps += (I->Low == I->High ? 1 : 2);
2544 // Count unique destinations
2545 SmallSet<MachineBasicBlock*, 4> Dests;
2546 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2547 Dests.insert(I->BB);
2548 if (Dests.size() > 3)
2549 // Don't bother the code below, if there are too much unique destinations
2552 DEBUG(dbgs() << "Total number of unique destinations: "
2553 << Dests.size() << '\n'
2554 << "Total number of comparisons: " << numCmps << '\n');
2556 // Compute span of values.
2557 const APInt& minValue = FrontCase.Low->getValue();
2558 const APInt& maxValue = BackCase.High->getValue();
2559 APInt cmpRange = maxValue - minValue;
2561 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2562 << "Low bound: " << minValue << '\n'
2563 << "High bound: " << maxValue << '\n');
2565 if (cmpRange.uge(IntPtrBits) ||
2566 (!(Dests.size() == 1 && numCmps >= 3) &&
2567 !(Dests.size() == 2 && numCmps >= 5) &&
2568 !(Dests.size() >= 3 && numCmps >= 6)))
2571 DEBUG(dbgs() << "Emitting bit tests\n");
2572 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2574 // Optimize the case where all the case values fit in a
2575 // word without having to subtract minValue. In this case,
2576 // we can optimize away the subtraction.
2577 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2578 cmpRange = maxValue;
2580 lowBound = minValue;
2583 CaseBitsVector CasesBits;
2584 unsigned i, count = 0;
2586 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2587 MachineBasicBlock* Dest = I->BB;
2588 for (i = 0; i < count; ++i)
2589 if (Dest == CasesBits[i].BB)
2593 assert((count < 3) && "Too much destinations to test!");
2594 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2598 const APInt& lowValue = I->Low->getValue();
2599 const APInt& highValue = I->High->getValue();
2601 uint64_t lo = (lowValue - lowBound).getZExtValue();
2602 uint64_t hi = (highValue - lowBound).getZExtValue();
2603 CasesBits[i].ExtraWeight += I->ExtraWeight;
2605 for (uint64_t j = lo; j <= hi; j++) {
2606 CasesBits[i].Mask |= 1ULL << j;
2607 CasesBits[i].Bits++;
2611 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2615 // Figure out which block is immediately after the current one.
2616 MachineFunction::iterator BBI = CR.CaseBB;
2619 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2621 DEBUG(dbgs() << "Cases:\n");
2622 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2623 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2624 << ", Bits: " << CasesBits[i].Bits
2625 << ", BB: " << CasesBits[i].BB << '\n');
2627 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2628 CurMF->insert(BBI, CaseBB);
2629 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2631 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2633 // Put SV in a virtual register to make it available from the new blocks.
2634 ExportFromCurrentBlock(SV);
2637 BitTestBlock BTB(lowBound, cmpRange, SV,
2638 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2639 CR.CaseBB, Default, std::move(BTC));
2641 if (CR.CaseBB == SwitchBB)
2642 visitBitTestHeader(BTB, SwitchBB);
2644 BitTestCases.push_back(std::move(BTB));
2649 void SelectionDAGBuilder::Clusterify(CaseVector &Cases, const SwitchInst *SI) {
2650 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2652 // Extract cases from the switch and sort them.
2653 typedef std::pair<const ConstantInt*, unsigned> CasePair;
2654 std::vector<CasePair> Sorted;
2655 Sorted.reserve(SI->getNumCases());
2656 for (auto I : SI->cases())
2657 Sorted.push_back(std::make_pair(I.getCaseValue(), I.getSuccessorIndex()));
2658 std::sort(Sorted.begin(), Sorted.end(), [](CasePair a, CasePair b) {
2659 return a.first->getValue().slt(b.first->getValue());
2662 // Merge adjacent cases with the same destination, build Cases vector.
2663 assert(Cases.empty() && "Cases should be empty before Clusterify;");
2664 Cases.reserve(SI->getNumCases());
2665 MachineBasicBlock *PreviousSucc = nullptr;
2666 for (CasePair &CP : Sorted) {
2667 const ConstantInt *CaseVal = CP.first;
2668 unsigned SuccIndex = CP.second;
2669 MachineBasicBlock *Succ = FuncInfo.MBBMap[SI->getSuccessor(SuccIndex)];
2670 uint32_t Weight = BPI ? BPI->getEdgeWeight(SI->getParent(), SuccIndex) : 0;
2672 if (PreviousSucc == Succ &&
2673 (CaseVal->getValue() - Cases.back().High->getValue()) == 1) {
2674 // If this case has the same successor and is a neighbour, merge it into
2675 // the previous cluster.
2676 Cases.back().High = CaseVal;
2677 Cases.back().ExtraWeight += Weight;
2679 Cases.push_back(Case(CaseVal, CaseVal, Succ, Weight));
2682 PreviousSucc = Succ;
2687 for (auto &I : Cases)
2688 // A range counts double, since it requires two compares.
2689 numCmps += I.Low != I.High ? 2 : 1;
2691 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2692 << ". Total compares: " << numCmps << '\n';
2696 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2697 MachineBasicBlock *Last) {
2699 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2700 if (JTCases[i].first.HeaderBB == First)
2701 JTCases[i].first.HeaderBB = Last;
2703 // Update BitTestCases.
2704 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2705 if (BitTestCases[i].Parent == First)
2706 BitTestCases[i].Parent = Last;
2709 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2710 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2712 // Create a vector of Cases, sorted so that we can efficiently create a binary
2713 // search tree from them.
2715 Clusterify(Cases, &SI);
2717 // Get the default destination MBB.
2718 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2720 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2722 // Replace an unreachable default destination with the most popular case
2724 DenseMap<const BasicBlock *, unsigned> Popularity;
2725 unsigned MaxPop = 0;
2726 const BasicBlock *MaxBB = nullptr;
2727 for (auto I : SI.cases()) {
2728 const BasicBlock *BB = I.getCaseSuccessor();
2729 if (++Popularity[BB] > MaxPop) {
2730 MaxPop = Popularity[BB];
2738 Default = FuncInfo.MBBMap[MaxBB];
2740 // Remove cases that were pointing to the destination that is now the default.
2741 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2742 [&](const Case &C) { return C.BB == Default; }),
2746 // If there is only the default destination, go there directly.
2747 if (Cases.empty()) {
2748 // Update machine-CFG edges.
2749 SwitchMBB->addSuccessor(Default);
2751 // If this is not a fall-through branch, emit the branch.
2752 if (Default != NextBlock(SwitchMBB)) {
2753 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2754 getControlRoot(), DAG.getBasicBlock(Default)));
2759 // Get the Value to be switched on.
2760 const Value *SV = SI.getCondition();
2762 // Push the initial CaseRec onto the worklist
2763 CaseRecVector WorkList;
2764 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2765 CaseRange(Cases.begin(),Cases.end())));
2767 while (!WorkList.empty()) {
2768 // Grab a record representing a case range to process off the worklist
2769 CaseRec CR = WorkList.back();
2770 WorkList.pop_back();
2772 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2775 // If the range has few cases (two or less) emit a series of specific
2777 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2780 // If the switch has more than N blocks, and is at least 40% dense, and the
2781 // target supports indirect branches, then emit a jump table rather than
2782 // lowering the switch to a binary tree of conditional branches.
2783 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2784 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2787 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2788 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2789 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2793 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2794 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2796 // Update machine-CFG edges with unique successors.
2797 SmallSet<BasicBlock*, 32> Done;
2798 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2799 BasicBlock *BB = I.getSuccessor(i);
2800 bool Inserted = Done.insert(BB).second;
2804 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2805 addSuccessorWithWeight(IndirectBrMBB, Succ);
2808 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2809 MVT::Other, getControlRoot(),
2810 getValue(I.getAddress())));
2813 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2814 if (DAG.getTarget().Options.TrapUnreachable)
2815 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2818 void SelectionDAGBuilder::visitFSub(const User &I) {
2819 // -0.0 - X --> fneg
2820 Type *Ty = I.getType();
2821 if (isa<Constant>(I.getOperand(0)) &&
2822 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2823 SDValue Op2 = getValue(I.getOperand(1));
2824 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2825 Op2.getValueType(), Op2));
2829 visitBinary(I, ISD::FSUB);
2832 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2833 SDValue Op1 = getValue(I.getOperand(0));
2834 SDValue Op2 = getValue(I.getOperand(1));
2839 if (const OverflowingBinaryOperator *OFBinOp =
2840 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2841 nuw = OFBinOp->hasNoUnsignedWrap();
2842 nsw = OFBinOp->hasNoSignedWrap();
2844 if (const PossiblyExactOperator *ExactOp =
2845 dyn_cast<const PossiblyExactOperator>(&I))
2846 exact = ExactOp->isExact();
2848 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2849 Op1, Op2, nuw, nsw, exact);
2850 setValue(&I, BinNodeValue);
2853 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2854 SDValue Op1 = getValue(I.getOperand(0));
2855 SDValue Op2 = getValue(I.getOperand(1));
2858 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2860 // Coerce the shift amount to the right type if we can.
2861 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2862 unsigned ShiftSize = ShiftTy.getSizeInBits();
2863 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2864 SDLoc DL = getCurSDLoc();
2866 // If the operand is smaller than the shift count type, promote it.
2867 if (ShiftSize > Op2Size)
2868 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2870 // If the operand is larger than the shift count type but the shift
2871 // count type has enough bits to represent any shift value, truncate
2872 // it now. This is a common case and it exposes the truncate to
2873 // optimization early.
2874 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2875 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2876 // Otherwise we'll need to temporarily settle for some other convenient
2877 // type. Type legalization will make adjustments once the shiftee is split.
2879 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2886 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2888 if (const OverflowingBinaryOperator *OFBinOp =
2889 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2890 nuw = OFBinOp->hasNoUnsignedWrap();
2891 nsw = OFBinOp->hasNoSignedWrap();
2893 if (const PossiblyExactOperator *ExactOp =
2894 dyn_cast<const PossiblyExactOperator>(&I))
2895 exact = ExactOp->isExact();
2898 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2903 void SelectionDAGBuilder::visitSDiv(const User &I) {
2904 SDValue Op1 = getValue(I.getOperand(0));
2905 SDValue Op2 = getValue(I.getOperand(1));
2907 // Turn exact SDivs into multiplications.
2908 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2910 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2911 !isa<ConstantSDNode>(Op1) &&
2912 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2913 setValue(&I, DAG.getTargetLoweringInfo()
2914 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2916 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2920 void SelectionDAGBuilder::visitICmp(const User &I) {
2921 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2922 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2923 predicate = IC->getPredicate();
2924 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2925 predicate = ICmpInst::Predicate(IC->getPredicate());
2926 SDValue Op1 = getValue(I.getOperand(0));
2927 SDValue Op2 = getValue(I.getOperand(1));
2928 ISD::CondCode Opcode = getICmpCondCode(predicate);
2930 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2931 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2934 void SelectionDAGBuilder::visitFCmp(const User &I) {
2935 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2936 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2937 predicate = FC->getPredicate();
2938 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2939 predicate = FCmpInst::Predicate(FC->getPredicate());
2940 SDValue Op1 = getValue(I.getOperand(0));
2941 SDValue Op2 = getValue(I.getOperand(1));
2942 ISD::CondCode Condition = getFCmpCondCode(predicate);
2943 if (TM.Options.NoNaNsFPMath)
2944 Condition = getFCmpCodeWithoutNaN(Condition);
2945 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2946 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2949 void SelectionDAGBuilder::visitSelect(const User &I) {
2950 SmallVector<EVT, 4> ValueVTs;
2951 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2952 unsigned NumValues = ValueVTs.size();
2953 if (NumValues == 0) return;
2955 SmallVector<SDValue, 4> Values(NumValues);
2956 SDValue Cond = getValue(I.getOperand(0));
2957 SDValue TrueVal = getValue(I.getOperand(1));
2958 SDValue FalseVal = getValue(I.getOperand(2));
2959 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2960 ISD::VSELECT : ISD::SELECT;
2962 for (unsigned i = 0; i != NumValues; ++i)
2963 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2964 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2966 SDValue(TrueVal.getNode(),
2967 TrueVal.getResNo() + i),
2968 SDValue(FalseVal.getNode(),
2969 FalseVal.getResNo() + i));
2971 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2972 DAG.getVTList(ValueVTs), Values));
2975 void SelectionDAGBuilder::visitTrunc(const User &I) {
2976 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2977 SDValue N = getValue(I.getOperand(0));
2978 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2979 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2982 void SelectionDAGBuilder::visitZExt(const User &I) {
2983 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2984 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2985 SDValue N = getValue(I.getOperand(0));
2986 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2987 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2990 void SelectionDAGBuilder::visitSExt(const User &I) {
2991 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2992 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2993 SDValue N = getValue(I.getOperand(0));
2994 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2995 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2998 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2999 // FPTrunc is never a no-op cast, no need to check
3000 SDValue N = getValue(I.getOperand(0));
3001 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3002 EVT DestVT = TLI.getValueType(I.getType());
3003 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
3004 DAG.getTargetConstant(0, TLI.getPointerTy())));
3007 void SelectionDAGBuilder::visitFPExt(const User &I) {
3008 // FPExt is never a no-op cast, no need to check
3009 SDValue N = getValue(I.getOperand(0));
3010 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3011 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3014 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3015 // FPToUI is never a no-op cast, no need to check
3016 SDValue N = getValue(I.getOperand(0));
3017 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3018 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3021 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3022 // FPToSI is never a no-op cast, no need to check
3023 SDValue N = getValue(I.getOperand(0));
3024 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3025 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3028 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3029 // UIToFP is never a no-op cast, no need to check
3030 SDValue N = getValue(I.getOperand(0));
3031 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3032 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3035 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3036 // SIToFP is never a no-op cast, no need to check
3037 SDValue N = getValue(I.getOperand(0));
3038 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3039 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3042 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3043 // What to do depends on the size of the integer and the size of the pointer.
3044 // We can either truncate, zero extend, or no-op, accordingly.
3045 SDValue N = getValue(I.getOperand(0));
3046 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3047 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3050 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3051 // What to do depends on the size of the integer and the size of the pointer.
3052 // We can either truncate, zero extend, or no-op, accordingly.
3053 SDValue N = getValue(I.getOperand(0));
3054 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3055 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3058 void SelectionDAGBuilder::visitBitCast(const User &I) {
3059 SDValue N = getValue(I.getOperand(0));
3060 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3062 // BitCast assures us that source and destination are the same size so this is
3063 // either a BITCAST or a no-op.
3064 if (DestVT != N.getValueType())
3065 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3066 DestVT, N)); // convert types.
3067 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3068 // might fold any kind of constant expression to an integer constant and that
3069 // is not what we are looking for. Only regcognize a bitcast of a genuine
3070 // constant integer as an opaque constant.
3071 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3072 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3075 setValue(&I, N); // noop cast.
3078 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3080 const Value *SV = I.getOperand(0);
3081 SDValue N = getValue(SV);
3082 EVT DestVT = TLI.getValueType(I.getType());
3084 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3085 unsigned DestAS = I.getType()->getPointerAddressSpace();
3087 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3088 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3093 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3094 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3095 SDValue InVec = getValue(I.getOperand(0));
3096 SDValue InVal = getValue(I.getOperand(1));
3097 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3098 getCurSDLoc(), TLI.getVectorIdxTy());
3099 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3100 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3103 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3104 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3105 SDValue InVec = getValue(I.getOperand(0));
3106 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3107 getCurSDLoc(), TLI.getVectorIdxTy());
3108 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3109 TLI.getValueType(I.getType()), InVec, InIdx));
3112 // Utility for visitShuffleVector - Return true if every element in Mask,
3113 // beginning from position Pos and ending in Pos+Size, falls within the
3114 // specified sequential range [L, L+Pos). or is undef.
3115 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3116 unsigned Pos, unsigned Size, int Low) {
3117 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3118 if (Mask[i] >= 0 && Mask[i] != Low)
3123 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3124 SDValue Src1 = getValue(I.getOperand(0));
3125 SDValue Src2 = getValue(I.getOperand(1));
3127 SmallVector<int, 8> Mask;
3128 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3129 unsigned MaskNumElts = Mask.size();
3131 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3132 EVT VT = TLI.getValueType(I.getType());
3133 EVT SrcVT = Src1.getValueType();
3134 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3136 if (SrcNumElts == MaskNumElts) {
3137 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3142 // Normalize the shuffle vector since mask and vector length don't match.
3143 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3144 // Mask is longer than the source vectors and is a multiple of the source
3145 // vectors. We can use concatenate vector to make the mask and vectors
3147 if (SrcNumElts*2 == MaskNumElts) {
3148 // First check for Src1 in low and Src2 in high
3149 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3150 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3151 // The shuffle is concatenating two vectors together.
3152 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3156 // Then check for Src2 in low and Src1 in high
3157 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3158 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3159 // The shuffle is concatenating two vectors together.
3160 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3166 // Pad both vectors with undefs to make them the same length as the mask.
3167 unsigned NumConcat = MaskNumElts / SrcNumElts;
3168 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3169 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3170 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3172 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3173 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3177 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3178 getCurSDLoc(), VT, MOps1);
3179 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3180 getCurSDLoc(), VT, MOps2);
3182 // Readjust mask for new input vector length.
3183 SmallVector<int, 8> MappedOps;
3184 for (unsigned i = 0; i != MaskNumElts; ++i) {
3186 if (Idx >= (int)SrcNumElts)
3187 Idx -= SrcNumElts - MaskNumElts;
3188 MappedOps.push_back(Idx);
3191 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3196 if (SrcNumElts > MaskNumElts) {
3197 // Analyze the access pattern of the vector to see if we can extract
3198 // two subvectors and do the shuffle. The analysis is done by calculating
3199 // the range of elements the mask access on both vectors.
3200 int MinRange[2] = { static_cast<int>(SrcNumElts),
3201 static_cast<int>(SrcNumElts)};
3202 int MaxRange[2] = {-1, -1};
3204 for (unsigned i = 0; i != MaskNumElts; ++i) {
3210 if (Idx >= (int)SrcNumElts) {
3214 if (Idx > MaxRange[Input])
3215 MaxRange[Input] = Idx;
3216 if (Idx < MinRange[Input])
3217 MinRange[Input] = Idx;
3220 // Check if the access is smaller than the vector size and can we find
3221 // a reasonable extract index.
3222 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3224 int StartIdx[2]; // StartIdx to extract from
3225 for (unsigned Input = 0; Input < 2; ++Input) {
3226 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3227 RangeUse[Input] = 0; // Unused
3228 StartIdx[Input] = 0;
3232 // Find a good start index that is a multiple of the mask length. Then
3233 // see if the rest of the elements are in range.
3234 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3235 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3236 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3237 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3240 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3241 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3244 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3245 // Extract appropriate subvector and generate a vector shuffle
3246 for (unsigned Input = 0; Input < 2; ++Input) {
3247 SDValue &Src = Input == 0 ? Src1 : Src2;
3248 if (RangeUse[Input] == 0)
3249 Src = DAG.getUNDEF(VT);
3252 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3253 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3256 // Calculate new mask.
3257 SmallVector<int, 8> MappedOps;
3258 for (unsigned i = 0; i != MaskNumElts; ++i) {
3261 if (Idx < (int)SrcNumElts)
3264 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3266 MappedOps.push_back(Idx);
3269 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3275 // We can't use either concat vectors or extract subvectors so fall back to
3276 // replacing the shuffle with extract and build vector.
3277 // to insert and build vector.
3278 EVT EltVT = VT.getVectorElementType();
3279 EVT IdxVT = TLI.getVectorIdxTy();
3280 SmallVector<SDValue,8> Ops;
3281 for (unsigned i = 0; i != MaskNumElts; ++i) {
3286 Res = DAG.getUNDEF(EltVT);
3288 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3289 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3291 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3292 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3298 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3301 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3302 const Value *Op0 = I.getOperand(0);
3303 const Value *Op1 = I.getOperand(1);
3304 Type *AggTy = I.getType();
3305 Type *ValTy = Op1->getType();
3306 bool IntoUndef = isa<UndefValue>(Op0);
3307 bool FromUndef = isa<UndefValue>(Op1);
3309 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3312 SmallVector<EVT, 4> AggValueVTs;
3313 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3314 SmallVector<EVT, 4> ValValueVTs;
3315 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3317 unsigned NumAggValues = AggValueVTs.size();
3318 unsigned NumValValues = ValValueVTs.size();
3319 SmallVector<SDValue, 4> Values(NumAggValues);
3321 // Ignore an insertvalue that produces an empty object
3322 if (!NumAggValues) {
3323 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3327 SDValue Agg = getValue(Op0);
3329 // Copy the beginning value(s) from the original aggregate.
3330 for (; i != LinearIndex; ++i)
3331 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3332 SDValue(Agg.getNode(), Agg.getResNo() + i);
3333 // Copy values from the inserted value(s).
3335 SDValue Val = getValue(Op1);
3336 for (; i != LinearIndex + NumValValues; ++i)
3337 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3338 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3340 // Copy remaining value(s) from the original aggregate.
3341 for (; i != NumAggValues; ++i)
3342 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3343 SDValue(Agg.getNode(), Agg.getResNo() + i);
3345 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3346 DAG.getVTList(AggValueVTs), Values));
3349 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3350 const Value *Op0 = I.getOperand(0);
3351 Type *AggTy = Op0->getType();
3352 Type *ValTy = I.getType();
3353 bool OutOfUndef = isa<UndefValue>(Op0);
3355 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3358 SmallVector<EVT, 4> ValValueVTs;
3359 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3361 unsigned NumValValues = ValValueVTs.size();
3363 // Ignore a extractvalue that produces an empty object
3364 if (!NumValValues) {
3365 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3369 SmallVector<SDValue, 4> Values(NumValValues);
3371 SDValue Agg = getValue(Op0);
3372 // Copy out the selected value(s).
3373 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3374 Values[i - LinearIndex] =
3376 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3377 SDValue(Agg.getNode(), Agg.getResNo() + i);
3379 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3380 DAG.getVTList(ValValueVTs), Values));
3383 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3384 Value *Op0 = I.getOperand(0);
3385 // Note that the pointer operand may be a vector of pointers. Take the scalar
3386 // element which holds a pointer.
3387 Type *Ty = Op0->getType()->getScalarType();
3388 unsigned AS = Ty->getPointerAddressSpace();
3389 SDValue N = getValue(Op0);
3391 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3393 const Value *Idx = *OI;
3394 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3395 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3398 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3399 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3400 DAG.getConstant(Offset, N.getValueType()));
3403 Ty = StTy->getElementType(Field);
3405 Ty = cast<SequentialType>(Ty)->getElementType();
3406 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
3407 unsigned PtrSize = PtrTy.getSizeInBits();
3408 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3410 // If this is a constant subscript, handle it quickly.
3411 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
3414 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3415 SDValue OffsVal = DAG.getConstant(Offs, PtrTy);
3416 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal);
3420 // N = N + Idx * ElementSize;
3421 SDValue IdxN = getValue(Idx);
3423 // If the index is smaller or larger than intptr_t, truncate or extend
3425 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3427 // If this is a multiply by a power of two, turn it into a shl
3428 // immediately. This is a very common case.
3429 if (ElementSize != 1) {
3430 if (ElementSize.isPowerOf2()) {
3431 unsigned Amt = ElementSize.logBase2();
3432 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3433 N.getValueType(), IdxN,
3434 DAG.getConstant(Amt, IdxN.getValueType()));
3436 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3437 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3438 N.getValueType(), IdxN, Scale);
3442 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3443 N.getValueType(), N, IdxN);
3450 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3451 // If this is a fixed sized alloca in the entry block of the function,
3452 // allocate it statically on the stack.
3453 if (FuncInfo.StaticAllocaMap.count(&I))
3454 return; // getValue will auto-populate this.
3456 Type *Ty = I.getAllocatedType();
3457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3458 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3460 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3463 SDValue AllocSize = getValue(I.getArraySize());
3465 EVT IntPtr = TLI.getPointerTy();
3466 if (AllocSize.getValueType() != IntPtr)
3467 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3469 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3471 DAG.getConstant(TySize, IntPtr));
3473 // Handle alignment. If the requested alignment is less than or equal to
3474 // the stack alignment, ignore it. If the size is greater than or equal to
3475 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3476 unsigned StackAlign =
3477 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3478 if (Align <= StackAlign)
3481 // Round the size of the allocation up to the stack alignment size
3482 // by add SA-1 to the size.
3483 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3484 AllocSize.getValueType(), AllocSize,
3485 DAG.getIntPtrConstant(StackAlign-1));
3487 // Mask out the low bits for alignment purposes.
3488 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3489 AllocSize.getValueType(), AllocSize,
3490 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3492 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3493 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3494 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3496 DAG.setRoot(DSA.getValue(1));
3498 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3501 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3503 return visitAtomicLoad(I);
3505 const Value *SV = I.getOperand(0);
3506 SDValue Ptr = getValue(SV);
3508 Type *Ty = I.getType();
3510 bool isVolatile = I.isVolatile();
3511 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3512 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3513 unsigned Alignment = I.getAlignment();
3516 I.getAAMetadata(AAInfo);
3517 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3520 SmallVector<EVT, 4> ValueVTs;
3521 SmallVector<uint64_t, 4> Offsets;
3522 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3523 unsigned NumValues = ValueVTs.size();
3528 bool ConstantMemory = false;
3529 if (isVolatile || NumValues > MaxParallelChains)
3530 // Serialize volatile loads with other side effects.
3532 else if (AA->pointsToConstantMemory(
3533 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3534 // Do not serialize (non-volatile) loads of constant memory with anything.
3535 Root = DAG.getEntryNode();
3536 ConstantMemory = true;
3538 // Do not serialize non-volatile loads against each other.
3539 Root = DAG.getRoot();
3543 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3545 SmallVector<SDValue, 4> Values(NumValues);
3546 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3548 EVT PtrVT = Ptr.getValueType();
3549 unsigned ChainI = 0;
3550 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3551 // Serializing loads here may result in excessive register pressure, and
3552 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3553 // could recover a bit by hoisting nodes upward in the chain by recognizing
3554 // they are side-effect free or do not alias. The optimizer should really
3555 // avoid this case by converting large object/array copies to llvm.memcpy
3556 // (MaxParallelChains should always remain as failsafe).
3557 if (ChainI == MaxParallelChains) {
3558 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3559 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3560 makeArrayRef(Chains.data(), ChainI));
3564 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3566 DAG.getConstant(Offsets[i], PtrVT));
3567 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3568 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3569 isNonTemporal, isInvariant, Alignment, AAInfo,
3573 Chains[ChainI] = L.getValue(1);
3576 if (!ConstantMemory) {
3577 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3578 makeArrayRef(Chains.data(), ChainI));
3582 PendingLoads.push_back(Chain);
3585 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3586 DAG.getVTList(ValueVTs), Values));
3589 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3591 return visitAtomicStore(I);
3593 const Value *SrcV = I.getOperand(0);
3594 const Value *PtrV = I.getOperand(1);
3596 SmallVector<EVT, 4> ValueVTs;
3597 SmallVector<uint64_t, 4> Offsets;
3598 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3599 ValueVTs, &Offsets);
3600 unsigned NumValues = ValueVTs.size();
3604 // Get the lowered operands. Note that we do this after
3605 // checking if NumResults is zero, because with zero results
3606 // the operands won't have values in the map.
3607 SDValue Src = getValue(SrcV);
3608 SDValue Ptr = getValue(PtrV);
3610 SDValue Root = getRoot();
3611 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3613 EVT PtrVT = Ptr.getValueType();
3614 bool isVolatile = I.isVolatile();
3615 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3616 unsigned Alignment = I.getAlignment();
3619 I.getAAMetadata(AAInfo);
3621 unsigned ChainI = 0;
3622 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3623 // See visitLoad comments.
3624 if (ChainI == MaxParallelChains) {
3625 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3626 makeArrayRef(Chains.data(), ChainI));
3630 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3631 DAG.getConstant(Offsets[i], PtrVT));
3632 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3633 SDValue(Src.getNode(), Src.getResNo() + i),
3634 Add, MachinePointerInfo(PtrV, Offsets[i]),
3635 isVolatile, isNonTemporal, Alignment, AAInfo);
3636 Chains[ChainI] = St;
3639 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3640 makeArrayRef(Chains.data(), ChainI));
3641 DAG.setRoot(StoreNode);
3644 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3645 SDLoc sdl = getCurSDLoc();
3647 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3648 Value *PtrOperand = I.getArgOperand(1);
3649 SDValue Ptr = getValue(PtrOperand);
3650 SDValue Src0 = getValue(I.getArgOperand(0));
3651 SDValue Mask = getValue(I.getArgOperand(3));
3652 EVT VT = Src0.getValueType();
3653 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3655 Alignment = DAG.getEVTAlignment(VT);
3658 I.getAAMetadata(AAInfo);
3660 MachineMemOperand *MMO =
3661 DAG.getMachineFunction().
3662 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3663 MachineMemOperand::MOStore, VT.getStoreSize(),
3665 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3667 DAG.setRoot(StoreNode);
3668 setValue(&I, StoreNode);
3671 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3672 SDLoc sdl = getCurSDLoc();
3674 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3675 Value *PtrOperand = I.getArgOperand(0);
3676 SDValue Ptr = getValue(PtrOperand);
3677 SDValue Src0 = getValue(I.getArgOperand(3));
3678 SDValue Mask = getValue(I.getArgOperand(2));
3680 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3681 EVT VT = TLI.getValueType(I.getType());
3682 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3684 Alignment = DAG.getEVTAlignment(VT);
3687 I.getAAMetadata(AAInfo);
3688 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3690 SDValue InChain = DAG.getRoot();
3691 if (AA->pointsToConstantMemory(
3692 AliasAnalysis::Location(PtrOperand,
3693 AA->getTypeStoreSize(I.getType()),
3695 // Do not serialize (non-volatile) loads of constant memory with anything.
3696 InChain = DAG.getEntryNode();
3699 MachineMemOperand *MMO =
3700 DAG.getMachineFunction().
3701 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3702 MachineMemOperand::MOLoad, VT.getStoreSize(),
3703 Alignment, AAInfo, Ranges);
3705 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3707 SDValue OutChain = Load.getValue(1);
3708 DAG.setRoot(OutChain);
3712 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3713 SDLoc dl = getCurSDLoc();
3714 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3715 AtomicOrdering FailureOrder = I.getFailureOrdering();
3716 SynchronizationScope Scope = I.getSynchScope();
3718 SDValue InChain = getRoot();
3720 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3721 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3722 SDValue L = DAG.getAtomicCmpSwap(
3723 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3724 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3725 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3726 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3728 SDValue OutChain = L.getValue(2);
3731 DAG.setRoot(OutChain);
3734 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3735 SDLoc dl = getCurSDLoc();
3737 switch (I.getOperation()) {
3738 default: llvm_unreachable("Unknown atomicrmw operation");
3739 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3740 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3741 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3742 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3743 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3744 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3745 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3746 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3747 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3748 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3749 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3751 AtomicOrdering Order = I.getOrdering();
3752 SynchronizationScope Scope = I.getSynchScope();
3754 SDValue InChain = getRoot();
3757 DAG.getAtomic(NT, dl,
3758 getValue(I.getValOperand()).getSimpleValueType(),
3760 getValue(I.getPointerOperand()),
3761 getValue(I.getValOperand()),
3762 I.getPointerOperand(),
3763 /* Alignment=*/ 0, Order, Scope);
3765 SDValue OutChain = L.getValue(1);
3768 DAG.setRoot(OutChain);
3771 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3772 SDLoc dl = getCurSDLoc();
3773 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3776 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3777 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3778 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3781 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3782 SDLoc dl = getCurSDLoc();
3783 AtomicOrdering Order = I.getOrdering();
3784 SynchronizationScope Scope = I.getSynchScope();
3786 SDValue InChain = getRoot();
3788 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3789 EVT VT = TLI.getValueType(I.getType());
3791 if (I.getAlignment() < VT.getSizeInBits() / 8)
3792 report_fatal_error("Cannot generate unaligned atomic load");
3794 MachineMemOperand *MMO =
3795 DAG.getMachineFunction().
3796 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3797 MachineMemOperand::MOVolatile |
3798 MachineMemOperand::MOLoad,
3800 I.getAlignment() ? I.getAlignment() :
3801 DAG.getEVTAlignment(VT));
3803 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3805 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3806 getValue(I.getPointerOperand()), MMO,
3809 SDValue OutChain = L.getValue(1);
3812 DAG.setRoot(OutChain);
3815 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3816 SDLoc dl = getCurSDLoc();
3818 AtomicOrdering Order = I.getOrdering();
3819 SynchronizationScope Scope = I.getSynchScope();
3821 SDValue InChain = getRoot();
3823 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3824 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3826 if (I.getAlignment() < VT.getSizeInBits() / 8)
3827 report_fatal_error("Cannot generate unaligned atomic store");
3830 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3832 getValue(I.getPointerOperand()),
3833 getValue(I.getValueOperand()),
3834 I.getPointerOperand(), I.getAlignment(),
3837 DAG.setRoot(OutChain);
3840 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3842 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3843 unsigned Intrinsic) {
3844 bool HasChain = !I.doesNotAccessMemory();
3845 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3847 // Build the operand list.
3848 SmallVector<SDValue, 8> Ops;
3849 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3851 // We don't need to serialize loads against other loads.
3852 Ops.push_back(DAG.getRoot());
3854 Ops.push_back(getRoot());
3858 // Info is set by getTgtMemInstrinsic
3859 TargetLowering::IntrinsicInfo Info;
3860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3861 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3863 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3864 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3865 Info.opc == ISD::INTRINSIC_W_CHAIN)
3866 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3868 // Add all operands of the call to the operand list.
3869 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3870 SDValue Op = getValue(I.getArgOperand(i));
3874 SmallVector<EVT, 4> ValueVTs;
3875 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3878 ValueVTs.push_back(MVT::Other);
3880 SDVTList VTs = DAG.getVTList(ValueVTs);
3884 if (IsTgtIntrinsic) {
3885 // This is target intrinsic that touches memory
3886 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3887 VTs, Ops, Info.memVT,
3888 MachinePointerInfo(Info.ptrVal, Info.offset),
3889 Info.align, Info.vol,
3890 Info.readMem, Info.writeMem, Info.size);
3891 } else if (!HasChain) {
3892 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3893 } else if (!I.getType()->isVoidTy()) {
3894 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3896 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3900 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3902 PendingLoads.push_back(Chain);
3907 if (!I.getType()->isVoidTy()) {
3908 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3909 EVT VT = TLI.getValueType(PTy);
3910 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3913 setValue(&I, Result);
3917 /// GetSignificand - Get the significand and build it into a floating-point
3918 /// number with exponent of 1:
3920 /// Op = (Op & 0x007fffff) | 0x3f800000;
3922 /// where Op is the hexadecimal representation of floating point value.
3924 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3925 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3926 DAG.getConstant(0x007fffff, MVT::i32));
3927 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3928 DAG.getConstant(0x3f800000, MVT::i32));
3929 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3932 /// GetExponent - Get the exponent:
3934 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3936 /// where Op is the hexadecimal representation of floating point value.
3938 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3940 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3941 DAG.getConstant(0x7f800000, MVT::i32));
3942 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3943 DAG.getConstant(23, TLI.getPointerTy()));
3944 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3945 DAG.getConstant(127, MVT::i32));
3946 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3949 /// getF32Constant - Get 32-bit floating point constant.
3951 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3952 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3956 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3957 SelectionDAG &DAG) {
3958 // IntegerPartOfX = ((int32_t)(t0);
3959 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3961 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3962 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3963 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3965 // IntegerPartOfX <<= 23;
3966 IntegerPartOfX = DAG.getNode(
3967 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3968 DAG.getConstant(23, DAG.getTargetLoweringInfo().getPointerTy()));
3970 SDValue TwoToFractionalPartOfX;
3971 if (LimitFloatPrecision <= 6) {
3972 // For floating-point precision of 6:
3974 // TwoToFractionalPartOfX =
3976 // (0.735607626f + 0.252464424f * x) * x;
3978 // error 0.0144103317, which is 6 bits
3979 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3980 getF32Constant(DAG, 0x3e814304));
3981 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3982 getF32Constant(DAG, 0x3f3c50c8));
3983 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3984 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3985 getF32Constant(DAG, 0x3f7f5e7e));
3986 } else if (LimitFloatPrecision <= 12) {
3987 // For floating-point precision of 12:
3989 // TwoToFractionalPartOfX =
3992 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3994 // error 0.000107046256, which is 13 to 14 bits
3995 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3996 getF32Constant(DAG, 0x3da235e3));
3997 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3998 getF32Constant(DAG, 0x3e65b8f3));
3999 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4000 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4001 getF32Constant(DAG, 0x3f324b07));
4002 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4003 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4004 getF32Constant(DAG, 0x3f7ff8fd));
4005 } else { // LimitFloatPrecision <= 18
4006 // For floating-point precision of 18:
4008 // TwoToFractionalPartOfX =
4012 // (0.554906021e-1f +
4013 // (0.961591928e-2f +
4014 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4015 // error 2.47208000*10^(-7), which is better than 18 bits
4016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4017 getF32Constant(DAG, 0x3924b03e));
4018 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4019 getF32Constant(DAG, 0x3ab24b87));
4020 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4021 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4022 getF32Constant(DAG, 0x3c1d8c17));
4023 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4024 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4025 getF32Constant(DAG, 0x3d634a1d));
4026 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4027 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4028 getF32Constant(DAG, 0x3e75fe14));
4029 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4030 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4031 getF32Constant(DAG, 0x3f317234));
4032 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4033 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4034 getF32Constant(DAG, 0x3f800000));
4037 // Add the exponent into the result in integer domain.
4038 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4039 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4040 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4043 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4044 /// limited-precision mode.
4045 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4046 const TargetLowering &TLI) {
4047 if (Op.getValueType() == MVT::f32 &&
4048 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4050 // Put the exponent in the right bit position for later addition to the
4053 // #define LOG2OFe 1.4426950f
4054 // t0 = Op * LOG2OFe
4055 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4056 getF32Constant(DAG, 0x3fb8aa3b));
4057 return getLimitedPrecisionExp2(t0, dl, DAG);
4060 // No special expansion.
4061 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4064 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4065 /// limited-precision mode.
4066 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4067 const TargetLowering &TLI) {
4068 if (Op.getValueType() == MVT::f32 &&
4069 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4070 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4072 // Scale the exponent by log(2) [0.69314718f].
4073 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4074 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4075 getF32Constant(DAG, 0x3f317218));
4077 // Get the significand and build it into a floating-point number with
4079 SDValue X = GetSignificand(DAG, Op1, dl);
4081 SDValue LogOfMantissa;
4082 if (LimitFloatPrecision <= 6) {
4083 // For floating-point precision of 6:
4087 // (1.4034025f - 0.23903021f * x) * x;
4089 // error 0.0034276066, which is better than 8 bits
4090 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4091 getF32Constant(DAG, 0xbe74c456));
4092 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4093 getF32Constant(DAG, 0x3fb3a2b1));
4094 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4095 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4096 getF32Constant(DAG, 0x3f949a29));
4097 } else if (LimitFloatPrecision <= 12) {
4098 // For floating-point precision of 12:
4104 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4106 // error 0.000061011436, which is 14 bits
4107 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4108 getF32Constant(DAG, 0xbd67b6d6));
4109 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4110 getF32Constant(DAG, 0x3ee4f4b8));
4111 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4112 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4113 getF32Constant(DAG, 0x3fbc278b));
4114 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4115 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4116 getF32Constant(DAG, 0x40348e95));
4117 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4118 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4119 getF32Constant(DAG, 0x3fdef31a));
4120 } else { // LimitFloatPrecision <= 18
4121 // For floating-point precision of 18:
4129 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4131 // error 0.0000023660568, which is better than 18 bits
4132 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4133 getF32Constant(DAG, 0xbc91e5ac));
4134 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4135 getF32Constant(DAG, 0x3e4350aa));
4136 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4137 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4138 getF32Constant(DAG, 0x3f60d3e3));
4139 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4140 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4141 getF32Constant(DAG, 0x4011cdf0));
4142 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4143 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4144 getF32Constant(DAG, 0x406cfd1c));
4145 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4146 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4147 getF32Constant(DAG, 0x408797cb));
4148 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4149 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4150 getF32Constant(DAG, 0x4006dcab));
4153 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4156 // No special expansion.
4157 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4160 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4161 /// limited-precision mode.
4162 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4163 const TargetLowering &TLI) {
4164 if (Op.getValueType() == MVT::f32 &&
4165 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4166 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4168 // Get the exponent.
4169 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4171 // Get the significand and build it into a floating-point number with
4173 SDValue X = GetSignificand(DAG, Op1, dl);
4175 // Different possible minimax approximations of significand in
4176 // floating-point for various degrees of accuracy over [1,2].
4177 SDValue Log2ofMantissa;
4178 if (LimitFloatPrecision <= 6) {
4179 // For floating-point precision of 6:
4181 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4183 // error 0.0049451742, which is more than 7 bits
4184 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4185 getF32Constant(DAG, 0xbeb08fe0));
4186 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4187 getF32Constant(DAG, 0x40019463));
4188 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4189 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4190 getF32Constant(DAG, 0x3fd6633d));
4191 } else if (LimitFloatPrecision <= 12) {
4192 // For floating-point precision of 12:
4198 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4200 // error 0.0000876136000, which is better than 13 bits
4201 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4202 getF32Constant(DAG, 0xbda7262e));
4203 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4204 getF32Constant(DAG, 0x3f25280b));
4205 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4206 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4207 getF32Constant(DAG, 0x4007b923));
4208 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4209 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4210 getF32Constant(DAG, 0x40823e2f));
4211 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4212 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4213 getF32Constant(DAG, 0x4020d29c));
4214 } else { // LimitFloatPrecision <= 18
4215 // For floating-point precision of 18:
4224 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4226 // error 0.0000018516, which is better than 18 bits
4227 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4228 getF32Constant(DAG, 0xbcd2769e));
4229 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4230 getF32Constant(DAG, 0x3e8ce0b9));
4231 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4232 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4233 getF32Constant(DAG, 0x3fa22ae7));
4234 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4235 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4236 getF32Constant(DAG, 0x40525723));
4237 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4238 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4239 getF32Constant(DAG, 0x40aaf200));
4240 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4241 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4242 getF32Constant(DAG, 0x40c39dad));
4243 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4244 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4245 getF32Constant(DAG, 0x4042902c));
4248 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4251 // No special expansion.
4252 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4255 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4256 /// limited-precision mode.
4257 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4258 const TargetLowering &TLI) {
4259 if (Op.getValueType() == MVT::f32 &&
4260 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4261 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4263 // Scale the exponent by log10(2) [0.30102999f].
4264 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4265 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4266 getF32Constant(DAG, 0x3e9a209a));
4268 // Get the significand and build it into a floating-point number with
4270 SDValue X = GetSignificand(DAG, Op1, dl);
4272 SDValue Log10ofMantissa;
4273 if (LimitFloatPrecision <= 6) {
4274 // For floating-point precision of 6:
4276 // Log10ofMantissa =
4278 // (0.60948995f - 0.10380950f * x) * x;
4280 // error 0.0014886165, which is 6 bits
4281 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4282 getF32Constant(DAG, 0xbdd49a13));
4283 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4284 getF32Constant(DAG, 0x3f1c0789));
4285 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4286 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4287 getF32Constant(DAG, 0x3f011300));
4288 } else if (LimitFloatPrecision <= 12) {
4289 // For floating-point precision of 12:
4291 // Log10ofMantissa =
4294 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4296 // error 0.00019228036, which is better than 12 bits
4297 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4298 getF32Constant(DAG, 0x3d431f31));
4299 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4300 getF32Constant(DAG, 0x3ea21fb2));
4301 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4302 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4303 getF32Constant(DAG, 0x3f6ae232));
4304 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4305 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4306 getF32Constant(DAG, 0x3f25f7c3));
4307 } else { // LimitFloatPrecision <= 18
4308 // For floating-point precision of 18:
4310 // Log10ofMantissa =
4315 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4317 // error 0.0000037995730, which is better than 18 bits
4318 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4319 getF32Constant(DAG, 0x3c5d51ce));
4320 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4321 getF32Constant(DAG, 0x3e00685a));
4322 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4323 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4324 getF32Constant(DAG, 0x3efb6798));
4325 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4326 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4327 getF32Constant(DAG, 0x3f88d192));
4328 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4329 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4330 getF32Constant(DAG, 0x3fc4316c));
4331 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4332 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4333 getF32Constant(DAG, 0x3f57ce70));
4336 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4339 // No special expansion.
4340 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4343 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4344 /// limited-precision mode.
4345 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4346 const TargetLowering &TLI) {
4347 if (Op.getValueType() == MVT::f32 &&
4348 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4349 return getLimitedPrecisionExp2(Op, dl, DAG);
4351 // No special expansion.
4352 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4355 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4356 /// limited-precision mode with x == 10.0f.
4357 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4358 SelectionDAG &DAG, const TargetLowering &TLI) {
4359 bool IsExp10 = false;
4360 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4361 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4362 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4364 IsExp10 = LHSC->isExactlyValue(Ten);
4369 // Put the exponent in the right bit position for later addition to the
4372 // #define LOG2OF10 3.3219281f
4373 // t0 = Op * LOG2OF10;
4374 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4375 getF32Constant(DAG, 0x40549a78));
4376 return getLimitedPrecisionExp2(t0, dl, DAG);
4379 // No special expansion.
4380 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4384 /// ExpandPowI - Expand a llvm.powi intrinsic.
4385 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4386 SelectionDAG &DAG) {
4387 // If RHS is a constant, we can expand this out to a multiplication tree,
4388 // otherwise we end up lowering to a call to __powidf2 (for example). When
4389 // optimizing for size, we only want to do this if the expansion would produce
4390 // a small number of multiplies, otherwise we do the full expansion.
4391 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4392 // Get the exponent as a positive value.
4393 unsigned Val = RHSC->getSExtValue();
4394 if ((int)Val < 0) Val = -Val;
4396 // powi(x, 0) -> 1.0
4398 return DAG.getConstantFP(1.0, LHS.getValueType());
4400 const Function *F = DAG.getMachineFunction().getFunction();
4401 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
4402 // If optimizing for size, don't insert too many multiplies. This
4403 // inserts up to 5 multiplies.
4404 countPopulation(Val) + Log2_32(Val) < 7) {
4405 // We use the simple binary decomposition method to generate the multiply
4406 // sequence. There are more optimal ways to do this (for example,
4407 // powi(x,15) generates one more multiply than it should), but this has
4408 // the benefit of being both really simple and much better than a libcall.
4409 SDValue Res; // Logically starts equal to 1.0
4410 SDValue CurSquare = LHS;
4414 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4416 Res = CurSquare; // 1.0*CurSquare.
4419 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4420 CurSquare, CurSquare);
4424 // If the original was negative, invert the result, producing 1/(x*x*x).
4425 if (RHSC->getSExtValue() < 0)
4426 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4427 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4432 // Otherwise, expand to a libcall.
4433 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4436 // getTruncatedArgReg - Find underlying register used for an truncated
4438 static unsigned getTruncatedArgReg(const SDValue &N) {
4439 if (N.getOpcode() != ISD::TRUNCATE)
4442 const SDValue &Ext = N.getOperand(0);
4443 if (Ext.getOpcode() == ISD::AssertZext ||
4444 Ext.getOpcode() == ISD::AssertSext) {
4445 const SDValue &CFR = Ext.getOperand(0);
4446 if (CFR.getOpcode() == ISD::CopyFromReg)
4447 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4448 if (CFR.getOpcode() == ISD::TRUNCATE)
4449 return getTruncatedArgReg(CFR);
4454 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4455 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4456 /// At the end of instruction selection, they will be inserted to the entry BB.
4457 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4459 MDNode *Expr, int64_t Offset,
4462 const Argument *Arg = dyn_cast<Argument>(V);
4466 MachineFunction &MF = DAG.getMachineFunction();
4467 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4469 // Ignore inlined function arguments here.
4470 DIVariable DV(Variable);
4471 if (DV.isInlinedFnArgument(MF.getFunction()))
4474 Optional<MachineOperand> Op;
4475 // Some arguments' frame index is recorded during argument lowering.
4476 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4477 Op = MachineOperand::CreateFI(FI);
4479 if (!Op && N.getNode()) {
4481 if (N.getOpcode() == ISD::CopyFromReg)
4482 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4484 Reg = getTruncatedArgReg(N);
4485 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4486 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4487 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4492 Op = MachineOperand::CreateReg(Reg, false);
4496 // Check if ValueMap has reg number.
4497 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4498 if (VMI != FuncInfo.ValueMap.end())
4499 Op = MachineOperand::CreateReg(VMI->second, false);
4502 if (!Op && N.getNode())
4503 // Check if frame index is available.
4504 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4505 if (FrameIndexSDNode *FINode =
4506 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4507 Op = MachineOperand::CreateFI(FINode->getIndex());
4513 FuncInfo.ArgDbgValues.push_back(
4514 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4515 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4517 FuncInfo.ArgDbgValues.push_back(
4518 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4521 .addMetadata(Variable)
4522 .addMetadata(Expr));
4527 // VisualStudio defines setjmp as _setjmp
4528 #if defined(_MSC_VER) && defined(setjmp) && \
4529 !defined(setjmp_undefined_for_msvc)
4530 # pragma push_macro("setjmp")
4532 # define setjmp_undefined_for_msvc
4535 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4536 /// we want to emit this as a call to a named external function, return the name
4537 /// otherwise lower it and return null.
4539 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4540 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4541 SDLoc sdl = getCurSDLoc();
4542 DebugLoc dl = getCurDebugLoc();
4545 switch (Intrinsic) {
4547 // By default, turn this into a target intrinsic node.
4548 visitTargetIntrinsic(I, Intrinsic);
4550 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4551 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4552 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4553 case Intrinsic::returnaddress:
4554 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4555 getValue(I.getArgOperand(0))));
4557 case Intrinsic::frameaddress:
4558 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4559 getValue(I.getArgOperand(0))));
4561 case Intrinsic::read_register: {
4562 Value *Reg = I.getArgOperand(0);
4564 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4565 EVT VT = TLI.getValueType(I.getType());
4566 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4569 case Intrinsic::write_register: {
4570 Value *Reg = I.getArgOperand(0);
4571 Value *RegValue = I.getArgOperand(1);
4572 SDValue Chain = getValue(RegValue).getOperand(0);
4574 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4575 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4576 RegName, getValue(RegValue)));
4579 case Intrinsic::setjmp:
4580 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4581 case Intrinsic::longjmp:
4582 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4583 case Intrinsic::memcpy: {
4584 // FIXME: this definition of "user defined address space" is x86-specific
4585 // Assert for address < 256 since we support only user defined address
4587 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4589 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4591 "Unknown address space");
4592 SDValue Op1 = getValue(I.getArgOperand(0));
4593 SDValue Op2 = getValue(I.getArgOperand(1));
4594 SDValue Op3 = getValue(I.getArgOperand(2));
4595 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4597 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4598 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4599 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4600 MachinePointerInfo(I.getArgOperand(0)),
4601 MachinePointerInfo(I.getArgOperand(1))));
4604 case Intrinsic::memset: {
4605 // FIXME: this definition of "user defined address space" is x86-specific
4606 // Assert for address < 256 since we support only user defined address
4608 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4610 "Unknown address space");
4611 SDValue Op1 = getValue(I.getArgOperand(0));
4612 SDValue Op2 = getValue(I.getArgOperand(1));
4613 SDValue Op3 = getValue(I.getArgOperand(2));
4614 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4616 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4617 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4618 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4619 MachinePointerInfo(I.getArgOperand(0))));
4622 case Intrinsic::memmove: {
4623 // FIXME: this definition of "user defined address space" is x86-specific
4624 // Assert for address < 256 since we support only user defined address
4626 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4628 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4630 "Unknown address space");
4631 SDValue Op1 = getValue(I.getArgOperand(0));
4632 SDValue Op2 = getValue(I.getArgOperand(1));
4633 SDValue Op3 = getValue(I.getArgOperand(2));
4634 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4636 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4637 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4638 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4639 MachinePointerInfo(I.getArgOperand(0)),
4640 MachinePointerInfo(I.getArgOperand(1))));
4643 case Intrinsic::dbg_declare: {
4644 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4645 MDNode *Variable = DI.getVariable();
4646 MDNode *Expression = DI.getExpression();
4647 const Value *Address = DI.getAddress();
4648 DIVariable DIVar(Variable);
4649 assert((!DIVar || DIVar.isVariable()) &&
4650 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4651 if (!Address || !DIVar) {
4652 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4656 // Check if address has undef value.
4657 if (isa<UndefValue>(Address) ||
4658 (Address->use_empty() && !isa<Argument>(Address))) {
4659 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4663 SDValue &N = NodeMap[Address];
4664 if (!N.getNode() && isa<Argument>(Address))
4665 // Check unused arguments map.
4666 N = UnusedArgNodeMap[Address];
4669 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4670 Address = BCI->getOperand(0);
4671 // Parameters are handled specially.
4673 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4674 isa<Argument>(Address));
4676 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4678 if (isParameter && !AI) {
4679 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4681 // Byval parameter. We have a frame index at this point.
4682 SDV = DAG.getFrameIndexDbgValue(
4683 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4685 // Address is an argument, so try to emit its dbg value using
4686 // virtual register info from the FuncInfo.ValueMap.
4687 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4691 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4692 true, 0, dl, SDNodeOrder);
4694 // Can't do anything with other non-AI cases yet.
4695 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4696 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4697 DEBUG(Address->dump());
4700 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4702 // If Address is an argument then try to emit its dbg value using
4703 // virtual register info from the FuncInfo.ValueMap.
4704 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4706 // If variable is pinned by a alloca in dominating bb then
4707 // use StaticAllocaMap.
4708 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4709 if (AI->getParent() != DI.getParent()) {
4710 DenseMap<const AllocaInst*, int>::iterator SI =
4711 FuncInfo.StaticAllocaMap.find(AI);
4712 if (SI != FuncInfo.StaticAllocaMap.end()) {
4713 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4714 0, dl, SDNodeOrder);
4715 DAG.AddDbgValue(SDV, nullptr, false);
4720 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4725 case Intrinsic::dbg_value: {
4726 const DbgValueInst &DI = cast<DbgValueInst>(I);
4727 DIVariable DIVar(DI.getVariable());
4728 assert((!DIVar || DIVar.isVariable()) &&
4729 "Variable in DbgValueInst should be either null or a DIVariable.");
4733 MDNode *Variable = DI.getVariable();
4734 MDNode *Expression = DI.getExpression();
4735 uint64_t Offset = DI.getOffset();
4736 const Value *V = DI.getValue();
4741 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4742 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4744 DAG.AddDbgValue(SDV, nullptr, false);
4746 // Do not use getValue() in here; we don't want to generate code at
4747 // this point if it hasn't been done yet.
4748 SDValue N = NodeMap[V];
4749 if (!N.getNode() && isa<Argument>(V))
4750 // Check unused arguments map.
4751 N = UnusedArgNodeMap[V];
4753 // A dbg.value for an alloca is always indirect.
4754 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4755 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4757 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4758 IsIndirect, Offset, dl, SDNodeOrder);
4759 DAG.AddDbgValue(SDV, N.getNode(), false);
4761 } else if (!V->use_empty() ) {
4762 // Do not call getValue(V) yet, as we don't want to generate code.
4763 // Remember it for later.
4764 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4765 DanglingDebugInfoMap[V] = DDI;
4767 // We may expand this to cover more cases. One case where we have no
4768 // data available is an unreferenced parameter.
4769 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4773 // Build a debug info table entry.
4774 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4775 V = BCI->getOperand(0);
4776 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4777 // Don't handle byval struct arguments or VLAs, for example.
4779 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4780 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4783 DenseMap<const AllocaInst*, int>::iterator SI =
4784 FuncInfo.StaticAllocaMap.find(AI);
4785 if (SI == FuncInfo.StaticAllocaMap.end())
4786 return nullptr; // VLAs.
4790 case Intrinsic::eh_typeid_for: {
4791 // Find the type id for the given typeinfo.
4792 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4793 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4794 Res = DAG.getConstant(TypeID, MVT::i32);
4799 case Intrinsic::eh_return_i32:
4800 case Intrinsic::eh_return_i64:
4801 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4802 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4805 getValue(I.getArgOperand(0)),
4806 getValue(I.getArgOperand(1))));
4808 case Intrinsic::eh_unwind_init:
4809 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4811 case Intrinsic::eh_dwarf_cfa: {
4812 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4813 TLI.getPointerTy());
4814 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4815 CfaArg.getValueType(),
4816 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4817 CfaArg.getValueType()),
4819 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4820 DAG.getConstant(0, TLI.getPointerTy()));
4821 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4825 case Intrinsic::eh_sjlj_callsite: {
4826 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4827 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4828 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4829 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4831 MMI.setCurrentCallSite(CI->getZExtValue());
4834 case Intrinsic::eh_sjlj_functioncontext: {
4835 // Get and store the index of the function context.
4836 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4838 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4839 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4840 MFI->setFunctionContextIndex(FI);
4843 case Intrinsic::eh_sjlj_setjmp: {
4846 Ops[1] = getValue(I.getArgOperand(0));
4847 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4848 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4849 setValue(&I, Op.getValue(0));
4850 DAG.setRoot(Op.getValue(1));
4853 case Intrinsic::eh_sjlj_longjmp: {
4854 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4855 getRoot(), getValue(I.getArgOperand(0))));
4859 case Intrinsic::masked_load:
4862 case Intrinsic::masked_store:
4863 visitMaskedStore(I);
4865 case Intrinsic::x86_mmx_pslli_w:
4866 case Intrinsic::x86_mmx_pslli_d:
4867 case Intrinsic::x86_mmx_pslli_q:
4868 case Intrinsic::x86_mmx_psrli_w:
4869 case Intrinsic::x86_mmx_psrli_d:
4870 case Intrinsic::x86_mmx_psrli_q:
4871 case Intrinsic::x86_mmx_psrai_w:
4872 case Intrinsic::x86_mmx_psrai_d: {
4873 SDValue ShAmt = getValue(I.getArgOperand(1));
4874 if (isa<ConstantSDNode>(ShAmt)) {
4875 visitTargetIntrinsic(I, Intrinsic);
4878 unsigned NewIntrinsic = 0;
4879 EVT ShAmtVT = MVT::v2i32;
4880 switch (Intrinsic) {
4881 case Intrinsic::x86_mmx_pslli_w:
4882 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4884 case Intrinsic::x86_mmx_pslli_d:
4885 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4887 case Intrinsic::x86_mmx_pslli_q:
4888 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4890 case Intrinsic::x86_mmx_psrli_w:
4891 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4893 case Intrinsic::x86_mmx_psrli_d:
4894 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4896 case Intrinsic::x86_mmx_psrli_q:
4897 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4899 case Intrinsic::x86_mmx_psrai_w:
4900 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4902 case Intrinsic::x86_mmx_psrai_d:
4903 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4905 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4908 // The vector shift intrinsics with scalars uses 32b shift amounts but
4909 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4911 // We must do this early because v2i32 is not a legal type.
4914 ShOps[1] = DAG.getConstant(0, MVT::i32);
4915 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4916 EVT DestVT = TLI.getValueType(I.getType());
4917 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4918 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4919 DAG.getConstant(NewIntrinsic, MVT::i32),
4920 getValue(I.getArgOperand(0)), ShAmt);
4924 case Intrinsic::convertff:
4925 case Intrinsic::convertfsi:
4926 case Intrinsic::convertfui:
4927 case Intrinsic::convertsif:
4928 case Intrinsic::convertuif:
4929 case Intrinsic::convertss:
4930 case Intrinsic::convertsu:
4931 case Intrinsic::convertus:
4932 case Intrinsic::convertuu: {
4933 ISD::CvtCode Code = ISD::CVT_INVALID;
4934 switch (Intrinsic) {
4935 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4936 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4937 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4938 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4939 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4940 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4941 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4942 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4943 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4944 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4946 EVT DestVT = TLI.getValueType(I.getType());
4947 const Value *Op1 = I.getArgOperand(0);
4948 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4949 DAG.getValueType(DestVT),
4950 DAG.getValueType(getValue(Op1).getValueType()),
4951 getValue(I.getArgOperand(1)),
4952 getValue(I.getArgOperand(2)),
4957 case Intrinsic::powi:
4958 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4959 getValue(I.getArgOperand(1)), DAG));
4961 case Intrinsic::log:
4962 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4964 case Intrinsic::log2:
4965 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4967 case Intrinsic::log10:
4968 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4970 case Intrinsic::exp:
4971 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4973 case Intrinsic::exp2:
4974 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4976 case Intrinsic::pow:
4977 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4978 getValue(I.getArgOperand(1)), DAG, TLI));
4980 case Intrinsic::sqrt:
4981 case Intrinsic::fabs:
4982 case Intrinsic::sin:
4983 case Intrinsic::cos:
4984 case Intrinsic::floor:
4985 case Intrinsic::ceil:
4986 case Intrinsic::trunc:
4987 case Intrinsic::rint:
4988 case Intrinsic::nearbyint:
4989 case Intrinsic::round: {
4991 switch (Intrinsic) {
4992 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4993 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4994 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4995 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4996 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4997 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4998 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4999 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5000 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5001 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5002 case Intrinsic::round: Opcode = ISD::FROUND; break;
5005 setValue(&I, DAG.getNode(Opcode, sdl,
5006 getValue(I.getArgOperand(0)).getValueType(),
5007 getValue(I.getArgOperand(0))));
5010 case Intrinsic::minnum:
5011 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5012 getValue(I.getArgOperand(0)).getValueType(),
5013 getValue(I.getArgOperand(0)),
5014 getValue(I.getArgOperand(1))));
5016 case Intrinsic::maxnum:
5017 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5018 getValue(I.getArgOperand(0)).getValueType(),
5019 getValue(I.getArgOperand(0)),
5020 getValue(I.getArgOperand(1))));
5022 case Intrinsic::copysign:
5023 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5024 getValue(I.getArgOperand(0)).getValueType(),
5025 getValue(I.getArgOperand(0)),
5026 getValue(I.getArgOperand(1))));
5028 case Intrinsic::fma:
5029 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5030 getValue(I.getArgOperand(0)).getValueType(),
5031 getValue(I.getArgOperand(0)),
5032 getValue(I.getArgOperand(1)),
5033 getValue(I.getArgOperand(2))));
5035 case Intrinsic::fmuladd: {
5036 EVT VT = TLI.getValueType(I.getType());
5037 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5038 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5039 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5040 getValue(I.getArgOperand(0)).getValueType(),
5041 getValue(I.getArgOperand(0)),
5042 getValue(I.getArgOperand(1)),
5043 getValue(I.getArgOperand(2))));
5045 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5046 getValue(I.getArgOperand(0)).getValueType(),
5047 getValue(I.getArgOperand(0)),
5048 getValue(I.getArgOperand(1)));
5049 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5050 getValue(I.getArgOperand(0)).getValueType(),
5052 getValue(I.getArgOperand(2)));
5057 case Intrinsic::convert_to_fp16:
5058 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5059 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5060 getValue(I.getArgOperand(0)),
5061 DAG.getTargetConstant(0, MVT::i32))));
5063 case Intrinsic::convert_from_fp16:
5065 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5066 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5067 getValue(I.getArgOperand(0)))));
5069 case Intrinsic::pcmarker: {
5070 SDValue Tmp = getValue(I.getArgOperand(0));
5071 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5074 case Intrinsic::readcyclecounter: {
5075 SDValue Op = getRoot();
5076 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5077 DAG.getVTList(MVT::i64, MVT::Other), Op);
5079 DAG.setRoot(Res.getValue(1));
5082 case Intrinsic::bswap:
5083 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5084 getValue(I.getArgOperand(0)).getValueType(),
5085 getValue(I.getArgOperand(0))));
5087 case Intrinsic::cttz: {
5088 SDValue Arg = getValue(I.getArgOperand(0));
5089 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5090 EVT Ty = Arg.getValueType();
5091 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5095 case Intrinsic::ctlz: {
5096 SDValue Arg = getValue(I.getArgOperand(0));
5097 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5098 EVT Ty = Arg.getValueType();
5099 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5103 case Intrinsic::ctpop: {
5104 SDValue Arg = getValue(I.getArgOperand(0));
5105 EVT Ty = Arg.getValueType();
5106 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5109 case Intrinsic::stacksave: {
5110 SDValue Op = getRoot();
5111 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5112 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5114 DAG.setRoot(Res.getValue(1));
5117 case Intrinsic::stackrestore: {
5118 Res = getValue(I.getArgOperand(0));
5119 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5122 case Intrinsic::stackprotector: {
5123 // Emit code into the DAG to store the stack guard onto the stack.
5124 MachineFunction &MF = DAG.getMachineFunction();
5125 MachineFrameInfo *MFI = MF.getFrameInfo();
5126 EVT PtrTy = TLI.getPointerTy();
5127 SDValue Src, Chain = getRoot();
5128 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5129 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5131 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5132 // global variable __stack_chk_guard.
5134 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5135 if (BC->getOpcode() == Instruction::BitCast)
5136 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5138 if (GV && TLI.useLoadStackGuardNode()) {
5139 // Emit a LOAD_STACK_GUARD node.
5140 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5142 MachinePointerInfo MPInfo(GV);
5143 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5144 unsigned Flags = MachineMemOperand::MOLoad |
5145 MachineMemOperand::MOInvariant;
5146 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5147 PtrTy.getSizeInBits() / 8,
5148 DAG.getEVTAlignment(PtrTy));
5149 Node->setMemRefs(MemRefs, MemRefs + 1);
5151 // Copy the guard value to a virtual register so that it can be
5152 // retrieved in the epilogue.
5153 Src = SDValue(Node, 0);
5154 const TargetRegisterClass *RC =
5155 TLI.getRegClassFor(Src.getSimpleValueType());
5156 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5158 SPDescriptor.setGuardReg(Reg);
5159 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5161 Src = getValue(I.getArgOperand(0)); // The guard's value.
5164 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5166 int FI = FuncInfo.StaticAllocaMap[Slot];
5167 MFI->setStackProtectorIndex(FI);
5169 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5171 // Store the stack protector onto the stack.
5172 Res = DAG.getStore(Chain, sdl, Src, FIN,
5173 MachinePointerInfo::getFixedStack(FI),
5179 case Intrinsic::objectsize: {
5180 // If we don't know by now, we're never going to know.
5181 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5183 assert(CI && "Non-constant type in __builtin_object_size?");
5185 SDValue Arg = getValue(I.getCalledValue());
5186 EVT Ty = Arg.getValueType();
5189 Res = DAG.getConstant(-1ULL, Ty);
5191 Res = DAG.getConstant(0, Ty);
5196 case Intrinsic::annotation:
5197 case Intrinsic::ptr_annotation:
5198 // Drop the intrinsic, but forward the value
5199 setValue(&I, getValue(I.getOperand(0)));
5201 case Intrinsic::assume:
5202 case Intrinsic::var_annotation:
5203 // Discard annotate attributes and assumptions
5206 case Intrinsic::init_trampoline: {
5207 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5211 Ops[1] = getValue(I.getArgOperand(0));
5212 Ops[2] = getValue(I.getArgOperand(1));
5213 Ops[3] = getValue(I.getArgOperand(2));
5214 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5215 Ops[5] = DAG.getSrcValue(F);
5217 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5222 case Intrinsic::adjust_trampoline: {
5223 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5225 getValue(I.getArgOperand(0))));
5228 case Intrinsic::gcroot:
5230 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5231 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5233 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5234 GFI->addStackRoot(FI->getIndex(), TypeMap);
5237 case Intrinsic::gcread:
5238 case Intrinsic::gcwrite:
5239 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5240 case Intrinsic::flt_rounds:
5241 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5244 case Intrinsic::expect: {
5245 // Just replace __builtin_expect(exp, c) with EXP.
5246 setValue(&I, getValue(I.getArgOperand(0)));
5250 case Intrinsic::debugtrap:
5251 case Intrinsic::trap: {
5252 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5253 if (TrapFuncName.empty()) {
5254 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5255 ISD::TRAP : ISD::DEBUGTRAP;
5256 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5259 TargetLowering::ArgListTy Args;
5261 TargetLowering::CallLoweringInfo CLI(DAG);
5262 CLI.setDebugLoc(sdl).setChain(getRoot())
5263 .setCallee(CallingConv::C, I.getType(),
5264 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5265 std::move(Args), 0);
5267 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5268 DAG.setRoot(Result.second);
5272 case Intrinsic::uadd_with_overflow:
5273 case Intrinsic::sadd_with_overflow:
5274 case Intrinsic::usub_with_overflow:
5275 case Intrinsic::ssub_with_overflow:
5276 case Intrinsic::umul_with_overflow:
5277 case Intrinsic::smul_with_overflow: {
5279 switch (Intrinsic) {
5280 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5281 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5282 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5283 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5284 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5285 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5286 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5288 SDValue Op1 = getValue(I.getArgOperand(0));
5289 SDValue Op2 = getValue(I.getArgOperand(1));
5291 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5292 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5295 case Intrinsic::prefetch: {
5297 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5299 Ops[1] = getValue(I.getArgOperand(0));
5300 Ops[2] = getValue(I.getArgOperand(1));
5301 Ops[3] = getValue(I.getArgOperand(2));
5302 Ops[4] = getValue(I.getArgOperand(3));
5303 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5304 DAG.getVTList(MVT::Other), Ops,
5305 EVT::getIntegerVT(*Context, 8),
5306 MachinePointerInfo(I.getArgOperand(0)),
5308 false, /* volatile */
5310 rw==1)); /* write */
5313 case Intrinsic::lifetime_start:
5314 case Intrinsic::lifetime_end: {
5315 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5316 // Stack coloring is not enabled in O0, discard region information.
5317 if (TM.getOptLevel() == CodeGenOpt::None)
5320 SmallVector<Value *, 4> Allocas;
5321 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5323 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5324 E = Allocas.end(); Object != E; ++Object) {
5325 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5327 // Could not find an Alloca.
5328 if (!LifetimeObject)
5331 // First check that the Alloca is static, otherwise it won't have a
5332 // valid frame index.
5333 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5334 if (SI == FuncInfo.StaticAllocaMap.end())
5337 int FI = SI->second;
5341 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5342 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5344 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5349 case Intrinsic::invariant_start:
5350 // Discard region information.
5351 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5353 case Intrinsic::invariant_end:
5354 // Discard region information.
5356 case Intrinsic::stackprotectorcheck: {
5357 // Do not actually emit anything for this basic block. Instead we initialize
5358 // the stack protector descriptor and export the guard variable so we can
5359 // access it in FinishBasicBlock.
5360 const BasicBlock *BB = I.getParent();
5361 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5362 ExportFromCurrentBlock(SPDescriptor.getGuard());
5364 // Flush our exports since we are going to process a terminator.
5365 (void)getControlRoot();
5368 case Intrinsic::clear_cache:
5369 return TLI.getClearCacheBuiltinName();
5370 case Intrinsic::donothing:
5373 case Intrinsic::experimental_stackmap: {
5377 case Intrinsic::experimental_patchpoint_void:
5378 case Intrinsic::experimental_patchpoint_i64: {
5379 visitPatchpoint(&I);
5382 case Intrinsic::experimental_gc_statepoint: {
5386 case Intrinsic::experimental_gc_result_int:
5387 case Intrinsic::experimental_gc_result_float:
5388 case Intrinsic::experimental_gc_result_ptr:
5389 case Intrinsic::experimental_gc_result: {
5393 case Intrinsic::experimental_gc_relocate: {
5397 case Intrinsic::instrprof_increment:
5398 llvm_unreachable("instrprof failed to lower an increment");
5400 case Intrinsic::frameescape: {
5401 MachineFunction &MF = DAG.getMachineFunction();
5402 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5404 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
5405 // is the same on all targets.
5406 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5408 cast<AllocaInst>(I.getArgOperand(Idx)->stripPointerCasts());
5409 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5410 "can only escape static allocas");
5411 int FI = FuncInfo.StaticAllocaMap[Slot];
5412 MCSymbol *FrameAllocSym =
5413 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(MF.getName(),
5415 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5416 TII->get(TargetOpcode::FRAME_ALLOC))
5417 .addSym(FrameAllocSym)
5424 case Intrinsic::framerecover: {
5425 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
5426 MachineFunction &MF = DAG.getMachineFunction();
5427 MVT PtrVT = TLI.getPointerTy(0);
5429 // Get the symbol that defines the frame offset.
5430 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5431 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5432 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5433 MCSymbol *FrameAllocSym =
5434 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(Fn->getName(),
5437 // Create a TargetExternalSymbol for the label to avoid any target lowering
5438 // that would make this PC relative.
5439 StringRef Name = FrameAllocSym->getName();
5440 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
5441 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5443 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5445 // Add the offset to the FP.
5446 Value *FP = I.getArgOperand(1);
5447 SDValue FPVal = getValue(FP);
5448 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5453 case Intrinsic::eh_begincatch:
5454 case Intrinsic::eh_endcatch:
5455 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5459 std::pair<SDValue, SDValue>
5460 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5461 MachineBasicBlock *LandingPad) {
5462 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5463 MCSymbol *BeginLabel = nullptr;
5466 // Insert a label before the invoke call to mark the try range. This can be
5467 // used to detect deletion of the invoke via the MachineModuleInfo.
5468 BeginLabel = MMI.getContext().CreateTempSymbol();
5470 // For SjLj, keep track of which landing pads go with which invokes
5471 // so as to maintain the ordering of pads in the LSDA.
5472 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5473 if (CallSiteIndex) {
5474 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5475 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5477 // Now that the call site is handled, stop tracking it.
5478 MMI.setCurrentCallSite(0);
5481 // Both PendingLoads and PendingExports must be flushed here;
5482 // this call might not return.
5484 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5486 CLI.setChain(getRoot());
5488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5489 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5491 assert((CLI.IsTailCall || Result.second.getNode()) &&
5492 "Non-null chain expected with non-tail call!");
5493 assert((Result.second.getNode() || !Result.first.getNode()) &&
5494 "Null value expected with tail call!");
5496 if (!Result.second.getNode()) {
5497 // As a special case, a null chain means that a tail call has been emitted
5498 // and the DAG root is already updated.
5501 // Since there's no actual continuation from this block, nothing can be
5502 // relying on us setting vregs for them.
5503 PendingExports.clear();
5505 DAG.setRoot(Result.second);
5509 // Insert a label at the end of the invoke call to mark the try range. This
5510 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5511 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5512 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5514 // Inform MachineModuleInfo of range.
5515 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5521 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5523 MachineBasicBlock *LandingPad) {
5524 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5525 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5526 Type *RetTy = FTy->getReturnType();
5528 TargetLowering::ArgListTy Args;
5529 TargetLowering::ArgListEntry Entry;
5530 Args.reserve(CS.arg_size());
5532 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5534 const Value *V = *i;
5537 if (V->getType()->isEmptyTy())
5540 SDValue ArgNode = getValue(V);
5541 Entry.Node = ArgNode; Entry.Ty = V->getType();
5543 // Skip the first return-type Attribute to get to params.
5544 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5545 Args.push_back(Entry);
5548 // Check if target-independent constraints permit a tail call here.
5549 // Target-dependent constraints are checked within TLI->LowerCallTo.
5550 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5553 TargetLowering::CallLoweringInfo CLI(DAG);
5554 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5555 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5556 .setTailCall(isTailCall);
5557 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5559 if (Result.first.getNode())
5560 setValue(CS.getInstruction(), Result.first);
5563 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5564 /// value is equal or not-equal to zero.
5565 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5566 for (const User *U : V->users()) {
5567 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5568 if (IC->isEquality())
5569 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5570 if (C->isNullValue())
5572 // Unknown instruction.
5578 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5580 SelectionDAGBuilder &Builder) {
5582 // Check to see if this load can be trivially constant folded, e.g. if the
5583 // input is from a string literal.
5584 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5585 // Cast pointer to the type we really want to load.
5586 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5587 PointerType::getUnqual(LoadTy));
5589 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5590 const_cast<Constant *>(LoadInput), *Builder.DL))
5591 return Builder.getValue(LoadCst);
5594 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5595 // still constant memory, the input chain can be the entry node.
5597 bool ConstantMemory = false;
5599 // Do not serialize (non-volatile) loads of constant memory with anything.
5600 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5601 Root = Builder.DAG.getEntryNode();
5602 ConstantMemory = true;
5604 // Do not serialize non-volatile loads against each other.
5605 Root = Builder.DAG.getRoot();
5608 SDValue Ptr = Builder.getValue(PtrVal);
5609 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5610 Ptr, MachinePointerInfo(PtrVal),
5612 false /*nontemporal*/,
5613 false /*isinvariant*/, 1 /* align=1 */);
5615 if (!ConstantMemory)
5616 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5620 /// processIntegerCallValue - Record the value for an instruction that
5621 /// produces an integer result, converting the type where necessary.
5622 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5625 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5627 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5629 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5630 setValue(&I, Value);
5633 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5634 /// If so, return true and lower it, otherwise return false and it will be
5635 /// lowered like a normal call.
5636 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5637 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5638 if (I.getNumArgOperands() != 3)
5641 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5642 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5643 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5644 !I.getType()->isIntegerTy())
5647 const Value *Size = I.getArgOperand(2);
5648 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5649 if (CSize && CSize->getZExtValue() == 0) {
5650 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5651 setValue(&I, DAG.getConstant(0, CallVT));
5655 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5656 std::pair<SDValue, SDValue> Res =
5657 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5658 getValue(LHS), getValue(RHS), getValue(Size),
5659 MachinePointerInfo(LHS),
5660 MachinePointerInfo(RHS));
5661 if (Res.first.getNode()) {
5662 processIntegerCallValue(I, Res.first, true);
5663 PendingLoads.push_back(Res.second);
5667 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5668 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5669 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5670 bool ActuallyDoIt = true;
5673 switch (CSize->getZExtValue()) {
5675 LoadVT = MVT::Other;
5677 ActuallyDoIt = false;
5681 LoadTy = Type::getInt16Ty(CSize->getContext());
5685 LoadTy = Type::getInt32Ty(CSize->getContext());
5689 LoadTy = Type::getInt64Ty(CSize->getContext());
5693 LoadVT = MVT::v4i32;
5694 LoadTy = Type::getInt32Ty(CSize->getContext());
5695 LoadTy = VectorType::get(LoadTy, 4);
5700 // This turns into unaligned loads. We only do this if the target natively
5701 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5702 // we'll only produce a small number of byte loads.
5704 // Require that we can find a legal MVT, and only do this if the target
5705 // supports unaligned loads of that type. Expanding into byte loads would
5707 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5708 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5709 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5710 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5711 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5712 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5713 // TODO: Check alignment of src and dest ptrs.
5714 if (!TLI.isTypeLegal(LoadVT) ||
5715 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5716 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5717 ActuallyDoIt = false;
5721 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5722 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5724 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5726 processIntegerCallValue(I, Res, false);
5735 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5736 /// form. If so, return true and lower it, otherwise return false and it
5737 /// will be lowered like a normal call.
5738 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5739 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5740 if (I.getNumArgOperands() != 3)
5743 const Value *Src = I.getArgOperand(0);
5744 const Value *Char = I.getArgOperand(1);
5745 const Value *Length = I.getArgOperand(2);
5746 if (!Src->getType()->isPointerTy() ||
5747 !Char->getType()->isIntegerTy() ||
5748 !Length->getType()->isIntegerTy() ||
5749 !I.getType()->isPointerTy())
5752 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5753 std::pair<SDValue, SDValue> Res =
5754 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5755 getValue(Src), getValue(Char), getValue(Length),
5756 MachinePointerInfo(Src));
5757 if (Res.first.getNode()) {
5758 setValue(&I, Res.first);
5759 PendingLoads.push_back(Res.second);
5766 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5767 /// optimized form. If so, return true and lower it, otherwise return false
5768 /// and it will be lowered like a normal call.
5769 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5770 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5771 if (I.getNumArgOperands() != 2)
5774 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5775 if (!Arg0->getType()->isPointerTy() ||
5776 !Arg1->getType()->isPointerTy() ||
5777 !I.getType()->isPointerTy())
5780 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5781 std::pair<SDValue, SDValue> Res =
5782 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5783 getValue(Arg0), getValue(Arg1),
5784 MachinePointerInfo(Arg0),
5785 MachinePointerInfo(Arg1), isStpcpy);
5786 if (Res.first.getNode()) {
5787 setValue(&I, Res.first);
5788 DAG.setRoot(Res.second);
5795 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5796 /// If so, return true and lower it, otherwise return false and it will be
5797 /// lowered like a normal call.
5798 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5799 // Verify that the prototype makes sense. int strcmp(void*,void*)
5800 if (I.getNumArgOperands() != 2)
5803 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5804 if (!Arg0->getType()->isPointerTy() ||
5805 !Arg1->getType()->isPointerTy() ||
5806 !I.getType()->isIntegerTy())
5809 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5810 std::pair<SDValue, SDValue> Res =
5811 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5812 getValue(Arg0), getValue(Arg1),
5813 MachinePointerInfo(Arg0),
5814 MachinePointerInfo(Arg1));
5815 if (Res.first.getNode()) {
5816 processIntegerCallValue(I, Res.first, true);
5817 PendingLoads.push_back(Res.second);
5824 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5825 /// form. If so, return true and lower it, otherwise return false and it
5826 /// will be lowered like a normal call.
5827 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5828 // Verify that the prototype makes sense. size_t strlen(char *)
5829 if (I.getNumArgOperands() != 1)
5832 const Value *Arg0 = I.getArgOperand(0);
5833 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5836 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5837 std::pair<SDValue, SDValue> Res =
5838 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5839 getValue(Arg0), MachinePointerInfo(Arg0));
5840 if (Res.first.getNode()) {
5841 processIntegerCallValue(I, Res.first, false);
5842 PendingLoads.push_back(Res.second);
5849 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5850 /// form. If so, return true and lower it, otherwise return false and it
5851 /// will be lowered like a normal call.
5852 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5853 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5854 if (I.getNumArgOperands() != 2)
5857 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5858 if (!Arg0->getType()->isPointerTy() ||
5859 !Arg1->getType()->isIntegerTy() ||
5860 !I.getType()->isIntegerTy())
5863 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5864 std::pair<SDValue, SDValue> Res =
5865 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5866 getValue(Arg0), getValue(Arg1),
5867 MachinePointerInfo(Arg0));
5868 if (Res.first.getNode()) {
5869 processIntegerCallValue(I, Res.first, false);
5870 PendingLoads.push_back(Res.second);
5877 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5878 /// operation (as expected), translate it to an SDNode with the specified opcode
5879 /// and return true.
5880 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5882 // Sanity check that it really is a unary floating-point call.
5883 if (I.getNumArgOperands() != 1 ||
5884 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5885 I.getType() != I.getArgOperand(0)->getType() ||
5886 !I.onlyReadsMemory())
5889 SDValue Tmp = getValue(I.getArgOperand(0));
5890 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5894 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5895 /// operation (as expected), translate it to an SDNode with the specified opcode
5896 /// and return true.
5897 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5899 // Sanity check that it really is a binary floating-point call.
5900 if (I.getNumArgOperands() != 2 ||
5901 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5902 I.getType() != I.getArgOperand(0)->getType() ||
5903 I.getType() != I.getArgOperand(1)->getType() ||
5904 !I.onlyReadsMemory())
5907 SDValue Tmp0 = getValue(I.getArgOperand(0));
5908 SDValue Tmp1 = getValue(I.getArgOperand(1));
5909 EVT VT = Tmp0.getValueType();
5910 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5914 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5915 // Handle inline assembly differently.
5916 if (isa<InlineAsm>(I.getCalledValue())) {
5921 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5922 ComputeUsesVAFloatArgument(I, &MMI);
5924 const char *RenameFn = nullptr;
5925 if (Function *F = I.getCalledFunction()) {
5926 if (F->isDeclaration()) {
5927 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5928 if (unsigned IID = II->getIntrinsicID(F)) {
5929 RenameFn = visitIntrinsicCall(I, IID);
5934 if (unsigned IID = F->getIntrinsicID()) {
5935 RenameFn = visitIntrinsicCall(I, IID);
5941 // Check for well-known libc/libm calls. If the function is internal, it
5942 // can't be a library call.
5944 if (!F->hasLocalLinkage() && F->hasName() &&
5945 LibInfo->getLibFunc(F->getName(), Func) &&
5946 LibInfo->hasOptimizedCodeGen(Func)) {
5949 case LibFunc::copysign:
5950 case LibFunc::copysignf:
5951 case LibFunc::copysignl:
5952 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5953 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5954 I.getType() == I.getArgOperand(0)->getType() &&
5955 I.getType() == I.getArgOperand(1)->getType() &&
5956 I.onlyReadsMemory()) {
5957 SDValue LHS = getValue(I.getArgOperand(0));
5958 SDValue RHS = getValue(I.getArgOperand(1));
5959 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5960 LHS.getValueType(), LHS, RHS));
5965 case LibFunc::fabsf:
5966 case LibFunc::fabsl:
5967 if (visitUnaryFloatCall(I, ISD::FABS))
5971 case LibFunc::fminf:
5972 case LibFunc::fminl:
5973 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5977 case LibFunc::fmaxf:
5978 case LibFunc::fmaxl:
5979 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5985 if (visitUnaryFloatCall(I, ISD::FSIN))
5991 if (visitUnaryFloatCall(I, ISD::FCOS))
5995 case LibFunc::sqrtf:
5996 case LibFunc::sqrtl:
5997 case LibFunc::sqrt_finite:
5998 case LibFunc::sqrtf_finite:
5999 case LibFunc::sqrtl_finite:
6000 if (visitUnaryFloatCall(I, ISD::FSQRT))
6003 case LibFunc::floor:
6004 case LibFunc::floorf:
6005 case LibFunc::floorl:
6006 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6009 case LibFunc::nearbyint:
6010 case LibFunc::nearbyintf:
6011 case LibFunc::nearbyintl:
6012 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6016 case LibFunc::ceilf:
6017 case LibFunc::ceill:
6018 if (visitUnaryFloatCall(I, ISD::FCEIL))
6022 case LibFunc::rintf:
6023 case LibFunc::rintl:
6024 if (visitUnaryFloatCall(I, ISD::FRINT))
6027 case LibFunc::round:
6028 case LibFunc::roundf:
6029 case LibFunc::roundl:
6030 if (visitUnaryFloatCall(I, ISD::FROUND))
6033 case LibFunc::trunc:
6034 case LibFunc::truncf:
6035 case LibFunc::truncl:
6036 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6040 case LibFunc::log2f:
6041 case LibFunc::log2l:
6042 if (visitUnaryFloatCall(I, ISD::FLOG2))
6046 case LibFunc::exp2f:
6047 case LibFunc::exp2l:
6048 if (visitUnaryFloatCall(I, ISD::FEXP2))
6051 case LibFunc::memcmp:
6052 if (visitMemCmpCall(I))
6055 case LibFunc::memchr:
6056 if (visitMemChrCall(I))
6059 case LibFunc::strcpy:
6060 if (visitStrCpyCall(I, false))
6063 case LibFunc::stpcpy:
6064 if (visitStrCpyCall(I, true))
6067 case LibFunc::strcmp:
6068 if (visitStrCmpCall(I))
6071 case LibFunc::strlen:
6072 if (visitStrLenCall(I))
6075 case LibFunc::strnlen:
6076 if (visitStrNLenCall(I))
6085 Callee = getValue(I.getCalledValue());
6087 Callee = DAG.getExternalSymbol(RenameFn,
6088 DAG.getTargetLoweringInfo().getPointerTy());
6090 // Check if we can potentially perform a tail call. More detailed checking is
6091 // be done within LowerCallTo, after more information about the call is known.
6092 LowerCallTo(&I, Callee, I.isTailCall());
6097 /// AsmOperandInfo - This contains information for each constraint that we are
6099 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6101 /// CallOperand - If this is the result output operand or a clobber
6102 /// this is null, otherwise it is the incoming operand to the CallInst.
6103 /// This gets modified as the asm is processed.
6104 SDValue CallOperand;
6106 /// AssignedRegs - If this is a register or register class operand, this
6107 /// contains the set of register corresponding to the operand.
6108 RegsForValue AssignedRegs;
6110 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6111 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6114 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6115 /// corresponds to. If there is no Value* for this operand, it returns
6117 EVT getCallOperandValEVT(LLVMContext &Context,
6118 const TargetLowering &TLI,
6119 const DataLayout *DL) const {
6120 if (!CallOperandVal) return MVT::Other;
6122 if (isa<BasicBlock>(CallOperandVal))
6123 return TLI.getPointerTy();
6125 llvm::Type *OpTy = CallOperandVal->getType();
6127 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6128 // If this is an indirect operand, the operand is a pointer to the
6131 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6133 report_fatal_error("Indirect operand for inline asm not a pointer!");
6134 OpTy = PtrTy->getElementType();
6137 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6138 if (StructType *STy = dyn_cast<StructType>(OpTy))
6139 if (STy->getNumElements() == 1)
6140 OpTy = STy->getElementType(0);
6142 // If OpTy is not a single value, it may be a struct/union that we
6143 // can tile with integers.
6144 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6145 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6154 OpTy = IntegerType::get(Context, BitSize);
6159 return TLI.getValueType(OpTy, true);
6163 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6165 } // end anonymous namespace
6167 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6168 /// specified operand. We prefer to assign virtual registers, to allow the
6169 /// register allocator to handle the assignment process. However, if the asm
6170 /// uses features that we can't model on machineinstrs, we have SDISel do the
6171 /// allocation. This produces generally horrible, but correct, code.
6173 /// OpInfo describes the operand.
6175 static void GetRegistersForValue(SelectionDAG &DAG,
6176 const TargetLowering &TLI,
6178 SDISelAsmOperandInfo &OpInfo) {
6179 LLVMContext &Context = *DAG.getContext();
6181 MachineFunction &MF = DAG.getMachineFunction();
6182 SmallVector<unsigned, 4> Regs;
6184 // If this is a constraint for a single physreg, or a constraint for a
6185 // register class, find it.
6186 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6187 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6188 OpInfo.ConstraintCode,
6189 OpInfo.ConstraintVT);
6191 unsigned NumRegs = 1;
6192 if (OpInfo.ConstraintVT != MVT::Other) {
6193 // If this is a FP input in an integer register (or visa versa) insert a bit
6194 // cast of the input value. More generally, handle any case where the input
6195 // value disagrees with the register class we plan to stick this in.
6196 if (OpInfo.Type == InlineAsm::isInput &&
6197 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6198 // Try to convert to the first EVT that the reg class contains. If the
6199 // types are identical size, use a bitcast to convert (e.g. two differing
6201 MVT RegVT = *PhysReg.second->vt_begin();
6202 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6203 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6204 RegVT, OpInfo.CallOperand);
6205 OpInfo.ConstraintVT = RegVT;
6206 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6207 // If the input is a FP value and we want it in FP registers, do a
6208 // bitcast to the corresponding integer type. This turns an f64 value
6209 // into i64, which can be passed with two i32 values on a 32-bit
6211 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6212 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6213 RegVT, OpInfo.CallOperand);
6214 OpInfo.ConstraintVT = RegVT;
6218 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6222 EVT ValueVT = OpInfo.ConstraintVT;
6224 // If this is a constraint for a specific physical register, like {r17},
6226 if (unsigned AssignedReg = PhysReg.first) {
6227 const TargetRegisterClass *RC = PhysReg.second;
6228 if (OpInfo.ConstraintVT == MVT::Other)
6229 ValueVT = *RC->vt_begin();
6231 // Get the actual register value type. This is important, because the user
6232 // may have asked for (e.g.) the AX register in i32 type. We need to
6233 // remember that AX is actually i16 to get the right extension.
6234 RegVT = *RC->vt_begin();
6236 // This is a explicit reference to a physical register.
6237 Regs.push_back(AssignedReg);
6239 // If this is an expanded reference, add the rest of the regs to Regs.
6241 TargetRegisterClass::iterator I = RC->begin();
6242 for (; *I != AssignedReg; ++I)
6243 assert(I != RC->end() && "Didn't find reg!");
6245 // Already added the first reg.
6247 for (; NumRegs; --NumRegs, ++I) {
6248 assert(I != RC->end() && "Ran out of registers to allocate!");
6253 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6257 // Otherwise, if this was a reference to an LLVM register class, create vregs
6258 // for this reference.
6259 if (const TargetRegisterClass *RC = PhysReg.second) {
6260 RegVT = *RC->vt_begin();
6261 if (OpInfo.ConstraintVT == MVT::Other)
6264 // Create the appropriate number of virtual registers.
6265 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6266 for (; NumRegs; --NumRegs)
6267 Regs.push_back(RegInfo.createVirtualRegister(RC));
6269 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6273 // Otherwise, we couldn't allocate enough registers for this.
6276 /// visitInlineAsm - Handle a call to an InlineAsm object.
6278 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6279 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6281 /// ConstraintOperands - Information about all of the constraints.
6282 SDISelAsmOperandInfoVector ConstraintOperands;
6284 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6285 TargetLowering::AsmOperandInfoVector TargetConstraints =
6286 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
6288 bool hasMemory = false;
6290 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6291 unsigned ResNo = 0; // ResNo - The result number of the next output.
6292 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6293 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6294 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6296 MVT OpVT = MVT::Other;
6298 // Compute the value type for each operand.
6299 switch (OpInfo.Type) {
6300 case InlineAsm::isOutput:
6301 // Indirect outputs just consume an argument.
6302 if (OpInfo.isIndirect) {
6303 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6307 // The return value of the call is this value. As such, there is no
6308 // corresponding argument.
6309 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6310 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6311 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6313 assert(ResNo == 0 && "Asm only has one result!");
6314 OpVT = TLI.getSimpleValueType(CS.getType());
6318 case InlineAsm::isInput:
6319 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6321 case InlineAsm::isClobber:
6326 // If this is an input or an indirect output, process the call argument.
6327 // BasicBlocks are labels, currently appearing only in asm's.
6328 if (OpInfo.CallOperandVal) {
6329 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6330 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6332 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6336 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6339 OpInfo.ConstraintVT = OpVT;
6341 // Indirect operand accesses access memory.
6342 if (OpInfo.isIndirect)
6345 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6346 TargetLowering::ConstraintType
6347 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6348 if (CType == TargetLowering::C_Memory) {
6356 SDValue Chain, Flag;
6358 // We won't need to flush pending loads if this asm doesn't touch
6359 // memory and is nonvolatile.
6360 if (hasMemory || IA->hasSideEffects())
6363 Chain = DAG.getRoot();
6365 // Second pass over the constraints: compute which constraint option to use
6366 // and assign registers to constraints that want a specific physreg.
6367 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6368 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6370 // If this is an output operand with a matching input operand, look up the
6371 // matching input. If their types mismatch, e.g. one is an integer, the
6372 // other is floating point, or their sizes are different, flag it as an
6374 if (OpInfo.hasMatchingInput()) {
6375 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6377 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6378 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6379 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6380 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6381 OpInfo.ConstraintVT);
6382 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6383 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6384 Input.ConstraintVT);
6385 if ((OpInfo.ConstraintVT.isInteger() !=
6386 Input.ConstraintVT.isInteger()) ||
6387 (MatchRC.second != InputRC.second)) {
6388 report_fatal_error("Unsupported asm: input constraint"
6389 " with a matching output constraint of"
6390 " incompatible type!");
6392 Input.ConstraintVT = OpInfo.ConstraintVT;
6396 // Compute the constraint code and ConstraintType to use.
6397 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6399 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6400 OpInfo.Type == InlineAsm::isClobber)
6403 // If this is a memory input, and if the operand is not indirect, do what we
6404 // need to to provide an address for the memory input.
6405 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6406 !OpInfo.isIndirect) {
6407 assert((OpInfo.isMultipleAlternative ||
6408 (OpInfo.Type == InlineAsm::isInput)) &&
6409 "Can only indirectify direct input operands!");
6411 // Memory operands really want the address of the value. If we don't have
6412 // an indirect input, put it in the constpool if we can, otherwise spill
6413 // it to a stack slot.
6414 // TODO: This isn't quite right. We need to handle these according to
6415 // the addressing mode that the constraint wants. Also, this may take
6416 // an additional register for the computation and we don't want that
6419 // If the operand is a float, integer, or vector constant, spill to a
6420 // constant pool entry to get its address.
6421 const Value *OpVal = OpInfo.CallOperandVal;
6422 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6423 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6424 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6425 TLI.getPointerTy());
6427 // Otherwise, create a stack slot and emit a store to it before the
6429 Type *Ty = OpVal->getType();
6430 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6431 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6432 MachineFunction &MF = DAG.getMachineFunction();
6433 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6434 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6435 Chain = DAG.getStore(Chain, getCurSDLoc(),
6436 OpInfo.CallOperand, StackSlot,
6437 MachinePointerInfo::getFixedStack(SSFI),
6439 OpInfo.CallOperand = StackSlot;
6442 // There is no longer a Value* corresponding to this operand.
6443 OpInfo.CallOperandVal = nullptr;
6445 // It is now an indirect operand.
6446 OpInfo.isIndirect = true;
6449 // If this constraint is for a specific register, allocate it before
6451 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6452 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6455 // Second pass - Loop over all of the operands, assigning virtual or physregs
6456 // to register class operands.
6457 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6458 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6460 // C_Register operands have already been allocated, Other/Memory don't need
6462 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6463 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6466 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6467 std::vector<SDValue> AsmNodeOperands;
6468 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6469 AsmNodeOperands.push_back(
6470 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6471 TLI.getPointerTy()));
6473 // If we have a !srcloc metadata node associated with it, we want to attach
6474 // this to the ultimately generated inline asm machineinstr. To do this, we
6475 // pass in the third operand as this (potentially null) inline asm MDNode.
6476 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6477 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6479 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6480 // bits as operand 3.
6481 unsigned ExtraInfo = 0;
6482 if (IA->hasSideEffects())
6483 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6484 if (IA->isAlignStack())
6485 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6486 // Set the asm dialect.
6487 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6489 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6490 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6491 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6493 // Compute the constraint code and ConstraintType to use.
6494 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6496 // Ideally, we would only check against memory constraints. However, the
6497 // meaning of an other constraint can be target-specific and we can't easily
6498 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6499 // for other constriants as well.
6500 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6501 OpInfo.ConstraintType == TargetLowering::C_Other) {
6502 if (OpInfo.Type == InlineAsm::isInput)
6503 ExtraInfo |= InlineAsm::Extra_MayLoad;
6504 else if (OpInfo.Type == InlineAsm::isOutput)
6505 ExtraInfo |= InlineAsm::Extra_MayStore;
6506 else if (OpInfo.Type == InlineAsm::isClobber)
6507 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6511 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6512 TLI.getPointerTy()));
6514 // Loop over all of the inputs, copying the operand values into the
6515 // appropriate registers and processing the output regs.
6516 RegsForValue RetValRegs;
6518 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6519 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6521 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6522 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6524 switch (OpInfo.Type) {
6525 case InlineAsm::isOutput: {
6526 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6527 OpInfo.ConstraintType != TargetLowering::C_Register) {
6528 // Memory output, or 'other' output (e.g. 'X' constraint).
6529 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6531 unsigned ConstraintID =
6532 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6533 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6534 "Failed to convert memory constraint code to constraint id.");
6536 // Add information to the INLINEASM node to know about this output.
6537 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6538 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6539 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
6540 AsmNodeOperands.push_back(OpInfo.CallOperand);
6544 // Otherwise, this is a register or register class output.
6546 // Copy the output from the appropriate register. Find a register that
6548 if (OpInfo.AssignedRegs.Regs.empty()) {
6549 LLVMContext &Ctx = *DAG.getContext();
6550 Ctx.emitError(CS.getInstruction(),
6551 "couldn't allocate output register for constraint '" +
6552 Twine(OpInfo.ConstraintCode) + "'");
6556 // If this is an indirect operand, store through the pointer after the
6558 if (OpInfo.isIndirect) {
6559 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6560 OpInfo.CallOperandVal));
6562 // This is the result value of the call.
6563 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6564 // Concatenate this output onto the outputs list.
6565 RetValRegs.append(OpInfo.AssignedRegs);
6568 // Add information to the INLINEASM node to know that this register is
6571 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6572 ? InlineAsm::Kind_RegDefEarlyClobber
6573 : InlineAsm::Kind_RegDef,
6574 false, 0, DAG, AsmNodeOperands);
6577 case InlineAsm::isInput: {
6578 SDValue InOperandVal = OpInfo.CallOperand;
6580 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6581 // If this is required to match an output register we have already set,
6582 // just use its register.
6583 unsigned OperandNo = OpInfo.getMatchedOperand();
6585 // Scan until we find the definition we already emitted of this operand.
6586 // When we find it, create a RegsForValue operand.
6587 unsigned CurOp = InlineAsm::Op_FirstOperand;
6588 for (; OperandNo; --OperandNo) {
6589 // Advance to the next operand.
6591 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6592 assert((InlineAsm::isRegDefKind(OpFlag) ||
6593 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6594 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6595 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6599 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6600 if (InlineAsm::isRegDefKind(OpFlag) ||
6601 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6602 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6603 if (OpInfo.isIndirect) {
6604 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6605 LLVMContext &Ctx = *DAG.getContext();
6606 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6607 " don't know how to handle tied "
6608 "indirect register inputs");
6612 RegsForValue MatchedRegs;
6613 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6614 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6615 MatchedRegs.RegVTs.push_back(RegVT);
6616 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6617 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6619 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6620 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6622 LLVMContext &Ctx = *DAG.getContext();
6623 Ctx.emitError(CS.getInstruction(),
6624 "inline asm error: This value"
6625 " type register class is not natively supported!");
6629 // Use the produced MatchedRegs object to
6630 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6631 Chain, &Flag, CS.getInstruction());
6632 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6633 true, OpInfo.getMatchedOperand(),
6634 DAG, AsmNodeOperands);
6638 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6639 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6640 "Unexpected number of operands");
6641 // Add information to the INLINEASM node to know about this input.
6642 // See InlineAsm.h isUseOperandTiedToDef.
6643 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6644 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6645 OpInfo.getMatchedOperand());
6646 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6647 TLI.getPointerTy()));
6648 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6652 // Treat indirect 'X' constraint as memory.
6653 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6655 OpInfo.ConstraintType = TargetLowering::C_Memory;
6657 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6658 std::vector<SDValue> Ops;
6659 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6662 LLVMContext &Ctx = *DAG.getContext();
6663 Ctx.emitError(CS.getInstruction(),
6664 "invalid operand for inline asm constraint '" +
6665 Twine(OpInfo.ConstraintCode) + "'");
6669 // Add information to the INLINEASM node to know about this input.
6670 unsigned ResOpType =
6671 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6672 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6673 TLI.getPointerTy()));
6674 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6678 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6679 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6680 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6681 "Memory operands expect pointer values");
6683 unsigned ConstraintID =
6684 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6685 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6686 "Failed to convert memory constraint code to constraint id.");
6688 // Add information to the INLINEASM node to know about this input.
6689 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6690 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6691 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
6692 AsmNodeOperands.push_back(InOperandVal);
6696 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6697 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6698 "Unknown constraint type!");
6700 // TODO: Support this.
6701 if (OpInfo.isIndirect) {
6702 LLVMContext &Ctx = *DAG.getContext();
6703 Ctx.emitError(CS.getInstruction(),
6704 "Don't know how to handle indirect register inputs yet "
6705 "for constraint '" +
6706 Twine(OpInfo.ConstraintCode) + "'");
6710 // Copy the input into the appropriate registers.
6711 if (OpInfo.AssignedRegs.Regs.empty()) {
6712 LLVMContext &Ctx = *DAG.getContext();
6713 Ctx.emitError(CS.getInstruction(),
6714 "couldn't allocate input reg for constraint '" +
6715 Twine(OpInfo.ConstraintCode) + "'");
6719 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6720 Chain, &Flag, CS.getInstruction());
6722 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6723 DAG, AsmNodeOperands);
6726 case InlineAsm::isClobber: {
6727 // Add the clobbered value to the operand list, so that the register
6728 // allocator is aware that the physreg got clobbered.
6729 if (!OpInfo.AssignedRegs.Regs.empty())
6730 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6738 // Finish up input operands. Set the input chain and add the flag last.
6739 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6740 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6742 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6743 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6744 Flag = Chain.getValue(1);
6746 // If this asm returns a register value, copy the result from that register
6747 // and set it as the value of the call.
6748 if (!RetValRegs.Regs.empty()) {
6749 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6750 Chain, &Flag, CS.getInstruction());
6752 // FIXME: Why don't we do this for inline asms with MRVs?
6753 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6754 EVT ResultType = TLI.getValueType(CS.getType());
6756 // If any of the results of the inline asm is a vector, it may have the
6757 // wrong width/num elts. This can happen for register classes that can
6758 // contain multiple different value types. The preg or vreg allocated may
6759 // not have the same VT as was expected. Convert it to the right type
6760 // with bit_convert.
6761 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6762 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6765 } else if (ResultType != Val.getValueType() &&
6766 ResultType.isInteger() && Val.getValueType().isInteger()) {
6767 // If a result value was tied to an input value, the computed result may
6768 // have a wider width than the expected result. Extract the relevant
6770 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6773 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6776 setValue(CS.getInstruction(), Val);
6777 // Don't need to use this as a chain in this case.
6778 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6782 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6784 // Process indirect outputs, first output all of the flagged copies out of
6786 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6787 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6788 const Value *Ptr = IndirectStoresToEmit[i].second;
6789 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6791 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6794 // Emit the non-flagged stores from the physregs.
6795 SmallVector<SDValue, 8> OutChains;
6796 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6797 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6798 StoresToEmit[i].first,
6799 getValue(StoresToEmit[i].second),
6800 MachinePointerInfo(StoresToEmit[i].second),
6802 OutChains.push_back(Val);
6805 if (!OutChains.empty())
6806 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6811 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6812 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6813 MVT::Other, getRoot(),
6814 getValue(I.getArgOperand(0)),
6815 DAG.getSrcValue(I.getArgOperand(0))));
6818 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6820 const DataLayout &DL = *TLI.getDataLayout();
6821 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6822 getRoot(), getValue(I.getOperand(0)),
6823 DAG.getSrcValue(I.getOperand(0)),
6824 DL.getABITypeAlignment(I.getType()));
6826 DAG.setRoot(V.getValue(1));
6829 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6830 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6831 MVT::Other, getRoot(),
6832 getValue(I.getArgOperand(0)),
6833 DAG.getSrcValue(I.getArgOperand(0))));
6836 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6837 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6838 MVT::Other, getRoot(),
6839 getValue(I.getArgOperand(0)),
6840 getValue(I.getArgOperand(1)),
6841 DAG.getSrcValue(I.getArgOperand(0)),
6842 DAG.getSrcValue(I.getArgOperand(1))));
6845 /// \brief Lower an argument list according to the target calling convention.
6847 /// \return A tuple of <return-value, token-chain>
6849 /// This is a helper for lowering intrinsics that follow a target calling
6850 /// convention or require stack pointer adjustment. Only a subset of the
6851 /// intrinsic's operands need to participate in the calling convention.
6852 std::pair<SDValue, SDValue>
6853 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6854 unsigned NumArgs, SDValue Callee,
6856 MachineBasicBlock *LandingPad,
6857 bool IsPatchPoint) {
6858 TargetLowering::ArgListTy Args;
6859 Args.reserve(NumArgs);
6861 // Populate the argument list.
6862 // Attributes for args start at offset 1, after the return attribute.
6863 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6864 ArgI != ArgE; ++ArgI) {
6865 const Value *V = CS->getOperand(ArgI);
6867 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6869 TargetLowering::ArgListEntry Entry;
6870 Entry.Node = getValue(V);
6871 Entry.Ty = V->getType();
6872 Entry.setAttributes(&CS, AttrI);
6873 Args.push_back(Entry);
6876 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6877 TargetLowering::CallLoweringInfo CLI(DAG);
6878 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6879 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6880 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6882 return lowerInvokable(CLI, LandingPad);
6885 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6886 /// or patchpoint target node's operand list.
6888 /// Constants are converted to TargetConstants purely as an optimization to
6889 /// avoid constant materialization and register allocation.
6891 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6892 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6893 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6894 /// address materialization and register allocation, but may also be required
6895 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6896 /// alloca in the entry block, then the runtime may assume that the alloca's
6897 /// StackMap location can be read immediately after compilation and that the
6898 /// location is valid at any point during execution (this is similar to the
6899 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6900 /// only available in a register, then the runtime would need to trap when
6901 /// execution reaches the StackMap in order to read the alloca's location.
6902 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6903 SmallVectorImpl<SDValue> &Ops,
6904 SelectionDAGBuilder &Builder) {
6905 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6906 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6907 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6909 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6911 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6912 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6913 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6915 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6917 Ops.push_back(OpVal);
6921 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6922 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6923 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6924 // [live variables...])
6926 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6928 SDValue Chain, InFlag, Callee, NullPtr;
6929 SmallVector<SDValue, 32> Ops;
6931 SDLoc DL = getCurSDLoc();
6932 Callee = getValue(CI.getCalledValue());
6933 NullPtr = DAG.getIntPtrConstant(0, true);
6935 // The stackmap intrinsic only records the live variables (the arguemnts
6936 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6937 // intrinsic, this won't be lowered to a function call. This means we don't
6938 // have to worry about calling conventions and target specific lowering code.
6939 // Instead we perform the call lowering right here.
6941 // chain, flag = CALLSEQ_START(chain, 0)
6942 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6943 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6945 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6946 InFlag = Chain.getValue(1);
6948 // Add the <id> and <numBytes> constants.
6949 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6950 Ops.push_back(DAG.getTargetConstant(
6951 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6952 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6953 Ops.push_back(DAG.getTargetConstant(
6954 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6956 // Push live variables for the stack map.
6957 addStackMapLiveVars(&CI, 2, Ops, *this);
6959 // We are not pushing any register mask info here on the operands list,
6960 // because the stackmap doesn't clobber anything.
6962 // Push the chain and the glue flag.
6963 Ops.push_back(Chain);
6964 Ops.push_back(InFlag);
6966 // Create the STACKMAP node.
6967 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6968 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6969 Chain = SDValue(SM, 0);
6970 InFlag = Chain.getValue(1);
6972 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6974 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6976 // Set the root to the target-lowered call chain.
6979 // Inform the Frame Information that we have a stackmap in this function.
6980 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6983 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6984 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6985 MachineBasicBlock *LandingPad) {
6986 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6991 // [live variables...])
6993 CallingConv::ID CC = CS.getCallingConv();
6994 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6995 bool HasDef = !CS->getType()->isVoidTy();
6996 SDValue Callee = getValue(CS->getOperand(2)); // <target>
6998 // Get the real number of arguments participating in the call <numArgs>
6999 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7000 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7002 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7003 // Intrinsics include all meta-operands up to but not including CC.
7004 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7005 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7006 "Not enough arguments provided to the patchpoint intrinsic");
7008 // For AnyRegCC the arguments are lowered later on manually.
7009 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7010 std::pair<SDValue, SDValue> Result =
7011 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7014 SDNode *CallEnd = Result.second.getNode();
7015 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7016 CallEnd = CallEnd->getOperand(0).getNode();
7018 /// Get a call instruction from the call sequence chain.
7019 /// Tail calls are not allowed.
7020 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7021 "Expected a callseq node.");
7022 SDNode *Call = CallEnd->getOperand(0).getNode();
7023 bool HasGlue = Call->getGluedNode();
7025 // Replace the target specific call node with the patchable intrinsic.
7026 SmallVector<SDValue, 8> Ops;
7028 // Add the <id> and <numBytes> constants.
7029 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7030 Ops.push_back(DAG.getTargetConstant(
7031 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7032 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7033 Ops.push_back(DAG.getTargetConstant(
7034 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7036 // Assume that the Callee is a constant address.
7037 // FIXME: handle function symbols in the future.
7039 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7040 /*isTarget=*/true));
7042 // Adjust <numArgs> to account for any arguments that have been passed on the
7044 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7045 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7046 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7047 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7049 // Add the calling convention
7050 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7052 // Add the arguments we omitted previously. The register allocator should
7053 // place these in any free register.
7055 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7056 Ops.push_back(getValue(CS.getArgument(i)));
7058 // Push the arguments from the call instruction up to the register mask.
7059 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7060 Ops.append(Call->op_begin() + 2, e);
7062 // Push live variables for the stack map.
7063 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7065 // Push the register mask info.
7067 Ops.push_back(*(Call->op_end()-2));
7069 Ops.push_back(*(Call->op_end()-1));
7071 // Push the chain (this is originally the first operand of the call, but
7072 // becomes now the last or second to last operand).
7073 Ops.push_back(*(Call->op_begin()));
7075 // Push the glue flag (last operand).
7077 Ops.push_back(*(Call->op_end()-1));
7080 if (IsAnyRegCC && HasDef) {
7081 // Create the return types based on the intrinsic definition
7082 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7083 SmallVector<EVT, 3> ValueVTs;
7084 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7085 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7087 // There is always a chain and a glue type at the end
7088 ValueVTs.push_back(MVT::Other);
7089 ValueVTs.push_back(MVT::Glue);
7090 NodeTys = DAG.getVTList(ValueVTs);
7092 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7094 // Replace the target specific call node with a PATCHPOINT node.
7095 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7096 getCurSDLoc(), NodeTys, Ops);
7098 // Update the NodeMap.
7101 setValue(CS.getInstruction(), SDValue(MN, 0));
7103 setValue(CS.getInstruction(), Result.first);
7106 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7107 // call sequence. Furthermore the location of the chain and glue can change
7108 // when the AnyReg calling convention is used and the intrinsic returns a
7110 if (IsAnyRegCC && HasDef) {
7111 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7112 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7113 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7115 DAG.ReplaceAllUsesWith(Call, MN);
7116 DAG.DeleteNode(Call);
7118 // Inform the Frame Information that we have a patchpoint in this function.
7119 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7122 /// Returns an AttributeSet representing the attributes applied to the return
7123 /// value of the given call.
7124 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7125 SmallVector<Attribute::AttrKind, 2> Attrs;
7127 Attrs.push_back(Attribute::SExt);
7129 Attrs.push_back(Attribute::ZExt);
7131 Attrs.push_back(Attribute::InReg);
7133 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7137 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7138 /// implementation, which just calls LowerCall.
7139 /// FIXME: When all targets are
7140 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7141 std::pair<SDValue, SDValue>
7142 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7143 // Handle the incoming return values from the call.
7145 Type *OrigRetTy = CLI.RetTy;
7146 SmallVector<EVT, 4> RetTys;
7147 SmallVector<uint64_t, 4> Offsets;
7148 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7150 SmallVector<ISD::OutputArg, 4> Outs;
7151 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7153 bool CanLowerReturn =
7154 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7155 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7157 SDValue DemoteStackSlot;
7158 int DemoteStackIdx = -100;
7159 if (!CanLowerReturn) {
7160 // FIXME: equivalent assert?
7161 // assert(!CS.hasInAllocaArgument() &&
7162 // "sret demotion is incompatible with inalloca");
7163 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7164 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7165 MachineFunction &MF = CLI.DAG.getMachineFunction();
7166 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7167 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7169 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7171 Entry.Node = DemoteStackSlot;
7172 Entry.Ty = StackSlotPtrType;
7173 Entry.isSExt = false;
7174 Entry.isZExt = false;
7175 Entry.isInReg = false;
7176 Entry.isSRet = true;
7177 Entry.isNest = false;
7178 Entry.isByVal = false;
7179 Entry.isReturned = false;
7180 Entry.Alignment = Align;
7181 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7182 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7184 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7186 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7187 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7188 for (unsigned i = 0; i != NumRegs; ++i) {
7189 ISD::InputArg MyFlags;
7190 MyFlags.VT = RegisterVT;
7192 MyFlags.Used = CLI.IsReturnValueUsed;
7194 MyFlags.Flags.setSExt();
7196 MyFlags.Flags.setZExt();
7198 MyFlags.Flags.setInReg();
7199 CLI.Ins.push_back(MyFlags);
7204 // Handle all of the outgoing arguments.
7206 CLI.OutVals.clear();
7207 ArgListTy &Args = CLI.getArgs();
7208 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7209 SmallVector<EVT, 4> ValueVTs;
7210 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7211 Type *FinalType = Args[i].Ty;
7212 if (Args[i].isByVal)
7213 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7214 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7215 FinalType, CLI.CallConv, CLI.IsVarArg);
7216 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7218 EVT VT = ValueVTs[Value];
7219 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7220 SDValue Op = SDValue(Args[i].Node.getNode(),
7221 Args[i].Node.getResNo() + Value);
7222 ISD::ArgFlagsTy Flags;
7223 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7229 if (Args[i].isInReg)
7233 if (Args[i].isByVal)
7235 if (Args[i].isInAlloca) {
7236 Flags.setInAlloca();
7237 // Set the byval flag for CCAssignFn callbacks that don't know about
7238 // inalloca. This way we can know how many bytes we should've allocated
7239 // and how many bytes a callee cleanup function will pop. If we port
7240 // inalloca to more targets, we'll have to add custom inalloca handling
7241 // in the various CC lowering callbacks.
7244 if (Args[i].isByVal || Args[i].isInAlloca) {
7245 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7246 Type *ElementTy = Ty->getElementType();
7247 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7248 // For ByVal, alignment should come from FE. BE will guess if this
7249 // info is not there but there are cases it cannot get right.
7250 unsigned FrameAlign;
7251 if (Args[i].Alignment)
7252 FrameAlign = Args[i].Alignment;
7254 FrameAlign = getByValTypeAlignment(ElementTy);
7255 Flags.setByValAlign(FrameAlign);
7260 Flags.setInConsecutiveRegs();
7261 Flags.setOrigAlign(OriginalAlignment);
7263 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7264 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7265 SmallVector<SDValue, 4> Parts(NumParts);
7266 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7269 ExtendKind = ISD::SIGN_EXTEND;
7270 else if (Args[i].isZExt)
7271 ExtendKind = ISD::ZERO_EXTEND;
7273 // Conservatively only handle 'returned' on non-vectors for now
7274 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7275 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7276 "unexpected use of 'returned'");
7277 // Before passing 'returned' to the target lowering code, ensure that
7278 // either the register MVT and the actual EVT are the same size or that
7279 // the return value and argument are extended in the same way; in these
7280 // cases it's safe to pass the argument register value unchanged as the
7281 // return register value (although it's at the target's option whether
7283 // TODO: allow code generation to take advantage of partially preserved
7284 // registers rather than clobbering the entire register when the
7285 // parameter extension method is not compatible with the return
7287 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7288 (ExtendKind != ISD::ANY_EXTEND &&
7289 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7290 Flags.setReturned();
7293 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7294 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7296 for (unsigned j = 0; j != NumParts; ++j) {
7297 // if it isn't first piece, alignment must be 1
7298 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7299 i < CLI.NumFixedArgs,
7300 i, j*Parts[j].getValueType().getStoreSize());
7301 if (NumParts > 1 && j == 0)
7302 MyFlags.Flags.setSplit();
7304 MyFlags.Flags.setOrigAlign(1);
7306 CLI.Outs.push_back(MyFlags);
7307 CLI.OutVals.push_back(Parts[j]);
7310 if (NeedsRegBlock && Value == NumValues - 1)
7311 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7315 SmallVector<SDValue, 4> InVals;
7316 CLI.Chain = LowerCall(CLI, InVals);
7318 // Verify that the target's LowerCall behaved as expected.
7319 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7320 "LowerCall didn't return a valid chain!");
7321 assert((!CLI.IsTailCall || InVals.empty()) &&
7322 "LowerCall emitted a return value for a tail call!");
7323 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7324 "LowerCall didn't emit the correct number of values!");
7326 // For a tail call, the return value is merely live-out and there aren't
7327 // any nodes in the DAG representing it. Return a special value to
7328 // indicate that a tail call has been emitted and no more Instructions
7329 // should be processed in the current block.
7330 if (CLI.IsTailCall) {
7331 CLI.DAG.setRoot(CLI.Chain);
7332 return std::make_pair(SDValue(), SDValue());
7335 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7336 assert(InVals[i].getNode() &&
7337 "LowerCall emitted a null value!");
7338 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7339 "LowerCall emitted a value with the wrong type!");
7342 SmallVector<SDValue, 4> ReturnValues;
7343 if (!CanLowerReturn) {
7344 // The instruction result is the result of loading from the
7345 // hidden sret parameter.
7346 SmallVector<EVT, 1> PVTs;
7347 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7349 ComputeValueVTs(*this, PtrRetTy, PVTs);
7350 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7351 EVT PtrVT = PVTs[0];
7353 unsigned NumValues = RetTys.size();
7354 ReturnValues.resize(NumValues);
7355 SmallVector<SDValue, 4> Chains(NumValues);
7357 for (unsigned i = 0; i < NumValues; ++i) {
7358 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7359 CLI.DAG.getConstant(Offsets[i], PtrVT));
7360 SDValue L = CLI.DAG.getLoad(
7361 RetTys[i], CLI.DL, CLI.Chain, Add,
7362 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7364 ReturnValues[i] = L;
7365 Chains[i] = L.getValue(1);
7368 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7370 // Collect the legal value parts into potentially illegal values
7371 // that correspond to the original function's return values.
7372 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7374 AssertOp = ISD::AssertSext;
7375 else if (CLI.RetZExt)
7376 AssertOp = ISD::AssertZext;
7377 unsigned CurReg = 0;
7378 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7380 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7381 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7383 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7384 NumRegs, RegisterVT, VT, nullptr,
7389 // For a function returning void, there is no return value. We can't create
7390 // such a node, so we just return a null return value in that case. In
7391 // that case, nothing will actually look at the value.
7392 if (ReturnValues.empty())
7393 return std::make_pair(SDValue(), CLI.Chain);
7396 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7397 CLI.DAG.getVTList(RetTys), ReturnValues);
7398 return std::make_pair(Res, CLI.Chain);
7401 void TargetLowering::LowerOperationWrapper(SDNode *N,
7402 SmallVectorImpl<SDValue> &Results,
7403 SelectionDAG &DAG) const {
7404 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7406 Results.push_back(Res);
7409 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7410 llvm_unreachable("LowerOperation not implemented for this target!");
7414 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7415 SDValue Op = getNonRegisterValue(V);
7416 assert((Op.getOpcode() != ISD::CopyFromReg ||
7417 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7418 "Copy from a reg to the same reg!");
7419 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7422 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7423 SDValue Chain = DAG.getEntryNode();
7425 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7426 FuncInfo.PreferredExtendType.end())
7428 : FuncInfo.PreferredExtendType[V];
7429 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7430 PendingExports.push_back(Chain);
7433 #include "llvm/CodeGen/SelectionDAGISel.h"
7435 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7436 /// entry block, return true. This includes arguments used by switches, since
7437 /// the switch may expand into multiple basic blocks.
7438 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7439 // With FastISel active, we may be splitting blocks, so force creation
7440 // of virtual registers for all non-dead arguments.
7442 return A->use_empty();
7444 const BasicBlock *Entry = A->getParent()->begin();
7445 for (const User *U : A->users())
7446 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7447 return false; // Use not in entry block.
7452 void SelectionDAGISel::LowerArguments(const Function &F) {
7453 SelectionDAG &DAG = SDB->DAG;
7454 SDLoc dl = SDB->getCurSDLoc();
7455 const DataLayout *DL = TLI->getDataLayout();
7456 SmallVector<ISD::InputArg, 16> Ins;
7458 if (!FuncInfo->CanLowerReturn) {
7459 // Put in an sret pointer parameter before all the other parameters.
7460 SmallVector<EVT, 1> ValueVTs;
7461 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7463 // NOTE: Assuming that a pointer will never break down to more than one VT
7465 ISD::ArgFlagsTy Flags;
7467 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7468 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7469 ISD::InputArg::NoArgIndex, 0);
7470 Ins.push_back(RetArg);
7473 // Set up the incoming argument description vector.
7475 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7476 I != E; ++I, ++Idx) {
7477 SmallVector<EVT, 4> ValueVTs;
7478 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7479 bool isArgValueUsed = !I->use_empty();
7480 unsigned PartBase = 0;
7481 Type *FinalType = I->getType();
7482 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7483 FinalType = cast<PointerType>(FinalType)->getElementType();
7484 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7485 FinalType, F.getCallingConv(), F.isVarArg());
7486 for (unsigned Value = 0, NumValues = ValueVTs.size();
7487 Value != NumValues; ++Value) {
7488 EVT VT = ValueVTs[Value];
7489 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7490 ISD::ArgFlagsTy Flags;
7491 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7493 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7495 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7497 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7499 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7501 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7503 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7504 Flags.setInAlloca();
7505 // Set the byval flag for CCAssignFn callbacks that don't know about
7506 // inalloca. This way we can know how many bytes we should've allocated
7507 // and how many bytes a callee cleanup function will pop. If we port
7508 // inalloca to more targets, we'll have to add custom inalloca handling
7509 // in the various CC lowering callbacks.
7512 if (Flags.isByVal() || Flags.isInAlloca()) {
7513 PointerType *Ty = cast<PointerType>(I->getType());
7514 Type *ElementTy = Ty->getElementType();
7515 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7516 // For ByVal, alignment should be passed from FE. BE will guess if
7517 // this info is not there but there are cases it cannot get right.
7518 unsigned FrameAlign;
7519 if (F.getParamAlignment(Idx))
7520 FrameAlign = F.getParamAlignment(Idx);
7522 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7523 Flags.setByValAlign(FrameAlign);
7525 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7528 Flags.setInConsecutiveRegs();
7529 Flags.setOrigAlign(OriginalAlignment);
7531 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7532 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7533 for (unsigned i = 0; i != NumRegs; ++i) {
7534 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7535 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7536 if (NumRegs > 1 && i == 0)
7537 MyFlags.Flags.setSplit();
7538 // if it isn't first piece, alignment must be 1
7540 MyFlags.Flags.setOrigAlign(1);
7541 Ins.push_back(MyFlags);
7543 if (NeedsRegBlock && Value == NumValues - 1)
7544 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7545 PartBase += VT.getStoreSize();
7549 // Call the target to set up the argument values.
7550 SmallVector<SDValue, 8> InVals;
7551 SDValue NewRoot = TLI->LowerFormalArguments(
7552 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7554 // Verify that the target's LowerFormalArguments behaved as expected.
7555 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7556 "LowerFormalArguments didn't return a valid chain!");
7557 assert(InVals.size() == Ins.size() &&
7558 "LowerFormalArguments didn't emit the correct number of values!");
7560 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7561 assert(InVals[i].getNode() &&
7562 "LowerFormalArguments emitted a null value!");
7563 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7564 "LowerFormalArguments emitted a value with the wrong type!");
7568 // Update the DAG with the new chain value resulting from argument lowering.
7569 DAG.setRoot(NewRoot);
7571 // Set up the argument values.
7574 if (!FuncInfo->CanLowerReturn) {
7575 // Create a virtual register for the sret pointer, and put in a copy
7576 // from the sret argument into it.
7577 SmallVector<EVT, 1> ValueVTs;
7578 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7579 MVT VT = ValueVTs[0].getSimpleVT();
7580 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7581 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7582 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7583 RegVT, VT, nullptr, AssertOp);
7585 MachineFunction& MF = SDB->DAG.getMachineFunction();
7586 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7587 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7588 FuncInfo->DemoteRegister = SRetReg;
7590 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7591 DAG.setRoot(NewRoot);
7593 // i indexes lowered arguments. Bump it past the hidden sret argument.
7594 // Idx indexes LLVM arguments. Don't touch it.
7598 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7600 SmallVector<SDValue, 4> ArgValues;
7601 SmallVector<EVT, 4> ValueVTs;
7602 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7603 unsigned NumValues = ValueVTs.size();
7605 // If this argument is unused then remember its value. It is used to generate
7606 // debugging information.
7607 if (I->use_empty() && NumValues) {
7608 SDB->setUnusedArgValue(I, InVals[i]);
7610 // Also remember any frame index for use in FastISel.
7611 if (FrameIndexSDNode *FI =
7612 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7613 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7616 for (unsigned Val = 0; Val != NumValues; ++Val) {
7617 EVT VT = ValueVTs[Val];
7618 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7619 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7621 if (!I->use_empty()) {
7622 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7623 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7624 AssertOp = ISD::AssertSext;
7625 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7626 AssertOp = ISD::AssertZext;
7628 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7629 NumParts, PartVT, VT,
7630 nullptr, AssertOp));
7636 // We don't need to do anything else for unused arguments.
7637 if (ArgValues.empty())
7640 // Note down frame index.
7641 if (FrameIndexSDNode *FI =
7642 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7643 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7645 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7646 SDB->getCurSDLoc());
7648 SDB->setValue(I, Res);
7649 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7650 if (LoadSDNode *LNode =
7651 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7652 if (FrameIndexSDNode *FI =
7653 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7654 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7657 // If this argument is live outside of the entry block, insert a copy from
7658 // wherever we got it to the vreg that other BB's will reference it as.
7659 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7660 // If we can, though, try to skip creating an unnecessary vreg.
7661 // FIXME: This isn't very clean... it would be nice to make this more
7662 // general. It's also subtly incompatible with the hacks FastISel
7664 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7665 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7666 FuncInfo->ValueMap[I] = Reg;
7670 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7671 FuncInfo->InitializeRegForValue(I);
7672 SDB->CopyToExportRegsIfNeeded(I);
7676 assert(i == InVals.size() && "Argument register count mismatch!");
7678 // Finally, if the target has anything special to do, allow it to do so.
7679 EmitFunctionEntryCode();
7682 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7683 /// ensure constants are generated when needed. Remember the virtual registers
7684 /// that need to be added to the Machine PHI nodes as input. We cannot just
7685 /// directly add them, because expansion might result in multiple MBB's for one
7686 /// BB. As such, the start of the BB might correspond to a different MBB than
7690 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7691 const TerminatorInst *TI = LLVMBB->getTerminator();
7693 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7695 // Check PHI nodes in successors that expect a value to be available from this
7697 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7698 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7699 if (!isa<PHINode>(SuccBB->begin())) continue;
7700 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7702 // If this terminator has multiple identical successors (common for
7703 // switches), only handle each succ once.
7704 if (!SuccsHandled.insert(SuccMBB).second)
7707 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7709 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7710 // nodes and Machine PHI nodes, but the incoming operands have not been
7712 for (BasicBlock::const_iterator I = SuccBB->begin();
7713 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7714 // Ignore dead phi's.
7715 if (PN->use_empty()) continue;
7718 if (PN->getType()->isEmptyTy())
7722 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7724 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7725 unsigned &RegOut = ConstantsOut[C];
7727 RegOut = FuncInfo.CreateRegs(C->getType());
7728 CopyValueToVirtualRegister(C, RegOut);
7732 DenseMap<const Value *, unsigned>::iterator I =
7733 FuncInfo.ValueMap.find(PHIOp);
7734 if (I != FuncInfo.ValueMap.end())
7737 assert(isa<AllocaInst>(PHIOp) &&
7738 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7739 "Didn't codegen value into a register!??");
7740 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7741 CopyValueToVirtualRegister(PHIOp, Reg);
7745 // Remember that this register needs to added to the machine PHI node as
7746 // the input for this MBB.
7747 SmallVector<EVT, 4> ValueVTs;
7748 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7749 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7750 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7751 EVT VT = ValueVTs[vti];
7752 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7753 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7754 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7755 Reg += NumRegisters;
7760 ConstantsOut.clear();
7763 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7766 SelectionDAGBuilder::StackProtectorDescriptor::
7767 AddSuccessorMBB(const BasicBlock *BB,
7768 MachineBasicBlock *ParentMBB,
7770 MachineBasicBlock *SuccMBB) {
7771 // If SuccBB has not been created yet, create it.
7773 MachineFunction *MF = ParentMBB->getParent();
7774 MachineFunction::iterator BBI = ParentMBB;
7775 SuccMBB = MF->CreateMachineBasicBlock(BB);
7776 MF->insert(++BBI, SuccMBB);
7778 // Add it as a successor of ParentMBB.
7779 ParentMBB->addSuccessor(
7780 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7784 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7785 MachineFunction::iterator I = MBB;
7786 if (++I == FuncInfo.MF->end())