1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/ConstantFolding.h"
21 #include "llvm/Constants.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/DerivedTypes.h"
24 #include "llvm/Function.h"
25 #include "llvm/GlobalVariable.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/Instructions.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/IntrinsicInst.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/Module.h"
32 #include "llvm/CodeGen/Analysis.h"
33 #include "llvm/CodeGen/FastISel.h"
34 #include "llvm/CodeGen/FunctionLoweringInfo.h"
35 #include "llvm/CodeGen/GCStrategy.h"
36 #include "llvm/CodeGen/GCMetadata.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineJumpTableInfo.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/PseudoSourceValue.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetRegisterInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameInfo.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
74 const SDValue *Parts, unsigned NumParts,
75 EVT PartVT, EVT ValueVT);
77 /// getCopyFromParts - Create a value that contains the specified legal parts
78 /// combined into the value they represent. If the parts combine to a type
79 /// larger then ValueVT then AssertOp can be used to specify whether the extra
80 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
81 /// (ISD::AssertSext).
82 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
84 unsigned NumParts, EVT PartVT, EVT ValueVT,
85 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
86 if (ValueVT.isVector())
87 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
89 assert(NumParts > 0 && "No parts to assemble!");
90 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
91 SDValue Val = Parts[0];
94 // Assemble the value from multiple parts.
95 if (ValueVT.isInteger()) {
96 unsigned PartBits = PartVT.getSizeInBits();
97 unsigned ValueBits = ValueVT.getSizeInBits();
99 // Assemble the power of 2 part.
100 unsigned RoundParts = NumParts & (NumParts - 1) ?
101 1 << Log2_32(NumParts) : NumParts;
102 unsigned RoundBits = PartBits * RoundParts;
103 EVT RoundVT = RoundBits == ValueBits ?
104 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
107 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
109 if (RoundParts > 2) {
110 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
112 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
113 RoundParts / 2, PartVT, HalfVT);
115 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]);
116 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]);
119 if (TLI.isBigEndian())
122 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
124 if (RoundParts < NumParts) {
125 // Assemble the trailing non-power-of-2 part.
126 unsigned OddParts = NumParts - RoundParts;
127 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
128 Hi = getCopyFromParts(DAG, DL,
129 Parts + RoundParts, OddParts, PartVT, OddVT);
131 // Combine the round and odd parts.
133 if (TLI.isBigEndian())
135 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
136 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
137 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
138 DAG.getConstant(Lo.getValueType().getSizeInBits(),
139 TLI.getPointerTy()));
140 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
141 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
143 } else if (PartVT.isFloatingPoint()) {
144 // FP split into multiple FP parts (for ppcf128)
145 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
148 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]);
149 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]);
150 if (TLI.isBigEndian())
152 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
154 // FP split into integer parts (soft fp)
155 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
156 !PartVT.isVector() && "Unexpected split");
157 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
158 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
162 // There is now one part, held in Val. Correct it to match ValueVT.
163 PartVT = Val.getValueType();
165 if (PartVT == ValueVT)
168 if (PartVT.isInteger() && ValueVT.isInteger()) {
169 if (ValueVT.bitsLT(PartVT)) {
170 // For a truncate, see if we have any information to
171 // indicate whether the truncated bits will always be
172 // zero or sign-extension.
173 if (AssertOp != ISD::DELETED_NODE)
174 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
175 DAG.getValueType(ValueVT));
176 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
178 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
181 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
182 // FP_ROUND's are always exact here.
183 if (ValueVT.bitsLT(Val.getValueType()))
184 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
185 DAG.getIntPtrConstant(1));
187 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
190 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
191 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
193 llvm_unreachable("Unknown mismatch!");
197 /// getCopyFromParts - Create a value that contains the specified legal parts
198 /// combined into the value they represent. If the parts combine to a type
199 /// larger then ValueVT then AssertOp can be used to specify whether the extra
200 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
201 /// (ISD::AssertSext).
202 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
203 const SDValue *Parts, unsigned NumParts,
204 EVT PartVT, EVT ValueVT) {
205 assert(ValueVT.isVector() && "Not a vector value");
206 assert(NumParts > 0 && "No parts to assemble!");
207 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
208 SDValue Val = Parts[0];
210 // Handle a multi-element vector.
212 EVT IntermediateVT, RegisterVT;
213 unsigned NumIntermediates;
215 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
216 NumIntermediates, RegisterVT);
217 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
218 NumParts = NumRegs; // Silence a compiler warning.
219 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
220 assert(RegisterVT == Parts[0].getValueType() &&
221 "Part type doesn't match part!");
223 // Assemble the parts into intermediate operands.
224 SmallVector<SDValue, 8> Ops(NumIntermediates);
225 if (NumIntermediates == NumParts) {
226 // If the register was not expanded, truncate or copy the value,
228 for (unsigned i = 0; i != NumParts; ++i)
229 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
230 PartVT, IntermediateVT);
231 } else if (NumParts > 0) {
232 // If the intermediate type was expanded, build the intermediate
233 // operands from the parts.
234 assert(NumParts % NumIntermediates == 0 &&
235 "Must expand into a divisible number of parts!");
236 unsigned Factor = NumParts / NumIntermediates;
237 for (unsigned i = 0; i != NumIntermediates; ++i)
238 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
239 PartVT, IntermediateVT);
242 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
243 // intermediate operands.
244 Val = DAG.getNode(IntermediateVT.isVector() ?
245 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
246 ValueVT, &Ops[0], NumIntermediates);
249 // There is now one part, held in Val. Correct it to match ValueVT.
250 PartVT = Val.getValueType();
252 if (PartVT == ValueVT)
255 if (PartVT.isVector()) {
256 // If the element type of the source/dest vectors are the same, but the
257 // parts vector has more elements than the value vector, then we have a
258 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
260 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
261 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
262 "Cannot narrow, it would be a lossy transformation");
263 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
264 DAG.getIntPtrConstant(0));
267 // Vector/Vector bitcast.
268 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
271 assert(ValueVT.getVectorElementType() == PartVT &&
272 ValueVT.getVectorNumElements() == 1 &&
273 "Only trivial scalar-to-vector conversions should get here!");
274 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
280 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
281 SDValue Val, SDValue *Parts, unsigned NumParts,
284 /// getCopyToParts - Create a series of nodes that contain the specified value
285 /// split into legal parts. If the parts contain more bits than Val, then, for
286 /// integers, ExtendKind can be used to specify how to generate the extra bits.
287 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
288 SDValue Val, SDValue *Parts, unsigned NumParts,
290 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
291 EVT ValueVT = Val.getValueType();
293 // Handle the vector case separately.
294 if (ValueVT.isVector())
295 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
298 unsigned PartBits = PartVT.getSizeInBits();
299 unsigned OrigNumParts = NumParts;
300 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
305 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
306 if (PartVT == ValueVT) {
307 assert(NumParts == 1 && "No-op copy with multiple parts!");
312 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
313 // If the parts cover more bits than the value has, promote the value.
314 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
315 assert(NumParts == 1 && "Do not know what to promote to!");
316 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
318 assert(PartVT.isInteger() && ValueVT.isInteger() &&
319 "Unknown mismatch!");
320 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
321 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
323 } else if (PartBits == ValueVT.getSizeInBits()) {
324 // Different types of the same size.
325 assert(NumParts == 1 && PartVT != ValueVT);
326 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
327 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
328 // If the parts cover less bits than value has, truncate the value.
329 assert(PartVT.isInteger() && ValueVT.isInteger() &&
330 "Unknown mismatch!");
331 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
332 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
335 // The value may have changed - recompute ValueVT.
336 ValueVT = Val.getValueType();
337 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
338 "Failed to tile the value with PartVT!");
341 assert(PartVT == ValueVT && "Type conversion failed!");
346 // Expand the value into multiple parts.
347 if (NumParts & (NumParts - 1)) {
348 // The number of parts is not a power of 2. Split off and copy the tail.
349 assert(PartVT.isInteger() && ValueVT.isInteger() &&
350 "Do not know what to expand to!");
351 unsigned RoundParts = 1 << Log2_32(NumParts);
352 unsigned RoundBits = RoundParts * PartBits;
353 unsigned OddParts = NumParts - RoundParts;
354 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
355 DAG.getIntPtrConstant(RoundBits));
356 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
358 if (TLI.isBigEndian())
359 // The odd parts were reversed by getCopyToParts - unreverse them.
360 std::reverse(Parts + RoundParts, Parts + NumParts);
362 NumParts = RoundParts;
363 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
364 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
367 // The number of parts is a power of 2. Repeatedly bisect the value using
369 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL,
370 EVT::getIntegerVT(*DAG.getContext(),
371 ValueVT.getSizeInBits()),
374 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
375 for (unsigned i = 0; i < NumParts; i += StepSize) {
376 unsigned ThisBits = StepSize * PartBits / 2;
377 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
378 SDValue &Part0 = Parts[i];
379 SDValue &Part1 = Parts[i+StepSize/2];
381 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
382 ThisVT, Part0, DAG.getIntPtrConstant(1));
383 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
384 ThisVT, Part0, DAG.getIntPtrConstant(0));
386 if (ThisBits == PartBits && ThisVT != PartVT) {
387 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0);
388 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1);
393 if (TLI.isBigEndian())
394 std::reverse(Parts, Parts + OrigNumParts);
398 /// getCopyToPartsVector - Create a series of nodes that contain the specified
399 /// value split into legal parts.
400 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
401 SDValue Val, SDValue *Parts, unsigned NumParts,
403 EVT ValueVT = Val.getValueType();
404 assert(ValueVT.isVector() && "Not a vector");
405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
408 if (PartVT == ValueVT) {
410 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
411 // Bitconvert vector->vector case.
412 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
413 } else if (PartVT.isVector() &&
414 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
415 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
416 EVT ElementVT = PartVT.getVectorElementType();
417 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
419 SmallVector<SDValue, 16> Ops;
420 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
421 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
422 ElementVT, Val, DAG.getIntPtrConstant(i)));
424 for (unsigned i = ValueVT.getVectorNumElements(),
425 e = PartVT.getVectorNumElements(); i != e; ++i)
426 Ops.push_back(DAG.getUNDEF(ElementVT));
428 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
430 // FIXME: Use CONCAT for 2x -> 4x.
432 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
433 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
435 // Vector -> scalar conversion.
436 assert(ValueVT.getVectorElementType() == PartVT &&
437 ValueVT.getVectorNumElements() == 1 &&
438 "Only trivial vector-to-scalar conversions should get here!");
439 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
440 PartVT, Val, DAG.getIntPtrConstant(0));
447 // Handle a multi-element vector.
448 EVT IntermediateVT, RegisterVT;
449 unsigned NumIntermediates;
450 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
451 IntermediateVT, NumIntermediates, RegisterVT);
452 unsigned NumElements = ValueVT.getVectorNumElements();
454 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
455 NumParts = NumRegs; // Silence a compiler warning.
456 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
458 // Split the vector into intermediate operands.
459 SmallVector<SDValue, 8> Ops(NumIntermediates);
460 for (unsigned i = 0; i != NumIntermediates; ++i) {
461 if (IntermediateVT.isVector())
462 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
464 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
466 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
467 IntermediateVT, Val, DAG.getIntPtrConstant(i));
470 // Split the intermediate operands into legal parts.
471 if (NumParts == NumIntermediates) {
472 // If the register was not expanded, promote or copy the value,
474 for (unsigned i = 0; i != NumParts; ++i)
475 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
476 } else if (NumParts > 0) {
477 // If the intermediate type was expanded, split each the value into
479 assert(NumParts % NumIntermediates == 0 &&
480 "Must expand into a divisible number of parts!");
481 unsigned Factor = NumParts / NumIntermediates;
482 for (unsigned i = 0; i != NumIntermediates; ++i)
483 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
491 /// RegsForValue - This struct represents the registers (physical or virtual)
492 /// that a particular set of values is assigned, and the type information
493 /// about the value. The most common situation is to represent one value at a
494 /// time, but struct or array values are handled element-wise as multiple
495 /// values. The splitting of aggregates is performed recursively, so that we
496 /// never have aggregate-typed registers. The values at this point do not
497 /// necessarily have legal types, so each value may require one or more
498 /// registers of some legal type.
500 struct RegsForValue {
501 /// ValueVTs - The value types of the values, which may not be legal, and
502 /// may need be promoted or synthesized from one or more registers.
504 SmallVector<EVT, 4> ValueVTs;
506 /// RegVTs - The value types of the registers. This is the same size as
507 /// ValueVTs and it records, for each value, what the type of the assigned
508 /// register or registers are. (Individual values are never synthesized
509 /// from more than one type of register.)
511 /// With virtual registers, the contents of RegVTs is redundant with TLI's
512 /// getRegisterType member function, however when with physical registers
513 /// it is necessary to have a separate record of the types.
515 SmallVector<EVT, 4> RegVTs;
517 /// Regs - This list holds the registers assigned to the values.
518 /// Each legal or promoted value requires one register, and each
519 /// expanded value requires multiple registers.
521 SmallVector<unsigned, 4> Regs;
525 RegsForValue(const SmallVector<unsigned, 4> ®s,
526 EVT regvt, EVT valuevt)
527 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
529 RegsForValue(const SmallVector<unsigned, 4> ®s,
530 const SmallVector<EVT, 4> ®vts,
531 const SmallVector<EVT, 4> &valuevts)
532 : ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
534 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
535 unsigned Reg, const Type *Ty) {
536 ComputeValueVTs(tli, Ty, ValueVTs);
538 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
539 EVT ValueVT = ValueVTs[Value];
540 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
541 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
542 for (unsigned i = 0; i != NumRegs; ++i)
543 Regs.push_back(Reg + i);
544 RegVTs.push_back(RegisterVT);
549 /// areValueTypesLegal - Return true if types of all the values are legal.
550 bool areValueTypesLegal(const TargetLowering &TLI) {
551 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
552 EVT RegisterVT = RegVTs[Value];
553 if (!TLI.isTypeLegal(RegisterVT))
559 /// append - Add the specified values to this one.
560 void append(const RegsForValue &RHS) {
561 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
562 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
563 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
566 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
567 /// this value and returns the result as a ValueVTs value. This uses
568 /// Chain/Flag as the input and updates them for the output Chain/Flag.
569 /// If the Flag pointer is NULL, no flag is used.
570 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
572 SDValue &Chain, SDValue *Flag) const;
574 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
575 /// specified value into the registers specified by this object. This uses
576 /// Chain/Flag as the input and updates them for the output Chain/Flag.
577 /// If the Flag pointer is NULL, no flag is used.
578 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
579 SDValue &Chain, SDValue *Flag) const;
581 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
582 /// operand list. This adds the code marker, matching input operand index
583 /// (if applicable), and includes the number of values added into it.
584 void AddInlineAsmOperands(unsigned Kind,
585 bool HasMatching, unsigned MatchingIdx,
587 std::vector<SDValue> &Ops) const;
591 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
592 /// this value and returns the result as a ValueVT value. This uses
593 /// Chain/Flag as the input and updates them for the output Chain/Flag.
594 /// If the Flag pointer is NULL, no flag is used.
595 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
596 FunctionLoweringInfo &FuncInfo,
598 SDValue &Chain, SDValue *Flag) const {
599 // A Value with type {} or [0 x %t] needs no registers.
600 if (ValueVTs.empty())
603 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
605 // Assemble the legal parts into the final values.
606 SmallVector<SDValue, 4> Values(ValueVTs.size());
607 SmallVector<SDValue, 8> Parts;
608 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
609 // Copy the legal parts from the registers.
610 EVT ValueVT = ValueVTs[Value];
611 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
612 EVT RegisterVT = RegVTs[Value];
614 Parts.resize(NumRegs);
615 for (unsigned i = 0; i != NumRegs; ++i) {
618 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
620 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
621 *Flag = P.getValue(2);
624 Chain = P.getValue(1);
626 // If the source register was virtual and if we know something about it,
627 // add an assert node.
628 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
629 RegisterVT.isInteger() && !RegisterVT.isVector()) {
630 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
631 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) {
632 const FunctionLoweringInfo::LiveOutInfo &LOI =
633 FuncInfo.LiveOutRegInfo[SlotNo];
635 unsigned RegSize = RegisterVT.getSizeInBits();
636 unsigned NumSignBits = LOI.NumSignBits;
637 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
639 // FIXME: We capture more information than the dag can represent. For
640 // now, just use the tightest assertzext/assertsext possible.
642 EVT FromVT(MVT::Other);
643 if (NumSignBits == RegSize)
644 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
645 else if (NumZeroBits >= RegSize-1)
646 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
647 else if (NumSignBits > RegSize-8)
648 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
649 else if (NumZeroBits >= RegSize-8)
650 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
651 else if (NumSignBits > RegSize-16)
652 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
653 else if (NumZeroBits >= RegSize-16)
654 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
655 else if (NumSignBits > RegSize-32)
656 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
657 else if (NumZeroBits >= RegSize-32)
658 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
660 if (FromVT != MVT::Other)
661 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
662 RegisterVT, P, DAG.getValueType(FromVT));
669 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
670 NumRegs, RegisterVT, ValueVT);
675 return DAG.getNode(ISD::MERGE_VALUES, dl,
676 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
677 &Values[0], ValueVTs.size());
680 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
681 /// specified value into the registers specified by this object. This uses
682 /// Chain/Flag as the input and updates them for the output Chain/Flag.
683 /// If the Flag pointer is NULL, no flag is used.
684 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
685 SDValue &Chain, SDValue *Flag) const {
686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
688 // Get the list of the values's legal parts.
689 unsigned NumRegs = Regs.size();
690 SmallVector<SDValue, 8> Parts(NumRegs);
691 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
692 EVT ValueVT = ValueVTs[Value];
693 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
694 EVT RegisterVT = RegVTs[Value];
696 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
697 &Parts[Part], NumParts, RegisterVT);
701 // Copy the parts into the registers.
702 SmallVector<SDValue, 8> Chains(NumRegs);
703 for (unsigned i = 0; i != NumRegs; ++i) {
706 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
708 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
709 *Flag = Part.getValue(1);
712 Chains[i] = Part.getValue(0);
715 if (NumRegs == 1 || Flag)
716 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
717 // flagged to it. That is the CopyToReg nodes and the user are considered
718 // a single scheduling unit. If we create a TokenFactor and return it as
719 // chain, then the TokenFactor is both a predecessor (operand) of the
720 // user as well as a successor (the TF operands are flagged to the user).
721 // c1, f1 = CopyToReg
722 // c2, f2 = CopyToReg
723 // c3 = TokenFactor c1, c2
726 Chain = Chains[NumRegs-1];
728 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
731 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
732 /// operand list. This adds the code marker and includes the number of
733 /// values added into it.
734 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
735 unsigned MatchingIdx,
737 std::vector<SDValue> &Ops) const {
738 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
740 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
742 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
743 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
746 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
747 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
748 EVT RegisterVT = RegVTs[Value];
749 for (unsigned i = 0; i != NumRegs; ++i) {
750 assert(Reg < Regs.size() && "Mismatch in # registers expected");
751 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
756 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
759 TD = DAG.getTarget().getTargetData();
762 /// clear - Clear out the current SelectionDAG and the associated
763 /// state and prepare this SelectionDAGBuilder object to be used
764 /// for a new block. This doesn't clear out information about
765 /// additional blocks that are needed to complete switch lowering
766 /// or PHI node updating; that information is cleared out as it is
768 void SelectionDAGBuilder::clear() {
770 UnusedArgNodeMap.clear();
771 PendingLoads.clear();
772 PendingExports.clear();
773 DanglingDebugInfoMap.clear();
774 CurDebugLoc = DebugLoc();
778 /// getRoot - Return the current virtual root of the Selection DAG,
779 /// flushing any PendingLoad items. This must be done before emitting
780 /// a store or any other node that may need to be ordered after any
781 /// prior load instructions.
783 SDValue SelectionDAGBuilder::getRoot() {
784 if (PendingLoads.empty())
785 return DAG.getRoot();
787 if (PendingLoads.size() == 1) {
788 SDValue Root = PendingLoads[0];
790 PendingLoads.clear();
794 // Otherwise, we have to make a token factor node.
795 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
796 &PendingLoads[0], PendingLoads.size());
797 PendingLoads.clear();
802 /// getControlRoot - Similar to getRoot, but instead of flushing all the
803 /// PendingLoad items, flush all the PendingExports items. It is necessary
804 /// to do this before emitting a terminator instruction.
806 SDValue SelectionDAGBuilder::getControlRoot() {
807 SDValue Root = DAG.getRoot();
809 if (PendingExports.empty())
812 // Turn all of the CopyToReg chains into one factored node.
813 if (Root.getOpcode() != ISD::EntryToken) {
814 unsigned i = 0, e = PendingExports.size();
815 for (; i != e; ++i) {
816 assert(PendingExports[i].getNode()->getNumOperands() > 1);
817 if (PendingExports[i].getNode()->getOperand(0) == Root)
818 break; // Don't add the root if we already indirectly depend on it.
822 PendingExports.push_back(Root);
825 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
827 PendingExports.size());
828 PendingExports.clear();
833 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
834 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
835 DAG.AssignOrdering(Node, SDNodeOrder);
837 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
838 AssignOrderingToNode(Node->getOperand(I).getNode());
841 void SelectionDAGBuilder::visit(const Instruction &I) {
842 // Set up outgoing PHI node register values before emitting the terminator.
843 if (isa<TerminatorInst>(&I))
844 HandlePHINodesInSuccessorBlocks(I.getParent());
846 CurDebugLoc = I.getDebugLoc();
848 visit(I.getOpcode(), I);
850 if (!isa<TerminatorInst>(&I) && !HasTailCall)
851 CopyToExportRegsIfNeeded(&I);
853 CurDebugLoc = DebugLoc();
856 void SelectionDAGBuilder::visitPHI(const PHINode &) {
857 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
860 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
861 // Note: this doesn't use InstVisitor, because it has to work with
862 // ConstantExpr's in addition to instructions.
864 default: llvm_unreachable("Unknown instruction type encountered!");
865 // Build the switch statement using the Instruction.def file.
866 #define HANDLE_INST(NUM, OPCODE, CLASS) \
867 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
868 #include "llvm/Instruction.def"
871 // Assign the ordering to the freshly created DAG nodes.
872 if (NodeMap.count(&I)) {
874 AssignOrderingToNode(getValue(&I).getNode());
878 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
879 // generate the debug data structures now that we've seen its definition.
880 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
882 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
884 const DbgValueInst *DI = DDI.getDI();
885 DebugLoc dl = DDI.getdl();
886 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
887 MDNode *Variable = DI->getVariable();
888 uint64_t Offset = DI->getOffset();
891 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
892 SDV = DAG.getDbgValue(Variable, Val.getNode(),
893 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
894 DAG.AddDbgValue(SDV, Val.getNode(), false);
897 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
898 Offset, dl, SDNodeOrder);
899 DAG.AddDbgValue(SDV, 0, false);
901 DanglingDebugInfoMap[V] = DanglingDebugInfo();
905 // getValue - Return an SDValue for the given Value.
906 SDValue SelectionDAGBuilder::getValue(const Value *V) {
907 // If we already have an SDValue for this value, use it. It's important
908 // to do this first, so that we don't create a CopyFromReg if we already
909 // have a regular SDValue.
910 SDValue &N = NodeMap[V];
911 if (N.getNode()) return N;
913 // If there's a virtual register allocated and initialized for this
915 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
916 if (It != FuncInfo.ValueMap.end()) {
917 unsigned InReg = It->second;
918 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
919 SDValue Chain = DAG.getEntryNode();
920 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
923 // Otherwise create a new SDValue and remember it.
924 SDValue Val = getValueImpl(V);
926 resolveDanglingDebugInfo(V, Val);
930 /// getNonRegisterValue - Return an SDValue for the given Value, but
931 /// don't look in FuncInfo.ValueMap for a virtual register.
932 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
933 // If we already have an SDValue for this value, use it.
934 SDValue &N = NodeMap[V];
935 if (N.getNode()) return N;
937 // Otherwise create a new SDValue and remember it.
938 SDValue Val = getValueImpl(V);
940 resolveDanglingDebugInfo(V, Val);
944 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
945 /// Create an SDValue for the given value.
946 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
947 if (const Constant *C = dyn_cast<Constant>(V)) {
948 EVT VT = TLI.getValueType(V->getType(), true);
950 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
951 return DAG.getConstant(*CI, VT);
953 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
954 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
956 if (isa<ConstantPointerNull>(C))
957 return DAG.getConstant(0, TLI.getPointerTy());
959 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
960 return DAG.getConstantFP(*CFP, VT);
962 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
963 return DAG.getUNDEF(VT);
965 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
966 visit(CE->getOpcode(), *CE);
967 SDValue N1 = NodeMap[V];
968 assert(N1.getNode() && "visit didn't populate the NodeMap!");
972 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
973 SmallVector<SDValue, 4> Constants;
974 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
976 SDNode *Val = getValue(*OI).getNode();
977 // If the operand is an empty aggregate, there are no values.
979 // Add each leaf value from the operand to the Constants list
980 // to form a flattened list of all the values.
981 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
982 Constants.push_back(SDValue(Val, i));
985 return DAG.getMergeValues(&Constants[0], Constants.size(),
989 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
990 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
991 "Unknown struct or array constant!");
993 SmallVector<EVT, 4> ValueVTs;
994 ComputeValueVTs(TLI, C->getType(), ValueVTs);
995 unsigned NumElts = ValueVTs.size();
997 return SDValue(); // empty struct
998 SmallVector<SDValue, 4> Constants(NumElts);
999 for (unsigned i = 0; i != NumElts; ++i) {
1000 EVT EltVT = ValueVTs[i];
1001 if (isa<UndefValue>(C))
1002 Constants[i] = DAG.getUNDEF(EltVT);
1003 else if (EltVT.isFloatingPoint())
1004 Constants[i] = DAG.getConstantFP(0, EltVT);
1006 Constants[i] = DAG.getConstant(0, EltVT);
1009 return DAG.getMergeValues(&Constants[0], NumElts,
1013 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1014 return DAG.getBlockAddress(BA, VT);
1016 const VectorType *VecTy = cast<VectorType>(V->getType());
1017 unsigned NumElements = VecTy->getNumElements();
1019 // Now that we know the number and type of the elements, get that number of
1020 // elements into the Ops array based on what kind of constant it is.
1021 SmallVector<SDValue, 16> Ops;
1022 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1023 for (unsigned i = 0; i != NumElements; ++i)
1024 Ops.push_back(getValue(CP->getOperand(i)));
1026 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1027 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1030 if (EltVT.isFloatingPoint())
1031 Op = DAG.getConstantFP(0, EltVT);
1033 Op = DAG.getConstant(0, EltVT);
1034 Ops.assign(NumElements, Op);
1037 // Create a BUILD_VECTOR node.
1038 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1039 VT, &Ops[0], Ops.size());
1042 // If this is a static alloca, generate it as the frameindex instead of
1044 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1045 DenseMap<const AllocaInst*, int>::iterator SI =
1046 FuncInfo.StaticAllocaMap.find(AI);
1047 if (SI != FuncInfo.StaticAllocaMap.end())
1048 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1051 // If this is an instruction which fast-isel has deferred, select it now.
1052 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1053 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1054 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1055 SDValue Chain = DAG.getEntryNode();
1056 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1059 llvm_unreachable("Can't get register for value!");
1063 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1064 SDValue Chain = getControlRoot();
1065 SmallVector<ISD::OutputArg, 8> Outs;
1066 SmallVector<SDValue, 8> OutVals;
1068 if (!FuncInfo.CanLowerReturn) {
1069 unsigned DemoteReg = FuncInfo.DemoteRegister;
1070 const Function *F = I.getParent()->getParent();
1072 // Emit a store of the return value through the virtual register.
1073 // Leave Outs empty so that LowerReturn won't try to load return
1074 // registers the usual way.
1075 SmallVector<EVT, 1> PtrValueVTs;
1076 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1079 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1080 SDValue RetOp = getValue(I.getOperand(0));
1082 SmallVector<EVT, 4> ValueVTs;
1083 SmallVector<uint64_t, 4> Offsets;
1084 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1085 unsigned NumValues = ValueVTs.size();
1087 SmallVector<SDValue, 4> Chains(NumValues);
1088 for (unsigned i = 0; i != NumValues; ++i) {
1089 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1090 RetPtr.getValueType(), RetPtr,
1091 DAG.getIntPtrConstant(Offsets[i]));
1093 DAG.getStore(Chain, getCurDebugLoc(),
1094 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1095 Add, NULL, Offsets[i], false, false, 0);
1098 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1099 MVT::Other, &Chains[0], NumValues);
1100 } else if (I.getNumOperands() != 0) {
1101 SmallVector<EVT, 4> ValueVTs;
1102 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1103 unsigned NumValues = ValueVTs.size();
1105 SDValue RetOp = getValue(I.getOperand(0));
1106 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1107 EVT VT = ValueVTs[j];
1109 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1111 const Function *F = I.getParent()->getParent();
1112 if (F->paramHasAttr(0, Attribute::SExt))
1113 ExtendKind = ISD::SIGN_EXTEND;
1114 else if (F->paramHasAttr(0, Attribute::ZExt))
1115 ExtendKind = ISD::ZERO_EXTEND;
1117 // FIXME: C calling convention requires the return type to be promoted
1118 // to at least 32-bit. But this is not necessary for non-C calling
1119 // conventions. The frontend should mark functions whose return values
1120 // require promoting with signext or zeroext attributes.
1121 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1122 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1123 if (VT.bitsLT(MinVT))
1127 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1128 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1129 SmallVector<SDValue, 4> Parts(NumParts);
1130 getCopyToParts(DAG, getCurDebugLoc(),
1131 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1132 &Parts[0], NumParts, PartVT, ExtendKind);
1134 // 'inreg' on function refers to return value
1135 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1136 if (F->paramHasAttr(0, Attribute::InReg))
1139 // Propagate extension type if any
1140 if (F->paramHasAttr(0, Attribute::SExt))
1142 else if (F->paramHasAttr(0, Attribute::ZExt))
1145 for (unsigned i = 0; i < NumParts; ++i) {
1146 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1148 OutVals.push_back(Parts[i]);
1154 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1155 CallingConv::ID CallConv =
1156 DAG.getMachineFunction().getFunction()->getCallingConv();
1157 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1158 Outs, OutVals, getCurDebugLoc(), DAG);
1160 // Verify that the target's LowerReturn behaved as expected.
1161 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1162 "LowerReturn didn't return a valid chain!");
1164 // Update the DAG with the new chain value resulting from return lowering.
1168 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1169 /// created for it, emit nodes to copy the value into the virtual
1171 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1172 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1173 if (VMI != FuncInfo.ValueMap.end()) {
1174 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1175 CopyValueToVirtualRegister(V, VMI->second);
1179 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1180 /// the current basic block, add it to ValueMap now so that we'll get a
1182 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1183 // No need to export constants.
1184 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1186 // Already exported?
1187 if (FuncInfo.isExportedInst(V)) return;
1189 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1190 CopyValueToVirtualRegister(V, Reg);
1193 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1194 const BasicBlock *FromBB) {
1195 // The operands of the setcc have to be in this block. We don't know
1196 // how to export them from some other block.
1197 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1198 // Can export from current BB.
1199 if (VI->getParent() == FromBB)
1202 // Is already exported, noop.
1203 return FuncInfo.isExportedInst(V);
1206 // If this is an argument, we can export it if the BB is the entry block or
1207 // if it is already exported.
1208 if (isa<Argument>(V)) {
1209 if (FromBB == &FromBB->getParent()->getEntryBlock())
1212 // Otherwise, can only export this if it is already exported.
1213 return FuncInfo.isExportedInst(V);
1216 // Otherwise, constants can always be exported.
1220 static bool InBlock(const Value *V, const BasicBlock *BB) {
1221 if (const Instruction *I = dyn_cast<Instruction>(V))
1222 return I->getParent() == BB;
1226 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1227 /// This function emits a branch and is used at the leaves of an OR or an
1228 /// AND operator tree.
1231 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1232 MachineBasicBlock *TBB,
1233 MachineBasicBlock *FBB,
1234 MachineBasicBlock *CurBB,
1235 MachineBasicBlock *SwitchBB) {
1236 const BasicBlock *BB = CurBB->getBasicBlock();
1238 // If the leaf of the tree is a comparison, merge the condition into
1240 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1241 // The operands of the cmp have to be in this block. We don't know
1242 // how to export them from some other block. If this is the first block
1243 // of the sequence, no exporting is needed.
1244 if (CurBB == SwitchBB ||
1245 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1246 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1247 ISD::CondCode Condition;
1248 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1249 Condition = getICmpCondCode(IC->getPredicate());
1250 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1251 Condition = getFCmpCondCode(FC->getPredicate());
1253 Condition = ISD::SETEQ; // silence warning.
1254 llvm_unreachable("Unknown compare instruction");
1257 CaseBlock CB(Condition, BOp->getOperand(0),
1258 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1259 SwitchCases.push_back(CB);
1264 // Create a CaseBlock record representing this branch.
1265 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1266 NULL, TBB, FBB, CurBB);
1267 SwitchCases.push_back(CB);
1270 /// FindMergedConditions - If Cond is an expression like
1271 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1272 MachineBasicBlock *TBB,
1273 MachineBasicBlock *FBB,
1274 MachineBasicBlock *CurBB,
1275 MachineBasicBlock *SwitchBB,
1277 // If this node is not part of the or/and tree, emit it as a branch.
1278 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1279 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1280 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1281 BOp->getParent() != CurBB->getBasicBlock() ||
1282 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1283 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1284 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1288 // Create TmpBB after CurBB.
1289 MachineFunction::iterator BBI = CurBB;
1290 MachineFunction &MF = DAG.getMachineFunction();
1291 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1292 CurBB->getParent()->insert(++BBI, TmpBB);
1294 if (Opc == Instruction::Or) {
1295 // Codegen X | Y as:
1303 // Emit the LHS condition.
1304 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1306 // Emit the RHS condition into TmpBB.
1307 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1309 assert(Opc == Instruction::And && "Unknown merge op!");
1310 // Codegen X & Y as:
1317 // This requires creation of TmpBB after CurBB.
1319 // Emit the LHS condition.
1320 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1322 // Emit the RHS condition into TmpBB.
1323 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1327 /// If the set of cases should be emitted as a series of branches, return true.
1328 /// If we should emit this as a bunch of and/or'd together conditions, return
1331 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1332 if (Cases.size() != 2) return true;
1334 // If this is two comparisons of the same values or'd or and'd together, they
1335 // will get folded into a single comparison, so don't emit two blocks.
1336 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1337 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1338 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1339 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1343 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1344 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1345 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1346 Cases[0].CC == Cases[1].CC &&
1347 isa<Constant>(Cases[0].CmpRHS) &&
1348 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1349 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1351 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1358 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1359 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1361 // Update machine-CFG edges.
1362 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1364 // Figure out which block is immediately after the current one.
1365 MachineBasicBlock *NextBlock = 0;
1366 MachineFunction::iterator BBI = BrMBB;
1367 if (++BBI != FuncInfo.MF->end())
1370 if (I.isUnconditional()) {
1371 // Update machine-CFG edges.
1372 BrMBB->addSuccessor(Succ0MBB);
1374 // If this is not a fall-through branch, emit the branch.
1375 if (Succ0MBB != NextBlock)
1376 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1377 MVT::Other, getControlRoot(),
1378 DAG.getBasicBlock(Succ0MBB)));
1383 // If this condition is one of the special cases we handle, do special stuff
1385 const Value *CondVal = I.getCondition();
1386 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1388 // If this is a series of conditions that are or'd or and'd together, emit
1389 // this as a sequence of branches instead of setcc's with and/or operations.
1390 // For example, instead of something like:
1403 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1404 if (BOp->hasOneUse() &&
1405 (BOp->getOpcode() == Instruction::And ||
1406 BOp->getOpcode() == Instruction::Or)) {
1407 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1409 // If the compares in later blocks need to use values not currently
1410 // exported from this block, export them now. This block should always
1411 // be the first entry.
1412 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1414 // Allow some cases to be rejected.
1415 if (ShouldEmitAsBranches(SwitchCases)) {
1416 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1417 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1418 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1421 // Emit the branch for this block.
1422 visitSwitchCase(SwitchCases[0], BrMBB);
1423 SwitchCases.erase(SwitchCases.begin());
1427 // Okay, we decided not to do this, remove any inserted MBB's and clear
1429 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1430 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1432 SwitchCases.clear();
1436 // Create a CaseBlock record representing this branch.
1437 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1438 NULL, Succ0MBB, Succ1MBB, BrMBB);
1440 // Use visitSwitchCase to actually insert the fast branch sequence for this
1442 visitSwitchCase(CB, BrMBB);
1445 /// visitSwitchCase - Emits the necessary code to represent a single node in
1446 /// the binary search tree resulting from lowering a switch instruction.
1447 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1448 MachineBasicBlock *SwitchBB) {
1450 SDValue CondLHS = getValue(CB.CmpLHS);
1451 DebugLoc dl = getCurDebugLoc();
1453 // Build the setcc now.
1454 if (CB.CmpMHS == NULL) {
1455 // Fold "(X == true)" to X and "(X == false)" to !X to
1456 // handle common cases produced by branch lowering.
1457 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1458 CB.CC == ISD::SETEQ)
1460 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1461 CB.CC == ISD::SETEQ) {
1462 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1463 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1465 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1467 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1469 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1470 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1472 SDValue CmpOp = getValue(CB.CmpMHS);
1473 EVT VT = CmpOp.getValueType();
1475 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1476 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1479 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1480 VT, CmpOp, DAG.getConstant(Low, VT));
1481 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1482 DAG.getConstant(High-Low, VT), ISD::SETULE);
1486 // Update successor info
1487 SwitchBB->addSuccessor(CB.TrueBB);
1488 SwitchBB->addSuccessor(CB.FalseBB);
1490 // Set NextBlock to be the MBB immediately after the current one, if any.
1491 // This is used to avoid emitting unnecessary branches to the next block.
1492 MachineBasicBlock *NextBlock = 0;
1493 MachineFunction::iterator BBI = SwitchBB;
1494 if (++BBI != FuncInfo.MF->end())
1497 // If the lhs block is the next block, invert the condition so that we can
1498 // fall through to the lhs instead of the rhs block.
1499 if (CB.TrueBB == NextBlock) {
1500 std::swap(CB.TrueBB, CB.FalseBB);
1501 SDValue True = DAG.getConstant(1, Cond.getValueType());
1502 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1505 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1506 MVT::Other, getControlRoot(), Cond,
1507 DAG.getBasicBlock(CB.TrueBB));
1509 // Insert the false branch.
1510 if (CB.FalseBB != NextBlock)
1511 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1512 DAG.getBasicBlock(CB.FalseBB));
1514 DAG.setRoot(BrCond);
1517 /// visitJumpTable - Emit JumpTable node in the current MBB
1518 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1519 // Emit the code for the jump table
1520 assert(JT.Reg != -1U && "Should lower JT Header first!");
1521 EVT PTy = TLI.getPointerTy();
1522 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1524 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1525 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1526 MVT::Other, Index.getValue(1),
1528 DAG.setRoot(BrJumpTable);
1531 /// visitJumpTableHeader - This function emits necessary code to produce index
1532 /// in the JumpTable from switch case.
1533 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1534 JumpTableHeader &JTH,
1535 MachineBasicBlock *SwitchBB) {
1536 // Subtract the lowest switch case value from the value being switched on and
1537 // conditional branch to default mbb if the result is greater than the
1538 // difference between smallest and largest cases.
1539 SDValue SwitchOp = getValue(JTH.SValue);
1540 EVT VT = SwitchOp.getValueType();
1541 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1542 DAG.getConstant(JTH.First, VT));
1544 // The SDNode we just created, which holds the value being switched on minus
1545 // the smallest case value, needs to be copied to a virtual register so it
1546 // can be used as an index into the jump table in a subsequent basic block.
1547 // This value may be smaller or larger than the target's pointer type, and
1548 // therefore require extension or truncating.
1549 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1551 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1552 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1553 JumpTableReg, SwitchOp);
1554 JT.Reg = JumpTableReg;
1556 // Emit the range check for the jump table, and branch to the default block
1557 // for the switch statement if the value being switched on exceeds the largest
1558 // case in the switch.
1559 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1560 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1561 DAG.getConstant(JTH.Last-JTH.First,VT),
1564 // Set NextBlock to be the MBB immediately after the current one, if any.
1565 // This is used to avoid emitting unnecessary branches to the next block.
1566 MachineBasicBlock *NextBlock = 0;
1567 MachineFunction::iterator BBI = SwitchBB;
1569 if (++BBI != FuncInfo.MF->end())
1572 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1573 MVT::Other, CopyTo, CMP,
1574 DAG.getBasicBlock(JT.Default));
1576 if (JT.MBB != NextBlock)
1577 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1578 DAG.getBasicBlock(JT.MBB));
1580 DAG.setRoot(BrCond);
1583 /// visitBitTestHeader - This function emits necessary code to produce value
1584 /// suitable for "bit tests"
1585 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1586 MachineBasicBlock *SwitchBB) {
1587 // Subtract the minimum value
1588 SDValue SwitchOp = getValue(B.SValue);
1589 EVT VT = SwitchOp.getValueType();
1590 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1591 DAG.getConstant(B.First, VT));
1594 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1595 TLI.getSetCCResultType(Sub.getValueType()),
1596 Sub, DAG.getConstant(B.Range, VT),
1599 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1600 TLI.getPointerTy());
1602 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy());
1603 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1606 // Set NextBlock to be the MBB immediately after the current one, if any.
1607 // This is used to avoid emitting unnecessary branches to the next block.
1608 MachineBasicBlock *NextBlock = 0;
1609 MachineFunction::iterator BBI = SwitchBB;
1610 if (++BBI != FuncInfo.MF->end())
1613 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1615 SwitchBB->addSuccessor(B.Default);
1616 SwitchBB->addSuccessor(MBB);
1618 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1619 MVT::Other, CopyTo, RangeCmp,
1620 DAG.getBasicBlock(B.Default));
1622 if (MBB != NextBlock)
1623 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1624 DAG.getBasicBlock(MBB));
1626 DAG.setRoot(BrRange);
1629 /// visitBitTestCase - this function produces one "bit test"
1630 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1633 MachineBasicBlock *SwitchBB) {
1634 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1635 TLI.getPointerTy());
1637 if (CountPopulation_64(B.Mask) == 1) {
1638 // Testing for a single bit; just compare the shift count with what it
1639 // would need to be to shift a 1 bit in that position.
1640 Cmp = DAG.getSetCC(getCurDebugLoc(),
1641 TLI.getSetCCResultType(ShiftOp.getValueType()),
1643 DAG.getConstant(CountTrailingZeros_64(B.Mask),
1644 TLI.getPointerTy()),
1647 // Make desired shift
1648 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1650 DAG.getConstant(1, TLI.getPointerTy()),
1653 // Emit bit tests and jumps
1654 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1655 TLI.getPointerTy(), SwitchVal,
1656 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1657 Cmp = DAG.getSetCC(getCurDebugLoc(),
1658 TLI.getSetCCResultType(AndOp.getValueType()),
1659 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1663 SwitchBB->addSuccessor(B.TargetBB);
1664 SwitchBB->addSuccessor(NextMBB);
1666 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1667 MVT::Other, getControlRoot(),
1668 Cmp, DAG.getBasicBlock(B.TargetBB));
1670 // Set NextBlock to be the MBB immediately after the current one, if any.
1671 // This is used to avoid emitting unnecessary branches to the next block.
1672 MachineBasicBlock *NextBlock = 0;
1673 MachineFunction::iterator BBI = SwitchBB;
1674 if (++BBI != FuncInfo.MF->end())
1677 if (NextMBB != NextBlock)
1678 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1679 DAG.getBasicBlock(NextMBB));
1684 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1685 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1687 // Retrieve successors.
1688 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1689 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1691 const Value *Callee(I.getCalledValue());
1692 if (isa<InlineAsm>(Callee))
1695 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1697 // If the value of the invoke is used outside of its defining block, make it
1698 // available as a virtual register.
1699 CopyToExportRegsIfNeeded(&I);
1701 // Update successor info
1702 InvokeMBB->addSuccessor(Return);
1703 InvokeMBB->addSuccessor(LandingPad);
1705 // Drop into normal successor.
1706 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1707 MVT::Other, getControlRoot(),
1708 DAG.getBasicBlock(Return)));
1711 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1714 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1715 /// small case ranges).
1716 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1717 CaseRecVector& WorkList,
1719 MachineBasicBlock *Default,
1720 MachineBasicBlock *SwitchBB) {
1721 Case& BackCase = *(CR.Range.second-1);
1723 // Size is the number of Cases represented by this range.
1724 size_t Size = CR.Range.second - CR.Range.first;
1728 // Get the MachineFunction which holds the current MBB. This is used when
1729 // inserting any additional MBBs necessary to represent the switch.
1730 MachineFunction *CurMF = FuncInfo.MF;
1732 // Figure out which block is immediately after the current one.
1733 MachineBasicBlock *NextBlock = 0;
1734 MachineFunction::iterator BBI = CR.CaseBB;
1736 if (++BBI != FuncInfo.MF->end())
1739 // TODO: If any two of the cases has the same destination, and if one value
1740 // is the same as the other, but has one bit unset that the other has set,
1741 // use bit manipulation to do two compares at once. For example:
1742 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1744 // Rearrange the case blocks so that the last one falls through if possible.
1745 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1746 // The last case block won't fall through into 'NextBlock' if we emit the
1747 // branches in this order. See if rearranging a case value would help.
1748 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1749 if (I->BB == NextBlock) {
1750 std::swap(*I, BackCase);
1756 // Create a CaseBlock record representing a conditional branch to
1757 // the Case's target mbb if the value being switched on SV is equal
1759 MachineBasicBlock *CurBlock = CR.CaseBB;
1760 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1761 MachineBasicBlock *FallThrough;
1763 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1764 CurMF->insert(BBI, FallThrough);
1766 // Put SV in a virtual register to make it available from the new blocks.
1767 ExportFromCurrentBlock(SV);
1769 // If the last case doesn't match, go to the default block.
1770 FallThrough = Default;
1773 const Value *RHS, *LHS, *MHS;
1775 if (I->High == I->Low) {
1776 // This is just small small case range :) containing exactly 1 case
1778 LHS = SV; RHS = I->High; MHS = NULL;
1781 LHS = I->Low; MHS = SV; RHS = I->High;
1783 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1785 // If emitting the first comparison, just call visitSwitchCase to emit the
1786 // code into the current block. Otherwise, push the CaseBlock onto the
1787 // vector to be later processed by SDISel, and insert the node's MBB
1788 // before the next MBB.
1789 if (CurBlock == SwitchBB)
1790 visitSwitchCase(CB, SwitchBB);
1792 SwitchCases.push_back(CB);
1794 CurBlock = FallThrough;
1800 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1801 return !DisableJumpTables &&
1802 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1803 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1806 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1807 APInt LastExt(Last), FirstExt(First);
1808 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1809 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1810 return (LastExt - FirstExt + 1ULL);
1813 /// handleJTSwitchCase - Emit jumptable for current switch case range
1814 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1815 CaseRecVector& WorkList,
1817 MachineBasicBlock* Default,
1818 MachineBasicBlock *SwitchBB) {
1819 Case& FrontCase = *CR.Range.first;
1820 Case& BackCase = *(CR.Range.second-1);
1822 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1823 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1825 APInt TSize(First.getBitWidth(), 0);
1826 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1830 if (!areJTsAllowed(TLI) || TSize.ult(4))
1833 APInt Range = ComputeRange(First, Last);
1834 double Density = TSize.roundToDouble() / Range.roundToDouble();
1838 DEBUG(dbgs() << "Lowering jump table\n"
1839 << "First entry: " << First << ". Last entry: " << Last << '\n'
1840 << "Range: " << Range
1841 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1843 // Get the MachineFunction which holds the current MBB. This is used when
1844 // inserting any additional MBBs necessary to represent the switch.
1845 MachineFunction *CurMF = FuncInfo.MF;
1847 // Figure out which block is immediately after the current one.
1848 MachineFunction::iterator BBI = CR.CaseBB;
1851 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1853 // Create a new basic block to hold the code for loading the address
1854 // of the jump table, and jumping to it. Update successor information;
1855 // we will either branch to the default case for the switch, or the jump
1857 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1858 CurMF->insert(BBI, JumpTableBB);
1859 CR.CaseBB->addSuccessor(Default);
1860 CR.CaseBB->addSuccessor(JumpTableBB);
1862 // Build a vector of destination BBs, corresponding to each target
1863 // of the jump table. If the value of the jump table slot corresponds to
1864 // a case statement, push the case's BB onto the vector, otherwise, push
1866 std::vector<MachineBasicBlock*> DestBBs;
1868 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1869 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1870 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1872 if (Low.sle(TEI) && TEI.sle(High)) {
1873 DestBBs.push_back(I->BB);
1877 DestBBs.push_back(Default);
1881 // Update successor info. Add one edge to each unique successor.
1882 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1883 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1884 E = DestBBs.end(); I != E; ++I) {
1885 if (!SuccsHandled[(*I)->getNumber()]) {
1886 SuccsHandled[(*I)->getNumber()] = true;
1887 JumpTableBB->addSuccessor(*I);
1891 // Create a jump table index for this jump table.
1892 unsigned JTEncoding = TLI.getJumpTableEncoding();
1893 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1894 ->createJumpTableIndex(DestBBs);
1896 // Set the jump table information so that we can codegen it as a second
1897 // MachineBasicBlock
1898 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1899 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1900 if (CR.CaseBB == SwitchBB)
1901 visitJumpTableHeader(JT, JTH, SwitchBB);
1903 JTCases.push_back(JumpTableBlock(JTH, JT));
1908 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1910 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1911 CaseRecVector& WorkList,
1913 MachineBasicBlock *Default,
1914 MachineBasicBlock *SwitchBB) {
1915 // Get the MachineFunction which holds the current MBB. This is used when
1916 // inserting any additional MBBs necessary to represent the switch.
1917 MachineFunction *CurMF = FuncInfo.MF;
1919 // Figure out which block is immediately after the current one.
1920 MachineFunction::iterator BBI = CR.CaseBB;
1923 Case& FrontCase = *CR.Range.first;
1924 Case& BackCase = *(CR.Range.second-1);
1925 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1927 // Size is the number of Cases represented by this range.
1928 unsigned Size = CR.Range.second - CR.Range.first;
1930 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1931 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1933 CaseItr Pivot = CR.Range.first + Size/2;
1935 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1936 // (heuristically) allow us to emit JumpTable's later.
1937 APInt TSize(First.getBitWidth(), 0);
1938 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1942 APInt LSize = FrontCase.size();
1943 APInt RSize = TSize-LSize;
1944 DEBUG(dbgs() << "Selecting best pivot: \n"
1945 << "First: " << First << ", Last: " << Last <<'\n'
1946 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1947 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1949 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1950 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1951 APInt Range = ComputeRange(LEnd, RBegin);
1952 assert((Range - 2ULL).isNonNegative() &&
1953 "Invalid case distance");
1954 double LDensity = (double)LSize.roundToDouble() /
1955 (LEnd - First + 1ULL).roundToDouble();
1956 double RDensity = (double)RSize.roundToDouble() /
1957 (Last - RBegin + 1ULL).roundToDouble();
1958 double Metric = Range.logBase2()*(LDensity+RDensity);
1959 // Should always split in some non-trivial place
1960 DEBUG(dbgs() <<"=>Step\n"
1961 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1962 << "LDensity: " << LDensity
1963 << ", RDensity: " << RDensity << '\n'
1964 << "Metric: " << Metric << '\n');
1965 if (FMetric < Metric) {
1968 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1974 if (areJTsAllowed(TLI)) {
1975 // If our case is dense we *really* should handle it earlier!
1976 assert((FMetric > 0) && "Should handle dense range earlier!");
1978 Pivot = CR.Range.first + Size/2;
1981 CaseRange LHSR(CR.Range.first, Pivot);
1982 CaseRange RHSR(Pivot, CR.Range.second);
1983 Constant *C = Pivot->Low;
1984 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1986 // We know that we branch to the LHS if the Value being switched on is
1987 // less than the Pivot value, C. We use this to optimize our binary
1988 // tree a bit, by recognizing that if SV is greater than or equal to the
1989 // LHS's Case Value, and that Case Value is exactly one less than the
1990 // Pivot's Value, then we can branch directly to the LHS's Target,
1991 // rather than creating a leaf node for it.
1992 if ((LHSR.second - LHSR.first) == 1 &&
1993 LHSR.first->High == CR.GE &&
1994 cast<ConstantInt>(C)->getValue() ==
1995 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1996 TrueBB = LHSR.first->BB;
1998 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1999 CurMF->insert(BBI, TrueBB);
2000 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2002 // Put SV in a virtual register to make it available from the new blocks.
2003 ExportFromCurrentBlock(SV);
2006 // Similar to the optimization above, if the Value being switched on is
2007 // known to be less than the Constant CR.LT, and the current Case Value
2008 // is CR.LT - 1, then we can branch directly to the target block for
2009 // the current Case Value, rather than emitting a RHS leaf node for it.
2010 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2011 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2012 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2013 FalseBB = RHSR.first->BB;
2015 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2016 CurMF->insert(BBI, FalseBB);
2017 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2019 // Put SV in a virtual register to make it available from the new blocks.
2020 ExportFromCurrentBlock(SV);
2023 // Create a CaseBlock record representing a conditional branch to
2024 // the LHS node if the value being switched on SV is less than C.
2025 // Otherwise, branch to LHS.
2026 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2028 if (CR.CaseBB == SwitchBB)
2029 visitSwitchCase(CB, SwitchBB);
2031 SwitchCases.push_back(CB);
2036 /// handleBitTestsSwitchCase - if current case range has few destination and
2037 /// range span less, than machine word bitwidth, encode case range into series
2038 /// of masks and emit bit tests with these masks.
2039 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2040 CaseRecVector& WorkList,
2042 MachineBasicBlock* Default,
2043 MachineBasicBlock *SwitchBB){
2044 EVT PTy = TLI.getPointerTy();
2045 unsigned IntPtrBits = PTy.getSizeInBits();
2047 Case& FrontCase = *CR.Range.first;
2048 Case& BackCase = *(CR.Range.second-1);
2050 // Get the MachineFunction which holds the current MBB. This is used when
2051 // inserting any additional MBBs necessary to represent the switch.
2052 MachineFunction *CurMF = FuncInfo.MF;
2054 // If target does not have legal shift left, do not emit bit tests at all.
2055 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2059 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2061 // Single case counts one, case range - two.
2062 numCmps += (I->Low == I->High ? 1 : 2);
2065 // Count unique destinations
2066 SmallSet<MachineBasicBlock*, 4> Dests;
2067 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2068 Dests.insert(I->BB);
2069 if (Dests.size() > 3)
2070 // Don't bother the code below, if there are too much unique destinations
2073 DEBUG(dbgs() << "Total number of unique destinations: "
2074 << Dests.size() << '\n'
2075 << "Total number of comparisons: " << numCmps << '\n');
2077 // Compute span of values.
2078 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2079 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2080 APInt cmpRange = maxValue - minValue;
2082 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2083 << "Low bound: " << minValue << '\n'
2084 << "High bound: " << maxValue << '\n');
2086 if (cmpRange.uge(IntPtrBits) ||
2087 (!(Dests.size() == 1 && numCmps >= 3) &&
2088 !(Dests.size() == 2 && numCmps >= 5) &&
2089 !(Dests.size() >= 3 && numCmps >= 6)))
2092 DEBUG(dbgs() << "Emitting bit tests\n");
2093 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2095 // Optimize the case where all the case values fit in a
2096 // word without having to subtract minValue. In this case,
2097 // we can optimize away the subtraction.
2098 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2099 cmpRange = maxValue;
2101 lowBound = minValue;
2104 CaseBitsVector CasesBits;
2105 unsigned i, count = 0;
2107 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2108 MachineBasicBlock* Dest = I->BB;
2109 for (i = 0; i < count; ++i)
2110 if (Dest == CasesBits[i].BB)
2114 assert((count < 3) && "Too much destinations to test!");
2115 CasesBits.push_back(CaseBits(0, Dest, 0));
2119 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2120 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2122 uint64_t lo = (lowValue - lowBound).getZExtValue();
2123 uint64_t hi = (highValue - lowBound).getZExtValue();
2125 for (uint64_t j = lo; j <= hi; j++) {
2126 CasesBits[i].Mask |= 1ULL << j;
2127 CasesBits[i].Bits++;
2131 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2135 // Figure out which block is immediately after the current one.
2136 MachineFunction::iterator BBI = CR.CaseBB;
2139 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2141 DEBUG(dbgs() << "Cases:\n");
2142 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2143 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2144 << ", Bits: " << CasesBits[i].Bits
2145 << ", BB: " << CasesBits[i].BB << '\n');
2147 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2148 CurMF->insert(BBI, CaseBB);
2149 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2153 // Put SV in a virtual register to make it available from the new blocks.
2154 ExportFromCurrentBlock(SV);
2157 BitTestBlock BTB(lowBound, cmpRange, SV,
2158 -1U, (CR.CaseBB == SwitchBB),
2159 CR.CaseBB, Default, BTC);
2161 if (CR.CaseBB == SwitchBB)
2162 visitBitTestHeader(BTB, SwitchBB);
2164 BitTestCases.push_back(BTB);
2169 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2170 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2171 const SwitchInst& SI) {
2174 // Start with "simple" cases
2175 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2176 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2177 Cases.push_back(Case(SI.getSuccessorValue(i),
2178 SI.getSuccessorValue(i),
2181 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2183 // Merge case into clusters
2184 if (Cases.size() >= 2)
2185 // Must recompute end() each iteration because it may be
2186 // invalidated by erase if we hold on to it
2187 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2188 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2189 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2190 MachineBasicBlock* nextBB = J->BB;
2191 MachineBasicBlock* currentBB = I->BB;
2193 // If the two neighboring cases go to the same destination, merge them
2194 // into a single case.
2195 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2203 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2204 if (I->Low != I->High)
2205 // A range counts double, since it requires two compares.
2212 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2213 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2215 // Figure out which block is immediately after the current one.
2216 MachineBasicBlock *NextBlock = 0;
2217 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2219 // If there is only the default destination, branch to it if it is not the
2220 // next basic block. Otherwise, just fall through.
2221 if (SI.getNumOperands() == 2) {
2222 // Update machine-CFG edges.
2224 // If this is not a fall-through branch, emit the branch.
2225 SwitchMBB->addSuccessor(Default);
2226 if (Default != NextBlock)
2227 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2228 MVT::Other, getControlRoot(),
2229 DAG.getBasicBlock(Default)));
2234 // If there are any non-default case statements, create a vector of Cases
2235 // representing each one, and sort the vector so that we can efficiently
2236 // create a binary search tree from them.
2238 size_t numCmps = Clusterify(Cases, SI);
2239 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2240 << ". Total compares: " << numCmps << '\n');
2243 // Get the Value to be switched on and default basic blocks, which will be
2244 // inserted into CaseBlock records, representing basic blocks in the binary
2246 const Value *SV = SI.getOperand(0);
2248 // Push the initial CaseRec onto the worklist
2249 CaseRecVector WorkList;
2250 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2251 CaseRange(Cases.begin(),Cases.end())));
2253 while (!WorkList.empty()) {
2254 // Grab a record representing a case range to process off the worklist
2255 CaseRec CR = WorkList.back();
2256 WorkList.pop_back();
2258 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2261 // If the range has few cases (two or less) emit a series of specific
2263 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2266 // If the switch has more than 5 blocks, and at least 40% dense, and the
2267 // target supports indirect branches, then emit a jump table rather than
2268 // lowering the switch to a binary tree of conditional branches.
2269 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2272 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2273 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2274 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2278 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2279 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2281 // Update machine-CFG edges with unique successors.
2282 SmallVector<BasicBlock*, 32> succs;
2283 succs.reserve(I.getNumSuccessors());
2284 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2285 succs.push_back(I.getSuccessor(i));
2286 array_pod_sort(succs.begin(), succs.end());
2287 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2288 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2289 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2291 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2292 MVT::Other, getControlRoot(),
2293 getValue(I.getAddress())));
2296 void SelectionDAGBuilder::visitFSub(const User &I) {
2297 // -0.0 - X --> fneg
2298 const Type *Ty = I.getType();
2299 if (Ty->isVectorTy()) {
2300 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2301 const VectorType *DestTy = cast<VectorType>(I.getType());
2302 const Type *ElTy = DestTy->getElementType();
2303 unsigned VL = DestTy->getNumElements();
2304 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2305 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2307 SDValue Op2 = getValue(I.getOperand(1));
2308 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2309 Op2.getValueType(), Op2));
2315 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2316 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2317 SDValue Op2 = getValue(I.getOperand(1));
2318 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2319 Op2.getValueType(), Op2));
2323 visitBinary(I, ISD::FSUB);
2326 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2327 SDValue Op1 = getValue(I.getOperand(0));
2328 SDValue Op2 = getValue(I.getOperand(1));
2329 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2330 Op1.getValueType(), Op1, Op2));
2333 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2334 SDValue Op1 = getValue(I.getOperand(0));
2335 SDValue Op2 = getValue(I.getOperand(1));
2336 if (!I.getType()->isVectorTy() &&
2337 Op2.getValueType() != TLI.getShiftAmountTy()) {
2338 // If the operand is smaller than the shift count type, promote it.
2339 EVT PTy = TLI.getPointerTy();
2340 EVT STy = TLI.getShiftAmountTy();
2341 if (STy.bitsGT(Op2.getValueType()))
2342 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2343 TLI.getShiftAmountTy(), Op2);
2344 // If the operand is larger than the shift count type but the shift
2345 // count type has enough bits to represent any shift value, truncate
2346 // it now. This is a common case and it exposes the truncate to
2347 // optimization early.
2348 else if (STy.getSizeInBits() >=
2349 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2350 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2351 TLI.getShiftAmountTy(), Op2);
2352 // Otherwise we'll need to temporarily settle for some other
2353 // convenient type; type legalization will make adjustments as
2355 else if (PTy.bitsLT(Op2.getValueType()))
2356 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2357 TLI.getPointerTy(), Op2);
2358 else if (PTy.bitsGT(Op2.getValueType()))
2359 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2360 TLI.getPointerTy(), Op2);
2363 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2364 Op1.getValueType(), Op1, Op2));
2367 void SelectionDAGBuilder::visitICmp(const User &I) {
2368 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2369 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2370 predicate = IC->getPredicate();
2371 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2372 predicate = ICmpInst::Predicate(IC->getPredicate());
2373 SDValue Op1 = getValue(I.getOperand(0));
2374 SDValue Op2 = getValue(I.getOperand(1));
2375 ISD::CondCode Opcode = getICmpCondCode(predicate);
2377 EVT DestVT = TLI.getValueType(I.getType());
2378 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2381 void SelectionDAGBuilder::visitFCmp(const User &I) {
2382 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2383 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2384 predicate = FC->getPredicate();
2385 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2386 predicate = FCmpInst::Predicate(FC->getPredicate());
2387 SDValue Op1 = getValue(I.getOperand(0));
2388 SDValue Op2 = getValue(I.getOperand(1));
2389 ISD::CondCode Condition = getFCmpCondCode(predicate);
2390 EVT DestVT = TLI.getValueType(I.getType());
2391 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2394 void SelectionDAGBuilder::visitSelect(const User &I) {
2395 SmallVector<EVT, 4> ValueVTs;
2396 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2397 unsigned NumValues = ValueVTs.size();
2398 if (NumValues == 0) return;
2400 SmallVector<SDValue, 4> Values(NumValues);
2401 SDValue Cond = getValue(I.getOperand(0));
2402 SDValue TrueVal = getValue(I.getOperand(1));
2403 SDValue FalseVal = getValue(I.getOperand(2));
2405 for (unsigned i = 0; i != NumValues; ++i)
2406 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2407 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2409 SDValue(TrueVal.getNode(),
2410 TrueVal.getResNo() + i),
2411 SDValue(FalseVal.getNode(),
2412 FalseVal.getResNo() + i));
2414 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2415 DAG.getVTList(&ValueVTs[0], NumValues),
2416 &Values[0], NumValues));
2419 void SelectionDAGBuilder::visitTrunc(const User &I) {
2420 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2421 SDValue N = getValue(I.getOperand(0));
2422 EVT DestVT = TLI.getValueType(I.getType());
2423 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2426 void SelectionDAGBuilder::visitZExt(const User &I) {
2427 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2428 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2429 SDValue N = getValue(I.getOperand(0));
2430 EVT DestVT = TLI.getValueType(I.getType());
2431 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2434 void SelectionDAGBuilder::visitSExt(const User &I) {
2435 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2436 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2437 SDValue N = getValue(I.getOperand(0));
2438 EVT DestVT = TLI.getValueType(I.getType());
2439 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2442 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2443 // FPTrunc is never a no-op cast, no need to check
2444 SDValue N = getValue(I.getOperand(0));
2445 EVT DestVT = TLI.getValueType(I.getType());
2446 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2447 DestVT, N, DAG.getIntPtrConstant(0)));
2450 void SelectionDAGBuilder::visitFPExt(const User &I){
2451 // FPTrunc is never a no-op cast, no need to check
2452 SDValue N = getValue(I.getOperand(0));
2453 EVT DestVT = TLI.getValueType(I.getType());
2454 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2457 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2458 // FPToUI is never a no-op cast, no need to check
2459 SDValue N = getValue(I.getOperand(0));
2460 EVT DestVT = TLI.getValueType(I.getType());
2461 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2464 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2465 // FPToSI is never a no-op cast, no need to check
2466 SDValue N = getValue(I.getOperand(0));
2467 EVT DestVT = TLI.getValueType(I.getType());
2468 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2471 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2472 // UIToFP is never a no-op cast, no need to check
2473 SDValue N = getValue(I.getOperand(0));
2474 EVT DestVT = TLI.getValueType(I.getType());
2475 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2478 void SelectionDAGBuilder::visitSIToFP(const User &I){
2479 // SIToFP is never a no-op cast, no need to check
2480 SDValue N = getValue(I.getOperand(0));
2481 EVT DestVT = TLI.getValueType(I.getType());
2482 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2485 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2486 // What to do depends on the size of the integer and the size of the pointer.
2487 // We can either truncate, zero extend, or no-op, accordingly.
2488 SDValue N = getValue(I.getOperand(0));
2489 EVT DestVT = TLI.getValueType(I.getType());
2490 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2493 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2494 // What to do depends on the size of the integer and the size of the pointer.
2495 // We can either truncate, zero extend, or no-op, accordingly.
2496 SDValue N = getValue(I.getOperand(0));
2497 EVT DestVT = TLI.getValueType(I.getType());
2498 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2501 void SelectionDAGBuilder::visitBitCast(const User &I) {
2502 SDValue N = getValue(I.getOperand(0));
2503 EVT DestVT = TLI.getValueType(I.getType());
2505 // BitCast assures us that source and destination are the same size so this is
2506 // either a BIT_CONVERT or a no-op.
2507 if (DestVT != N.getValueType())
2508 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2509 DestVT, N)); // convert types.
2511 setValue(&I, N); // noop cast.
2514 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2515 SDValue InVec = getValue(I.getOperand(0));
2516 SDValue InVal = getValue(I.getOperand(1));
2517 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2519 getValue(I.getOperand(2)));
2520 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2521 TLI.getValueType(I.getType()),
2522 InVec, InVal, InIdx));
2525 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2526 SDValue InVec = getValue(I.getOperand(0));
2527 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2529 getValue(I.getOperand(1)));
2530 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2531 TLI.getValueType(I.getType()), InVec, InIdx));
2534 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2535 // from SIndx and increasing to the element length (undefs are allowed).
2536 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2537 unsigned MaskNumElts = Mask.size();
2538 for (unsigned i = 0; i != MaskNumElts; ++i)
2539 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2544 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2545 SmallVector<int, 8> Mask;
2546 SDValue Src1 = getValue(I.getOperand(0));
2547 SDValue Src2 = getValue(I.getOperand(1));
2549 // Convert the ConstantVector mask operand into an array of ints, with -1
2550 // representing undef values.
2551 SmallVector<Constant*, 8> MaskElts;
2552 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2553 unsigned MaskNumElts = MaskElts.size();
2554 for (unsigned i = 0; i != MaskNumElts; ++i) {
2555 if (isa<UndefValue>(MaskElts[i]))
2558 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2561 EVT VT = TLI.getValueType(I.getType());
2562 EVT SrcVT = Src1.getValueType();
2563 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2565 if (SrcNumElts == MaskNumElts) {
2566 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2571 // Normalize the shuffle vector since mask and vector length don't match.
2572 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2573 // Mask is longer than the source vectors and is a multiple of the source
2574 // vectors. We can use concatenate vector to make the mask and vectors
2576 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2577 // The shuffle is concatenating two vectors together.
2578 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2583 // Pad both vectors with undefs to make them the same length as the mask.
2584 unsigned NumConcat = MaskNumElts / SrcNumElts;
2585 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2586 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2587 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2589 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2590 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2594 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2595 getCurDebugLoc(), VT,
2596 &MOps1[0], NumConcat);
2597 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2598 getCurDebugLoc(), VT,
2599 &MOps2[0], NumConcat);
2601 // Readjust mask for new input vector length.
2602 SmallVector<int, 8> MappedOps;
2603 for (unsigned i = 0; i != MaskNumElts; ++i) {
2605 if (Idx < (int)SrcNumElts)
2606 MappedOps.push_back(Idx);
2608 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2611 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2616 if (SrcNumElts > MaskNumElts) {
2617 // Analyze the access pattern of the vector to see if we can extract
2618 // two subvectors and do the shuffle. The analysis is done by calculating
2619 // the range of elements the mask access on both vectors.
2620 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2621 int MaxRange[2] = {-1, -1};
2623 for (unsigned i = 0; i != MaskNumElts; ++i) {
2629 if (Idx >= (int)SrcNumElts) {
2633 if (Idx > MaxRange[Input])
2634 MaxRange[Input] = Idx;
2635 if (Idx < MinRange[Input])
2636 MinRange[Input] = Idx;
2639 // Check if the access is smaller than the vector size and can we find
2640 // a reasonable extract index.
2641 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2643 int StartIdx[2]; // StartIdx to extract from
2644 for (int Input=0; Input < 2; ++Input) {
2645 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2646 RangeUse[Input] = 0; // Unused
2647 StartIdx[Input] = 0;
2648 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2649 // Fits within range but we should see if we can find a good
2650 // start index that is a multiple of the mask length.
2651 if (MaxRange[Input] < (int)MaskNumElts) {
2652 RangeUse[Input] = 1; // Extract from beginning of the vector
2653 StartIdx[Input] = 0;
2655 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2656 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2657 StartIdx[Input] + MaskNumElts < SrcNumElts)
2658 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2663 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2664 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2667 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2668 // Extract appropriate subvector and generate a vector shuffle
2669 for (int Input=0; Input < 2; ++Input) {
2670 SDValue &Src = Input == 0 ? Src1 : Src2;
2671 if (RangeUse[Input] == 0)
2672 Src = DAG.getUNDEF(VT);
2674 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2675 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2678 // Calculate new mask.
2679 SmallVector<int, 8> MappedOps;
2680 for (unsigned i = 0; i != MaskNumElts; ++i) {
2683 MappedOps.push_back(Idx);
2684 else if (Idx < (int)SrcNumElts)
2685 MappedOps.push_back(Idx - StartIdx[0]);
2687 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2690 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2696 // We can't use either concat vectors or extract subvectors so fall back to
2697 // replacing the shuffle with extract and build vector.
2698 // to insert and build vector.
2699 EVT EltVT = VT.getVectorElementType();
2700 EVT PtrVT = TLI.getPointerTy();
2701 SmallVector<SDValue,8> Ops;
2702 for (unsigned i = 0; i != MaskNumElts; ++i) {
2704 Ops.push_back(DAG.getUNDEF(EltVT));
2709 if (Idx < (int)SrcNumElts)
2710 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2711 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2713 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2715 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2721 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2722 VT, &Ops[0], Ops.size()));
2725 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2726 const Value *Op0 = I.getOperand(0);
2727 const Value *Op1 = I.getOperand(1);
2728 const Type *AggTy = I.getType();
2729 const Type *ValTy = Op1->getType();
2730 bool IntoUndef = isa<UndefValue>(Op0);
2731 bool FromUndef = isa<UndefValue>(Op1);
2733 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2734 I.idx_begin(), I.idx_end());
2736 SmallVector<EVT, 4> AggValueVTs;
2737 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2738 SmallVector<EVT, 4> ValValueVTs;
2739 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2741 unsigned NumAggValues = AggValueVTs.size();
2742 unsigned NumValValues = ValValueVTs.size();
2743 SmallVector<SDValue, 4> Values(NumAggValues);
2745 SDValue Agg = getValue(Op0);
2746 SDValue Val = getValue(Op1);
2748 // Copy the beginning value(s) from the original aggregate.
2749 for (; i != LinearIndex; ++i)
2750 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2751 SDValue(Agg.getNode(), Agg.getResNo() + i);
2752 // Copy values from the inserted value(s).
2753 for (; i != LinearIndex + NumValValues; ++i)
2754 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2755 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2756 // Copy remaining value(s) from the original aggregate.
2757 for (; i != NumAggValues; ++i)
2758 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2759 SDValue(Agg.getNode(), Agg.getResNo() + i);
2761 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2762 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2763 &Values[0], NumAggValues));
2766 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2767 const Value *Op0 = I.getOperand(0);
2768 const Type *AggTy = Op0->getType();
2769 const Type *ValTy = I.getType();
2770 bool OutOfUndef = isa<UndefValue>(Op0);
2772 unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
2773 I.idx_begin(), I.idx_end());
2775 SmallVector<EVT, 4> ValValueVTs;
2776 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2778 unsigned NumValValues = ValValueVTs.size();
2779 SmallVector<SDValue, 4> Values(NumValValues);
2781 SDValue Agg = getValue(Op0);
2782 // Copy out the selected value(s).
2783 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2784 Values[i - LinearIndex] =
2786 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2787 SDValue(Agg.getNode(), Agg.getResNo() + i);
2789 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2790 DAG.getVTList(&ValValueVTs[0], NumValValues),
2791 &Values[0], NumValValues));
2794 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2795 SDValue N = getValue(I.getOperand(0));
2796 const Type *Ty = I.getOperand(0)->getType();
2798 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2800 const Value *Idx = *OI;
2801 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2802 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2805 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2806 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2807 DAG.getIntPtrConstant(Offset));
2810 Ty = StTy->getElementType(Field);
2811 } else if (const UnionType *UnTy = dyn_cast<UnionType>(Ty)) {
2812 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2814 // Offset canonically 0 for unions, but type changes
2815 Ty = UnTy->getElementType(Field);
2817 Ty = cast<SequentialType>(Ty)->getElementType();
2819 // If this is a constant subscript, handle it quickly.
2820 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2821 if (CI->isZero()) continue;
2823 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2825 EVT PTy = TLI.getPointerTy();
2826 unsigned PtrBits = PTy.getSizeInBits();
2828 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2830 DAG.getConstant(Offs, MVT::i64));
2832 OffsVal = DAG.getIntPtrConstant(Offs);
2834 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2839 // N = N + Idx * ElementSize;
2840 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2841 TD->getTypeAllocSize(Ty));
2842 SDValue IdxN = getValue(Idx);
2844 // If the index is smaller or larger than intptr_t, truncate or extend
2846 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2848 // If this is a multiply by a power of two, turn it into a shl
2849 // immediately. This is a very common case.
2850 if (ElementSize != 1) {
2851 if (ElementSize.isPowerOf2()) {
2852 unsigned Amt = ElementSize.logBase2();
2853 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2854 N.getValueType(), IdxN,
2855 DAG.getConstant(Amt, TLI.getPointerTy()));
2857 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2858 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2859 N.getValueType(), IdxN, Scale);
2863 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2864 N.getValueType(), N, IdxN);
2871 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2872 // If this is a fixed sized alloca in the entry block of the function,
2873 // allocate it statically on the stack.
2874 if (FuncInfo.StaticAllocaMap.count(&I))
2875 return; // getValue will auto-populate this.
2877 const Type *Ty = I.getAllocatedType();
2878 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2880 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2883 SDValue AllocSize = getValue(I.getArraySize());
2885 EVT IntPtr = TLI.getPointerTy();
2886 if (AllocSize.getValueType() != IntPtr)
2887 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2889 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2891 DAG.getConstant(TySize, IntPtr));
2893 // Handle alignment. If the requested alignment is less than or equal to
2894 // the stack alignment, ignore it. If the size is greater than or equal to
2895 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2896 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2897 if (Align <= StackAlign)
2900 // Round the size of the allocation up to the stack alignment size
2901 // by add SA-1 to the size.
2902 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2903 AllocSize.getValueType(), AllocSize,
2904 DAG.getIntPtrConstant(StackAlign-1));
2906 // Mask out the low bits for alignment purposes.
2907 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2908 AllocSize.getValueType(), AllocSize,
2909 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2911 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2912 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2913 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2916 DAG.setRoot(DSA.getValue(1));
2918 // Inform the Frame Information that we have just allocated a variable-sized
2920 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2923 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2924 const Value *SV = I.getOperand(0);
2925 SDValue Ptr = getValue(SV);
2927 const Type *Ty = I.getType();
2929 bool isVolatile = I.isVolatile();
2930 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2931 unsigned Alignment = I.getAlignment();
2933 SmallVector<EVT, 4> ValueVTs;
2934 SmallVector<uint64_t, 4> Offsets;
2935 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2936 unsigned NumValues = ValueVTs.size();
2941 bool ConstantMemory = false;
2943 // Serialize volatile loads with other side effects.
2945 else if (AA->pointsToConstantMemory(SV)) {
2946 // Do not serialize (non-volatile) loads of constant memory with anything.
2947 Root = DAG.getEntryNode();
2948 ConstantMemory = true;
2950 // Do not serialize non-volatile loads against each other.
2951 Root = DAG.getRoot();
2954 SmallVector<SDValue, 4> Values(NumValues);
2955 SmallVector<SDValue, 4> Chains(NumValues);
2956 EVT PtrVT = Ptr.getValueType();
2957 for (unsigned i = 0; i != NumValues; ++i) {
2958 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2960 DAG.getConstant(Offsets[i], PtrVT));
2961 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2962 A, SV, Offsets[i], isVolatile,
2963 isNonTemporal, Alignment);
2966 Chains[i] = L.getValue(1);
2969 if (!ConstantMemory) {
2970 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2971 MVT::Other, &Chains[0], NumValues);
2975 PendingLoads.push_back(Chain);
2978 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2979 DAG.getVTList(&ValueVTs[0], NumValues),
2980 &Values[0], NumValues));
2983 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2984 const Value *SrcV = I.getOperand(0);
2985 const Value *PtrV = I.getOperand(1);
2987 SmallVector<EVT, 4> ValueVTs;
2988 SmallVector<uint64_t, 4> Offsets;
2989 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2990 unsigned NumValues = ValueVTs.size();
2994 // Get the lowered operands. Note that we do this after
2995 // checking if NumResults is zero, because with zero results
2996 // the operands won't have values in the map.
2997 SDValue Src = getValue(SrcV);
2998 SDValue Ptr = getValue(PtrV);
3000 SDValue Root = getRoot();
3001 SmallVector<SDValue, 4> Chains(NumValues);
3002 EVT PtrVT = Ptr.getValueType();
3003 bool isVolatile = I.isVolatile();
3004 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3005 unsigned Alignment = I.getAlignment();
3007 for (unsigned i = 0; i != NumValues; ++i) {
3008 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3009 DAG.getConstant(Offsets[i], PtrVT));
3010 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
3011 SDValue(Src.getNode(), Src.getResNo() + i),
3012 Add, PtrV, Offsets[i], isVolatile,
3013 isNonTemporal, Alignment);
3016 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3017 MVT::Other, &Chains[0], NumValues));
3020 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3022 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3023 unsigned Intrinsic) {
3024 bool HasChain = !I.doesNotAccessMemory();
3025 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3027 // Build the operand list.
3028 SmallVector<SDValue, 8> Ops;
3029 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3031 // We don't need to serialize loads against other loads.
3032 Ops.push_back(DAG.getRoot());
3034 Ops.push_back(getRoot());
3038 // Info is set by getTgtMemInstrinsic
3039 TargetLowering::IntrinsicInfo Info;
3040 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3042 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3043 if (!IsTgtIntrinsic)
3044 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3046 // Add all operands of the call to the operand list.
3047 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3048 SDValue Op = getValue(I.getArgOperand(i));
3049 assert(TLI.isTypeLegal(Op.getValueType()) &&
3050 "Intrinsic uses a non-legal type?");
3054 SmallVector<EVT, 4> ValueVTs;
3055 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3057 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3058 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3059 "Intrinsic uses a non-legal type?");
3064 ValueVTs.push_back(MVT::Other);
3066 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3070 if (IsTgtIntrinsic) {
3071 // This is target intrinsic that touches memory
3072 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3073 VTs, &Ops[0], Ops.size(),
3074 Info.memVT, Info.ptrVal, Info.offset,
3075 Info.align, Info.vol,
3076 Info.readMem, Info.writeMem);
3077 } else if (!HasChain) {
3078 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3079 VTs, &Ops[0], Ops.size());
3080 } else if (!I.getType()->isVoidTy()) {
3081 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3082 VTs, &Ops[0], Ops.size());
3084 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3085 VTs, &Ops[0], Ops.size());
3089 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3091 PendingLoads.push_back(Chain);
3096 if (!I.getType()->isVoidTy()) {
3097 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3098 EVT VT = TLI.getValueType(PTy);
3099 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3102 setValue(&I, Result);
3106 /// GetSignificand - Get the significand and build it into a floating-point
3107 /// number with exponent of 1:
3109 /// Op = (Op & 0x007fffff) | 0x3f800000;
3111 /// where Op is the hexidecimal representation of floating point value.
3113 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3114 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3115 DAG.getConstant(0x007fffff, MVT::i32));
3116 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3117 DAG.getConstant(0x3f800000, MVT::i32));
3118 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3121 /// GetExponent - Get the exponent:
3123 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3125 /// where Op is the hexidecimal representation of floating point value.
3127 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3129 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3130 DAG.getConstant(0x7f800000, MVT::i32));
3131 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3132 DAG.getConstant(23, TLI.getPointerTy()));
3133 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3134 DAG.getConstant(127, MVT::i32));
3135 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3138 /// getF32Constant - Get 32-bit floating point constant.
3140 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3141 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3144 /// Inlined utility function to implement binary input atomic intrinsics for
3145 /// visitIntrinsicCall: I is a call instruction
3146 /// Op is the associated NodeType for I
3148 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3150 SDValue Root = getRoot();
3152 DAG.getAtomic(Op, getCurDebugLoc(),
3153 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3155 getValue(I.getArgOperand(0)),
3156 getValue(I.getArgOperand(1)),
3157 I.getArgOperand(0));
3159 DAG.setRoot(L.getValue(1));
3163 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3165 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3166 SDValue Op1 = getValue(I.getArgOperand(0));
3167 SDValue Op2 = getValue(I.getArgOperand(1));
3169 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3170 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3174 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3175 /// limited-precision mode.
3177 SelectionDAGBuilder::visitExp(const CallInst &I) {
3179 DebugLoc dl = getCurDebugLoc();
3181 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3182 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3183 SDValue Op = getValue(I.getArgOperand(0));
3185 // Put the exponent in the right bit position for later addition to the
3188 // #define LOG2OFe 1.4426950f
3189 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3190 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3191 getF32Constant(DAG, 0x3fb8aa3b));
3192 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3194 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3195 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3196 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3198 // IntegerPartOfX <<= 23;
3199 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3200 DAG.getConstant(23, TLI.getPointerTy()));
3202 if (LimitFloatPrecision <= 6) {
3203 // For floating-point precision of 6:
3205 // TwoToFractionalPartOfX =
3207 // (0.735607626f + 0.252464424f * x) * x;
3209 // error 0.0144103317, which is 6 bits
3210 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3211 getF32Constant(DAG, 0x3e814304));
3212 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3213 getF32Constant(DAG, 0x3f3c50c8));
3214 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3215 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3216 getF32Constant(DAG, 0x3f7f5e7e));
3217 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3219 // Add the exponent into the result in integer domain.
3220 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3221 TwoToFracPartOfX, IntegerPartOfX);
3223 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3224 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3225 // For floating-point precision of 12:
3227 // TwoToFractionalPartOfX =
3230 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3232 // 0.000107046256 error, which is 13 to 14 bits
3233 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3234 getF32Constant(DAG, 0x3da235e3));
3235 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3236 getF32Constant(DAG, 0x3e65b8f3));
3237 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3238 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3239 getF32Constant(DAG, 0x3f324b07));
3240 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3241 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3242 getF32Constant(DAG, 0x3f7ff8fd));
3243 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3245 // Add the exponent into the result in integer domain.
3246 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3247 TwoToFracPartOfX, IntegerPartOfX);
3249 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3250 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3251 // For floating-point precision of 18:
3253 // TwoToFractionalPartOfX =
3257 // (0.554906021e-1f +
3258 // (0.961591928e-2f +
3259 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3261 // error 2.47208000*10^(-7), which is better than 18 bits
3262 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3263 getF32Constant(DAG, 0x3924b03e));
3264 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3265 getF32Constant(DAG, 0x3ab24b87));
3266 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3267 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3268 getF32Constant(DAG, 0x3c1d8c17));
3269 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3270 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3271 getF32Constant(DAG, 0x3d634a1d));
3272 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3273 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3274 getF32Constant(DAG, 0x3e75fe14));
3275 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3276 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3277 getF32Constant(DAG, 0x3f317234));
3278 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3279 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3280 getF32Constant(DAG, 0x3f800000));
3281 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3284 // Add the exponent into the result in integer domain.
3285 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3286 TwoToFracPartOfX, IntegerPartOfX);
3288 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3291 // No special expansion.
3292 result = DAG.getNode(ISD::FEXP, dl,
3293 getValue(I.getArgOperand(0)).getValueType(),
3294 getValue(I.getArgOperand(0)));
3297 setValue(&I, result);
3300 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3301 /// limited-precision mode.
3303 SelectionDAGBuilder::visitLog(const CallInst &I) {
3305 DebugLoc dl = getCurDebugLoc();
3307 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3308 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3309 SDValue Op = getValue(I.getArgOperand(0));
3310 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3312 // Scale the exponent by log(2) [0.69314718f].
3313 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3314 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3315 getF32Constant(DAG, 0x3f317218));
3317 // Get the significand and build it into a floating-point number with
3319 SDValue X = GetSignificand(DAG, Op1, dl);
3321 if (LimitFloatPrecision <= 6) {
3322 // For floating-point precision of 6:
3326 // (1.4034025f - 0.23903021f * x) * x;
3328 // error 0.0034276066, which is better than 8 bits
3329 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3330 getF32Constant(DAG, 0xbe74c456));
3331 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3332 getF32Constant(DAG, 0x3fb3a2b1));
3333 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3334 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3335 getF32Constant(DAG, 0x3f949a29));
3337 result = DAG.getNode(ISD::FADD, dl,
3338 MVT::f32, LogOfExponent, LogOfMantissa);
3339 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3340 // For floating-point precision of 12:
3346 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3348 // error 0.000061011436, which is 14 bits
3349 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3350 getF32Constant(DAG, 0xbd67b6d6));
3351 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3352 getF32Constant(DAG, 0x3ee4f4b8));
3353 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3354 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3355 getF32Constant(DAG, 0x3fbc278b));
3356 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3357 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3358 getF32Constant(DAG, 0x40348e95));
3359 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3360 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3361 getF32Constant(DAG, 0x3fdef31a));
3363 result = DAG.getNode(ISD::FADD, dl,
3364 MVT::f32, LogOfExponent, LogOfMantissa);
3365 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3366 // For floating-point precision of 18:
3374 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3376 // error 0.0000023660568, which is better than 18 bits
3377 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3378 getF32Constant(DAG, 0xbc91e5ac));
3379 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3380 getF32Constant(DAG, 0x3e4350aa));
3381 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3382 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3383 getF32Constant(DAG, 0x3f60d3e3));
3384 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3385 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3386 getF32Constant(DAG, 0x4011cdf0));
3387 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3388 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3389 getF32Constant(DAG, 0x406cfd1c));
3390 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3391 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3392 getF32Constant(DAG, 0x408797cb));
3393 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3394 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3395 getF32Constant(DAG, 0x4006dcab));
3397 result = DAG.getNode(ISD::FADD, dl,
3398 MVT::f32, LogOfExponent, LogOfMantissa);
3401 // No special expansion.
3402 result = DAG.getNode(ISD::FLOG, dl,
3403 getValue(I.getArgOperand(0)).getValueType(),
3404 getValue(I.getArgOperand(0)));
3407 setValue(&I, result);
3410 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3411 /// limited-precision mode.
3413 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3415 DebugLoc dl = getCurDebugLoc();
3417 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3418 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3419 SDValue Op = getValue(I.getArgOperand(0));
3420 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3422 // Get the exponent.
3423 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3425 // Get the significand and build it into a floating-point number with
3427 SDValue X = GetSignificand(DAG, Op1, dl);
3429 // Different possible minimax approximations of significand in
3430 // floating-point for various degrees of accuracy over [1,2].
3431 if (LimitFloatPrecision <= 6) {
3432 // For floating-point precision of 6:
3434 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3436 // error 0.0049451742, which is more than 7 bits
3437 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3438 getF32Constant(DAG, 0xbeb08fe0));
3439 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3440 getF32Constant(DAG, 0x40019463));
3441 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3442 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3443 getF32Constant(DAG, 0x3fd6633d));
3445 result = DAG.getNode(ISD::FADD, dl,
3446 MVT::f32, LogOfExponent, Log2ofMantissa);
3447 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3448 // For floating-point precision of 12:
3454 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3456 // error 0.0000876136000, which is better than 13 bits
3457 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3458 getF32Constant(DAG, 0xbda7262e));
3459 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3460 getF32Constant(DAG, 0x3f25280b));
3461 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3462 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3463 getF32Constant(DAG, 0x4007b923));
3464 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3465 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3466 getF32Constant(DAG, 0x40823e2f));
3467 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3468 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3469 getF32Constant(DAG, 0x4020d29c));
3471 result = DAG.getNode(ISD::FADD, dl,
3472 MVT::f32, LogOfExponent, Log2ofMantissa);
3473 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3474 // For floating-point precision of 18:
3483 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3485 // error 0.0000018516, which is better than 18 bits
3486 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3487 getF32Constant(DAG, 0xbcd2769e));
3488 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3489 getF32Constant(DAG, 0x3e8ce0b9));
3490 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3491 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3492 getF32Constant(DAG, 0x3fa22ae7));
3493 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3494 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3495 getF32Constant(DAG, 0x40525723));
3496 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3497 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3498 getF32Constant(DAG, 0x40aaf200));
3499 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3500 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3501 getF32Constant(DAG, 0x40c39dad));
3502 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3503 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3504 getF32Constant(DAG, 0x4042902c));
3506 result = DAG.getNode(ISD::FADD, dl,
3507 MVT::f32, LogOfExponent, Log2ofMantissa);
3510 // No special expansion.
3511 result = DAG.getNode(ISD::FLOG2, dl,
3512 getValue(I.getArgOperand(0)).getValueType(),
3513 getValue(I.getArgOperand(0)));
3516 setValue(&I, result);
3519 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3520 /// limited-precision mode.
3522 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3524 DebugLoc dl = getCurDebugLoc();
3526 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3527 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3528 SDValue Op = getValue(I.getArgOperand(0));
3529 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3531 // Scale the exponent by log10(2) [0.30102999f].
3532 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3533 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3534 getF32Constant(DAG, 0x3e9a209a));
3536 // Get the significand and build it into a floating-point number with
3538 SDValue X = GetSignificand(DAG, Op1, dl);
3540 if (LimitFloatPrecision <= 6) {
3541 // For floating-point precision of 6:
3543 // Log10ofMantissa =
3545 // (0.60948995f - 0.10380950f * x) * x;
3547 // error 0.0014886165, which is 6 bits
3548 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3549 getF32Constant(DAG, 0xbdd49a13));
3550 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3551 getF32Constant(DAG, 0x3f1c0789));
3552 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3553 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3554 getF32Constant(DAG, 0x3f011300));
3556 result = DAG.getNode(ISD::FADD, dl,
3557 MVT::f32, LogOfExponent, Log10ofMantissa);
3558 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3559 // For floating-point precision of 12:
3561 // Log10ofMantissa =
3564 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3566 // error 0.00019228036, which is better than 12 bits
3567 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3568 getF32Constant(DAG, 0x3d431f31));
3569 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3570 getF32Constant(DAG, 0x3ea21fb2));
3571 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3572 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3573 getF32Constant(DAG, 0x3f6ae232));
3574 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3575 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3576 getF32Constant(DAG, 0x3f25f7c3));
3578 result = DAG.getNode(ISD::FADD, dl,
3579 MVT::f32, LogOfExponent, Log10ofMantissa);
3580 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3581 // For floating-point precision of 18:
3583 // Log10ofMantissa =
3588 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3590 // error 0.0000037995730, which is better than 18 bits
3591 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3592 getF32Constant(DAG, 0x3c5d51ce));
3593 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3594 getF32Constant(DAG, 0x3e00685a));
3595 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3596 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3597 getF32Constant(DAG, 0x3efb6798));
3598 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3599 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3600 getF32Constant(DAG, 0x3f88d192));
3601 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3602 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3603 getF32Constant(DAG, 0x3fc4316c));
3604 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3605 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3606 getF32Constant(DAG, 0x3f57ce70));
3608 result = DAG.getNode(ISD::FADD, dl,
3609 MVT::f32, LogOfExponent, Log10ofMantissa);
3612 // No special expansion.
3613 result = DAG.getNode(ISD::FLOG10, dl,
3614 getValue(I.getArgOperand(0)).getValueType(),
3615 getValue(I.getArgOperand(0)));
3618 setValue(&I, result);
3621 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3622 /// limited-precision mode.
3624 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3626 DebugLoc dl = getCurDebugLoc();
3628 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3629 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3630 SDValue Op = getValue(I.getArgOperand(0));
3632 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3634 // FractionalPartOfX = x - (float)IntegerPartOfX;
3635 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3636 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3638 // IntegerPartOfX <<= 23;
3639 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3640 DAG.getConstant(23, TLI.getPointerTy()));
3642 if (LimitFloatPrecision <= 6) {
3643 // For floating-point precision of 6:
3645 // TwoToFractionalPartOfX =
3647 // (0.735607626f + 0.252464424f * x) * x;
3649 // error 0.0144103317, which is 6 bits
3650 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3651 getF32Constant(DAG, 0x3e814304));
3652 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3653 getF32Constant(DAG, 0x3f3c50c8));
3654 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3655 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3656 getF32Constant(DAG, 0x3f7f5e7e));
3657 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3658 SDValue TwoToFractionalPartOfX =
3659 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3661 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3662 MVT::f32, TwoToFractionalPartOfX);
3663 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3664 // For floating-point precision of 12:
3666 // TwoToFractionalPartOfX =
3669 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3671 // error 0.000107046256, which is 13 to 14 bits
3672 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3673 getF32Constant(DAG, 0x3da235e3));
3674 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3675 getF32Constant(DAG, 0x3e65b8f3));
3676 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3677 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3678 getF32Constant(DAG, 0x3f324b07));
3679 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3680 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3681 getF32Constant(DAG, 0x3f7ff8fd));
3682 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3683 SDValue TwoToFractionalPartOfX =
3684 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3686 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3687 MVT::f32, TwoToFractionalPartOfX);
3688 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3689 // For floating-point precision of 18:
3691 // TwoToFractionalPartOfX =
3695 // (0.554906021e-1f +
3696 // (0.961591928e-2f +
3697 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3698 // error 2.47208000*10^(-7), which is better than 18 bits
3699 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3700 getF32Constant(DAG, 0x3924b03e));
3701 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3702 getF32Constant(DAG, 0x3ab24b87));
3703 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3704 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3705 getF32Constant(DAG, 0x3c1d8c17));
3706 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3707 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3708 getF32Constant(DAG, 0x3d634a1d));
3709 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3710 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3711 getF32Constant(DAG, 0x3e75fe14));
3712 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3713 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3714 getF32Constant(DAG, 0x3f317234));
3715 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3716 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3717 getF32Constant(DAG, 0x3f800000));
3718 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3719 SDValue TwoToFractionalPartOfX =
3720 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3722 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3723 MVT::f32, TwoToFractionalPartOfX);
3726 // No special expansion.
3727 result = DAG.getNode(ISD::FEXP2, dl,
3728 getValue(I.getArgOperand(0)).getValueType(),
3729 getValue(I.getArgOperand(0)));
3732 setValue(&I, result);
3735 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3736 /// limited-precision mode with x == 10.0f.
3738 SelectionDAGBuilder::visitPow(const CallInst &I) {
3740 const Value *Val = I.getArgOperand(0);
3741 DebugLoc dl = getCurDebugLoc();
3742 bool IsExp10 = false;
3744 if (getValue(Val).getValueType() == MVT::f32 &&
3745 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3746 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3747 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3748 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3750 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3755 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3756 SDValue Op = getValue(I.getArgOperand(1));
3758 // Put the exponent in the right bit position for later addition to the
3761 // #define LOG2OF10 3.3219281f
3762 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3763 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3764 getF32Constant(DAG, 0x40549a78));
3765 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3767 // FractionalPartOfX = x - (float)IntegerPartOfX;
3768 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3769 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3771 // IntegerPartOfX <<= 23;
3772 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3773 DAG.getConstant(23, TLI.getPointerTy()));
3775 if (LimitFloatPrecision <= 6) {
3776 // For floating-point precision of 6:
3778 // twoToFractionalPartOfX =
3780 // (0.735607626f + 0.252464424f * x) * x;
3782 // error 0.0144103317, which is 6 bits
3783 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3784 getF32Constant(DAG, 0x3e814304));
3785 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3786 getF32Constant(DAG, 0x3f3c50c8));
3787 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3788 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3789 getF32Constant(DAG, 0x3f7f5e7e));
3790 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3791 SDValue TwoToFractionalPartOfX =
3792 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3794 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3795 MVT::f32, TwoToFractionalPartOfX);
3796 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3797 // For floating-point precision of 12:
3799 // TwoToFractionalPartOfX =
3802 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3804 // error 0.000107046256, which is 13 to 14 bits
3805 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3806 getF32Constant(DAG, 0x3da235e3));
3807 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3808 getF32Constant(DAG, 0x3e65b8f3));
3809 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3810 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3811 getF32Constant(DAG, 0x3f324b07));
3812 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3813 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3814 getF32Constant(DAG, 0x3f7ff8fd));
3815 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3816 SDValue TwoToFractionalPartOfX =
3817 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3819 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3820 MVT::f32, TwoToFractionalPartOfX);
3821 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3822 // For floating-point precision of 18:
3824 // TwoToFractionalPartOfX =
3828 // (0.554906021e-1f +
3829 // (0.961591928e-2f +
3830 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3831 // error 2.47208000*10^(-7), which is better than 18 bits
3832 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3833 getF32Constant(DAG, 0x3924b03e));
3834 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3835 getF32Constant(DAG, 0x3ab24b87));
3836 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3837 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3838 getF32Constant(DAG, 0x3c1d8c17));
3839 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3840 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3841 getF32Constant(DAG, 0x3d634a1d));
3842 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3843 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3844 getF32Constant(DAG, 0x3e75fe14));
3845 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3846 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3847 getF32Constant(DAG, 0x3f317234));
3848 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3849 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3850 getF32Constant(DAG, 0x3f800000));
3851 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3852 SDValue TwoToFractionalPartOfX =
3853 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3855 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3856 MVT::f32, TwoToFractionalPartOfX);
3859 // No special expansion.
3860 result = DAG.getNode(ISD::FPOW, dl,
3861 getValue(I.getArgOperand(0)).getValueType(),
3862 getValue(I.getArgOperand(0)),
3863 getValue(I.getArgOperand(1)));
3866 setValue(&I, result);
3870 /// ExpandPowI - Expand a llvm.powi intrinsic.
3871 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3872 SelectionDAG &DAG) {
3873 // If RHS is a constant, we can expand this out to a multiplication tree,
3874 // otherwise we end up lowering to a call to __powidf2 (for example). When
3875 // optimizing for size, we only want to do this if the expansion would produce
3876 // a small number of multiplies, otherwise we do the full expansion.
3877 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3878 // Get the exponent as a positive value.
3879 unsigned Val = RHSC->getSExtValue();
3880 if ((int)Val < 0) Val = -Val;
3882 // powi(x, 0) -> 1.0
3884 return DAG.getConstantFP(1.0, LHS.getValueType());
3886 const Function *F = DAG.getMachineFunction().getFunction();
3887 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3888 // If optimizing for size, don't insert too many multiplies. This
3889 // inserts up to 5 multiplies.
3890 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3891 // We use the simple binary decomposition method to generate the multiply
3892 // sequence. There are more optimal ways to do this (for example,
3893 // powi(x,15) generates one more multiply than it should), but this has
3894 // the benefit of being both really simple and much better than a libcall.
3895 SDValue Res; // Logically starts equal to 1.0
3896 SDValue CurSquare = LHS;
3900 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3902 Res = CurSquare; // 1.0*CurSquare.
3905 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3906 CurSquare, CurSquare);
3910 // If the original was negative, invert the result, producing 1/(x*x*x).
3911 if (RHSC->getSExtValue() < 0)
3912 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3913 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3918 // Otherwise, expand to a libcall.
3919 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3922 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3923 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3924 /// At the end of instruction selection, they will be inserted to the entry BB.
3926 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
3929 if (!isa<Argument>(V))
3932 MachineFunction &MF = DAG.getMachineFunction();
3933 // Ignore inlined function arguments here.
3934 DIVariable DV(Variable);
3935 if (DV.isInlinedFnArgument(MF.getFunction()))
3938 MachineBasicBlock *MBB = FuncInfo.MBB;
3939 if (MBB != &MF.front())
3943 if (N.getOpcode() == ISD::CopyFromReg) {
3944 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3945 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3946 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3947 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3954 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
3955 if (VMI == FuncInfo.ValueMap.end())
3960 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
3961 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
3962 TII->get(TargetOpcode::DBG_VALUE))
3963 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
3964 FuncInfo.ArgDbgValues.push_back(&*MIB);
3968 // VisualStudio defines setjmp as _setjmp
3969 #if defined(_MSC_VER) && defined(setjmp)
3970 #define setjmp_undefined_for_visual_studio
3974 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3975 /// we want to emit this as a call to a named external function, return the name
3976 /// otherwise lower it and return null.
3978 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
3979 DebugLoc dl = getCurDebugLoc();
3982 switch (Intrinsic) {
3984 // By default, turn this into a target intrinsic node.
3985 visitTargetIntrinsic(I, Intrinsic);
3987 case Intrinsic::vastart: visitVAStart(I); return 0;
3988 case Intrinsic::vaend: visitVAEnd(I); return 0;
3989 case Intrinsic::vacopy: visitVACopy(I); return 0;
3990 case Intrinsic::returnaddress:
3991 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
3992 getValue(I.getArgOperand(0))));
3994 case Intrinsic::frameaddress:
3995 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
3996 getValue(I.getArgOperand(0))));
3998 case Intrinsic::setjmp:
3999 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4000 case Intrinsic::longjmp:
4001 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4002 case Intrinsic::memcpy: {
4003 // Assert for address < 256 since we support only user defined address
4005 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4007 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4009 "Unknown address space");
4010 SDValue Op1 = getValue(I.getArgOperand(0));
4011 SDValue Op2 = getValue(I.getArgOperand(1));
4012 SDValue Op3 = getValue(I.getArgOperand(2));
4013 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4014 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4015 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4016 I.getArgOperand(0), 0, I.getArgOperand(1), 0));
4019 case Intrinsic::memset: {
4020 // Assert for address < 256 since we support only user defined address
4022 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4024 "Unknown address space");
4025 SDValue Op1 = getValue(I.getArgOperand(0));
4026 SDValue Op2 = getValue(I.getArgOperand(1));
4027 SDValue Op3 = getValue(I.getArgOperand(2));
4028 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4029 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4030 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4031 I.getArgOperand(0), 0));
4034 case Intrinsic::memmove: {
4035 // Assert for address < 256 since we support only user defined address
4037 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4039 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4041 "Unknown address space");
4042 SDValue Op1 = getValue(I.getArgOperand(0));
4043 SDValue Op2 = getValue(I.getArgOperand(1));
4044 SDValue Op3 = getValue(I.getArgOperand(2));
4045 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4046 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4048 // If the source and destination are known to not be aliases, we can
4049 // lower memmove as memcpy.
4050 uint64_t Size = -1ULL;
4051 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4052 Size = C->getZExtValue();
4053 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) ==
4054 AliasAnalysis::NoAlias) {
4055 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4056 false, I.getArgOperand(0), 0,
4057 I.getArgOperand(1), 0));
4061 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4062 I.getArgOperand(0), 0, I.getArgOperand(1), 0));
4065 case Intrinsic::dbg_declare: {
4066 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4067 if (!DIVariable(DI.getVariable()).Verify())
4070 MDNode *Variable = DI.getVariable();
4071 // Parameters are handled specially.
4073 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4074 const Value *Address = DI.getAddress();
4077 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4078 Address = BCI->getOperand(0);
4079 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4081 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4082 // but do not always have a corresponding SDNode built. The SDNodeOrder
4083 // absolute, but not relative, values are different depending on whether
4084 // debug info exists.
4086 SDValue &N = NodeMap[Address];
4089 if (isParameter && !AI) {
4090 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4092 // Byval parameter. We have a frame index at this point.
4093 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4094 0, dl, SDNodeOrder);
4096 // Can't do anything with other non-AI cases yet. This might be a
4097 // parameter of a callee function that got inlined, for example.
4100 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4101 0, dl, SDNodeOrder);
4103 // Can't do anything with other non-AI cases yet.
4105 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4107 // This isn't useful, but it shows what we're missing.
4108 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4109 0, dl, SDNodeOrder);
4110 DAG.AddDbgValue(SDV, 0, isParameter);
4114 case Intrinsic::dbg_value: {
4115 const DbgValueInst &DI = cast<DbgValueInst>(I);
4116 if (!DIVariable(DI.getVariable()).Verify())
4119 MDNode *Variable = DI.getVariable();
4120 uint64_t Offset = DI.getOffset();
4121 const Value *V = DI.getValue();
4125 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4126 // but do not always have a corresponding SDNode built. The SDNodeOrder
4127 // absolute, but not relative, values are different depending on whether
4128 // debug info exists.
4131 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4132 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4133 DAG.AddDbgValue(SDV, 0, false);
4135 bool createUndef = false;
4136 // Do not use getValue() in here; we don't want to generate code at
4137 // this point if it hasn't been done yet.
4138 SDValue N = NodeMap[V];
4139 if (!N.getNode() && isa<Argument>(V))
4140 // Check unused arguments map.
4141 N = UnusedArgNodeMap[V];
4143 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4144 SDV = DAG.getDbgValue(Variable, N.getNode(),
4145 N.getResNo(), Offset, dl, SDNodeOrder);
4146 DAG.AddDbgValue(SDV, N.getNode(), false);
4148 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4149 // Do not call getValue(V) yet, as we don't want to generate code.
4150 // Remember it for later.
4151 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4152 DanglingDebugInfoMap[V] = DDI;
4156 // We may expand this to cover more cases. One case where we have no
4157 // data available is an unreferenced parameter; we need this fallback.
4158 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
4159 Offset, dl, SDNodeOrder);
4160 DAG.AddDbgValue(SDV, 0, false);
4164 // Build a debug info table entry.
4165 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4166 V = BCI->getOperand(0);
4167 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4168 // Don't handle byval struct arguments or VLAs, for example.
4171 DenseMap<const AllocaInst*, int>::iterator SI =
4172 FuncInfo.StaticAllocaMap.find(AI);
4173 if (SI == FuncInfo.StaticAllocaMap.end())
4175 int FI = SI->second;
4177 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4178 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4179 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4182 case Intrinsic::eh_exception: {
4183 // Insert the EXCEPTIONADDR instruction.
4184 assert(FuncInfo.MBB->isLandingPad() &&
4185 "Call to eh.exception not in landing pad!");
4186 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4188 Ops[0] = DAG.getRoot();
4189 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4191 DAG.setRoot(Op.getValue(1));
4195 case Intrinsic::eh_selector: {
4196 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4197 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4198 if (CallMBB->isLandingPad())
4199 AddCatchInfo(I, &MMI, CallMBB);
4202 FuncInfo.CatchInfoLost.insert(&I);
4204 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4205 unsigned Reg = TLI.getExceptionSelectorRegister();
4206 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4209 // Insert the EHSELECTION instruction.
4210 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4212 Ops[0] = getValue(I.getArgOperand(0));
4214 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4215 DAG.setRoot(Op.getValue(1));
4216 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4220 case Intrinsic::eh_typeid_for: {
4221 // Find the type id for the given typeinfo.
4222 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4223 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4224 Res = DAG.getConstant(TypeID, MVT::i32);
4229 case Intrinsic::eh_return_i32:
4230 case Intrinsic::eh_return_i64:
4231 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4232 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4235 getValue(I.getArgOperand(0)),
4236 getValue(I.getArgOperand(1))));
4238 case Intrinsic::eh_unwind_init:
4239 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4241 case Intrinsic::eh_dwarf_cfa: {
4242 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4243 TLI.getPointerTy());
4244 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4246 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4247 TLI.getPointerTy()),
4249 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4251 DAG.getConstant(0, TLI.getPointerTy()));
4252 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4256 case Intrinsic::eh_sjlj_callsite: {
4257 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4258 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4259 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4260 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4262 MMI.setCurrentCallSite(CI->getZExtValue());
4265 case Intrinsic::eh_sjlj_setjmp: {
4266 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4267 getValue(I.getArgOperand(0))));
4270 case Intrinsic::eh_sjlj_longjmp: {
4271 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4273 getValue(I.getArgOperand(0))));
4277 case Intrinsic::convertff:
4278 case Intrinsic::convertfsi:
4279 case Intrinsic::convertfui:
4280 case Intrinsic::convertsif:
4281 case Intrinsic::convertuif:
4282 case Intrinsic::convertss:
4283 case Intrinsic::convertsu:
4284 case Intrinsic::convertus:
4285 case Intrinsic::convertuu: {
4286 ISD::CvtCode Code = ISD::CVT_INVALID;
4287 switch (Intrinsic) {
4288 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4289 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4290 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4291 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4292 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4293 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4294 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4295 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4296 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4298 EVT DestVT = TLI.getValueType(I.getType());
4299 const Value *Op1 = I.getArgOperand(0);
4300 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4301 DAG.getValueType(DestVT),
4302 DAG.getValueType(getValue(Op1).getValueType()),
4303 getValue(I.getArgOperand(1)),
4304 getValue(I.getArgOperand(2)),
4309 case Intrinsic::sqrt:
4310 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4311 getValue(I.getArgOperand(0)).getValueType(),
4312 getValue(I.getArgOperand(0))));
4314 case Intrinsic::powi:
4315 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4316 getValue(I.getArgOperand(1)), DAG));
4318 case Intrinsic::sin:
4319 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4320 getValue(I.getArgOperand(0)).getValueType(),
4321 getValue(I.getArgOperand(0))));
4323 case Intrinsic::cos:
4324 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4325 getValue(I.getArgOperand(0)).getValueType(),
4326 getValue(I.getArgOperand(0))));
4328 case Intrinsic::log:
4331 case Intrinsic::log2:
4334 case Intrinsic::log10:
4337 case Intrinsic::exp:
4340 case Intrinsic::exp2:
4343 case Intrinsic::pow:
4346 case Intrinsic::convert_to_fp16:
4347 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4348 MVT::i16, getValue(I.getArgOperand(0))));
4350 case Intrinsic::convert_from_fp16:
4351 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4352 MVT::f32, getValue(I.getArgOperand(0))));
4354 case Intrinsic::pcmarker: {
4355 SDValue Tmp = getValue(I.getArgOperand(0));
4356 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4359 case Intrinsic::readcyclecounter: {
4360 SDValue Op = getRoot();
4361 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4362 DAG.getVTList(MVT::i64, MVT::Other),
4365 DAG.setRoot(Res.getValue(1));
4368 case Intrinsic::bswap:
4369 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4370 getValue(I.getArgOperand(0)).getValueType(),
4371 getValue(I.getArgOperand(0))));
4373 case Intrinsic::cttz: {
4374 SDValue Arg = getValue(I.getArgOperand(0));
4375 EVT Ty = Arg.getValueType();
4376 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4379 case Intrinsic::ctlz: {
4380 SDValue Arg = getValue(I.getArgOperand(0));
4381 EVT Ty = Arg.getValueType();
4382 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4385 case Intrinsic::ctpop: {
4386 SDValue Arg = getValue(I.getArgOperand(0));
4387 EVT Ty = Arg.getValueType();
4388 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4391 case Intrinsic::stacksave: {
4392 SDValue Op = getRoot();
4393 Res = DAG.getNode(ISD::STACKSAVE, dl,
4394 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4396 DAG.setRoot(Res.getValue(1));
4399 case Intrinsic::stackrestore: {
4400 Res = getValue(I.getArgOperand(0));
4401 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4404 case Intrinsic::stackprotector: {
4405 // Emit code into the DAG to store the stack guard onto the stack.
4406 MachineFunction &MF = DAG.getMachineFunction();
4407 MachineFrameInfo *MFI = MF.getFrameInfo();
4408 EVT PtrTy = TLI.getPointerTy();
4410 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4411 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4413 int FI = FuncInfo.StaticAllocaMap[Slot];
4414 MFI->setStackProtectorIndex(FI);
4416 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4418 // Store the stack protector onto the stack.
4419 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4420 PseudoSourceValue::getFixedStack(FI),
4426 case Intrinsic::objectsize: {
4427 // If we don't know by now, we're never going to know.
4428 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4430 assert(CI && "Non-constant type in __builtin_object_size?");
4432 SDValue Arg = getValue(I.getCalledValue());
4433 EVT Ty = Arg.getValueType();
4436 Res = DAG.getConstant(-1ULL, Ty);
4438 Res = DAG.getConstant(0, Ty);
4443 case Intrinsic::var_annotation:
4444 // Discard annotate attributes
4447 case Intrinsic::init_trampoline: {
4448 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4452 Ops[1] = getValue(I.getArgOperand(0));
4453 Ops[2] = getValue(I.getArgOperand(1));
4454 Ops[3] = getValue(I.getArgOperand(2));
4455 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4456 Ops[5] = DAG.getSrcValue(F);
4458 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4459 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4463 DAG.setRoot(Res.getValue(1));
4466 case Intrinsic::gcroot:
4468 const Value *Alloca = I.getArgOperand(0);
4469 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4471 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4472 GFI->addStackRoot(FI->getIndex(), TypeMap);
4475 case Intrinsic::gcread:
4476 case Intrinsic::gcwrite:
4477 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4479 case Intrinsic::flt_rounds:
4480 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4482 case Intrinsic::trap:
4483 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4485 case Intrinsic::uadd_with_overflow:
4486 return implVisitAluOverflow(I, ISD::UADDO);
4487 case Intrinsic::sadd_with_overflow:
4488 return implVisitAluOverflow(I, ISD::SADDO);
4489 case Intrinsic::usub_with_overflow:
4490 return implVisitAluOverflow(I, ISD::USUBO);
4491 case Intrinsic::ssub_with_overflow:
4492 return implVisitAluOverflow(I, ISD::SSUBO);
4493 case Intrinsic::umul_with_overflow:
4494 return implVisitAluOverflow(I, ISD::UMULO);
4495 case Intrinsic::smul_with_overflow:
4496 return implVisitAluOverflow(I, ISD::SMULO);
4498 case Intrinsic::prefetch: {
4501 Ops[1] = getValue(I.getArgOperand(0));
4502 Ops[2] = getValue(I.getArgOperand(1));
4503 Ops[3] = getValue(I.getArgOperand(2));
4504 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4508 case Intrinsic::memory_barrier: {
4511 for (int x = 1; x < 6; ++x)
4512 Ops[x] = getValue(I.getArgOperand(x - 1));
4514 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4517 case Intrinsic::atomic_cmp_swap: {
4518 SDValue Root = getRoot();
4520 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4521 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4523 getValue(I.getArgOperand(0)),
4524 getValue(I.getArgOperand(1)),
4525 getValue(I.getArgOperand(2)),
4526 I.getArgOperand(0));
4528 DAG.setRoot(L.getValue(1));
4531 case Intrinsic::atomic_load_add:
4532 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4533 case Intrinsic::atomic_load_sub:
4534 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4535 case Intrinsic::atomic_load_or:
4536 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4537 case Intrinsic::atomic_load_xor:
4538 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4539 case Intrinsic::atomic_load_and:
4540 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4541 case Intrinsic::atomic_load_nand:
4542 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4543 case Intrinsic::atomic_load_max:
4544 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4545 case Intrinsic::atomic_load_min:
4546 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4547 case Intrinsic::atomic_load_umin:
4548 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4549 case Intrinsic::atomic_load_umax:
4550 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4551 case Intrinsic::atomic_swap:
4552 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4554 case Intrinsic::invariant_start:
4555 case Intrinsic::lifetime_start:
4556 // Discard region information.
4557 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4559 case Intrinsic::invariant_end:
4560 case Intrinsic::lifetime_end:
4561 // Discard region information.
4566 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4568 MachineBasicBlock *LandingPad) {
4569 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4570 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4571 const Type *RetTy = FTy->getReturnType();
4572 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4573 MCSymbol *BeginLabel = 0;
4575 TargetLowering::ArgListTy Args;
4576 TargetLowering::ArgListEntry Entry;
4577 Args.reserve(CS.arg_size());
4579 // Check whether the function can return without sret-demotion.
4580 SmallVector<ISD::OutputArg, 4> Outs;
4581 SmallVector<uint64_t, 4> Offsets;
4582 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4583 Outs, TLI, &Offsets);
4585 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4586 FTy->isVarArg(), Outs, FTy->getContext());
4588 SDValue DemoteStackSlot;
4590 if (!CanLowerReturn) {
4591 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4592 FTy->getReturnType());
4593 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4594 FTy->getReturnType());
4595 MachineFunction &MF = DAG.getMachineFunction();
4596 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4597 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4599 DemoteStackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4600 Entry.Node = DemoteStackSlot;
4601 Entry.Ty = StackSlotPtrType;
4602 Entry.isSExt = false;
4603 Entry.isZExt = false;
4604 Entry.isInReg = false;
4605 Entry.isSRet = true;
4606 Entry.isNest = false;
4607 Entry.isByVal = false;
4608 Entry.Alignment = Align;
4609 Args.push_back(Entry);
4610 RetTy = Type::getVoidTy(FTy->getContext());
4613 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4615 SDValue ArgNode = getValue(*i);
4616 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4618 unsigned attrInd = i - CS.arg_begin() + 1;
4619 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4620 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4621 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4622 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4623 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4624 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4625 Entry.Alignment = CS.getParamAlignment(attrInd);
4626 Args.push_back(Entry);
4630 // Insert a label before the invoke call to mark the try range. This can be
4631 // used to detect deletion of the invoke via the MachineModuleInfo.
4632 BeginLabel = MMI.getContext().CreateTempSymbol();
4634 // For SjLj, keep track of which landing pads go with which invokes
4635 // so as to maintain the ordering of pads in the LSDA.
4636 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4637 if (CallSiteIndex) {
4638 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4639 // Now that the call site is handled, stop tracking it.
4640 MMI.setCurrentCallSite(0);
4643 // Both PendingLoads and PendingExports must be flushed here;
4644 // this call might not return.
4646 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4649 // Check if target-independent constraints permit a tail call here.
4650 // Target-dependent constraints are checked within TLI.LowerCallTo.
4652 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4655 std::pair<SDValue,SDValue> Result =
4656 TLI.LowerCallTo(getRoot(), RetTy,
4657 CS.paramHasAttr(0, Attribute::SExt),
4658 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4659 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4660 CS.getCallingConv(),
4662 !CS.getInstruction()->use_empty(),
4663 Callee, Args, DAG, getCurDebugLoc());
4664 assert((isTailCall || Result.second.getNode()) &&
4665 "Non-null chain expected with non-tail call!");
4666 assert((Result.second.getNode() || !Result.first.getNode()) &&
4667 "Null value expected with tail call!");
4668 if (Result.first.getNode()) {
4669 setValue(CS.getInstruction(), Result.first);
4670 } else if (!CanLowerReturn && Result.second.getNode()) {
4671 // The instruction result is the result of loading from the
4672 // hidden sret parameter.
4673 SmallVector<EVT, 1> PVTs;
4674 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4676 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4677 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4678 EVT PtrVT = PVTs[0];
4679 unsigned NumValues = Outs.size();
4680 SmallVector<SDValue, 4> Values(NumValues);
4681 SmallVector<SDValue, 4> Chains(NumValues);
4683 for (unsigned i = 0; i < NumValues; ++i) {
4684 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4686 DAG.getConstant(Offsets[i], PtrVT));
4687 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4688 Add, NULL, Offsets[i], false, false, 1);
4690 Chains[i] = L.getValue(1);
4693 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4694 MVT::Other, &Chains[0], NumValues);
4695 PendingLoads.push_back(Chain);
4697 // Collect the legal value parts into potentially illegal values
4698 // that correspond to the original function's return values.
4699 SmallVector<EVT, 4> RetTys;
4700 RetTy = FTy->getReturnType();
4701 ComputeValueVTs(TLI, RetTy, RetTys);
4702 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4703 SmallVector<SDValue, 4> ReturnValues;
4704 unsigned CurReg = 0;
4705 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4707 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4708 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4710 SDValue ReturnValue =
4711 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4712 RegisterVT, VT, AssertOp);
4713 ReturnValues.push_back(ReturnValue);
4717 setValue(CS.getInstruction(),
4718 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4719 DAG.getVTList(&RetTys[0], RetTys.size()),
4720 &ReturnValues[0], ReturnValues.size()));
4724 // As a special case, a null chain means that a tail call has been emitted and
4725 // the DAG root is already updated.
4726 if (Result.second.getNode())
4727 DAG.setRoot(Result.second);
4732 // Insert a label at the end of the invoke call to mark the try range. This
4733 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4734 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4735 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4737 // Inform MachineModuleInfo of range.
4738 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4742 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4743 /// value is equal or not-equal to zero.
4744 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4745 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4747 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4748 if (IC->isEquality())
4749 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4750 if (C->isNullValue())
4752 // Unknown instruction.
4758 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4760 SelectionDAGBuilder &Builder) {
4762 // Check to see if this load can be trivially constant folded, e.g. if the
4763 // input is from a string literal.
4764 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4765 // Cast pointer to the type we really want to load.
4766 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4767 PointerType::getUnqual(LoadTy));
4769 if (const Constant *LoadCst =
4770 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4772 return Builder.getValue(LoadCst);
4775 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4776 // still constant memory, the input chain can be the entry node.
4778 bool ConstantMemory = false;
4780 // Do not serialize (non-volatile) loads of constant memory with anything.
4781 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4782 Root = Builder.DAG.getEntryNode();
4783 ConstantMemory = true;
4785 // Do not serialize non-volatile loads against each other.
4786 Root = Builder.DAG.getRoot();
4789 SDValue Ptr = Builder.getValue(PtrVal);
4790 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4791 Ptr, PtrVal /*SrcValue*/, 0/*SVOffset*/,
4793 false /*nontemporal*/, 1 /* align=1 */);
4795 if (!ConstantMemory)
4796 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4801 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4802 /// If so, return true and lower it, otherwise return false and it will be
4803 /// lowered like a normal call.
4804 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4805 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4806 if (I.getNumArgOperands() != 3)
4809 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
4810 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4811 !I.getArgOperand(2)->getType()->isIntegerTy() ||
4812 !I.getType()->isIntegerTy())
4815 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
4817 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4818 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4819 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4820 bool ActuallyDoIt = true;
4823 switch (Size->getZExtValue()) {
4825 LoadVT = MVT::Other;
4827 ActuallyDoIt = false;
4831 LoadTy = Type::getInt16Ty(Size->getContext());
4835 LoadTy = Type::getInt32Ty(Size->getContext());
4839 LoadTy = Type::getInt64Ty(Size->getContext());
4843 LoadVT = MVT::v4i32;
4844 LoadTy = Type::getInt32Ty(Size->getContext());
4845 LoadTy = VectorType::get(LoadTy, 4);
4850 // This turns into unaligned loads. We only do this if the target natively
4851 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4852 // we'll only produce a small number of byte loads.
4854 // Require that we can find a legal MVT, and only do this if the target
4855 // supports unaligned loads of that type. Expanding into byte loads would
4857 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4858 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4859 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4860 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4861 ActuallyDoIt = false;
4865 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4866 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4868 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4870 EVT CallVT = TLI.getValueType(I.getType(), true);
4871 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4881 void SelectionDAGBuilder::visitCall(const CallInst &I) {
4882 // Handle inline assembly differently.
4883 if (isa<InlineAsm>(I.getCalledValue())) {
4888 const char *RenameFn = 0;
4889 if (Function *F = I.getCalledFunction()) {
4890 if (F->isDeclaration()) {
4891 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
4892 if (unsigned IID = II->getIntrinsicID(F)) {
4893 RenameFn = visitIntrinsicCall(I, IID);
4898 if (unsigned IID = F->getIntrinsicID()) {
4899 RenameFn = visitIntrinsicCall(I, IID);
4905 // Check for well-known libc/libm calls. If the function is internal, it
4906 // can't be a library call.
4907 if (!F->hasLocalLinkage() && F->hasName()) {
4908 StringRef Name = F->getName();
4909 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
4910 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
4911 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4912 I.getType() == I.getArgOperand(0)->getType() &&
4913 I.getType() == I.getArgOperand(1)->getType()) {
4914 SDValue LHS = getValue(I.getArgOperand(0));
4915 SDValue RHS = getValue(I.getArgOperand(1));
4916 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
4917 LHS.getValueType(), LHS, RHS));
4920 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
4921 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4922 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4923 I.getType() == I.getArgOperand(0)->getType()) {
4924 SDValue Tmp = getValue(I.getArgOperand(0));
4925 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
4926 Tmp.getValueType(), Tmp));
4929 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
4930 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4931 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4932 I.getType() == I.getArgOperand(0)->getType() &&
4933 I.onlyReadsMemory()) {
4934 SDValue Tmp = getValue(I.getArgOperand(0));
4935 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
4936 Tmp.getValueType(), Tmp));
4939 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
4940 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4941 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4942 I.getType() == I.getArgOperand(0)->getType() &&
4943 I.onlyReadsMemory()) {
4944 SDValue Tmp = getValue(I.getArgOperand(0));
4945 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
4946 Tmp.getValueType(), Tmp));
4949 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
4950 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
4951 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
4952 I.getType() == I.getArgOperand(0)->getType() &&
4953 I.onlyReadsMemory()) {
4954 SDValue Tmp = getValue(I.getArgOperand(0));
4955 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
4956 Tmp.getValueType(), Tmp));
4959 } else if (Name == "memcmp") {
4960 if (visitMemCmpCall(I))
4968 Callee = getValue(I.getCalledValue());
4970 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
4972 // Check if we can potentially perform a tail call. More detailed checking is
4973 // be done within LowerCallTo, after more information about the call is known.
4974 LowerCallTo(&I, Callee, I.isTailCall());
4979 /// AsmOperandInfo - This contains information for each constraint that we are
4981 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
4982 public TargetLowering::AsmOperandInfo {
4984 /// CallOperand - If this is the result output operand or a clobber
4985 /// this is null, otherwise it is the incoming operand to the CallInst.
4986 /// This gets modified as the asm is processed.
4987 SDValue CallOperand;
4989 /// AssignedRegs - If this is a register or register class operand, this
4990 /// contains the set of register corresponding to the operand.
4991 RegsForValue AssignedRegs;
4993 explicit SDISelAsmOperandInfo(const InlineAsm::ConstraintInfo &info)
4994 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
4997 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
4998 /// busy in OutputRegs/InputRegs.
4999 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5000 std::set<unsigned> &OutputRegs,
5001 std::set<unsigned> &InputRegs,
5002 const TargetRegisterInfo &TRI) const {
5004 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5005 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5008 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5009 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5013 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5014 /// corresponds to. If there is no Value* for this operand, it returns
5016 EVT getCallOperandValEVT(LLVMContext &Context,
5017 const TargetLowering &TLI,
5018 const TargetData *TD) const {
5019 if (CallOperandVal == 0) return MVT::Other;
5021 if (isa<BasicBlock>(CallOperandVal))
5022 return TLI.getPointerTy();
5024 const llvm::Type *OpTy = CallOperandVal->getType();
5026 // If this is an indirect operand, the operand is a pointer to the
5029 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5031 report_fatal_error("Indirect operand for inline asm not a pointer!");
5032 OpTy = PtrTy->getElementType();
5035 // If OpTy is not a single value, it may be a struct/union that we
5036 // can tile with integers.
5037 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5038 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5047 OpTy = IntegerType::get(Context, BitSize);
5052 return TLI.getValueType(OpTy, true);
5056 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5058 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5059 const TargetRegisterInfo &TRI) {
5060 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5062 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5063 for (; *Aliases; ++Aliases)
5064 Regs.insert(*Aliases);
5068 } // end llvm namespace.
5070 /// isAllocatableRegister - If the specified register is safe to allocate,
5071 /// i.e. it isn't a stack pointer or some other special register, return the
5072 /// register class for the register. Otherwise, return null.
5073 static const TargetRegisterClass *
5074 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5075 const TargetLowering &TLI,
5076 const TargetRegisterInfo *TRI) {
5077 EVT FoundVT = MVT::Other;
5078 const TargetRegisterClass *FoundRC = 0;
5079 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5080 E = TRI->regclass_end(); RCI != E; ++RCI) {
5081 EVT ThisVT = MVT::Other;
5083 const TargetRegisterClass *RC = *RCI;
5084 // If none of the value types for this register class are valid, we
5085 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5086 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5088 if (TLI.isTypeLegal(*I)) {
5089 // If we have already found this register in a different register class,
5090 // choose the one with the largest VT specified. For example, on
5091 // PowerPC, we favor f64 register classes over f32.
5092 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5099 if (ThisVT == MVT::Other) continue;
5101 // NOTE: This isn't ideal. In particular, this might allocate the
5102 // frame pointer in functions that need it (due to them not being taken
5103 // out of allocation, because a variable sized allocation hasn't been seen
5104 // yet). This is a slight code pessimization, but should still work.
5105 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5106 E = RC->allocation_order_end(MF); I != E; ++I)
5108 // We found a matching register class. Keep looking at others in case
5109 // we find one with larger registers that this physreg is also in.
5118 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5119 /// specified operand. We prefer to assign virtual registers, to allow the
5120 /// register allocator to handle the assignment process. However, if the asm
5121 /// uses features that we can't model on machineinstrs, we have SDISel do the
5122 /// allocation. This produces generally horrible, but correct, code.
5124 /// OpInfo describes the operand.
5125 /// Input and OutputRegs are the set of already allocated physical registers.
5127 void SelectionDAGBuilder::
5128 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5129 std::set<unsigned> &OutputRegs,
5130 std::set<unsigned> &InputRegs) {
5131 LLVMContext &Context = FuncInfo.Fn->getContext();
5133 // Compute whether this value requires an input register, an output register,
5135 bool isOutReg = false;
5136 bool isInReg = false;
5137 switch (OpInfo.Type) {
5138 case InlineAsm::isOutput:
5141 // If there is an input constraint that matches this, we need to reserve
5142 // the input register so no other inputs allocate to it.
5143 isInReg = OpInfo.hasMatchingInput();
5145 case InlineAsm::isInput:
5149 case InlineAsm::isClobber:
5156 MachineFunction &MF = DAG.getMachineFunction();
5157 SmallVector<unsigned, 4> Regs;
5159 // If this is a constraint for a single physreg, or a constraint for a
5160 // register class, find it.
5161 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5162 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5163 OpInfo.ConstraintVT);
5165 unsigned NumRegs = 1;
5166 if (OpInfo.ConstraintVT != MVT::Other) {
5167 // If this is a FP input in an integer register (or visa versa) insert a bit
5168 // cast of the input value. More generally, handle any case where the input
5169 // value disagrees with the register class we plan to stick this in.
5170 if (OpInfo.Type == InlineAsm::isInput &&
5171 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5172 // Try to convert to the first EVT that the reg class contains. If the
5173 // types are identical size, use a bitcast to convert (e.g. two differing
5175 EVT RegVT = *PhysReg.second->vt_begin();
5176 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5177 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5178 RegVT, OpInfo.CallOperand);
5179 OpInfo.ConstraintVT = RegVT;
5180 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5181 // If the input is a FP value and we want it in FP registers, do a
5182 // bitcast to the corresponding integer type. This turns an f64 value
5183 // into i64, which can be passed with two i32 values on a 32-bit
5185 RegVT = EVT::getIntegerVT(Context,
5186 OpInfo.ConstraintVT.getSizeInBits());
5187 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5188 RegVT, OpInfo.CallOperand);
5189 OpInfo.ConstraintVT = RegVT;
5193 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5197 EVT ValueVT = OpInfo.ConstraintVT;
5199 // If this is a constraint for a specific physical register, like {r17},
5201 if (unsigned AssignedReg = PhysReg.first) {
5202 const TargetRegisterClass *RC = PhysReg.second;
5203 if (OpInfo.ConstraintVT == MVT::Other)
5204 ValueVT = *RC->vt_begin();
5206 // Get the actual register value type. This is important, because the user
5207 // may have asked for (e.g.) the AX register in i32 type. We need to
5208 // remember that AX is actually i16 to get the right extension.
5209 RegVT = *RC->vt_begin();
5211 // This is a explicit reference to a physical register.
5212 Regs.push_back(AssignedReg);
5214 // If this is an expanded reference, add the rest of the regs to Regs.
5216 TargetRegisterClass::iterator I = RC->begin();
5217 for (; *I != AssignedReg; ++I)
5218 assert(I != RC->end() && "Didn't find reg!");
5220 // Already added the first reg.
5222 for (; NumRegs; --NumRegs, ++I) {
5223 assert(I != RC->end() && "Ran out of registers to allocate!");
5228 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5229 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5230 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5234 // Otherwise, if this was a reference to an LLVM register class, create vregs
5235 // for this reference.
5236 if (const TargetRegisterClass *RC = PhysReg.second) {
5237 RegVT = *RC->vt_begin();
5238 if (OpInfo.ConstraintVT == MVT::Other)
5241 // Create the appropriate number of virtual registers.
5242 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5243 for (; NumRegs; --NumRegs)
5244 Regs.push_back(RegInfo.createVirtualRegister(RC));
5246 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5250 // This is a reference to a register class that doesn't directly correspond
5251 // to an LLVM register class. Allocate NumRegs consecutive, available,
5252 // registers from the class.
5253 std::vector<unsigned> RegClassRegs
5254 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5255 OpInfo.ConstraintVT);
5257 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5258 unsigned NumAllocated = 0;
5259 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5260 unsigned Reg = RegClassRegs[i];
5261 // See if this register is available.
5262 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5263 (isInReg && InputRegs.count(Reg))) { // Already used.
5264 // Make sure we find consecutive registers.
5269 // Check to see if this register is allocatable (i.e. don't give out the
5271 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5272 if (!RC) { // Couldn't allocate this register.
5273 // Reset NumAllocated to make sure we return consecutive registers.
5278 // Okay, this register is good, we can use it.
5281 // If we allocated enough consecutive registers, succeed.
5282 if (NumAllocated == NumRegs) {
5283 unsigned RegStart = (i-NumAllocated)+1;
5284 unsigned RegEnd = i+1;
5285 // Mark all of the allocated registers used.
5286 for (unsigned i = RegStart; i != RegEnd; ++i)
5287 Regs.push_back(RegClassRegs[i]);
5289 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5290 OpInfo.ConstraintVT);
5291 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5296 // Otherwise, we couldn't allocate enough registers for this.
5299 /// visitInlineAsm - Handle a call to an InlineAsm object.
5301 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5302 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5304 /// ConstraintOperands - Information about all of the constraints.
5305 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5307 std::set<unsigned> OutputRegs, InputRegs;
5309 // Do a prepass over the constraints, canonicalizing them, and building up the
5310 // ConstraintOperands list.
5311 std::vector<InlineAsm::ConstraintInfo>
5312 ConstraintInfos = IA->ParseConstraints();
5314 bool hasMemory = hasInlineAsmMemConstraint(ConstraintInfos, TLI);
5316 SDValue Chain, Flag;
5318 // We won't need to flush pending loads if this asm doesn't touch
5319 // memory and is nonvolatile.
5320 if (hasMemory || IA->hasSideEffects())
5323 Chain = DAG.getRoot();
5325 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5326 unsigned ResNo = 0; // ResNo - The result number of the next output.
5327 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5328 ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
5329 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5331 EVT OpVT = MVT::Other;
5333 // Compute the value type for each operand.
5334 switch (OpInfo.Type) {
5335 case InlineAsm::isOutput:
5336 // Indirect outputs just consume an argument.
5337 if (OpInfo.isIndirect) {
5338 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5342 // The return value of the call is this value. As such, there is no
5343 // corresponding argument.
5344 assert(!CS.getType()->isVoidTy() &&
5346 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5347 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5349 assert(ResNo == 0 && "Asm only has one result!");
5350 OpVT = TLI.getValueType(CS.getType());
5354 case InlineAsm::isInput:
5355 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5357 case InlineAsm::isClobber:
5362 // If this is an input or an indirect output, process the call argument.
5363 // BasicBlocks are labels, currently appearing only in asm's.
5364 if (OpInfo.CallOperandVal) {
5365 // Strip bitcasts, if any. This mostly comes up for functions.
5366 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5368 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5369 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5371 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5374 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5377 OpInfo.ConstraintVT = OpVT;
5380 // Second pass over the constraints: compute which constraint option to use
5381 // and assign registers to constraints that want a specific physreg.
5382 for (unsigned i = 0, e = ConstraintInfos.size(); i != e; ++i) {
5383 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5385 // If this is an output operand with a matching input operand, look up the
5386 // matching input. If their types mismatch, e.g. one is an integer, the
5387 // other is floating point, or their sizes are different, flag it as an
5389 if (OpInfo.hasMatchingInput()) {
5390 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5392 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5393 if ((OpInfo.ConstraintVT.isInteger() !=
5394 Input.ConstraintVT.isInteger()) ||
5395 (OpInfo.ConstraintVT.getSizeInBits() !=
5396 Input.ConstraintVT.getSizeInBits())) {
5397 report_fatal_error("Unsupported asm: input constraint"
5398 " with a matching output constraint of"
5399 " incompatible type!");
5401 Input.ConstraintVT = OpInfo.ConstraintVT;
5405 // Compute the constraint code and ConstraintType to use.
5406 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5408 // If this is a memory input, and if the operand is not indirect, do what we
5409 // need to to provide an address for the memory input.
5410 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5411 !OpInfo.isIndirect) {
5412 assert(OpInfo.Type == InlineAsm::isInput &&
5413 "Can only indirectify direct input operands!");
5415 // Memory operands really want the address of the value. If we don't have
5416 // an indirect input, put it in the constpool if we can, otherwise spill
5417 // it to a stack slot.
5419 // If the operand is a float, integer, or vector constant, spill to a
5420 // constant pool entry to get its address.
5421 const Value *OpVal = OpInfo.CallOperandVal;
5422 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5423 isa<ConstantVector>(OpVal)) {
5424 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5425 TLI.getPointerTy());
5427 // Otherwise, create a stack slot and emit a store to it before the
5429 const Type *Ty = OpVal->getType();
5430 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5431 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5432 MachineFunction &MF = DAG.getMachineFunction();
5433 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5434 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5435 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5436 OpInfo.CallOperand, StackSlot, NULL, 0,
5438 OpInfo.CallOperand = StackSlot;
5441 // There is no longer a Value* corresponding to this operand.
5442 OpInfo.CallOperandVal = 0;
5444 // It is now an indirect operand.
5445 OpInfo.isIndirect = true;
5448 // If this constraint is for a specific register, allocate it before
5450 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5451 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5454 ConstraintInfos.clear();
5456 // Second pass - Loop over all of the operands, assigning virtual or physregs
5457 // to register class operands.
5458 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5459 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5461 // C_Register operands have already been allocated, Other/Memory don't need
5463 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5464 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5467 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5468 std::vector<SDValue> AsmNodeOperands;
5469 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5470 AsmNodeOperands.push_back(
5471 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5472 TLI.getPointerTy()));
5474 // If we have a !srcloc metadata node associated with it, we want to attach
5475 // this to the ultimately generated inline asm machineinstr. To do this, we
5476 // pass in the third operand as this (potentially null) inline asm MDNode.
5477 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5478 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5480 // Remember the AlignStack bit as operand 3.
5481 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0,
5484 // Loop over all of the inputs, copying the operand values into the
5485 // appropriate registers and processing the output regs.
5486 RegsForValue RetValRegs;
5488 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5489 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5491 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5492 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5494 switch (OpInfo.Type) {
5495 case InlineAsm::isOutput: {
5496 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5497 OpInfo.ConstraintType != TargetLowering::C_Register) {
5498 // Memory output, or 'other' output (e.g. 'X' constraint).
5499 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5501 // Add information to the INLINEASM node to know about this output.
5502 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5503 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5504 TLI.getPointerTy()));
5505 AsmNodeOperands.push_back(OpInfo.CallOperand);
5509 // Otherwise, this is a register or register class output.
5511 // Copy the output from the appropriate register. Find a register that
5513 if (OpInfo.AssignedRegs.Regs.empty())
5514 report_fatal_error("Couldn't allocate output reg for constraint '" +
5515 Twine(OpInfo.ConstraintCode) + "'!");
5517 // If this is an indirect operand, store through the pointer after the
5519 if (OpInfo.isIndirect) {
5520 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5521 OpInfo.CallOperandVal));
5523 // This is the result value of the call.
5524 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5525 // Concatenate this output onto the outputs list.
5526 RetValRegs.append(OpInfo.AssignedRegs);
5529 // Add information to the INLINEASM node to know that this register is
5531 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5532 InlineAsm::Kind_RegDefEarlyClobber :
5533 InlineAsm::Kind_RegDef,
5540 case InlineAsm::isInput: {
5541 SDValue InOperandVal = OpInfo.CallOperand;
5543 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5544 // If this is required to match an output register we have already set,
5545 // just use its register.
5546 unsigned OperandNo = OpInfo.getMatchedOperand();
5548 // Scan until we find the definition we already emitted of this operand.
5549 // When we find it, create a RegsForValue operand.
5550 unsigned CurOp = InlineAsm::Op_FirstOperand;
5551 for (; OperandNo; --OperandNo) {
5552 // Advance to the next operand.
5554 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5555 assert((InlineAsm::isRegDefKind(OpFlag) ||
5556 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5557 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5558 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5562 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5563 if (InlineAsm::isRegDefKind(OpFlag) ||
5564 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5565 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5566 if (OpInfo.isIndirect) {
5567 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5568 LLVMContext &Ctx = *DAG.getContext();
5569 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5570 " don't know how to handle tied "
5571 "indirect register inputs");
5574 RegsForValue MatchedRegs;
5575 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5576 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5577 MatchedRegs.RegVTs.push_back(RegVT);
5578 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5579 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5581 MatchedRegs.Regs.push_back
5582 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5584 // Use the produced MatchedRegs object to
5585 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5587 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5588 true, OpInfo.getMatchedOperand(),
5589 DAG, AsmNodeOperands);
5593 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5594 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5595 "Unexpected number of operands");
5596 // Add information to the INLINEASM node to know about this input.
5597 // See InlineAsm.h isUseOperandTiedToDef.
5598 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5599 OpInfo.getMatchedOperand());
5600 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5601 TLI.getPointerTy()));
5602 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5606 // Treat indirect 'X' constraint as memory.
5607 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5609 OpInfo.ConstraintType = TargetLowering::C_Memory;
5611 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5612 std::vector<SDValue> Ops;
5613 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5616 report_fatal_error("Invalid operand for inline asm constraint '" +
5617 Twine(OpInfo.ConstraintCode) + "'!");
5619 // Add information to the INLINEASM node to know about this input.
5620 unsigned ResOpType =
5621 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5622 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5623 TLI.getPointerTy()));
5624 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5628 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5629 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5630 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5631 "Memory operands expect pointer values");
5633 // Add information to the INLINEASM node to know about this input.
5634 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5635 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5636 TLI.getPointerTy()));
5637 AsmNodeOperands.push_back(InOperandVal);
5641 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5642 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5643 "Unknown constraint type!");
5644 assert(!OpInfo.isIndirect &&
5645 "Don't know how to handle indirect register inputs yet!");
5647 // Copy the input into the appropriate registers.
5648 if (OpInfo.AssignedRegs.Regs.empty() ||
5649 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5650 report_fatal_error("Couldn't allocate input reg for constraint '" +
5651 Twine(OpInfo.ConstraintCode) + "'!");
5653 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5656 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5657 DAG, AsmNodeOperands);
5660 case InlineAsm::isClobber: {
5661 // Add the clobbered value to the operand list, so that the register
5662 // allocator is aware that the physreg got clobbered.
5663 if (!OpInfo.AssignedRegs.Regs.empty())
5664 OpInfo.AssignedRegs.AddInlineAsmOperands(
5665 InlineAsm::Kind_RegDefEarlyClobber,
5673 // Finish up input operands. Set the input chain and add the flag last.
5674 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5675 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5677 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5678 DAG.getVTList(MVT::Other, MVT::Flag),
5679 &AsmNodeOperands[0], AsmNodeOperands.size());
5680 Flag = Chain.getValue(1);
5682 // If this asm returns a register value, copy the result from that register
5683 // and set it as the value of the call.
5684 if (!RetValRegs.Regs.empty()) {
5685 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5688 // FIXME: Why don't we do this for inline asms with MRVs?
5689 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5690 EVT ResultType = TLI.getValueType(CS.getType());
5692 // If any of the results of the inline asm is a vector, it may have the
5693 // wrong width/num elts. This can happen for register classes that can
5694 // contain multiple different value types. The preg or vreg allocated may
5695 // not have the same VT as was expected. Convert it to the right type
5696 // with bit_convert.
5697 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5698 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5701 } else if (ResultType != Val.getValueType() &&
5702 ResultType.isInteger() && Val.getValueType().isInteger()) {
5703 // If a result value was tied to an input value, the computed result may
5704 // have a wider width than the expected result. Extract the relevant
5706 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5709 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5712 setValue(CS.getInstruction(), Val);
5713 // Don't need to use this as a chain in this case.
5714 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5718 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5720 // Process indirect outputs, first output all of the flagged copies out of
5722 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5723 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5724 const Value *Ptr = IndirectStoresToEmit[i].second;
5725 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5727 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5730 // Emit the non-flagged stores from the physregs.
5731 SmallVector<SDValue, 8> OutChains;
5732 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5733 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5734 StoresToEmit[i].first,
5735 getValue(StoresToEmit[i].second),
5736 StoresToEmit[i].second, 0,
5738 OutChains.push_back(Val);
5741 if (!OutChains.empty())
5742 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5743 &OutChains[0], OutChains.size());
5748 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5749 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5750 MVT::Other, getRoot(),
5751 getValue(I.getArgOperand(0)),
5752 DAG.getSrcValue(I.getArgOperand(0))));
5755 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5756 const TargetData &TD = *TLI.getTargetData();
5757 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5758 getRoot(), getValue(I.getOperand(0)),
5759 DAG.getSrcValue(I.getOperand(0)),
5760 TD.getABITypeAlignment(I.getType()));
5762 DAG.setRoot(V.getValue(1));
5765 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5766 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5767 MVT::Other, getRoot(),
5768 getValue(I.getArgOperand(0)),
5769 DAG.getSrcValue(I.getArgOperand(0))));
5772 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5773 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5774 MVT::Other, getRoot(),
5775 getValue(I.getArgOperand(0)),
5776 getValue(I.getArgOperand(1)),
5777 DAG.getSrcValue(I.getArgOperand(0)),
5778 DAG.getSrcValue(I.getArgOperand(1))));
5781 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5782 /// implementation, which just calls LowerCall.
5783 /// FIXME: When all targets are
5784 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5785 std::pair<SDValue, SDValue>
5786 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5787 bool RetSExt, bool RetZExt, bool isVarArg,
5788 bool isInreg, unsigned NumFixedArgs,
5789 CallingConv::ID CallConv, bool isTailCall,
5790 bool isReturnValueUsed,
5792 ArgListTy &Args, SelectionDAG &DAG,
5793 DebugLoc dl) const {
5794 // Handle all of the outgoing arguments.
5795 SmallVector<ISD::OutputArg, 32> Outs;
5796 SmallVector<SDValue, 32> OutVals;
5797 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5798 SmallVector<EVT, 4> ValueVTs;
5799 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5800 for (unsigned Value = 0, NumValues = ValueVTs.size();
5801 Value != NumValues; ++Value) {
5802 EVT VT = ValueVTs[Value];
5803 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5804 SDValue Op = SDValue(Args[i].Node.getNode(),
5805 Args[i].Node.getResNo() + Value);
5806 ISD::ArgFlagsTy Flags;
5807 unsigned OriginalAlignment =
5808 getTargetData()->getABITypeAlignment(ArgTy);
5814 if (Args[i].isInReg)
5818 if (Args[i].isByVal) {
5820 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5821 const Type *ElementTy = Ty->getElementType();
5822 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5823 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5824 // For ByVal, alignment should come from FE. BE will guess if this
5825 // info is not there but there are cases it cannot get right.
5826 if (Args[i].Alignment)
5827 FrameAlign = Args[i].Alignment;
5828 Flags.setByValAlign(FrameAlign);
5829 Flags.setByValSize(FrameSize);
5833 Flags.setOrigAlign(OriginalAlignment);
5835 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5836 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5837 SmallVector<SDValue, 4> Parts(NumParts);
5838 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5841 ExtendKind = ISD::SIGN_EXTEND;
5842 else if (Args[i].isZExt)
5843 ExtendKind = ISD::ZERO_EXTEND;
5845 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5846 PartVT, ExtendKind);
5848 for (unsigned j = 0; j != NumParts; ++j) {
5849 // if it isn't first piece, alignment must be 1
5850 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
5852 if (NumParts > 1 && j == 0)
5853 MyFlags.Flags.setSplit();
5855 MyFlags.Flags.setOrigAlign(1);
5857 Outs.push_back(MyFlags);
5858 OutVals.push_back(Parts[j]);
5863 // Handle the incoming return values from the call.
5864 SmallVector<ISD::InputArg, 32> Ins;
5865 SmallVector<EVT, 4> RetTys;
5866 ComputeValueVTs(*this, RetTy, RetTys);
5867 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5869 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5870 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5871 for (unsigned i = 0; i != NumRegs; ++i) {
5872 ISD::InputArg MyFlags;
5873 MyFlags.VT = RegisterVT;
5874 MyFlags.Used = isReturnValueUsed;
5876 MyFlags.Flags.setSExt();
5878 MyFlags.Flags.setZExt();
5880 MyFlags.Flags.setInReg();
5881 Ins.push_back(MyFlags);
5885 SmallVector<SDValue, 4> InVals;
5886 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
5887 Outs, OutVals, Ins, dl, DAG, InVals);
5889 // Verify that the target's LowerCall behaved as expected.
5890 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
5891 "LowerCall didn't return a valid chain!");
5892 assert((!isTailCall || InVals.empty()) &&
5893 "LowerCall emitted a return value for a tail call!");
5894 assert((isTailCall || InVals.size() == Ins.size()) &&
5895 "LowerCall didn't emit the correct number of values!");
5897 // For a tail call, the return value is merely live-out and there aren't
5898 // any nodes in the DAG representing it. Return a special value to
5899 // indicate that a tail call has been emitted and no more Instructions
5900 // should be processed in the current block.
5903 return std::make_pair(SDValue(), SDValue());
5906 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
5907 assert(InVals[i].getNode() &&
5908 "LowerCall emitted a null value!");
5909 assert(Ins[i].VT == InVals[i].getValueType() &&
5910 "LowerCall emitted a value with the wrong type!");
5913 // Collect the legal value parts into potentially illegal values
5914 // that correspond to the original function's return values.
5915 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5917 AssertOp = ISD::AssertSext;
5919 AssertOp = ISD::AssertZext;
5920 SmallVector<SDValue, 4> ReturnValues;
5921 unsigned CurReg = 0;
5922 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5924 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
5925 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
5927 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
5928 NumRegs, RegisterVT, VT,
5933 // For a function returning void, there is no return value. We can't create
5934 // such a node, so we just return a null return value in that case. In
5935 // that case, nothing will actualy look at the value.
5936 if (ReturnValues.empty())
5937 return std::make_pair(SDValue(), Chain);
5939 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
5940 DAG.getVTList(&RetTys[0], RetTys.size()),
5941 &ReturnValues[0], ReturnValues.size());
5942 return std::make_pair(Res, Chain);
5945 void TargetLowering::LowerOperationWrapper(SDNode *N,
5946 SmallVectorImpl<SDValue> &Results,
5947 SelectionDAG &DAG) const {
5948 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
5950 Results.push_back(Res);
5953 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5954 llvm_unreachable("LowerOperation not implemented for this target!");
5959 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
5960 SDValue Op = getNonRegisterValue(V);
5961 assert((Op.getOpcode() != ISD::CopyFromReg ||
5962 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
5963 "Copy from a reg to the same reg!");
5964 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
5966 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
5967 SDValue Chain = DAG.getEntryNode();
5968 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
5969 PendingExports.push_back(Chain);
5972 #include "llvm/CodeGen/SelectionDAGISel.h"
5974 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
5975 // If this is the entry block, emit arguments.
5976 const Function &F = *LLVMBB->getParent();
5977 SelectionDAG &DAG = SDB->DAG;
5978 DebugLoc dl = SDB->getCurDebugLoc();
5979 const TargetData *TD = TLI.getTargetData();
5980 SmallVector<ISD::InputArg, 16> Ins;
5982 // Check whether the function can return without sret-demotion.
5983 SmallVector<ISD::OutputArg, 4> Outs;
5984 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5987 if (!FuncInfo->CanLowerReturn) {
5988 // Put in an sret pointer parameter before all the other parameters.
5989 SmallVector<EVT, 1> ValueVTs;
5990 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
5992 // NOTE: Assuming that a pointer will never break down to more than one VT
5994 ISD::ArgFlagsTy Flags;
5996 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
5997 ISD::InputArg RetArg(Flags, RegisterVT, true);
5998 Ins.push_back(RetArg);
6001 // Set up the incoming argument description vector.
6003 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6004 I != E; ++I, ++Idx) {
6005 SmallVector<EVT, 4> ValueVTs;
6006 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6007 bool isArgValueUsed = !I->use_empty();
6008 for (unsigned Value = 0, NumValues = ValueVTs.size();
6009 Value != NumValues; ++Value) {
6010 EVT VT = ValueVTs[Value];
6011 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6012 ISD::ArgFlagsTy Flags;
6013 unsigned OriginalAlignment =
6014 TD->getABITypeAlignment(ArgTy);
6016 if (F.paramHasAttr(Idx, Attribute::ZExt))
6018 if (F.paramHasAttr(Idx, Attribute::SExt))
6020 if (F.paramHasAttr(Idx, Attribute::InReg))
6022 if (F.paramHasAttr(Idx, Attribute::StructRet))
6024 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6026 const PointerType *Ty = cast<PointerType>(I->getType());
6027 const Type *ElementTy = Ty->getElementType();
6028 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6029 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6030 // For ByVal, alignment should be passed from FE. BE will guess if
6031 // this info is not there but there are cases it cannot get right.
6032 if (F.getParamAlignment(Idx))
6033 FrameAlign = F.getParamAlignment(Idx);
6034 Flags.setByValAlign(FrameAlign);
6035 Flags.setByValSize(FrameSize);
6037 if (F.paramHasAttr(Idx, Attribute::Nest))
6039 Flags.setOrigAlign(OriginalAlignment);
6041 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6042 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6043 for (unsigned i = 0; i != NumRegs; ++i) {
6044 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6045 if (NumRegs > 1 && i == 0)
6046 MyFlags.Flags.setSplit();
6047 // if it isn't first piece, alignment must be 1
6049 MyFlags.Flags.setOrigAlign(1);
6050 Ins.push_back(MyFlags);
6055 // Call the target to set up the argument values.
6056 SmallVector<SDValue, 8> InVals;
6057 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6061 // Verify that the target's LowerFormalArguments behaved as expected.
6062 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6063 "LowerFormalArguments didn't return a valid chain!");
6064 assert(InVals.size() == Ins.size() &&
6065 "LowerFormalArguments didn't emit the correct number of values!");
6067 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6068 assert(InVals[i].getNode() &&
6069 "LowerFormalArguments emitted a null value!");
6070 assert(Ins[i].VT == InVals[i].getValueType() &&
6071 "LowerFormalArguments emitted a value with the wrong type!");
6075 // Update the DAG with the new chain value resulting from argument lowering.
6076 DAG.setRoot(NewRoot);
6078 // Set up the argument values.
6081 if (!FuncInfo->CanLowerReturn) {
6082 // Create a virtual register for the sret pointer, and put in a copy
6083 // from the sret argument into it.
6084 SmallVector<EVT, 1> ValueVTs;
6085 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6086 EVT VT = ValueVTs[0];
6087 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6088 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6089 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6090 RegVT, VT, AssertOp);
6092 MachineFunction& MF = SDB->DAG.getMachineFunction();
6093 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6094 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6095 FuncInfo->DemoteRegister = SRetReg;
6096 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6098 DAG.setRoot(NewRoot);
6100 // i indexes lowered arguments. Bump it past the hidden sret argument.
6101 // Idx indexes LLVM arguments. Don't touch it.
6105 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6107 SmallVector<SDValue, 4> ArgValues;
6108 SmallVector<EVT, 4> ValueVTs;
6109 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6110 unsigned NumValues = ValueVTs.size();
6112 // If this argument is unused then remember its value. It is used to generate
6113 // debugging information.
6114 if (I->use_empty() && NumValues)
6115 SDB->setUnusedArgValue(I, InVals[i]);
6117 for (unsigned Value = 0; Value != NumValues; ++Value) {
6118 EVT VT = ValueVTs[Value];
6119 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6120 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6122 if (!I->use_empty()) {
6123 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6124 if (F.paramHasAttr(Idx, Attribute::SExt))
6125 AssertOp = ISD::AssertSext;
6126 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6127 AssertOp = ISD::AssertZext;
6129 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6130 NumParts, PartVT, VT,
6137 if (!I->use_empty()) {
6139 if (!ArgValues.empty())
6140 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6141 SDB->getCurDebugLoc());
6142 SDB->setValue(I, Res);
6144 // If this argument is live outside of the entry block, insert a copy from
6145 // whereever we got it to the vreg that other BB's will reference it as.
6146 SDB->CopyToExportRegsIfNeeded(I);
6150 assert(i == InVals.size() && "Argument register count mismatch!");
6152 // Finally, if the target has anything special to do, allow it to do so.
6153 // FIXME: this should insert code into the DAG!
6154 EmitFunctionEntryCode();
6157 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6158 /// ensure constants are generated when needed. Remember the virtual registers
6159 /// that need to be added to the Machine PHI nodes as input. We cannot just
6160 /// directly add them, because expansion might result in multiple MBB's for one
6161 /// BB. As such, the start of the BB might correspond to a different MBB than
6165 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6166 const TerminatorInst *TI = LLVMBB->getTerminator();
6168 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6170 // Check successor nodes' PHI nodes that expect a constant to be available
6172 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6173 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6174 if (!isa<PHINode>(SuccBB->begin())) continue;
6175 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6177 // If this terminator has multiple identical successors (common for
6178 // switches), only handle each succ once.
6179 if (!SuccsHandled.insert(SuccMBB)) continue;
6181 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6183 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6184 // nodes and Machine PHI nodes, but the incoming operands have not been
6186 for (BasicBlock::const_iterator I = SuccBB->begin();
6187 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6188 // Ignore dead phi's.
6189 if (PN->use_empty()) continue;
6192 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6194 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6195 unsigned &RegOut = ConstantsOut[C];
6197 RegOut = FuncInfo.CreateRegs(C->getType());
6198 CopyValueToVirtualRegister(C, RegOut);
6202 DenseMap<const Value *, unsigned>::iterator I =
6203 FuncInfo.ValueMap.find(PHIOp);
6204 if (I != FuncInfo.ValueMap.end())
6207 assert(isa<AllocaInst>(PHIOp) &&
6208 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6209 "Didn't codegen value into a register!??");
6210 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6211 CopyValueToVirtualRegister(PHIOp, Reg);
6215 // Remember that this register needs to added to the machine PHI node as
6216 // the input for this MBB.
6217 SmallVector<EVT, 4> ValueVTs;
6218 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6219 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6220 EVT VT = ValueVTs[vti];
6221 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6222 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6223 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6224 Reg += NumRegisters;
6228 ConstantsOut.clear();