1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
48 #include "llvm/Target/TargetData.h"
49 #include "llvm/Target/TargetFrameInfo.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Support/Compiler.h"
55 #include "llvm/Support/CommandLine.h"
56 #include "llvm/Support/Debug.h"
57 #include "llvm/Support/ErrorHandling.h"
58 #include "llvm/Support/MathExtras.h"
59 #include "llvm/Support/raw_ostream.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs.
81 // MaxParallelChains default is arbitrarily high to avoid affecting
82 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
83 // sequence over this should have been converted to llvm.memcpy by the
84 // frontend. It easy to induce this behavior with .ll code such as:
85 // %buffer = alloca [4096 x i8]
86 // %data = load [4096 x i8]* %argPtr
87 // store [4096 x i8] %data, [4096 x i8]* %buffer
88 static cl::opt<unsigned>
89 MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"),
90 cl::init(64), cl::Hidden);
92 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
93 const SDValue *Parts, unsigned NumParts,
94 EVT PartVT, EVT ValueVT);
96 /// getCopyFromParts - Create a value that contains the specified legal parts
97 /// combined into the value they represent. If the parts combine to a type
98 /// larger then ValueVT then AssertOp can be used to specify whether the extra
99 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
100 /// (ISD::AssertSext).
101 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
102 const SDValue *Parts,
103 unsigned NumParts, EVT PartVT, EVT ValueVT,
104 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
105 if (ValueVT.isVector())
106 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
108 assert(NumParts > 0 && "No parts to assemble!");
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
110 SDValue Val = Parts[0];
113 // Assemble the value from multiple parts.
114 if (ValueVT.isInteger()) {
115 unsigned PartBits = PartVT.getSizeInBits();
116 unsigned ValueBits = ValueVT.getSizeInBits();
118 // Assemble the power of 2 part.
119 unsigned RoundParts = NumParts & (NumParts - 1) ?
120 1 << Log2_32(NumParts) : NumParts;
121 unsigned RoundBits = PartBits * RoundParts;
122 EVT RoundVT = RoundBits == ValueBits ?
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
128 if (RoundParts > 2) {
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
132 RoundParts / 2, PartVT, HalfVT);
134 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
138 if (TLI.isBigEndian())
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 if (RoundParts < NumParts) {
144 // Assemble the trailing non-power-of-2 part.
145 unsigned OddParts = NumParts - RoundParts;
146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
147 Hi = getCopyFromParts(DAG, DL,
148 Parts + RoundParts, OddParts, PartVT, OddVT);
150 // Combine the round and odd parts.
152 if (TLI.isBigEndian())
154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
158 TLI.getPointerTy()));
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
162 } else if (PartVT.isFloatingPoint()) {
163 // FP split into multiple FP parts (for ppcf128)
164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
167 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
169 if (TLI.isBigEndian())
171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
173 // FP split into integer parts (soft fp)
174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
175 !PartVT.isVector() && "Unexpected split");
176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
181 // There is now one part, held in Val. Correct it to match ValueVT.
182 PartVT = Val.getValueType();
184 if (PartVT == ValueVT)
187 if (PartVT.isInteger() && ValueVT.isInteger()) {
188 if (ValueVT.bitsLT(PartVT)) {
189 // For a truncate, see if we have any information to
190 // indicate whether the truncated bits will always be
191 // zero or sign-extension.
192 if (AssertOp != ISD::DELETED_NODE)
193 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
194 DAG.getValueType(ValueVT));
195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
200 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
201 // FP_ROUND's are always exact here.
202 if (ValueVT.bitsLT(Val.getValueType()))
203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
204 DAG.getIntPtrConstant(1));
206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
209 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
210 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
212 llvm_unreachable("Unknown mismatch!");
216 /// getCopyFromParts - Create a value that contains the specified legal parts
217 /// combined into the value they represent. If the parts combine to a type
218 /// larger then ValueVT then AssertOp can be used to specify whether the extra
219 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
220 /// (ISD::AssertSext).
221 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
222 const SDValue *Parts, unsigned NumParts,
223 EVT PartVT, EVT ValueVT) {
224 assert(ValueVT.isVector() && "Not a vector value");
225 assert(NumParts > 0 && "No parts to assemble!");
226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
227 SDValue Val = Parts[0];
229 // Handle a multi-element vector.
231 EVT IntermediateVT, RegisterVT;
232 unsigned NumIntermediates;
234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
235 NumIntermediates, RegisterVT);
236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
237 NumParts = NumRegs; // Silence a compiler warning.
238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
239 assert(RegisterVT == Parts[0].getValueType() &&
240 "Part type doesn't match part!");
242 // Assemble the parts into intermediate operands.
243 SmallVector<SDValue, 8> Ops(NumIntermediates);
244 if (NumIntermediates == NumParts) {
245 // If the register was not expanded, truncate or copy the value,
247 for (unsigned i = 0; i != NumParts; ++i)
248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
249 PartVT, IntermediateVT);
250 } else if (NumParts > 0) {
251 // If the intermediate type was expanded, build the intermediate
252 // operands from the parts.
253 assert(NumParts % NumIntermediates == 0 &&
254 "Must expand into a divisible number of parts!");
255 unsigned Factor = NumParts / NumIntermediates;
256 for (unsigned i = 0; i != NumIntermediates; ++i)
257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
258 PartVT, IntermediateVT);
261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
262 // intermediate operands.
263 Val = DAG.getNode(IntermediateVT.isVector() ?
264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
265 ValueVT, &Ops[0], NumIntermediates);
268 // There is now one part, held in Val. Correct it to match ValueVT.
269 PartVT = Val.getValueType();
271 if (PartVT == ValueVT)
274 if (PartVT.isVector()) {
275 // If the element type of the source/dest vectors are the same, but the
276 // parts vector has more elements than the value vector, then we have a
277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
279 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
280 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
281 "Cannot narrow, it would be a lossy transformation");
282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
283 DAG.getIntPtrConstant(0));
286 // Vector/Vector bitcast.
287 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
290 assert(ValueVT.getVectorElementType() == PartVT &&
291 ValueVT.getVectorNumElements() == 1 &&
292 "Only trivial scalar-to-vector conversions should get here!");
293 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
299 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
300 SDValue Val, SDValue *Parts, unsigned NumParts,
303 /// getCopyToParts - Create a series of nodes that contain the specified value
304 /// split into legal parts. If the parts contain more bits than Val, then, for
305 /// integers, ExtendKind can be used to specify how to generate the extra bits.
306 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
307 SDValue Val, SDValue *Parts, unsigned NumParts,
309 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
310 EVT ValueVT = Val.getValueType();
312 // Handle the vector case separately.
313 if (ValueVT.isVector())
314 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
317 unsigned PartBits = PartVT.getSizeInBits();
318 unsigned OrigNumParts = NumParts;
319 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
324 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
325 if (PartVT == ValueVT) {
326 assert(NumParts == 1 && "No-op copy with multiple parts!");
331 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
332 // If the parts cover more bits than the value has, promote the value.
333 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
334 assert(NumParts == 1 && "Do not know what to promote to!");
335 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
337 assert(PartVT.isInteger() && ValueVT.isInteger() &&
338 "Unknown mismatch!");
339 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
340 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
342 } else if (PartBits == ValueVT.getSizeInBits()) {
343 // Different types of the same size.
344 assert(NumParts == 1 && PartVT != ValueVT);
345 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
346 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
347 // If the parts cover less bits than value has, truncate the value.
348 assert(PartVT.isInteger() && ValueVT.isInteger() &&
349 "Unknown mismatch!");
350 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
351 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
354 // The value may have changed - recompute ValueVT.
355 ValueVT = Val.getValueType();
356 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
357 "Failed to tile the value with PartVT!");
360 assert(PartVT == ValueVT && "Type conversion failed!");
365 // Expand the value into multiple parts.
366 if (NumParts & (NumParts - 1)) {
367 // The number of parts is not a power of 2. Split off and copy the tail.
368 assert(PartVT.isInteger() && ValueVT.isInteger() &&
369 "Do not know what to expand to!");
370 unsigned RoundParts = 1 << Log2_32(NumParts);
371 unsigned RoundBits = RoundParts * PartBits;
372 unsigned OddParts = NumParts - RoundParts;
373 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
374 DAG.getIntPtrConstant(RoundBits));
375 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
377 if (TLI.isBigEndian())
378 // The odd parts were reversed by getCopyToParts - unreverse them.
379 std::reverse(Parts + RoundParts, Parts + NumParts);
381 NumParts = RoundParts;
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
386 // The number of parts is a power of 2. Repeatedly bisect the value using
388 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
389 EVT::getIntegerVT(*DAG.getContext(),
390 ValueVT.getSizeInBits()),
393 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
394 for (unsigned i = 0; i < NumParts; i += StepSize) {
395 unsigned ThisBits = StepSize * PartBits / 2;
396 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
397 SDValue &Part0 = Parts[i];
398 SDValue &Part1 = Parts[i+StepSize/2];
400 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
401 ThisVT, Part0, DAG.getIntPtrConstant(1));
402 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
403 ThisVT, Part0, DAG.getIntPtrConstant(0));
405 if (ThisBits == PartBits && ThisVT != PartVT) {
406 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
407 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
412 if (TLI.isBigEndian())
413 std::reverse(Parts, Parts + OrigNumParts);
417 /// getCopyToPartsVector - Create a series of nodes that contain the specified
418 /// value split into legal parts.
419 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
420 SDValue Val, SDValue *Parts, unsigned NumParts,
422 EVT ValueVT = Val.getValueType();
423 assert(ValueVT.isVector() && "Not a vector");
424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
427 if (PartVT == ValueVT) {
429 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
430 // Bitconvert vector->vector case.
431 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
432 } else if (PartVT.isVector() &&
433 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
434 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
435 EVT ElementVT = PartVT.getVectorElementType();
436 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
438 SmallVector<SDValue, 16> Ops;
439 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
440 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
441 ElementVT, Val, DAG.getIntPtrConstant(i)));
443 for (unsigned i = ValueVT.getVectorNumElements(),
444 e = PartVT.getVectorNumElements(); i != e; ++i)
445 Ops.push_back(DAG.getUNDEF(ElementVT));
447 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
449 // FIXME: Use CONCAT for 2x -> 4x.
451 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
452 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
454 // Vector -> scalar conversion.
455 assert(ValueVT.getVectorElementType() == PartVT &&
456 ValueVT.getVectorNumElements() == 1 &&
457 "Only trivial vector-to-scalar conversions should get here!");
458 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
459 PartVT, Val, DAG.getIntPtrConstant(0));
466 // Handle a multi-element vector.
467 EVT IntermediateVT, RegisterVT;
468 unsigned NumIntermediates;
469 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
471 NumIntermediates, RegisterVT);
472 unsigned NumElements = ValueVT.getVectorNumElements();
474 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
475 NumParts = NumRegs; // Silence a compiler warning.
476 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
478 // Split the vector into intermediate operands.
479 SmallVector<SDValue, 8> Ops(NumIntermediates);
480 for (unsigned i = 0; i != NumIntermediates; ++i) {
481 if (IntermediateVT.isVector())
482 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
484 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
486 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
487 IntermediateVT, Val, DAG.getIntPtrConstant(i));
490 // Split the intermediate operands into legal parts.
491 if (NumParts == NumIntermediates) {
492 // If the register was not expanded, promote or copy the value,
494 for (unsigned i = 0; i != NumParts; ++i)
495 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
496 } else if (NumParts > 0) {
497 // If the intermediate type was expanded, split each the value into
499 assert(NumParts % NumIntermediates == 0 &&
500 "Must expand into a divisible number of parts!");
501 unsigned Factor = NumParts / NumIntermediates;
502 for (unsigned i = 0; i != NumIntermediates; ++i)
503 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
511 /// RegsForValue - This struct represents the registers (physical or virtual)
512 /// that a particular set of values is assigned, and the type information
513 /// about the value. The most common situation is to represent one value at a
514 /// time, but struct or array values are handled element-wise as multiple
515 /// values. The splitting of aggregates is performed recursively, so that we
516 /// never have aggregate-typed registers. The values at this point do not
517 /// necessarily have legal types, so each value may require one or more
518 /// registers of some legal type.
520 struct RegsForValue {
521 /// ValueVTs - The value types of the values, which may not be legal, and
522 /// may need be promoted or synthesized from one or more registers.
524 SmallVector<EVT, 4> ValueVTs;
526 /// RegVTs - The value types of the registers. This is the same size as
527 /// ValueVTs and it records, for each value, what the type of the assigned
528 /// register or registers are. (Individual values are never synthesized
529 /// from more than one type of register.)
531 /// With virtual registers, the contents of RegVTs is redundant with TLI's
532 /// getRegisterType member function, however when with physical registers
533 /// it is necessary to have a separate record of the types.
535 SmallVector<EVT, 4> RegVTs;
537 /// Regs - This list holds the registers assigned to the values.
538 /// Each legal or promoted value requires one register, and each
539 /// expanded value requires multiple registers.
541 SmallVector<unsigned, 4> Regs;
545 RegsForValue(const SmallVector<unsigned, 4> ®s,
546 EVT regvt, EVT valuevt)
547 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
549 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
550 unsigned Reg, const Type *Ty) {
551 ComputeValueVTs(tli, Ty, ValueVTs);
553 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
554 EVT ValueVT = ValueVTs[Value];
555 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
556 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
557 for (unsigned i = 0; i != NumRegs; ++i)
558 Regs.push_back(Reg + i);
559 RegVTs.push_back(RegisterVT);
564 /// areValueTypesLegal - Return true if types of all the values are legal.
565 bool areValueTypesLegal(const TargetLowering &TLI) {
566 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
567 EVT RegisterVT = RegVTs[Value];
568 if (!TLI.isTypeLegal(RegisterVT))
574 /// append - Add the specified values to this one.
575 void append(const RegsForValue &RHS) {
576 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
577 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
578 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
581 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
582 /// this value and returns the result as a ValueVTs value. This uses
583 /// Chain/Flag as the input and updates them for the output Chain/Flag.
584 /// If the Flag pointer is NULL, no flag is used.
585 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
587 SDValue &Chain, SDValue *Flag) const;
589 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
590 /// specified value into the registers specified by this object. This uses
591 /// Chain/Flag as the input and updates them for the output Chain/Flag.
592 /// If the Flag pointer is NULL, no flag is used.
593 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
594 SDValue &Chain, SDValue *Flag) const;
596 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
597 /// operand list. This adds the code marker, matching input operand index
598 /// (if applicable), and includes the number of values added into it.
599 void AddInlineAsmOperands(unsigned Kind,
600 bool HasMatching, unsigned MatchingIdx,
602 std::vector<SDValue> &Ops) const;
606 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
607 /// this value and returns the result as a ValueVT value. This uses
608 /// Chain/Flag as the input and updates them for the output Chain/Flag.
609 /// If the Flag pointer is NULL, no flag is used.
610 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
611 FunctionLoweringInfo &FuncInfo,
613 SDValue &Chain, SDValue *Flag) const {
614 // A Value with type {} or [0 x %t] needs no registers.
615 if (ValueVTs.empty())
618 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
620 // Assemble the legal parts into the final values.
621 SmallVector<SDValue, 4> Values(ValueVTs.size());
622 SmallVector<SDValue, 8> Parts;
623 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 // Copy the legal parts from the registers.
625 EVT ValueVT = ValueVTs[Value];
626 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
627 EVT RegisterVT = RegVTs[Value];
629 Parts.resize(NumRegs);
630 for (unsigned i = 0; i != NumRegs; ++i) {
633 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
635 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
636 *Flag = P.getValue(2);
639 Chain = P.getValue(1);
642 // If the source register was virtual and if we know something about it,
643 // add an assert node.
644 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
645 !RegisterVT.isInteger() || RegisterVT.isVector())
648 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
649 if (SlotNo >= FuncInfo.LiveOutRegInfo.size()) continue;
651 const FunctionLoweringInfo::LiveOutInfo &LOI =
652 FuncInfo.LiveOutRegInfo[SlotNo];
654 unsigned RegSize = RegisterVT.getSizeInBits();
655 unsigned NumSignBits = LOI.NumSignBits;
656 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
658 // FIXME: We capture more information than the dag can represent. For
659 // now, just use the tightest assertzext/assertsext possible.
661 EVT FromVT(MVT::Other);
662 if (NumSignBits == RegSize)
663 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
664 else if (NumZeroBits >= RegSize-1)
665 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
666 else if (NumSignBits > RegSize-8)
667 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
668 else if (NumZeroBits >= RegSize-8)
669 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
670 else if (NumSignBits > RegSize-16)
671 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
672 else if (NumZeroBits >= RegSize-16)
673 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
674 else if (NumSignBits > RegSize-32)
675 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
676 else if (NumZeroBits >= RegSize-32)
677 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
681 // Add an assertion node.
682 assert(FromVT != MVT::Other);
683 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
684 RegisterVT, P, DAG.getValueType(FromVT));
687 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
688 NumRegs, RegisterVT, ValueVT);
693 return DAG.getNode(ISD::MERGE_VALUES, dl,
694 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
695 &Values[0], ValueVTs.size());
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
703 SDValue &Chain, SDValue *Flag) const {
704 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 // Get the list of the values's legal parts.
707 unsigned NumRegs = Regs.size();
708 SmallVector<SDValue, 8> Parts(NumRegs);
709 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
710 EVT ValueVT = ValueVTs[Value];
711 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
712 EVT RegisterVT = RegVTs[Value];
714 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
715 &Parts[Part], NumParts, RegisterVT);
719 // Copy the parts into the registers.
720 SmallVector<SDValue, 8> Chains(NumRegs);
721 for (unsigned i = 0; i != NumRegs; ++i) {
724 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
726 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
727 *Flag = Part.getValue(1);
730 Chains[i] = Part.getValue(0);
733 if (NumRegs == 1 || Flag)
734 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
735 // flagged to it. That is the CopyToReg nodes and the user are considered
736 // a single scheduling unit. If we create a TokenFactor and return it as
737 // chain, then the TokenFactor is both a predecessor (operand) of the
738 // user as well as a successor (the TF operands are flagged to the user).
739 // c1, f1 = CopyToReg
740 // c2, f2 = CopyToReg
741 // c3 = TokenFactor c1, c2
744 Chain = Chains[NumRegs-1];
746 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
749 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
750 /// operand list. This adds the code marker and includes the number of
751 /// values added into it.
752 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
753 unsigned MatchingIdx,
755 std::vector<SDValue> &Ops) const {
756 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
758 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
760 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
761 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
764 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
765 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
766 EVT RegisterVT = RegVTs[Value];
767 for (unsigned i = 0; i != NumRegs; ++i) {
768 assert(Reg < Regs.size() && "Mismatch in # registers expected");
769 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
774 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
777 TD = DAG.getTarget().getTargetData();
780 /// clear - Clear out the current SelectionDAG and the associated
781 /// state and prepare this SelectionDAGBuilder object to be used
782 /// for a new block. This doesn't clear out information about
783 /// additional blocks that are needed to complete switch lowering
784 /// or PHI node updating; that information is cleared out as it is
786 void SelectionDAGBuilder::clear() {
788 UnusedArgNodeMap.clear();
789 PendingLoads.clear();
790 PendingExports.clear();
791 DanglingDebugInfoMap.clear();
792 CurDebugLoc = DebugLoc();
796 /// getRoot - Return the current virtual root of the Selection DAG,
797 /// flushing any PendingLoad items. This must be done before emitting
798 /// a store or any other node that may need to be ordered after any
799 /// prior load instructions.
801 SDValue SelectionDAGBuilder::getRoot() {
802 if (PendingLoads.empty())
803 return DAG.getRoot();
805 if (PendingLoads.size() == 1) {
806 SDValue Root = PendingLoads[0];
808 PendingLoads.clear();
812 // Otherwise, we have to make a token factor node.
813 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
814 &PendingLoads[0], PendingLoads.size());
815 PendingLoads.clear();
820 /// getControlRoot - Similar to getRoot, but instead of flushing all the
821 /// PendingLoad items, flush all the PendingExports items. It is necessary
822 /// to do this before emitting a terminator instruction.
824 SDValue SelectionDAGBuilder::getControlRoot() {
825 SDValue Root = DAG.getRoot();
827 if (PendingExports.empty())
830 // Turn all of the CopyToReg chains into one factored node.
831 if (Root.getOpcode() != ISD::EntryToken) {
832 unsigned i = 0, e = PendingExports.size();
833 for (; i != e; ++i) {
834 assert(PendingExports[i].getNode()->getNumOperands() > 1);
835 if (PendingExports[i].getNode()->getOperand(0) == Root)
836 break; // Don't add the root if we already indirectly depend on it.
840 PendingExports.push_back(Root);
843 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
845 PendingExports.size());
846 PendingExports.clear();
851 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
852 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
853 DAG.AssignOrdering(Node, SDNodeOrder);
855 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
856 AssignOrderingToNode(Node->getOperand(I).getNode());
859 void SelectionDAGBuilder::visit(const Instruction &I) {
860 // Set up outgoing PHI node register values before emitting the terminator.
861 if (isa<TerminatorInst>(&I))
862 HandlePHINodesInSuccessorBlocks(I.getParent());
864 CurDebugLoc = I.getDebugLoc();
866 visit(I.getOpcode(), I);
868 if (!isa<TerminatorInst>(&I) && !HasTailCall)
869 CopyToExportRegsIfNeeded(&I);
871 CurDebugLoc = DebugLoc();
874 void SelectionDAGBuilder::visitPHI(const PHINode &) {
875 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
878 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
879 // Note: this doesn't use InstVisitor, because it has to work with
880 // ConstantExpr's in addition to instructions.
882 default: llvm_unreachable("Unknown instruction type encountered!");
883 // Build the switch statement using the Instruction.def file.
884 #define HANDLE_INST(NUM, OPCODE, CLASS) \
885 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
886 #include "llvm/Instruction.def"
889 // Assign the ordering to the freshly created DAG nodes.
890 if (NodeMap.count(&I)) {
892 AssignOrderingToNode(getValue(&I).getNode());
896 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
897 // generate the debug data structures now that we've seen its definition.
898 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
900 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
902 const DbgValueInst *DI = DDI.getDI();
903 DebugLoc dl = DDI.getdl();
904 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
905 MDNode *Variable = DI->getVariable();
906 uint64_t Offset = DI->getOffset();
909 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
910 SDV = DAG.getDbgValue(Variable, Val.getNode(),
911 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
912 DAG.AddDbgValue(SDV, Val.getNode(), false);
915 DEBUG(dbgs() << "Dropping debug info for " << DI);
916 DanglingDebugInfoMap[V] = DanglingDebugInfo();
920 // getValue - Return an SDValue for the given Value.
921 SDValue SelectionDAGBuilder::getValue(const Value *V) {
922 // If we already have an SDValue for this value, use it. It's important
923 // to do this first, so that we don't create a CopyFromReg if we already
924 // have a regular SDValue.
925 SDValue &N = NodeMap[V];
926 if (N.getNode()) return N;
928 // If there's a virtual register allocated and initialized for this
930 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
931 if (It != FuncInfo.ValueMap.end()) {
932 unsigned InReg = It->second;
933 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
934 SDValue Chain = DAG.getEntryNode();
935 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
938 // Otherwise create a new SDValue and remember it.
939 SDValue Val = getValueImpl(V);
941 resolveDanglingDebugInfo(V, Val);
945 /// getNonRegisterValue - Return an SDValue for the given Value, but
946 /// don't look in FuncInfo.ValueMap for a virtual register.
947 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
948 // If we already have an SDValue for this value, use it.
949 SDValue &N = NodeMap[V];
950 if (N.getNode()) return N;
952 // Otherwise create a new SDValue and remember it.
953 SDValue Val = getValueImpl(V);
955 resolveDanglingDebugInfo(V, Val);
959 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
960 /// Create an SDValue for the given value.
961 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
962 if (const Constant *C = dyn_cast<Constant>(V)) {
963 EVT VT = TLI.getValueType(V->getType(), true);
965 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
966 return DAG.getConstant(*CI, VT);
968 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
969 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
971 if (isa<ConstantPointerNull>(C))
972 return DAG.getConstant(0, TLI.getPointerTy());
974 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
975 return DAG.getConstantFP(*CFP, VT);
977 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
978 return DAG.getUNDEF(VT);
980 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
981 visit(CE->getOpcode(), *CE);
982 SDValue N1 = NodeMap[V];
983 assert(N1.getNode() && "visit didn't populate the NodeMap!");
987 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
988 SmallVector<SDValue, 4> Constants;
989 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
991 SDNode *Val = getValue(*OI).getNode();
992 // If the operand is an empty aggregate, there are no values.
994 // Add each leaf value from the operand to the Constants list
995 // to form a flattened list of all the values.
996 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
997 Constants.push_back(SDValue(Val, i));
1000 return DAG.getMergeValues(&Constants[0], Constants.size(),
1004 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1005 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1006 "Unknown struct or array constant!");
1008 SmallVector<EVT, 4> ValueVTs;
1009 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1010 unsigned NumElts = ValueVTs.size();
1012 return SDValue(); // empty struct
1013 SmallVector<SDValue, 4> Constants(NumElts);
1014 for (unsigned i = 0; i != NumElts; ++i) {
1015 EVT EltVT = ValueVTs[i];
1016 if (isa<UndefValue>(C))
1017 Constants[i] = DAG.getUNDEF(EltVT);
1018 else if (EltVT.isFloatingPoint())
1019 Constants[i] = DAG.getConstantFP(0, EltVT);
1021 Constants[i] = DAG.getConstant(0, EltVT);
1024 return DAG.getMergeValues(&Constants[0], NumElts,
1028 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1029 return DAG.getBlockAddress(BA, VT);
1031 const VectorType *VecTy = cast<VectorType>(V->getType());
1032 unsigned NumElements = VecTy->getNumElements();
1034 // Now that we know the number and type of the elements, get that number of
1035 // elements into the Ops array based on what kind of constant it is.
1036 SmallVector<SDValue, 16> Ops;
1037 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1038 for (unsigned i = 0; i != NumElements; ++i)
1039 Ops.push_back(getValue(CP->getOperand(i)));
1041 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1042 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1045 if (EltVT.isFloatingPoint())
1046 Op = DAG.getConstantFP(0, EltVT);
1048 Op = DAG.getConstant(0, EltVT);
1049 Ops.assign(NumElements, Op);
1052 // Create a BUILD_VECTOR node.
1053 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1054 VT, &Ops[0], Ops.size());
1057 // If this is a static alloca, generate it as the frameindex instead of
1059 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1060 DenseMap<const AllocaInst*, int>::iterator SI =
1061 FuncInfo.StaticAllocaMap.find(AI);
1062 if (SI != FuncInfo.StaticAllocaMap.end())
1063 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1066 // If this is an instruction which fast-isel has deferred, select it now.
1067 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1068 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1069 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1070 SDValue Chain = DAG.getEntryNode();
1071 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1074 llvm_unreachable("Can't get register for value!");
1078 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1079 SDValue Chain = getControlRoot();
1080 SmallVector<ISD::OutputArg, 8> Outs;
1081 SmallVector<SDValue, 8> OutVals;
1083 if (!FuncInfo.CanLowerReturn) {
1084 unsigned DemoteReg = FuncInfo.DemoteRegister;
1085 const Function *F = I.getParent()->getParent();
1087 // Emit a store of the return value through the virtual register.
1088 // Leave Outs empty so that LowerReturn won't try to load return
1089 // registers the usual way.
1090 SmallVector<EVT, 1> PtrValueVTs;
1091 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1094 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1095 SDValue RetOp = getValue(I.getOperand(0));
1097 SmallVector<EVT, 4> ValueVTs;
1098 SmallVector<uint64_t, 4> Offsets;
1099 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1100 unsigned NumValues = ValueVTs.size();
1102 SmallVector<SDValue, 4> Chains(NumValues);
1103 for (unsigned i = 0; i != NumValues; ++i) {
1104 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1105 RetPtr.getValueType(), RetPtr,
1106 DAG.getIntPtrConstant(Offsets[i]));
1108 DAG.getStore(Chain, getCurDebugLoc(),
1109 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1110 // FIXME: better loc info would be nice.
1111 Add, MachinePointerInfo(), false, false, 0);
1114 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1115 MVT::Other, &Chains[0], NumValues);
1116 } else if (I.getNumOperands() != 0) {
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1119 unsigned NumValues = ValueVTs.size();
1121 SDValue RetOp = getValue(I.getOperand(0));
1122 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1123 EVT VT = ValueVTs[j];
1125 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1127 const Function *F = I.getParent()->getParent();
1128 if (F->paramHasAttr(0, Attribute::SExt))
1129 ExtendKind = ISD::SIGN_EXTEND;
1130 else if (F->paramHasAttr(0, Attribute::ZExt))
1131 ExtendKind = ISD::ZERO_EXTEND;
1133 // FIXME: C calling convention requires the return type to be promoted
1134 // to at least 32-bit. But this is not necessary for non-C calling
1135 // conventions. The frontend should mark functions whose return values
1136 // require promoting with signext or zeroext attributes.
1137 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1138 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1139 if (VT.bitsLT(MinVT))
1143 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1144 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1145 SmallVector<SDValue, 4> Parts(NumParts);
1146 getCopyToParts(DAG, getCurDebugLoc(),
1147 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1148 &Parts[0], NumParts, PartVT, ExtendKind);
1150 // 'inreg' on function refers to return value
1151 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1152 if (F->paramHasAttr(0, Attribute::InReg))
1155 // Propagate extension type if any
1156 if (F->paramHasAttr(0, Attribute::SExt))
1158 else if (F->paramHasAttr(0, Attribute::ZExt))
1161 for (unsigned i = 0; i < NumParts; ++i) {
1162 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1164 OutVals.push_back(Parts[i]);
1170 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1171 CallingConv::ID CallConv =
1172 DAG.getMachineFunction().getFunction()->getCallingConv();
1173 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1174 Outs, OutVals, getCurDebugLoc(), DAG);
1176 // Verify that the target's LowerReturn behaved as expected.
1177 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1178 "LowerReturn didn't return a valid chain!");
1180 // Update the DAG with the new chain value resulting from return lowering.
1184 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1185 /// created for it, emit nodes to copy the value into the virtual
1187 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1188 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1189 if (VMI != FuncInfo.ValueMap.end()) {
1190 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1191 CopyValueToVirtualRegister(V, VMI->second);
1195 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1196 /// the current basic block, add it to ValueMap now so that we'll get a
1198 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1199 // No need to export constants.
1200 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1202 // Already exported?
1203 if (FuncInfo.isExportedInst(V)) return;
1205 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1206 CopyValueToVirtualRegister(V, Reg);
1209 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1210 const BasicBlock *FromBB) {
1211 // The operands of the setcc have to be in this block. We don't know
1212 // how to export them from some other block.
1213 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1214 // Can export from current BB.
1215 if (VI->getParent() == FromBB)
1218 // Is already exported, noop.
1219 return FuncInfo.isExportedInst(V);
1222 // If this is an argument, we can export it if the BB is the entry block or
1223 // if it is already exported.
1224 if (isa<Argument>(V)) {
1225 if (FromBB == &FromBB->getParent()->getEntryBlock())
1228 // Otherwise, can only export this if it is already exported.
1229 return FuncInfo.isExportedInst(V);
1232 // Otherwise, constants can always be exported.
1236 static bool InBlock(const Value *V, const BasicBlock *BB) {
1237 if (const Instruction *I = dyn_cast<Instruction>(V))
1238 return I->getParent() == BB;
1242 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1243 /// This function emits a branch and is used at the leaves of an OR or an
1244 /// AND operator tree.
1247 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1248 MachineBasicBlock *TBB,
1249 MachineBasicBlock *FBB,
1250 MachineBasicBlock *CurBB,
1251 MachineBasicBlock *SwitchBB) {
1252 const BasicBlock *BB = CurBB->getBasicBlock();
1254 // If the leaf of the tree is a comparison, merge the condition into
1256 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1257 // The operands of the cmp have to be in this block. We don't know
1258 // how to export them from some other block. If this is the first block
1259 // of the sequence, no exporting is needed.
1260 if (CurBB == SwitchBB ||
1261 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1262 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1263 ISD::CondCode Condition;
1264 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1265 Condition = getICmpCondCode(IC->getPredicate());
1266 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1267 Condition = getFCmpCondCode(FC->getPredicate());
1269 Condition = ISD::SETEQ; // silence warning.
1270 llvm_unreachable("Unknown compare instruction");
1273 CaseBlock CB(Condition, BOp->getOperand(0),
1274 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1275 SwitchCases.push_back(CB);
1280 // Create a CaseBlock record representing this branch.
1281 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1282 NULL, TBB, FBB, CurBB);
1283 SwitchCases.push_back(CB);
1286 /// FindMergedConditions - If Cond is an expression like
1287 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1288 MachineBasicBlock *TBB,
1289 MachineBasicBlock *FBB,
1290 MachineBasicBlock *CurBB,
1291 MachineBasicBlock *SwitchBB,
1293 // If this node is not part of the or/and tree, emit it as a branch.
1294 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1295 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1296 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1297 BOp->getParent() != CurBB->getBasicBlock() ||
1298 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1299 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1300 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1304 // Create TmpBB after CurBB.
1305 MachineFunction::iterator BBI = CurBB;
1306 MachineFunction &MF = DAG.getMachineFunction();
1307 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1308 CurBB->getParent()->insert(++BBI, TmpBB);
1310 if (Opc == Instruction::Or) {
1311 // Codegen X | Y as:
1319 // Emit the LHS condition.
1320 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1322 // Emit the RHS condition into TmpBB.
1323 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1325 assert(Opc == Instruction::And && "Unknown merge op!");
1326 // Codegen X & Y as:
1333 // This requires creation of TmpBB after CurBB.
1335 // Emit the LHS condition.
1336 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1338 // Emit the RHS condition into TmpBB.
1339 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1343 /// If the set of cases should be emitted as a series of branches, return true.
1344 /// If we should emit this as a bunch of and/or'd together conditions, return
1347 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1348 if (Cases.size() != 2) return true;
1350 // If this is two comparisons of the same values or'd or and'd together, they
1351 // will get folded into a single comparison, so don't emit two blocks.
1352 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1353 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1354 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1355 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1359 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1360 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1361 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1362 Cases[0].CC == Cases[1].CC &&
1363 isa<Constant>(Cases[0].CmpRHS) &&
1364 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1365 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1367 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1374 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1375 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1377 // Update machine-CFG edges.
1378 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1380 // Figure out which block is immediately after the current one.
1381 MachineBasicBlock *NextBlock = 0;
1382 MachineFunction::iterator BBI = BrMBB;
1383 if (++BBI != FuncInfo.MF->end())
1386 if (I.isUnconditional()) {
1387 // Update machine-CFG edges.
1388 BrMBB->addSuccessor(Succ0MBB);
1390 // If this is not a fall-through branch, emit the branch.
1391 if (Succ0MBB != NextBlock)
1392 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1393 MVT::Other, getControlRoot(),
1394 DAG.getBasicBlock(Succ0MBB)));
1399 // If this condition is one of the special cases we handle, do special stuff
1401 const Value *CondVal = I.getCondition();
1402 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1404 // If this is a series of conditions that are or'd or and'd together, emit
1405 // this as a sequence of branches instead of setcc's with and/or operations.
1406 // As long as jumps are not expensive, this should improve performance.
1407 // For example, instead of something like:
1420 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1421 if (!TLI.isJumpExpensive() &&
1423 (BOp->getOpcode() == Instruction::And ||
1424 BOp->getOpcode() == Instruction::Or)) {
1425 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1427 // If the compares in later blocks need to use values not currently
1428 // exported from this block, export them now. This block should always
1429 // be the first entry.
1430 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1432 // Allow some cases to be rejected.
1433 if (ShouldEmitAsBranches(SwitchCases)) {
1434 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1435 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1436 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1439 // Emit the branch for this block.
1440 visitSwitchCase(SwitchCases[0], BrMBB);
1441 SwitchCases.erase(SwitchCases.begin());
1445 // Okay, we decided not to do this, remove any inserted MBB's and clear
1447 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1448 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1450 SwitchCases.clear();
1454 // Create a CaseBlock record representing this branch.
1455 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1456 NULL, Succ0MBB, Succ1MBB, BrMBB);
1458 // Use visitSwitchCase to actually insert the fast branch sequence for this
1460 visitSwitchCase(CB, BrMBB);
1463 /// visitSwitchCase - Emits the necessary code to represent a single node in
1464 /// the binary search tree resulting from lowering a switch instruction.
1465 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1466 MachineBasicBlock *SwitchBB) {
1468 SDValue CondLHS = getValue(CB.CmpLHS);
1469 DebugLoc dl = getCurDebugLoc();
1471 // Build the setcc now.
1472 if (CB.CmpMHS == NULL) {
1473 // Fold "(X == true)" to X and "(X == false)" to !X to
1474 // handle common cases produced by branch lowering.
1475 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1476 CB.CC == ISD::SETEQ)
1478 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1479 CB.CC == ISD::SETEQ) {
1480 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1481 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1483 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1485 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1487 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1488 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1490 SDValue CmpOp = getValue(CB.CmpMHS);
1491 EVT VT = CmpOp.getValueType();
1493 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1494 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1497 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1498 VT, CmpOp, DAG.getConstant(Low, VT));
1499 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1500 DAG.getConstant(High-Low, VT), ISD::SETULE);
1504 // Update successor info
1505 SwitchBB->addSuccessor(CB.TrueBB);
1506 SwitchBB->addSuccessor(CB.FalseBB);
1508 // Set NextBlock to be the MBB immediately after the current one, if any.
1509 // This is used to avoid emitting unnecessary branches to the next block.
1510 MachineBasicBlock *NextBlock = 0;
1511 MachineFunction::iterator BBI = SwitchBB;
1512 if (++BBI != FuncInfo.MF->end())
1515 // If the lhs block is the next block, invert the condition so that we can
1516 // fall through to the lhs instead of the rhs block.
1517 if (CB.TrueBB == NextBlock) {
1518 std::swap(CB.TrueBB, CB.FalseBB);
1519 SDValue True = DAG.getConstant(1, Cond.getValueType());
1520 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1523 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1524 MVT::Other, getControlRoot(), Cond,
1525 DAG.getBasicBlock(CB.TrueBB));
1527 // Insert the false branch. Do this even if it's a fall through branch,
1528 // this makes it easier to do DAG optimizations which require inverting
1529 // the branch condition.
1530 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1531 DAG.getBasicBlock(CB.FalseBB));
1533 DAG.setRoot(BrCond);
1536 /// visitJumpTable - Emit JumpTable node in the current MBB
1537 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1538 // Emit the code for the jump table
1539 assert(JT.Reg != -1U && "Should lower JT Header first!");
1540 EVT PTy = TLI.getPointerTy();
1541 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1543 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1544 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1545 MVT::Other, Index.getValue(1),
1547 DAG.setRoot(BrJumpTable);
1550 /// visitJumpTableHeader - This function emits necessary code to produce index
1551 /// in the JumpTable from switch case.
1552 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1553 JumpTableHeader &JTH,
1554 MachineBasicBlock *SwitchBB) {
1555 // Subtract the lowest switch case value from the value being switched on and
1556 // conditional branch to default mbb if the result is greater than the
1557 // difference between smallest and largest cases.
1558 SDValue SwitchOp = getValue(JTH.SValue);
1559 EVT VT = SwitchOp.getValueType();
1560 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1561 DAG.getConstant(JTH.First, VT));
1563 // The SDNode we just created, which holds the value being switched on minus
1564 // the smallest case value, needs to be copied to a virtual register so it
1565 // can be used as an index into the jump table in a subsequent basic block.
1566 // This value may be smaller or larger than the target's pointer type, and
1567 // therefore require extension or truncating.
1568 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1570 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1571 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1572 JumpTableReg, SwitchOp);
1573 JT.Reg = JumpTableReg;
1575 // Emit the range check for the jump table, and branch to the default block
1576 // for the switch statement if the value being switched on exceeds the largest
1577 // case in the switch.
1578 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1579 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1580 DAG.getConstant(JTH.Last-JTH.First,VT),
1583 // Set NextBlock to be the MBB immediately after the current one, if any.
1584 // This is used to avoid emitting unnecessary branches to the next block.
1585 MachineBasicBlock *NextBlock = 0;
1586 MachineFunction::iterator BBI = SwitchBB;
1588 if (++BBI != FuncInfo.MF->end())
1591 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1592 MVT::Other, CopyTo, CMP,
1593 DAG.getBasicBlock(JT.Default));
1595 if (JT.MBB != NextBlock)
1596 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1597 DAG.getBasicBlock(JT.MBB));
1599 DAG.setRoot(BrCond);
1602 /// visitBitTestHeader - This function emits necessary code to produce value
1603 /// suitable for "bit tests"
1604 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1605 MachineBasicBlock *SwitchBB) {
1606 // Subtract the minimum value
1607 SDValue SwitchOp = getValue(B.SValue);
1608 EVT VT = SwitchOp.getValueType();
1609 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1610 DAG.getConstant(B.First, VT));
1613 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1614 TLI.getSetCCResultType(Sub.getValueType()),
1615 Sub, DAG.getConstant(B.Range, VT),
1618 // Determine the type of the test operands.
1619 bool UsePtrType = false;
1620 if (!TLI.isTypeLegal(VT))
1623 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1624 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1625 // Switch table case range are encoded into series of masks.
1626 // Just use pointer type, it's guaranteed to fit.
1632 VT = TLI.getPointerTy();
1633 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1637 B.Reg = FuncInfo.CreateReg(VT);
1638 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1641 // Set NextBlock to be the MBB immediately after the current one, if any.
1642 // This is used to avoid emitting unnecessary branches to the next block.
1643 MachineBasicBlock *NextBlock = 0;
1644 MachineFunction::iterator BBI = SwitchBB;
1645 if (++BBI != FuncInfo.MF->end())
1648 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1650 SwitchBB->addSuccessor(B.Default);
1651 SwitchBB->addSuccessor(MBB);
1653 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1654 MVT::Other, CopyTo, RangeCmp,
1655 DAG.getBasicBlock(B.Default));
1657 if (MBB != NextBlock)
1658 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1659 DAG.getBasicBlock(MBB));
1661 DAG.setRoot(BrRange);
1664 /// visitBitTestCase - this function produces one "bit test"
1665 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1666 MachineBasicBlock* NextMBB,
1669 MachineBasicBlock *SwitchBB) {
1671 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1674 if (CountPopulation_64(B.Mask) == 1) {
1675 // Testing for a single bit; just compare the shift count with what it
1676 // would need to be to shift a 1 bit in that position.
1677 Cmp = DAG.getSetCC(getCurDebugLoc(),
1678 TLI.getSetCCResultType(VT),
1680 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1683 // Make desired shift
1684 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1685 DAG.getConstant(1, VT), ShiftOp);
1687 // Emit bit tests and jumps
1688 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1689 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1690 Cmp = DAG.getSetCC(getCurDebugLoc(),
1691 TLI.getSetCCResultType(VT),
1692 AndOp, DAG.getConstant(0, VT),
1696 SwitchBB->addSuccessor(B.TargetBB);
1697 SwitchBB->addSuccessor(NextMBB);
1699 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1700 MVT::Other, getControlRoot(),
1701 Cmp, DAG.getBasicBlock(B.TargetBB));
1703 // Set NextBlock to be the MBB immediately after the current one, if any.
1704 // This is used to avoid emitting unnecessary branches to the next block.
1705 MachineBasicBlock *NextBlock = 0;
1706 MachineFunction::iterator BBI = SwitchBB;
1707 if (++BBI != FuncInfo.MF->end())
1710 if (NextMBB != NextBlock)
1711 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1712 DAG.getBasicBlock(NextMBB));
1717 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1718 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1720 // Retrieve successors.
1721 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1722 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1724 const Value *Callee(I.getCalledValue());
1725 if (isa<InlineAsm>(Callee))
1728 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1730 // If the value of the invoke is used outside of its defining block, make it
1731 // available as a virtual register.
1732 CopyToExportRegsIfNeeded(&I);
1734 // Update successor info
1735 InvokeMBB->addSuccessor(Return);
1736 InvokeMBB->addSuccessor(LandingPad);
1738 // Drop into normal successor.
1739 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1740 MVT::Other, getControlRoot(),
1741 DAG.getBasicBlock(Return)));
1744 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1747 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1748 /// small case ranges).
1749 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1750 CaseRecVector& WorkList,
1752 MachineBasicBlock *Default,
1753 MachineBasicBlock *SwitchBB) {
1754 Case& BackCase = *(CR.Range.second-1);
1756 // Size is the number of Cases represented by this range.
1757 size_t Size = CR.Range.second - CR.Range.first;
1761 // Get the MachineFunction which holds the current MBB. This is used when
1762 // inserting any additional MBBs necessary to represent the switch.
1763 MachineFunction *CurMF = FuncInfo.MF;
1765 // Figure out which block is immediately after the current one.
1766 MachineBasicBlock *NextBlock = 0;
1767 MachineFunction::iterator BBI = CR.CaseBB;
1769 if (++BBI != FuncInfo.MF->end())
1772 // If any two of the cases has the same destination, and if one value
1773 // is the same as the other, but has one bit unset that the other has set,
1774 // use bit manipulation to do two compares at once. For example:
1775 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1776 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1777 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1778 if (Size == 2 && CR.CaseBB == SwitchBB) {
1779 Case &Small = *CR.Range.first;
1780 Case &Big = *(CR.Range.second-1);
1782 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1783 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1784 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1786 // Check that there is only one bit different.
1787 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1788 (SmallValue | BigValue) == BigValue) {
1789 // Isolate the common bit.
1790 APInt CommonBit = BigValue & ~SmallValue;
1791 assert((SmallValue | CommonBit) == BigValue &&
1792 CommonBit.countPopulation() == 1 && "Not a common bit?");
1794 SDValue CondLHS = getValue(SV);
1795 EVT VT = CondLHS.getValueType();
1796 DebugLoc DL = getCurDebugLoc();
1798 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1799 DAG.getConstant(CommonBit, VT));
1800 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1801 Or, DAG.getConstant(BigValue, VT),
1804 // Update successor info.
1805 SwitchBB->addSuccessor(Small.BB);
1806 SwitchBB->addSuccessor(Default);
1808 // Insert the true branch.
1809 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1810 getControlRoot(), Cond,
1811 DAG.getBasicBlock(Small.BB));
1813 // Insert the false branch.
1814 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1815 DAG.getBasicBlock(Default));
1817 DAG.setRoot(BrCond);
1823 // Rearrange the case blocks so that the last one falls through if possible.
1824 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1825 // The last case block won't fall through into 'NextBlock' if we emit the
1826 // branches in this order. See if rearranging a case value would help.
1827 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1828 if (I->BB == NextBlock) {
1829 std::swap(*I, BackCase);
1835 // Create a CaseBlock record representing a conditional branch to
1836 // the Case's target mbb if the value being switched on SV is equal
1838 MachineBasicBlock *CurBlock = CR.CaseBB;
1839 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1840 MachineBasicBlock *FallThrough;
1842 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1843 CurMF->insert(BBI, FallThrough);
1845 // Put SV in a virtual register to make it available from the new blocks.
1846 ExportFromCurrentBlock(SV);
1848 // If the last case doesn't match, go to the default block.
1849 FallThrough = Default;
1852 const Value *RHS, *LHS, *MHS;
1854 if (I->High == I->Low) {
1855 // This is just small small case range :) containing exactly 1 case
1857 LHS = SV; RHS = I->High; MHS = NULL;
1860 LHS = I->Low; MHS = SV; RHS = I->High;
1862 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1864 // If emitting the first comparison, just call visitSwitchCase to emit the
1865 // code into the current block. Otherwise, push the CaseBlock onto the
1866 // vector to be later processed by SDISel, and insert the node's MBB
1867 // before the next MBB.
1868 if (CurBlock == SwitchBB)
1869 visitSwitchCase(CB, SwitchBB);
1871 SwitchCases.push_back(CB);
1873 CurBlock = FallThrough;
1879 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1880 return !DisableJumpTables &&
1881 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1882 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1885 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1886 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1887 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1888 return (LastExt - FirstExt + 1ULL);
1891 /// handleJTSwitchCase - Emit jumptable for current switch case range
1892 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1893 CaseRecVector& WorkList,
1895 MachineBasicBlock* Default,
1896 MachineBasicBlock *SwitchBB) {
1897 Case& FrontCase = *CR.Range.first;
1898 Case& BackCase = *(CR.Range.second-1);
1900 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1901 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1903 APInt TSize(First.getBitWidth(), 0);
1904 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1908 if (!areJTsAllowed(TLI) || TSize.ult(4))
1911 APInt Range = ComputeRange(First, Last);
1912 double Density = TSize.roundToDouble() / Range.roundToDouble();
1916 DEBUG(dbgs() << "Lowering jump table\n"
1917 << "First entry: " << First << ". Last entry: " << Last << '\n'
1918 << "Range: " << Range
1919 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1921 // Get the MachineFunction which holds the current MBB. This is used when
1922 // inserting any additional MBBs necessary to represent the switch.
1923 MachineFunction *CurMF = FuncInfo.MF;
1925 // Figure out which block is immediately after the current one.
1926 MachineFunction::iterator BBI = CR.CaseBB;
1929 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1931 // Create a new basic block to hold the code for loading the address
1932 // of the jump table, and jumping to it. Update successor information;
1933 // we will either branch to the default case for the switch, or the jump
1935 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1936 CurMF->insert(BBI, JumpTableBB);
1937 CR.CaseBB->addSuccessor(Default);
1938 CR.CaseBB->addSuccessor(JumpTableBB);
1940 // Build a vector of destination BBs, corresponding to each target
1941 // of the jump table. If the value of the jump table slot corresponds to
1942 // a case statement, push the case's BB onto the vector, otherwise, push
1944 std::vector<MachineBasicBlock*> DestBBs;
1946 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1947 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1948 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1950 if (Low.sle(TEI) && TEI.sle(High)) {
1951 DestBBs.push_back(I->BB);
1955 DestBBs.push_back(Default);
1959 // Update successor info. Add one edge to each unique successor.
1960 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1961 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1962 E = DestBBs.end(); I != E; ++I) {
1963 if (!SuccsHandled[(*I)->getNumber()]) {
1964 SuccsHandled[(*I)->getNumber()] = true;
1965 JumpTableBB->addSuccessor(*I);
1969 // Create a jump table index for this jump table.
1970 unsigned JTEncoding = TLI.getJumpTableEncoding();
1971 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1972 ->createJumpTableIndex(DestBBs);
1974 // Set the jump table information so that we can codegen it as a second
1975 // MachineBasicBlock
1976 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1977 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1978 if (CR.CaseBB == SwitchBB)
1979 visitJumpTableHeader(JT, JTH, SwitchBB);
1981 JTCases.push_back(JumpTableBlock(JTH, JT));
1986 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1988 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1989 CaseRecVector& WorkList,
1991 MachineBasicBlock *Default,
1992 MachineBasicBlock *SwitchBB) {
1993 // Get the MachineFunction which holds the current MBB. This is used when
1994 // inserting any additional MBBs necessary to represent the switch.
1995 MachineFunction *CurMF = FuncInfo.MF;
1997 // Figure out which block is immediately after the current one.
1998 MachineFunction::iterator BBI = CR.CaseBB;
2001 Case& FrontCase = *CR.Range.first;
2002 Case& BackCase = *(CR.Range.second-1);
2003 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2005 // Size is the number of Cases represented by this range.
2006 unsigned Size = CR.Range.second - CR.Range.first;
2008 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2009 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2011 CaseItr Pivot = CR.Range.first + Size/2;
2013 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2014 // (heuristically) allow us to emit JumpTable's later.
2015 APInt TSize(First.getBitWidth(), 0);
2016 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2020 APInt LSize = FrontCase.size();
2021 APInt RSize = TSize-LSize;
2022 DEBUG(dbgs() << "Selecting best pivot: \n"
2023 << "First: " << First << ", Last: " << Last <<'\n'
2024 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2025 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2027 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2028 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2029 APInt Range = ComputeRange(LEnd, RBegin);
2030 assert((Range - 2ULL).isNonNegative() &&
2031 "Invalid case distance");
2032 double LDensity = (double)LSize.roundToDouble() /
2033 (LEnd - First + 1ULL).roundToDouble();
2034 double RDensity = (double)RSize.roundToDouble() /
2035 (Last - RBegin + 1ULL).roundToDouble();
2036 double Metric = Range.logBase2()*(LDensity+RDensity);
2037 // Should always split in some non-trivial place
2038 DEBUG(dbgs() <<"=>Step\n"
2039 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2040 << "LDensity: " << LDensity
2041 << ", RDensity: " << RDensity << '\n'
2042 << "Metric: " << Metric << '\n');
2043 if (FMetric < Metric) {
2046 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2052 if (areJTsAllowed(TLI)) {
2053 // If our case is dense we *really* should handle it earlier!
2054 assert((FMetric > 0) && "Should handle dense range earlier!");
2056 Pivot = CR.Range.first + Size/2;
2059 CaseRange LHSR(CR.Range.first, Pivot);
2060 CaseRange RHSR(Pivot, CR.Range.second);
2061 Constant *C = Pivot->Low;
2062 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2064 // We know that we branch to the LHS if the Value being switched on is
2065 // less than the Pivot value, C. We use this to optimize our binary
2066 // tree a bit, by recognizing that if SV is greater than or equal to the
2067 // LHS's Case Value, and that Case Value is exactly one less than the
2068 // Pivot's Value, then we can branch directly to the LHS's Target,
2069 // rather than creating a leaf node for it.
2070 if ((LHSR.second - LHSR.first) == 1 &&
2071 LHSR.first->High == CR.GE &&
2072 cast<ConstantInt>(C)->getValue() ==
2073 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2074 TrueBB = LHSR.first->BB;
2076 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2077 CurMF->insert(BBI, TrueBB);
2078 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2080 // Put SV in a virtual register to make it available from the new blocks.
2081 ExportFromCurrentBlock(SV);
2084 // Similar to the optimization above, if the Value being switched on is
2085 // known to be less than the Constant CR.LT, and the current Case Value
2086 // is CR.LT - 1, then we can branch directly to the target block for
2087 // the current Case Value, rather than emitting a RHS leaf node for it.
2088 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2089 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2090 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2091 FalseBB = RHSR.first->BB;
2093 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2094 CurMF->insert(BBI, FalseBB);
2095 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2097 // Put SV in a virtual register to make it available from the new blocks.
2098 ExportFromCurrentBlock(SV);
2101 // Create a CaseBlock record representing a conditional branch to
2102 // the LHS node if the value being switched on SV is less than C.
2103 // Otherwise, branch to LHS.
2104 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2106 if (CR.CaseBB == SwitchBB)
2107 visitSwitchCase(CB, SwitchBB);
2109 SwitchCases.push_back(CB);
2114 /// handleBitTestsSwitchCase - if current case range has few destination and
2115 /// range span less, than machine word bitwidth, encode case range into series
2116 /// of masks and emit bit tests with these masks.
2117 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2118 CaseRecVector& WorkList,
2120 MachineBasicBlock* Default,
2121 MachineBasicBlock *SwitchBB){
2122 EVT PTy = TLI.getPointerTy();
2123 unsigned IntPtrBits = PTy.getSizeInBits();
2125 Case& FrontCase = *CR.Range.first;
2126 Case& BackCase = *(CR.Range.second-1);
2128 // Get the MachineFunction which holds the current MBB. This is used when
2129 // inserting any additional MBBs necessary to represent the switch.
2130 MachineFunction *CurMF = FuncInfo.MF;
2132 // If target does not have legal shift left, do not emit bit tests at all.
2133 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2137 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2139 // Single case counts one, case range - two.
2140 numCmps += (I->Low == I->High ? 1 : 2);
2143 // Count unique destinations
2144 SmallSet<MachineBasicBlock*, 4> Dests;
2145 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2146 Dests.insert(I->BB);
2147 if (Dests.size() > 3)
2148 // Don't bother the code below, if there are too much unique destinations
2151 DEBUG(dbgs() << "Total number of unique destinations: "
2152 << Dests.size() << '\n'
2153 << "Total number of comparisons: " << numCmps << '\n');
2155 // Compute span of values.
2156 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2157 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2158 APInt cmpRange = maxValue - minValue;
2160 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2161 << "Low bound: " << minValue << '\n'
2162 << "High bound: " << maxValue << '\n');
2164 if (cmpRange.uge(IntPtrBits) ||
2165 (!(Dests.size() == 1 && numCmps >= 3) &&
2166 !(Dests.size() == 2 && numCmps >= 5) &&
2167 !(Dests.size() >= 3 && numCmps >= 6)))
2170 DEBUG(dbgs() << "Emitting bit tests\n");
2171 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2173 // Optimize the case where all the case values fit in a
2174 // word without having to subtract minValue. In this case,
2175 // we can optimize away the subtraction.
2176 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2177 cmpRange = maxValue;
2179 lowBound = minValue;
2182 CaseBitsVector CasesBits;
2183 unsigned i, count = 0;
2185 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2186 MachineBasicBlock* Dest = I->BB;
2187 for (i = 0; i < count; ++i)
2188 if (Dest == CasesBits[i].BB)
2192 assert((count < 3) && "Too much destinations to test!");
2193 CasesBits.push_back(CaseBits(0, Dest, 0));
2197 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2198 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2200 uint64_t lo = (lowValue - lowBound).getZExtValue();
2201 uint64_t hi = (highValue - lowBound).getZExtValue();
2203 for (uint64_t j = lo; j <= hi; j++) {
2204 CasesBits[i].Mask |= 1ULL << j;
2205 CasesBits[i].Bits++;
2209 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2213 // Figure out which block is immediately after the current one.
2214 MachineFunction::iterator BBI = CR.CaseBB;
2217 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2219 DEBUG(dbgs() << "Cases:\n");
2220 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2221 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2222 << ", Bits: " << CasesBits[i].Bits
2223 << ", BB: " << CasesBits[i].BB << '\n');
2225 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2226 CurMF->insert(BBI, CaseBB);
2227 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2231 // Put SV in a virtual register to make it available from the new blocks.
2232 ExportFromCurrentBlock(SV);
2235 BitTestBlock BTB(lowBound, cmpRange, SV,
2236 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2237 CR.CaseBB, Default, BTC);
2239 if (CR.CaseBB == SwitchBB)
2240 visitBitTestHeader(BTB, SwitchBB);
2242 BitTestCases.push_back(BTB);
2247 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2248 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2249 const SwitchInst& SI) {
2252 // Start with "simple" cases
2253 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2254 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2255 Cases.push_back(Case(SI.getSuccessorValue(i),
2256 SI.getSuccessorValue(i),
2259 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2261 // Merge case into clusters
2262 if (Cases.size() >= 2)
2263 // Must recompute end() each iteration because it may be
2264 // invalidated by erase if we hold on to it
2265 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2266 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2267 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2268 MachineBasicBlock* nextBB = J->BB;
2269 MachineBasicBlock* currentBB = I->BB;
2271 // If the two neighboring cases go to the same destination, merge them
2272 // into a single case.
2273 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2281 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2282 if (I->Low != I->High)
2283 // A range counts double, since it requires two compares.
2290 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2291 MachineBasicBlock *Last) {
2293 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2294 if (JTCases[i].first.HeaderBB == First)
2295 JTCases[i].first.HeaderBB = Last;
2297 // Update BitTestCases.
2298 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2299 if (BitTestCases[i].Parent == First)
2300 BitTestCases[i].Parent = Last;
2303 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2304 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2306 // Figure out which block is immediately after the current one.
2307 MachineBasicBlock *NextBlock = 0;
2308 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2310 // If there is only the default destination, branch to it if it is not the
2311 // next basic block. Otherwise, just fall through.
2312 if (SI.getNumOperands() == 2) {
2313 // Update machine-CFG edges.
2315 // If this is not a fall-through branch, emit the branch.
2316 SwitchMBB->addSuccessor(Default);
2317 if (Default != NextBlock)
2318 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2319 MVT::Other, getControlRoot(),
2320 DAG.getBasicBlock(Default)));
2325 // If there are any non-default case statements, create a vector of Cases
2326 // representing each one, and sort the vector so that we can efficiently
2327 // create a binary search tree from them.
2329 size_t numCmps = Clusterify(Cases, SI);
2330 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2331 << ". Total compares: " << numCmps << '\n');
2334 // Get the Value to be switched on and default basic blocks, which will be
2335 // inserted into CaseBlock records, representing basic blocks in the binary
2337 const Value *SV = SI.getOperand(0);
2339 // Push the initial CaseRec onto the worklist
2340 CaseRecVector WorkList;
2341 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2342 CaseRange(Cases.begin(),Cases.end())));
2344 while (!WorkList.empty()) {
2345 // Grab a record representing a case range to process off the worklist
2346 CaseRec CR = WorkList.back();
2347 WorkList.pop_back();
2349 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2352 // If the range has few cases (two or less) emit a series of specific
2354 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2357 // If the switch has more than 5 blocks, and at least 40% dense, and the
2358 // target supports indirect branches, then emit a jump table rather than
2359 // lowering the switch to a binary tree of conditional branches.
2360 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2363 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2364 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2365 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2369 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2370 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2372 // Update machine-CFG edges with unique successors.
2373 SmallVector<BasicBlock*, 32> succs;
2374 succs.reserve(I.getNumSuccessors());
2375 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2376 succs.push_back(I.getSuccessor(i));
2377 array_pod_sort(succs.begin(), succs.end());
2378 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2379 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2380 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2382 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2383 MVT::Other, getControlRoot(),
2384 getValue(I.getAddress())));
2387 void SelectionDAGBuilder::visitFSub(const User &I) {
2388 // -0.0 - X --> fneg
2389 const Type *Ty = I.getType();
2390 if (Ty->isVectorTy()) {
2391 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2392 const VectorType *DestTy = cast<VectorType>(I.getType());
2393 const Type *ElTy = DestTy->getElementType();
2394 unsigned VL = DestTy->getNumElements();
2395 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2396 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2398 SDValue Op2 = getValue(I.getOperand(1));
2399 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2400 Op2.getValueType(), Op2));
2406 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2407 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2408 SDValue Op2 = getValue(I.getOperand(1));
2409 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2410 Op2.getValueType(), Op2));
2414 visitBinary(I, ISD::FSUB);
2417 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2418 SDValue Op1 = getValue(I.getOperand(0));
2419 SDValue Op2 = getValue(I.getOperand(1));
2420 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2421 Op1.getValueType(), Op1, Op2));
2424 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2425 SDValue Op1 = getValue(I.getOperand(0));
2426 SDValue Op2 = getValue(I.getOperand(1));
2427 if (!I.getType()->isVectorTy() &&
2428 Op2.getValueType() != TLI.getShiftAmountTy()) {
2429 // If the operand is smaller than the shift count type, promote it.
2430 EVT PTy = TLI.getPointerTy();
2431 EVT STy = TLI.getShiftAmountTy();
2432 if (STy.bitsGT(Op2.getValueType()))
2433 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2434 TLI.getShiftAmountTy(), Op2);
2435 // If the operand is larger than the shift count type but the shift
2436 // count type has enough bits to represent any shift value, truncate
2437 // it now. This is a common case and it exposes the truncate to
2438 // optimization early.
2439 else if (STy.getSizeInBits() >=
2440 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2441 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2442 TLI.getShiftAmountTy(), Op2);
2443 // Otherwise we'll need to temporarily settle for some other
2444 // convenient type; type legalization will make adjustments as
2446 else if (PTy.bitsLT(Op2.getValueType()))
2447 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2448 TLI.getPointerTy(), Op2);
2449 else if (PTy.bitsGT(Op2.getValueType()))
2450 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2451 TLI.getPointerTy(), Op2);
2454 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2455 Op1.getValueType(), Op1, Op2));
2458 void SelectionDAGBuilder::visitICmp(const User &I) {
2459 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2460 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2461 predicate = IC->getPredicate();
2462 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2463 predicate = ICmpInst::Predicate(IC->getPredicate());
2464 SDValue Op1 = getValue(I.getOperand(0));
2465 SDValue Op2 = getValue(I.getOperand(1));
2466 ISD::CondCode Opcode = getICmpCondCode(predicate);
2468 EVT DestVT = TLI.getValueType(I.getType());
2469 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2472 void SelectionDAGBuilder::visitFCmp(const User &I) {
2473 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2474 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2475 predicate = FC->getPredicate();
2476 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2477 predicate = FCmpInst::Predicate(FC->getPredicate());
2478 SDValue Op1 = getValue(I.getOperand(0));
2479 SDValue Op2 = getValue(I.getOperand(1));
2480 ISD::CondCode Condition = getFCmpCondCode(predicate);
2481 EVT DestVT = TLI.getValueType(I.getType());
2482 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2485 void SelectionDAGBuilder::visitSelect(const User &I) {
2486 SmallVector<EVT, 4> ValueVTs;
2487 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2488 unsigned NumValues = ValueVTs.size();
2489 if (NumValues == 0) return;
2491 SmallVector<SDValue, 4> Values(NumValues);
2492 SDValue Cond = getValue(I.getOperand(0));
2493 SDValue TrueVal = getValue(I.getOperand(1));
2494 SDValue FalseVal = getValue(I.getOperand(2));
2496 for (unsigned i = 0; i != NumValues; ++i)
2497 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2498 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2500 SDValue(TrueVal.getNode(),
2501 TrueVal.getResNo() + i),
2502 SDValue(FalseVal.getNode(),
2503 FalseVal.getResNo() + i));
2505 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2506 DAG.getVTList(&ValueVTs[0], NumValues),
2507 &Values[0], NumValues));
2510 void SelectionDAGBuilder::visitTrunc(const User &I) {
2511 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2512 SDValue N = getValue(I.getOperand(0));
2513 EVT DestVT = TLI.getValueType(I.getType());
2514 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2517 void SelectionDAGBuilder::visitZExt(const User &I) {
2518 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2519 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2520 SDValue N = getValue(I.getOperand(0));
2521 EVT DestVT = TLI.getValueType(I.getType());
2522 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2525 void SelectionDAGBuilder::visitSExt(const User &I) {
2526 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2527 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2528 SDValue N = getValue(I.getOperand(0));
2529 EVT DestVT = TLI.getValueType(I.getType());
2530 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2533 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2534 // FPTrunc is never a no-op cast, no need to check
2535 SDValue N = getValue(I.getOperand(0));
2536 EVT DestVT = TLI.getValueType(I.getType());
2537 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2538 DestVT, N, DAG.getIntPtrConstant(0)));
2541 void SelectionDAGBuilder::visitFPExt(const User &I){
2542 // FPTrunc is never a no-op cast, no need to check
2543 SDValue N = getValue(I.getOperand(0));
2544 EVT DestVT = TLI.getValueType(I.getType());
2545 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2548 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2549 // FPToUI is never a no-op cast, no need to check
2550 SDValue N = getValue(I.getOperand(0));
2551 EVT DestVT = TLI.getValueType(I.getType());
2552 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2555 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2556 // FPToSI is never a no-op cast, no need to check
2557 SDValue N = getValue(I.getOperand(0));
2558 EVT DestVT = TLI.getValueType(I.getType());
2559 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2562 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2563 // UIToFP is never a no-op cast, no need to check
2564 SDValue N = getValue(I.getOperand(0));
2565 EVT DestVT = TLI.getValueType(I.getType());
2566 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2569 void SelectionDAGBuilder::visitSIToFP(const User &I){
2570 // SIToFP is never a no-op cast, no need to check
2571 SDValue N = getValue(I.getOperand(0));
2572 EVT DestVT = TLI.getValueType(I.getType());
2573 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2576 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2577 // What to do depends on the size of the integer and the size of the pointer.
2578 // We can either truncate, zero extend, or no-op, accordingly.
2579 SDValue N = getValue(I.getOperand(0));
2580 EVT DestVT = TLI.getValueType(I.getType());
2581 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2584 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2585 // What to do depends on the size of the integer and the size of the pointer.
2586 // We can either truncate, zero extend, or no-op, accordingly.
2587 SDValue N = getValue(I.getOperand(0));
2588 EVT DestVT = TLI.getValueType(I.getType());
2589 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2592 void SelectionDAGBuilder::visitBitCast(const User &I) {
2593 SDValue N = getValue(I.getOperand(0));
2594 EVT DestVT = TLI.getValueType(I.getType());
2596 // BitCast assures us that source and destination are the same size so this is
2597 // either a BITCAST or a no-op.
2598 if (DestVT != N.getValueType())
2599 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2600 DestVT, N)); // convert types.
2602 setValue(&I, N); // noop cast.
2605 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2606 SDValue InVec = getValue(I.getOperand(0));
2607 SDValue InVal = getValue(I.getOperand(1));
2608 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2610 getValue(I.getOperand(2)));
2611 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2612 TLI.getValueType(I.getType()),
2613 InVec, InVal, InIdx));
2616 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2617 SDValue InVec = getValue(I.getOperand(0));
2618 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2620 getValue(I.getOperand(1)));
2621 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2622 TLI.getValueType(I.getType()), InVec, InIdx));
2625 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2626 // from SIndx and increasing to the element length (undefs are allowed).
2627 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2628 unsigned MaskNumElts = Mask.size();
2629 for (unsigned i = 0; i != MaskNumElts; ++i)
2630 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2635 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2636 SmallVector<int, 8> Mask;
2637 SDValue Src1 = getValue(I.getOperand(0));
2638 SDValue Src2 = getValue(I.getOperand(1));
2640 // Convert the ConstantVector mask operand into an array of ints, with -1
2641 // representing undef values.
2642 SmallVector<Constant*, 8> MaskElts;
2643 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2644 unsigned MaskNumElts = MaskElts.size();
2645 for (unsigned i = 0; i != MaskNumElts; ++i) {
2646 if (isa<UndefValue>(MaskElts[i]))
2649 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2652 EVT VT = TLI.getValueType(I.getType());
2653 EVT SrcVT = Src1.getValueType();
2654 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2656 if (SrcNumElts == MaskNumElts) {
2657 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2662 // Normalize the shuffle vector since mask and vector length don't match.
2663 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2664 // Mask is longer than the source vectors and is a multiple of the source
2665 // vectors. We can use concatenate vector to make the mask and vectors
2667 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2668 // The shuffle is concatenating two vectors together.
2669 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2674 // Pad both vectors with undefs to make them the same length as the mask.
2675 unsigned NumConcat = MaskNumElts / SrcNumElts;
2676 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2677 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2678 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2680 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2681 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2685 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2686 getCurDebugLoc(), VT,
2687 &MOps1[0], NumConcat);
2688 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2689 getCurDebugLoc(), VT,
2690 &MOps2[0], NumConcat);
2692 // Readjust mask for new input vector length.
2693 SmallVector<int, 8> MappedOps;
2694 for (unsigned i = 0; i != MaskNumElts; ++i) {
2696 if (Idx < (int)SrcNumElts)
2697 MappedOps.push_back(Idx);
2699 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2702 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2707 if (SrcNumElts > MaskNumElts) {
2708 // Analyze the access pattern of the vector to see if we can extract
2709 // two subvectors and do the shuffle. The analysis is done by calculating
2710 // the range of elements the mask access on both vectors.
2711 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2712 int MaxRange[2] = {-1, -1};
2714 for (unsigned i = 0; i != MaskNumElts; ++i) {
2720 if (Idx >= (int)SrcNumElts) {
2724 if (Idx > MaxRange[Input])
2725 MaxRange[Input] = Idx;
2726 if (Idx < MinRange[Input])
2727 MinRange[Input] = Idx;
2730 // Check if the access is smaller than the vector size and can we find
2731 // a reasonable extract index.
2732 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2734 int StartIdx[2]; // StartIdx to extract from
2735 for (int Input=0; Input < 2; ++Input) {
2736 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2737 RangeUse[Input] = 0; // Unused
2738 StartIdx[Input] = 0;
2739 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2740 // Fits within range but we should see if we can find a good
2741 // start index that is a multiple of the mask length.
2742 if (MaxRange[Input] < (int)MaskNumElts) {
2743 RangeUse[Input] = 1; // Extract from beginning of the vector
2744 StartIdx[Input] = 0;
2746 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2747 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2748 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2749 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2754 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2755 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2758 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2759 // Extract appropriate subvector and generate a vector shuffle
2760 for (int Input=0; Input < 2; ++Input) {
2761 SDValue &Src = Input == 0 ? Src1 : Src2;
2762 if (RangeUse[Input] == 0)
2763 Src = DAG.getUNDEF(VT);
2765 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2766 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2769 // Calculate new mask.
2770 SmallVector<int, 8> MappedOps;
2771 for (unsigned i = 0; i != MaskNumElts; ++i) {
2774 MappedOps.push_back(Idx);
2775 else if (Idx < (int)SrcNumElts)
2776 MappedOps.push_back(Idx - StartIdx[0]);
2778 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2781 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2787 // We can't use either concat vectors or extract subvectors so fall back to
2788 // replacing the shuffle with extract and build vector.
2789 // to insert and build vector.
2790 EVT EltVT = VT.getVectorElementType();
2791 EVT PtrVT = TLI.getPointerTy();
2792 SmallVector<SDValue,8> Ops;
2793 for (unsigned i = 0; i != MaskNumElts; ++i) {
2795 Ops.push_back(DAG.getUNDEF(EltVT));
2800 if (Idx < (int)SrcNumElts)
2801 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2802 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2804 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2806 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2812 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2813 VT, &Ops[0], Ops.size()));
2816 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2817 const Value *Op0 = I.getOperand(0);
2818 const Value *Op1 = I.getOperand(1);
2819 const Type *AggTy = I.getType();
2820 const Type *ValTy = Op1->getType();
2821 bool IntoUndef = isa<UndefValue>(Op0);
2822 bool FromUndef = isa<UndefValue>(Op1);
2824 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2826 SmallVector<EVT, 4> AggValueVTs;
2827 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2828 SmallVector<EVT, 4> ValValueVTs;
2829 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2831 unsigned NumAggValues = AggValueVTs.size();
2832 unsigned NumValValues = ValValueVTs.size();
2833 SmallVector<SDValue, 4> Values(NumAggValues);
2835 SDValue Agg = getValue(Op0);
2836 SDValue Val = getValue(Op1);
2838 // Copy the beginning value(s) from the original aggregate.
2839 for (; i != LinearIndex; ++i)
2840 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2841 SDValue(Agg.getNode(), Agg.getResNo() + i);
2842 // Copy values from the inserted value(s).
2843 for (; i != LinearIndex + NumValValues; ++i)
2844 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2845 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2846 // Copy remaining value(s) from the original aggregate.
2847 for (; i != NumAggValues; ++i)
2848 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2849 SDValue(Agg.getNode(), Agg.getResNo() + i);
2851 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2852 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2853 &Values[0], NumAggValues));
2856 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2857 const Value *Op0 = I.getOperand(0);
2858 const Type *AggTy = Op0->getType();
2859 const Type *ValTy = I.getType();
2860 bool OutOfUndef = isa<UndefValue>(Op0);
2862 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2864 SmallVector<EVT, 4> ValValueVTs;
2865 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2867 unsigned NumValValues = ValValueVTs.size();
2868 SmallVector<SDValue, 4> Values(NumValValues);
2870 SDValue Agg = getValue(Op0);
2871 // Copy out the selected value(s).
2872 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2873 Values[i - LinearIndex] =
2875 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2876 SDValue(Agg.getNode(), Agg.getResNo() + i);
2878 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2879 DAG.getVTList(&ValValueVTs[0], NumValValues),
2880 &Values[0], NumValValues));
2883 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2884 SDValue N = getValue(I.getOperand(0));
2885 const Type *Ty = I.getOperand(0)->getType();
2887 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2889 const Value *Idx = *OI;
2890 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2891 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2894 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2895 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2896 DAG.getIntPtrConstant(Offset));
2899 Ty = StTy->getElementType(Field);
2901 Ty = cast<SequentialType>(Ty)->getElementType();
2903 // If this is a constant subscript, handle it quickly.
2904 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2905 if (CI->isZero()) continue;
2907 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2909 EVT PTy = TLI.getPointerTy();
2910 unsigned PtrBits = PTy.getSizeInBits();
2912 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2914 DAG.getConstant(Offs, MVT::i64));
2916 OffsVal = DAG.getIntPtrConstant(Offs);
2918 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2923 // N = N + Idx * ElementSize;
2924 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2925 TD->getTypeAllocSize(Ty));
2926 SDValue IdxN = getValue(Idx);
2928 // If the index is smaller or larger than intptr_t, truncate or extend
2930 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2932 // If this is a multiply by a power of two, turn it into a shl
2933 // immediately. This is a very common case.
2934 if (ElementSize != 1) {
2935 if (ElementSize.isPowerOf2()) {
2936 unsigned Amt = ElementSize.logBase2();
2937 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2938 N.getValueType(), IdxN,
2939 DAG.getConstant(Amt, TLI.getPointerTy()));
2941 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2942 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2943 N.getValueType(), IdxN, Scale);
2947 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2948 N.getValueType(), N, IdxN);
2955 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2956 // If this is a fixed sized alloca in the entry block of the function,
2957 // allocate it statically on the stack.
2958 if (FuncInfo.StaticAllocaMap.count(&I))
2959 return; // getValue will auto-populate this.
2961 const Type *Ty = I.getAllocatedType();
2962 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2964 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2967 SDValue AllocSize = getValue(I.getArraySize());
2969 EVT IntPtr = TLI.getPointerTy();
2970 if (AllocSize.getValueType() != IntPtr)
2971 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2973 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2975 DAG.getConstant(TySize, IntPtr));
2977 // Handle alignment. If the requested alignment is less than or equal to
2978 // the stack alignment, ignore it. If the size is greater than or equal to
2979 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2980 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2981 if (Align <= StackAlign)
2984 // Round the size of the allocation up to the stack alignment size
2985 // by add SA-1 to the size.
2986 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2987 AllocSize.getValueType(), AllocSize,
2988 DAG.getIntPtrConstant(StackAlign-1));
2990 // Mask out the low bits for alignment purposes.
2991 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2992 AllocSize.getValueType(), AllocSize,
2993 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2995 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2996 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2997 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3000 DAG.setRoot(DSA.getValue(1));
3002 // Inform the Frame Information that we have just allocated a variable-sized
3004 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3007 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3008 const Value *SV = I.getOperand(0);
3009 SDValue Ptr = getValue(SV);
3011 const Type *Ty = I.getType();
3013 bool isVolatile = I.isVolatile();
3014 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3015 unsigned Alignment = I.getAlignment();
3016 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3018 SmallVector<EVT, 4> ValueVTs;
3019 SmallVector<uint64_t, 4> Offsets;
3020 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3021 unsigned NumValues = ValueVTs.size();
3026 bool ConstantMemory = false;
3027 if (I.isVolatile() || NumValues > MaxParallelChains)
3028 // Serialize volatile loads with other side effects.
3030 else if (AA->pointsToConstantMemory(
3031 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3032 // Do not serialize (non-volatile) loads of constant memory with anything.
3033 Root = DAG.getEntryNode();
3034 ConstantMemory = true;
3036 // Do not serialize non-volatile loads against each other.
3037 Root = DAG.getRoot();
3040 SmallVector<SDValue, 4> Values(NumValues);
3041 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3043 EVT PtrVT = Ptr.getValueType();
3044 unsigned ChainI = 0;
3045 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3046 // Serializing loads here may result in excessive register pressure, and
3047 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3048 // could recover a bit by hoisting nodes upward in the chain by recognizing
3049 // they are side-effect free or do not alias. The optimizer should really
3050 // avoid this case by converting large object/array copies to llvm.memcpy
3051 // (MaxParallelChains should always remain as failsafe).
3052 if (ChainI == MaxParallelChains) {
3053 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3054 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3055 MVT::Other, &Chains[0], ChainI);
3059 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3061 DAG.getConstant(Offsets[i], PtrVT));
3062 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3063 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3064 isNonTemporal, Alignment, TBAAInfo);
3067 Chains[ChainI] = L.getValue(1);
3070 if (!ConstantMemory) {
3071 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3072 MVT::Other, &Chains[0], ChainI);
3076 PendingLoads.push_back(Chain);
3079 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3080 DAG.getVTList(&ValueVTs[0], NumValues),
3081 &Values[0], NumValues));
3084 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3085 const Value *SrcV = I.getOperand(0);
3086 const Value *PtrV = I.getOperand(1);
3088 SmallVector<EVT, 4> ValueVTs;
3089 SmallVector<uint64_t, 4> Offsets;
3090 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3091 unsigned NumValues = ValueVTs.size();
3095 // Get the lowered operands. Note that we do this after
3096 // checking if NumResults is zero, because with zero results
3097 // the operands won't have values in the map.
3098 SDValue Src = getValue(SrcV);
3099 SDValue Ptr = getValue(PtrV);
3101 SDValue Root = getRoot();
3102 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3104 EVT PtrVT = Ptr.getValueType();
3105 bool isVolatile = I.isVolatile();
3106 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3107 unsigned Alignment = I.getAlignment();
3108 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3110 unsigned ChainI = 0;
3111 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3112 // See visitLoad comments.
3113 if (ChainI == MaxParallelChains) {
3114 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3115 MVT::Other, &Chains[0], ChainI);
3119 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3120 DAG.getConstant(Offsets[i], PtrVT));
3121 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3122 SDValue(Src.getNode(), Src.getResNo() + i),
3123 Add, MachinePointerInfo(PtrV, Offsets[i]),
3124 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3125 Chains[ChainI] = St;
3128 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3129 MVT::Other, &Chains[0], ChainI);
3131 AssignOrderingToNode(StoreNode.getNode());
3132 DAG.setRoot(StoreNode);
3135 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3137 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3138 unsigned Intrinsic) {
3139 bool HasChain = !I.doesNotAccessMemory();
3140 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3142 // Build the operand list.
3143 SmallVector<SDValue, 8> Ops;
3144 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3146 // We don't need to serialize loads against other loads.
3147 Ops.push_back(DAG.getRoot());
3149 Ops.push_back(getRoot());
3153 // Info is set by getTgtMemInstrinsic
3154 TargetLowering::IntrinsicInfo Info;
3155 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3157 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3158 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3159 Info.opc == ISD::INTRINSIC_W_CHAIN)
3160 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3162 // Add all operands of the call to the operand list.
3163 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3164 SDValue Op = getValue(I.getArgOperand(i));
3165 assert(TLI.isTypeLegal(Op.getValueType()) &&
3166 "Intrinsic uses a non-legal type?");
3170 SmallVector<EVT, 4> ValueVTs;
3171 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3173 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3174 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3175 "Intrinsic uses a non-legal type?");
3180 ValueVTs.push_back(MVT::Other);
3182 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3186 if (IsTgtIntrinsic) {
3187 // This is target intrinsic that touches memory
3188 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3189 VTs, &Ops[0], Ops.size(),
3191 MachinePointerInfo(Info.ptrVal, Info.offset),
3192 Info.align, Info.vol,
3193 Info.readMem, Info.writeMem);
3194 } else if (!HasChain) {
3195 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3196 VTs, &Ops[0], Ops.size());
3197 } else if (!I.getType()->isVoidTy()) {
3198 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3199 VTs, &Ops[0], Ops.size());
3201 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3202 VTs, &Ops[0], Ops.size());
3206 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3208 PendingLoads.push_back(Chain);
3213 if (!I.getType()->isVoidTy()) {
3214 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3215 EVT VT = TLI.getValueType(PTy);
3216 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3219 setValue(&I, Result);
3223 /// GetSignificand - Get the significand and build it into a floating-point
3224 /// number with exponent of 1:
3226 /// Op = (Op & 0x007fffff) | 0x3f800000;
3228 /// where Op is the hexidecimal representation of floating point value.
3230 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3231 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3232 DAG.getConstant(0x007fffff, MVT::i32));
3233 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3234 DAG.getConstant(0x3f800000, MVT::i32));
3235 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3238 /// GetExponent - Get the exponent:
3240 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3242 /// where Op is the hexidecimal representation of floating point value.
3244 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3246 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3247 DAG.getConstant(0x7f800000, MVT::i32));
3248 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3249 DAG.getConstant(23, TLI.getPointerTy()));
3250 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3251 DAG.getConstant(127, MVT::i32));
3252 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3255 /// getF32Constant - Get 32-bit floating point constant.
3257 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3258 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3261 /// Inlined utility function to implement binary input atomic intrinsics for
3262 /// visitIntrinsicCall: I is a call instruction
3263 /// Op is the associated NodeType for I
3265 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3267 SDValue Root = getRoot();
3269 DAG.getAtomic(Op, getCurDebugLoc(),
3270 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3272 getValue(I.getArgOperand(0)),
3273 getValue(I.getArgOperand(1)),
3274 I.getArgOperand(0));
3276 DAG.setRoot(L.getValue(1));
3280 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3282 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3283 SDValue Op1 = getValue(I.getArgOperand(0));
3284 SDValue Op2 = getValue(I.getArgOperand(1));
3286 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3287 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3291 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3292 /// limited-precision mode.
3294 SelectionDAGBuilder::visitExp(const CallInst &I) {
3296 DebugLoc dl = getCurDebugLoc();
3298 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3299 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3300 SDValue Op = getValue(I.getArgOperand(0));
3302 // Put the exponent in the right bit position for later addition to the
3305 // #define LOG2OFe 1.4426950f
3306 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3307 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3308 getF32Constant(DAG, 0x3fb8aa3b));
3309 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3311 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3312 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3313 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3315 // IntegerPartOfX <<= 23;
3316 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3317 DAG.getConstant(23, TLI.getPointerTy()));
3319 if (LimitFloatPrecision <= 6) {
3320 // For floating-point precision of 6:
3322 // TwoToFractionalPartOfX =
3324 // (0.735607626f + 0.252464424f * x) * x;
3326 // error 0.0144103317, which is 6 bits
3327 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3328 getF32Constant(DAG, 0x3e814304));
3329 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3330 getF32Constant(DAG, 0x3f3c50c8));
3331 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3332 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3333 getF32Constant(DAG, 0x3f7f5e7e));
3334 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3336 // Add the exponent into the result in integer domain.
3337 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3338 TwoToFracPartOfX, IntegerPartOfX);
3340 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3341 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3342 // For floating-point precision of 12:
3344 // TwoToFractionalPartOfX =
3347 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3349 // 0.000107046256 error, which is 13 to 14 bits
3350 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3351 getF32Constant(DAG, 0x3da235e3));
3352 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3353 getF32Constant(DAG, 0x3e65b8f3));
3354 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3355 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3356 getF32Constant(DAG, 0x3f324b07));
3357 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3358 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3359 getF32Constant(DAG, 0x3f7ff8fd));
3360 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3362 // Add the exponent into the result in integer domain.
3363 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3364 TwoToFracPartOfX, IntegerPartOfX);
3366 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3367 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3368 // For floating-point precision of 18:
3370 // TwoToFractionalPartOfX =
3374 // (0.554906021e-1f +
3375 // (0.961591928e-2f +
3376 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3378 // error 2.47208000*10^(-7), which is better than 18 bits
3379 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3380 getF32Constant(DAG, 0x3924b03e));
3381 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3382 getF32Constant(DAG, 0x3ab24b87));
3383 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3384 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3385 getF32Constant(DAG, 0x3c1d8c17));
3386 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3387 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3388 getF32Constant(DAG, 0x3d634a1d));
3389 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3390 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3391 getF32Constant(DAG, 0x3e75fe14));
3392 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3393 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3394 getF32Constant(DAG, 0x3f317234));
3395 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3396 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3397 getF32Constant(DAG, 0x3f800000));
3398 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3401 // Add the exponent into the result in integer domain.
3402 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3403 TwoToFracPartOfX, IntegerPartOfX);
3405 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3408 // No special expansion.
3409 result = DAG.getNode(ISD::FEXP, dl,
3410 getValue(I.getArgOperand(0)).getValueType(),
3411 getValue(I.getArgOperand(0)));
3414 setValue(&I, result);
3417 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3418 /// limited-precision mode.
3420 SelectionDAGBuilder::visitLog(const CallInst &I) {
3422 DebugLoc dl = getCurDebugLoc();
3424 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3425 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3426 SDValue Op = getValue(I.getArgOperand(0));
3427 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3429 // Scale the exponent by log(2) [0.69314718f].
3430 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3431 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3432 getF32Constant(DAG, 0x3f317218));
3434 // Get the significand and build it into a floating-point number with
3436 SDValue X = GetSignificand(DAG, Op1, dl);
3438 if (LimitFloatPrecision <= 6) {
3439 // For floating-point precision of 6:
3443 // (1.4034025f - 0.23903021f * x) * x;
3445 // error 0.0034276066, which is better than 8 bits
3446 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3447 getF32Constant(DAG, 0xbe74c456));
3448 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3449 getF32Constant(DAG, 0x3fb3a2b1));
3450 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3451 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3452 getF32Constant(DAG, 0x3f949a29));
3454 result = DAG.getNode(ISD::FADD, dl,
3455 MVT::f32, LogOfExponent, LogOfMantissa);
3456 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3457 // For floating-point precision of 12:
3463 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3465 // error 0.000061011436, which is 14 bits
3466 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3467 getF32Constant(DAG, 0xbd67b6d6));
3468 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3469 getF32Constant(DAG, 0x3ee4f4b8));
3470 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3471 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3472 getF32Constant(DAG, 0x3fbc278b));
3473 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3474 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3475 getF32Constant(DAG, 0x40348e95));
3476 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3477 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3478 getF32Constant(DAG, 0x3fdef31a));
3480 result = DAG.getNode(ISD::FADD, dl,
3481 MVT::f32, LogOfExponent, LogOfMantissa);
3482 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3483 // For floating-point precision of 18:
3491 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3493 // error 0.0000023660568, which is better than 18 bits
3494 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3495 getF32Constant(DAG, 0xbc91e5ac));
3496 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3497 getF32Constant(DAG, 0x3e4350aa));
3498 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3499 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3500 getF32Constant(DAG, 0x3f60d3e3));
3501 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3502 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3503 getF32Constant(DAG, 0x4011cdf0));
3504 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3505 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3506 getF32Constant(DAG, 0x406cfd1c));
3507 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3508 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3509 getF32Constant(DAG, 0x408797cb));
3510 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3511 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3512 getF32Constant(DAG, 0x4006dcab));
3514 result = DAG.getNode(ISD::FADD, dl,
3515 MVT::f32, LogOfExponent, LogOfMantissa);
3518 // No special expansion.
3519 result = DAG.getNode(ISD::FLOG, dl,
3520 getValue(I.getArgOperand(0)).getValueType(),
3521 getValue(I.getArgOperand(0)));
3524 setValue(&I, result);
3527 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3528 /// limited-precision mode.
3530 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3532 DebugLoc dl = getCurDebugLoc();
3534 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3535 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3536 SDValue Op = getValue(I.getArgOperand(0));
3537 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3539 // Get the exponent.
3540 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3542 // Get the significand and build it into a floating-point number with
3544 SDValue X = GetSignificand(DAG, Op1, dl);
3546 // Different possible minimax approximations of significand in
3547 // floating-point for various degrees of accuracy over [1,2].
3548 if (LimitFloatPrecision <= 6) {
3549 // For floating-point precision of 6:
3551 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3553 // error 0.0049451742, which is more than 7 bits
3554 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3555 getF32Constant(DAG, 0xbeb08fe0));
3556 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3557 getF32Constant(DAG, 0x40019463));
3558 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3559 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3560 getF32Constant(DAG, 0x3fd6633d));
3562 result = DAG.getNode(ISD::FADD, dl,
3563 MVT::f32, LogOfExponent, Log2ofMantissa);
3564 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3565 // For floating-point precision of 12:
3571 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3573 // error 0.0000876136000, which is better than 13 bits
3574 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3575 getF32Constant(DAG, 0xbda7262e));
3576 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3577 getF32Constant(DAG, 0x3f25280b));
3578 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3579 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3580 getF32Constant(DAG, 0x4007b923));
3581 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3582 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3583 getF32Constant(DAG, 0x40823e2f));
3584 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3585 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3586 getF32Constant(DAG, 0x4020d29c));
3588 result = DAG.getNode(ISD::FADD, dl,
3589 MVT::f32, LogOfExponent, Log2ofMantissa);
3590 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3591 // For floating-point precision of 18:
3600 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3602 // error 0.0000018516, which is better than 18 bits
3603 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3604 getF32Constant(DAG, 0xbcd2769e));
3605 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3606 getF32Constant(DAG, 0x3e8ce0b9));
3607 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3608 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3609 getF32Constant(DAG, 0x3fa22ae7));
3610 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3611 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3612 getF32Constant(DAG, 0x40525723));
3613 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3614 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3615 getF32Constant(DAG, 0x40aaf200));
3616 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3617 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3618 getF32Constant(DAG, 0x40c39dad));
3619 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3620 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3621 getF32Constant(DAG, 0x4042902c));
3623 result = DAG.getNode(ISD::FADD, dl,
3624 MVT::f32, LogOfExponent, Log2ofMantissa);
3627 // No special expansion.
3628 result = DAG.getNode(ISD::FLOG2, dl,
3629 getValue(I.getArgOperand(0)).getValueType(),
3630 getValue(I.getArgOperand(0)));
3633 setValue(&I, result);
3636 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3637 /// limited-precision mode.
3639 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3641 DebugLoc dl = getCurDebugLoc();
3643 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3644 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3645 SDValue Op = getValue(I.getArgOperand(0));
3646 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3648 // Scale the exponent by log10(2) [0.30102999f].
3649 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3650 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3651 getF32Constant(DAG, 0x3e9a209a));
3653 // Get the significand and build it into a floating-point number with
3655 SDValue X = GetSignificand(DAG, Op1, dl);
3657 if (LimitFloatPrecision <= 6) {
3658 // For floating-point precision of 6:
3660 // Log10ofMantissa =
3662 // (0.60948995f - 0.10380950f * x) * x;
3664 // error 0.0014886165, which is 6 bits
3665 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3666 getF32Constant(DAG, 0xbdd49a13));
3667 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3668 getF32Constant(DAG, 0x3f1c0789));
3669 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3670 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3671 getF32Constant(DAG, 0x3f011300));
3673 result = DAG.getNode(ISD::FADD, dl,
3674 MVT::f32, LogOfExponent, Log10ofMantissa);
3675 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3676 // For floating-point precision of 12:
3678 // Log10ofMantissa =
3681 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3683 // error 0.00019228036, which is better than 12 bits
3684 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3685 getF32Constant(DAG, 0x3d431f31));
3686 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3687 getF32Constant(DAG, 0x3ea21fb2));
3688 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3689 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3690 getF32Constant(DAG, 0x3f6ae232));
3691 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3692 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3693 getF32Constant(DAG, 0x3f25f7c3));
3695 result = DAG.getNode(ISD::FADD, dl,
3696 MVT::f32, LogOfExponent, Log10ofMantissa);
3697 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3698 // For floating-point precision of 18:
3700 // Log10ofMantissa =
3705 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3707 // error 0.0000037995730, which is better than 18 bits
3708 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3709 getF32Constant(DAG, 0x3c5d51ce));
3710 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3711 getF32Constant(DAG, 0x3e00685a));
3712 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3713 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3714 getF32Constant(DAG, 0x3efb6798));
3715 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3716 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3717 getF32Constant(DAG, 0x3f88d192));
3718 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3719 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3720 getF32Constant(DAG, 0x3fc4316c));
3721 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3722 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3723 getF32Constant(DAG, 0x3f57ce70));
3725 result = DAG.getNode(ISD::FADD, dl,
3726 MVT::f32, LogOfExponent, Log10ofMantissa);
3729 // No special expansion.
3730 result = DAG.getNode(ISD::FLOG10, dl,
3731 getValue(I.getArgOperand(0)).getValueType(),
3732 getValue(I.getArgOperand(0)));
3735 setValue(&I, result);
3738 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3739 /// limited-precision mode.
3741 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3743 DebugLoc dl = getCurDebugLoc();
3745 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3746 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3747 SDValue Op = getValue(I.getArgOperand(0));
3749 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3751 // FractionalPartOfX = x - (float)IntegerPartOfX;
3752 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3753 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3755 // IntegerPartOfX <<= 23;
3756 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3757 DAG.getConstant(23, TLI.getPointerTy()));
3759 if (LimitFloatPrecision <= 6) {
3760 // For floating-point precision of 6:
3762 // TwoToFractionalPartOfX =
3764 // (0.735607626f + 0.252464424f * x) * x;
3766 // error 0.0144103317, which is 6 bits
3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3768 getF32Constant(DAG, 0x3e814304));
3769 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3770 getF32Constant(DAG, 0x3f3c50c8));
3771 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3772 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3773 getF32Constant(DAG, 0x3f7f5e7e));
3774 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3775 SDValue TwoToFractionalPartOfX =
3776 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3778 result = DAG.getNode(ISD::BITCAST, dl,
3779 MVT::f32, TwoToFractionalPartOfX);
3780 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3781 // For floating-point precision of 12:
3783 // TwoToFractionalPartOfX =
3786 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3788 // error 0.000107046256, which is 13 to 14 bits
3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3790 getF32Constant(DAG, 0x3da235e3));
3791 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3792 getF32Constant(DAG, 0x3e65b8f3));
3793 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3794 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3795 getF32Constant(DAG, 0x3f324b07));
3796 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3797 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3798 getF32Constant(DAG, 0x3f7ff8fd));
3799 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3800 SDValue TwoToFractionalPartOfX =
3801 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3803 result = DAG.getNode(ISD::BITCAST, dl,
3804 MVT::f32, TwoToFractionalPartOfX);
3805 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3806 // For floating-point precision of 18:
3808 // TwoToFractionalPartOfX =
3812 // (0.554906021e-1f +
3813 // (0.961591928e-2f +
3814 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3815 // error 2.47208000*10^(-7), which is better than 18 bits
3816 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3817 getF32Constant(DAG, 0x3924b03e));
3818 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3819 getF32Constant(DAG, 0x3ab24b87));
3820 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3821 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3822 getF32Constant(DAG, 0x3c1d8c17));
3823 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3824 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3825 getF32Constant(DAG, 0x3d634a1d));
3826 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3827 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3828 getF32Constant(DAG, 0x3e75fe14));
3829 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3830 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3831 getF32Constant(DAG, 0x3f317234));
3832 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3833 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3834 getF32Constant(DAG, 0x3f800000));
3835 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3836 SDValue TwoToFractionalPartOfX =
3837 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3839 result = DAG.getNode(ISD::BITCAST, dl,
3840 MVT::f32, TwoToFractionalPartOfX);
3843 // No special expansion.
3844 result = DAG.getNode(ISD::FEXP2, dl,
3845 getValue(I.getArgOperand(0)).getValueType(),
3846 getValue(I.getArgOperand(0)));
3849 setValue(&I, result);
3852 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3853 /// limited-precision mode with x == 10.0f.
3855 SelectionDAGBuilder::visitPow(const CallInst &I) {
3857 const Value *Val = I.getArgOperand(0);
3858 DebugLoc dl = getCurDebugLoc();
3859 bool IsExp10 = false;
3861 if (getValue(Val).getValueType() == MVT::f32 &&
3862 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3863 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3864 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3865 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3867 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3872 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3873 SDValue Op = getValue(I.getArgOperand(1));
3875 // Put the exponent in the right bit position for later addition to the
3878 // #define LOG2OF10 3.3219281f
3879 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3880 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3881 getF32Constant(DAG, 0x40549a78));
3882 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3884 // FractionalPartOfX = x - (float)IntegerPartOfX;
3885 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3886 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3888 // IntegerPartOfX <<= 23;
3889 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3890 DAG.getConstant(23, TLI.getPointerTy()));
3892 if (LimitFloatPrecision <= 6) {
3893 // For floating-point precision of 6:
3895 // twoToFractionalPartOfX =
3897 // (0.735607626f + 0.252464424f * x) * x;
3899 // error 0.0144103317, which is 6 bits
3900 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3901 getF32Constant(DAG, 0x3e814304));
3902 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3903 getF32Constant(DAG, 0x3f3c50c8));
3904 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3905 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3906 getF32Constant(DAG, 0x3f7f5e7e));
3907 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3908 SDValue TwoToFractionalPartOfX =
3909 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3911 result = DAG.getNode(ISD::BITCAST, dl,
3912 MVT::f32, TwoToFractionalPartOfX);
3913 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3914 // For floating-point precision of 12:
3916 // TwoToFractionalPartOfX =
3919 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3921 // error 0.000107046256, which is 13 to 14 bits
3922 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3923 getF32Constant(DAG, 0x3da235e3));
3924 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3925 getF32Constant(DAG, 0x3e65b8f3));
3926 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3927 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3928 getF32Constant(DAG, 0x3f324b07));
3929 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3930 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3931 getF32Constant(DAG, 0x3f7ff8fd));
3932 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3933 SDValue TwoToFractionalPartOfX =
3934 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3936 result = DAG.getNode(ISD::BITCAST, dl,
3937 MVT::f32, TwoToFractionalPartOfX);
3938 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3939 // For floating-point precision of 18:
3941 // TwoToFractionalPartOfX =
3945 // (0.554906021e-1f +
3946 // (0.961591928e-2f +
3947 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3948 // error 2.47208000*10^(-7), which is better than 18 bits
3949 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3950 getF32Constant(DAG, 0x3924b03e));
3951 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3952 getF32Constant(DAG, 0x3ab24b87));
3953 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3954 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3955 getF32Constant(DAG, 0x3c1d8c17));
3956 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3957 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3958 getF32Constant(DAG, 0x3d634a1d));
3959 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3960 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3961 getF32Constant(DAG, 0x3e75fe14));
3962 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3963 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3964 getF32Constant(DAG, 0x3f317234));
3965 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3966 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3967 getF32Constant(DAG, 0x3f800000));
3968 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3969 SDValue TwoToFractionalPartOfX =
3970 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3972 result = DAG.getNode(ISD::BITCAST, dl,
3973 MVT::f32, TwoToFractionalPartOfX);
3976 // No special expansion.
3977 result = DAG.getNode(ISD::FPOW, dl,
3978 getValue(I.getArgOperand(0)).getValueType(),
3979 getValue(I.getArgOperand(0)),
3980 getValue(I.getArgOperand(1)));
3983 setValue(&I, result);
3987 /// ExpandPowI - Expand a llvm.powi intrinsic.
3988 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3989 SelectionDAG &DAG) {
3990 // If RHS is a constant, we can expand this out to a multiplication tree,
3991 // otherwise we end up lowering to a call to __powidf2 (for example). When
3992 // optimizing for size, we only want to do this if the expansion would produce
3993 // a small number of multiplies, otherwise we do the full expansion.
3994 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3995 // Get the exponent as a positive value.
3996 unsigned Val = RHSC->getSExtValue();
3997 if ((int)Val < 0) Val = -Val;
3999 // powi(x, 0) -> 1.0
4001 return DAG.getConstantFP(1.0, LHS.getValueType());
4003 const Function *F = DAG.getMachineFunction().getFunction();
4004 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4005 // If optimizing for size, don't insert too many multiplies. This
4006 // inserts up to 5 multiplies.
4007 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4008 // We use the simple binary decomposition method to generate the multiply
4009 // sequence. There are more optimal ways to do this (for example,
4010 // powi(x,15) generates one more multiply than it should), but this has
4011 // the benefit of being both really simple and much better than a libcall.
4012 SDValue Res; // Logically starts equal to 1.0
4013 SDValue CurSquare = LHS;
4017 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4019 Res = CurSquare; // 1.0*CurSquare.
4022 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4023 CurSquare, CurSquare);
4027 // If the original was negative, invert the result, producing 1/(x*x*x).
4028 if (RHSC->getSExtValue() < 0)
4029 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4030 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4035 // Otherwise, expand to a libcall.
4036 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4039 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4040 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4041 /// At the end of instruction selection, they will be inserted to the entry BB.
4043 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4046 const Argument *Arg = dyn_cast<Argument>(V);
4050 MachineFunction &MF = DAG.getMachineFunction();
4051 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4052 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4054 // Ignore inlined function arguments here.
4055 DIVariable DV(Variable);
4056 if (DV.isInlinedFnArgument(MF.getFunction()))
4059 MachineBasicBlock *MBB = FuncInfo.MBB;
4060 if (MBB != &MF.front())
4064 if (Arg->hasByValAttr()) {
4065 // Byval arguments' frame index is recorded during argument lowering.
4066 // Use this info directly.
4067 Reg = TRI->getFrameRegister(MF);
4068 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4069 // If byval argument ofset is not recorded then ignore this.
4074 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4075 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4076 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4077 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4078 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4085 // Check if ValueMap has reg number.
4086 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4087 if (VMI != FuncInfo.ValueMap.end())
4091 if (!Reg && N.getNode()) {
4092 // Check if frame index is available.
4093 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4094 if (FrameIndexSDNode *FINode =
4095 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4096 Reg = TRI->getFrameRegister(MF);
4097 Offset = FINode->getIndex();
4104 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4105 TII->get(TargetOpcode::DBG_VALUE))
4106 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4107 FuncInfo.ArgDbgValues.push_back(&*MIB);
4111 // VisualStudio defines setjmp as _setjmp
4112 #if defined(_MSC_VER) && defined(setjmp) && \
4113 !defined(setjmp_undefined_for_msvc)
4114 # pragma push_macro("setjmp")
4116 # define setjmp_undefined_for_msvc
4119 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4120 /// we want to emit this as a call to a named external function, return the name
4121 /// otherwise lower it and return null.
4123 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4124 DebugLoc dl = getCurDebugLoc();
4127 switch (Intrinsic) {
4129 // By default, turn this into a target intrinsic node.
4130 visitTargetIntrinsic(I, Intrinsic);
4132 case Intrinsic::vastart: visitVAStart(I); return 0;
4133 case Intrinsic::vaend: visitVAEnd(I); return 0;
4134 case Intrinsic::vacopy: visitVACopy(I); return 0;
4135 case Intrinsic::returnaddress:
4136 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4137 getValue(I.getArgOperand(0))));
4139 case Intrinsic::frameaddress:
4140 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4141 getValue(I.getArgOperand(0))));
4143 case Intrinsic::setjmp:
4144 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4145 case Intrinsic::longjmp:
4146 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4147 case Intrinsic::memcpy: {
4148 // Assert for address < 256 since we support only user defined address
4150 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4152 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4154 "Unknown address space");
4155 SDValue Op1 = getValue(I.getArgOperand(0));
4156 SDValue Op2 = getValue(I.getArgOperand(1));
4157 SDValue Op3 = getValue(I.getArgOperand(2));
4158 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4159 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4160 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4161 MachinePointerInfo(I.getArgOperand(0)),
4162 MachinePointerInfo(I.getArgOperand(1))));
4165 case Intrinsic::memset: {
4166 // Assert for address < 256 since we support only user defined address
4168 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4170 "Unknown address space");
4171 SDValue Op1 = getValue(I.getArgOperand(0));
4172 SDValue Op2 = getValue(I.getArgOperand(1));
4173 SDValue Op3 = getValue(I.getArgOperand(2));
4174 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4175 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4176 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4177 MachinePointerInfo(I.getArgOperand(0))));
4180 case Intrinsic::memmove: {
4181 // Assert for address < 256 since we support only user defined address
4183 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4185 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4187 "Unknown address space");
4188 SDValue Op1 = getValue(I.getArgOperand(0));
4189 SDValue Op2 = getValue(I.getArgOperand(1));
4190 SDValue Op3 = getValue(I.getArgOperand(2));
4191 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4192 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4193 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4194 MachinePointerInfo(I.getArgOperand(0)),
4195 MachinePointerInfo(I.getArgOperand(1))));
4198 case Intrinsic::dbg_declare: {
4199 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4200 MDNode *Variable = DI.getVariable();
4201 const Value *Address = DI.getAddress();
4202 if (!Address || !DIVariable(DI.getVariable()).Verify())
4205 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4206 // but do not always have a corresponding SDNode built. The SDNodeOrder
4207 // absolute, but not relative, values are different depending on whether
4208 // debug info exists.
4211 // Check if address has undef value.
4212 if (isa<UndefValue>(Address) ||
4213 (Address->use_empty() && !isa<Argument>(Address))) {
4214 DEBUG(dbgs() << "Dropping debug info for " << DI);
4218 SDValue &N = NodeMap[Address];
4219 if (!N.getNode() && isa<Argument>(Address))
4220 // Check unused arguments map.
4221 N = UnusedArgNodeMap[Address];
4224 // Parameters are handled specially.
4226 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4227 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4228 Address = BCI->getOperand(0);
4229 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4231 if (isParameter && !AI) {
4232 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4234 // Byval parameter. We have a frame index at this point.
4235 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4236 0, dl, SDNodeOrder);
4238 // Can't do anything with other non-AI cases yet. This might be a
4239 // parameter of a callee function that got inlined, for example.
4240 DEBUG(dbgs() << "Dropping debug info for " << DI);
4244 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4245 0, dl, SDNodeOrder);
4247 // Can't do anything with other non-AI cases yet.
4248 DEBUG(dbgs() << "Dropping debug info for " << DI);
4251 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4253 // If Address is an argument then try to emit its dbg value using
4254 // virtual register info from the FuncInfo.ValueMap.
4255 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4256 // If variable is pinned by a alloca in dominating bb then
4257 // use StaticAllocaMap.
4258 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4259 if (AI->getParent() != DI.getParent()) {
4260 DenseMap<const AllocaInst*, int>::iterator SI =
4261 FuncInfo.StaticAllocaMap.find(AI);
4262 if (SI != FuncInfo.StaticAllocaMap.end()) {
4263 SDV = DAG.getDbgValue(Variable, SI->second,
4264 0, dl, SDNodeOrder);
4265 DAG.AddDbgValue(SDV, 0, false);
4270 DEBUG(dbgs() << "Dropping debug info for " << DI);
4275 case Intrinsic::dbg_value: {
4276 const DbgValueInst &DI = cast<DbgValueInst>(I);
4277 if (!DIVariable(DI.getVariable()).Verify())
4280 MDNode *Variable = DI.getVariable();
4281 uint64_t Offset = DI.getOffset();
4282 const Value *V = DI.getValue();
4286 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4287 // but do not always have a corresponding SDNode built. The SDNodeOrder
4288 // absolute, but not relative, values are different depending on whether
4289 // debug info exists.
4292 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4293 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4294 DAG.AddDbgValue(SDV, 0, false);
4296 // Do not use getValue() in here; we don't want to generate code at
4297 // this point if it hasn't been done yet.
4298 SDValue N = NodeMap[V];
4299 if (!N.getNode() && isa<Argument>(V))
4300 // Check unused arguments map.
4301 N = UnusedArgNodeMap[V];
4303 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4304 SDV = DAG.getDbgValue(Variable, N.getNode(),
4305 N.getResNo(), Offset, dl, SDNodeOrder);
4306 DAG.AddDbgValue(SDV, N.getNode(), false);
4308 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4309 // Do not call getValue(V) yet, as we don't want to generate code.
4310 // Remember it for later.
4311 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4312 DanglingDebugInfoMap[V] = DDI;
4314 // We may expand this to cover more cases. One case where we have no
4315 // data available is an unreferenced parameter.
4316 DEBUG(dbgs() << "Dropping debug info for " << DI);
4320 // Build a debug info table entry.
4321 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4322 V = BCI->getOperand(0);
4323 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4324 // Don't handle byval struct arguments or VLAs, for example.
4327 DenseMap<const AllocaInst*, int>::iterator SI =
4328 FuncInfo.StaticAllocaMap.find(AI);
4329 if (SI == FuncInfo.StaticAllocaMap.end())
4331 int FI = SI->second;
4333 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4334 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4335 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4338 case Intrinsic::eh_exception: {
4339 // Insert the EXCEPTIONADDR instruction.
4340 assert(FuncInfo.MBB->isLandingPad() &&
4341 "Call to eh.exception not in landing pad!");
4342 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4344 Ops[0] = DAG.getRoot();
4345 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4347 DAG.setRoot(Op.getValue(1));
4351 case Intrinsic::eh_selector: {
4352 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4353 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4354 if (CallMBB->isLandingPad())
4355 AddCatchInfo(I, &MMI, CallMBB);
4358 FuncInfo.CatchInfoLost.insert(&I);
4360 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4361 unsigned Reg = TLI.getExceptionSelectorRegister();
4362 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4365 // Insert the EHSELECTION instruction.
4366 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4368 Ops[0] = getValue(I.getArgOperand(0));
4370 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4371 DAG.setRoot(Op.getValue(1));
4372 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4376 case Intrinsic::eh_typeid_for: {
4377 // Find the type id for the given typeinfo.
4378 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4379 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4380 Res = DAG.getConstant(TypeID, MVT::i32);
4385 case Intrinsic::eh_return_i32:
4386 case Intrinsic::eh_return_i64:
4387 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4388 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4391 getValue(I.getArgOperand(0)),
4392 getValue(I.getArgOperand(1))));
4394 case Intrinsic::eh_unwind_init:
4395 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4397 case Intrinsic::eh_dwarf_cfa: {
4398 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4399 TLI.getPointerTy());
4400 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4402 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4403 TLI.getPointerTy()),
4405 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4407 DAG.getConstant(0, TLI.getPointerTy()));
4408 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4412 case Intrinsic::eh_sjlj_callsite: {
4413 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4414 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4415 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4416 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4418 MMI.setCurrentCallSite(CI->getZExtValue());
4421 case Intrinsic::eh_sjlj_setjmp: {
4422 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4423 getValue(I.getArgOperand(0))));
4426 case Intrinsic::eh_sjlj_longjmp: {
4427 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4428 getRoot(), getValue(I.getArgOperand(0))));
4431 case Intrinsic::eh_sjlj_dispatch_setup: {
4432 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4433 getRoot(), getValue(I.getArgOperand(0))));
4437 case Intrinsic::x86_mmx_pslli_w:
4438 case Intrinsic::x86_mmx_pslli_d:
4439 case Intrinsic::x86_mmx_pslli_q:
4440 case Intrinsic::x86_mmx_psrli_w:
4441 case Intrinsic::x86_mmx_psrli_d:
4442 case Intrinsic::x86_mmx_psrli_q:
4443 case Intrinsic::x86_mmx_psrai_w:
4444 case Intrinsic::x86_mmx_psrai_d: {
4445 SDValue ShAmt = getValue(I.getArgOperand(1));
4446 if (isa<ConstantSDNode>(ShAmt)) {
4447 visitTargetIntrinsic(I, Intrinsic);
4450 unsigned NewIntrinsic = 0;
4451 EVT ShAmtVT = MVT::v2i32;
4452 switch (Intrinsic) {
4453 case Intrinsic::x86_mmx_pslli_w:
4454 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4456 case Intrinsic::x86_mmx_pslli_d:
4457 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4459 case Intrinsic::x86_mmx_pslli_q:
4460 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4462 case Intrinsic::x86_mmx_psrli_w:
4463 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4465 case Intrinsic::x86_mmx_psrli_d:
4466 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4468 case Intrinsic::x86_mmx_psrli_q:
4469 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4471 case Intrinsic::x86_mmx_psrai_w:
4472 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4474 case Intrinsic::x86_mmx_psrai_d:
4475 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4477 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4480 // The vector shift intrinsics with scalars uses 32b shift amounts but
4481 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4483 // We must do this early because v2i32 is not a legal type.
4484 DebugLoc dl = getCurDebugLoc();
4487 ShOps[1] = DAG.getConstant(0, MVT::i32);
4488 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4489 EVT DestVT = TLI.getValueType(I.getType());
4490 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4491 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4492 DAG.getConstant(NewIntrinsic, MVT::i32),
4493 getValue(I.getArgOperand(0)), ShAmt);
4497 case Intrinsic::convertff:
4498 case Intrinsic::convertfsi:
4499 case Intrinsic::convertfui:
4500 case Intrinsic::convertsif:
4501 case Intrinsic::convertuif:
4502 case Intrinsic::convertss:
4503 case Intrinsic::convertsu:
4504 case Intrinsic::convertus:
4505 case Intrinsic::convertuu: {
4506 ISD::CvtCode Code = ISD::CVT_INVALID;
4507 switch (Intrinsic) {
4508 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4509 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4510 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4511 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4512 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4513 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4514 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4515 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4516 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4518 EVT DestVT = TLI.getValueType(I.getType());
4519 const Value *Op1 = I.getArgOperand(0);
4520 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4521 DAG.getValueType(DestVT),
4522 DAG.getValueType(getValue(Op1).getValueType()),
4523 getValue(I.getArgOperand(1)),
4524 getValue(I.getArgOperand(2)),
4529 case Intrinsic::sqrt:
4530 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4531 getValue(I.getArgOperand(0)).getValueType(),
4532 getValue(I.getArgOperand(0))));
4534 case Intrinsic::powi:
4535 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4536 getValue(I.getArgOperand(1)), DAG));
4538 case Intrinsic::sin:
4539 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4540 getValue(I.getArgOperand(0)).getValueType(),
4541 getValue(I.getArgOperand(0))));
4543 case Intrinsic::cos:
4544 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4545 getValue(I.getArgOperand(0)).getValueType(),
4546 getValue(I.getArgOperand(0))));
4548 case Intrinsic::log:
4551 case Intrinsic::log2:
4554 case Intrinsic::log10:
4557 case Intrinsic::exp:
4560 case Intrinsic::exp2:
4563 case Intrinsic::pow:
4566 case Intrinsic::convert_to_fp16:
4567 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4568 MVT::i16, getValue(I.getArgOperand(0))));
4570 case Intrinsic::convert_from_fp16:
4571 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4572 MVT::f32, getValue(I.getArgOperand(0))));
4574 case Intrinsic::pcmarker: {
4575 SDValue Tmp = getValue(I.getArgOperand(0));
4576 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4579 case Intrinsic::readcyclecounter: {
4580 SDValue Op = getRoot();
4581 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4582 DAG.getVTList(MVT::i64, MVT::Other),
4585 DAG.setRoot(Res.getValue(1));
4588 case Intrinsic::bswap:
4589 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4590 getValue(I.getArgOperand(0)).getValueType(),
4591 getValue(I.getArgOperand(0))));
4593 case Intrinsic::cttz: {
4594 SDValue Arg = getValue(I.getArgOperand(0));
4595 EVT Ty = Arg.getValueType();
4596 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4599 case Intrinsic::ctlz: {
4600 SDValue Arg = getValue(I.getArgOperand(0));
4601 EVT Ty = Arg.getValueType();
4602 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4605 case Intrinsic::ctpop: {
4606 SDValue Arg = getValue(I.getArgOperand(0));
4607 EVT Ty = Arg.getValueType();
4608 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4611 case Intrinsic::stacksave: {
4612 SDValue Op = getRoot();
4613 Res = DAG.getNode(ISD::STACKSAVE, dl,
4614 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4616 DAG.setRoot(Res.getValue(1));
4619 case Intrinsic::stackrestore: {
4620 Res = getValue(I.getArgOperand(0));
4621 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4624 case Intrinsic::stackprotector: {
4625 // Emit code into the DAG to store the stack guard onto the stack.
4626 MachineFunction &MF = DAG.getMachineFunction();
4627 MachineFrameInfo *MFI = MF.getFrameInfo();
4628 EVT PtrTy = TLI.getPointerTy();
4630 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4631 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4633 int FI = FuncInfo.StaticAllocaMap[Slot];
4634 MFI->setStackProtectorIndex(FI);
4636 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4638 // Store the stack protector onto the stack.
4639 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4640 MachinePointerInfo::getFixedStack(FI),
4646 case Intrinsic::objectsize: {
4647 // If we don't know by now, we're never going to know.
4648 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4650 assert(CI && "Non-constant type in __builtin_object_size?");
4652 SDValue Arg = getValue(I.getCalledValue());
4653 EVT Ty = Arg.getValueType();
4656 Res = DAG.getConstant(-1ULL, Ty);
4658 Res = DAG.getConstant(0, Ty);
4663 case Intrinsic::var_annotation:
4664 // Discard annotate attributes
4667 case Intrinsic::init_trampoline: {
4668 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4672 Ops[1] = getValue(I.getArgOperand(0));
4673 Ops[2] = getValue(I.getArgOperand(1));
4674 Ops[3] = getValue(I.getArgOperand(2));
4675 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4676 Ops[5] = DAG.getSrcValue(F);
4678 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4679 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4683 DAG.setRoot(Res.getValue(1));
4686 case Intrinsic::gcroot:
4688 const Value *Alloca = I.getArgOperand(0);
4689 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4691 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4692 GFI->addStackRoot(FI->getIndex(), TypeMap);
4695 case Intrinsic::gcread:
4696 case Intrinsic::gcwrite:
4697 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4699 case Intrinsic::flt_rounds:
4700 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4702 case Intrinsic::trap:
4703 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4705 case Intrinsic::uadd_with_overflow:
4706 return implVisitAluOverflow(I, ISD::UADDO);
4707 case Intrinsic::sadd_with_overflow:
4708 return implVisitAluOverflow(I, ISD::SADDO);
4709 case Intrinsic::usub_with_overflow:
4710 return implVisitAluOverflow(I, ISD::USUBO);
4711 case Intrinsic::ssub_with_overflow:
4712 return implVisitAluOverflow(I, ISD::SSUBO);
4713 case Intrinsic::umul_with_overflow:
4714 return implVisitAluOverflow(I, ISD::UMULO);
4715 case Intrinsic::smul_with_overflow:
4716 return implVisitAluOverflow(I, ISD::SMULO);
4718 case Intrinsic::prefetch: {
4720 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4722 Ops[1] = getValue(I.getArgOperand(0));
4723 Ops[2] = getValue(I.getArgOperand(1));
4724 Ops[3] = getValue(I.getArgOperand(2));
4725 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4726 DAG.getVTList(MVT::Other),
4728 EVT::getIntegerVT(*Context, 8),
4729 MachinePointerInfo(I.getArgOperand(0)),
4731 false, /* volatile */
4733 rw==1)); /* write */
4736 case Intrinsic::memory_barrier: {
4739 for (int x = 1; x < 6; ++x)
4740 Ops[x] = getValue(I.getArgOperand(x - 1));
4742 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4745 case Intrinsic::atomic_cmp_swap: {
4746 SDValue Root = getRoot();
4748 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4749 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4751 getValue(I.getArgOperand(0)),
4752 getValue(I.getArgOperand(1)),
4753 getValue(I.getArgOperand(2)),
4754 MachinePointerInfo(I.getArgOperand(0)));
4756 DAG.setRoot(L.getValue(1));
4759 case Intrinsic::atomic_load_add:
4760 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4761 case Intrinsic::atomic_load_sub:
4762 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4763 case Intrinsic::atomic_load_or:
4764 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4765 case Intrinsic::atomic_load_xor:
4766 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4767 case Intrinsic::atomic_load_and:
4768 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4769 case Intrinsic::atomic_load_nand:
4770 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4771 case Intrinsic::atomic_load_max:
4772 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4773 case Intrinsic::atomic_load_min:
4774 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4775 case Intrinsic::atomic_load_umin:
4776 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4777 case Intrinsic::atomic_load_umax:
4778 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4779 case Intrinsic::atomic_swap:
4780 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4782 case Intrinsic::invariant_start:
4783 case Intrinsic::lifetime_start:
4784 // Discard region information.
4785 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4787 case Intrinsic::invariant_end:
4788 case Intrinsic::lifetime_end:
4789 // Discard region information.
4794 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4796 MachineBasicBlock *LandingPad) {
4797 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4798 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4799 const Type *RetTy = FTy->getReturnType();
4800 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4801 MCSymbol *BeginLabel = 0;
4803 TargetLowering::ArgListTy Args;
4804 TargetLowering::ArgListEntry Entry;
4805 Args.reserve(CS.arg_size());
4807 // Check whether the function can return without sret-demotion.
4808 SmallVector<ISD::OutputArg, 4> Outs;
4809 SmallVector<uint64_t, 4> Offsets;
4810 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4811 Outs, TLI, &Offsets);
4813 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4814 FTy->isVarArg(), Outs, FTy->getContext());
4816 SDValue DemoteStackSlot;
4817 int DemoteStackIdx = -100;
4819 if (!CanLowerReturn) {
4820 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4821 FTy->getReturnType());
4822 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4823 FTy->getReturnType());
4824 MachineFunction &MF = DAG.getMachineFunction();
4825 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4826 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4828 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4829 Entry.Node = DemoteStackSlot;
4830 Entry.Ty = StackSlotPtrType;
4831 Entry.isSExt = false;
4832 Entry.isZExt = false;
4833 Entry.isInReg = false;
4834 Entry.isSRet = true;
4835 Entry.isNest = false;
4836 Entry.isByVal = false;
4837 Entry.Alignment = Align;
4838 Args.push_back(Entry);
4839 RetTy = Type::getVoidTy(FTy->getContext());
4842 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4844 SDValue ArgNode = getValue(*i);
4845 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4847 unsigned attrInd = i - CS.arg_begin() + 1;
4848 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4849 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4850 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4851 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4852 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4853 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4854 Entry.Alignment = CS.getParamAlignment(attrInd);
4855 Args.push_back(Entry);
4859 // Insert a label before the invoke call to mark the try range. This can be
4860 // used to detect deletion of the invoke via the MachineModuleInfo.
4861 BeginLabel = MMI.getContext().CreateTempSymbol();
4863 // For SjLj, keep track of which landing pads go with which invokes
4864 // so as to maintain the ordering of pads in the LSDA.
4865 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4866 if (CallSiteIndex) {
4867 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4868 // Now that the call site is handled, stop tracking it.
4869 MMI.setCurrentCallSite(0);
4872 // Both PendingLoads and PendingExports must be flushed here;
4873 // this call might not return.
4875 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4878 // Check if target-independent constraints permit a tail call here.
4879 // Target-dependent constraints are checked within TLI.LowerCallTo.
4881 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4884 // If there's a possibility that fast-isel has already selected some amount
4885 // of the current basic block, don't emit a tail call.
4886 if (isTailCall && EnableFastISel)
4889 std::pair<SDValue,SDValue> Result =
4890 TLI.LowerCallTo(getRoot(), RetTy,
4891 CS.paramHasAttr(0, Attribute::SExt),
4892 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4893 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4894 CS.getCallingConv(),
4896 !CS.getInstruction()->use_empty(),
4897 Callee, Args, DAG, getCurDebugLoc());
4898 assert((isTailCall || Result.second.getNode()) &&
4899 "Non-null chain expected with non-tail call!");
4900 assert((Result.second.getNode() || !Result.first.getNode()) &&
4901 "Null value expected with tail call!");
4902 if (Result.first.getNode()) {
4903 setValue(CS.getInstruction(), Result.first);
4904 } else if (!CanLowerReturn && Result.second.getNode()) {
4905 // The instruction result is the result of loading from the
4906 // hidden sret parameter.
4907 SmallVector<EVT, 1> PVTs;
4908 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4910 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4911 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4912 EVT PtrVT = PVTs[0];
4913 unsigned NumValues = Outs.size();
4914 SmallVector<SDValue, 4> Values(NumValues);
4915 SmallVector<SDValue, 4> Chains(NumValues);
4917 for (unsigned i = 0; i < NumValues; ++i) {
4918 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4920 DAG.getConstant(Offsets[i], PtrVT));
4921 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4923 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4926 Chains[i] = L.getValue(1);
4929 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4930 MVT::Other, &Chains[0], NumValues);
4931 PendingLoads.push_back(Chain);
4933 // Collect the legal value parts into potentially illegal values
4934 // that correspond to the original function's return values.
4935 SmallVector<EVT, 4> RetTys;
4936 RetTy = FTy->getReturnType();
4937 ComputeValueVTs(TLI, RetTy, RetTys);
4938 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4939 SmallVector<SDValue, 4> ReturnValues;
4940 unsigned CurReg = 0;
4941 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4943 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4944 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4946 SDValue ReturnValue =
4947 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4948 RegisterVT, VT, AssertOp);
4949 ReturnValues.push_back(ReturnValue);
4953 setValue(CS.getInstruction(),
4954 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4955 DAG.getVTList(&RetTys[0], RetTys.size()),
4956 &ReturnValues[0], ReturnValues.size()));
4960 // As a special case, a null chain means that a tail call has been emitted and
4961 // the DAG root is already updated.
4962 if (Result.second.getNode())
4963 DAG.setRoot(Result.second);
4968 // Insert a label at the end of the invoke call to mark the try range. This
4969 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4970 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4971 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4973 // Inform MachineModuleInfo of range.
4974 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4978 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4979 /// value is equal or not-equal to zero.
4980 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4981 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4983 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4984 if (IC->isEquality())
4985 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4986 if (C->isNullValue())
4988 // Unknown instruction.
4994 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4996 SelectionDAGBuilder &Builder) {
4998 // Check to see if this load can be trivially constant folded, e.g. if the
4999 // input is from a string literal.
5000 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5001 // Cast pointer to the type we really want to load.
5002 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5003 PointerType::getUnqual(LoadTy));
5005 if (const Constant *LoadCst =
5006 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5008 return Builder.getValue(LoadCst);
5011 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5012 // still constant memory, the input chain can be the entry node.
5014 bool ConstantMemory = false;
5016 // Do not serialize (non-volatile) loads of constant memory with anything.
5017 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5018 Root = Builder.DAG.getEntryNode();
5019 ConstantMemory = true;
5021 // Do not serialize non-volatile loads against each other.
5022 Root = Builder.DAG.getRoot();
5025 SDValue Ptr = Builder.getValue(PtrVal);
5026 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5027 Ptr, MachinePointerInfo(PtrVal),
5029 false /*nontemporal*/, 1 /* align=1 */);
5031 if (!ConstantMemory)
5032 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5037 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5038 /// If so, return true and lower it, otherwise return false and it will be
5039 /// lowered like a normal call.
5040 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5041 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5042 if (I.getNumArgOperands() != 3)
5045 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5046 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5047 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5048 !I.getType()->isIntegerTy())
5051 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5053 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5054 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5055 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5056 bool ActuallyDoIt = true;
5059 switch (Size->getZExtValue()) {
5061 LoadVT = MVT::Other;
5063 ActuallyDoIt = false;
5067 LoadTy = Type::getInt16Ty(Size->getContext());
5071 LoadTy = Type::getInt32Ty(Size->getContext());
5075 LoadTy = Type::getInt64Ty(Size->getContext());
5079 LoadVT = MVT::v4i32;
5080 LoadTy = Type::getInt32Ty(Size->getContext());
5081 LoadTy = VectorType::get(LoadTy, 4);
5086 // This turns into unaligned loads. We only do this if the target natively
5087 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5088 // we'll only produce a small number of byte loads.
5090 // Require that we can find a legal MVT, and only do this if the target
5091 // supports unaligned loads of that type. Expanding into byte loads would
5093 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5094 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5095 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5096 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5097 ActuallyDoIt = false;
5101 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5102 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5104 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5106 EVT CallVT = TLI.getValueType(I.getType(), true);
5107 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5117 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5118 // Handle inline assembly differently.
5119 if (isa<InlineAsm>(I.getCalledValue())) {
5124 // See if any floating point values are being passed to this function. This is
5125 // used to emit an undefined reference to fltused on Windows.
5126 const FunctionType *FT =
5127 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5128 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5129 if (FT->isVarArg() &&
5130 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5131 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5132 const Type* T = I.getArgOperand(i)->getType();
5133 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5135 if (!i->isFloatingPointTy()) continue;
5136 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5142 const char *RenameFn = 0;
5143 if (Function *F = I.getCalledFunction()) {
5144 if (F->isDeclaration()) {
5145 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5146 if (unsigned IID = II->getIntrinsicID(F)) {
5147 RenameFn = visitIntrinsicCall(I, IID);
5152 if (unsigned IID = F->getIntrinsicID()) {
5153 RenameFn = visitIntrinsicCall(I, IID);
5159 // Check for well-known libc/libm calls. If the function is internal, it
5160 // can't be a library call.
5161 if (!F->hasLocalLinkage() && F->hasName()) {
5162 StringRef Name = F->getName();
5163 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5164 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5165 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5166 I.getType() == I.getArgOperand(0)->getType() &&
5167 I.getType() == I.getArgOperand(1)->getType()) {
5168 SDValue LHS = getValue(I.getArgOperand(0));
5169 SDValue RHS = getValue(I.getArgOperand(1));
5170 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5171 LHS.getValueType(), LHS, RHS));
5174 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5175 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5176 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5177 I.getType() == I.getArgOperand(0)->getType()) {
5178 SDValue Tmp = getValue(I.getArgOperand(0));
5179 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5180 Tmp.getValueType(), Tmp));
5183 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5184 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5185 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5186 I.getType() == I.getArgOperand(0)->getType() &&
5187 I.onlyReadsMemory()) {
5188 SDValue Tmp = getValue(I.getArgOperand(0));
5189 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5190 Tmp.getValueType(), Tmp));
5193 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5194 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5195 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5196 I.getType() == I.getArgOperand(0)->getType() &&
5197 I.onlyReadsMemory()) {
5198 SDValue Tmp = getValue(I.getArgOperand(0));
5199 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5200 Tmp.getValueType(), Tmp));
5203 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5204 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5205 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5206 I.getType() == I.getArgOperand(0)->getType() &&
5207 I.onlyReadsMemory()) {
5208 SDValue Tmp = getValue(I.getArgOperand(0));
5209 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5210 Tmp.getValueType(), Tmp));
5213 } else if (Name == "memcmp") {
5214 if (visitMemCmpCall(I))
5222 Callee = getValue(I.getCalledValue());
5224 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5226 // Check if we can potentially perform a tail call. More detailed checking is
5227 // be done within LowerCallTo, after more information about the call is known.
5228 LowerCallTo(&I, Callee, I.isTailCall());
5233 /// AsmOperandInfo - This contains information for each constraint that we are
5235 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5236 public TargetLowering::AsmOperandInfo {
5238 /// CallOperand - If this is the result output operand or a clobber
5239 /// this is null, otherwise it is the incoming operand to the CallInst.
5240 /// This gets modified as the asm is processed.
5241 SDValue CallOperand;
5243 /// AssignedRegs - If this is a register or register class operand, this
5244 /// contains the set of register corresponding to the operand.
5245 RegsForValue AssignedRegs;
5247 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5248 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5251 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5252 /// busy in OutputRegs/InputRegs.
5253 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5254 std::set<unsigned> &OutputRegs,
5255 std::set<unsigned> &InputRegs,
5256 const TargetRegisterInfo &TRI) const {
5258 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5259 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5262 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5263 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5267 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5268 /// corresponds to. If there is no Value* for this operand, it returns
5270 EVT getCallOperandValEVT(LLVMContext &Context,
5271 const TargetLowering &TLI,
5272 const TargetData *TD) const {
5273 if (CallOperandVal == 0) return MVT::Other;
5275 if (isa<BasicBlock>(CallOperandVal))
5276 return TLI.getPointerTy();
5278 const llvm::Type *OpTy = CallOperandVal->getType();
5280 // If this is an indirect operand, the operand is a pointer to the
5283 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5285 report_fatal_error("Indirect operand for inline asm not a pointer!");
5286 OpTy = PtrTy->getElementType();
5289 // If OpTy is not a single value, it may be a struct/union that we
5290 // can tile with integers.
5291 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5292 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5301 OpTy = IntegerType::get(Context, BitSize);
5306 return TLI.getValueType(OpTy, true);
5310 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5312 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5313 const TargetRegisterInfo &TRI) {
5314 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5316 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5317 for (; *Aliases; ++Aliases)
5318 Regs.insert(*Aliases);
5322 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5324 } // end llvm namespace.
5326 /// isAllocatableRegister - If the specified register is safe to allocate,
5327 /// i.e. it isn't a stack pointer or some other special register, return the
5328 /// register class for the register. Otherwise, return null.
5329 static const TargetRegisterClass *
5330 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5331 const TargetLowering &TLI,
5332 const TargetRegisterInfo *TRI) {
5333 EVT FoundVT = MVT::Other;
5334 const TargetRegisterClass *FoundRC = 0;
5335 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5336 E = TRI->regclass_end(); RCI != E; ++RCI) {
5337 EVT ThisVT = MVT::Other;
5339 const TargetRegisterClass *RC = *RCI;
5340 // If none of the value types for this register class are valid, we
5341 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5342 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5344 if (TLI.isTypeLegal(*I)) {
5345 // If we have already found this register in a different register class,
5346 // choose the one with the largest VT specified. For example, on
5347 // PowerPC, we favor f64 register classes over f32.
5348 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5355 if (ThisVT == MVT::Other) continue;
5357 // NOTE: This isn't ideal. In particular, this might allocate the
5358 // frame pointer in functions that need it (due to them not being taken
5359 // out of allocation, because a variable sized allocation hasn't been seen
5360 // yet). This is a slight code pessimization, but should still work.
5361 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5362 E = RC->allocation_order_end(MF); I != E; ++I)
5364 // We found a matching register class. Keep looking at others in case
5365 // we find one with larger registers that this physreg is also in.
5374 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5375 /// specified operand. We prefer to assign virtual registers, to allow the
5376 /// register allocator to handle the assignment process. However, if the asm
5377 /// uses features that we can't model on machineinstrs, we have SDISel do the
5378 /// allocation. This produces generally horrible, but correct, code.
5380 /// OpInfo describes the operand.
5381 /// Input and OutputRegs are the set of already allocated physical registers.
5383 void SelectionDAGBuilder::
5384 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5385 std::set<unsigned> &OutputRegs,
5386 std::set<unsigned> &InputRegs) {
5387 LLVMContext &Context = FuncInfo.Fn->getContext();
5389 // Compute whether this value requires an input register, an output register,
5391 bool isOutReg = false;
5392 bool isInReg = false;
5393 switch (OpInfo.Type) {
5394 case InlineAsm::isOutput:
5397 // If there is an input constraint that matches this, we need to reserve
5398 // the input register so no other inputs allocate to it.
5399 isInReg = OpInfo.hasMatchingInput();
5401 case InlineAsm::isInput:
5405 case InlineAsm::isClobber:
5412 MachineFunction &MF = DAG.getMachineFunction();
5413 SmallVector<unsigned, 4> Regs;
5415 // If this is a constraint for a single physreg, or a constraint for a
5416 // register class, find it.
5417 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5418 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5419 OpInfo.ConstraintVT);
5421 unsigned NumRegs = 1;
5422 if (OpInfo.ConstraintVT != MVT::Other) {
5423 // If this is a FP input in an integer register (or visa versa) insert a bit
5424 // cast of the input value. More generally, handle any case where the input
5425 // value disagrees with the register class we plan to stick this in.
5426 if (OpInfo.Type == InlineAsm::isInput &&
5427 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5428 // Try to convert to the first EVT that the reg class contains. If the
5429 // types are identical size, use a bitcast to convert (e.g. two differing
5431 EVT RegVT = *PhysReg.second->vt_begin();
5432 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5433 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5434 RegVT, OpInfo.CallOperand);
5435 OpInfo.ConstraintVT = RegVT;
5436 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5437 // If the input is a FP value and we want it in FP registers, do a
5438 // bitcast to the corresponding integer type. This turns an f64 value
5439 // into i64, which can be passed with two i32 values on a 32-bit
5441 RegVT = EVT::getIntegerVT(Context,
5442 OpInfo.ConstraintVT.getSizeInBits());
5443 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5444 RegVT, OpInfo.CallOperand);
5445 OpInfo.ConstraintVT = RegVT;
5449 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5453 EVT ValueVT = OpInfo.ConstraintVT;
5455 // If this is a constraint for a specific physical register, like {r17},
5457 if (unsigned AssignedReg = PhysReg.first) {
5458 const TargetRegisterClass *RC = PhysReg.second;
5459 if (OpInfo.ConstraintVT == MVT::Other)
5460 ValueVT = *RC->vt_begin();
5462 // Get the actual register value type. This is important, because the user
5463 // may have asked for (e.g.) the AX register in i32 type. We need to
5464 // remember that AX is actually i16 to get the right extension.
5465 RegVT = *RC->vt_begin();
5467 // This is a explicit reference to a physical register.
5468 Regs.push_back(AssignedReg);
5470 // If this is an expanded reference, add the rest of the regs to Regs.
5472 TargetRegisterClass::iterator I = RC->begin();
5473 for (; *I != AssignedReg; ++I)
5474 assert(I != RC->end() && "Didn't find reg!");
5476 // Already added the first reg.
5478 for (; NumRegs; --NumRegs, ++I) {
5479 assert(I != RC->end() && "Ran out of registers to allocate!");
5484 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5485 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5486 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5490 // Otherwise, if this was a reference to an LLVM register class, create vregs
5491 // for this reference.
5492 if (const TargetRegisterClass *RC = PhysReg.second) {
5493 RegVT = *RC->vt_begin();
5494 if (OpInfo.ConstraintVT == MVT::Other)
5497 // Create the appropriate number of virtual registers.
5498 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5499 for (; NumRegs; --NumRegs)
5500 Regs.push_back(RegInfo.createVirtualRegister(RC));
5502 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5506 // This is a reference to a register class that doesn't directly correspond
5507 // to an LLVM register class. Allocate NumRegs consecutive, available,
5508 // registers from the class.
5509 std::vector<unsigned> RegClassRegs
5510 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5511 OpInfo.ConstraintVT);
5513 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5514 unsigned NumAllocated = 0;
5515 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5516 unsigned Reg = RegClassRegs[i];
5517 // See if this register is available.
5518 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5519 (isInReg && InputRegs.count(Reg))) { // Already used.
5520 // Make sure we find consecutive registers.
5525 // Check to see if this register is allocatable (i.e. don't give out the
5527 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5528 if (!RC) { // Couldn't allocate this register.
5529 // Reset NumAllocated to make sure we return consecutive registers.
5534 // Okay, this register is good, we can use it.
5537 // If we allocated enough consecutive registers, succeed.
5538 if (NumAllocated == NumRegs) {
5539 unsigned RegStart = (i-NumAllocated)+1;
5540 unsigned RegEnd = i+1;
5541 // Mark all of the allocated registers used.
5542 for (unsigned i = RegStart; i != RegEnd; ++i)
5543 Regs.push_back(RegClassRegs[i]);
5545 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5546 OpInfo.ConstraintVT);
5547 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5552 // Otherwise, we couldn't allocate enough registers for this.
5555 /// visitInlineAsm - Handle a call to an InlineAsm object.
5557 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5558 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5560 /// ConstraintOperands - Information about all of the constraints.
5561 SDISelAsmOperandInfoVector ConstraintOperands;
5563 std::set<unsigned> OutputRegs, InputRegs;
5565 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5566 bool hasMemory = false;
5568 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5569 unsigned ResNo = 0; // ResNo - The result number of the next output.
5570 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5571 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5572 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5574 EVT OpVT = MVT::Other;
5576 // Compute the value type for each operand.
5577 switch (OpInfo.Type) {
5578 case InlineAsm::isOutput:
5579 // Indirect outputs just consume an argument.
5580 if (OpInfo.isIndirect) {
5581 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5585 // The return value of the call is this value. As such, there is no
5586 // corresponding argument.
5587 assert(!CS.getType()->isVoidTy() &&
5589 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5590 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5592 assert(ResNo == 0 && "Asm only has one result!");
5593 OpVT = TLI.getValueType(CS.getType());
5597 case InlineAsm::isInput:
5598 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5600 case InlineAsm::isClobber:
5605 // If this is an input or an indirect output, process the call argument.
5606 // BasicBlocks are labels, currently appearing only in asm's.
5607 if (OpInfo.CallOperandVal) {
5608 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5609 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5611 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5614 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5617 OpInfo.ConstraintVT = OpVT;
5619 // Indirect operand accesses access memory.
5620 if (OpInfo.isIndirect)
5623 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5624 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5625 if (CType == TargetLowering::C_Memory) {
5633 SDValue Chain, Flag;
5635 // We won't need to flush pending loads if this asm doesn't touch
5636 // memory and is nonvolatile.
5637 if (hasMemory || IA->hasSideEffects())
5640 Chain = DAG.getRoot();
5642 // Second pass over the constraints: compute which constraint option to use
5643 // and assign registers to constraints that want a specific physreg.
5644 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5645 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5647 // If this is an output operand with a matching input operand, look up the
5648 // matching input. If their types mismatch, e.g. one is an integer, the
5649 // other is floating point, or their sizes are different, flag it as an
5651 if (OpInfo.hasMatchingInput()) {
5652 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5654 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5655 if ((OpInfo.ConstraintVT.isInteger() !=
5656 Input.ConstraintVT.isInteger()) ||
5657 (OpInfo.ConstraintVT.getSizeInBits() !=
5658 Input.ConstraintVT.getSizeInBits())) {
5659 report_fatal_error("Unsupported asm: input constraint"
5660 " with a matching output constraint of"
5661 " incompatible type!");
5663 Input.ConstraintVT = OpInfo.ConstraintVT;
5667 // Compute the constraint code and ConstraintType to use.
5668 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5670 // If this is a memory input, and if the operand is not indirect, do what we
5671 // need to to provide an address for the memory input.
5672 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5673 !OpInfo.isIndirect) {
5674 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5675 "Can only indirectify direct input operands!");
5677 // Memory operands really want the address of the value. If we don't have
5678 // an indirect input, put it in the constpool if we can, otherwise spill
5679 // it to a stack slot.
5681 // If the operand is a float, integer, or vector constant, spill to a
5682 // constant pool entry to get its address.
5683 const Value *OpVal = OpInfo.CallOperandVal;
5684 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5685 isa<ConstantVector>(OpVal)) {
5686 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5687 TLI.getPointerTy());
5689 // Otherwise, create a stack slot and emit a store to it before the
5691 const Type *Ty = OpVal->getType();
5692 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5693 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5694 MachineFunction &MF = DAG.getMachineFunction();
5695 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5696 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5697 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5698 OpInfo.CallOperand, StackSlot,
5699 MachinePointerInfo::getFixedStack(SSFI),
5701 OpInfo.CallOperand = StackSlot;
5704 // There is no longer a Value* corresponding to this operand.
5705 OpInfo.CallOperandVal = 0;
5707 // It is now an indirect operand.
5708 OpInfo.isIndirect = true;
5711 // If this constraint is for a specific register, allocate it before
5713 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5714 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5717 // Second pass - Loop over all of the operands, assigning virtual or physregs
5718 // to register class operands.
5719 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5720 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5722 // C_Register operands have already been allocated, Other/Memory don't need
5724 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5725 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5728 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5729 std::vector<SDValue> AsmNodeOperands;
5730 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5731 AsmNodeOperands.push_back(
5732 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5733 TLI.getPointerTy()));
5735 // If we have a !srcloc metadata node associated with it, we want to attach
5736 // this to the ultimately generated inline asm machineinstr. To do this, we
5737 // pass in the third operand as this (potentially null) inline asm MDNode.
5738 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5739 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5741 // Remember the HasSideEffect and AlignStack bits as operand 3.
5742 unsigned ExtraInfo = 0;
5743 if (IA->hasSideEffects())
5744 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5745 if (IA->isAlignStack())
5746 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5747 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5748 TLI.getPointerTy()));
5750 // Loop over all of the inputs, copying the operand values into the
5751 // appropriate registers and processing the output regs.
5752 RegsForValue RetValRegs;
5754 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5755 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5757 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5758 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5760 switch (OpInfo.Type) {
5761 case InlineAsm::isOutput: {
5762 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5763 OpInfo.ConstraintType != TargetLowering::C_Register) {
5764 // Memory output, or 'other' output (e.g. 'X' constraint).
5765 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5767 // Add information to the INLINEASM node to know about this output.
5768 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5769 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5770 TLI.getPointerTy()));
5771 AsmNodeOperands.push_back(OpInfo.CallOperand);
5775 // Otherwise, this is a register or register class output.
5777 // Copy the output from the appropriate register. Find a register that
5779 if (OpInfo.AssignedRegs.Regs.empty())
5780 report_fatal_error("Couldn't allocate output reg for constraint '" +
5781 Twine(OpInfo.ConstraintCode) + "'!");
5783 // If this is an indirect operand, store through the pointer after the
5785 if (OpInfo.isIndirect) {
5786 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5787 OpInfo.CallOperandVal));
5789 // This is the result value of the call.
5790 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5791 // Concatenate this output onto the outputs list.
5792 RetValRegs.append(OpInfo.AssignedRegs);
5795 // Add information to the INLINEASM node to know that this register is
5797 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5798 InlineAsm::Kind_RegDefEarlyClobber :
5799 InlineAsm::Kind_RegDef,
5806 case InlineAsm::isInput: {
5807 SDValue InOperandVal = OpInfo.CallOperand;
5809 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5810 // If this is required to match an output register we have already set,
5811 // just use its register.
5812 unsigned OperandNo = OpInfo.getMatchedOperand();
5814 // Scan until we find the definition we already emitted of this operand.
5815 // When we find it, create a RegsForValue operand.
5816 unsigned CurOp = InlineAsm::Op_FirstOperand;
5817 for (; OperandNo; --OperandNo) {
5818 // Advance to the next operand.
5820 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5821 assert((InlineAsm::isRegDefKind(OpFlag) ||
5822 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5823 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5824 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5828 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5829 if (InlineAsm::isRegDefKind(OpFlag) ||
5830 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5831 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5832 if (OpInfo.isIndirect) {
5833 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5834 LLVMContext &Ctx = *DAG.getContext();
5835 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5836 " don't know how to handle tied "
5837 "indirect register inputs");
5840 RegsForValue MatchedRegs;
5841 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5842 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5843 MatchedRegs.RegVTs.push_back(RegVT);
5844 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5845 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5847 MatchedRegs.Regs.push_back
5848 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5850 // Use the produced MatchedRegs object to
5851 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5853 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5854 true, OpInfo.getMatchedOperand(),
5855 DAG, AsmNodeOperands);
5859 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5860 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5861 "Unexpected number of operands");
5862 // Add information to the INLINEASM node to know about this input.
5863 // See InlineAsm.h isUseOperandTiedToDef.
5864 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5865 OpInfo.getMatchedOperand());
5866 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5867 TLI.getPointerTy()));
5868 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5872 // Treat indirect 'X' constraint as memory.
5873 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5875 OpInfo.ConstraintType = TargetLowering::C_Memory;
5877 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5878 std::vector<SDValue> Ops;
5879 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5882 report_fatal_error("Invalid operand for inline asm constraint '" +
5883 Twine(OpInfo.ConstraintCode) + "'!");
5885 // Add information to the INLINEASM node to know about this input.
5886 unsigned ResOpType =
5887 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5888 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5889 TLI.getPointerTy()));
5890 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5894 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5895 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5896 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5897 "Memory operands expect pointer values");
5899 // Add information to the INLINEASM node to know about this input.
5900 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5901 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5902 TLI.getPointerTy()));
5903 AsmNodeOperands.push_back(InOperandVal);
5907 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5908 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5909 "Unknown constraint type!");
5910 assert(!OpInfo.isIndirect &&
5911 "Don't know how to handle indirect register inputs yet!");
5913 // Copy the input into the appropriate registers.
5914 if (OpInfo.AssignedRegs.Regs.empty() ||
5915 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5916 report_fatal_error("Couldn't allocate input reg for constraint '" +
5917 Twine(OpInfo.ConstraintCode) + "'!");
5919 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5922 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5923 DAG, AsmNodeOperands);
5926 case InlineAsm::isClobber: {
5927 // Add the clobbered value to the operand list, so that the register
5928 // allocator is aware that the physreg got clobbered.
5929 if (!OpInfo.AssignedRegs.Regs.empty())
5930 OpInfo.AssignedRegs.AddInlineAsmOperands(
5931 InlineAsm::Kind_RegDefEarlyClobber,
5939 // Finish up input operands. Set the input chain and add the flag last.
5940 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5941 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5943 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5944 DAG.getVTList(MVT::Other, MVT::Glue),
5945 &AsmNodeOperands[0], AsmNodeOperands.size());
5946 Flag = Chain.getValue(1);
5948 // If this asm returns a register value, copy the result from that register
5949 // and set it as the value of the call.
5950 if (!RetValRegs.Regs.empty()) {
5951 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5954 // FIXME: Why don't we do this for inline asms with MRVs?
5955 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5956 EVT ResultType = TLI.getValueType(CS.getType());
5958 // If any of the results of the inline asm is a vector, it may have the
5959 // wrong width/num elts. This can happen for register classes that can
5960 // contain multiple different value types. The preg or vreg allocated may
5961 // not have the same VT as was expected. Convert it to the right type
5962 // with bit_convert.
5963 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5964 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5967 } else if (ResultType != Val.getValueType() &&
5968 ResultType.isInteger() && Val.getValueType().isInteger()) {
5969 // If a result value was tied to an input value, the computed result may
5970 // have a wider width than the expected result. Extract the relevant
5972 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5975 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5978 setValue(CS.getInstruction(), Val);
5979 // Don't need to use this as a chain in this case.
5980 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5984 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5986 // Process indirect outputs, first output all of the flagged copies out of
5988 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5989 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5990 const Value *Ptr = IndirectStoresToEmit[i].second;
5991 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5993 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5996 // Emit the non-flagged stores from the physregs.
5997 SmallVector<SDValue, 8> OutChains;
5998 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5999 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6000 StoresToEmit[i].first,
6001 getValue(StoresToEmit[i].second),
6002 MachinePointerInfo(StoresToEmit[i].second),
6004 OutChains.push_back(Val);
6007 if (!OutChains.empty())
6008 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6009 &OutChains[0], OutChains.size());
6014 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6015 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6016 MVT::Other, getRoot(),
6017 getValue(I.getArgOperand(0)),
6018 DAG.getSrcValue(I.getArgOperand(0))));
6021 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6022 const TargetData &TD = *TLI.getTargetData();
6023 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6024 getRoot(), getValue(I.getOperand(0)),
6025 DAG.getSrcValue(I.getOperand(0)),
6026 TD.getABITypeAlignment(I.getType()));
6028 DAG.setRoot(V.getValue(1));
6031 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6032 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6033 MVT::Other, getRoot(),
6034 getValue(I.getArgOperand(0)),
6035 DAG.getSrcValue(I.getArgOperand(0))));
6038 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6039 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6040 MVT::Other, getRoot(),
6041 getValue(I.getArgOperand(0)),
6042 getValue(I.getArgOperand(1)),
6043 DAG.getSrcValue(I.getArgOperand(0)),
6044 DAG.getSrcValue(I.getArgOperand(1))));
6047 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6048 /// implementation, which just calls LowerCall.
6049 /// FIXME: When all targets are
6050 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6051 std::pair<SDValue, SDValue>
6052 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6053 bool RetSExt, bool RetZExt, bool isVarArg,
6054 bool isInreg, unsigned NumFixedArgs,
6055 CallingConv::ID CallConv, bool isTailCall,
6056 bool isReturnValueUsed,
6058 ArgListTy &Args, SelectionDAG &DAG,
6059 DebugLoc dl) const {
6060 // Handle all of the outgoing arguments.
6061 SmallVector<ISD::OutputArg, 32> Outs;
6062 SmallVector<SDValue, 32> OutVals;
6063 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6064 SmallVector<EVT, 4> ValueVTs;
6065 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6066 for (unsigned Value = 0, NumValues = ValueVTs.size();
6067 Value != NumValues; ++Value) {
6068 EVT VT = ValueVTs[Value];
6069 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6070 SDValue Op = SDValue(Args[i].Node.getNode(),
6071 Args[i].Node.getResNo() + Value);
6072 ISD::ArgFlagsTy Flags;
6073 unsigned OriginalAlignment =
6074 getTargetData()->getABITypeAlignment(ArgTy);
6080 if (Args[i].isInReg)
6084 if (Args[i].isByVal) {
6086 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6087 const Type *ElementTy = Ty->getElementType();
6088 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6089 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6090 // For ByVal, alignment should come from FE. BE will guess if this
6091 // info is not there but there are cases it cannot get right.
6092 if (Args[i].Alignment)
6093 FrameAlign = Args[i].Alignment;
6094 Flags.setByValAlign(FrameAlign);
6095 Flags.setByValSize(FrameSize);
6099 Flags.setOrigAlign(OriginalAlignment);
6101 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6102 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6103 SmallVector<SDValue, 4> Parts(NumParts);
6104 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6107 ExtendKind = ISD::SIGN_EXTEND;
6108 else if (Args[i].isZExt)
6109 ExtendKind = ISD::ZERO_EXTEND;
6111 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6112 PartVT, ExtendKind);
6114 for (unsigned j = 0; j != NumParts; ++j) {
6115 // if it isn't first piece, alignment must be 1
6116 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6118 if (NumParts > 1 && j == 0)
6119 MyFlags.Flags.setSplit();
6121 MyFlags.Flags.setOrigAlign(1);
6123 Outs.push_back(MyFlags);
6124 OutVals.push_back(Parts[j]);
6129 // Handle the incoming return values from the call.
6130 SmallVector<ISD::InputArg, 32> Ins;
6131 SmallVector<EVT, 4> RetTys;
6132 ComputeValueVTs(*this, RetTy, RetTys);
6133 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6135 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6136 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6137 for (unsigned i = 0; i != NumRegs; ++i) {
6138 ISD::InputArg MyFlags;
6139 MyFlags.VT = RegisterVT.getSimpleVT();
6140 MyFlags.Used = isReturnValueUsed;
6142 MyFlags.Flags.setSExt();
6144 MyFlags.Flags.setZExt();
6146 MyFlags.Flags.setInReg();
6147 Ins.push_back(MyFlags);
6151 SmallVector<SDValue, 4> InVals;
6152 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6153 Outs, OutVals, Ins, dl, DAG, InVals);
6155 // Verify that the target's LowerCall behaved as expected.
6156 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6157 "LowerCall didn't return a valid chain!");
6158 assert((!isTailCall || InVals.empty()) &&
6159 "LowerCall emitted a return value for a tail call!");
6160 assert((isTailCall || InVals.size() == Ins.size()) &&
6161 "LowerCall didn't emit the correct number of values!");
6163 // For a tail call, the return value is merely live-out and there aren't
6164 // any nodes in the DAG representing it. Return a special value to
6165 // indicate that a tail call has been emitted and no more Instructions
6166 // should be processed in the current block.
6169 return std::make_pair(SDValue(), SDValue());
6172 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6173 assert(InVals[i].getNode() &&
6174 "LowerCall emitted a null value!");
6175 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6176 "LowerCall emitted a value with the wrong type!");
6179 // Collect the legal value parts into potentially illegal values
6180 // that correspond to the original function's return values.
6181 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6183 AssertOp = ISD::AssertSext;
6185 AssertOp = ISD::AssertZext;
6186 SmallVector<SDValue, 4> ReturnValues;
6187 unsigned CurReg = 0;
6188 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6190 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6191 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6193 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6194 NumRegs, RegisterVT, VT,
6199 // For a function returning void, there is no return value. We can't create
6200 // such a node, so we just return a null return value in that case. In
6201 // that case, nothing will actualy look at the value.
6202 if (ReturnValues.empty())
6203 return std::make_pair(SDValue(), Chain);
6205 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6206 DAG.getVTList(&RetTys[0], RetTys.size()),
6207 &ReturnValues[0], ReturnValues.size());
6208 return std::make_pair(Res, Chain);
6211 void TargetLowering::LowerOperationWrapper(SDNode *N,
6212 SmallVectorImpl<SDValue> &Results,
6213 SelectionDAG &DAG) const {
6214 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6216 Results.push_back(Res);
6219 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6220 llvm_unreachable("LowerOperation not implemented for this target!");
6225 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6226 SDValue Op = getNonRegisterValue(V);
6227 assert((Op.getOpcode() != ISD::CopyFromReg ||
6228 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6229 "Copy from a reg to the same reg!");
6230 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6232 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6233 SDValue Chain = DAG.getEntryNode();
6234 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6235 PendingExports.push_back(Chain);
6238 #include "llvm/CodeGen/SelectionDAGISel.h"
6240 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6241 // If this is the entry block, emit arguments.
6242 const Function &F = *LLVMBB->getParent();
6243 SelectionDAG &DAG = SDB->DAG;
6244 DebugLoc dl = SDB->getCurDebugLoc();
6245 const TargetData *TD = TLI.getTargetData();
6246 SmallVector<ISD::InputArg, 16> Ins;
6248 // Check whether the function can return without sret-demotion.
6249 SmallVector<ISD::OutputArg, 4> Outs;
6250 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6253 if (!FuncInfo->CanLowerReturn) {
6254 // Put in an sret pointer parameter before all the other parameters.
6255 SmallVector<EVT, 1> ValueVTs;
6256 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6258 // NOTE: Assuming that a pointer will never break down to more than one VT
6260 ISD::ArgFlagsTy Flags;
6262 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6263 ISD::InputArg RetArg(Flags, RegisterVT, true);
6264 Ins.push_back(RetArg);
6267 // Set up the incoming argument description vector.
6269 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6270 I != E; ++I, ++Idx) {
6271 SmallVector<EVT, 4> ValueVTs;
6272 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6273 bool isArgValueUsed = !I->use_empty();
6274 for (unsigned Value = 0, NumValues = ValueVTs.size();
6275 Value != NumValues; ++Value) {
6276 EVT VT = ValueVTs[Value];
6277 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6278 ISD::ArgFlagsTy Flags;
6279 unsigned OriginalAlignment =
6280 TD->getABITypeAlignment(ArgTy);
6282 if (F.paramHasAttr(Idx, Attribute::ZExt))
6284 if (F.paramHasAttr(Idx, Attribute::SExt))
6286 if (F.paramHasAttr(Idx, Attribute::InReg))
6288 if (F.paramHasAttr(Idx, Attribute::StructRet))
6290 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6292 const PointerType *Ty = cast<PointerType>(I->getType());
6293 const Type *ElementTy = Ty->getElementType();
6294 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6295 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6296 // For ByVal, alignment should be passed from FE. BE will guess if
6297 // this info is not there but there are cases it cannot get right.
6298 if (F.getParamAlignment(Idx))
6299 FrameAlign = F.getParamAlignment(Idx);
6300 Flags.setByValAlign(FrameAlign);
6301 Flags.setByValSize(FrameSize);
6303 if (F.paramHasAttr(Idx, Attribute::Nest))
6305 Flags.setOrigAlign(OriginalAlignment);
6307 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6308 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6309 for (unsigned i = 0; i != NumRegs; ++i) {
6310 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6311 if (NumRegs > 1 && i == 0)
6312 MyFlags.Flags.setSplit();
6313 // if it isn't first piece, alignment must be 1
6315 MyFlags.Flags.setOrigAlign(1);
6316 Ins.push_back(MyFlags);
6321 // Call the target to set up the argument values.
6322 SmallVector<SDValue, 8> InVals;
6323 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6327 // Verify that the target's LowerFormalArguments behaved as expected.
6328 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6329 "LowerFormalArguments didn't return a valid chain!");
6330 assert(InVals.size() == Ins.size() &&
6331 "LowerFormalArguments didn't emit the correct number of values!");
6333 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6334 assert(InVals[i].getNode() &&
6335 "LowerFormalArguments emitted a null value!");
6336 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6337 "LowerFormalArguments emitted a value with the wrong type!");
6341 // Update the DAG with the new chain value resulting from argument lowering.
6342 DAG.setRoot(NewRoot);
6344 // Set up the argument values.
6347 if (!FuncInfo->CanLowerReturn) {
6348 // Create a virtual register for the sret pointer, and put in a copy
6349 // from the sret argument into it.
6350 SmallVector<EVT, 1> ValueVTs;
6351 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6352 EVT VT = ValueVTs[0];
6353 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6354 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6355 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6356 RegVT, VT, AssertOp);
6358 MachineFunction& MF = SDB->DAG.getMachineFunction();
6359 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6360 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6361 FuncInfo->DemoteRegister = SRetReg;
6362 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6364 DAG.setRoot(NewRoot);
6366 // i indexes lowered arguments. Bump it past the hidden sret argument.
6367 // Idx indexes LLVM arguments. Don't touch it.
6371 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6373 SmallVector<SDValue, 4> ArgValues;
6374 SmallVector<EVT, 4> ValueVTs;
6375 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6376 unsigned NumValues = ValueVTs.size();
6378 // If this argument is unused then remember its value. It is used to generate
6379 // debugging information.
6380 if (I->use_empty() && NumValues)
6381 SDB->setUnusedArgValue(I, InVals[i]);
6383 for (unsigned Value = 0; Value != NumValues; ++Value) {
6384 EVT VT = ValueVTs[Value];
6385 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6386 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6388 if (!I->use_empty()) {
6389 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6390 if (F.paramHasAttr(Idx, Attribute::SExt))
6391 AssertOp = ISD::AssertSext;
6392 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6393 AssertOp = ISD::AssertZext;
6395 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6396 NumParts, PartVT, VT,
6403 // Note down frame index for byval arguments.
6404 if (I->hasByValAttr() && !ArgValues.empty())
6405 if (FrameIndexSDNode *FI =
6406 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6407 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6409 if (!I->use_empty()) {
6411 if (!ArgValues.empty())
6412 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6413 SDB->getCurDebugLoc());
6414 SDB->setValue(I, Res);
6416 // If this argument is live outside of the entry block, insert a copy from
6417 // whereever we got it to the vreg that other BB's will reference it as.
6418 SDB->CopyToExportRegsIfNeeded(I);
6422 assert(i == InVals.size() && "Argument register count mismatch!");
6424 // Finally, if the target has anything special to do, allow it to do so.
6425 // FIXME: this should insert code into the DAG!
6426 EmitFunctionEntryCode();
6429 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6430 /// ensure constants are generated when needed. Remember the virtual registers
6431 /// that need to be added to the Machine PHI nodes as input. We cannot just
6432 /// directly add them, because expansion might result in multiple MBB's for one
6433 /// BB. As such, the start of the BB might correspond to a different MBB than
6437 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6438 const TerminatorInst *TI = LLVMBB->getTerminator();
6440 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6442 // Check successor nodes' PHI nodes that expect a constant to be available
6444 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6445 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6446 if (!isa<PHINode>(SuccBB->begin())) continue;
6447 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6449 // If this terminator has multiple identical successors (common for
6450 // switches), only handle each succ once.
6451 if (!SuccsHandled.insert(SuccMBB)) continue;
6453 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6455 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6456 // nodes and Machine PHI nodes, but the incoming operands have not been
6458 for (BasicBlock::const_iterator I = SuccBB->begin();
6459 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6460 // Ignore dead phi's.
6461 if (PN->use_empty()) continue;
6464 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6466 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6467 unsigned &RegOut = ConstantsOut[C];
6469 RegOut = FuncInfo.CreateRegs(C->getType());
6470 CopyValueToVirtualRegister(C, RegOut);
6474 DenseMap<const Value *, unsigned>::iterator I =
6475 FuncInfo.ValueMap.find(PHIOp);
6476 if (I != FuncInfo.ValueMap.end())
6479 assert(isa<AllocaInst>(PHIOp) &&
6480 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6481 "Didn't codegen value into a register!??");
6482 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6483 CopyValueToVirtualRegister(PHIOp, Reg);
6487 // Remember that this register needs to added to the machine PHI node as
6488 // the input for this MBB.
6489 SmallVector<EVT, 4> ValueVTs;
6490 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6491 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6492 EVT VT = ValueVTs[vti];
6493 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6494 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6495 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6496 Reg += NumRegisters;
6500 ConstantsOut.clear();