1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
48 #include "llvm/Target/TargetData.h"
49 #include "llvm/Target/TargetFrameInfo.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Support/Compiler.h"
55 #include "llvm/Support/CommandLine.h"
56 #include "llvm/Support/Debug.h"
57 #include "llvm/Support/ErrorHandling.h"
58 #include "llvm/Support/MathExtras.h"
59 #include "llvm/Support/raw_ostream.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 // Limit the width of DAG chains. This is important in general to prevent
75 // prevent DAG-based analysis from blowing up. For example, alias analysis and
76 // load clustering may not complete in reasonable time. It is difficult to
77 // recognize and avoid this situation within each individual analysis, and
78 // future analyses are likely to have the same behavior. Limiting DAG width is
79 // the safe approach, and will be especially important with global DAGs.
81 // MaxParallelChains default is arbitrarily high to avoid affecting
82 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
83 // sequence over this should have been converted to llvm.memcpy by the
84 // frontend. It easy to induce this behavior with .ll code such as:
85 // %buffer = alloca [4096 x i8]
86 // %data = load [4096 x i8]* %argPtr
87 // store [4096 x i8] %data, [4096 x i8]* %buffer
88 static cl::opt<unsigned>
89 MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"),
90 cl::init(64), cl::Hidden);
92 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
93 const SDValue *Parts, unsigned NumParts,
94 EVT PartVT, EVT ValueVT);
96 /// getCopyFromParts - Create a value that contains the specified legal parts
97 /// combined into the value they represent. If the parts combine to a type
98 /// larger then ValueVT then AssertOp can be used to specify whether the extra
99 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
100 /// (ISD::AssertSext).
101 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
102 const SDValue *Parts,
103 unsigned NumParts, EVT PartVT, EVT ValueVT,
104 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
105 if (ValueVT.isVector())
106 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
108 assert(NumParts > 0 && "No parts to assemble!");
109 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
110 SDValue Val = Parts[0];
113 // Assemble the value from multiple parts.
114 if (ValueVT.isInteger()) {
115 unsigned PartBits = PartVT.getSizeInBits();
116 unsigned ValueBits = ValueVT.getSizeInBits();
118 // Assemble the power of 2 part.
119 unsigned RoundParts = NumParts & (NumParts - 1) ?
120 1 << Log2_32(NumParts) : NumParts;
121 unsigned RoundBits = PartBits * RoundParts;
122 EVT RoundVT = RoundBits == ValueBits ?
123 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
126 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
128 if (RoundParts > 2) {
129 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
131 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
132 RoundParts / 2, PartVT, HalfVT);
134 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]);
135 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]);
138 if (TLI.isBigEndian())
141 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
143 if (RoundParts < NumParts) {
144 // Assemble the trailing non-power-of-2 part.
145 unsigned OddParts = NumParts - RoundParts;
146 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
147 Hi = getCopyFromParts(DAG, DL,
148 Parts + RoundParts, OddParts, PartVT, OddVT);
150 // Combine the round and odd parts.
152 if (TLI.isBigEndian())
154 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
155 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
156 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
157 DAG.getConstant(Lo.getValueType().getSizeInBits(),
158 TLI.getPointerTy()));
159 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
160 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
162 } else if (PartVT.isFloatingPoint()) {
163 // FP split into multiple FP parts (for ppcf128)
164 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
167 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]);
168 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]);
169 if (TLI.isBigEndian())
171 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
173 // FP split into integer parts (soft fp)
174 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
175 !PartVT.isVector() && "Unexpected split");
176 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
177 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
181 // There is now one part, held in Val. Correct it to match ValueVT.
182 PartVT = Val.getValueType();
184 if (PartVT == ValueVT)
187 if (PartVT.isInteger() && ValueVT.isInteger()) {
188 if (ValueVT.bitsLT(PartVT)) {
189 // For a truncate, see if we have any information to
190 // indicate whether the truncated bits will always be
191 // zero or sign-extension.
192 if (AssertOp != ISD::DELETED_NODE)
193 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
194 DAG.getValueType(ValueVT));
195 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
197 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
200 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
201 // FP_ROUND's are always exact here.
202 if (ValueVT.bitsLT(Val.getValueType()))
203 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
204 DAG.getIntPtrConstant(1));
206 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
209 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
210 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
212 llvm_unreachable("Unknown mismatch!");
216 /// getCopyFromParts - Create a value that contains the specified legal parts
217 /// combined into the value they represent. If the parts combine to a type
218 /// larger then ValueVT then AssertOp can be used to specify whether the extra
219 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
220 /// (ISD::AssertSext).
221 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
222 const SDValue *Parts, unsigned NumParts,
223 EVT PartVT, EVT ValueVT) {
224 assert(ValueVT.isVector() && "Not a vector value");
225 assert(NumParts > 0 && "No parts to assemble!");
226 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
227 SDValue Val = Parts[0];
229 // Handle a multi-element vector.
231 EVT IntermediateVT, RegisterVT;
232 unsigned NumIntermediates;
234 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
235 NumIntermediates, RegisterVT);
236 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
237 NumParts = NumRegs; // Silence a compiler warning.
238 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
239 assert(RegisterVT == Parts[0].getValueType() &&
240 "Part type doesn't match part!");
242 // Assemble the parts into intermediate operands.
243 SmallVector<SDValue, 8> Ops(NumIntermediates);
244 if (NumIntermediates == NumParts) {
245 // If the register was not expanded, truncate or copy the value,
247 for (unsigned i = 0; i != NumParts; ++i)
248 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
249 PartVT, IntermediateVT);
250 } else if (NumParts > 0) {
251 // If the intermediate type was expanded, build the intermediate
252 // operands from the parts.
253 assert(NumParts % NumIntermediates == 0 &&
254 "Must expand into a divisible number of parts!");
255 unsigned Factor = NumParts / NumIntermediates;
256 for (unsigned i = 0; i != NumIntermediates; ++i)
257 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
258 PartVT, IntermediateVT);
261 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
262 // intermediate operands.
263 Val = DAG.getNode(IntermediateVT.isVector() ?
264 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
265 ValueVT, &Ops[0], NumIntermediates);
268 // There is now one part, held in Val. Correct it to match ValueVT.
269 PartVT = Val.getValueType();
271 if (PartVT == ValueVT)
274 if (PartVT.isVector()) {
275 // If the element type of the source/dest vectors are the same, but the
276 // parts vector has more elements than the value vector, then we have a
277 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
279 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
280 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
281 "Cannot narrow, it would be a lossy transformation");
282 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
283 DAG.getIntPtrConstant(0));
286 // Vector/Vector bitcast.
287 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
290 assert(ValueVT.getVectorElementType() == PartVT &&
291 ValueVT.getVectorNumElements() == 1 &&
292 "Only trivial scalar-to-vector conversions should get here!");
293 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
299 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
300 SDValue Val, SDValue *Parts, unsigned NumParts,
303 /// getCopyToParts - Create a series of nodes that contain the specified value
304 /// split into legal parts. If the parts contain more bits than Val, then, for
305 /// integers, ExtendKind can be used to specify how to generate the extra bits.
306 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
307 SDValue Val, SDValue *Parts, unsigned NumParts,
309 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
310 EVT ValueVT = Val.getValueType();
312 // Handle the vector case separately.
313 if (ValueVT.isVector())
314 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
317 unsigned PartBits = PartVT.getSizeInBits();
318 unsigned OrigNumParts = NumParts;
319 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
324 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
325 if (PartVT == ValueVT) {
326 assert(NumParts == 1 && "No-op copy with multiple parts!");
331 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
332 // If the parts cover more bits than the value has, promote the value.
333 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
334 assert(NumParts == 1 && "Do not know what to promote to!");
335 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
337 assert(PartVT.isInteger() && ValueVT.isInteger() &&
338 "Unknown mismatch!");
339 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
340 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
342 } else if (PartBits == ValueVT.getSizeInBits()) {
343 // Different types of the same size.
344 assert(NumParts == 1 && PartVT != ValueVT);
345 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
346 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
347 // If the parts cover less bits than value has, truncate the value.
348 assert(PartVT.isInteger() && ValueVT.isInteger() &&
349 "Unknown mismatch!");
350 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
351 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
354 // The value may have changed - recompute ValueVT.
355 ValueVT = Val.getValueType();
356 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
357 "Failed to tile the value with PartVT!");
360 assert(PartVT == ValueVT && "Type conversion failed!");
365 // Expand the value into multiple parts.
366 if (NumParts & (NumParts - 1)) {
367 // The number of parts is not a power of 2. Split off and copy the tail.
368 assert(PartVT.isInteger() && ValueVT.isInteger() &&
369 "Do not know what to expand to!");
370 unsigned RoundParts = 1 << Log2_32(NumParts);
371 unsigned RoundBits = RoundParts * PartBits;
372 unsigned OddParts = NumParts - RoundParts;
373 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
374 DAG.getIntPtrConstant(RoundBits));
375 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
377 if (TLI.isBigEndian())
378 // The odd parts were reversed by getCopyToParts - unreverse them.
379 std::reverse(Parts + RoundParts, Parts + NumParts);
381 NumParts = RoundParts;
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
386 // The number of parts is a power of 2. Repeatedly bisect the value using
388 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL,
389 EVT::getIntegerVT(*DAG.getContext(),
390 ValueVT.getSizeInBits()),
393 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
394 for (unsigned i = 0; i < NumParts; i += StepSize) {
395 unsigned ThisBits = StepSize * PartBits / 2;
396 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
397 SDValue &Part0 = Parts[i];
398 SDValue &Part1 = Parts[i+StepSize/2];
400 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
401 ThisVT, Part0, DAG.getIntPtrConstant(1));
402 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
403 ThisVT, Part0, DAG.getIntPtrConstant(0));
405 if (ThisBits == PartBits && ThisVT != PartVT) {
406 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0);
407 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1);
412 if (TLI.isBigEndian())
413 std::reverse(Parts, Parts + OrigNumParts);
417 /// getCopyToPartsVector - Create a series of nodes that contain the specified
418 /// value split into legal parts.
419 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
420 SDValue Val, SDValue *Parts, unsigned NumParts,
422 EVT ValueVT = Val.getValueType();
423 assert(ValueVT.isVector() && "Not a vector");
424 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
427 if (PartVT == ValueVT) {
429 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
430 // Bitconvert vector->vector case.
431 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
432 } else if (PartVT.isVector() &&
433 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
434 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
435 EVT ElementVT = PartVT.getVectorElementType();
436 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
438 SmallVector<SDValue, 16> Ops;
439 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
440 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
441 ElementVT, Val, DAG.getIntPtrConstant(i)));
443 for (unsigned i = ValueVT.getVectorNumElements(),
444 e = PartVT.getVectorNumElements(); i != e; ++i)
445 Ops.push_back(DAG.getUNDEF(ElementVT));
447 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
449 // FIXME: Use CONCAT for 2x -> 4x.
451 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
452 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
454 // Vector -> scalar conversion.
455 assert(ValueVT.getVectorElementType() == PartVT &&
456 ValueVT.getVectorNumElements() == 1 &&
457 "Only trivial vector-to-scalar conversions should get here!");
458 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
459 PartVT, Val, DAG.getIntPtrConstant(0));
466 // Handle a multi-element vector.
467 EVT IntermediateVT, RegisterVT;
468 unsigned NumIntermediates;
469 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
471 NumIntermediates, RegisterVT);
472 unsigned NumElements = ValueVT.getVectorNumElements();
474 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
475 NumParts = NumRegs; // Silence a compiler warning.
476 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
478 // Split the vector into intermediate operands.
479 SmallVector<SDValue, 8> Ops(NumIntermediates);
480 for (unsigned i = 0; i != NumIntermediates; ++i) {
481 if (IntermediateVT.isVector())
482 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
484 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
486 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
487 IntermediateVT, Val, DAG.getIntPtrConstant(i));
490 // Split the intermediate operands into legal parts.
491 if (NumParts == NumIntermediates) {
492 // If the register was not expanded, promote or copy the value,
494 for (unsigned i = 0; i != NumParts; ++i)
495 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
496 } else if (NumParts > 0) {
497 // If the intermediate type was expanded, split each the value into
499 assert(NumParts % NumIntermediates == 0 &&
500 "Must expand into a divisible number of parts!");
501 unsigned Factor = NumParts / NumIntermediates;
502 for (unsigned i = 0; i != NumIntermediates; ++i)
503 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
511 /// RegsForValue - This struct represents the registers (physical or virtual)
512 /// that a particular set of values is assigned, and the type information
513 /// about the value. The most common situation is to represent one value at a
514 /// time, but struct or array values are handled element-wise as multiple
515 /// values. The splitting of aggregates is performed recursively, so that we
516 /// never have aggregate-typed registers. The values at this point do not
517 /// necessarily have legal types, so each value may require one or more
518 /// registers of some legal type.
520 struct RegsForValue {
521 /// ValueVTs - The value types of the values, which may not be legal, and
522 /// may need be promoted or synthesized from one or more registers.
524 SmallVector<EVT, 4> ValueVTs;
526 /// RegVTs - The value types of the registers. This is the same size as
527 /// ValueVTs and it records, for each value, what the type of the assigned
528 /// register or registers are. (Individual values are never synthesized
529 /// from more than one type of register.)
531 /// With virtual registers, the contents of RegVTs is redundant with TLI's
532 /// getRegisterType member function, however when with physical registers
533 /// it is necessary to have a separate record of the types.
535 SmallVector<EVT, 4> RegVTs;
537 /// Regs - This list holds the registers assigned to the values.
538 /// Each legal or promoted value requires one register, and each
539 /// expanded value requires multiple registers.
541 SmallVector<unsigned, 4> Regs;
545 RegsForValue(const SmallVector<unsigned, 4> ®s,
546 EVT regvt, EVT valuevt)
547 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
549 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
550 unsigned Reg, const Type *Ty) {
551 ComputeValueVTs(tli, Ty, ValueVTs);
553 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
554 EVT ValueVT = ValueVTs[Value];
555 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
556 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
557 for (unsigned i = 0; i != NumRegs; ++i)
558 Regs.push_back(Reg + i);
559 RegVTs.push_back(RegisterVT);
564 /// areValueTypesLegal - Return true if types of all the values are legal.
565 bool areValueTypesLegal(const TargetLowering &TLI) {
566 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
567 EVT RegisterVT = RegVTs[Value];
568 if (!TLI.isTypeLegal(RegisterVT))
574 /// append - Add the specified values to this one.
575 void append(const RegsForValue &RHS) {
576 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
577 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
578 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
581 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
582 /// this value and returns the result as a ValueVTs value. This uses
583 /// Chain/Flag as the input and updates them for the output Chain/Flag.
584 /// If the Flag pointer is NULL, no flag is used.
585 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
587 SDValue &Chain, SDValue *Flag) const;
589 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
590 /// specified value into the registers specified by this object. This uses
591 /// Chain/Flag as the input and updates them for the output Chain/Flag.
592 /// If the Flag pointer is NULL, no flag is used.
593 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
594 SDValue &Chain, SDValue *Flag) const;
596 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
597 /// operand list. This adds the code marker, matching input operand index
598 /// (if applicable), and includes the number of values added into it.
599 void AddInlineAsmOperands(unsigned Kind,
600 bool HasMatching, unsigned MatchingIdx,
602 std::vector<SDValue> &Ops) const;
606 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
607 /// this value and returns the result as a ValueVT value. This uses
608 /// Chain/Flag as the input and updates them for the output Chain/Flag.
609 /// If the Flag pointer is NULL, no flag is used.
610 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
611 FunctionLoweringInfo &FuncInfo,
613 SDValue &Chain, SDValue *Flag) const {
614 // A Value with type {} or [0 x %t] needs no registers.
615 if (ValueVTs.empty())
618 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
620 // Assemble the legal parts into the final values.
621 SmallVector<SDValue, 4> Values(ValueVTs.size());
622 SmallVector<SDValue, 8> Parts;
623 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 // Copy the legal parts from the registers.
625 EVT ValueVT = ValueVTs[Value];
626 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
627 EVT RegisterVT = RegVTs[Value];
629 Parts.resize(NumRegs);
630 for (unsigned i = 0; i != NumRegs; ++i) {
633 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
635 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
636 *Flag = P.getValue(2);
639 Chain = P.getValue(1);
641 // If the source register was virtual and if we know something about it,
642 // add an assert node.
643 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
644 RegisterVT.isInteger() && !RegisterVT.isVector()) {
645 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
646 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) {
647 const FunctionLoweringInfo::LiveOutInfo &LOI =
648 FuncInfo.LiveOutRegInfo[SlotNo];
650 unsigned RegSize = RegisterVT.getSizeInBits();
651 unsigned NumSignBits = LOI.NumSignBits;
652 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
654 // FIXME: We capture more information than the dag can represent. For
655 // now, just use the tightest assertzext/assertsext possible.
657 EVT FromVT(MVT::Other);
658 if (NumSignBits == RegSize)
659 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
660 else if (NumZeroBits >= RegSize-1)
661 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
662 else if (NumSignBits > RegSize-8)
663 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
664 else if (NumZeroBits >= RegSize-8)
665 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
666 else if (NumSignBits > RegSize-16)
667 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
668 else if (NumZeroBits >= RegSize-16)
669 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
670 else if (NumSignBits > RegSize-32)
671 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
672 else if (NumZeroBits >= RegSize-32)
673 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
675 if (FromVT != MVT::Other)
676 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
677 RegisterVT, P, DAG.getValueType(FromVT));
684 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
685 NumRegs, RegisterVT, ValueVT);
690 return DAG.getNode(ISD::MERGE_VALUES, dl,
691 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
692 &Values[0], ValueVTs.size());
695 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
696 /// specified value into the registers specified by this object. This uses
697 /// Chain/Flag as the input and updates them for the output Chain/Flag.
698 /// If the Flag pointer is NULL, no flag is used.
699 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
700 SDValue &Chain, SDValue *Flag) const {
701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
703 // Get the list of the values's legal parts.
704 unsigned NumRegs = Regs.size();
705 SmallVector<SDValue, 8> Parts(NumRegs);
706 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
707 EVT ValueVT = ValueVTs[Value];
708 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
709 EVT RegisterVT = RegVTs[Value];
711 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
712 &Parts[Part], NumParts, RegisterVT);
716 // Copy the parts into the registers.
717 SmallVector<SDValue, 8> Chains(NumRegs);
718 for (unsigned i = 0; i != NumRegs; ++i) {
721 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
723 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
724 *Flag = Part.getValue(1);
727 Chains[i] = Part.getValue(0);
730 if (NumRegs == 1 || Flag)
731 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
732 // flagged to it. That is the CopyToReg nodes and the user are considered
733 // a single scheduling unit. If we create a TokenFactor and return it as
734 // chain, then the TokenFactor is both a predecessor (operand) of the
735 // user as well as a successor (the TF operands are flagged to the user).
736 // c1, f1 = CopyToReg
737 // c2, f2 = CopyToReg
738 // c3 = TokenFactor c1, c2
741 Chain = Chains[NumRegs-1];
743 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
746 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
747 /// operand list. This adds the code marker and includes the number of
748 /// values added into it.
749 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
750 unsigned MatchingIdx,
752 std::vector<SDValue> &Ops) const {
753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
755 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
757 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
758 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
761 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
762 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
763 EVT RegisterVT = RegVTs[Value];
764 for (unsigned i = 0; i != NumRegs; ++i) {
765 assert(Reg < Regs.size() && "Mismatch in # registers expected");
766 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
771 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
774 TD = DAG.getTarget().getTargetData();
777 /// clear - Clear out the current SelectionDAG and the associated
778 /// state and prepare this SelectionDAGBuilder object to be used
779 /// for a new block. This doesn't clear out information about
780 /// additional blocks that are needed to complete switch lowering
781 /// or PHI node updating; that information is cleared out as it is
783 void SelectionDAGBuilder::clear() {
785 UnusedArgNodeMap.clear();
786 PendingLoads.clear();
787 PendingExports.clear();
788 DanglingDebugInfoMap.clear();
789 CurDebugLoc = DebugLoc();
793 /// getRoot - Return the current virtual root of the Selection DAG,
794 /// flushing any PendingLoad items. This must be done before emitting
795 /// a store or any other node that may need to be ordered after any
796 /// prior load instructions.
798 SDValue SelectionDAGBuilder::getRoot() {
799 if (PendingLoads.empty())
800 return DAG.getRoot();
802 if (PendingLoads.size() == 1) {
803 SDValue Root = PendingLoads[0];
805 PendingLoads.clear();
809 // Otherwise, we have to make a token factor node.
810 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
811 &PendingLoads[0], PendingLoads.size());
812 PendingLoads.clear();
817 /// getControlRoot - Similar to getRoot, but instead of flushing all the
818 /// PendingLoad items, flush all the PendingExports items. It is necessary
819 /// to do this before emitting a terminator instruction.
821 SDValue SelectionDAGBuilder::getControlRoot() {
822 SDValue Root = DAG.getRoot();
824 if (PendingExports.empty())
827 // Turn all of the CopyToReg chains into one factored node.
828 if (Root.getOpcode() != ISD::EntryToken) {
829 unsigned i = 0, e = PendingExports.size();
830 for (; i != e; ++i) {
831 assert(PendingExports[i].getNode()->getNumOperands() > 1);
832 if (PendingExports[i].getNode()->getOperand(0) == Root)
833 break; // Don't add the root if we already indirectly depend on it.
837 PendingExports.push_back(Root);
840 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
842 PendingExports.size());
843 PendingExports.clear();
848 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
849 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
850 DAG.AssignOrdering(Node, SDNodeOrder);
852 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
853 AssignOrderingToNode(Node->getOperand(I).getNode());
856 void SelectionDAGBuilder::visit(const Instruction &I) {
857 // Set up outgoing PHI node register values before emitting the terminator.
858 if (isa<TerminatorInst>(&I))
859 HandlePHINodesInSuccessorBlocks(I.getParent());
861 CurDebugLoc = I.getDebugLoc();
863 visit(I.getOpcode(), I);
865 if (!isa<TerminatorInst>(&I) && !HasTailCall)
866 CopyToExportRegsIfNeeded(&I);
868 CurDebugLoc = DebugLoc();
871 void SelectionDAGBuilder::visitPHI(const PHINode &) {
872 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
875 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
876 // Note: this doesn't use InstVisitor, because it has to work with
877 // ConstantExpr's in addition to instructions.
879 default: llvm_unreachable("Unknown instruction type encountered!");
880 // Build the switch statement using the Instruction.def file.
881 #define HANDLE_INST(NUM, OPCODE, CLASS) \
882 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
883 #include "llvm/Instruction.def"
886 // Assign the ordering to the freshly created DAG nodes.
887 if (NodeMap.count(&I)) {
889 AssignOrderingToNode(getValue(&I).getNode());
893 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
894 // generate the debug data structures now that we've seen its definition.
895 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
897 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
899 const DbgValueInst *DI = DDI.getDI();
900 DebugLoc dl = DDI.getdl();
901 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
902 MDNode *Variable = DI->getVariable();
903 uint64_t Offset = DI->getOffset();
906 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
907 SDV = DAG.getDbgValue(Variable, Val.getNode(),
908 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
909 DAG.AddDbgValue(SDV, Val.getNode(), false);
912 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
913 Offset, dl, SDNodeOrder);
914 DAG.AddDbgValue(SDV, 0, false);
916 DanglingDebugInfoMap[V] = DanglingDebugInfo();
920 // getValue - Return an SDValue for the given Value.
921 SDValue SelectionDAGBuilder::getValue(const Value *V) {
922 // If we already have an SDValue for this value, use it. It's important
923 // to do this first, so that we don't create a CopyFromReg if we already
924 // have a regular SDValue.
925 SDValue &N = NodeMap[V];
926 if (N.getNode()) return N;
928 // If there's a virtual register allocated and initialized for this
930 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
931 if (It != FuncInfo.ValueMap.end()) {
932 unsigned InReg = It->second;
933 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
934 SDValue Chain = DAG.getEntryNode();
935 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
938 // Otherwise create a new SDValue and remember it.
939 SDValue Val = getValueImpl(V);
941 resolveDanglingDebugInfo(V, Val);
945 /// getNonRegisterValue - Return an SDValue for the given Value, but
946 /// don't look in FuncInfo.ValueMap for a virtual register.
947 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
948 // If we already have an SDValue for this value, use it.
949 SDValue &N = NodeMap[V];
950 if (N.getNode()) return N;
952 // Otherwise create a new SDValue and remember it.
953 SDValue Val = getValueImpl(V);
955 resolveDanglingDebugInfo(V, Val);
959 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
960 /// Create an SDValue for the given value.
961 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
962 if (const Constant *C = dyn_cast<Constant>(V)) {
963 EVT VT = TLI.getValueType(V->getType(), true);
965 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
966 return DAG.getConstant(*CI, VT);
968 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
969 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
971 if (isa<ConstantPointerNull>(C))
972 return DAG.getConstant(0, TLI.getPointerTy());
974 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
975 return DAG.getConstantFP(*CFP, VT);
977 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
978 return DAG.getUNDEF(VT);
980 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
981 visit(CE->getOpcode(), *CE);
982 SDValue N1 = NodeMap[V];
983 assert(N1.getNode() && "visit didn't populate the NodeMap!");
987 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
988 SmallVector<SDValue, 4> Constants;
989 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
991 SDNode *Val = getValue(*OI).getNode();
992 // If the operand is an empty aggregate, there are no values.
994 // Add each leaf value from the operand to the Constants list
995 // to form a flattened list of all the values.
996 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
997 Constants.push_back(SDValue(Val, i));
1000 return DAG.getMergeValues(&Constants[0], Constants.size(),
1004 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1005 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1006 "Unknown struct or array constant!");
1008 SmallVector<EVT, 4> ValueVTs;
1009 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1010 unsigned NumElts = ValueVTs.size();
1012 return SDValue(); // empty struct
1013 SmallVector<SDValue, 4> Constants(NumElts);
1014 for (unsigned i = 0; i != NumElts; ++i) {
1015 EVT EltVT = ValueVTs[i];
1016 if (isa<UndefValue>(C))
1017 Constants[i] = DAG.getUNDEF(EltVT);
1018 else if (EltVT.isFloatingPoint())
1019 Constants[i] = DAG.getConstantFP(0, EltVT);
1021 Constants[i] = DAG.getConstant(0, EltVT);
1024 return DAG.getMergeValues(&Constants[0], NumElts,
1028 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1029 return DAG.getBlockAddress(BA, VT);
1031 const VectorType *VecTy = cast<VectorType>(V->getType());
1032 unsigned NumElements = VecTy->getNumElements();
1034 // Now that we know the number and type of the elements, get that number of
1035 // elements into the Ops array based on what kind of constant it is.
1036 SmallVector<SDValue, 16> Ops;
1037 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1038 for (unsigned i = 0; i != NumElements; ++i)
1039 Ops.push_back(getValue(CP->getOperand(i)));
1041 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1042 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1045 if (EltVT.isFloatingPoint())
1046 Op = DAG.getConstantFP(0, EltVT);
1048 Op = DAG.getConstant(0, EltVT);
1049 Ops.assign(NumElements, Op);
1052 // Create a BUILD_VECTOR node.
1053 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1054 VT, &Ops[0], Ops.size());
1057 // If this is a static alloca, generate it as the frameindex instead of
1059 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1060 DenseMap<const AllocaInst*, int>::iterator SI =
1061 FuncInfo.StaticAllocaMap.find(AI);
1062 if (SI != FuncInfo.StaticAllocaMap.end())
1063 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1066 // If this is an instruction which fast-isel has deferred, select it now.
1067 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1068 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1069 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1070 SDValue Chain = DAG.getEntryNode();
1071 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1074 llvm_unreachable("Can't get register for value!");
1078 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1079 SDValue Chain = getControlRoot();
1080 SmallVector<ISD::OutputArg, 8> Outs;
1081 SmallVector<SDValue, 8> OutVals;
1083 if (!FuncInfo.CanLowerReturn) {
1084 unsigned DemoteReg = FuncInfo.DemoteRegister;
1085 const Function *F = I.getParent()->getParent();
1087 // Emit a store of the return value through the virtual register.
1088 // Leave Outs empty so that LowerReturn won't try to load return
1089 // registers the usual way.
1090 SmallVector<EVT, 1> PtrValueVTs;
1091 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1094 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1095 SDValue RetOp = getValue(I.getOperand(0));
1097 SmallVector<EVT, 4> ValueVTs;
1098 SmallVector<uint64_t, 4> Offsets;
1099 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1100 unsigned NumValues = ValueVTs.size();
1102 SmallVector<SDValue, 4> Chains(NumValues);
1103 for (unsigned i = 0; i != NumValues; ++i) {
1104 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1105 RetPtr.getValueType(), RetPtr,
1106 DAG.getIntPtrConstant(Offsets[i]));
1108 DAG.getStore(Chain, getCurDebugLoc(),
1109 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1110 // FIXME: better loc info would be nice.
1111 Add, MachinePointerInfo(), false, false, 0);
1114 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1115 MVT::Other, &Chains[0], NumValues);
1116 } else if (I.getNumOperands() != 0) {
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1119 unsigned NumValues = ValueVTs.size();
1121 SDValue RetOp = getValue(I.getOperand(0));
1122 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1123 EVT VT = ValueVTs[j];
1125 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1127 const Function *F = I.getParent()->getParent();
1128 if (F->paramHasAttr(0, Attribute::SExt))
1129 ExtendKind = ISD::SIGN_EXTEND;
1130 else if (F->paramHasAttr(0, Attribute::ZExt))
1131 ExtendKind = ISD::ZERO_EXTEND;
1133 // FIXME: C calling convention requires the return type to be promoted
1134 // to at least 32-bit. But this is not necessary for non-C calling
1135 // conventions. The frontend should mark functions whose return values
1136 // require promoting with signext or zeroext attributes.
1137 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1138 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1139 if (VT.bitsLT(MinVT))
1143 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1144 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1145 SmallVector<SDValue, 4> Parts(NumParts);
1146 getCopyToParts(DAG, getCurDebugLoc(),
1147 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1148 &Parts[0], NumParts, PartVT, ExtendKind);
1150 // 'inreg' on function refers to return value
1151 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1152 if (F->paramHasAttr(0, Attribute::InReg))
1155 // Propagate extension type if any
1156 if (F->paramHasAttr(0, Attribute::SExt))
1158 else if (F->paramHasAttr(0, Attribute::ZExt))
1161 for (unsigned i = 0; i < NumParts; ++i) {
1162 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1164 OutVals.push_back(Parts[i]);
1170 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1171 CallingConv::ID CallConv =
1172 DAG.getMachineFunction().getFunction()->getCallingConv();
1173 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1174 Outs, OutVals, getCurDebugLoc(), DAG);
1176 // Verify that the target's LowerReturn behaved as expected.
1177 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1178 "LowerReturn didn't return a valid chain!");
1180 // Update the DAG with the new chain value resulting from return lowering.
1184 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1185 /// created for it, emit nodes to copy the value into the virtual
1187 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1188 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1189 if (VMI != FuncInfo.ValueMap.end()) {
1190 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1191 CopyValueToVirtualRegister(V, VMI->second);
1195 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1196 /// the current basic block, add it to ValueMap now so that we'll get a
1198 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1199 // No need to export constants.
1200 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1202 // Already exported?
1203 if (FuncInfo.isExportedInst(V)) return;
1205 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1206 CopyValueToVirtualRegister(V, Reg);
1209 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1210 const BasicBlock *FromBB) {
1211 // The operands of the setcc have to be in this block. We don't know
1212 // how to export them from some other block.
1213 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1214 // Can export from current BB.
1215 if (VI->getParent() == FromBB)
1218 // Is already exported, noop.
1219 return FuncInfo.isExportedInst(V);
1222 // If this is an argument, we can export it if the BB is the entry block or
1223 // if it is already exported.
1224 if (isa<Argument>(V)) {
1225 if (FromBB == &FromBB->getParent()->getEntryBlock())
1228 // Otherwise, can only export this if it is already exported.
1229 return FuncInfo.isExportedInst(V);
1232 // Otherwise, constants can always be exported.
1236 static bool InBlock(const Value *V, const BasicBlock *BB) {
1237 if (const Instruction *I = dyn_cast<Instruction>(V))
1238 return I->getParent() == BB;
1242 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1243 /// This function emits a branch and is used at the leaves of an OR or an
1244 /// AND operator tree.
1247 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1248 MachineBasicBlock *TBB,
1249 MachineBasicBlock *FBB,
1250 MachineBasicBlock *CurBB,
1251 MachineBasicBlock *SwitchBB) {
1252 const BasicBlock *BB = CurBB->getBasicBlock();
1254 // If the leaf of the tree is a comparison, merge the condition into
1256 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1257 // The operands of the cmp have to be in this block. We don't know
1258 // how to export them from some other block. If this is the first block
1259 // of the sequence, no exporting is needed.
1260 if (CurBB == SwitchBB ||
1261 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1262 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1263 ISD::CondCode Condition;
1264 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1265 Condition = getICmpCondCode(IC->getPredicate());
1266 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1267 Condition = getFCmpCondCode(FC->getPredicate());
1269 Condition = ISD::SETEQ; // silence warning.
1270 llvm_unreachable("Unknown compare instruction");
1273 CaseBlock CB(Condition, BOp->getOperand(0),
1274 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1275 SwitchCases.push_back(CB);
1280 // Create a CaseBlock record representing this branch.
1281 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1282 NULL, TBB, FBB, CurBB);
1283 SwitchCases.push_back(CB);
1286 /// FindMergedConditions - If Cond is an expression like
1287 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1288 MachineBasicBlock *TBB,
1289 MachineBasicBlock *FBB,
1290 MachineBasicBlock *CurBB,
1291 MachineBasicBlock *SwitchBB,
1293 // If this node is not part of the or/and tree, emit it as a branch.
1294 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1295 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1296 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1297 BOp->getParent() != CurBB->getBasicBlock() ||
1298 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1299 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1300 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1304 // Create TmpBB after CurBB.
1305 MachineFunction::iterator BBI = CurBB;
1306 MachineFunction &MF = DAG.getMachineFunction();
1307 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1308 CurBB->getParent()->insert(++BBI, TmpBB);
1310 if (Opc == Instruction::Or) {
1311 // Codegen X | Y as:
1319 // Emit the LHS condition.
1320 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1322 // Emit the RHS condition into TmpBB.
1323 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1325 assert(Opc == Instruction::And && "Unknown merge op!");
1326 // Codegen X & Y as:
1333 // This requires creation of TmpBB after CurBB.
1335 // Emit the LHS condition.
1336 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1338 // Emit the RHS condition into TmpBB.
1339 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1343 /// If the set of cases should be emitted as a series of branches, return true.
1344 /// If we should emit this as a bunch of and/or'd together conditions, return
1347 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1348 if (Cases.size() != 2) return true;
1350 // If this is two comparisons of the same values or'd or and'd together, they
1351 // will get folded into a single comparison, so don't emit two blocks.
1352 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1353 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1354 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1355 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1359 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1360 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1361 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1362 Cases[0].CC == Cases[1].CC &&
1363 isa<Constant>(Cases[0].CmpRHS) &&
1364 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1365 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1367 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1374 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1375 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1377 // Update machine-CFG edges.
1378 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1380 // Figure out which block is immediately after the current one.
1381 MachineBasicBlock *NextBlock = 0;
1382 MachineFunction::iterator BBI = BrMBB;
1383 if (++BBI != FuncInfo.MF->end())
1386 if (I.isUnconditional()) {
1387 // Update machine-CFG edges.
1388 BrMBB->addSuccessor(Succ0MBB);
1390 // If this is not a fall-through branch, emit the branch.
1391 if (Succ0MBB != NextBlock)
1392 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1393 MVT::Other, getControlRoot(),
1394 DAG.getBasicBlock(Succ0MBB)));
1399 // If this condition is one of the special cases we handle, do special stuff
1401 const Value *CondVal = I.getCondition();
1402 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1404 // If this is a series of conditions that are or'd or and'd together, emit
1405 // this as a sequence of branches instead of setcc's with and/or operations.
1406 // For example, instead of something like:
1419 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1420 if (BOp->hasOneUse() &&
1421 (BOp->getOpcode() == Instruction::And ||
1422 BOp->getOpcode() == Instruction::Or)) {
1423 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1425 // If the compares in later blocks need to use values not currently
1426 // exported from this block, export them now. This block should always
1427 // be the first entry.
1428 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1430 // Allow some cases to be rejected.
1431 if (ShouldEmitAsBranches(SwitchCases)) {
1432 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1433 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1434 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1437 // Emit the branch for this block.
1438 visitSwitchCase(SwitchCases[0], BrMBB);
1439 SwitchCases.erase(SwitchCases.begin());
1443 // Okay, we decided not to do this, remove any inserted MBB's and clear
1445 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1446 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1448 SwitchCases.clear();
1452 // Create a CaseBlock record representing this branch.
1453 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1454 NULL, Succ0MBB, Succ1MBB, BrMBB);
1456 // Use visitSwitchCase to actually insert the fast branch sequence for this
1458 visitSwitchCase(CB, BrMBB);
1461 /// visitSwitchCase - Emits the necessary code to represent a single node in
1462 /// the binary search tree resulting from lowering a switch instruction.
1463 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1464 MachineBasicBlock *SwitchBB) {
1466 SDValue CondLHS = getValue(CB.CmpLHS);
1467 DebugLoc dl = getCurDebugLoc();
1469 // Build the setcc now.
1470 if (CB.CmpMHS == NULL) {
1471 // Fold "(X == true)" to X and "(X == false)" to !X to
1472 // handle common cases produced by branch lowering.
1473 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1474 CB.CC == ISD::SETEQ)
1476 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1477 CB.CC == ISD::SETEQ) {
1478 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1479 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1481 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1483 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1485 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1486 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1488 SDValue CmpOp = getValue(CB.CmpMHS);
1489 EVT VT = CmpOp.getValueType();
1491 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1492 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1495 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1496 VT, CmpOp, DAG.getConstant(Low, VT));
1497 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1498 DAG.getConstant(High-Low, VT), ISD::SETULE);
1502 // Update successor info
1503 SwitchBB->addSuccessor(CB.TrueBB);
1504 SwitchBB->addSuccessor(CB.FalseBB);
1506 // Set NextBlock to be the MBB immediately after the current one, if any.
1507 // This is used to avoid emitting unnecessary branches to the next block.
1508 MachineBasicBlock *NextBlock = 0;
1509 MachineFunction::iterator BBI = SwitchBB;
1510 if (++BBI != FuncInfo.MF->end())
1513 // If the lhs block is the next block, invert the condition so that we can
1514 // fall through to the lhs instead of the rhs block.
1515 if (CB.TrueBB == NextBlock) {
1516 std::swap(CB.TrueBB, CB.FalseBB);
1517 SDValue True = DAG.getConstant(1, Cond.getValueType());
1518 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1521 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1522 MVT::Other, getControlRoot(), Cond,
1523 DAG.getBasicBlock(CB.TrueBB));
1525 // Insert the false branch. Do this even if it's a fall through branch,
1526 // this makes it easier to do DAG optimizations which require inverting
1527 // the branch condition.
1528 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1529 DAG.getBasicBlock(CB.FalseBB));
1531 DAG.setRoot(BrCond);
1534 /// visitJumpTable - Emit JumpTable node in the current MBB
1535 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1536 // Emit the code for the jump table
1537 assert(JT.Reg != -1U && "Should lower JT Header first!");
1538 EVT PTy = TLI.getPointerTy();
1539 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1541 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1542 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1543 MVT::Other, Index.getValue(1),
1545 DAG.setRoot(BrJumpTable);
1548 /// visitJumpTableHeader - This function emits necessary code to produce index
1549 /// in the JumpTable from switch case.
1550 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1551 JumpTableHeader &JTH,
1552 MachineBasicBlock *SwitchBB) {
1553 // Subtract the lowest switch case value from the value being switched on and
1554 // conditional branch to default mbb if the result is greater than the
1555 // difference between smallest and largest cases.
1556 SDValue SwitchOp = getValue(JTH.SValue);
1557 EVT VT = SwitchOp.getValueType();
1558 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1559 DAG.getConstant(JTH.First, VT));
1561 // The SDNode we just created, which holds the value being switched on minus
1562 // the smallest case value, needs to be copied to a virtual register so it
1563 // can be used as an index into the jump table in a subsequent basic block.
1564 // This value may be smaller or larger than the target's pointer type, and
1565 // therefore require extension or truncating.
1566 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1568 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1569 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1570 JumpTableReg, SwitchOp);
1571 JT.Reg = JumpTableReg;
1573 // Emit the range check for the jump table, and branch to the default block
1574 // for the switch statement if the value being switched on exceeds the largest
1575 // case in the switch.
1576 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1577 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1578 DAG.getConstant(JTH.Last-JTH.First,VT),
1581 // Set NextBlock to be the MBB immediately after the current one, if any.
1582 // This is used to avoid emitting unnecessary branches to the next block.
1583 MachineBasicBlock *NextBlock = 0;
1584 MachineFunction::iterator BBI = SwitchBB;
1586 if (++BBI != FuncInfo.MF->end())
1589 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1590 MVT::Other, CopyTo, CMP,
1591 DAG.getBasicBlock(JT.Default));
1593 if (JT.MBB != NextBlock)
1594 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1595 DAG.getBasicBlock(JT.MBB));
1597 DAG.setRoot(BrCond);
1600 /// visitBitTestHeader - This function emits necessary code to produce value
1601 /// suitable for "bit tests"
1602 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1603 MachineBasicBlock *SwitchBB) {
1604 // Subtract the minimum value
1605 SDValue SwitchOp = getValue(B.SValue);
1606 EVT VT = SwitchOp.getValueType();
1607 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1608 DAG.getConstant(B.First, VT));
1611 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1612 TLI.getSetCCResultType(Sub.getValueType()),
1613 Sub, DAG.getConstant(B.Range, VT),
1616 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1617 TLI.getPointerTy());
1619 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy());
1620 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1623 // Set NextBlock to be the MBB immediately after the current one, if any.
1624 // This is used to avoid emitting unnecessary branches to the next block.
1625 MachineBasicBlock *NextBlock = 0;
1626 MachineFunction::iterator BBI = SwitchBB;
1627 if (++BBI != FuncInfo.MF->end())
1630 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1632 SwitchBB->addSuccessor(B.Default);
1633 SwitchBB->addSuccessor(MBB);
1635 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1636 MVT::Other, CopyTo, RangeCmp,
1637 DAG.getBasicBlock(B.Default));
1639 if (MBB != NextBlock)
1640 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1641 DAG.getBasicBlock(MBB));
1643 DAG.setRoot(BrRange);
1646 /// visitBitTestCase - this function produces one "bit test"
1647 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1650 MachineBasicBlock *SwitchBB) {
1651 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1652 TLI.getPointerTy());
1654 if (CountPopulation_64(B.Mask) == 1) {
1655 // Testing for a single bit; just compare the shift count with what it
1656 // would need to be to shift a 1 bit in that position.
1657 Cmp = DAG.getSetCC(getCurDebugLoc(),
1658 TLI.getSetCCResultType(ShiftOp.getValueType()),
1660 DAG.getConstant(CountTrailingZeros_64(B.Mask),
1661 TLI.getPointerTy()),
1664 // Make desired shift
1665 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1667 DAG.getConstant(1, TLI.getPointerTy()),
1670 // Emit bit tests and jumps
1671 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1672 TLI.getPointerTy(), SwitchVal,
1673 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1674 Cmp = DAG.getSetCC(getCurDebugLoc(),
1675 TLI.getSetCCResultType(AndOp.getValueType()),
1676 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1680 SwitchBB->addSuccessor(B.TargetBB);
1681 SwitchBB->addSuccessor(NextMBB);
1683 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1684 MVT::Other, getControlRoot(),
1685 Cmp, DAG.getBasicBlock(B.TargetBB));
1687 // Set NextBlock to be the MBB immediately after the current one, if any.
1688 // This is used to avoid emitting unnecessary branches to the next block.
1689 MachineBasicBlock *NextBlock = 0;
1690 MachineFunction::iterator BBI = SwitchBB;
1691 if (++BBI != FuncInfo.MF->end())
1694 if (NextMBB != NextBlock)
1695 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1696 DAG.getBasicBlock(NextMBB));
1701 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1702 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1704 // Retrieve successors.
1705 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1706 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1708 const Value *Callee(I.getCalledValue());
1709 if (isa<InlineAsm>(Callee))
1712 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1714 // If the value of the invoke is used outside of its defining block, make it
1715 // available as a virtual register.
1716 CopyToExportRegsIfNeeded(&I);
1718 // Update successor info
1719 InvokeMBB->addSuccessor(Return);
1720 InvokeMBB->addSuccessor(LandingPad);
1722 // Drop into normal successor.
1723 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1724 MVT::Other, getControlRoot(),
1725 DAG.getBasicBlock(Return)));
1728 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1731 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1732 /// small case ranges).
1733 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1734 CaseRecVector& WorkList,
1736 MachineBasicBlock *Default,
1737 MachineBasicBlock *SwitchBB) {
1738 Case& BackCase = *(CR.Range.second-1);
1740 // Size is the number of Cases represented by this range.
1741 size_t Size = CR.Range.second - CR.Range.first;
1745 // Get the MachineFunction which holds the current MBB. This is used when
1746 // inserting any additional MBBs necessary to represent the switch.
1747 MachineFunction *CurMF = FuncInfo.MF;
1749 // Figure out which block is immediately after the current one.
1750 MachineBasicBlock *NextBlock = 0;
1751 MachineFunction::iterator BBI = CR.CaseBB;
1753 if (++BBI != FuncInfo.MF->end())
1756 // TODO: If any two of the cases has the same destination, and if one value
1757 // is the same as the other, but has one bit unset that the other has set,
1758 // use bit manipulation to do two compares at once. For example:
1759 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1761 // Rearrange the case blocks so that the last one falls through if possible.
1762 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1763 // The last case block won't fall through into 'NextBlock' if we emit the
1764 // branches in this order. See if rearranging a case value would help.
1765 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1766 if (I->BB == NextBlock) {
1767 std::swap(*I, BackCase);
1773 // Create a CaseBlock record representing a conditional branch to
1774 // the Case's target mbb if the value being switched on SV is equal
1776 MachineBasicBlock *CurBlock = CR.CaseBB;
1777 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1778 MachineBasicBlock *FallThrough;
1780 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1781 CurMF->insert(BBI, FallThrough);
1783 // Put SV in a virtual register to make it available from the new blocks.
1784 ExportFromCurrentBlock(SV);
1786 // If the last case doesn't match, go to the default block.
1787 FallThrough = Default;
1790 const Value *RHS, *LHS, *MHS;
1792 if (I->High == I->Low) {
1793 // This is just small small case range :) containing exactly 1 case
1795 LHS = SV; RHS = I->High; MHS = NULL;
1798 LHS = I->Low; MHS = SV; RHS = I->High;
1800 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1802 // If emitting the first comparison, just call visitSwitchCase to emit the
1803 // code into the current block. Otherwise, push the CaseBlock onto the
1804 // vector to be later processed by SDISel, and insert the node's MBB
1805 // before the next MBB.
1806 if (CurBlock == SwitchBB)
1807 visitSwitchCase(CB, SwitchBB);
1809 SwitchCases.push_back(CB);
1811 CurBlock = FallThrough;
1817 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1818 return !DisableJumpTables &&
1819 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1820 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1823 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1824 APInt LastExt(Last), FirstExt(First);
1825 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1826 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1827 return (LastExt - FirstExt + 1ULL);
1830 /// handleJTSwitchCase - Emit jumptable for current switch case range
1831 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1832 CaseRecVector& WorkList,
1834 MachineBasicBlock* Default,
1835 MachineBasicBlock *SwitchBB) {
1836 Case& FrontCase = *CR.Range.first;
1837 Case& BackCase = *(CR.Range.second-1);
1839 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1840 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1842 APInt TSize(First.getBitWidth(), 0);
1843 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1847 if (!areJTsAllowed(TLI) || TSize.ult(4))
1850 APInt Range = ComputeRange(First, Last);
1851 double Density = TSize.roundToDouble() / Range.roundToDouble();
1855 DEBUG(dbgs() << "Lowering jump table\n"
1856 << "First entry: " << First << ". Last entry: " << Last << '\n'
1857 << "Range: " << Range
1858 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1860 // Get the MachineFunction which holds the current MBB. This is used when
1861 // inserting any additional MBBs necessary to represent the switch.
1862 MachineFunction *CurMF = FuncInfo.MF;
1864 // Figure out which block is immediately after the current one.
1865 MachineFunction::iterator BBI = CR.CaseBB;
1868 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1870 // Create a new basic block to hold the code for loading the address
1871 // of the jump table, and jumping to it. Update successor information;
1872 // we will either branch to the default case for the switch, or the jump
1874 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1875 CurMF->insert(BBI, JumpTableBB);
1876 CR.CaseBB->addSuccessor(Default);
1877 CR.CaseBB->addSuccessor(JumpTableBB);
1879 // Build a vector of destination BBs, corresponding to each target
1880 // of the jump table. If the value of the jump table slot corresponds to
1881 // a case statement, push the case's BB onto the vector, otherwise, push
1883 std::vector<MachineBasicBlock*> DestBBs;
1885 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1886 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1887 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1889 if (Low.sle(TEI) && TEI.sle(High)) {
1890 DestBBs.push_back(I->BB);
1894 DestBBs.push_back(Default);
1898 // Update successor info. Add one edge to each unique successor.
1899 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1900 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1901 E = DestBBs.end(); I != E; ++I) {
1902 if (!SuccsHandled[(*I)->getNumber()]) {
1903 SuccsHandled[(*I)->getNumber()] = true;
1904 JumpTableBB->addSuccessor(*I);
1908 // Create a jump table index for this jump table.
1909 unsigned JTEncoding = TLI.getJumpTableEncoding();
1910 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1911 ->createJumpTableIndex(DestBBs);
1913 // Set the jump table information so that we can codegen it as a second
1914 // MachineBasicBlock
1915 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1916 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1917 if (CR.CaseBB == SwitchBB)
1918 visitJumpTableHeader(JT, JTH, SwitchBB);
1920 JTCases.push_back(JumpTableBlock(JTH, JT));
1925 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1927 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1928 CaseRecVector& WorkList,
1930 MachineBasicBlock *Default,
1931 MachineBasicBlock *SwitchBB) {
1932 // Get the MachineFunction which holds the current MBB. This is used when
1933 // inserting any additional MBBs necessary to represent the switch.
1934 MachineFunction *CurMF = FuncInfo.MF;
1936 // Figure out which block is immediately after the current one.
1937 MachineFunction::iterator BBI = CR.CaseBB;
1940 Case& FrontCase = *CR.Range.first;
1941 Case& BackCase = *(CR.Range.second-1);
1942 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1944 // Size is the number of Cases represented by this range.
1945 unsigned Size = CR.Range.second - CR.Range.first;
1947 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1948 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1950 CaseItr Pivot = CR.Range.first + Size/2;
1952 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1953 // (heuristically) allow us to emit JumpTable's later.
1954 APInt TSize(First.getBitWidth(), 0);
1955 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1959 APInt LSize = FrontCase.size();
1960 APInt RSize = TSize-LSize;
1961 DEBUG(dbgs() << "Selecting best pivot: \n"
1962 << "First: " << First << ", Last: " << Last <<'\n'
1963 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1964 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1966 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1967 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1968 APInt Range = ComputeRange(LEnd, RBegin);
1969 assert((Range - 2ULL).isNonNegative() &&
1970 "Invalid case distance");
1971 double LDensity = (double)LSize.roundToDouble() /
1972 (LEnd - First + 1ULL).roundToDouble();
1973 double RDensity = (double)RSize.roundToDouble() /
1974 (Last - RBegin + 1ULL).roundToDouble();
1975 double Metric = Range.logBase2()*(LDensity+RDensity);
1976 // Should always split in some non-trivial place
1977 DEBUG(dbgs() <<"=>Step\n"
1978 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1979 << "LDensity: " << LDensity
1980 << ", RDensity: " << RDensity << '\n'
1981 << "Metric: " << Metric << '\n');
1982 if (FMetric < Metric) {
1985 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1991 if (areJTsAllowed(TLI)) {
1992 // If our case is dense we *really* should handle it earlier!
1993 assert((FMetric > 0) && "Should handle dense range earlier!");
1995 Pivot = CR.Range.first + Size/2;
1998 CaseRange LHSR(CR.Range.first, Pivot);
1999 CaseRange RHSR(Pivot, CR.Range.second);
2000 Constant *C = Pivot->Low;
2001 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2003 // We know that we branch to the LHS if the Value being switched on is
2004 // less than the Pivot value, C. We use this to optimize our binary
2005 // tree a bit, by recognizing that if SV is greater than or equal to the
2006 // LHS's Case Value, and that Case Value is exactly one less than the
2007 // Pivot's Value, then we can branch directly to the LHS's Target,
2008 // rather than creating a leaf node for it.
2009 if ((LHSR.second - LHSR.first) == 1 &&
2010 LHSR.first->High == CR.GE &&
2011 cast<ConstantInt>(C)->getValue() ==
2012 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2013 TrueBB = LHSR.first->BB;
2015 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2016 CurMF->insert(BBI, TrueBB);
2017 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2019 // Put SV in a virtual register to make it available from the new blocks.
2020 ExportFromCurrentBlock(SV);
2023 // Similar to the optimization above, if the Value being switched on is
2024 // known to be less than the Constant CR.LT, and the current Case Value
2025 // is CR.LT - 1, then we can branch directly to the target block for
2026 // the current Case Value, rather than emitting a RHS leaf node for it.
2027 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2028 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2029 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2030 FalseBB = RHSR.first->BB;
2032 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2033 CurMF->insert(BBI, FalseBB);
2034 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2036 // Put SV in a virtual register to make it available from the new blocks.
2037 ExportFromCurrentBlock(SV);
2040 // Create a CaseBlock record representing a conditional branch to
2041 // the LHS node if the value being switched on SV is less than C.
2042 // Otherwise, branch to LHS.
2043 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2045 if (CR.CaseBB == SwitchBB)
2046 visitSwitchCase(CB, SwitchBB);
2048 SwitchCases.push_back(CB);
2053 /// handleBitTestsSwitchCase - if current case range has few destination and
2054 /// range span less, than machine word bitwidth, encode case range into series
2055 /// of masks and emit bit tests with these masks.
2056 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2057 CaseRecVector& WorkList,
2059 MachineBasicBlock* Default,
2060 MachineBasicBlock *SwitchBB){
2061 EVT PTy = TLI.getPointerTy();
2062 unsigned IntPtrBits = PTy.getSizeInBits();
2064 Case& FrontCase = *CR.Range.first;
2065 Case& BackCase = *(CR.Range.second-1);
2067 // Get the MachineFunction which holds the current MBB. This is used when
2068 // inserting any additional MBBs necessary to represent the switch.
2069 MachineFunction *CurMF = FuncInfo.MF;
2071 // If target does not have legal shift left, do not emit bit tests at all.
2072 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2076 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2078 // Single case counts one, case range - two.
2079 numCmps += (I->Low == I->High ? 1 : 2);
2082 // Count unique destinations
2083 SmallSet<MachineBasicBlock*, 4> Dests;
2084 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2085 Dests.insert(I->BB);
2086 if (Dests.size() > 3)
2087 // Don't bother the code below, if there are too much unique destinations
2090 DEBUG(dbgs() << "Total number of unique destinations: "
2091 << Dests.size() << '\n'
2092 << "Total number of comparisons: " << numCmps << '\n');
2094 // Compute span of values.
2095 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2096 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2097 APInt cmpRange = maxValue - minValue;
2099 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2100 << "Low bound: " << minValue << '\n'
2101 << "High bound: " << maxValue << '\n');
2103 if (cmpRange.uge(IntPtrBits) ||
2104 (!(Dests.size() == 1 && numCmps >= 3) &&
2105 !(Dests.size() == 2 && numCmps >= 5) &&
2106 !(Dests.size() >= 3 && numCmps >= 6)))
2109 DEBUG(dbgs() << "Emitting bit tests\n");
2110 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2112 // Optimize the case where all the case values fit in a
2113 // word without having to subtract minValue. In this case,
2114 // we can optimize away the subtraction.
2115 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2116 cmpRange = maxValue;
2118 lowBound = minValue;
2121 CaseBitsVector CasesBits;
2122 unsigned i, count = 0;
2124 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2125 MachineBasicBlock* Dest = I->BB;
2126 for (i = 0; i < count; ++i)
2127 if (Dest == CasesBits[i].BB)
2131 assert((count < 3) && "Too much destinations to test!");
2132 CasesBits.push_back(CaseBits(0, Dest, 0));
2136 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2137 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2139 uint64_t lo = (lowValue - lowBound).getZExtValue();
2140 uint64_t hi = (highValue - lowBound).getZExtValue();
2142 for (uint64_t j = lo; j <= hi; j++) {
2143 CasesBits[i].Mask |= 1ULL << j;
2144 CasesBits[i].Bits++;
2148 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2152 // Figure out which block is immediately after the current one.
2153 MachineFunction::iterator BBI = CR.CaseBB;
2156 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2158 DEBUG(dbgs() << "Cases:\n");
2159 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2160 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2161 << ", Bits: " << CasesBits[i].Bits
2162 << ", BB: " << CasesBits[i].BB << '\n');
2164 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2165 CurMF->insert(BBI, CaseBB);
2166 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2170 // Put SV in a virtual register to make it available from the new blocks.
2171 ExportFromCurrentBlock(SV);
2174 BitTestBlock BTB(lowBound, cmpRange, SV,
2175 -1U, (CR.CaseBB == SwitchBB),
2176 CR.CaseBB, Default, BTC);
2178 if (CR.CaseBB == SwitchBB)
2179 visitBitTestHeader(BTB, SwitchBB);
2181 BitTestCases.push_back(BTB);
2186 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2187 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2188 const SwitchInst& SI) {
2191 // Start with "simple" cases
2192 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2193 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2194 Cases.push_back(Case(SI.getSuccessorValue(i),
2195 SI.getSuccessorValue(i),
2198 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2200 // Merge case into clusters
2201 if (Cases.size() >= 2)
2202 // Must recompute end() each iteration because it may be
2203 // invalidated by erase if we hold on to it
2204 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2205 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2206 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2207 MachineBasicBlock* nextBB = J->BB;
2208 MachineBasicBlock* currentBB = I->BB;
2210 // If the two neighboring cases go to the same destination, merge them
2211 // into a single case.
2212 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2220 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2221 if (I->Low != I->High)
2222 // A range counts double, since it requires two compares.
2229 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2230 MachineBasicBlock *Last) {
2232 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2233 if (JTCases[i].first.HeaderBB == First)
2234 JTCases[i].first.HeaderBB = Last;
2236 // Update BitTestCases.
2237 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2238 if (BitTestCases[i].Parent == First)
2239 BitTestCases[i].Parent = Last;
2242 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2243 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2245 // Figure out which block is immediately after the current one.
2246 MachineBasicBlock *NextBlock = 0;
2247 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2249 // If there is only the default destination, branch to it if it is not the
2250 // next basic block. Otherwise, just fall through.
2251 if (SI.getNumOperands() == 2) {
2252 // Update machine-CFG edges.
2254 // If this is not a fall-through branch, emit the branch.
2255 SwitchMBB->addSuccessor(Default);
2256 if (Default != NextBlock)
2257 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2258 MVT::Other, getControlRoot(),
2259 DAG.getBasicBlock(Default)));
2264 // If there are any non-default case statements, create a vector of Cases
2265 // representing each one, and sort the vector so that we can efficiently
2266 // create a binary search tree from them.
2268 size_t numCmps = Clusterify(Cases, SI);
2269 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2270 << ". Total compares: " << numCmps << '\n');
2273 // Get the Value to be switched on and default basic blocks, which will be
2274 // inserted into CaseBlock records, representing basic blocks in the binary
2276 const Value *SV = SI.getOperand(0);
2278 // Push the initial CaseRec onto the worklist
2279 CaseRecVector WorkList;
2280 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2281 CaseRange(Cases.begin(),Cases.end())));
2283 while (!WorkList.empty()) {
2284 // Grab a record representing a case range to process off the worklist
2285 CaseRec CR = WorkList.back();
2286 WorkList.pop_back();
2288 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2291 // If the range has few cases (two or less) emit a series of specific
2293 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2296 // If the switch has more than 5 blocks, and at least 40% dense, and the
2297 // target supports indirect branches, then emit a jump table rather than
2298 // lowering the switch to a binary tree of conditional branches.
2299 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2302 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2303 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2304 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2308 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2309 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2311 // Update machine-CFG edges with unique successors.
2312 SmallVector<BasicBlock*, 32> succs;
2313 succs.reserve(I.getNumSuccessors());
2314 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2315 succs.push_back(I.getSuccessor(i));
2316 array_pod_sort(succs.begin(), succs.end());
2317 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2318 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2319 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2321 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2322 MVT::Other, getControlRoot(),
2323 getValue(I.getAddress())));
2326 void SelectionDAGBuilder::visitFSub(const User &I) {
2327 // -0.0 - X --> fneg
2328 const Type *Ty = I.getType();
2329 if (Ty->isVectorTy()) {
2330 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2331 const VectorType *DestTy = cast<VectorType>(I.getType());
2332 const Type *ElTy = DestTy->getElementType();
2333 unsigned VL = DestTy->getNumElements();
2334 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2335 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2337 SDValue Op2 = getValue(I.getOperand(1));
2338 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2339 Op2.getValueType(), Op2));
2345 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2346 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2347 SDValue Op2 = getValue(I.getOperand(1));
2348 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2349 Op2.getValueType(), Op2));
2353 visitBinary(I, ISD::FSUB);
2356 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2357 SDValue Op1 = getValue(I.getOperand(0));
2358 SDValue Op2 = getValue(I.getOperand(1));
2359 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2360 Op1.getValueType(), Op1, Op2));
2363 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2364 SDValue Op1 = getValue(I.getOperand(0));
2365 SDValue Op2 = getValue(I.getOperand(1));
2366 if (!I.getType()->isVectorTy() &&
2367 Op2.getValueType() != TLI.getShiftAmountTy()) {
2368 // If the operand is smaller than the shift count type, promote it.
2369 EVT PTy = TLI.getPointerTy();
2370 EVT STy = TLI.getShiftAmountTy();
2371 if (STy.bitsGT(Op2.getValueType()))
2372 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2373 TLI.getShiftAmountTy(), Op2);
2374 // If the operand is larger than the shift count type but the shift
2375 // count type has enough bits to represent any shift value, truncate
2376 // it now. This is a common case and it exposes the truncate to
2377 // optimization early.
2378 else if (STy.getSizeInBits() >=
2379 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2380 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2381 TLI.getShiftAmountTy(), Op2);
2382 // Otherwise we'll need to temporarily settle for some other
2383 // convenient type; type legalization will make adjustments as
2385 else if (PTy.bitsLT(Op2.getValueType()))
2386 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2387 TLI.getPointerTy(), Op2);
2388 else if (PTy.bitsGT(Op2.getValueType()))
2389 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2390 TLI.getPointerTy(), Op2);
2393 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2394 Op1.getValueType(), Op1, Op2));
2397 void SelectionDAGBuilder::visitICmp(const User &I) {
2398 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2399 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2400 predicate = IC->getPredicate();
2401 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2402 predicate = ICmpInst::Predicate(IC->getPredicate());
2403 SDValue Op1 = getValue(I.getOperand(0));
2404 SDValue Op2 = getValue(I.getOperand(1));
2405 ISD::CondCode Opcode = getICmpCondCode(predicate);
2407 EVT DestVT = TLI.getValueType(I.getType());
2408 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2411 void SelectionDAGBuilder::visitFCmp(const User &I) {
2412 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2413 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2414 predicate = FC->getPredicate();
2415 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2416 predicate = FCmpInst::Predicate(FC->getPredicate());
2417 SDValue Op1 = getValue(I.getOperand(0));
2418 SDValue Op2 = getValue(I.getOperand(1));
2419 ISD::CondCode Condition = getFCmpCondCode(predicate);
2420 EVT DestVT = TLI.getValueType(I.getType());
2421 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2424 void SelectionDAGBuilder::visitSelect(const User &I) {
2425 SmallVector<EVT, 4> ValueVTs;
2426 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2427 unsigned NumValues = ValueVTs.size();
2428 if (NumValues == 0) return;
2430 SmallVector<SDValue, 4> Values(NumValues);
2431 SDValue Cond = getValue(I.getOperand(0));
2432 SDValue TrueVal = getValue(I.getOperand(1));
2433 SDValue FalseVal = getValue(I.getOperand(2));
2435 for (unsigned i = 0; i != NumValues; ++i)
2436 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2437 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2439 SDValue(TrueVal.getNode(),
2440 TrueVal.getResNo() + i),
2441 SDValue(FalseVal.getNode(),
2442 FalseVal.getResNo() + i));
2444 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2445 DAG.getVTList(&ValueVTs[0], NumValues),
2446 &Values[0], NumValues));
2449 void SelectionDAGBuilder::visitTrunc(const User &I) {
2450 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2451 SDValue N = getValue(I.getOperand(0));
2452 EVT DestVT = TLI.getValueType(I.getType());
2453 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2456 void SelectionDAGBuilder::visitZExt(const User &I) {
2457 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2458 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2459 SDValue N = getValue(I.getOperand(0));
2460 EVT DestVT = TLI.getValueType(I.getType());
2461 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2464 void SelectionDAGBuilder::visitSExt(const User &I) {
2465 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2466 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2467 SDValue N = getValue(I.getOperand(0));
2468 EVT DestVT = TLI.getValueType(I.getType());
2469 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2472 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2473 // FPTrunc is never a no-op cast, no need to check
2474 SDValue N = getValue(I.getOperand(0));
2475 EVT DestVT = TLI.getValueType(I.getType());
2476 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2477 DestVT, N, DAG.getIntPtrConstant(0)));
2480 void SelectionDAGBuilder::visitFPExt(const User &I){
2481 // FPTrunc is never a no-op cast, no need to check
2482 SDValue N = getValue(I.getOperand(0));
2483 EVT DestVT = TLI.getValueType(I.getType());
2484 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2487 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2488 // FPToUI is never a no-op cast, no need to check
2489 SDValue N = getValue(I.getOperand(0));
2490 EVT DestVT = TLI.getValueType(I.getType());
2491 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2494 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2495 // FPToSI is never a no-op cast, no need to check
2496 SDValue N = getValue(I.getOperand(0));
2497 EVT DestVT = TLI.getValueType(I.getType());
2498 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2501 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2502 // UIToFP is never a no-op cast, no need to check
2503 SDValue N = getValue(I.getOperand(0));
2504 EVT DestVT = TLI.getValueType(I.getType());
2505 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2508 void SelectionDAGBuilder::visitSIToFP(const User &I){
2509 // SIToFP is never a no-op cast, no need to check
2510 SDValue N = getValue(I.getOperand(0));
2511 EVT DestVT = TLI.getValueType(I.getType());
2512 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2515 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2516 // What to do depends on the size of the integer and the size of the pointer.
2517 // We can either truncate, zero extend, or no-op, accordingly.
2518 SDValue N = getValue(I.getOperand(0));
2519 EVT DestVT = TLI.getValueType(I.getType());
2520 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2523 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2524 // What to do depends on the size of the integer and the size of the pointer.
2525 // We can either truncate, zero extend, or no-op, accordingly.
2526 SDValue N = getValue(I.getOperand(0));
2527 EVT DestVT = TLI.getValueType(I.getType());
2528 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2531 void SelectionDAGBuilder::visitBitCast(const User &I) {
2532 SDValue N = getValue(I.getOperand(0));
2533 EVT DestVT = TLI.getValueType(I.getType());
2535 // BitCast assures us that source and destination are the same size so this is
2536 // either a BIT_CONVERT or a no-op.
2537 if (DestVT != N.getValueType())
2538 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2539 DestVT, N)); // convert types.
2541 setValue(&I, N); // noop cast.
2544 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2545 SDValue InVec = getValue(I.getOperand(0));
2546 SDValue InVal = getValue(I.getOperand(1));
2547 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2549 getValue(I.getOperand(2)));
2550 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2551 TLI.getValueType(I.getType()),
2552 InVec, InVal, InIdx));
2555 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2556 SDValue InVec = getValue(I.getOperand(0));
2557 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2559 getValue(I.getOperand(1)));
2560 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2561 TLI.getValueType(I.getType()), InVec, InIdx));
2564 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2565 // from SIndx and increasing to the element length (undefs are allowed).
2566 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2567 unsigned MaskNumElts = Mask.size();
2568 for (unsigned i = 0; i != MaskNumElts; ++i)
2569 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2574 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2575 SmallVector<int, 8> Mask;
2576 SDValue Src1 = getValue(I.getOperand(0));
2577 SDValue Src2 = getValue(I.getOperand(1));
2579 // Convert the ConstantVector mask operand into an array of ints, with -1
2580 // representing undef values.
2581 SmallVector<Constant*, 8> MaskElts;
2582 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2583 unsigned MaskNumElts = MaskElts.size();
2584 for (unsigned i = 0; i != MaskNumElts; ++i) {
2585 if (isa<UndefValue>(MaskElts[i]))
2588 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2591 EVT VT = TLI.getValueType(I.getType());
2592 EVT SrcVT = Src1.getValueType();
2593 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2595 if (SrcNumElts == MaskNumElts) {
2596 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2601 // Normalize the shuffle vector since mask and vector length don't match.
2602 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2603 // Mask is longer than the source vectors and is a multiple of the source
2604 // vectors. We can use concatenate vector to make the mask and vectors
2606 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2607 // The shuffle is concatenating two vectors together.
2608 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2613 // Pad both vectors with undefs to make them the same length as the mask.
2614 unsigned NumConcat = MaskNumElts / SrcNumElts;
2615 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2616 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2617 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2619 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2620 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2624 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2625 getCurDebugLoc(), VT,
2626 &MOps1[0], NumConcat);
2627 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2628 getCurDebugLoc(), VT,
2629 &MOps2[0], NumConcat);
2631 // Readjust mask for new input vector length.
2632 SmallVector<int, 8> MappedOps;
2633 for (unsigned i = 0; i != MaskNumElts; ++i) {
2635 if (Idx < (int)SrcNumElts)
2636 MappedOps.push_back(Idx);
2638 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2641 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2646 if (SrcNumElts > MaskNumElts) {
2647 // Analyze the access pattern of the vector to see if we can extract
2648 // two subvectors and do the shuffle. The analysis is done by calculating
2649 // the range of elements the mask access on both vectors.
2650 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2651 int MaxRange[2] = {-1, -1};
2653 for (unsigned i = 0; i != MaskNumElts; ++i) {
2659 if (Idx >= (int)SrcNumElts) {
2663 if (Idx > MaxRange[Input])
2664 MaxRange[Input] = Idx;
2665 if (Idx < MinRange[Input])
2666 MinRange[Input] = Idx;
2669 // Check if the access is smaller than the vector size and can we find
2670 // a reasonable extract index.
2671 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2673 int StartIdx[2]; // StartIdx to extract from
2674 for (int Input=0; Input < 2; ++Input) {
2675 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2676 RangeUse[Input] = 0; // Unused
2677 StartIdx[Input] = 0;
2678 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2679 // Fits within range but we should see if we can find a good
2680 // start index that is a multiple of the mask length.
2681 if (MaxRange[Input] < (int)MaskNumElts) {
2682 RangeUse[Input] = 1; // Extract from beginning of the vector
2683 StartIdx[Input] = 0;
2685 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2686 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2687 StartIdx[Input] + MaskNumElts < SrcNumElts)
2688 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2693 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2694 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2697 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2698 // Extract appropriate subvector and generate a vector shuffle
2699 for (int Input=0; Input < 2; ++Input) {
2700 SDValue &Src = Input == 0 ? Src1 : Src2;
2701 if (RangeUse[Input] == 0)
2702 Src = DAG.getUNDEF(VT);
2704 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2705 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2708 // Calculate new mask.
2709 SmallVector<int, 8> MappedOps;
2710 for (unsigned i = 0; i != MaskNumElts; ++i) {
2713 MappedOps.push_back(Idx);
2714 else if (Idx < (int)SrcNumElts)
2715 MappedOps.push_back(Idx - StartIdx[0]);
2717 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2720 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2726 // We can't use either concat vectors or extract subvectors so fall back to
2727 // replacing the shuffle with extract and build vector.
2728 // to insert and build vector.
2729 EVT EltVT = VT.getVectorElementType();
2730 EVT PtrVT = TLI.getPointerTy();
2731 SmallVector<SDValue,8> Ops;
2732 for (unsigned i = 0; i != MaskNumElts; ++i) {
2734 Ops.push_back(DAG.getUNDEF(EltVT));
2739 if (Idx < (int)SrcNumElts)
2740 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2741 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2743 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2745 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2751 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2752 VT, &Ops[0], Ops.size()));
2755 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2756 const Value *Op0 = I.getOperand(0);
2757 const Value *Op1 = I.getOperand(1);
2758 const Type *AggTy = I.getType();
2759 const Type *ValTy = Op1->getType();
2760 bool IntoUndef = isa<UndefValue>(Op0);
2761 bool FromUndef = isa<UndefValue>(Op1);
2763 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2765 SmallVector<EVT, 4> AggValueVTs;
2766 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2767 SmallVector<EVT, 4> ValValueVTs;
2768 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2770 unsigned NumAggValues = AggValueVTs.size();
2771 unsigned NumValValues = ValValueVTs.size();
2772 SmallVector<SDValue, 4> Values(NumAggValues);
2774 SDValue Agg = getValue(Op0);
2775 SDValue Val = getValue(Op1);
2777 // Copy the beginning value(s) from the original aggregate.
2778 for (; i != LinearIndex; ++i)
2779 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2780 SDValue(Agg.getNode(), Agg.getResNo() + i);
2781 // Copy values from the inserted value(s).
2782 for (; i != LinearIndex + NumValValues; ++i)
2783 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2784 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2785 // Copy remaining value(s) from the original aggregate.
2786 for (; i != NumAggValues; ++i)
2787 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2788 SDValue(Agg.getNode(), Agg.getResNo() + i);
2790 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2791 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2792 &Values[0], NumAggValues));
2795 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2796 const Value *Op0 = I.getOperand(0);
2797 const Type *AggTy = Op0->getType();
2798 const Type *ValTy = I.getType();
2799 bool OutOfUndef = isa<UndefValue>(Op0);
2801 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2803 SmallVector<EVT, 4> ValValueVTs;
2804 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2806 unsigned NumValValues = ValValueVTs.size();
2807 SmallVector<SDValue, 4> Values(NumValValues);
2809 SDValue Agg = getValue(Op0);
2810 // Copy out the selected value(s).
2811 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2812 Values[i - LinearIndex] =
2814 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2815 SDValue(Agg.getNode(), Agg.getResNo() + i);
2817 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2818 DAG.getVTList(&ValValueVTs[0], NumValValues),
2819 &Values[0], NumValValues));
2822 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2823 SDValue N = getValue(I.getOperand(0));
2824 const Type *Ty = I.getOperand(0)->getType();
2826 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2828 const Value *Idx = *OI;
2829 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2830 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2833 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2834 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2835 DAG.getIntPtrConstant(Offset));
2838 Ty = StTy->getElementType(Field);
2840 Ty = cast<SequentialType>(Ty)->getElementType();
2842 // If this is a constant subscript, handle it quickly.
2843 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2844 if (CI->isZero()) continue;
2846 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2848 EVT PTy = TLI.getPointerTy();
2849 unsigned PtrBits = PTy.getSizeInBits();
2851 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2853 DAG.getConstant(Offs, MVT::i64));
2855 OffsVal = DAG.getIntPtrConstant(Offs);
2857 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2862 // N = N + Idx * ElementSize;
2863 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2864 TD->getTypeAllocSize(Ty));
2865 SDValue IdxN = getValue(Idx);
2867 // If the index is smaller or larger than intptr_t, truncate or extend
2869 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2871 // If this is a multiply by a power of two, turn it into a shl
2872 // immediately. This is a very common case.
2873 if (ElementSize != 1) {
2874 if (ElementSize.isPowerOf2()) {
2875 unsigned Amt = ElementSize.logBase2();
2876 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2877 N.getValueType(), IdxN,
2878 DAG.getConstant(Amt, TLI.getPointerTy()));
2880 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2881 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2882 N.getValueType(), IdxN, Scale);
2886 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2887 N.getValueType(), N, IdxN);
2894 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2895 // If this is a fixed sized alloca in the entry block of the function,
2896 // allocate it statically on the stack.
2897 if (FuncInfo.StaticAllocaMap.count(&I))
2898 return; // getValue will auto-populate this.
2900 const Type *Ty = I.getAllocatedType();
2901 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2903 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2906 SDValue AllocSize = getValue(I.getArraySize());
2908 EVT IntPtr = TLI.getPointerTy();
2909 if (AllocSize.getValueType() != IntPtr)
2910 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2912 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2914 DAG.getConstant(TySize, IntPtr));
2916 // Handle alignment. If the requested alignment is less than or equal to
2917 // the stack alignment, ignore it. If the size is greater than or equal to
2918 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2919 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2920 if (Align <= StackAlign)
2923 // Round the size of the allocation up to the stack alignment size
2924 // by add SA-1 to the size.
2925 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2926 AllocSize.getValueType(), AllocSize,
2927 DAG.getIntPtrConstant(StackAlign-1));
2929 // Mask out the low bits for alignment purposes.
2930 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2931 AllocSize.getValueType(), AllocSize,
2932 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2934 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2935 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2936 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2939 DAG.setRoot(DSA.getValue(1));
2941 // Inform the Frame Information that we have just allocated a variable-sized
2943 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2946 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2947 const Value *SV = I.getOperand(0);
2948 SDValue Ptr = getValue(SV);
2950 const Type *Ty = I.getType();
2952 bool isVolatile = I.isVolatile();
2953 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2954 unsigned Alignment = I.getAlignment();
2955 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
2957 SmallVector<EVT, 4> ValueVTs;
2958 SmallVector<uint64_t, 4> Offsets;
2959 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2960 unsigned NumValues = ValueVTs.size();
2965 bool ConstantMemory = false;
2966 if (I.isVolatile() || NumValues > MaxParallelChains)
2967 // Serialize volatile loads with other side effects.
2969 else if (AA->pointsToConstantMemory(
2970 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
2971 // Do not serialize (non-volatile) loads of constant memory with anything.
2972 Root = DAG.getEntryNode();
2973 ConstantMemory = true;
2975 // Do not serialize non-volatile loads against each other.
2976 Root = DAG.getRoot();
2979 SmallVector<SDValue, 4> Values(NumValues);
2980 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2982 EVT PtrVT = Ptr.getValueType();
2983 unsigned ChainI = 0;
2984 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2985 // Serializing loads here may result in excessive register pressure, and
2986 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2987 // could recover a bit by hoisting nodes upward in the chain by recognizing
2988 // they are side-effect free or do not alias. The optimizer should really
2989 // avoid this case by converting large object/array copies to llvm.memcpy
2990 // (MaxParallelChains should always remain as failsafe).
2991 if (ChainI == MaxParallelChains) {
2992 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2993 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2994 MVT::Other, &Chains[0], ChainI);
2998 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3000 DAG.getConstant(Offsets[i], PtrVT));
3001 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3002 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3003 isNonTemporal, Alignment, TBAAInfo);
3006 Chains[ChainI] = L.getValue(1);
3009 if (!ConstantMemory) {
3010 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3011 MVT::Other, &Chains[0], ChainI);
3015 PendingLoads.push_back(Chain);
3018 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3019 DAG.getVTList(&ValueVTs[0], NumValues),
3020 &Values[0], NumValues));
3023 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3024 const Value *SrcV = I.getOperand(0);
3025 const Value *PtrV = I.getOperand(1);
3027 SmallVector<EVT, 4> ValueVTs;
3028 SmallVector<uint64_t, 4> Offsets;
3029 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3030 unsigned NumValues = ValueVTs.size();
3034 // Get the lowered operands. Note that we do this after
3035 // checking if NumResults is zero, because with zero results
3036 // the operands won't have values in the map.
3037 SDValue Src = getValue(SrcV);
3038 SDValue Ptr = getValue(PtrV);
3040 SDValue Root = getRoot();
3041 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3043 EVT PtrVT = Ptr.getValueType();
3044 bool isVolatile = I.isVolatile();
3045 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3046 unsigned Alignment = I.getAlignment();
3047 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3049 unsigned ChainI = 0;
3050 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3051 // See visitLoad comments.
3052 if (ChainI == MaxParallelChains) {
3053 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3054 MVT::Other, &Chains[0], ChainI);
3058 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3059 DAG.getConstant(Offsets[i], PtrVT));
3060 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3061 SDValue(Src.getNode(), Src.getResNo() + i),
3062 Add, MachinePointerInfo(PtrV, Offsets[i]),
3063 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3064 Chains[ChainI] = St;
3067 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3068 MVT::Other, &Chains[0], ChainI);
3070 AssignOrderingToNode(StoreNode.getNode());
3071 DAG.setRoot(StoreNode);
3074 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3076 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3077 unsigned Intrinsic) {
3078 bool HasChain = !I.doesNotAccessMemory();
3079 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3081 // Build the operand list.
3082 SmallVector<SDValue, 8> Ops;
3083 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3085 // We don't need to serialize loads against other loads.
3086 Ops.push_back(DAG.getRoot());
3088 Ops.push_back(getRoot());
3092 // Info is set by getTgtMemInstrinsic
3093 TargetLowering::IntrinsicInfo Info;
3094 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3096 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3097 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3098 Info.opc == ISD::INTRINSIC_W_CHAIN)
3099 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3101 // Add all operands of the call to the operand list.
3102 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3103 SDValue Op = getValue(I.getArgOperand(i));
3104 assert(TLI.isTypeLegal(Op.getValueType()) &&
3105 "Intrinsic uses a non-legal type?");
3109 SmallVector<EVT, 4> ValueVTs;
3110 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3112 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3113 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3114 "Intrinsic uses a non-legal type?");
3119 ValueVTs.push_back(MVT::Other);
3121 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3125 if (IsTgtIntrinsic) {
3126 // This is target intrinsic that touches memory
3127 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3128 VTs, &Ops[0], Ops.size(),
3130 MachinePointerInfo(Info.ptrVal, Info.offset),
3131 Info.align, Info.vol,
3132 Info.readMem, Info.writeMem);
3133 } else if (!HasChain) {
3134 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3135 VTs, &Ops[0], Ops.size());
3136 } else if (!I.getType()->isVoidTy()) {
3137 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3138 VTs, &Ops[0], Ops.size());
3140 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3141 VTs, &Ops[0], Ops.size());
3145 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3147 PendingLoads.push_back(Chain);
3152 if (!I.getType()->isVoidTy()) {
3153 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3154 EVT VT = TLI.getValueType(PTy);
3155 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3158 setValue(&I, Result);
3162 /// GetSignificand - Get the significand and build it into a floating-point
3163 /// number with exponent of 1:
3165 /// Op = (Op & 0x007fffff) | 0x3f800000;
3167 /// where Op is the hexidecimal representation of floating point value.
3169 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3170 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3171 DAG.getConstant(0x007fffff, MVT::i32));
3172 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3173 DAG.getConstant(0x3f800000, MVT::i32));
3174 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3177 /// GetExponent - Get the exponent:
3179 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3181 /// where Op is the hexidecimal representation of floating point value.
3183 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3185 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3186 DAG.getConstant(0x7f800000, MVT::i32));
3187 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3188 DAG.getConstant(23, TLI.getPointerTy()));
3189 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3190 DAG.getConstant(127, MVT::i32));
3191 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3194 /// getF32Constant - Get 32-bit floating point constant.
3196 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3197 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3200 /// Inlined utility function to implement binary input atomic intrinsics for
3201 /// visitIntrinsicCall: I is a call instruction
3202 /// Op is the associated NodeType for I
3204 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3206 SDValue Root = getRoot();
3208 DAG.getAtomic(Op, getCurDebugLoc(),
3209 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3211 getValue(I.getArgOperand(0)),
3212 getValue(I.getArgOperand(1)),
3213 I.getArgOperand(0));
3215 DAG.setRoot(L.getValue(1));
3219 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3221 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3222 SDValue Op1 = getValue(I.getArgOperand(0));
3223 SDValue Op2 = getValue(I.getArgOperand(1));
3225 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3226 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3230 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3231 /// limited-precision mode.
3233 SelectionDAGBuilder::visitExp(const CallInst &I) {
3235 DebugLoc dl = getCurDebugLoc();
3237 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3238 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3239 SDValue Op = getValue(I.getArgOperand(0));
3241 // Put the exponent in the right bit position for later addition to the
3244 // #define LOG2OFe 1.4426950f
3245 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3246 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3247 getF32Constant(DAG, 0x3fb8aa3b));
3248 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3250 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3251 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3252 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3254 // IntegerPartOfX <<= 23;
3255 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3256 DAG.getConstant(23, TLI.getPointerTy()));
3258 if (LimitFloatPrecision <= 6) {
3259 // For floating-point precision of 6:
3261 // TwoToFractionalPartOfX =
3263 // (0.735607626f + 0.252464424f * x) * x;
3265 // error 0.0144103317, which is 6 bits
3266 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3267 getF32Constant(DAG, 0x3e814304));
3268 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3269 getF32Constant(DAG, 0x3f3c50c8));
3270 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3271 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3272 getF32Constant(DAG, 0x3f7f5e7e));
3273 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3275 // Add the exponent into the result in integer domain.
3276 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3277 TwoToFracPartOfX, IntegerPartOfX);
3279 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3280 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3281 // For floating-point precision of 12:
3283 // TwoToFractionalPartOfX =
3286 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3288 // 0.000107046256 error, which is 13 to 14 bits
3289 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3290 getF32Constant(DAG, 0x3da235e3));
3291 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3292 getF32Constant(DAG, 0x3e65b8f3));
3293 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3294 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3295 getF32Constant(DAG, 0x3f324b07));
3296 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3297 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3298 getF32Constant(DAG, 0x3f7ff8fd));
3299 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3301 // Add the exponent into the result in integer domain.
3302 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3303 TwoToFracPartOfX, IntegerPartOfX);
3305 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3306 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3307 // For floating-point precision of 18:
3309 // TwoToFractionalPartOfX =
3313 // (0.554906021e-1f +
3314 // (0.961591928e-2f +
3315 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3317 // error 2.47208000*10^(-7), which is better than 18 bits
3318 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3319 getF32Constant(DAG, 0x3924b03e));
3320 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3321 getF32Constant(DAG, 0x3ab24b87));
3322 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3323 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3324 getF32Constant(DAG, 0x3c1d8c17));
3325 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3326 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3327 getF32Constant(DAG, 0x3d634a1d));
3328 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3329 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3330 getF32Constant(DAG, 0x3e75fe14));
3331 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3332 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3333 getF32Constant(DAG, 0x3f317234));
3334 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3335 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3336 getF32Constant(DAG, 0x3f800000));
3337 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3340 // Add the exponent into the result in integer domain.
3341 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3342 TwoToFracPartOfX, IntegerPartOfX);
3344 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3347 // No special expansion.
3348 result = DAG.getNode(ISD::FEXP, dl,
3349 getValue(I.getArgOperand(0)).getValueType(),
3350 getValue(I.getArgOperand(0)));
3353 setValue(&I, result);
3356 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3357 /// limited-precision mode.
3359 SelectionDAGBuilder::visitLog(const CallInst &I) {
3361 DebugLoc dl = getCurDebugLoc();
3363 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3364 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3365 SDValue Op = getValue(I.getArgOperand(0));
3366 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3368 // Scale the exponent by log(2) [0.69314718f].
3369 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3370 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3371 getF32Constant(DAG, 0x3f317218));
3373 // Get the significand and build it into a floating-point number with
3375 SDValue X = GetSignificand(DAG, Op1, dl);
3377 if (LimitFloatPrecision <= 6) {
3378 // For floating-point precision of 6:
3382 // (1.4034025f - 0.23903021f * x) * x;
3384 // error 0.0034276066, which is better than 8 bits
3385 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3386 getF32Constant(DAG, 0xbe74c456));
3387 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3388 getF32Constant(DAG, 0x3fb3a2b1));
3389 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3390 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3391 getF32Constant(DAG, 0x3f949a29));
3393 result = DAG.getNode(ISD::FADD, dl,
3394 MVT::f32, LogOfExponent, LogOfMantissa);
3395 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3396 // For floating-point precision of 12:
3402 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3404 // error 0.000061011436, which is 14 bits
3405 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3406 getF32Constant(DAG, 0xbd67b6d6));
3407 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3408 getF32Constant(DAG, 0x3ee4f4b8));
3409 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3410 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3411 getF32Constant(DAG, 0x3fbc278b));
3412 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3413 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3414 getF32Constant(DAG, 0x40348e95));
3415 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3416 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3417 getF32Constant(DAG, 0x3fdef31a));
3419 result = DAG.getNode(ISD::FADD, dl,
3420 MVT::f32, LogOfExponent, LogOfMantissa);
3421 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3422 // For floating-point precision of 18:
3430 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3432 // error 0.0000023660568, which is better than 18 bits
3433 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3434 getF32Constant(DAG, 0xbc91e5ac));
3435 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3436 getF32Constant(DAG, 0x3e4350aa));
3437 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3438 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3439 getF32Constant(DAG, 0x3f60d3e3));
3440 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3441 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3442 getF32Constant(DAG, 0x4011cdf0));
3443 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3444 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3445 getF32Constant(DAG, 0x406cfd1c));
3446 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3447 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3448 getF32Constant(DAG, 0x408797cb));
3449 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3450 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3451 getF32Constant(DAG, 0x4006dcab));
3453 result = DAG.getNode(ISD::FADD, dl,
3454 MVT::f32, LogOfExponent, LogOfMantissa);
3457 // No special expansion.
3458 result = DAG.getNode(ISD::FLOG, dl,
3459 getValue(I.getArgOperand(0)).getValueType(),
3460 getValue(I.getArgOperand(0)));
3463 setValue(&I, result);
3466 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3467 /// limited-precision mode.
3469 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3471 DebugLoc dl = getCurDebugLoc();
3473 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3474 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3475 SDValue Op = getValue(I.getArgOperand(0));
3476 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3478 // Get the exponent.
3479 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3481 // Get the significand and build it into a floating-point number with
3483 SDValue X = GetSignificand(DAG, Op1, dl);
3485 // Different possible minimax approximations of significand in
3486 // floating-point for various degrees of accuracy over [1,2].
3487 if (LimitFloatPrecision <= 6) {
3488 // For floating-point precision of 6:
3490 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3492 // error 0.0049451742, which is more than 7 bits
3493 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3494 getF32Constant(DAG, 0xbeb08fe0));
3495 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3496 getF32Constant(DAG, 0x40019463));
3497 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3498 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3499 getF32Constant(DAG, 0x3fd6633d));
3501 result = DAG.getNode(ISD::FADD, dl,
3502 MVT::f32, LogOfExponent, Log2ofMantissa);
3503 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3504 // For floating-point precision of 12:
3510 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3512 // error 0.0000876136000, which is better than 13 bits
3513 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3514 getF32Constant(DAG, 0xbda7262e));
3515 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3516 getF32Constant(DAG, 0x3f25280b));
3517 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3518 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3519 getF32Constant(DAG, 0x4007b923));
3520 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3521 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3522 getF32Constant(DAG, 0x40823e2f));
3523 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3524 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3525 getF32Constant(DAG, 0x4020d29c));
3527 result = DAG.getNode(ISD::FADD, dl,
3528 MVT::f32, LogOfExponent, Log2ofMantissa);
3529 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3530 // For floating-point precision of 18:
3539 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3541 // error 0.0000018516, which is better than 18 bits
3542 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3543 getF32Constant(DAG, 0xbcd2769e));
3544 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3545 getF32Constant(DAG, 0x3e8ce0b9));
3546 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3547 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3548 getF32Constant(DAG, 0x3fa22ae7));
3549 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3550 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3551 getF32Constant(DAG, 0x40525723));
3552 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3553 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3554 getF32Constant(DAG, 0x40aaf200));
3555 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3556 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3557 getF32Constant(DAG, 0x40c39dad));
3558 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3559 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3560 getF32Constant(DAG, 0x4042902c));
3562 result = DAG.getNode(ISD::FADD, dl,
3563 MVT::f32, LogOfExponent, Log2ofMantissa);
3566 // No special expansion.
3567 result = DAG.getNode(ISD::FLOG2, dl,
3568 getValue(I.getArgOperand(0)).getValueType(),
3569 getValue(I.getArgOperand(0)));
3572 setValue(&I, result);
3575 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3576 /// limited-precision mode.
3578 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3580 DebugLoc dl = getCurDebugLoc();
3582 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3583 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3584 SDValue Op = getValue(I.getArgOperand(0));
3585 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3587 // Scale the exponent by log10(2) [0.30102999f].
3588 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3589 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3590 getF32Constant(DAG, 0x3e9a209a));
3592 // Get the significand and build it into a floating-point number with
3594 SDValue X = GetSignificand(DAG, Op1, dl);
3596 if (LimitFloatPrecision <= 6) {
3597 // For floating-point precision of 6:
3599 // Log10ofMantissa =
3601 // (0.60948995f - 0.10380950f * x) * x;
3603 // error 0.0014886165, which is 6 bits
3604 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3605 getF32Constant(DAG, 0xbdd49a13));
3606 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3607 getF32Constant(DAG, 0x3f1c0789));
3608 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3609 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3610 getF32Constant(DAG, 0x3f011300));
3612 result = DAG.getNode(ISD::FADD, dl,
3613 MVT::f32, LogOfExponent, Log10ofMantissa);
3614 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3615 // For floating-point precision of 12:
3617 // Log10ofMantissa =
3620 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3622 // error 0.00019228036, which is better than 12 bits
3623 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3624 getF32Constant(DAG, 0x3d431f31));
3625 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3626 getF32Constant(DAG, 0x3ea21fb2));
3627 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3628 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3629 getF32Constant(DAG, 0x3f6ae232));
3630 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3631 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3632 getF32Constant(DAG, 0x3f25f7c3));
3634 result = DAG.getNode(ISD::FADD, dl,
3635 MVT::f32, LogOfExponent, Log10ofMantissa);
3636 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3637 // For floating-point precision of 18:
3639 // Log10ofMantissa =
3644 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3646 // error 0.0000037995730, which is better than 18 bits
3647 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3648 getF32Constant(DAG, 0x3c5d51ce));
3649 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3650 getF32Constant(DAG, 0x3e00685a));
3651 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3652 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3653 getF32Constant(DAG, 0x3efb6798));
3654 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3655 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3656 getF32Constant(DAG, 0x3f88d192));
3657 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3658 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3659 getF32Constant(DAG, 0x3fc4316c));
3660 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3661 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3662 getF32Constant(DAG, 0x3f57ce70));
3664 result = DAG.getNode(ISD::FADD, dl,
3665 MVT::f32, LogOfExponent, Log10ofMantissa);
3668 // No special expansion.
3669 result = DAG.getNode(ISD::FLOG10, dl,
3670 getValue(I.getArgOperand(0)).getValueType(),
3671 getValue(I.getArgOperand(0)));
3674 setValue(&I, result);
3677 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3678 /// limited-precision mode.
3680 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3682 DebugLoc dl = getCurDebugLoc();
3684 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3685 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3686 SDValue Op = getValue(I.getArgOperand(0));
3688 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3690 // FractionalPartOfX = x - (float)IntegerPartOfX;
3691 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3692 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3694 // IntegerPartOfX <<= 23;
3695 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3696 DAG.getConstant(23, TLI.getPointerTy()));
3698 if (LimitFloatPrecision <= 6) {
3699 // For floating-point precision of 6:
3701 // TwoToFractionalPartOfX =
3703 // (0.735607626f + 0.252464424f * x) * x;
3705 // error 0.0144103317, which is 6 bits
3706 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3707 getF32Constant(DAG, 0x3e814304));
3708 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3709 getF32Constant(DAG, 0x3f3c50c8));
3710 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3711 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3712 getF32Constant(DAG, 0x3f7f5e7e));
3713 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3714 SDValue TwoToFractionalPartOfX =
3715 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3717 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3718 MVT::f32, TwoToFractionalPartOfX);
3719 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3720 // For floating-point precision of 12:
3722 // TwoToFractionalPartOfX =
3725 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3727 // error 0.000107046256, which is 13 to 14 bits
3728 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3729 getF32Constant(DAG, 0x3da235e3));
3730 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3731 getF32Constant(DAG, 0x3e65b8f3));
3732 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3733 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3734 getF32Constant(DAG, 0x3f324b07));
3735 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3736 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3737 getF32Constant(DAG, 0x3f7ff8fd));
3738 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3739 SDValue TwoToFractionalPartOfX =
3740 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3742 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3743 MVT::f32, TwoToFractionalPartOfX);
3744 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3745 // For floating-point precision of 18:
3747 // TwoToFractionalPartOfX =
3751 // (0.554906021e-1f +
3752 // (0.961591928e-2f +
3753 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3754 // error 2.47208000*10^(-7), which is better than 18 bits
3755 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3756 getF32Constant(DAG, 0x3924b03e));
3757 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3758 getF32Constant(DAG, 0x3ab24b87));
3759 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3760 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3761 getF32Constant(DAG, 0x3c1d8c17));
3762 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3763 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3764 getF32Constant(DAG, 0x3d634a1d));
3765 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3766 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3767 getF32Constant(DAG, 0x3e75fe14));
3768 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3769 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3770 getF32Constant(DAG, 0x3f317234));
3771 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3772 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3773 getF32Constant(DAG, 0x3f800000));
3774 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3775 SDValue TwoToFractionalPartOfX =
3776 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3778 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3779 MVT::f32, TwoToFractionalPartOfX);
3782 // No special expansion.
3783 result = DAG.getNode(ISD::FEXP2, dl,
3784 getValue(I.getArgOperand(0)).getValueType(),
3785 getValue(I.getArgOperand(0)));
3788 setValue(&I, result);
3791 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3792 /// limited-precision mode with x == 10.0f.
3794 SelectionDAGBuilder::visitPow(const CallInst &I) {
3796 const Value *Val = I.getArgOperand(0);
3797 DebugLoc dl = getCurDebugLoc();
3798 bool IsExp10 = false;
3800 if (getValue(Val).getValueType() == MVT::f32 &&
3801 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3802 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3803 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3804 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3806 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3811 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3812 SDValue Op = getValue(I.getArgOperand(1));
3814 // Put the exponent in the right bit position for later addition to the
3817 // #define LOG2OF10 3.3219281f
3818 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3819 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3820 getF32Constant(DAG, 0x40549a78));
3821 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3823 // FractionalPartOfX = x - (float)IntegerPartOfX;
3824 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3825 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3827 // IntegerPartOfX <<= 23;
3828 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3829 DAG.getConstant(23, TLI.getPointerTy()));
3831 if (LimitFloatPrecision <= 6) {
3832 // For floating-point precision of 6:
3834 // twoToFractionalPartOfX =
3836 // (0.735607626f + 0.252464424f * x) * x;
3838 // error 0.0144103317, which is 6 bits
3839 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3840 getF32Constant(DAG, 0x3e814304));
3841 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3842 getF32Constant(DAG, 0x3f3c50c8));
3843 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3844 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3845 getF32Constant(DAG, 0x3f7f5e7e));
3846 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3847 SDValue TwoToFractionalPartOfX =
3848 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3850 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3851 MVT::f32, TwoToFractionalPartOfX);
3852 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3853 // For floating-point precision of 12:
3855 // TwoToFractionalPartOfX =
3858 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3860 // error 0.000107046256, which is 13 to 14 bits
3861 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3862 getF32Constant(DAG, 0x3da235e3));
3863 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3864 getF32Constant(DAG, 0x3e65b8f3));
3865 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3866 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3867 getF32Constant(DAG, 0x3f324b07));
3868 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3869 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3870 getF32Constant(DAG, 0x3f7ff8fd));
3871 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3872 SDValue TwoToFractionalPartOfX =
3873 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3875 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3876 MVT::f32, TwoToFractionalPartOfX);
3877 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3878 // For floating-point precision of 18:
3880 // TwoToFractionalPartOfX =
3884 // (0.554906021e-1f +
3885 // (0.961591928e-2f +
3886 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3887 // error 2.47208000*10^(-7), which is better than 18 bits
3888 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3889 getF32Constant(DAG, 0x3924b03e));
3890 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3891 getF32Constant(DAG, 0x3ab24b87));
3892 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3893 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3894 getF32Constant(DAG, 0x3c1d8c17));
3895 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3896 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3897 getF32Constant(DAG, 0x3d634a1d));
3898 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3899 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3900 getF32Constant(DAG, 0x3e75fe14));
3901 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3902 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3903 getF32Constant(DAG, 0x3f317234));
3904 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3905 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3906 getF32Constant(DAG, 0x3f800000));
3907 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3908 SDValue TwoToFractionalPartOfX =
3909 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3911 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3912 MVT::f32, TwoToFractionalPartOfX);
3915 // No special expansion.
3916 result = DAG.getNode(ISD::FPOW, dl,
3917 getValue(I.getArgOperand(0)).getValueType(),
3918 getValue(I.getArgOperand(0)),
3919 getValue(I.getArgOperand(1)));
3922 setValue(&I, result);
3926 /// ExpandPowI - Expand a llvm.powi intrinsic.
3927 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3928 SelectionDAG &DAG) {
3929 // If RHS is a constant, we can expand this out to a multiplication tree,
3930 // otherwise we end up lowering to a call to __powidf2 (for example). When
3931 // optimizing for size, we only want to do this if the expansion would produce
3932 // a small number of multiplies, otherwise we do the full expansion.
3933 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3934 // Get the exponent as a positive value.
3935 unsigned Val = RHSC->getSExtValue();
3936 if ((int)Val < 0) Val = -Val;
3938 // powi(x, 0) -> 1.0
3940 return DAG.getConstantFP(1.0, LHS.getValueType());
3942 const Function *F = DAG.getMachineFunction().getFunction();
3943 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3944 // If optimizing for size, don't insert too many multiplies. This
3945 // inserts up to 5 multiplies.
3946 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3947 // We use the simple binary decomposition method to generate the multiply
3948 // sequence. There are more optimal ways to do this (for example,
3949 // powi(x,15) generates one more multiply than it should), but this has
3950 // the benefit of being both really simple and much better than a libcall.
3951 SDValue Res; // Logically starts equal to 1.0
3952 SDValue CurSquare = LHS;
3956 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3958 Res = CurSquare; // 1.0*CurSquare.
3961 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3962 CurSquare, CurSquare);
3966 // If the original was negative, invert the result, producing 1/(x*x*x).
3967 if (RHSC->getSExtValue() < 0)
3968 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3969 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3974 // Otherwise, expand to a libcall.
3975 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3978 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3979 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3980 /// At the end of instruction selection, they will be inserted to the entry BB.
3982 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
3985 const Argument *Arg = dyn_cast<Argument>(V);
3989 MachineFunction &MF = DAG.getMachineFunction();
3990 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
3991 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3993 // Ignore inlined function arguments here.
3994 DIVariable DV(Variable);
3995 if (DV.isInlinedFnArgument(MF.getFunction()))
3998 MachineBasicBlock *MBB = FuncInfo.MBB;
3999 if (MBB != &MF.front())
4003 if (Arg->hasByValAttr()) {
4004 // Byval arguments' frame index is recorded during argument lowering.
4005 // Use this info directly.
4006 Reg = TRI->getFrameRegister(MF);
4007 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4008 // If byval argument ofset is not recorded then ignore this.
4013 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4014 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4015 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4016 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4017 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4024 // Check if ValueMap has reg number.
4025 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4026 if (VMI != FuncInfo.ValueMap.end())
4030 if (!Reg && N.getNode()) {
4031 // Check if frame index is available.
4032 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4033 if (FrameIndexSDNode *FINode =
4034 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4035 Reg = TRI->getFrameRegister(MF);
4036 Offset = FINode->getIndex();
4043 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4044 TII->get(TargetOpcode::DBG_VALUE))
4045 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4046 FuncInfo.ArgDbgValues.push_back(&*MIB);
4050 // VisualStudio defines setjmp as _setjmp
4051 #if defined(_MSC_VER) && defined(setjmp) && \
4052 !defined(setjmp_undefined_for_msvc)
4053 # pragma push_macro("setjmp")
4055 # define setjmp_undefined_for_msvc
4058 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4059 /// we want to emit this as a call to a named external function, return the name
4060 /// otherwise lower it and return null.
4062 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4063 DebugLoc dl = getCurDebugLoc();
4066 switch (Intrinsic) {
4068 // By default, turn this into a target intrinsic node.
4069 visitTargetIntrinsic(I, Intrinsic);
4071 case Intrinsic::vastart: visitVAStart(I); return 0;
4072 case Intrinsic::vaend: visitVAEnd(I); return 0;
4073 case Intrinsic::vacopy: visitVACopy(I); return 0;
4074 case Intrinsic::returnaddress:
4075 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4076 getValue(I.getArgOperand(0))));
4078 case Intrinsic::frameaddress:
4079 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4080 getValue(I.getArgOperand(0))));
4082 case Intrinsic::setjmp:
4083 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4084 case Intrinsic::longjmp:
4085 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4086 case Intrinsic::memcpy: {
4087 // Assert for address < 256 since we support only user defined address
4089 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4091 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4093 "Unknown address space");
4094 SDValue Op1 = getValue(I.getArgOperand(0));
4095 SDValue Op2 = getValue(I.getArgOperand(1));
4096 SDValue Op3 = getValue(I.getArgOperand(2));
4097 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4098 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4099 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4100 MachinePointerInfo(I.getArgOperand(0)),
4101 MachinePointerInfo(I.getArgOperand(1))));
4104 case Intrinsic::memset: {
4105 // Assert for address < 256 since we support only user defined address
4107 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4109 "Unknown address space");
4110 SDValue Op1 = getValue(I.getArgOperand(0));
4111 SDValue Op2 = getValue(I.getArgOperand(1));
4112 SDValue Op3 = getValue(I.getArgOperand(2));
4113 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4114 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4115 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4116 MachinePointerInfo(I.getArgOperand(0))));
4119 case Intrinsic::memmove: {
4120 // Assert for address < 256 since we support only user defined address
4122 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4124 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4126 "Unknown address space");
4127 SDValue Op1 = getValue(I.getArgOperand(0));
4128 SDValue Op2 = getValue(I.getArgOperand(1));
4129 SDValue Op3 = getValue(I.getArgOperand(2));
4130 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4131 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4132 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4133 MachinePointerInfo(I.getArgOperand(0)),
4134 MachinePointerInfo(I.getArgOperand(1))));
4137 case Intrinsic::dbg_declare: {
4138 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4139 MDNode *Variable = DI.getVariable();
4140 const Value *Address = DI.getAddress();
4141 if (!Address || !DIVariable(DI.getVariable()).Verify())
4144 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4145 // but do not always have a corresponding SDNode built. The SDNodeOrder
4146 // absolute, but not relative, values are different depending on whether
4147 // debug info exists.
4150 // Check if address has undef value.
4151 if (isa<UndefValue>(Address) ||
4152 (Address->use_empty() && !isa<Argument>(Address))) {
4154 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4155 0, dl, SDNodeOrder);
4156 DAG.AddDbgValue(SDV, 0, false);
4160 SDValue &N = NodeMap[Address];
4161 if (!N.getNode() && isa<Argument>(Address))
4162 // Check unused arguments map.
4163 N = UnusedArgNodeMap[Address];
4166 // Parameters are handled specially.
4168 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4169 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4170 Address = BCI->getOperand(0);
4171 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4173 if (isParameter && !AI) {
4174 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4176 // Byval parameter. We have a frame index at this point.
4177 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4178 0, dl, SDNodeOrder);
4180 // Can't do anything with other non-AI cases yet. This might be a
4181 // parameter of a callee function that got inlined, for example.
4184 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4185 0, dl, SDNodeOrder);
4187 // Can't do anything with other non-AI cases yet.
4189 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4191 // If Address is an argument then try to emit its dbg value using
4192 // virtual register info from the FuncInfo.ValueMap.
4193 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4194 // If variable is pinned by a alloca in dominating bb then
4195 // use StaticAllocaMap.
4196 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4197 if (AI->getParent() != DI.getParent()) {
4198 DenseMap<const AllocaInst*, int>::iterator SI =
4199 FuncInfo.StaticAllocaMap.find(AI);
4200 if (SI != FuncInfo.StaticAllocaMap.end()) {
4201 SDV = DAG.getDbgValue(Variable, SI->second,
4202 0, dl, SDNodeOrder);
4203 DAG.AddDbgValue(SDV, 0, false);
4208 // Otherwise add undef to help track missing debug info.
4209 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4210 0, dl, SDNodeOrder);
4211 DAG.AddDbgValue(SDV, 0, false);
4216 case Intrinsic::dbg_value: {
4217 const DbgValueInst &DI = cast<DbgValueInst>(I);
4218 if (!DIVariable(DI.getVariable()).Verify())
4221 MDNode *Variable = DI.getVariable();
4222 uint64_t Offset = DI.getOffset();
4223 const Value *V = DI.getValue();
4227 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4228 // but do not always have a corresponding SDNode built. The SDNodeOrder
4229 // absolute, but not relative, values are different depending on whether
4230 // debug info exists.
4233 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4234 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4235 DAG.AddDbgValue(SDV, 0, false);
4237 // Do not use getValue() in here; we don't want to generate code at
4238 // this point if it hasn't been done yet.
4239 SDValue N = NodeMap[V];
4240 if (!N.getNode() && isa<Argument>(V))
4241 // Check unused arguments map.
4242 N = UnusedArgNodeMap[V];
4244 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4245 SDV = DAG.getDbgValue(Variable, N.getNode(),
4246 N.getResNo(), Offset, dl, SDNodeOrder);
4247 DAG.AddDbgValue(SDV, N.getNode(), false);
4249 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4250 // Do not call getValue(V) yet, as we don't want to generate code.
4251 // Remember it for later.
4252 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4253 DanglingDebugInfoMap[V] = DDI;
4255 // We may expand this to cover more cases. One case where we have no
4256 // data available is an unreferenced parameter; we need this fallback.
4257 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
4258 Offset, dl, SDNodeOrder);
4259 DAG.AddDbgValue(SDV, 0, false);
4263 // Build a debug info table entry.
4264 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4265 V = BCI->getOperand(0);
4266 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4267 // Don't handle byval struct arguments or VLAs, for example.
4270 DenseMap<const AllocaInst*, int>::iterator SI =
4271 FuncInfo.StaticAllocaMap.find(AI);
4272 if (SI == FuncInfo.StaticAllocaMap.end())
4274 int FI = SI->second;
4276 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4277 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4278 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4281 case Intrinsic::eh_exception: {
4282 // Insert the EXCEPTIONADDR instruction.
4283 assert(FuncInfo.MBB->isLandingPad() &&
4284 "Call to eh.exception not in landing pad!");
4285 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4287 Ops[0] = DAG.getRoot();
4288 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4290 DAG.setRoot(Op.getValue(1));
4294 case Intrinsic::eh_selector: {
4295 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4296 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4297 if (CallMBB->isLandingPad())
4298 AddCatchInfo(I, &MMI, CallMBB);
4301 FuncInfo.CatchInfoLost.insert(&I);
4303 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4304 unsigned Reg = TLI.getExceptionSelectorRegister();
4305 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4308 // Insert the EHSELECTION instruction.
4309 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4311 Ops[0] = getValue(I.getArgOperand(0));
4313 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4314 DAG.setRoot(Op.getValue(1));
4315 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4319 case Intrinsic::eh_typeid_for: {
4320 // Find the type id for the given typeinfo.
4321 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4322 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4323 Res = DAG.getConstant(TypeID, MVT::i32);
4328 case Intrinsic::eh_return_i32:
4329 case Intrinsic::eh_return_i64:
4330 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4331 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4334 getValue(I.getArgOperand(0)),
4335 getValue(I.getArgOperand(1))));
4337 case Intrinsic::eh_unwind_init:
4338 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4340 case Intrinsic::eh_dwarf_cfa: {
4341 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4342 TLI.getPointerTy());
4343 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4345 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4346 TLI.getPointerTy()),
4348 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4350 DAG.getConstant(0, TLI.getPointerTy()));
4351 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4355 case Intrinsic::eh_sjlj_callsite: {
4356 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4357 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4358 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4359 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4361 MMI.setCurrentCallSite(CI->getZExtValue());
4364 case Intrinsic::eh_sjlj_setjmp: {
4365 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4366 getValue(I.getArgOperand(0))));
4369 case Intrinsic::eh_sjlj_longjmp: {
4370 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4371 getRoot(), getValue(I.getArgOperand(0))));
4374 case Intrinsic::eh_sjlj_dispatch_setup: {
4375 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4376 getRoot(), getValue(I.getArgOperand(0))));
4380 case Intrinsic::x86_mmx_pslli_w:
4381 case Intrinsic::x86_mmx_pslli_d:
4382 case Intrinsic::x86_mmx_pslli_q:
4383 case Intrinsic::x86_mmx_psrli_w:
4384 case Intrinsic::x86_mmx_psrli_d:
4385 case Intrinsic::x86_mmx_psrli_q:
4386 case Intrinsic::x86_mmx_psrai_w:
4387 case Intrinsic::x86_mmx_psrai_d: {
4388 SDValue ShAmt = getValue(I.getArgOperand(1));
4389 if (isa<ConstantSDNode>(ShAmt)) {
4390 visitTargetIntrinsic(I, Intrinsic);
4393 unsigned NewIntrinsic = 0;
4394 EVT ShAmtVT = MVT::v2i32;
4395 switch (Intrinsic) {
4396 case Intrinsic::x86_mmx_pslli_w:
4397 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4399 case Intrinsic::x86_mmx_pslli_d:
4400 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4402 case Intrinsic::x86_mmx_pslli_q:
4403 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4405 case Intrinsic::x86_mmx_psrli_w:
4406 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4408 case Intrinsic::x86_mmx_psrli_d:
4409 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4411 case Intrinsic::x86_mmx_psrli_q:
4412 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4414 case Intrinsic::x86_mmx_psrai_w:
4415 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4417 case Intrinsic::x86_mmx_psrai_d:
4418 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4420 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4423 // The vector shift intrinsics with scalars uses 32b shift amounts but
4424 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4426 // We must do this early because v2i32 is not a legal type.
4427 DebugLoc dl = getCurDebugLoc();
4430 ShOps[1] = DAG.getConstant(0, MVT::i32);
4431 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4432 EVT DestVT = TLI.getValueType(I.getType());
4433 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, DestVT, ShAmt);
4434 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4435 DAG.getConstant(NewIntrinsic, MVT::i32),
4436 getValue(I.getArgOperand(0)), ShAmt);
4440 case Intrinsic::convertff:
4441 case Intrinsic::convertfsi:
4442 case Intrinsic::convertfui:
4443 case Intrinsic::convertsif:
4444 case Intrinsic::convertuif:
4445 case Intrinsic::convertss:
4446 case Intrinsic::convertsu:
4447 case Intrinsic::convertus:
4448 case Intrinsic::convertuu: {
4449 ISD::CvtCode Code = ISD::CVT_INVALID;
4450 switch (Intrinsic) {
4451 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4452 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4453 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4454 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4455 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4456 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4457 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4458 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4459 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4461 EVT DestVT = TLI.getValueType(I.getType());
4462 const Value *Op1 = I.getArgOperand(0);
4463 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4464 DAG.getValueType(DestVT),
4465 DAG.getValueType(getValue(Op1).getValueType()),
4466 getValue(I.getArgOperand(1)),
4467 getValue(I.getArgOperand(2)),
4472 case Intrinsic::sqrt:
4473 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4474 getValue(I.getArgOperand(0)).getValueType(),
4475 getValue(I.getArgOperand(0))));
4477 case Intrinsic::powi:
4478 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4479 getValue(I.getArgOperand(1)), DAG));
4481 case Intrinsic::sin:
4482 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4483 getValue(I.getArgOperand(0)).getValueType(),
4484 getValue(I.getArgOperand(0))));
4486 case Intrinsic::cos:
4487 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4488 getValue(I.getArgOperand(0)).getValueType(),
4489 getValue(I.getArgOperand(0))));
4491 case Intrinsic::log:
4494 case Intrinsic::log2:
4497 case Intrinsic::log10:
4500 case Intrinsic::exp:
4503 case Intrinsic::exp2:
4506 case Intrinsic::pow:
4509 case Intrinsic::convert_to_fp16:
4510 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4511 MVT::i16, getValue(I.getArgOperand(0))));
4513 case Intrinsic::convert_from_fp16:
4514 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4515 MVT::f32, getValue(I.getArgOperand(0))));
4517 case Intrinsic::pcmarker: {
4518 SDValue Tmp = getValue(I.getArgOperand(0));
4519 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4522 case Intrinsic::readcyclecounter: {
4523 SDValue Op = getRoot();
4524 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4525 DAG.getVTList(MVT::i64, MVT::Other),
4528 DAG.setRoot(Res.getValue(1));
4531 case Intrinsic::bswap:
4532 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4533 getValue(I.getArgOperand(0)).getValueType(),
4534 getValue(I.getArgOperand(0))));
4536 case Intrinsic::cttz: {
4537 SDValue Arg = getValue(I.getArgOperand(0));
4538 EVT Ty = Arg.getValueType();
4539 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4542 case Intrinsic::ctlz: {
4543 SDValue Arg = getValue(I.getArgOperand(0));
4544 EVT Ty = Arg.getValueType();
4545 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4548 case Intrinsic::ctpop: {
4549 SDValue Arg = getValue(I.getArgOperand(0));
4550 EVT Ty = Arg.getValueType();
4551 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4554 case Intrinsic::stacksave: {
4555 SDValue Op = getRoot();
4556 Res = DAG.getNode(ISD::STACKSAVE, dl,
4557 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4559 DAG.setRoot(Res.getValue(1));
4562 case Intrinsic::stackrestore: {
4563 Res = getValue(I.getArgOperand(0));
4564 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4567 case Intrinsic::stackprotector: {
4568 // Emit code into the DAG to store the stack guard onto the stack.
4569 MachineFunction &MF = DAG.getMachineFunction();
4570 MachineFrameInfo *MFI = MF.getFrameInfo();
4571 EVT PtrTy = TLI.getPointerTy();
4573 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4574 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4576 int FI = FuncInfo.StaticAllocaMap[Slot];
4577 MFI->setStackProtectorIndex(FI);
4579 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4581 // Store the stack protector onto the stack.
4582 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4583 MachinePointerInfo::getFixedStack(FI),
4589 case Intrinsic::objectsize: {
4590 // If we don't know by now, we're never going to know.
4591 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4593 assert(CI && "Non-constant type in __builtin_object_size?");
4595 SDValue Arg = getValue(I.getCalledValue());
4596 EVT Ty = Arg.getValueType();
4599 Res = DAG.getConstant(-1ULL, Ty);
4601 Res = DAG.getConstant(0, Ty);
4606 case Intrinsic::var_annotation:
4607 // Discard annotate attributes
4610 case Intrinsic::init_trampoline: {
4611 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4615 Ops[1] = getValue(I.getArgOperand(0));
4616 Ops[2] = getValue(I.getArgOperand(1));
4617 Ops[3] = getValue(I.getArgOperand(2));
4618 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4619 Ops[5] = DAG.getSrcValue(F);
4621 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4622 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4626 DAG.setRoot(Res.getValue(1));
4629 case Intrinsic::gcroot:
4631 const Value *Alloca = I.getArgOperand(0);
4632 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4634 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4635 GFI->addStackRoot(FI->getIndex(), TypeMap);
4638 case Intrinsic::gcread:
4639 case Intrinsic::gcwrite:
4640 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4642 case Intrinsic::flt_rounds:
4643 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4645 case Intrinsic::trap:
4646 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4648 case Intrinsic::uadd_with_overflow:
4649 return implVisitAluOverflow(I, ISD::UADDO);
4650 case Intrinsic::sadd_with_overflow:
4651 return implVisitAluOverflow(I, ISD::SADDO);
4652 case Intrinsic::usub_with_overflow:
4653 return implVisitAluOverflow(I, ISD::USUBO);
4654 case Intrinsic::ssub_with_overflow:
4655 return implVisitAluOverflow(I, ISD::SSUBO);
4656 case Intrinsic::umul_with_overflow:
4657 return implVisitAluOverflow(I, ISD::UMULO);
4658 case Intrinsic::smul_with_overflow:
4659 return implVisitAluOverflow(I, ISD::SMULO);
4661 case Intrinsic::prefetch: {
4663 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4665 Ops[1] = getValue(I.getArgOperand(0));
4666 Ops[2] = getValue(I.getArgOperand(1));
4667 Ops[3] = getValue(I.getArgOperand(2));
4668 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4669 DAG.getVTList(MVT::Other),
4671 EVT::getIntegerVT(*Context, 8),
4672 MachinePointerInfo(I.getArgOperand(0)),
4674 false, /* volatile */
4676 rw==1)); /* write */
4679 case Intrinsic::memory_barrier: {
4682 for (int x = 1; x < 6; ++x)
4683 Ops[x] = getValue(I.getArgOperand(x - 1));
4685 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4688 case Intrinsic::atomic_cmp_swap: {
4689 SDValue Root = getRoot();
4691 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4692 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4694 getValue(I.getArgOperand(0)),
4695 getValue(I.getArgOperand(1)),
4696 getValue(I.getArgOperand(2)),
4697 MachinePointerInfo(I.getArgOperand(0)));
4699 DAG.setRoot(L.getValue(1));
4702 case Intrinsic::atomic_load_add:
4703 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4704 case Intrinsic::atomic_load_sub:
4705 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4706 case Intrinsic::atomic_load_or:
4707 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4708 case Intrinsic::atomic_load_xor:
4709 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4710 case Intrinsic::atomic_load_and:
4711 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4712 case Intrinsic::atomic_load_nand:
4713 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4714 case Intrinsic::atomic_load_max:
4715 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4716 case Intrinsic::atomic_load_min:
4717 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4718 case Intrinsic::atomic_load_umin:
4719 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4720 case Intrinsic::atomic_load_umax:
4721 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4722 case Intrinsic::atomic_swap:
4723 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4725 case Intrinsic::invariant_start:
4726 case Intrinsic::lifetime_start:
4727 // Discard region information.
4728 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4730 case Intrinsic::invariant_end:
4731 case Intrinsic::lifetime_end:
4732 // Discard region information.
4737 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4739 MachineBasicBlock *LandingPad) {
4740 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4741 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4742 const Type *RetTy = FTy->getReturnType();
4743 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4744 MCSymbol *BeginLabel = 0;
4746 TargetLowering::ArgListTy Args;
4747 TargetLowering::ArgListEntry Entry;
4748 Args.reserve(CS.arg_size());
4750 // Check whether the function can return without sret-demotion.
4751 SmallVector<ISD::OutputArg, 4> Outs;
4752 SmallVector<uint64_t, 4> Offsets;
4753 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4754 Outs, TLI, &Offsets);
4756 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4757 FTy->isVarArg(), Outs, FTy->getContext());
4759 SDValue DemoteStackSlot;
4760 int DemoteStackIdx = -100;
4762 if (!CanLowerReturn) {
4763 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4764 FTy->getReturnType());
4765 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4766 FTy->getReturnType());
4767 MachineFunction &MF = DAG.getMachineFunction();
4768 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4769 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4771 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4772 Entry.Node = DemoteStackSlot;
4773 Entry.Ty = StackSlotPtrType;
4774 Entry.isSExt = false;
4775 Entry.isZExt = false;
4776 Entry.isInReg = false;
4777 Entry.isSRet = true;
4778 Entry.isNest = false;
4779 Entry.isByVal = false;
4780 Entry.Alignment = Align;
4781 Args.push_back(Entry);
4782 RetTy = Type::getVoidTy(FTy->getContext());
4785 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4787 SDValue ArgNode = getValue(*i);
4788 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4790 unsigned attrInd = i - CS.arg_begin() + 1;
4791 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4792 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4793 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4794 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4795 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4796 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4797 Entry.Alignment = CS.getParamAlignment(attrInd);
4798 Args.push_back(Entry);
4802 // Insert a label before the invoke call to mark the try range. This can be
4803 // used to detect deletion of the invoke via the MachineModuleInfo.
4804 BeginLabel = MMI.getContext().CreateTempSymbol();
4806 // For SjLj, keep track of which landing pads go with which invokes
4807 // so as to maintain the ordering of pads in the LSDA.
4808 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4809 if (CallSiteIndex) {
4810 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4811 // Now that the call site is handled, stop tracking it.
4812 MMI.setCurrentCallSite(0);
4815 // Both PendingLoads and PendingExports must be flushed here;
4816 // this call might not return.
4818 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4821 // Check if target-independent constraints permit a tail call here.
4822 // Target-dependent constraints are checked within TLI.LowerCallTo.
4824 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4827 // If there's a possibility that fast-isel has already selected some amount
4828 // of the current basic block, don't emit a tail call.
4829 if (isTailCall && EnableFastISel)
4832 std::pair<SDValue,SDValue> Result =
4833 TLI.LowerCallTo(getRoot(), RetTy,
4834 CS.paramHasAttr(0, Attribute::SExt),
4835 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4836 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4837 CS.getCallingConv(),
4839 !CS.getInstruction()->use_empty(),
4840 Callee, Args, DAG, getCurDebugLoc());
4841 assert((isTailCall || Result.second.getNode()) &&
4842 "Non-null chain expected with non-tail call!");
4843 assert((Result.second.getNode() || !Result.first.getNode()) &&
4844 "Null value expected with tail call!");
4845 if (Result.first.getNode()) {
4846 setValue(CS.getInstruction(), Result.first);
4847 } else if (!CanLowerReturn && Result.second.getNode()) {
4848 // The instruction result is the result of loading from the
4849 // hidden sret parameter.
4850 SmallVector<EVT, 1> PVTs;
4851 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4853 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4854 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4855 EVT PtrVT = PVTs[0];
4856 unsigned NumValues = Outs.size();
4857 SmallVector<SDValue, 4> Values(NumValues);
4858 SmallVector<SDValue, 4> Chains(NumValues);
4860 for (unsigned i = 0; i < NumValues; ++i) {
4861 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4863 DAG.getConstant(Offsets[i], PtrVT));
4864 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4866 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4869 Chains[i] = L.getValue(1);
4872 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4873 MVT::Other, &Chains[0], NumValues);
4874 PendingLoads.push_back(Chain);
4876 // Collect the legal value parts into potentially illegal values
4877 // that correspond to the original function's return values.
4878 SmallVector<EVT, 4> RetTys;
4879 RetTy = FTy->getReturnType();
4880 ComputeValueVTs(TLI, RetTy, RetTys);
4881 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4882 SmallVector<SDValue, 4> ReturnValues;
4883 unsigned CurReg = 0;
4884 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4886 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4887 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4889 SDValue ReturnValue =
4890 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4891 RegisterVT, VT, AssertOp);
4892 ReturnValues.push_back(ReturnValue);
4896 setValue(CS.getInstruction(),
4897 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4898 DAG.getVTList(&RetTys[0], RetTys.size()),
4899 &ReturnValues[0], ReturnValues.size()));
4903 // As a special case, a null chain means that a tail call has been emitted and
4904 // the DAG root is already updated.
4905 if (Result.second.getNode())
4906 DAG.setRoot(Result.second);
4911 // Insert a label at the end of the invoke call to mark the try range. This
4912 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4913 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4914 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4916 // Inform MachineModuleInfo of range.
4917 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4921 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4922 /// value is equal or not-equal to zero.
4923 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4924 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4926 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4927 if (IC->isEquality())
4928 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4929 if (C->isNullValue())
4931 // Unknown instruction.
4937 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4939 SelectionDAGBuilder &Builder) {
4941 // Check to see if this load can be trivially constant folded, e.g. if the
4942 // input is from a string literal.
4943 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4944 // Cast pointer to the type we really want to load.
4945 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4946 PointerType::getUnqual(LoadTy));
4948 if (const Constant *LoadCst =
4949 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4951 return Builder.getValue(LoadCst);
4954 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4955 // still constant memory, the input chain can be the entry node.
4957 bool ConstantMemory = false;
4959 // Do not serialize (non-volatile) loads of constant memory with anything.
4960 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4961 Root = Builder.DAG.getEntryNode();
4962 ConstantMemory = true;
4964 // Do not serialize non-volatile loads against each other.
4965 Root = Builder.DAG.getRoot();
4968 SDValue Ptr = Builder.getValue(PtrVal);
4969 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4970 Ptr, MachinePointerInfo(PtrVal),
4972 false /*nontemporal*/, 1 /* align=1 */);
4974 if (!ConstantMemory)
4975 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4980 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4981 /// If so, return true and lower it, otherwise return false and it will be
4982 /// lowered like a normal call.
4983 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4984 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4985 if (I.getNumArgOperands() != 3)
4988 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
4989 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4990 !I.getArgOperand(2)->getType()->isIntegerTy() ||
4991 !I.getType()->isIntegerTy())
4994 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
4996 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4997 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4998 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4999 bool ActuallyDoIt = true;
5002 switch (Size->getZExtValue()) {
5004 LoadVT = MVT::Other;
5006 ActuallyDoIt = false;
5010 LoadTy = Type::getInt16Ty(Size->getContext());
5014 LoadTy = Type::getInt32Ty(Size->getContext());
5018 LoadTy = Type::getInt64Ty(Size->getContext());
5022 LoadVT = MVT::v4i32;
5023 LoadTy = Type::getInt32Ty(Size->getContext());
5024 LoadTy = VectorType::get(LoadTy, 4);
5029 // This turns into unaligned loads. We only do this if the target natively
5030 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5031 // we'll only produce a small number of byte loads.
5033 // Require that we can find a legal MVT, and only do this if the target
5034 // supports unaligned loads of that type. Expanding into byte loads would
5036 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5037 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5038 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5039 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5040 ActuallyDoIt = false;
5044 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5045 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5047 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5049 EVT CallVT = TLI.getValueType(I.getType(), true);
5050 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5060 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5061 // Handle inline assembly differently.
5062 if (isa<InlineAsm>(I.getCalledValue())) {
5067 // See if any floating point values are being passed to this function. This is
5068 // used to emit an undefined reference to fltused on Windows.
5069 const FunctionType *FT =
5070 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5071 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5072 if (FT->isVarArg() &&
5073 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5074 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5075 const Type* T = I.getArgOperand(i)->getType();
5076 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5078 if (!i->isFloatingPointTy()) continue;
5079 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5085 const char *RenameFn = 0;
5086 if (Function *F = I.getCalledFunction()) {
5087 if (F->isDeclaration()) {
5088 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5089 if (unsigned IID = II->getIntrinsicID(F)) {
5090 RenameFn = visitIntrinsicCall(I, IID);
5095 if (unsigned IID = F->getIntrinsicID()) {
5096 RenameFn = visitIntrinsicCall(I, IID);
5102 // Check for well-known libc/libm calls. If the function is internal, it
5103 // can't be a library call.
5104 if (!F->hasLocalLinkage() && F->hasName()) {
5105 StringRef Name = F->getName();
5106 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5107 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5108 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5109 I.getType() == I.getArgOperand(0)->getType() &&
5110 I.getType() == I.getArgOperand(1)->getType()) {
5111 SDValue LHS = getValue(I.getArgOperand(0));
5112 SDValue RHS = getValue(I.getArgOperand(1));
5113 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5114 LHS.getValueType(), LHS, RHS));
5117 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5118 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5119 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5120 I.getType() == I.getArgOperand(0)->getType()) {
5121 SDValue Tmp = getValue(I.getArgOperand(0));
5122 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5123 Tmp.getValueType(), Tmp));
5126 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5127 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5128 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5129 I.getType() == I.getArgOperand(0)->getType() &&
5130 I.onlyReadsMemory()) {
5131 SDValue Tmp = getValue(I.getArgOperand(0));
5132 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5133 Tmp.getValueType(), Tmp));
5136 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5137 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5138 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5139 I.getType() == I.getArgOperand(0)->getType() &&
5140 I.onlyReadsMemory()) {
5141 SDValue Tmp = getValue(I.getArgOperand(0));
5142 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5143 Tmp.getValueType(), Tmp));
5146 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5147 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5148 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5149 I.getType() == I.getArgOperand(0)->getType() &&
5150 I.onlyReadsMemory()) {
5151 SDValue Tmp = getValue(I.getArgOperand(0));
5152 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5153 Tmp.getValueType(), Tmp));
5156 } else if (Name == "memcmp") {
5157 if (visitMemCmpCall(I))
5165 Callee = getValue(I.getCalledValue());
5167 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5169 // Check if we can potentially perform a tail call. More detailed checking is
5170 // be done within LowerCallTo, after more information about the call is known.
5171 LowerCallTo(&I, Callee, I.isTailCall());
5176 /// AsmOperandInfo - This contains information for each constraint that we are
5178 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5179 public TargetLowering::AsmOperandInfo {
5181 /// CallOperand - If this is the result output operand or a clobber
5182 /// this is null, otherwise it is the incoming operand to the CallInst.
5183 /// This gets modified as the asm is processed.
5184 SDValue CallOperand;
5186 /// AssignedRegs - If this is a register or register class operand, this
5187 /// contains the set of register corresponding to the operand.
5188 RegsForValue AssignedRegs;
5190 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5191 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5194 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5195 /// busy in OutputRegs/InputRegs.
5196 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5197 std::set<unsigned> &OutputRegs,
5198 std::set<unsigned> &InputRegs,
5199 const TargetRegisterInfo &TRI) const {
5201 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5202 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5205 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5206 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5210 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5211 /// corresponds to. If there is no Value* for this operand, it returns
5213 EVT getCallOperandValEVT(LLVMContext &Context,
5214 const TargetLowering &TLI,
5215 const TargetData *TD) const {
5216 if (CallOperandVal == 0) return MVT::Other;
5218 if (isa<BasicBlock>(CallOperandVal))
5219 return TLI.getPointerTy();
5221 const llvm::Type *OpTy = CallOperandVal->getType();
5223 // If this is an indirect operand, the operand is a pointer to the
5226 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5228 report_fatal_error("Indirect operand for inline asm not a pointer!");
5229 OpTy = PtrTy->getElementType();
5232 // If OpTy is not a single value, it may be a struct/union that we
5233 // can tile with integers.
5234 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5235 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5244 OpTy = IntegerType::get(Context, BitSize);
5249 return TLI.getValueType(OpTy, true);
5253 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5255 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5256 const TargetRegisterInfo &TRI) {
5257 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5259 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5260 for (; *Aliases; ++Aliases)
5261 Regs.insert(*Aliases);
5265 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5267 } // end llvm namespace.
5269 /// isAllocatableRegister - If the specified register is safe to allocate,
5270 /// i.e. it isn't a stack pointer or some other special register, return the
5271 /// register class for the register. Otherwise, return null.
5272 static const TargetRegisterClass *
5273 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5274 const TargetLowering &TLI,
5275 const TargetRegisterInfo *TRI) {
5276 EVT FoundVT = MVT::Other;
5277 const TargetRegisterClass *FoundRC = 0;
5278 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5279 E = TRI->regclass_end(); RCI != E; ++RCI) {
5280 EVT ThisVT = MVT::Other;
5282 const TargetRegisterClass *RC = *RCI;
5283 // If none of the value types for this register class are valid, we
5284 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5285 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5287 if (TLI.isTypeLegal(*I)) {
5288 // If we have already found this register in a different register class,
5289 // choose the one with the largest VT specified. For example, on
5290 // PowerPC, we favor f64 register classes over f32.
5291 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5298 if (ThisVT == MVT::Other) continue;
5300 // NOTE: This isn't ideal. In particular, this might allocate the
5301 // frame pointer in functions that need it (due to them not being taken
5302 // out of allocation, because a variable sized allocation hasn't been seen
5303 // yet). This is a slight code pessimization, but should still work.
5304 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5305 E = RC->allocation_order_end(MF); I != E; ++I)
5307 // We found a matching register class. Keep looking at others in case
5308 // we find one with larger registers that this physreg is also in.
5317 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5318 /// specified operand. We prefer to assign virtual registers, to allow the
5319 /// register allocator to handle the assignment process. However, if the asm
5320 /// uses features that we can't model on machineinstrs, we have SDISel do the
5321 /// allocation. This produces generally horrible, but correct, code.
5323 /// OpInfo describes the operand.
5324 /// Input and OutputRegs are the set of already allocated physical registers.
5326 void SelectionDAGBuilder::
5327 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5328 std::set<unsigned> &OutputRegs,
5329 std::set<unsigned> &InputRegs) {
5330 LLVMContext &Context = FuncInfo.Fn->getContext();
5332 // Compute whether this value requires an input register, an output register,
5334 bool isOutReg = false;
5335 bool isInReg = false;
5336 switch (OpInfo.Type) {
5337 case InlineAsm::isOutput:
5340 // If there is an input constraint that matches this, we need to reserve
5341 // the input register so no other inputs allocate to it.
5342 isInReg = OpInfo.hasMatchingInput();
5344 case InlineAsm::isInput:
5348 case InlineAsm::isClobber:
5355 MachineFunction &MF = DAG.getMachineFunction();
5356 SmallVector<unsigned, 4> Regs;
5358 // If this is a constraint for a single physreg, or a constraint for a
5359 // register class, find it.
5360 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5361 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5362 OpInfo.ConstraintVT);
5364 unsigned NumRegs = 1;
5365 if (OpInfo.ConstraintVT != MVT::Other) {
5366 // If this is a FP input in an integer register (or visa versa) insert a bit
5367 // cast of the input value. More generally, handle any case where the input
5368 // value disagrees with the register class we plan to stick this in.
5369 if (OpInfo.Type == InlineAsm::isInput &&
5370 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5371 // Try to convert to the first EVT that the reg class contains. If the
5372 // types are identical size, use a bitcast to convert (e.g. two differing
5374 EVT RegVT = *PhysReg.second->vt_begin();
5375 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5376 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5377 RegVT, OpInfo.CallOperand);
5378 OpInfo.ConstraintVT = RegVT;
5379 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5380 // If the input is a FP value and we want it in FP registers, do a
5381 // bitcast to the corresponding integer type. This turns an f64 value
5382 // into i64, which can be passed with two i32 values on a 32-bit
5384 RegVT = EVT::getIntegerVT(Context,
5385 OpInfo.ConstraintVT.getSizeInBits());
5386 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5387 RegVT, OpInfo.CallOperand);
5388 OpInfo.ConstraintVT = RegVT;
5392 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5396 EVT ValueVT = OpInfo.ConstraintVT;
5398 // If this is a constraint for a specific physical register, like {r17},
5400 if (unsigned AssignedReg = PhysReg.first) {
5401 const TargetRegisterClass *RC = PhysReg.second;
5402 if (OpInfo.ConstraintVT == MVT::Other)
5403 ValueVT = *RC->vt_begin();
5405 // Get the actual register value type. This is important, because the user
5406 // may have asked for (e.g.) the AX register in i32 type. We need to
5407 // remember that AX is actually i16 to get the right extension.
5408 RegVT = *RC->vt_begin();
5410 // This is a explicit reference to a physical register.
5411 Regs.push_back(AssignedReg);
5413 // If this is an expanded reference, add the rest of the regs to Regs.
5415 TargetRegisterClass::iterator I = RC->begin();
5416 for (; *I != AssignedReg; ++I)
5417 assert(I != RC->end() && "Didn't find reg!");
5419 // Already added the first reg.
5421 for (; NumRegs; --NumRegs, ++I) {
5422 assert(I != RC->end() && "Ran out of registers to allocate!");
5427 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5428 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5429 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5433 // Otherwise, if this was a reference to an LLVM register class, create vregs
5434 // for this reference.
5435 if (const TargetRegisterClass *RC = PhysReg.second) {
5436 RegVT = *RC->vt_begin();
5437 if (OpInfo.ConstraintVT == MVT::Other)
5440 // Create the appropriate number of virtual registers.
5441 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5442 for (; NumRegs; --NumRegs)
5443 Regs.push_back(RegInfo.createVirtualRegister(RC));
5445 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5449 // This is a reference to a register class that doesn't directly correspond
5450 // to an LLVM register class. Allocate NumRegs consecutive, available,
5451 // registers from the class.
5452 std::vector<unsigned> RegClassRegs
5453 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5454 OpInfo.ConstraintVT);
5456 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5457 unsigned NumAllocated = 0;
5458 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5459 unsigned Reg = RegClassRegs[i];
5460 // See if this register is available.
5461 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5462 (isInReg && InputRegs.count(Reg))) { // Already used.
5463 // Make sure we find consecutive registers.
5468 // Check to see if this register is allocatable (i.e. don't give out the
5470 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5471 if (!RC) { // Couldn't allocate this register.
5472 // Reset NumAllocated to make sure we return consecutive registers.
5477 // Okay, this register is good, we can use it.
5480 // If we allocated enough consecutive registers, succeed.
5481 if (NumAllocated == NumRegs) {
5482 unsigned RegStart = (i-NumAllocated)+1;
5483 unsigned RegEnd = i+1;
5484 // Mark all of the allocated registers used.
5485 for (unsigned i = RegStart; i != RegEnd; ++i)
5486 Regs.push_back(RegClassRegs[i]);
5488 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5489 OpInfo.ConstraintVT);
5490 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5495 // Otherwise, we couldn't allocate enough registers for this.
5498 /// visitInlineAsm - Handle a call to an InlineAsm object.
5500 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5501 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5503 /// ConstraintOperands - Information about all of the constraints.
5504 SDISelAsmOperandInfoVector ConstraintOperands;
5506 std::set<unsigned> OutputRegs, InputRegs;
5508 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5509 bool hasMemory = false;
5511 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5512 unsigned ResNo = 0; // ResNo - The result number of the next output.
5513 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5514 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5515 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5517 EVT OpVT = MVT::Other;
5519 // Compute the value type for each operand.
5520 switch (OpInfo.Type) {
5521 case InlineAsm::isOutput:
5522 // Indirect outputs just consume an argument.
5523 if (OpInfo.isIndirect) {
5524 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5528 // The return value of the call is this value. As such, there is no
5529 // corresponding argument.
5530 assert(!CS.getType()->isVoidTy() &&
5532 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5533 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5535 assert(ResNo == 0 && "Asm only has one result!");
5536 OpVT = TLI.getValueType(CS.getType());
5540 case InlineAsm::isInput:
5541 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5543 case InlineAsm::isClobber:
5548 // If this is an input or an indirect output, process the call argument.
5549 // BasicBlocks are labels, currently appearing only in asm's.
5550 if (OpInfo.CallOperandVal) {
5551 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5552 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5554 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5557 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5560 OpInfo.ConstraintVT = OpVT;
5562 // Indirect operand accesses access memory.
5563 if (OpInfo.isIndirect)
5566 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5567 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5568 if (CType == TargetLowering::C_Memory) {
5576 SDValue Chain, Flag;
5578 // We won't need to flush pending loads if this asm doesn't touch
5579 // memory and is nonvolatile.
5580 if (hasMemory || IA->hasSideEffects())
5583 Chain = DAG.getRoot();
5585 // Second pass over the constraints: compute which constraint option to use
5586 // and assign registers to constraints that want a specific physreg.
5587 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5588 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5590 // If this is an output operand with a matching input operand, look up the
5591 // matching input. If their types mismatch, e.g. one is an integer, the
5592 // other is floating point, or their sizes are different, flag it as an
5594 if (OpInfo.hasMatchingInput()) {
5595 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5597 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5598 if ((OpInfo.ConstraintVT.isInteger() !=
5599 Input.ConstraintVT.isInteger()) ||
5600 (OpInfo.ConstraintVT.getSizeInBits() !=
5601 Input.ConstraintVT.getSizeInBits())) {
5602 report_fatal_error("Unsupported asm: input constraint"
5603 " with a matching output constraint of"
5604 " incompatible type!");
5606 Input.ConstraintVT = OpInfo.ConstraintVT;
5610 // Compute the constraint code and ConstraintType to use.
5611 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5613 // If this is a memory input, and if the operand is not indirect, do what we
5614 // need to to provide an address for the memory input.
5615 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5616 !OpInfo.isIndirect) {
5617 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5618 "Can only indirectify direct input operands!");
5620 // Memory operands really want the address of the value. If we don't have
5621 // an indirect input, put it in the constpool if we can, otherwise spill
5622 // it to a stack slot.
5624 // If the operand is a float, integer, or vector constant, spill to a
5625 // constant pool entry to get its address.
5626 const Value *OpVal = OpInfo.CallOperandVal;
5627 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5628 isa<ConstantVector>(OpVal)) {
5629 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5630 TLI.getPointerTy());
5632 // Otherwise, create a stack slot and emit a store to it before the
5634 const Type *Ty = OpVal->getType();
5635 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5636 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5637 MachineFunction &MF = DAG.getMachineFunction();
5638 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5639 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5640 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5641 OpInfo.CallOperand, StackSlot,
5642 MachinePointerInfo::getFixedStack(SSFI),
5644 OpInfo.CallOperand = StackSlot;
5647 // There is no longer a Value* corresponding to this operand.
5648 OpInfo.CallOperandVal = 0;
5650 // It is now an indirect operand.
5651 OpInfo.isIndirect = true;
5654 // If this constraint is for a specific register, allocate it before
5656 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5657 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5660 // Second pass - Loop over all of the operands, assigning virtual or physregs
5661 // to register class operands.
5662 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5663 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5665 // C_Register operands have already been allocated, Other/Memory don't need
5667 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5668 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5671 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5672 std::vector<SDValue> AsmNodeOperands;
5673 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5674 AsmNodeOperands.push_back(
5675 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5676 TLI.getPointerTy()));
5678 // If we have a !srcloc metadata node associated with it, we want to attach
5679 // this to the ultimately generated inline asm machineinstr. To do this, we
5680 // pass in the third operand as this (potentially null) inline asm MDNode.
5681 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5682 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5684 // Remember the AlignStack bit as operand 3.
5685 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0,
5688 // Loop over all of the inputs, copying the operand values into the
5689 // appropriate registers and processing the output regs.
5690 RegsForValue RetValRegs;
5692 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5693 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5695 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5696 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5698 switch (OpInfo.Type) {
5699 case InlineAsm::isOutput: {
5700 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5701 OpInfo.ConstraintType != TargetLowering::C_Register) {
5702 // Memory output, or 'other' output (e.g. 'X' constraint).
5703 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5705 // Add information to the INLINEASM node to know about this output.
5706 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5707 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5708 TLI.getPointerTy()));
5709 AsmNodeOperands.push_back(OpInfo.CallOperand);
5713 // Otherwise, this is a register or register class output.
5715 // Copy the output from the appropriate register. Find a register that
5717 if (OpInfo.AssignedRegs.Regs.empty())
5718 report_fatal_error("Couldn't allocate output reg for constraint '" +
5719 Twine(OpInfo.ConstraintCode) + "'!");
5721 // If this is an indirect operand, store through the pointer after the
5723 if (OpInfo.isIndirect) {
5724 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5725 OpInfo.CallOperandVal));
5727 // This is the result value of the call.
5728 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5729 // Concatenate this output onto the outputs list.
5730 RetValRegs.append(OpInfo.AssignedRegs);
5733 // Add information to the INLINEASM node to know that this register is
5735 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5736 InlineAsm::Kind_RegDefEarlyClobber :
5737 InlineAsm::Kind_RegDef,
5744 case InlineAsm::isInput: {
5745 SDValue InOperandVal = OpInfo.CallOperand;
5747 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5748 // If this is required to match an output register we have already set,
5749 // just use its register.
5750 unsigned OperandNo = OpInfo.getMatchedOperand();
5752 // Scan until we find the definition we already emitted of this operand.
5753 // When we find it, create a RegsForValue operand.
5754 unsigned CurOp = InlineAsm::Op_FirstOperand;
5755 for (; OperandNo; --OperandNo) {
5756 // Advance to the next operand.
5758 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5759 assert((InlineAsm::isRegDefKind(OpFlag) ||
5760 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5761 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5762 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5766 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5767 if (InlineAsm::isRegDefKind(OpFlag) ||
5768 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5769 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5770 if (OpInfo.isIndirect) {
5771 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5772 LLVMContext &Ctx = *DAG.getContext();
5773 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5774 " don't know how to handle tied "
5775 "indirect register inputs");
5778 RegsForValue MatchedRegs;
5779 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5780 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5781 MatchedRegs.RegVTs.push_back(RegVT);
5782 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5783 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5785 MatchedRegs.Regs.push_back
5786 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5788 // Use the produced MatchedRegs object to
5789 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5791 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5792 true, OpInfo.getMatchedOperand(),
5793 DAG, AsmNodeOperands);
5797 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5798 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5799 "Unexpected number of operands");
5800 // Add information to the INLINEASM node to know about this input.
5801 // See InlineAsm.h isUseOperandTiedToDef.
5802 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5803 OpInfo.getMatchedOperand());
5804 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5805 TLI.getPointerTy()));
5806 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5810 // Treat indirect 'X' constraint as memory.
5811 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5813 OpInfo.ConstraintType = TargetLowering::C_Memory;
5815 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5816 std::vector<SDValue> Ops;
5817 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5820 report_fatal_error("Invalid operand for inline asm constraint '" +
5821 Twine(OpInfo.ConstraintCode) + "'!");
5823 // Add information to the INLINEASM node to know about this input.
5824 unsigned ResOpType =
5825 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5826 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5827 TLI.getPointerTy()));
5828 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5832 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5833 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5834 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5835 "Memory operands expect pointer values");
5837 // Add information to the INLINEASM node to know about this input.
5838 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5839 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5840 TLI.getPointerTy()));
5841 AsmNodeOperands.push_back(InOperandVal);
5845 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5846 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5847 "Unknown constraint type!");
5848 assert(!OpInfo.isIndirect &&
5849 "Don't know how to handle indirect register inputs yet!");
5851 // Copy the input into the appropriate registers.
5852 if (OpInfo.AssignedRegs.Regs.empty() ||
5853 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5854 report_fatal_error("Couldn't allocate input reg for constraint '" +
5855 Twine(OpInfo.ConstraintCode) + "'!");
5857 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5860 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5861 DAG, AsmNodeOperands);
5864 case InlineAsm::isClobber: {
5865 // Add the clobbered value to the operand list, so that the register
5866 // allocator is aware that the physreg got clobbered.
5867 if (!OpInfo.AssignedRegs.Regs.empty())
5868 OpInfo.AssignedRegs.AddInlineAsmOperands(
5869 InlineAsm::Kind_RegDefEarlyClobber,
5877 // Finish up input operands. Set the input chain and add the flag last.
5878 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5879 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5881 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5882 DAG.getVTList(MVT::Other, MVT::Flag),
5883 &AsmNodeOperands[0], AsmNodeOperands.size());
5884 Flag = Chain.getValue(1);
5886 // If this asm returns a register value, copy the result from that register
5887 // and set it as the value of the call.
5888 if (!RetValRegs.Regs.empty()) {
5889 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5892 // FIXME: Why don't we do this for inline asms with MRVs?
5893 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5894 EVT ResultType = TLI.getValueType(CS.getType());
5896 // If any of the results of the inline asm is a vector, it may have the
5897 // wrong width/num elts. This can happen for register classes that can
5898 // contain multiple different value types. The preg or vreg allocated may
5899 // not have the same VT as was expected. Convert it to the right type
5900 // with bit_convert.
5901 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5902 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5905 } else if (ResultType != Val.getValueType() &&
5906 ResultType.isInteger() && Val.getValueType().isInteger()) {
5907 // If a result value was tied to an input value, the computed result may
5908 // have a wider width than the expected result. Extract the relevant
5910 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5913 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5916 setValue(CS.getInstruction(), Val);
5917 // Don't need to use this as a chain in this case.
5918 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5922 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5924 // Process indirect outputs, first output all of the flagged copies out of
5926 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5927 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5928 const Value *Ptr = IndirectStoresToEmit[i].second;
5929 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5931 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5934 // Emit the non-flagged stores from the physregs.
5935 SmallVector<SDValue, 8> OutChains;
5936 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5937 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5938 StoresToEmit[i].first,
5939 getValue(StoresToEmit[i].second),
5940 MachinePointerInfo(StoresToEmit[i].second),
5942 OutChains.push_back(Val);
5945 if (!OutChains.empty())
5946 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5947 &OutChains[0], OutChains.size());
5952 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5953 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5954 MVT::Other, getRoot(),
5955 getValue(I.getArgOperand(0)),
5956 DAG.getSrcValue(I.getArgOperand(0))));
5959 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5960 const TargetData &TD = *TLI.getTargetData();
5961 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5962 getRoot(), getValue(I.getOperand(0)),
5963 DAG.getSrcValue(I.getOperand(0)),
5964 TD.getABITypeAlignment(I.getType()));
5966 DAG.setRoot(V.getValue(1));
5969 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5970 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5971 MVT::Other, getRoot(),
5972 getValue(I.getArgOperand(0)),
5973 DAG.getSrcValue(I.getArgOperand(0))));
5976 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5977 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5978 MVT::Other, getRoot(),
5979 getValue(I.getArgOperand(0)),
5980 getValue(I.getArgOperand(1)),
5981 DAG.getSrcValue(I.getArgOperand(0)),
5982 DAG.getSrcValue(I.getArgOperand(1))));
5985 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5986 /// implementation, which just calls LowerCall.
5987 /// FIXME: When all targets are
5988 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5989 std::pair<SDValue, SDValue>
5990 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5991 bool RetSExt, bool RetZExt, bool isVarArg,
5992 bool isInreg, unsigned NumFixedArgs,
5993 CallingConv::ID CallConv, bool isTailCall,
5994 bool isReturnValueUsed,
5996 ArgListTy &Args, SelectionDAG &DAG,
5997 DebugLoc dl) const {
5998 // Handle all of the outgoing arguments.
5999 SmallVector<ISD::OutputArg, 32> Outs;
6000 SmallVector<SDValue, 32> OutVals;
6001 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6002 SmallVector<EVT, 4> ValueVTs;
6003 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6004 for (unsigned Value = 0, NumValues = ValueVTs.size();
6005 Value != NumValues; ++Value) {
6006 EVT VT = ValueVTs[Value];
6007 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6008 SDValue Op = SDValue(Args[i].Node.getNode(),
6009 Args[i].Node.getResNo() + Value);
6010 ISD::ArgFlagsTy Flags;
6011 unsigned OriginalAlignment =
6012 getTargetData()->getABITypeAlignment(ArgTy);
6018 if (Args[i].isInReg)
6022 if (Args[i].isByVal) {
6024 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6025 const Type *ElementTy = Ty->getElementType();
6026 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6027 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6028 // For ByVal, alignment should come from FE. BE will guess if this
6029 // info is not there but there are cases it cannot get right.
6030 if (Args[i].Alignment)
6031 FrameAlign = Args[i].Alignment;
6032 Flags.setByValAlign(FrameAlign);
6033 Flags.setByValSize(FrameSize);
6037 Flags.setOrigAlign(OriginalAlignment);
6039 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6040 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6041 SmallVector<SDValue, 4> Parts(NumParts);
6042 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6045 ExtendKind = ISD::SIGN_EXTEND;
6046 else if (Args[i].isZExt)
6047 ExtendKind = ISD::ZERO_EXTEND;
6049 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6050 PartVT, ExtendKind);
6052 for (unsigned j = 0; j != NumParts; ++j) {
6053 // if it isn't first piece, alignment must be 1
6054 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6056 if (NumParts > 1 && j == 0)
6057 MyFlags.Flags.setSplit();
6059 MyFlags.Flags.setOrigAlign(1);
6061 Outs.push_back(MyFlags);
6062 OutVals.push_back(Parts[j]);
6067 // Handle the incoming return values from the call.
6068 SmallVector<ISD::InputArg, 32> Ins;
6069 SmallVector<EVT, 4> RetTys;
6070 ComputeValueVTs(*this, RetTy, RetTys);
6071 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6073 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6074 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6075 for (unsigned i = 0; i != NumRegs; ++i) {
6076 ISD::InputArg MyFlags;
6077 MyFlags.VT = RegisterVT.getSimpleVT();
6078 MyFlags.Used = isReturnValueUsed;
6080 MyFlags.Flags.setSExt();
6082 MyFlags.Flags.setZExt();
6084 MyFlags.Flags.setInReg();
6085 Ins.push_back(MyFlags);
6089 SmallVector<SDValue, 4> InVals;
6090 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6091 Outs, OutVals, Ins, dl, DAG, InVals);
6093 // Verify that the target's LowerCall behaved as expected.
6094 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6095 "LowerCall didn't return a valid chain!");
6096 assert((!isTailCall || InVals.empty()) &&
6097 "LowerCall emitted a return value for a tail call!");
6098 assert((isTailCall || InVals.size() == Ins.size()) &&
6099 "LowerCall didn't emit the correct number of values!");
6101 // For a tail call, the return value is merely live-out and there aren't
6102 // any nodes in the DAG representing it. Return a special value to
6103 // indicate that a tail call has been emitted and no more Instructions
6104 // should be processed in the current block.
6107 return std::make_pair(SDValue(), SDValue());
6110 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6111 assert(InVals[i].getNode() &&
6112 "LowerCall emitted a null value!");
6113 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6114 "LowerCall emitted a value with the wrong type!");
6117 // Collect the legal value parts into potentially illegal values
6118 // that correspond to the original function's return values.
6119 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6121 AssertOp = ISD::AssertSext;
6123 AssertOp = ISD::AssertZext;
6124 SmallVector<SDValue, 4> ReturnValues;
6125 unsigned CurReg = 0;
6126 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6128 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6129 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6131 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6132 NumRegs, RegisterVT, VT,
6137 // For a function returning void, there is no return value. We can't create
6138 // such a node, so we just return a null return value in that case. In
6139 // that case, nothing will actualy look at the value.
6140 if (ReturnValues.empty())
6141 return std::make_pair(SDValue(), Chain);
6143 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6144 DAG.getVTList(&RetTys[0], RetTys.size()),
6145 &ReturnValues[0], ReturnValues.size());
6146 return std::make_pair(Res, Chain);
6149 void TargetLowering::LowerOperationWrapper(SDNode *N,
6150 SmallVectorImpl<SDValue> &Results,
6151 SelectionDAG &DAG) const {
6152 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6154 Results.push_back(Res);
6157 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6158 llvm_unreachable("LowerOperation not implemented for this target!");
6163 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6164 SDValue Op = getNonRegisterValue(V);
6165 assert((Op.getOpcode() != ISD::CopyFromReg ||
6166 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6167 "Copy from a reg to the same reg!");
6168 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6170 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6171 SDValue Chain = DAG.getEntryNode();
6172 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6173 PendingExports.push_back(Chain);
6176 #include "llvm/CodeGen/SelectionDAGISel.h"
6178 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6179 // If this is the entry block, emit arguments.
6180 const Function &F = *LLVMBB->getParent();
6181 SelectionDAG &DAG = SDB->DAG;
6182 DebugLoc dl = SDB->getCurDebugLoc();
6183 const TargetData *TD = TLI.getTargetData();
6184 SmallVector<ISD::InputArg, 16> Ins;
6186 // Check whether the function can return without sret-demotion.
6187 SmallVector<ISD::OutputArg, 4> Outs;
6188 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6191 if (!FuncInfo->CanLowerReturn) {
6192 // Put in an sret pointer parameter before all the other parameters.
6193 SmallVector<EVT, 1> ValueVTs;
6194 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6196 // NOTE: Assuming that a pointer will never break down to more than one VT
6198 ISD::ArgFlagsTy Flags;
6200 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6201 ISD::InputArg RetArg(Flags, RegisterVT, true);
6202 Ins.push_back(RetArg);
6205 // Set up the incoming argument description vector.
6207 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6208 I != E; ++I, ++Idx) {
6209 SmallVector<EVT, 4> ValueVTs;
6210 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6211 bool isArgValueUsed = !I->use_empty();
6212 for (unsigned Value = 0, NumValues = ValueVTs.size();
6213 Value != NumValues; ++Value) {
6214 EVT VT = ValueVTs[Value];
6215 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6216 ISD::ArgFlagsTy Flags;
6217 unsigned OriginalAlignment =
6218 TD->getABITypeAlignment(ArgTy);
6220 if (F.paramHasAttr(Idx, Attribute::ZExt))
6222 if (F.paramHasAttr(Idx, Attribute::SExt))
6224 if (F.paramHasAttr(Idx, Attribute::InReg))
6226 if (F.paramHasAttr(Idx, Attribute::StructRet))
6228 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6230 const PointerType *Ty = cast<PointerType>(I->getType());
6231 const Type *ElementTy = Ty->getElementType();
6232 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6233 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6234 // For ByVal, alignment should be passed from FE. BE will guess if
6235 // this info is not there but there are cases it cannot get right.
6236 if (F.getParamAlignment(Idx))
6237 FrameAlign = F.getParamAlignment(Idx);
6238 Flags.setByValAlign(FrameAlign);
6239 Flags.setByValSize(FrameSize);
6241 if (F.paramHasAttr(Idx, Attribute::Nest))
6243 Flags.setOrigAlign(OriginalAlignment);
6245 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6246 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6247 for (unsigned i = 0; i != NumRegs; ++i) {
6248 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6249 if (NumRegs > 1 && i == 0)
6250 MyFlags.Flags.setSplit();
6251 // if it isn't first piece, alignment must be 1
6253 MyFlags.Flags.setOrigAlign(1);
6254 Ins.push_back(MyFlags);
6259 // Call the target to set up the argument values.
6260 SmallVector<SDValue, 8> InVals;
6261 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6265 // Verify that the target's LowerFormalArguments behaved as expected.
6266 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6267 "LowerFormalArguments didn't return a valid chain!");
6268 assert(InVals.size() == Ins.size() &&
6269 "LowerFormalArguments didn't emit the correct number of values!");
6271 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6272 assert(InVals[i].getNode() &&
6273 "LowerFormalArguments emitted a null value!");
6274 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6275 "LowerFormalArguments emitted a value with the wrong type!");
6279 // Update the DAG with the new chain value resulting from argument lowering.
6280 DAG.setRoot(NewRoot);
6282 // Set up the argument values.
6285 if (!FuncInfo->CanLowerReturn) {
6286 // Create a virtual register for the sret pointer, and put in a copy
6287 // from the sret argument into it.
6288 SmallVector<EVT, 1> ValueVTs;
6289 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6290 EVT VT = ValueVTs[0];
6291 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6292 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6293 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6294 RegVT, VT, AssertOp);
6296 MachineFunction& MF = SDB->DAG.getMachineFunction();
6297 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6298 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6299 FuncInfo->DemoteRegister = SRetReg;
6300 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6302 DAG.setRoot(NewRoot);
6304 // i indexes lowered arguments. Bump it past the hidden sret argument.
6305 // Idx indexes LLVM arguments. Don't touch it.
6309 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6311 SmallVector<SDValue, 4> ArgValues;
6312 SmallVector<EVT, 4> ValueVTs;
6313 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6314 unsigned NumValues = ValueVTs.size();
6316 // If this argument is unused then remember its value. It is used to generate
6317 // debugging information.
6318 if (I->use_empty() && NumValues)
6319 SDB->setUnusedArgValue(I, InVals[i]);
6321 for (unsigned Value = 0; Value != NumValues; ++Value) {
6322 EVT VT = ValueVTs[Value];
6323 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6324 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6326 if (!I->use_empty()) {
6327 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6328 if (F.paramHasAttr(Idx, Attribute::SExt))
6329 AssertOp = ISD::AssertSext;
6330 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6331 AssertOp = ISD::AssertZext;
6333 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6334 NumParts, PartVT, VT,
6341 // Note down frame index for byval arguments.
6342 if (I->hasByValAttr() && !ArgValues.empty())
6343 if (FrameIndexSDNode *FI =
6344 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6345 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6347 if (!I->use_empty()) {
6349 if (!ArgValues.empty())
6350 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6351 SDB->getCurDebugLoc());
6352 SDB->setValue(I, Res);
6354 // If this argument is live outside of the entry block, insert a copy from
6355 // whereever we got it to the vreg that other BB's will reference it as.
6356 SDB->CopyToExportRegsIfNeeded(I);
6360 assert(i == InVals.size() && "Argument register count mismatch!");
6362 // Finally, if the target has anything special to do, allow it to do so.
6363 // FIXME: this should insert code into the DAG!
6364 EmitFunctionEntryCode();
6367 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6368 /// ensure constants are generated when needed. Remember the virtual registers
6369 /// that need to be added to the Machine PHI nodes as input. We cannot just
6370 /// directly add them, because expansion might result in multiple MBB's for one
6371 /// BB. As such, the start of the BB might correspond to a different MBB than
6375 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6376 const TerminatorInst *TI = LLVMBB->getTerminator();
6378 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6380 // Check successor nodes' PHI nodes that expect a constant to be available
6382 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6383 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6384 if (!isa<PHINode>(SuccBB->begin())) continue;
6385 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6387 // If this terminator has multiple identical successors (common for
6388 // switches), only handle each succ once.
6389 if (!SuccsHandled.insert(SuccMBB)) continue;
6391 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6393 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6394 // nodes and Machine PHI nodes, but the incoming operands have not been
6396 for (BasicBlock::const_iterator I = SuccBB->begin();
6397 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6398 // Ignore dead phi's.
6399 if (PN->use_empty()) continue;
6402 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6404 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6405 unsigned &RegOut = ConstantsOut[C];
6407 RegOut = FuncInfo.CreateRegs(C->getType());
6408 CopyValueToVirtualRegister(C, RegOut);
6412 DenseMap<const Value *, unsigned>::iterator I =
6413 FuncInfo.ValueMap.find(PHIOp);
6414 if (I != FuncInfo.ValueMap.end())
6417 assert(isa<AllocaInst>(PHIOp) &&
6418 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6419 "Didn't codegen value into a register!??");
6420 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6421 CopyValueToVirtualRegister(PHIOp, Reg);
6425 // Remember that this register needs to added to the machine PHI node as
6426 // the input for this MBB.
6427 SmallVector<EVT, 4> ValueVTs;
6428 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6429 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6430 EVT VT = ValueVTs[vti];
6431 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6432 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6433 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6434 Reg += NumRegisters;
6438 ConstantsOut.clear();