1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
202 ValueVT.bitsLT(PartEVT)) {
203 // For an FP value in an integer part, we need to truncate to the right
205 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
206 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
209 if (PartEVT.isInteger() && ValueVT.isInteger()) {
210 if (ValueVT.bitsLT(PartEVT)) {
211 // For a truncate, see if we have any information to
212 // indicate whether the truncated bits will always be
213 // zero or sign-extension.
214 if (AssertOp != ISD::DELETED_NODE)
215 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
216 DAG.getValueType(ValueVT));
217 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
219 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
223 // FP_ROUND's are always exact here.
224 if (ValueVT.bitsLT(Val.getValueType()))
226 ISD::FP_ROUND, DL, ValueVT, Val,
227 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
229 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
232 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
233 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
235 llvm_unreachable("Unknown mismatch!");
238 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
239 const Twine &ErrMsg) {
240 const Instruction *I = dyn_cast_or_null<Instruction>(V);
242 return Ctx.emitError(ErrMsg);
244 const char *AsmError = ", possible invalid constraint for vector type";
245 if (const CallInst *CI = dyn_cast<CallInst>(I))
246 if (isa<InlineAsm>(CI->getCalledValue()))
247 return Ctx.emitError(I, ErrMsg + AsmError);
249 return Ctx.emitError(I, ErrMsg);
252 /// getCopyFromPartsVector - Create a value that contains the specified legal
253 /// parts combined into the value they represent. If the parts combine to a
254 /// type larger then ValueVT then AssertOp can be used to specify whether the
255 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
256 /// ValueVT (ISD::AssertSext).
257 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
258 const SDValue *Parts, unsigned NumParts,
259 MVT PartVT, EVT ValueVT, const Value *V) {
260 assert(ValueVT.isVector() && "Not a vector value");
261 assert(NumParts > 0 && "No parts to assemble!");
262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
263 SDValue Val = Parts[0];
265 // Handle a multi-element vector.
269 unsigned NumIntermediates;
271 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
272 NumIntermediates, RegisterVT);
273 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
274 NumParts = NumRegs; // Silence a compiler warning.
275 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
276 assert(RegisterVT.getSizeInBits() ==
277 Parts[0].getSimpleValueType().getSizeInBits() &&
278 "Part type sizes don't match!");
280 // Assemble the parts into intermediate operands.
281 SmallVector<SDValue, 8> Ops(NumIntermediates);
282 if (NumIntermediates == NumParts) {
283 // If the register was not expanded, truncate or copy the value,
285 for (unsigned i = 0; i != NumParts; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
287 PartVT, IntermediateVT, V);
288 } else if (NumParts > 0) {
289 // If the intermediate type was expanded, build the intermediate
290 // operands from the parts.
291 assert(NumParts % NumIntermediates == 0 &&
292 "Must expand into a divisible number of parts!");
293 unsigned Factor = NumParts / NumIntermediates;
294 for (unsigned i = 0; i != NumIntermediates; ++i)
295 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
296 PartVT, IntermediateVT, V);
299 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
300 // intermediate operands.
301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
306 // There is now one part, held in Val. Correct it to match ValueVT.
307 EVT PartEVT = Val.getValueType();
309 if (PartEVT == ValueVT)
312 if (PartEVT.isVector()) {
313 // If the element type of the source/dest vectors are the same, but the
314 // parts vector has more elements than the value vector, then we have a
315 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
317 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
318 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
319 "Cannot narrow, it would be a lossy transformation");
321 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
322 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
325 // Vector/Vector bitcast.
326 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
327 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
329 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
330 "Cannot handle this kind of promotion");
331 // Promoted vector extract
332 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
336 // Trivial bitcast if the types are the same size and the destination
337 // vector type is legal.
338 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
339 TLI.isTypeLegal(ValueVT))
340 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
342 // Handle cases such as i8 -> <1 x i1>
343 if (ValueVT.getVectorNumElements() != 1) {
344 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
345 "non-trivial scalar-to-vector conversion");
346 return DAG.getUNDEF(ValueVT);
349 if (ValueVT.getVectorNumElements() == 1 &&
350 ValueVT.getVectorElementType() != PartEVT)
351 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
353 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
356 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
357 SDValue Val, SDValue *Parts, unsigned NumParts,
358 MVT PartVT, const Value *V);
360 /// getCopyToParts - Create a series of nodes that contain the specified value
361 /// split into legal parts. If the parts contain more bits than Val, then, for
362 /// integers, ExtendKind can be used to specify how to generate the extra bits.
363 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
364 SDValue Val, SDValue *Parts, unsigned NumParts,
365 MVT PartVT, const Value *V,
366 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
367 EVT ValueVT = Val.getValueType();
369 // Handle the vector case separately.
370 if (ValueVT.isVector())
371 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
373 unsigned PartBits = PartVT.getSizeInBits();
374 unsigned OrigNumParts = NumParts;
375 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
376 "Copying to an illegal type!");
381 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
382 EVT PartEVT = PartVT;
383 if (PartEVT == ValueVT) {
384 assert(NumParts == 1 && "No-op copy with multiple parts!");
389 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
390 // If the parts cover more bits than the value has, promote the value.
391 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
392 assert(NumParts == 1 && "Do not know what to promote to!");
393 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
395 if (ValueVT.isFloatingPoint()) {
396 // FP values need to be bitcast, then extended if they are being put
397 // into a larger container.
398 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
399 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 } else if (PartBits == ValueVT.getSizeInBits()) {
410 // Different types of the same size.
411 assert(NumParts == 1 && PartEVT != ValueVT);
412 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
413 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
414 // If the parts cover less bits than value has, truncate the value.
415 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
416 ValueVT.isInteger() &&
417 "Unknown mismatch!");
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
419 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
420 if (PartVT == MVT::x86mmx)
421 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
424 // The value may have changed - recompute ValueVT.
425 ValueVT = Val.getValueType();
426 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
427 "Failed to tile the value with PartVT!");
430 if (PartEVT != ValueVT)
431 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
432 "scalar-to-vector conversion failed");
438 // Expand the value into multiple parts.
439 if (NumParts & (NumParts - 1)) {
440 // The number of parts is not a power of 2. Split off and copy the tail.
441 assert(PartVT.isInteger() && ValueVT.isInteger() &&
442 "Do not know what to expand to!");
443 unsigned RoundParts = 1 << Log2_32(NumParts);
444 unsigned RoundBits = RoundParts * PartBits;
445 unsigned OddParts = NumParts - RoundParts;
446 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
447 DAG.getIntPtrConstant(RoundBits, DL));
448 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
450 if (DAG.getDataLayout().isBigEndian())
451 // The odd parts were reversed by getCopyToParts - unreverse them.
452 std::reverse(Parts + RoundParts, Parts + NumParts);
454 NumParts = RoundParts;
455 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
456 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
459 // The number of parts is a power of 2. Repeatedly bisect the value using
461 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
462 EVT::getIntegerVT(*DAG.getContext(),
463 ValueVT.getSizeInBits()),
466 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
467 for (unsigned i = 0; i < NumParts; i += StepSize) {
468 unsigned ThisBits = StepSize * PartBits / 2;
469 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
470 SDValue &Part0 = Parts[i];
471 SDValue &Part1 = Parts[i+StepSize/2];
473 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
474 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
475 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
476 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
478 if (ThisBits == PartBits && ThisVT != PartVT) {
479 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
480 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
485 if (DAG.getDataLayout().isBigEndian())
486 std::reverse(Parts, Parts + OrigNumParts);
490 /// getCopyToPartsVector - Create a series of nodes that contain the specified
491 /// value split into legal parts.
492 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
493 SDValue Val, SDValue *Parts, unsigned NumParts,
494 MVT PartVT, const Value *V) {
495 EVT ValueVT = Val.getValueType();
496 assert(ValueVT.isVector() && "Not a vector");
497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
500 EVT PartEVT = PartVT;
501 if (PartEVT == ValueVT) {
503 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
504 // Bitconvert vector->vector case.
505 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
508 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
509 EVT ElementVT = PartVT.getVectorElementType();
510 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
512 SmallVector<SDValue, 16> Ops;
513 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
514 Ops.push_back(DAG.getNode(
515 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
516 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
518 for (unsigned i = ValueVT.getVectorNumElements(),
519 e = PartVT.getVectorNumElements(); i != e; ++i)
520 Ops.push_back(DAG.getUNDEF(ElementVT));
522 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
524 // FIXME: Use CONCAT for 2x -> 4x.
526 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
527 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType().bitsGE(
530 ValueVT.getVectorElementType()) &&
531 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
533 // Promoted vector extract
534 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Vector -> scalar conversion.
537 assert(ValueVT.getVectorNumElements() == 1 &&
538 "Only trivial vector-to-scalar conversions should get here!");
540 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
541 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
543 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
550 // Handle a multi-element vector.
553 unsigned NumIntermediates;
554 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
556 NumIntermediates, RegisterVT);
557 unsigned NumElements = ValueVT.getVectorNumElements();
559 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
560 NumParts = NumRegs; // Silence a compiler warning.
561 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
563 // Split the vector into intermediate operands.
564 SmallVector<SDValue, 8> Ops(NumIntermediates);
565 for (unsigned i = 0; i != NumIntermediates; ++i) {
566 if (IntermediateVT.isVector())
568 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
569 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
570 TLI.getVectorIdxTy(DAG.getDataLayout())));
572 Ops[i] = DAG.getNode(
573 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
574 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
577 // Split the intermediate operands into legal parts.
578 if (NumParts == NumIntermediates) {
579 // If the register was not expanded, promote or copy the value,
581 for (unsigned i = 0; i != NumParts; ++i)
582 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
583 } else if (NumParts > 0) {
584 // If the intermediate type was expanded, split each the value into
586 assert(NumIntermediates != 0 && "division by zero");
587 assert(NumParts % NumIntermediates == 0 &&
588 "Must expand into a divisible number of parts!");
589 unsigned Factor = NumParts / NumIntermediates;
590 for (unsigned i = 0; i != NumIntermediates; ++i)
591 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
595 RegsForValue::RegsForValue() {}
597 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
601 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
602 const DataLayout &DL, unsigned Reg, Type *Ty) {
603 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
605 for (EVT ValueVT : ValueVTs) {
606 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
607 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
608 for (unsigned i = 0; i != NumRegs; ++i)
609 Regs.push_back(Reg + i);
610 RegVTs.push_back(RegisterVT);
615 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
616 /// this value and returns the result as a ValueVT value. This uses
617 /// Chain/Flag as the input and updates them for the output Chain/Flag.
618 /// If the Flag pointer is NULL, no flag is used.
619 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
620 FunctionLoweringInfo &FuncInfo,
622 SDValue &Chain, SDValue *Flag,
623 const Value *V) const {
624 // A Value with type {} or [0 x %t] needs no registers.
625 if (ValueVTs.empty())
628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
630 // Assemble the legal parts into the final values.
631 SmallVector<SDValue, 4> Values(ValueVTs.size());
632 SmallVector<SDValue, 8> Parts;
633 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
634 // Copy the legal parts from the registers.
635 EVT ValueVT = ValueVTs[Value];
636 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
637 MVT RegisterVT = RegVTs[Value];
639 Parts.resize(NumRegs);
640 for (unsigned i = 0; i != NumRegs; ++i) {
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
646 *Flag = P.getValue(2);
649 Chain = P.getValue(1);
652 // If the source register was virtual and if we know something about it,
653 // add an assert node.
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
655 !RegisterVT.isInteger() || RegisterVT.isVector())
658 const FunctionLoweringInfo::LiveOutInfo *LOI =
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
663 unsigned RegSize = RegisterVT.getSizeInBits();
664 unsigned NumSignBits = LOI->NumSignBits;
665 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
667 if (NumZeroBits == RegSize) {
668 // The current value is a zero.
669 // Explicitly express that as it would be easier for
670 // optimizations to kick in.
671 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
675 // FIXME: We capture more information than the dag can represent. For
676 // now, just use the tightest assertzext/assertsext possible.
678 EVT FromVT(MVT::Other);
679 if (NumSignBits == RegSize)
680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
681 else if (NumZeroBits >= RegSize-1)
682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
683 else if (NumSignBits > RegSize-8)
684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
685 else if (NumZeroBits >= RegSize-8)
686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
687 else if (NumSignBits > RegSize-16)
688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
689 else if (NumZeroBits >= RegSize-16)
690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
691 else if (NumSignBits > RegSize-32)
692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
693 else if (NumZeroBits >= RegSize-32)
694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
698 // Add an assertion node.
699 assert(FromVT != MVT::Other);
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
701 RegisterVT, P, DAG.getValueType(FromVT));
704 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
705 NumRegs, RegisterVT, ValueVT, V);
710 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
713 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
714 /// specified value into the registers specified by this object. This uses
715 /// Chain/Flag as the input and updates them for the output Chain/Flag.
716 /// If the Flag pointer is NULL, no flag is used.
717 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
718 SDValue &Chain, SDValue *Flag, const Value *V,
719 ISD::NodeType PreferredExtendType) const {
720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
721 ISD::NodeType ExtendKind = PreferredExtendType;
723 // Get the list of the values's legal parts.
724 unsigned NumRegs = Regs.size();
725 SmallVector<SDValue, 8> Parts(NumRegs);
726 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
727 EVT ValueVT = ValueVTs[Value];
728 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
729 MVT RegisterVT = RegVTs[Value];
731 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
732 ExtendKind = ISD::ZERO_EXTEND;
734 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
735 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
739 // Copy the parts into the registers.
740 SmallVector<SDValue, 8> Chains(NumRegs);
741 for (unsigned i = 0; i != NumRegs; ++i) {
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
747 *Flag = Part.getValue(1);
750 Chains[i] = Part.getValue(0);
753 if (NumRegs == 1 || Flag)
754 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
755 // flagged to it. That is the CopyToReg nodes and the user are considered
756 // a single scheduling unit. If we create a TokenFactor and return it as
757 // chain, then the TokenFactor is both a predecessor (operand) of the
758 // user as well as a successor (the TF operands are flagged to the user).
759 // c1, f1 = CopyToReg
760 // c2, f2 = CopyToReg
761 // c3 = TokenFactor c1, c2
764 Chain = Chains[NumRegs-1];
766 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
769 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
770 /// operand list. This adds the code marker and includes the number of
771 /// values added into it.
772 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
773 unsigned MatchingIdx, SDLoc dl,
775 std::vector<SDValue> &Ops) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
780 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
781 else if (!Regs.empty() &&
782 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
783 // Put the register class of the virtual registers in the flag word. That
784 // way, later passes can recompute register class constraints for inline
785 // assembly as well as normal instructions.
786 // Don't do this for tied operands that can use the regclass information
788 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
790 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
793 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
796 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
797 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
798 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
799 MVT RegisterVT = RegVTs[Value];
800 for (unsigned i = 0; i != NumRegs; ++i) {
801 assert(Reg < Regs.size() && "Mismatch in # registers expected");
802 unsigned TheReg = Regs[Reg++];
803 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
805 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
806 // If we clobbered the stack pointer, MFI should know about it.
807 assert(DAG.getMachineFunction().getFrameInfo()->
808 hasOpaqueSPAdjustment());
814 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
815 const TargetLibraryInfo *li) {
819 DL = &DAG.getDataLayout();
820 Context = DAG.getContext();
821 LPadToCallSiteMap.clear();
824 /// clear - Clear out the current SelectionDAG and the associated
825 /// state and prepare this SelectionDAGBuilder object to be used
826 /// for a new block. This doesn't clear out information about
827 /// additional blocks that are needed to complete switch lowering
828 /// or PHI node updating; that information is cleared out as it is
830 void SelectionDAGBuilder::clear() {
832 UnusedArgNodeMap.clear();
833 PendingLoads.clear();
834 PendingExports.clear();
837 SDNodeOrder = LowestSDNodeOrder;
838 StatepointLowering.clear();
841 /// clearDanglingDebugInfo - Clear the dangling debug information
842 /// map. This function is separated from the clear so that debug
843 /// information that is dangling in a basic block can be properly
844 /// resolved in a different basic block. This allows the
845 /// SelectionDAG to resolve dangling debug information attached
847 void SelectionDAGBuilder::clearDanglingDebugInfo() {
848 DanglingDebugInfoMap.clear();
851 /// getRoot - Return the current virtual root of the Selection DAG,
852 /// flushing any PendingLoad items. This must be done before emitting
853 /// a store or any other node that may need to be ordered after any
854 /// prior load instructions.
856 SDValue SelectionDAGBuilder::getRoot() {
857 if (PendingLoads.empty())
858 return DAG.getRoot();
860 if (PendingLoads.size() == 1) {
861 SDValue Root = PendingLoads[0];
863 PendingLoads.clear();
867 // Otherwise, we have to make a token factor node.
868 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
870 PendingLoads.clear();
875 /// getControlRoot - Similar to getRoot, but instead of flushing all the
876 /// PendingLoad items, flush all the PendingExports items. It is necessary
877 /// to do this before emitting a terminator instruction.
879 SDValue SelectionDAGBuilder::getControlRoot() {
880 SDValue Root = DAG.getRoot();
882 if (PendingExports.empty())
885 // Turn all of the CopyToReg chains into one factored node.
886 if (Root.getOpcode() != ISD::EntryToken) {
887 unsigned i = 0, e = PendingExports.size();
888 for (; i != e; ++i) {
889 assert(PendingExports[i].getNode()->getNumOperands() > 1);
890 if (PendingExports[i].getNode()->getOperand(0) == Root)
891 break; // Don't add the root if we already indirectly depend on it.
895 PendingExports.push_back(Root);
898 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
900 PendingExports.clear();
905 void SelectionDAGBuilder::visit(const Instruction &I) {
906 // Set up outgoing PHI node register values before emitting the terminator.
907 if (isa<TerminatorInst>(&I))
908 HandlePHINodesInSuccessorBlocks(I.getParent());
914 visit(I.getOpcode(), I);
916 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
917 !isStatepoint(&I)) // statepoints handle their exports internally
918 CopyToExportRegsIfNeeded(&I);
923 void SelectionDAGBuilder::visitPHI(const PHINode &) {
924 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
927 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
928 // Note: this doesn't use InstVisitor, because it has to work with
929 // ConstantExpr's in addition to instructions.
931 default: llvm_unreachable("Unknown instruction type encountered!");
932 // Build the switch statement using the Instruction.def file.
933 #define HANDLE_INST(NUM, OPCODE, CLASS) \
934 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
935 #include "llvm/IR/Instruction.def"
939 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
940 // generate the debug data structures now that we've seen its definition.
941 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
943 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
945 const DbgValueInst *DI = DDI.getDI();
946 DebugLoc dl = DDI.getdl();
947 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
948 DILocalVariable *Variable = DI->getVariable();
949 DIExpression *Expr = DI->getExpression();
950 assert(Variable->isValidLocationForIntrinsic(dl) &&
951 "Expected inlined-at fields to agree");
952 uint64_t Offset = DI->getOffset();
953 // A dbg.value for an alloca is always indirect.
954 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
957 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
959 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
960 IsIndirect, Offset, dl, DbgSDNodeOrder);
961 DAG.AddDbgValue(SDV, Val.getNode(), false);
964 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
965 DanglingDebugInfoMap[V] = DanglingDebugInfo();
969 /// getCopyFromRegs - If there was virtual register allocated for the value V
970 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
971 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
972 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
975 if (It != FuncInfo.ValueMap.end()) {
976 unsigned InReg = It->second;
977 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
978 DAG.getDataLayout(), InReg, Ty);
979 SDValue Chain = DAG.getEntryNode();
980 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
981 resolveDanglingDebugInfo(V, Result);
987 /// getValue - Return an SDValue for the given Value.
988 SDValue SelectionDAGBuilder::getValue(const Value *V) {
989 // If we already have an SDValue for this value, use it. It's important
990 // to do this first, so that we don't create a CopyFromReg if we already
991 // have a regular SDValue.
992 SDValue &N = NodeMap[V];
993 if (N.getNode()) return N;
995 // If there's a virtual register allocated and initialized for this
997 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
998 if (copyFromReg.getNode()) {
1002 // Otherwise create a new SDValue and remember it.
1003 SDValue Val = getValueImpl(V);
1005 resolveDanglingDebugInfo(V, Val);
1009 // Return true if SDValue exists for the given Value
1010 bool SelectionDAGBuilder::findValue(const Value *V) const {
1011 return (NodeMap.find(V) != NodeMap.end()) ||
1012 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1015 /// getNonRegisterValue - Return an SDValue for the given Value, but
1016 /// don't look in FuncInfo.ValueMap for a virtual register.
1017 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1018 // If we already have an SDValue for this value, use it.
1019 SDValue &N = NodeMap[V];
1021 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1022 // Remove the debug location from the node as the node is about to be used
1023 // in a location which may differ from the original debug location. This
1024 // is relevant to Constant and ConstantFP nodes because they can appear
1025 // as constant expressions inside PHI nodes.
1026 N->setDebugLoc(DebugLoc());
1031 // Otherwise create a new SDValue and remember it.
1032 SDValue Val = getValueImpl(V);
1034 resolveDanglingDebugInfo(V, Val);
1038 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1039 /// Create an SDValue for the given value.
1040 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1041 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1043 if (const Constant *C = dyn_cast<Constant>(V)) {
1044 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1046 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1047 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1049 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1050 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1052 if (isa<ConstantPointerNull>(C)) {
1053 unsigned AS = V->getType()->getPointerAddressSpace();
1054 return DAG.getConstant(0, getCurSDLoc(),
1055 TLI.getPointerTy(DAG.getDataLayout(), AS));
1058 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1059 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1061 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1062 return DAG.getUNDEF(VT);
1064 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1065 visit(CE->getOpcode(), *CE);
1066 SDValue N1 = NodeMap[V];
1067 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1071 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1072 SmallVector<SDValue, 4> Constants;
1073 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1075 SDNode *Val = getValue(*OI).getNode();
1076 // If the operand is an empty aggregate, there are no values.
1078 // Add each leaf value from the operand to the Constants list
1079 // to form a flattened list of all the values.
1080 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1081 Constants.push_back(SDValue(Val, i));
1084 return DAG.getMergeValues(Constants, getCurSDLoc());
1087 if (const ConstantDataSequential *CDS =
1088 dyn_cast<ConstantDataSequential>(C)) {
1089 SmallVector<SDValue, 4> Ops;
1090 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1091 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1092 // Add each leaf value from the operand to the Constants list
1093 // to form a flattened list of all the values.
1094 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1095 Ops.push_back(SDValue(Val, i));
1098 if (isa<ArrayType>(CDS->getType()))
1099 return DAG.getMergeValues(Ops, getCurSDLoc());
1100 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1104 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1105 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1106 "Unknown struct or array constant!");
1108 SmallVector<EVT, 4> ValueVTs;
1109 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1110 unsigned NumElts = ValueVTs.size();
1112 return SDValue(); // empty struct
1113 SmallVector<SDValue, 4> Constants(NumElts);
1114 for (unsigned i = 0; i != NumElts; ++i) {
1115 EVT EltVT = ValueVTs[i];
1116 if (isa<UndefValue>(C))
1117 Constants[i] = DAG.getUNDEF(EltVT);
1118 else if (EltVT.isFloatingPoint())
1119 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1121 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1124 return DAG.getMergeValues(Constants, getCurSDLoc());
1127 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1128 return DAG.getBlockAddress(BA, VT);
1130 VectorType *VecTy = cast<VectorType>(V->getType());
1131 unsigned NumElements = VecTy->getNumElements();
1133 // Now that we know the number and type of the elements, get that number of
1134 // elements into the Ops array based on what kind of constant it is.
1135 SmallVector<SDValue, 16> Ops;
1136 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1137 for (unsigned i = 0; i != NumElements; ++i)
1138 Ops.push_back(getValue(CV->getOperand(i)));
1140 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1142 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1145 if (EltVT.isFloatingPoint())
1146 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1148 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1149 Ops.assign(NumElements, Op);
1152 // Create a BUILD_VECTOR node.
1153 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1156 // If this is a static alloca, generate it as the frameindex instead of
1158 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1159 DenseMap<const AllocaInst*, int>::iterator SI =
1160 FuncInfo.StaticAllocaMap.find(AI);
1161 if (SI != FuncInfo.StaticAllocaMap.end())
1162 return DAG.getFrameIndex(SI->second,
1163 TLI.getPointerTy(DAG.getDataLayout()));
1166 // If this is an instruction which fast-isel has deferred, select it now.
1167 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1168 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1169 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1171 SDValue Chain = DAG.getEntryNode();
1172 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1175 llvm_unreachable("Can't get register for value!");
1178 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1179 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1180 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1181 bool IsSEH = isAsynchronousEHPersonality(Pers);
1182 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1183 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1184 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1185 if (IsMSVCCXX || IsCoreCLR)
1186 CatchPadMBB->setIsEHFuncletEntry();
1188 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1190 // Update machine-CFG edge.
1191 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1193 // CatchPads in SEH are not funclets, they are merely markers which indicate
1194 // where to insert register restoration code.
1196 DAG.setRoot(DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1197 getControlRoot(), DAG.getBasicBlock(NormalDestMBB),
1198 DAG.getBasicBlock(&FuncInfo.MF->front())));
1202 // If this is not a fall-through branch or optimizations are switched off,
1204 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1205 TM.getOptLevel() == CodeGenOpt::None)
1206 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1208 DAG.getBasicBlock(NormalDestMBB)));
1211 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1212 // Update machine-CFG edge.
1213 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1214 FuncInfo.MBB->addSuccessor(TargetMBB);
1216 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1217 bool IsSEH = isAsynchronousEHPersonality(Pers);
1219 // If this is not a fall-through branch or optimizations are switched off,
1221 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1222 TM.getOptLevel() == CodeGenOpt::None)
1223 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1224 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1228 // Figure out the funclet membership for the catchret's successor.
1229 // This will be used by the FuncletLayout pass to determine how to order the
1231 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1232 WinEHFuncInfo &EHInfo =
1233 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1234 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1235 assert(SuccessorColor && "No parent funclet for catchret!");
1236 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1237 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1239 // Create the terminator node.
1240 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1241 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1242 DAG.getBasicBlock(SuccessorColorMBB));
1246 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1247 llvm_unreachable("should never codegen catchendpads");
1250 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1251 // Don't emit any special code for the cleanuppad instruction. It just marks
1252 // the start of a funclet.
1253 FuncInfo.MBB->setIsEHFuncletEntry();
1254 FuncInfo.MBB->setIsCleanupFuncletEntry();
1257 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1258 /// many places it could ultimately go. In the IR, we have a single unwind
1259 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1260 /// This function skips over imaginary basic blocks that hold catchpad,
1261 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1262 /// basic block destinations. As those destinations may not be successors of
1263 /// EHPadBB, here we also calculate the edge weight to those destinations. The
1264 /// passed-in Weight is the edge weight to EHPadBB.
1265 static void findUnwindDestinations(
1266 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, uint32_t Weight,
1267 SmallVectorImpl<std::pair<MachineBasicBlock *, uint32_t>> &UnwindDests) {
1268 EHPersonality Personality =
1269 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1270 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1271 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1274 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1275 BasicBlock *NewEHPadBB = nullptr;
1276 if (isa<LandingPadInst>(Pad)) {
1277 // Stop on landingpads. They are not funclets.
1278 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1280 } else if (isa<CleanupPadInst>(Pad)) {
1281 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1283 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1284 UnwindDests.back().first->setIsEHFuncletEntry();
1286 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1287 // Add the catchpad handler to the possible destinations.
1288 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1289 // In MSVC C++, catchblocks are funclets and need prologues.
1290 if (IsMSVCCXX || IsCoreCLR)
1291 UnwindDests.back().first->setIsEHFuncletEntry();
1292 NewEHPadBB = CPI->getUnwindDest();
1293 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad))
1294 NewEHPadBB = CEPI->getUnwindDest();
1295 else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad))
1296 NewEHPadBB = CEPI->getUnwindDest();
1300 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1301 if (BPI && NewEHPadBB) {
1302 // When BPI is available, the calculated weight cannot be zero as zero
1303 // will be turned to a default weight in MachineBlockFrequencyInfo.
1304 Weight = std::max<uint32_t>(
1305 BPI->getEdgeProbability(EHPadBB, NewEHPadBB).scale(Weight), 1);
1307 EHPadBB = NewEHPadBB;
1311 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1312 // Update successor info.
1313 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
1314 auto UnwindDest = I.getUnwindDest();
1315 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1316 uint32_t UnwindDestWeight =
1317 BPI ? BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(), UnwindDest) : 0;
1318 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestWeight, UnwindDests);
1319 for (auto &UnwindDest : UnwindDests) {
1320 UnwindDest.first->setIsEHPad();
1321 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1324 // Create the terminator node.
1326 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1330 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1331 report_fatal_error("visitCleanupEndPad not yet implemented!");
1334 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1335 report_fatal_error("visitTerminatePad not yet implemented!");
1338 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1339 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1340 auto &DL = DAG.getDataLayout();
1341 SDValue Chain = getControlRoot();
1342 SmallVector<ISD::OutputArg, 8> Outs;
1343 SmallVector<SDValue, 8> OutVals;
1345 if (!FuncInfo.CanLowerReturn) {
1346 unsigned DemoteReg = FuncInfo.DemoteRegister;
1347 const Function *F = I.getParent()->getParent();
1349 // Emit a store of the return value through the virtual register.
1350 // Leave Outs empty so that LowerReturn won't try to load return
1351 // registers the usual way.
1352 SmallVector<EVT, 1> PtrValueVTs;
1353 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1356 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1357 SDValue RetOp = getValue(I.getOperand(0));
1359 SmallVector<EVT, 4> ValueVTs;
1360 SmallVector<uint64_t, 4> Offsets;
1361 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1362 unsigned NumValues = ValueVTs.size();
1364 SmallVector<SDValue, 4> Chains(NumValues);
1365 for (unsigned i = 0; i != NumValues; ++i) {
1366 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1367 RetPtr.getValueType(), RetPtr,
1368 DAG.getIntPtrConstant(Offsets[i],
1371 DAG.getStore(Chain, getCurSDLoc(),
1372 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1373 // FIXME: better loc info would be nice.
1374 Add, MachinePointerInfo(), false, false, 0);
1377 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1378 MVT::Other, Chains);
1379 } else if (I.getNumOperands() != 0) {
1380 SmallVector<EVT, 4> ValueVTs;
1381 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1382 unsigned NumValues = ValueVTs.size();
1384 SDValue RetOp = getValue(I.getOperand(0));
1386 const Function *F = I.getParent()->getParent();
1388 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1389 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1391 ExtendKind = ISD::SIGN_EXTEND;
1392 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1394 ExtendKind = ISD::ZERO_EXTEND;
1396 LLVMContext &Context = F->getContext();
1397 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1400 for (unsigned j = 0; j != NumValues; ++j) {
1401 EVT VT = ValueVTs[j];
1403 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1404 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1406 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1407 MVT PartVT = TLI.getRegisterType(Context, VT);
1408 SmallVector<SDValue, 4> Parts(NumParts);
1409 getCopyToParts(DAG, getCurSDLoc(),
1410 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1411 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1413 // 'inreg' on function refers to return value
1414 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1418 // Propagate extension type if any
1419 if (ExtendKind == ISD::SIGN_EXTEND)
1421 else if (ExtendKind == ISD::ZERO_EXTEND)
1424 for (unsigned i = 0; i < NumParts; ++i) {
1425 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1426 VT, /*isfixed=*/true, 0, 0));
1427 OutVals.push_back(Parts[i]);
1433 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1434 CallingConv::ID CallConv =
1435 DAG.getMachineFunction().getFunction()->getCallingConv();
1436 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1437 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1439 // Verify that the target's LowerReturn behaved as expected.
1440 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1441 "LowerReturn didn't return a valid chain!");
1443 // Update the DAG with the new chain value resulting from return lowering.
1447 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1448 /// created for it, emit nodes to copy the value into the virtual
1450 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1452 if (V->getType()->isEmptyTy())
1455 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1456 if (VMI != FuncInfo.ValueMap.end()) {
1457 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1458 CopyValueToVirtualRegister(V, VMI->second);
1462 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1463 /// the current basic block, add it to ValueMap now so that we'll get a
1465 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1466 // No need to export constants.
1467 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1469 // Already exported?
1470 if (FuncInfo.isExportedInst(V)) return;
1472 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1473 CopyValueToVirtualRegister(V, Reg);
1476 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1477 const BasicBlock *FromBB) {
1478 // The operands of the setcc have to be in this block. We don't know
1479 // how to export them from some other block.
1480 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1481 // Can export from current BB.
1482 if (VI->getParent() == FromBB)
1485 // Is already exported, noop.
1486 return FuncInfo.isExportedInst(V);
1489 // If this is an argument, we can export it if the BB is the entry block or
1490 // if it is already exported.
1491 if (isa<Argument>(V)) {
1492 if (FromBB == &FromBB->getParent()->getEntryBlock())
1495 // Otherwise, can only export this if it is already exported.
1496 return FuncInfo.isExportedInst(V);
1499 // Otherwise, constants can always be exported.
1503 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1504 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1505 const MachineBasicBlock *Dst) const {
1506 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1509 const BasicBlock *SrcBB = Src->getBasicBlock();
1510 const BasicBlock *DstBB = Dst->getBasicBlock();
1511 return BPI->getEdgeWeight(SrcBB, DstBB);
1514 void SelectionDAGBuilder::
1515 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1516 uint32_t Weight /* = 0 */) {
1518 Src->addSuccessorWithoutWeight(Dst);
1521 Weight = getEdgeWeight(Src, Dst);
1522 Src->addSuccessor(Dst, Weight);
1527 static bool InBlock(const Value *V, const BasicBlock *BB) {
1528 if (const Instruction *I = dyn_cast<Instruction>(V))
1529 return I->getParent() == BB;
1533 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1534 /// This function emits a branch and is used at the leaves of an OR or an
1535 /// AND operator tree.
1538 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1539 MachineBasicBlock *TBB,
1540 MachineBasicBlock *FBB,
1541 MachineBasicBlock *CurBB,
1542 MachineBasicBlock *SwitchBB,
1545 const BasicBlock *BB = CurBB->getBasicBlock();
1547 // If the leaf of the tree is a comparison, merge the condition into
1549 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1550 // The operands of the cmp have to be in this block. We don't know
1551 // how to export them from some other block. If this is the first block
1552 // of the sequence, no exporting is needed.
1553 if (CurBB == SwitchBB ||
1554 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1555 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1556 ISD::CondCode Condition;
1557 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1558 Condition = getICmpCondCode(IC->getPredicate());
1560 const FCmpInst *FC = cast<FCmpInst>(Cond);
1561 Condition = getFCmpCondCode(FC->getPredicate());
1562 if (TM.Options.NoNaNsFPMath)
1563 Condition = getFCmpCodeWithoutNaN(Condition);
1566 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1567 TBB, FBB, CurBB, TWeight, FWeight);
1568 SwitchCases.push_back(CB);
1573 // Create a CaseBlock record representing this branch.
1574 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1575 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1576 SwitchCases.push_back(CB);
1579 /// Scale down both weights to fit into uint32_t.
1580 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1581 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1582 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1583 NewTrue = NewTrue / Scale;
1584 NewFalse = NewFalse / Scale;
1587 /// FindMergedConditions - If Cond is an expression like
1588 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1589 MachineBasicBlock *TBB,
1590 MachineBasicBlock *FBB,
1591 MachineBasicBlock *CurBB,
1592 MachineBasicBlock *SwitchBB,
1593 Instruction::BinaryOps Opc,
1596 // If this node is not part of the or/and tree, emit it as a branch.
1597 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1598 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1599 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1600 BOp->getParent() != CurBB->getBasicBlock() ||
1601 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1602 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1603 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1608 // Create TmpBB after CurBB.
1609 MachineFunction::iterator BBI(CurBB);
1610 MachineFunction &MF = DAG.getMachineFunction();
1611 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1612 CurBB->getParent()->insert(++BBI, TmpBB);
1614 if (Opc == Instruction::Or) {
1615 // Codegen X | Y as:
1624 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1625 // The requirement is that
1626 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1627 // = TrueProb for original BB.
1628 // Assuming the original weights are A and B, one choice is to set BB1's
1629 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1631 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1632 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1633 // TmpBB, but the math is more complicated.
1635 uint64_t NewTrueWeight = TWeight;
1636 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1637 ScaleWeights(NewTrueWeight, NewFalseWeight);
1638 // Emit the LHS condition.
1639 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1640 NewTrueWeight, NewFalseWeight);
1642 NewTrueWeight = TWeight;
1643 NewFalseWeight = 2 * (uint64_t)FWeight;
1644 ScaleWeights(NewTrueWeight, NewFalseWeight);
1645 // Emit the RHS condition into TmpBB.
1646 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1647 NewTrueWeight, NewFalseWeight);
1649 assert(Opc == Instruction::And && "Unknown merge op!");
1650 // Codegen X & Y as:
1658 // This requires creation of TmpBB after CurBB.
1660 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1661 // The requirement is that
1662 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1663 // = FalseProb for original BB.
1664 // Assuming the original weights are A and B, one choice is to set BB1's
1665 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1667 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1669 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1670 uint64_t NewFalseWeight = FWeight;
1671 ScaleWeights(NewTrueWeight, NewFalseWeight);
1672 // Emit the LHS condition.
1673 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1674 NewTrueWeight, NewFalseWeight);
1676 NewTrueWeight = 2 * (uint64_t)TWeight;
1677 NewFalseWeight = FWeight;
1678 ScaleWeights(NewTrueWeight, NewFalseWeight);
1679 // Emit the RHS condition into TmpBB.
1680 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1681 NewTrueWeight, NewFalseWeight);
1685 /// If the set of cases should be emitted as a series of branches, return true.
1686 /// If we should emit this as a bunch of and/or'd together conditions, return
1689 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1690 if (Cases.size() != 2) return true;
1692 // If this is two comparisons of the same values or'd or and'd together, they
1693 // will get folded into a single comparison, so don't emit two blocks.
1694 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1695 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1696 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1697 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1701 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1702 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1703 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1704 Cases[0].CC == Cases[1].CC &&
1705 isa<Constant>(Cases[0].CmpRHS) &&
1706 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1707 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1709 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1716 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1717 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1719 // Update machine-CFG edges.
1720 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1722 if (I.isUnconditional()) {
1723 // Update machine-CFG edges.
1724 BrMBB->addSuccessor(Succ0MBB);
1726 // If this is not a fall-through branch or optimizations are switched off,
1728 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1729 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1730 MVT::Other, getControlRoot(),
1731 DAG.getBasicBlock(Succ0MBB)));
1736 // If this condition is one of the special cases we handle, do special stuff
1738 const Value *CondVal = I.getCondition();
1739 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1741 // If this is a series of conditions that are or'd or and'd together, emit
1742 // this as a sequence of branches instead of setcc's with and/or operations.
1743 // As long as jumps are not expensive, this should improve performance.
1744 // For example, instead of something like:
1757 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1758 Instruction::BinaryOps Opcode = BOp->getOpcode();
1759 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1760 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1761 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1762 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1763 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1764 getEdgeWeight(BrMBB, Succ1MBB));
1765 // If the compares in later blocks need to use values not currently
1766 // exported from this block, export them now. This block should always
1767 // be the first entry.
1768 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1770 // Allow some cases to be rejected.
1771 if (ShouldEmitAsBranches(SwitchCases)) {
1772 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1773 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1774 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1777 // Emit the branch for this block.
1778 visitSwitchCase(SwitchCases[0], BrMBB);
1779 SwitchCases.erase(SwitchCases.begin());
1783 // Okay, we decided not to do this, remove any inserted MBB's and clear
1785 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1786 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1788 SwitchCases.clear();
1792 // Create a CaseBlock record representing this branch.
1793 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1794 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1796 // Use visitSwitchCase to actually insert the fast branch sequence for this
1798 visitSwitchCase(CB, BrMBB);
1801 /// visitSwitchCase - Emits the necessary code to represent a single node in
1802 /// the binary search tree resulting from lowering a switch instruction.
1803 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1804 MachineBasicBlock *SwitchBB) {
1806 SDValue CondLHS = getValue(CB.CmpLHS);
1807 SDLoc dl = getCurSDLoc();
1809 // Build the setcc now.
1811 // Fold "(X == true)" to X and "(X == false)" to !X to
1812 // handle common cases produced by branch lowering.
1813 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1814 CB.CC == ISD::SETEQ)
1816 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1817 CB.CC == ISD::SETEQ) {
1818 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1819 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1821 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1823 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1825 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1826 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1828 SDValue CmpOp = getValue(CB.CmpMHS);
1829 EVT VT = CmpOp.getValueType();
1831 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1832 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1835 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1836 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1837 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1838 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1842 // Update successor info
1843 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1844 // TrueBB and FalseBB are always different unless the incoming IR is
1845 // degenerate. This only happens when running llc on weird IR.
1846 if (CB.TrueBB != CB.FalseBB)
1847 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1849 // If the lhs block is the next block, invert the condition so that we can
1850 // fall through to the lhs instead of the rhs block.
1851 if (CB.TrueBB == NextBlock(SwitchBB)) {
1852 std::swap(CB.TrueBB, CB.FalseBB);
1853 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1854 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1857 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1858 MVT::Other, getControlRoot(), Cond,
1859 DAG.getBasicBlock(CB.TrueBB));
1861 // Insert the false branch. Do this even if it's a fall through branch,
1862 // this makes it easier to do DAG optimizations which require inverting
1863 // the branch condition.
1864 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1865 DAG.getBasicBlock(CB.FalseBB));
1867 DAG.setRoot(BrCond);
1870 /// visitJumpTable - Emit JumpTable node in the current MBB
1871 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1872 // Emit the code for the jump table
1873 assert(JT.Reg != -1U && "Should lower JT Header first!");
1874 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1875 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1877 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1878 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1879 MVT::Other, Index.getValue(1),
1881 DAG.setRoot(BrJumpTable);
1884 /// visitJumpTableHeader - This function emits necessary code to produce index
1885 /// in the JumpTable from switch case.
1886 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1887 JumpTableHeader &JTH,
1888 MachineBasicBlock *SwitchBB) {
1889 SDLoc dl = getCurSDLoc();
1891 // Subtract the lowest switch case value from the value being switched on and
1892 // conditional branch to default mbb if the result is greater than the
1893 // difference between smallest and largest cases.
1894 SDValue SwitchOp = getValue(JTH.SValue);
1895 EVT VT = SwitchOp.getValueType();
1896 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1897 DAG.getConstant(JTH.First, dl, VT));
1899 // The SDNode we just created, which holds the value being switched on minus
1900 // the smallest case value, needs to be copied to a virtual register so it
1901 // can be used as an index into the jump table in a subsequent basic block.
1902 // This value may be smaller or larger than the target's pointer type, and
1903 // therefore require extension or truncating.
1904 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1905 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1907 unsigned JumpTableReg =
1908 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1909 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1910 JumpTableReg, SwitchOp);
1911 JT.Reg = JumpTableReg;
1913 // Emit the range check for the jump table, and branch to the default block
1914 // for the switch statement if the value being switched on exceeds the largest
1915 // case in the switch.
1916 SDValue CMP = DAG.getSetCC(
1917 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1918 Sub.getValueType()),
1919 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1921 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1922 MVT::Other, CopyTo, CMP,
1923 DAG.getBasicBlock(JT.Default));
1925 // Avoid emitting unnecessary branches to the next block.
1926 if (JT.MBB != NextBlock(SwitchBB))
1927 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1928 DAG.getBasicBlock(JT.MBB));
1930 DAG.setRoot(BrCond);
1933 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1934 /// tail spliced into a stack protector check success bb.
1936 /// For a high level explanation of how this fits into the stack protector
1937 /// generation see the comment on the declaration of class
1938 /// StackProtectorDescriptor.
1939 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1940 MachineBasicBlock *ParentBB) {
1942 // First create the loads to the guard/stack slot for the comparison.
1943 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1944 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1946 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1947 int FI = MFI->getStackProtectorIndex();
1949 const Value *IRGuard = SPD.getGuard();
1950 SDValue GuardPtr = getValue(IRGuard);
1951 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1953 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1956 SDLoc dl = getCurSDLoc();
1958 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1959 // guard value from the virtual register holding the value. Otherwise, emit a
1960 // volatile load to retrieve the stack guard value.
1961 unsigned GuardReg = SPD.getGuardReg();
1963 if (GuardReg && TLI.useLoadStackGuardNode())
1964 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1967 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1968 GuardPtr, MachinePointerInfo(IRGuard, 0),
1969 true, false, false, Align);
1971 SDValue StackSlot = DAG.getLoad(
1972 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1973 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1974 false, false, Align);
1976 // Perform the comparison via a subtract/getsetcc.
1977 EVT VT = Guard.getValueType();
1978 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1980 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1982 Sub.getValueType()),
1983 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1985 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1986 // branch to failure MBB.
1987 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1988 MVT::Other, StackSlot.getOperand(0),
1989 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1990 // Otherwise branch to success MBB.
1991 SDValue Br = DAG.getNode(ISD::BR, dl,
1993 DAG.getBasicBlock(SPD.getSuccessMBB()));
1998 /// Codegen the failure basic block for a stack protector check.
2000 /// A failure stack protector machine basic block consists simply of a call to
2001 /// __stack_chk_fail().
2003 /// For a high level explanation of how this fits into the stack protector
2004 /// generation see the comment on the declaration of class
2005 /// StackProtectorDescriptor.
2007 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
2008 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2010 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2011 None, false, getCurSDLoc(), false, false).second;
2015 /// visitBitTestHeader - This function emits necessary code to produce value
2016 /// suitable for "bit tests"
2017 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2018 MachineBasicBlock *SwitchBB) {
2019 SDLoc dl = getCurSDLoc();
2021 // Subtract the minimum value
2022 SDValue SwitchOp = getValue(B.SValue);
2023 EVT VT = SwitchOp.getValueType();
2024 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2025 DAG.getConstant(B.First, dl, VT));
2028 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2029 SDValue RangeCmp = DAG.getSetCC(
2030 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2031 Sub.getValueType()),
2032 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2034 // Determine the type of the test operands.
2035 bool UsePtrType = false;
2036 if (!TLI.isTypeLegal(VT))
2039 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2040 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2041 // Switch table case range are encoded into series of masks.
2042 // Just use pointer type, it's guaranteed to fit.
2048 VT = TLI.getPointerTy(DAG.getDataLayout());
2049 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2052 B.RegVT = VT.getSimpleVT();
2053 B.Reg = FuncInfo.CreateReg(B.RegVT);
2054 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2056 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2058 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2059 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2061 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2062 MVT::Other, CopyTo, RangeCmp,
2063 DAG.getBasicBlock(B.Default));
2065 // Avoid emitting unnecessary branches to the next block.
2066 if (MBB != NextBlock(SwitchBB))
2067 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2068 DAG.getBasicBlock(MBB));
2070 DAG.setRoot(BrRange);
2073 /// visitBitTestCase - this function produces one "bit test"
2074 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2075 MachineBasicBlock* NextMBB,
2076 uint32_t BranchWeightToNext,
2079 MachineBasicBlock *SwitchBB) {
2080 SDLoc dl = getCurSDLoc();
2082 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2084 unsigned PopCount = countPopulation(B.Mask);
2085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2086 if (PopCount == 1) {
2087 // Testing for a single bit; just compare the shift count with what it
2088 // would need to be to shift a 1 bit in that position.
2090 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2091 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2093 } else if (PopCount == BB.Range) {
2094 // There is only one zero bit in the range, test for it directly.
2096 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2097 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2100 // Make desired shift
2101 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2102 DAG.getConstant(1, dl, VT), ShiftOp);
2104 // Emit bit tests and jumps
2105 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2106 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2108 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2109 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2112 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2113 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2114 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2115 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2117 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2118 MVT::Other, getControlRoot(),
2119 Cmp, DAG.getBasicBlock(B.TargetBB));
2121 // Avoid emitting unnecessary branches to the next block.
2122 if (NextMBB != NextBlock(SwitchBB))
2123 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2124 DAG.getBasicBlock(NextMBB));
2129 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2130 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2132 // Retrieve successors. Look through artificial IR level blocks like catchpads
2133 // and catchendpads for successors.
2134 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2135 const BasicBlock *EHPadBB = I.getSuccessor(1);
2137 const Value *Callee(I.getCalledValue());
2138 const Function *Fn = dyn_cast<Function>(Callee);
2139 if (isa<InlineAsm>(Callee))
2141 else if (Fn && Fn->isIntrinsic()) {
2142 switch (Fn->getIntrinsicID()) {
2144 llvm_unreachable("Cannot invoke this intrinsic");
2145 case Intrinsic::donothing:
2146 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2148 case Intrinsic::experimental_patchpoint_void:
2149 case Intrinsic::experimental_patchpoint_i64:
2150 visitPatchpoint(&I, EHPadBB);
2152 case Intrinsic::experimental_gc_statepoint:
2153 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2157 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2159 // If the value of the invoke is used outside of its defining block, make it
2160 // available as a virtual register.
2161 // We already took care of the exported value for the statepoint instruction
2162 // during call to the LowerStatepoint.
2163 if (!isStatepoint(I)) {
2164 CopyToExportRegsIfNeeded(&I);
2167 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
2168 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2169 uint32_t EHPadBBWeight =
2170 BPI ? BPI->getEdgeWeight(InvokeMBB->getBasicBlock(), EHPadBB) : 0;
2171 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBWeight, UnwindDests);
2173 // Update successor info.
2174 addSuccessorWithWeight(InvokeMBB, Return);
2175 for (auto &UnwindDest : UnwindDests) {
2176 UnwindDest.first->setIsEHPad();
2177 addSuccessorWithWeight(InvokeMBB, UnwindDest.first, UnwindDest.second);
2180 // Drop into normal successor.
2181 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2182 MVT::Other, getControlRoot(),
2183 DAG.getBasicBlock(Return)));
2186 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2187 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2190 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2191 assert(FuncInfo.MBB->isEHPad() &&
2192 "Call to landingpad not in landing pad!");
2194 MachineBasicBlock *MBB = FuncInfo.MBB;
2195 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2196 AddLandingPadInfo(LP, MMI, MBB);
2198 // If there aren't registers to copy the values into (e.g., during SjLj
2199 // exceptions), then don't bother to create these DAG nodes.
2200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2201 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2202 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2203 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2206 SmallVector<EVT, 2> ValueVTs;
2207 SDLoc dl = getCurSDLoc();
2208 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2209 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2211 // Get the two live-in registers as SDValues. The physregs have already been
2212 // copied into virtual registers.
2214 if (FuncInfo.ExceptionPointerVirtReg) {
2215 Ops[0] = DAG.getZExtOrTrunc(
2216 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2217 FuncInfo.ExceptionPointerVirtReg,
2218 TLI.getPointerTy(DAG.getDataLayout())),
2221 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2223 Ops[1] = DAG.getZExtOrTrunc(
2224 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2225 FuncInfo.ExceptionSelectorVirtReg,
2226 TLI.getPointerTy(DAG.getDataLayout())),
2230 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2231 DAG.getVTList(ValueVTs), Ops);
2235 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2237 for (const CaseCluster &CC : Clusters)
2238 assert(CC.Low == CC.High && "Input clusters must be single-case");
2241 std::sort(Clusters.begin(), Clusters.end(),
2242 [](const CaseCluster &a, const CaseCluster &b) {
2243 return a.Low->getValue().slt(b.Low->getValue());
2246 // Merge adjacent clusters with the same destination.
2247 const unsigned N = Clusters.size();
2248 unsigned DstIndex = 0;
2249 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2250 CaseCluster &CC = Clusters[SrcIndex];
2251 const ConstantInt *CaseVal = CC.Low;
2252 MachineBasicBlock *Succ = CC.MBB;
2254 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2255 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2256 // If this case has the same successor and is a neighbour, merge it into
2257 // the previous cluster.
2258 Clusters[DstIndex - 1].High = CaseVal;
2259 Clusters[DstIndex - 1].Weight += CC.Weight;
2260 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2262 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2263 sizeof(Clusters[SrcIndex]));
2266 Clusters.resize(DstIndex);
2269 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2270 MachineBasicBlock *Last) {
2272 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2273 if (JTCases[i].first.HeaderBB == First)
2274 JTCases[i].first.HeaderBB = Last;
2276 // Update BitTestCases.
2277 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2278 if (BitTestCases[i].Parent == First)
2279 BitTestCases[i].Parent = Last;
2282 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2283 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2285 // Update machine-CFG edges with unique successors.
2286 SmallSet<BasicBlock*, 32> Done;
2287 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2288 BasicBlock *BB = I.getSuccessor(i);
2289 bool Inserted = Done.insert(BB).second;
2293 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2294 addSuccessorWithWeight(IndirectBrMBB, Succ);
2297 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2298 MVT::Other, getControlRoot(),
2299 getValue(I.getAddress())));
2302 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2303 if (DAG.getTarget().Options.TrapUnreachable)
2305 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2308 void SelectionDAGBuilder::visitFSub(const User &I) {
2309 // -0.0 - X --> fneg
2310 Type *Ty = I.getType();
2311 if (isa<Constant>(I.getOperand(0)) &&
2312 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2313 SDValue Op2 = getValue(I.getOperand(1));
2314 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2315 Op2.getValueType(), Op2));
2319 visitBinary(I, ISD::FSUB);
2322 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2323 SDValue Op1 = getValue(I.getOperand(0));
2324 SDValue Op2 = getValue(I.getOperand(1));
2331 if (const OverflowingBinaryOperator *OFBinOp =
2332 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2333 nuw = OFBinOp->hasNoUnsignedWrap();
2334 nsw = OFBinOp->hasNoSignedWrap();
2336 if (const PossiblyExactOperator *ExactOp =
2337 dyn_cast<const PossiblyExactOperator>(&I))
2338 exact = ExactOp->isExact();
2339 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2340 FMF = FPOp->getFastMathFlags();
2343 Flags.setExact(exact);
2344 Flags.setNoSignedWrap(nsw);
2345 Flags.setNoUnsignedWrap(nuw);
2346 if (EnableFMFInDAG) {
2347 Flags.setAllowReciprocal(FMF.allowReciprocal());
2348 Flags.setNoInfs(FMF.noInfs());
2349 Flags.setNoNaNs(FMF.noNaNs());
2350 Flags.setNoSignedZeros(FMF.noSignedZeros());
2351 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2353 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2355 setValue(&I, BinNodeValue);
2358 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2359 SDValue Op1 = getValue(I.getOperand(0));
2360 SDValue Op2 = getValue(I.getOperand(1));
2362 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2363 Op2.getValueType(), DAG.getDataLayout());
2365 // Coerce the shift amount to the right type if we can.
2366 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2367 unsigned ShiftSize = ShiftTy.getSizeInBits();
2368 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2369 SDLoc DL = getCurSDLoc();
2371 // If the operand is smaller than the shift count type, promote it.
2372 if (ShiftSize > Op2Size)
2373 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2375 // If the operand is larger than the shift count type but the shift
2376 // count type has enough bits to represent any shift value, truncate
2377 // it now. This is a common case and it exposes the truncate to
2378 // optimization early.
2379 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2380 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2381 // Otherwise we'll need to temporarily settle for some other convenient
2382 // type. Type legalization will make adjustments once the shiftee is split.
2384 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2391 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2393 if (const OverflowingBinaryOperator *OFBinOp =
2394 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2395 nuw = OFBinOp->hasNoUnsignedWrap();
2396 nsw = OFBinOp->hasNoSignedWrap();
2398 if (const PossiblyExactOperator *ExactOp =
2399 dyn_cast<const PossiblyExactOperator>(&I))
2400 exact = ExactOp->isExact();
2403 Flags.setExact(exact);
2404 Flags.setNoSignedWrap(nsw);
2405 Flags.setNoUnsignedWrap(nuw);
2406 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2411 void SelectionDAGBuilder::visitSDiv(const User &I) {
2412 SDValue Op1 = getValue(I.getOperand(0));
2413 SDValue Op2 = getValue(I.getOperand(1));
2416 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2417 cast<PossiblyExactOperator>(&I)->isExact());
2418 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2422 void SelectionDAGBuilder::visitICmp(const User &I) {
2423 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2424 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2425 predicate = IC->getPredicate();
2426 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2427 predicate = ICmpInst::Predicate(IC->getPredicate());
2428 SDValue Op1 = getValue(I.getOperand(0));
2429 SDValue Op2 = getValue(I.getOperand(1));
2430 ISD::CondCode Opcode = getICmpCondCode(predicate);
2432 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2434 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2437 void SelectionDAGBuilder::visitFCmp(const User &I) {
2438 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2439 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2440 predicate = FC->getPredicate();
2441 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2442 predicate = FCmpInst::Predicate(FC->getPredicate());
2443 SDValue Op1 = getValue(I.getOperand(0));
2444 SDValue Op2 = getValue(I.getOperand(1));
2445 ISD::CondCode Condition = getFCmpCondCode(predicate);
2447 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2448 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2449 // further optimization, but currently FMF is only applicable to binary nodes.
2450 if (TM.Options.NoNaNsFPMath)
2451 Condition = getFCmpCodeWithoutNaN(Condition);
2452 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2454 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2457 void SelectionDAGBuilder::visitSelect(const User &I) {
2458 SmallVector<EVT, 4> ValueVTs;
2459 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2461 unsigned NumValues = ValueVTs.size();
2462 if (NumValues == 0) return;
2464 SmallVector<SDValue, 4> Values(NumValues);
2465 SDValue Cond = getValue(I.getOperand(0));
2466 SDValue LHSVal = getValue(I.getOperand(1));
2467 SDValue RHSVal = getValue(I.getOperand(2));
2468 auto BaseOps = {Cond};
2469 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2470 ISD::VSELECT : ISD::SELECT;
2472 // Min/max matching is only viable if all output VTs are the same.
2473 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2474 EVT VT = ValueVTs[0];
2475 LLVMContext &Ctx = *DAG.getContext();
2476 auto &TLI = DAG.getTargetLoweringInfo();
2477 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2478 VT = TLI.getTypeToTransformTo(Ctx, VT);
2481 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2482 ISD::NodeType Opc = ISD::DELETED_NODE;
2483 switch (SPR.Flavor) {
2484 case SPF_UMAX: Opc = ISD::UMAX; break;
2485 case SPF_UMIN: Opc = ISD::UMIN; break;
2486 case SPF_SMAX: Opc = ISD::SMAX; break;
2487 case SPF_SMIN: Opc = ISD::SMIN; break;
2489 switch (SPR.NaNBehavior) {
2490 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2491 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2492 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2493 case SPNB_RETURNS_ANY:
2494 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2500 switch (SPR.NaNBehavior) {
2501 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2502 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2503 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2504 case SPNB_RETURNS_ANY:
2505 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2513 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2514 // If the underlying comparison instruction is used by any other instruction,
2515 // the consumed instructions won't be destroyed, so it is not profitable
2516 // to convert to a min/max.
2517 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2519 LHSVal = getValue(LHS);
2520 RHSVal = getValue(RHS);
2525 for (unsigned i = 0; i != NumValues; ++i) {
2526 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2527 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2528 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2529 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2530 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2534 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2535 DAG.getVTList(ValueVTs), Values));
2538 void SelectionDAGBuilder::visitTrunc(const User &I) {
2539 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2540 SDValue N = getValue(I.getOperand(0));
2541 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2543 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2546 void SelectionDAGBuilder::visitZExt(const User &I) {
2547 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2548 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2549 SDValue N = getValue(I.getOperand(0));
2550 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2552 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2555 void SelectionDAGBuilder::visitSExt(const User &I) {
2556 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2557 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2558 SDValue N = getValue(I.getOperand(0));
2559 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2561 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2564 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2565 // FPTrunc is never a no-op cast, no need to check
2566 SDValue N = getValue(I.getOperand(0));
2567 SDLoc dl = getCurSDLoc();
2568 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2569 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2570 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2571 DAG.getTargetConstant(
2572 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2575 void SelectionDAGBuilder::visitFPExt(const User &I) {
2576 // FPExt is never a no-op cast, no need to check
2577 SDValue N = getValue(I.getOperand(0));
2578 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2580 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2583 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2584 // FPToUI is never a no-op cast, no need to check
2585 SDValue N = getValue(I.getOperand(0));
2586 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2588 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2591 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2592 // FPToSI is never a no-op cast, no need to check
2593 SDValue N = getValue(I.getOperand(0));
2594 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2596 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2599 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2600 // UIToFP is never a no-op cast, no need to check
2601 SDValue N = getValue(I.getOperand(0));
2602 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2604 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2607 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2608 // SIToFP is never a no-op cast, no need to check
2609 SDValue N = getValue(I.getOperand(0));
2610 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2612 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2615 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2616 // What to do depends on the size of the integer and the size of the pointer.
2617 // We can either truncate, zero extend, or no-op, accordingly.
2618 SDValue N = getValue(I.getOperand(0));
2619 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2621 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2624 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2625 // What to do depends on the size of the integer and the size of the pointer.
2626 // We can either truncate, zero extend, or no-op, accordingly.
2627 SDValue N = getValue(I.getOperand(0));
2628 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2630 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2633 void SelectionDAGBuilder::visitBitCast(const User &I) {
2634 SDValue N = getValue(I.getOperand(0));
2635 SDLoc dl = getCurSDLoc();
2636 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2639 // BitCast assures us that source and destination are the same size so this is
2640 // either a BITCAST or a no-op.
2641 if (DestVT != N.getValueType())
2642 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2643 DestVT, N)); // convert types.
2644 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2645 // might fold any kind of constant expression to an integer constant and that
2646 // is not what we are looking for. Only regcognize a bitcast of a genuine
2647 // constant integer as an opaque constant.
2648 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2649 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2652 setValue(&I, N); // noop cast.
2655 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2656 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2657 const Value *SV = I.getOperand(0);
2658 SDValue N = getValue(SV);
2659 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2661 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2662 unsigned DestAS = I.getType()->getPointerAddressSpace();
2664 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2665 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2670 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2671 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2672 SDValue InVec = getValue(I.getOperand(0));
2673 SDValue InVal = getValue(I.getOperand(1));
2674 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2675 TLI.getVectorIdxTy(DAG.getDataLayout()));
2676 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2677 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2678 InVec, InVal, InIdx));
2681 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2683 SDValue InVec = getValue(I.getOperand(0));
2684 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2685 TLI.getVectorIdxTy(DAG.getDataLayout()));
2686 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2687 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2691 // Utility for visitShuffleVector - Return true if every element in Mask,
2692 // beginning from position Pos and ending in Pos+Size, falls within the
2693 // specified sequential range [L, L+Pos). or is undef.
2694 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2695 unsigned Pos, unsigned Size, int Low) {
2696 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2697 if (Mask[i] >= 0 && Mask[i] != Low)
2702 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2703 SDValue Src1 = getValue(I.getOperand(0));
2704 SDValue Src2 = getValue(I.getOperand(1));
2706 SmallVector<int, 8> Mask;
2707 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2708 unsigned MaskNumElts = Mask.size();
2710 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2711 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2712 EVT SrcVT = Src1.getValueType();
2713 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2715 if (SrcNumElts == MaskNumElts) {
2716 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2721 // Normalize the shuffle vector since mask and vector length don't match.
2722 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2723 // Mask is longer than the source vectors and is a multiple of the source
2724 // vectors. We can use concatenate vector to make the mask and vectors
2726 if (SrcNumElts*2 == MaskNumElts) {
2727 // First check for Src1 in low and Src2 in high
2728 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2729 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2730 // The shuffle is concatenating two vectors together.
2731 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2735 // Then check for Src2 in low and Src1 in high
2736 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2737 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2738 // The shuffle is concatenating two vectors together.
2739 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2745 // Pad both vectors with undefs to make them the same length as the mask.
2746 unsigned NumConcat = MaskNumElts / SrcNumElts;
2747 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2748 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2749 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2751 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2752 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2756 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2757 getCurSDLoc(), VT, MOps1);
2758 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2759 getCurSDLoc(), VT, MOps2);
2761 // Readjust mask for new input vector length.
2762 SmallVector<int, 8> MappedOps;
2763 for (unsigned i = 0; i != MaskNumElts; ++i) {
2765 if (Idx >= (int)SrcNumElts)
2766 Idx -= SrcNumElts - MaskNumElts;
2767 MappedOps.push_back(Idx);
2770 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2775 if (SrcNumElts > MaskNumElts) {
2776 // Analyze the access pattern of the vector to see if we can extract
2777 // two subvectors and do the shuffle. The analysis is done by calculating
2778 // the range of elements the mask access on both vectors.
2779 int MinRange[2] = { static_cast<int>(SrcNumElts),
2780 static_cast<int>(SrcNumElts)};
2781 int MaxRange[2] = {-1, -1};
2783 for (unsigned i = 0; i != MaskNumElts; ++i) {
2789 if (Idx >= (int)SrcNumElts) {
2793 if (Idx > MaxRange[Input])
2794 MaxRange[Input] = Idx;
2795 if (Idx < MinRange[Input])
2796 MinRange[Input] = Idx;
2799 // Check if the access is smaller than the vector size and can we find
2800 // a reasonable extract index.
2801 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2803 int StartIdx[2]; // StartIdx to extract from
2804 for (unsigned Input = 0; Input < 2; ++Input) {
2805 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2806 RangeUse[Input] = 0; // Unused
2807 StartIdx[Input] = 0;
2811 // Find a good start index that is a multiple of the mask length. Then
2812 // see if the rest of the elements are in range.
2813 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2814 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2815 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2816 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2819 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2820 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2823 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2824 // Extract appropriate subvector and generate a vector shuffle
2825 for (unsigned Input = 0; Input < 2; ++Input) {
2826 SDValue &Src = Input == 0 ? Src1 : Src2;
2827 if (RangeUse[Input] == 0)
2828 Src = DAG.getUNDEF(VT);
2830 SDLoc dl = getCurSDLoc();
2832 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2833 DAG.getConstant(StartIdx[Input], dl,
2834 TLI.getVectorIdxTy(DAG.getDataLayout())));
2838 // Calculate new mask.
2839 SmallVector<int, 8> MappedOps;
2840 for (unsigned i = 0; i != MaskNumElts; ++i) {
2843 if (Idx < (int)SrcNumElts)
2846 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2848 MappedOps.push_back(Idx);
2851 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2857 // We can't use either concat vectors or extract subvectors so fall back to
2858 // replacing the shuffle with extract and build vector.
2859 // to insert and build vector.
2860 EVT EltVT = VT.getVectorElementType();
2861 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2862 SDLoc dl = getCurSDLoc();
2863 SmallVector<SDValue,8> Ops;
2864 for (unsigned i = 0; i != MaskNumElts; ++i) {
2869 Res = DAG.getUNDEF(EltVT);
2871 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2872 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2874 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2875 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2881 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2884 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2885 const Value *Op0 = I.getOperand(0);
2886 const Value *Op1 = I.getOperand(1);
2887 Type *AggTy = I.getType();
2888 Type *ValTy = Op1->getType();
2889 bool IntoUndef = isa<UndefValue>(Op0);
2890 bool FromUndef = isa<UndefValue>(Op1);
2892 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2894 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2895 SmallVector<EVT, 4> AggValueVTs;
2896 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2897 SmallVector<EVT, 4> ValValueVTs;
2898 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2900 unsigned NumAggValues = AggValueVTs.size();
2901 unsigned NumValValues = ValValueVTs.size();
2902 SmallVector<SDValue, 4> Values(NumAggValues);
2904 // Ignore an insertvalue that produces an empty object
2905 if (!NumAggValues) {
2906 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2910 SDValue Agg = getValue(Op0);
2912 // Copy the beginning value(s) from the original aggregate.
2913 for (; i != LinearIndex; ++i)
2914 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2915 SDValue(Agg.getNode(), Agg.getResNo() + i);
2916 // Copy values from the inserted value(s).
2918 SDValue Val = getValue(Op1);
2919 for (; i != LinearIndex + NumValValues; ++i)
2920 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2921 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2923 // Copy remaining value(s) from the original aggregate.
2924 for (; i != NumAggValues; ++i)
2925 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2926 SDValue(Agg.getNode(), Agg.getResNo() + i);
2928 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2929 DAG.getVTList(AggValueVTs), Values));
2932 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2933 const Value *Op0 = I.getOperand(0);
2934 Type *AggTy = Op0->getType();
2935 Type *ValTy = I.getType();
2936 bool OutOfUndef = isa<UndefValue>(Op0);
2938 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2940 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2941 SmallVector<EVT, 4> ValValueVTs;
2942 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2944 unsigned NumValValues = ValValueVTs.size();
2946 // Ignore a extractvalue that produces an empty object
2947 if (!NumValValues) {
2948 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2952 SmallVector<SDValue, 4> Values(NumValValues);
2954 SDValue Agg = getValue(Op0);
2955 // Copy out the selected value(s).
2956 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2957 Values[i - LinearIndex] =
2959 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2960 SDValue(Agg.getNode(), Agg.getResNo() + i);
2962 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2963 DAG.getVTList(ValValueVTs), Values));
2966 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2967 Value *Op0 = I.getOperand(0);
2968 // Note that the pointer operand may be a vector of pointers. Take the scalar
2969 // element which holds a pointer.
2970 Type *Ty = Op0->getType()->getScalarType();
2971 unsigned AS = Ty->getPointerAddressSpace();
2972 SDValue N = getValue(Op0);
2973 SDLoc dl = getCurSDLoc();
2975 // Normalize Vector GEP - all scalar operands should be converted to the
2977 unsigned VectorWidth = I.getType()->isVectorTy() ?
2978 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2980 if (VectorWidth && !N.getValueType().isVector()) {
2981 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2982 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2983 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2985 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2987 const Value *Idx = *OI;
2988 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2989 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2992 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2993 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2994 DAG.getConstant(Offset, dl, N.getValueType()));
2997 Ty = StTy->getElementType(Field);
2999 Ty = cast<SequentialType>(Ty)->getElementType();
3001 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
3002 unsigned PtrSize = PtrTy.getSizeInBits();
3003 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3005 // If this is a scalar constant or a splat vector of constants,
3006 // handle it quickly.
3007 const auto *CI = dyn_cast<ConstantInt>(Idx);
3008 if (!CI && isa<ConstantDataVector>(Idx) &&
3009 cast<ConstantDataVector>(Idx)->getSplatValue())
3010 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3015 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3016 SDValue OffsVal = VectorWidth ?
3017 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
3018 DAG.getConstant(Offs, dl, PtrTy);
3019 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
3023 // N = N + Idx * ElementSize;
3024 SDValue IdxN = getValue(Idx);
3026 if (!IdxN.getValueType().isVector() && VectorWidth) {
3027 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3028 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3029 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3031 // If the index is smaller or larger than intptr_t, truncate or extend
3033 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3035 // If this is a multiply by a power of two, turn it into a shl
3036 // immediately. This is a very common case.
3037 if (ElementSize != 1) {
3038 if (ElementSize.isPowerOf2()) {
3039 unsigned Amt = ElementSize.logBase2();
3040 IdxN = DAG.getNode(ISD::SHL, dl,
3041 N.getValueType(), IdxN,
3042 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3044 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3045 IdxN = DAG.getNode(ISD::MUL, dl,
3046 N.getValueType(), IdxN, Scale);
3050 N = DAG.getNode(ISD::ADD, dl,
3051 N.getValueType(), N, IdxN);
3058 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3059 // If this is a fixed sized alloca in the entry block of the function,
3060 // allocate it statically on the stack.
3061 if (FuncInfo.StaticAllocaMap.count(&I))
3062 return; // getValue will auto-populate this.
3064 SDLoc dl = getCurSDLoc();
3065 Type *Ty = I.getAllocatedType();
3066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3067 auto &DL = DAG.getDataLayout();
3068 uint64_t TySize = DL.getTypeAllocSize(Ty);
3070 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3072 SDValue AllocSize = getValue(I.getArraySize());
3074 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3075 if (AllocSize.getValueType() != IntPtr)
3076 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3078 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3080 DAG.getConstant(TySize, dl, IntPtr));
3082 // Handle alignment. If the requested alignment is less than or equal to
3083 // the stack alignment, ignore it. If the size is greater than or equal to
3084 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3085 unsigned StackAlign =
3086 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3087 if (Align <= StackAlign)
3090 // Round the size of the allocation up to the stack alignment size
3091 // by add SA-1 to the size.
3092 AllocSize = DAG.getNode(ISD::ADD, dl,
3093 AllocSize.getValueType(), AllocSize,
3094 DAG.getIntPtrConstant(StackAlign - 1, dl));
3096 // Mask out the low bits for alignment purposes.
3097 AllocSize = DAG.getNode(ISD::AND, dl,
3098 AllocSize.getValueType(), AllocSize,
3099 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3102 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3103 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3104 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3106 DAG.setRoot(DSA.getValue(1));
3108 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3111 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3113 return visitAtomicLoad(I);
3115 const Value *SV = I.getOperand(0);
3116 SDValue Ptr = getValue(SV);
3118 Type *Ty = I.getType();
3120 bool isVolatile = I.isVolatile();
3121 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3123 // The IR notion of invariant_load only guarantees that all *non-faulting*
3124 // invariant loads result in the same value. The MI notion of invariant load
3125 // guarantees that the load can be legally moved to any location within its
3126 // containing function. The MI notion of invariant_load is stronger than the
3127 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3128 // with a guarantee that the location being loaded from is dereferenceable
3129 // throughout the function's lifetime.
3131 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3132 isDereferenceablePointer(SV, DAG.getDataLayout());
3133 unsigned Alignment = I.getAlignment();
3136 I.getAAMetadata(AAInfo);
3137 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3139 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3140 SmallVector<EVT, 4> ValueVTs;
3141 SmallVector<uint64_t, 4> Offsets;
3142 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3143 unsigned NumValues = ValueVTs.size();
3148 bool ConstantMemory = false;
3149 if (isVolatile || NumValues > MaxParallelChains)
3150 // Serialize volatile loads with other side effects.
3152 else if (AA->pointsToConstantMemory(MemoryLocation(
3153 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3154 // Do not serialize (non-volatile) loads of constant memory with anything.
3155 Root = DAG.getEntryNode();
3156 ConstantMemory = true;
3158 // Do not serialize non-volatile loads against each other.
3159 Root = DAG.getRoot();
3162 SDLoc dl = getCurSDLoc();
3165 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3167 SmallVector<SDValue, 4> Values(NumValues);
3168 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3169 EVT PtrVT = Ptr.getValueType();
3170 unsigned ChainI = 0;
3171 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3172 // Serializing loads here may result in excessive register pressure, and
3173 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3174 // could recover a bit by hoisting nodes upward in the chain by recognizing
3175 // they are side-effect free or do not alias. The optimizer should really
3176 // avoid this case by converting large object/array copies to llvm.memcpy
3177 // (MaxParallelChains should always remain as failsafe).
3178 if (ChainI == MaxParallelChains) {
3179 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3180 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3181 makeArrayRef(Chains.data(), ChainI));
3185 SDValue A = DAG.getNode(ISD::ADD, dl,
3187 DAG.getConstant(Offsets[i], dl, PtrVT));
3188 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3189 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3190 isNonTemporal, isInvariant, Alignment, AAInfo,
3194 Chains[ChainI] = L.getValue(1);
3197 if (!ConstantMemory) {
3198 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3199 makeArrayRef(Chains.data(), ChainI));
3203 PendingLoads.push_back(Chain);
3206 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3207 DAG.getVTList(ValueVTs), Values));
3210 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3212 return visitAtomicStore(I);
3214 const Value *SrcV = I.getOperand(0);
3215 const Value *PtrV = I.getOperand(1);
3217 SmallVector<EVT, 4> ValueVTs;
3218 SmallVector<uint64_t, 4> Offsets;
3219 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3220 SrcV->getType(), ValueVTs, &Offsets);
3221 unsigned NumValues = ValueVTs.size();
3225 // Get the lowered operands. Note that we do this after
3226 // checking if NumResults is zero, because with zero results
3227 // the operands won't have values in the map.
3228 SDValue Src = getValue(SrcV);
3229 SDValue Ptr = getValue(PtrV);
3231 SDValue Root = getRoot();
3232 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3233 EVT PtrVT = Ptr.getValueType();
3234 bool isVolatile = I.isVolatile();
3235 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3236 unsigned Alignment = I.getAlignment();
3237 SDLoc dl = getCurSDLoc();
3240 I.getAAMetadata(AAInfo);
3242 unsigned ChainI = 0;
3243 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3244 // See visitLoad comments.
3245 if (ChainI == MaxParallelChains) {
3246 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3247 makeArrayRef(Chains.data(), ChainI));
3251 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3252 DAG.getConstant(Offsets[i], dl, PtrVT));
3253 SDValue St = DAG.getStore(Root, dl,
3254 SDValue(Src.getNode(), Src.getResNo() + i),
3255 Add, MachinePointerInfo(PtrV, Offsets[i]),
3256 isVolatile, isNonTemporal, Alignment, AAInfo);
3257 Chains[ChainI] = St;
3260 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3261 makeArrayRef(Chains.data(), ChainI));
3262 DAG.setRoot(StoreNode);
3265 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3266 SDLoc sdl = getCurSDLoc();
3268 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3269 Value *PtrOperand = I.getArgOperand(1);
3270 SDValue Ptr = getValue(PtrOperand);
3271 SDValue Src0 = getValue(I.getArgOperand(0));
3272 SDValue Mask = getValue(I.getArgOperand(3));
3273 EVT VT = Src0.getValueType();
3274 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3276 Alignment = DAG.getEVTAlignment(VT);
3279 I.getAAMetadata(AAInfo);
3281 MachineMemOperand *MMO =
3282 DAG.getMachineFunction().
3283 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3284 MachineMemOperand::MOStore, VT.getStoreSize(),
3286 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3288 DAG.setRoot(StoreNode);
3289 setValue(&I, StoreNode);
3292 // Get a uniform base for the Gather/Scatter intrinsic.
3293 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3294 // We try to represent it as a base pointer + vector of indices.
3295 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3296 // The first operand of the GEP may be a single pointer or a vector of pointers
3298 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3300 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3301 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3303 // When the first GEP operand is a single pointer - it is the uniform base we
3304 // are looking for. If first operand of the GEP is a splat vector - we
3305 // extract the spalt value and use it as a uniform base.
3306 // In all other cases the function returns 'false'.
3308 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3309 SelectionDAGBuilder* SDB) {
3311 SelectionDAG& DAG = SDB->DAG;
3312 LLVMContext &Context = *DAG.getContext();
3314 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3315 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3316 if (!GEP || GEP->getNumOperands() > 2)
3319 Value *GEPPtr = GEP->getPointerOperand();
3320 if (!GEPPtr->getType()->isVectorTy())
3322 else if (!(Ptr = getSplatValue(GEPPtr)))
3325 Value *IndexVal = GEP->getOperand(1);
3327 // The operands of the GEP may be defined in another basic block.
3328 // In this case we'll not find nodes for the operands.
3329 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3332 Base = SDB->getValue(Ptr);
3333 Index = SDB->getValue(IndexVal);
3335 // Suppress sign extension.
3336 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3337 if (SDB->findValue(Sext->getOperand(0))) {
3338 IndexVal = Sext->getOperand(0);
3339 Index = SDB->getValue(IndexVal);
3342 if (!Index.getValueType().isVector()) {
3343 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3344 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3345 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3346 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3351 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3352 SDLoc sdl = getCurSDLoc();
3354 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3355 Value *Ptr = I.getArgOperand(1);
3356 SDValue Src0 = getValue(I.getArgOperand(0));
3357 SDValue Mask = getValue(I.getArgOperand(3));
3358 EVT VT = Src0.getValueType();
3359 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3361 Alignment = DAG.getEVTAlignment(VT);
3362 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3365 I.getAAMetadata(AAInfo);
3369 Value *BasePtr = Ptr;
3370 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3372 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3373 MachineMemOperand *MMO = DAG.getMachineFunction().
3374 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3375 MachineMemOperand::MOStore, VT.getStoreSize(),
3378 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3379 Index = getValue(Ptr);
3381 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3382 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3384 DAG.setRoot(Scatter);
3385 setValue(&I, Scatter);
3388 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3389 SDLoc sdl = getCurSDLoc();
3391 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3392 Value *PtrOperand = I.getArgOperand(0);
3393 SDValue Ptr = getValue(PtrOperand);
3394 SDValue Src0 = getValue(I.getArgOperand(3));
3395 SDValue Mask = getValue(I.getArgOperand(2));
3397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3398 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3399 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3401 Alignment = DAG.getEVTAlignment(VT);
3404 I.getAAMetadata(AAInfo);
3405 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3407 SDValue InChain = DAG.getRoot();
3408 if (AA->pointsToConstantMemory(MemoryLocation(
3409 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3411 // Do not serialize (non-volatile) loads of constant memory with anything.
3412 InChain = DAG.getEntryNode();
3415 MachineMemOperand *MMO =
3416 DAG.getMachineFunction().
3417 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3418 MachineMemOperand::MOLoad, VT.getStoreSize(),
3419 Alignment, AAInfo, Ranges);
3421 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3423 SDValue OutChain = Load.getValue(1);
3424 DAG.setRoot(OutChain);
3428 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3429 SDLoc sdl = getCurSDLoc();
3431 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3432 Value *Ptr = I.getArgOperand(0);
3433 SDValue Src0 = getValue(I.getArgOperand(3));
3434 SDValue Mask = getValue(I.getArgOperand(2));
3436 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3437 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3438 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3440 Alignment = DAG.getEVTAlignment(VT);
3443 I.getAAMetadata(AAInfo);
3444 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3446 SDValue Root = DAG.getRoot();
3449 Value *BasePtr = Ptr;
3450 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3451 bool ConstantMemory = false;
3453 AA->pointsToConstantMemory(MemoryLocation(
3454 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3456 // Do not serialize (non-volatile) loads of constant memory with anything.
3457 Root = DAG.getEntryNode();
3458 ConstantMemory = true;
3461 MachineMemOperand *MMO =
3462 DAG.getMachineFunction().
3463 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3464 MachineMemOperand::MOLoad, VT.getStoreSize(),
3465 Alignment, AAInfo, Ranges);
3468 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3469 Index = getValue(Ptr);
3471 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3472 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3475 SDValue OutChain = Gather.getValue(1);
3476 if (!ConstantMemory)
3477 PendingLoads.push_back(OutChain);
3478 setValue(&I, Gather);
3481 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3482 SDLoc dl = getCurSDLoc();
3483 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3484 AtomicOrdering FailureOrder = I.getFailureOrdering();
3485 SynchronizationScope Scope = I.getSynchScope();
3487 SDValue InChain = getRoot();
3489 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3490 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3491 SDValue L = DAG.getAtomicCmpSwap(
3492 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3493 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3494 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3495 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3497 SDValue OutChain = L.getValue(2);
3500 DAG.setRoot(OutChain);
3503 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3504 SDLoc dl = getCurSDLoc();
3506 switch (I.getOperation()) {
3507 default: llvm_unreachable("Unknown atomicrmw operation");
3508 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3509 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3510 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3511 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3512 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3513 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3514 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3515 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3516 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3517 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3518 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3520 AtomicOrdering Order = I.getOrdering();
3521 SynchronizationScope Scope = I.getSynchScope();
3523 SDValue InChain = getRoot();
3526 DAG.getAtomic(NT, dl,
3527 getValue(I.getValOperand()).getSimpleValueType(),
3529 getValue(I.getPointerOperand()),
3530 getValue(I.getValOperand()),
3531 I.getPointerOperand(),
3532 /* Alignment=*/ 0, Order, Scope);
3534 SDValue OutChain = L.getValue(1);
3537 DAG.setRoot(OutChain);
3540 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3541 SDLoc dl = getCurSDLoc();
3542 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3545 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3546 TLI.getPointerTy(DAG.getDataLayout()));
3547 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3548 TLI.getPointerTy(DAG.getDataLayout()));
3549 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3552 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3553 SDLoc dl = getCurSDLoc();
3554 AtomicOrdering Order = I.getOrdering();
3555 SynchronizationScope Scope = I.getSynchScope();
3557 SDValue InChain = getRoot();
3559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3560 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3562 if (I.getAlignment() < VT.getSizeInBits() / 8)
3563 report_fatal_error("Cannot generate unaligned atomic load");
3565 MachineMemOperand *MMO =
3566 DAG.getMachineFunction().
3567 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3568 MachineMemOperand::MOVolatile |
3569 MachineMemOperand::MOLoad,
3571 I.getAlignment() ? I.getAlignment() :
3572 DAG.getEVTAlignment(VT));
3574 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3576 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3577 getValue(I.getPointerOperand()), MMO,
3580 SDValue OutChain = L.getValue(1);
3583 DAG.setRoot(OutChain);
3586 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3587 SDLoc dl = getCurSDLoc();
3589 AtomicOrdering Order = I.getOrdering();
3590 SynchronizationScope Scope = I.getSynchScope();
3592 SDValue InChain = getRoot();
3594 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3596 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3598 if (I.getAlignment() < VT.getSizeInBits() / 8)
3599 report_fatal_error("Cannot generate unaligned atomic store");
3602 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3604 getValue(I.getPointerOperand()),
3605 getValue(I.getValueOperand()),
3606 I.getPointerOperand(), I.getAlignment(),
3609 DAG.setRoot(OutChain);
3612 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3614 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3615 unsigned Intrinsic) {
3616 bool HasChain = !I.doesNotAccessMemory();
3617 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3619 // Build the operand list.
3620 SmallVector<SDValue, 8> Ops;
3621 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3623 // We don't need to serialize loads against other loads.
3624 Ops.push_back(DAG.getRoot());
3626 Ops.push_back(getRoot());
3630 // Info is set by getTgtMemInstrinsic
3631 TargetLowering::IntrinsicInfo Info;
3632 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3633 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3635 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3636 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3637 Info.opc == ISD::INTRINSIC_W_CHAIN)
3638 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3639 TLI.getPointerTy(DAG.getDataLayout())));
3641 // Add all operands of the call to the operand list.
3642 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3643 SDValue Op = getValue(I.getArgOperand(i));
3647 SmallVector<EVT, 4> ValueVTs;
3648 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3651 ValueVTs.push_back(MVT::Other);
3653 SDVTList VTs = DAG.getVTList(ValueVTs);
3657 if (IsTgtIntrinsic) {
3658 // This is target intrinsic that touches memory
3659 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3660 VTs, Ops, Info.memVT,
3661 MachinePointerInfo(Info.ptrVal, Info.offset),
3662 Info.align, Info.vol,
3663 Info.readMem, Info.writeMem, Info.size);
3664 } else if (!HasChain) {
3665 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3666 } else if (!I.getType()->isVoidTy()) {
3667 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3669 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3673 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3675 PendingLoads.push_back(Chain);
3680 if (!I.getType()->isVoidTy()) {
3681 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3682 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3683 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3686 setValue(&I, Result);
3690 /// GetSignificand - Get the significand and build it into a floating-point
3691 /// number with exponent of 1:
3693 /// Op = (Op & 0x007fffff) | 0x3f800000;
3695 /// where Op is the hexadecimal representation of floating point value.
3697 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3698 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3699 DAG.getConstant(0x007fffff, dl, MVT::i32));
3700 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3701 DAG.getConstant(0x3f800000, dl, MVT::i32));
3702 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3705 /// GetExponent - Get the exponent:
3707 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3709 /// where Op is the hexadecimal representation of floating point value.
3711 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3713 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3714 DAG.getConstant(0x7f800000, dl, MVT::i32));
3715 SDValue t1 = DAG.getNode(
3716 ISD::SRL, dl, MVT::i32, t0,
3717 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3718 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3719 DAG.getConstant(127, dl, MVT::i32));
3720 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3723 /// getF32Constant - Get 32-bit floating point constant.
3725 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3726 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3730 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3731 SelectionDAG &DAG) {
3732 // TODO: What fast-math-flags should be set on the floating-point nodes?
3734 // IntegerPartOfX = ((int32_t)(t0);
3735 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3737 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3738 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3739 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3741 // IntegerPartOfX <<= 23;
3742 IntegerPartOfX = DAG.getNode(
3743 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3744 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3745 DAG.getDataLayout())));
3747 SDValue TwoToFractionalPartOfX;
3748 if (LimitFloatPrecision <= 6) {
3749 // For floating-point precision of 6:
3751 // TwoToFractionalPartOfX =
3753 // (0.735607626f + 0.252464424f * x) * x;
3755 // error 0.0144103317, which is 6 bits
3756 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3757 getF32Constant(DAG, 0x3e814304, dl));
3758 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3759 getF32Constant(DAG, 0x3f3c50c8, dl));
3760 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3761 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3762 getF32Constant(DAG, 0x3f7f5e7e, dl));
3763 } else if (LimitFloatPrecision <= 12) {
3764 // For floating-point precision of 12:
3766 // TwoToFractionalPartOfX =
3769 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3771 // error 0.000107046256, which is 13 to 14 bits
3772 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3773 getF32Constant(DAG, 0x3da235e3, dl));
3774 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3775 getF32Constant(DAG, 0x3e65b8f3, dl));
3776 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3777 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3778 getF32Constant(DAG, 0x3f324b07, dl));
3779 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3780 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3781 getF32Constant(DAG, 0x3f7ff8fd, dl));
3782 } else { // LimitFloatPrecision <= 18
3783 // For floating-point precision of 18:
3785 // TwoToFractionalPartOfX =
3789 // (0.554906021e-1f +
3790 // (0.961591928e-2f +
3791 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3792 // error 2.47208000*10^(-7), which is better than 18 bits
3793 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3794 getF32Constant(DAG, 0x3924b03e, dl));
3795 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3796 getF32Constant(DAG, 0x3ab24b87, dl));
3797 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3798 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3799 getF32Constant(DAG, 0x3c1d8c17, dl));
3800 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3801 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3802 getF32Constant(DAG, 0x3d634a1d, dl));
3803 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3804 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3805 getF32Constant(DAG, 0x3e75fe14, dl));
3806 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3807 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3808 getF32Constant(DAG, 0x3f317234, dl));
3809 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3810 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3811 getF32Constant(DAG, 0x3f800000, dl));
3814 // Add the exponent into the result in integer domain.
3815 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3816 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3817 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3820 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3821 /// limited-precision mode.
3822 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3823 const TargetLowering &TLI) {
3824 if (Op.getValueType() == MVT::f32 &&
3825 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3827 // Put the exponent in the right bit position for later addition to the
3830 // #define LOG2OFe 1.4426950f
3831 // t0 = Op * LOG2OFe
3833 // TODO: What fast-math-flags should be set here?
3834 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3835 getF32Constant(DAG, 0x3fb8aa3b, dl));
3836 return getLimitedPrecisionExp2(t0, dl, DAG);
3839 // No special expansion.
3840 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3843 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3844 /// limited-precision mode.
3845 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3846 const TargetLowering &TLI) {
3848 // TODO: What fast-math-flags should be set on the floating-point nodes?
3850 if (Op.getValueType() == MVT::f32 &&
3851 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3852 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3854 // Scale the exponent by log(2) [0.69314718f].
3855 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3856 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3857 getF32Constant(DAG, 0x3f317218, dl));
3859 // Get the significand and build it into a floating-point number with
3861 SDValue X = GetSignificand(DAG, Op1, dl);
3863 SDValue LogOfMantissa;
3864 if (LimitFloatPrecision <= 6) {
3865 // For floating-point precision of 6:
3869 // (1.4034025f - 0.23903021f * x) * x;
3871 // error 0.0034276066, which is better than 8 bits
3872 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3873 getF32Constant(DAG, 0xbe74c456, dl));
3874 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3875 getF32Constant(DAG, 0x3fb3a2b1, dl));
3876 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3877 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3878 getF32Constant(DAG, 0x3f949a29, dl));
3879 } else if (LimitFloatPrecision <= 12) {
3880 // For floating-point precision of 12:
3886 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3888 // error 0.000061011436, which is 14 bits
3889 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3890 getF32Constant(DAG, 0xbd67b6d6, dl));
3891 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3892 getF32Constant(DAG, 0x3ee4f4b8, dl));
3893 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3894 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3895 getF32Constant(DAG, 0x3fbc278b, dl));
3896 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3897 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3898 getF32Constant(DAG, 0x40348e95, dl));
3899 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3900 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3901 getF32Constant(DAG, 0x3fdef31a, dl));
3902 } else { // LimitFloatPrecision <= 18
3903 // For floating-point precision of 18:
3911 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3913 // error 0.0000023660568, which is better than 18 bits
3914 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3915 getF32Constant(DAG, 0xbc91e5ac, dl));
3916 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3917 getF32Constant(DAG, 0x3e4350aa, dl));
3918 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3919 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3920 getF32Constant(DAG, 0x3f60d3e3, dl));
3921 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3922 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3923 getF32Constant(DAG, 0x4011cdf0, dl));
3924 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3925 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3926 getF32Constant(DAG, 0x406cfd1c, dl));
3927 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3928 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3929 getF32Constant(DAG, 0x408797cb, dl));
3930 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3931 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3932 getF32Constant(DAG, 0x4006dcab, dl));
3935 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3938 // No special expansion.
3939 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3942 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3943 /// limited-precision mode.
3944 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3945 const TargetLowering &TLI) {
3947 // TODO: What fast-math-flags should be set on the floating-point nodes?
3949 if (Op.getValueType() == MVT::f32 &&
3950 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3951 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3953 // Get the exponent.
3954 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3956 // Get the significand and build it into a floating-point number with
3958 SDValue X = GetSignificand(DAG, Op1, dl);
3960 // Different possible minimax approximations of significand in
3961 // floating-point for various degrees of accuracy over [1,2].
3962 SDValue Log2ofMantissa;
3963 if (LimitFloatPrecision <= 6) {
3964 // For floating-point precision of 6:
3966 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3968 // error 0.0049451742, which is more than 7 bits
3969 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3970 getF32Constant(DAG, 0xbeb08fe0, dl));
3971 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3972 getF32Constant(DAG, 0x40019463, dl));
3973 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3974 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3975 getF32Constant(DAG, 0x3fd6633d, dl));
3976 } else if (LimitFloatPrecision <= 12) {
3977 // For floating-point precision of 12:
3983 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3985 // error 0.0000876136000, which is better than 13 bits
3986 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3987 getF32Constant(DAG, 0xbda7262e, dl));
3988 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3989 getF32Constant(DAG, 0x3f25280b, dl));
3990 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3991 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3992 getF32Constant(DAG, 0x4007b923, dl));
3993 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3994 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3995 getF32Constant(DAG, 0x40823e2f, dl));
3996 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3997 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3998 getF32Constant(DAG, 0x4020d29c, dl));
3999 } else { // LimitFloatPrecision <= 18
4000 // For floating-point precision of 18:
4009 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4011 // error 0.0000018516, which is better than 18 bits
4012 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4013 getF32Constant(DAG, 0xbcd2769e, dl));
4014 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4015 getF32Constant(DAG, 0x3e8ce0b9, dl));
4016 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4017 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4018 getF32Constant(DAG, 0x3fa22ae7, dl));
4019 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4020 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4021 getF32Constant(DAG, 0x40525723, dl));
4022 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4023 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4024 getF32Constant(DAG, 0x40aaf200, dl));
4025 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4026 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4027 getF32Constant(DAG, 0x40c39dad, dl));
4028 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4029 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4030 getF32Constant(DAG, 0x4042902c, dl));
4033 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4036 // No special expansion.
4037 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4040 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4041 /// limited-precision mode.
4042 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4043 const TargetLowering &TLI) {
4045 // TODO: What fast-math-flags should be set on the floating-point nodes?
4047 if (Op.getValueType() == MVT::f32 &&
4048 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4049 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4051 // Scale the exponent by log10(2) [0.30102999f].
4052 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4053 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4054 getF32Constant(DAG, 0x3e9a209a, dl));
4056 // Get the significand and build it into a floating-point number with
4058 SDValue X = GetSignificand(DAG, Op1, dl);
4060 SDValue Log10ofMantissa;
4061 if (LimitFloatPrecision <= 6) {
4062 // For floating-point precision of 6:
4064 // Log10ofMantissa =
4066 // (0.60948995f - 0.10380950f * x) * x;
4068 // error 0.0014886165, which is 6 bits
4069 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4070 getF32Constant(DAG, 0xbdd49a13, dl));
4071 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4072 getF32Constant(DAG, 0x3f1c0789, dl));
4073 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4074 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4075 getF32Constant(DAG, 0x3f011300, dl));
4076 } else if (LimitFloatPrecision <= 12) {
4077 // For floating-point precision of 12:
4079 // Log10ofMantissa =
4082 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4084 // error 0.00019228036, which is better than 12 bits
4085 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4086 getF32Constant(DAG, 0x3d431f31, dl));
4087 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4088 getF32Constant(DAG, 0x3ea21fb2, dl));
4089 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4090 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4091 getF32Constant(DAG, 0x3f6ae232, dl));
4092 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4093 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4094 getF32Constant(DAG, 0x3f25f7c3, dl));
4095 } else { // LimitFloatPrecision <= 18
4096 // For floating-point precision of 18:
4098 // Log10ofMantissa =
4103 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4105 // error 0.0000037995730, which is better than 18 bits
4106 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4107 getF32Constant(DAG, 0x3c5d51ce, dl));
4108 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4109 getF32Constant(DAG, 0x3e00685a, dl));
4110 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4111 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4112 getF32Constant(DAG, 0x3efb6798, dl));
4113 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4114 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4115 getF32Constant(DAG, 0x3f88d192, dl));
4116 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4117 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4118 getF32Constant(DAG, 0x3fc4316c, dl));
4119 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4120 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4121 getF32Constant(DAG, 0x3f57ce70, dl));
4124 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4127 // No special expansion.
4128 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4131 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4132 /// limited-precision mode.
4133 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4134 const TargetLowering &TLI) {
4135 if (Op.getValueType() == MVT::f32 &&
4136 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4137 return getLimitedPrecisionExp2(Op, dl, DAG);
4139 // No special expansion.
4140 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4143 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4144 /// limited-precision mode with x == 10.0f.
4145 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4146 SelectionDAG &DAG, const TargetLowering &TLI) {
4147 bool IsExp10 = false;
4148 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4149 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4150 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4152 IsExp10 = LHSC->isExactlyValue(Ten);
4156 // TODO: What fast-math-flags should be set on the FMUL node?
4158 // Put the exponent in the right bit position for later addition to the
4161 // #define LOG2OF10 3.3219281f
4162 // t0 = Op * LOG2OF10;
4163 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4164 getF32Constant(DAG, 0x40549a78, dl));
4165 return getLimitedPrecisionExp2(t0, dl, DAG);
4168 // No special expansion.
4169 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4173 /// ExpandPowI - Expand a llvm.powi intrinsic.
4174 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4175 SelectionDAG &DAG) {
4176 // If RHS is a constant, we can expand this out to a multiplication tree,
4177 // otherwise we end up lowering to a call to __powidf2 (for example). When
4178 // optimizing for size, we only want to do this if the expansion would produce
4179 // a small number of multiplies, otherwise we do the full expansion.
4180 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4181 // Get the exponent as a positive value.
4182 unsigned Val = RHSC->getSExtValue();
4183 if ((int)Val < 0) Val = -Val;
4185 // powi(x, 0) -> 1.0
4187 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4189 const Function *F = DAG.getMachineFunction().getFunction();
4190 if (!F->optForSize() ||
4191 // If optimizing for size, don't insert too many multiplies.
4192 // This inserts up to 5 multiplies.
4193 countPopulation(Val) + Log2_32(Val) < 7) {
4194 // We use the simple binary decomposition method to generate the multiply
4195 // sequence. There are more optimal ways to do this (for example,
4196 // powi(x,15) generates one more multiply than it should), but this has
4197 // the benefit of being both really simple and much better than a libcall.
4198 SDValue Res; // Logically starts equal to 1.0
4199 SDValue CurSquare = LHS;
4200 // TODO: Intrinsics should have fast-math-flags that propagate to these
4205 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4207 Res = CurSquare; // 1.0*CurSquare.
4210 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4211 CurSquare, CurSquare);
4215 // If the original was negative, invert the result, producing 1/(x*x*x).
4216 if (RHSC->getSExtValue() < 0)
4217 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4218 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4223 // Otherwise, expand to a libcall.
4224 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4227 // getUnderlyingArgReg - Find underlying register used for a truncated or
4228 // bitcasted argument.
4229 static unsigned getUnderlyingArgReg(const SDValue &N) {
4230 switch (N.getOpcode()) {
4231 case ISD::CopyFromReg:
4232 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4234 case ISD::AssertZext:
4235 case ISD::AssertSext:
4237 return getUnderlyingArgReg(N.getOperand(0));
4243 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4244 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4245 /// At the end of instruction selection, they will be inserted to the entry BB.
4246 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4247 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4248 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4249 const Argument *Arg = dyn_cast<Argument>(V);
4253 MachineFunction &MF = DAG.getMachineFunction();
4254 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4256 // Ignore inlined function arguments here.
4258 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4259 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4262 Optional<MachineOperand> Op;
4263 // Some arguments' frame index is recorded during argument lowering.
4264 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4265 Op = MachineOperand::CreateFI(FI);
4267 if (!Op && N.getNode()) {
4268 unsigned Reg = getUnderlyingArgReg(N);
4269 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4270 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4271 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4276 Op = MachineOperand::CreateReg(Reg, false);
4280 // Check if ValueMap has reg number.
4281 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4282 if (VMI != FuncInfo.ValueMap.end())
4283 Op = MachineOperand::CreateReg(VMI->second, false);
4286 if (!Op && N.getNode())
4287 // Check if frame index is available.
4288 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4289 if (FrameIndexSDNode *FINode =
4290 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4291 Op = MachineOperand::CreateFI(FINode->getIndex());
4296 assert(Variable->isValidLocationForIntrinsic(DL) &&
4297 "Expected inlined-at fields to agree");
4299 FuncInfo.ArgDbgValues.push_back(
4300 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4301 Op->getReg(), Offset, Variable, Expr));
4303 FuncInfo.ArgDbgValues.push_back(
4304 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4307 .addMetadata(Variable)
4308 .addMetadata(Expr));
4313 // VisualStudio defines setjmp as _setjmp
4314 #if defined(_MSC_VER) && defined(setjmp) && \
4315 !defined(setjmp_undefined_for_msvc)
4316 # pragma push_macro("setjmp")
4318 # define setjmp_undefined_for_msvc
4321 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4322 /// we want to emit this as a call to a named external function, return the name
4323 /// otherwise lower it and return null.
4325 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4326 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4327 SDLoc sdl = getCurSDLoc();
4328 DebugLoc dl = getCurDebugLoc();
4331 switch (Intrinsic) {
4333 // By default, turn this into a target intrinsic node.
4334 visitTargetIntrinsic(I, Intrinsic);
4336 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4337 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4338 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4339 case Intrinsic::returnaddress:
4340 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4341 TLI.getPointerTy(DAG.getDataLayout()),
4342 getValue(I.getArgOperand(0))));
4344 case Intrinsic::frameaddress:
4345 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4346 TLI.getPointerTy(DAG.getDataLayout()),
4347 getValue(I.getArgOperand(0))));
4349 case Intrinsic::read_register: {
4350 Value *Reg = I.getArgOperand(0);
4351 SDValue Chain = getRoot();
4353 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4354 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4355 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4356 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4358 DAG.setRoot(Res.getValue(1));
4361 case Intrinsic::write_register: {
4362 Value *Reg = I.getArgOperand(0);
4363 Value *RegValue = I.getArgOperand(1);
4364 SDValue Chain = getRoot();
4366 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4367 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4368 RegName, getValue(RegValue)));
4371 case Intrinsic::setjmp:
4372 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4373 case Intrinsic::longjmp:
4374 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4375 case Intrinsic::memcpy: {
4376 // FIXME: this definition of "user defined address space" is x86-specific
4377 // Assert for address < 256 since we support only user defined address
4379 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4381 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4383 "Unknown address space");
4384 SDValue Op1 = getValue(I.getArgOperand(0));
4385 SDValue Op2 = getValue(I.getArgOperand(1));
4386 SDValue Op3 = getValue(I.getArgOperand(2));
4387 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4389 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4390 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4391 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4392 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4394 MachinePointerInfo(I.getArgOperand(0)),
4395 MachinePointerInfo(I.getArgOperand(1)));
4396 updateDAGForMaybeTailCall(MC);
4399 case Intrinsic::memset: {
4400 // FIXME: this definition of "user defined address space" is x86-specific
4401 // Assert for address < 256 since we support only user defined address
4403 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4405 "Unknown address space");
4406 SDValue Op1 = getValue(I.getArgOperand(0));
4407 SDValue Op2 = getValue(I.getArgOperand(1));
4408 SDValue Op3 = getValue(I.getArgOperand(2));
4409 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4411 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4412 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4413 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4414 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4415 isTC, MachinePointerInfo(I.getArgOperand(0)));
4416 updateDAGForMaybeTailCall(MS);
4419 case Intrinsic::memmove: {
4420 // FIXME: this definition of "user defined address space" is x86-specific
4421 // Assert for address < 256 since we support only user defined address
4423 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4425 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4427 "Unknown address space");
4428 SDValue Op1 = getValue(I.getArgOperand(0));
4429 SDValue Op2 = getValue(I.getArgOperand(1));
4430 SDValue Op3 = getValue(I.getArgOperand(2));
4431 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4433 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4434 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4435 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4436 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4437 isTC, MachinePointerInfo(I.getArgOperand(0)),
4438 MachinePointerInfo(I.getArgOperand(1)));
4439 updateDAGForMaybeTailCall(MM);
4442 case Intrinsic::dbg_declare: {
4443 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4444 DILocalVariable *Variable = DI.getVariable();
4445 DIExpression *Expression = DI.getExpression();
4446 const Value *Address = DI.getAddress();
4447 assert(Variable && "Missing variable");
4449 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4453 // Check if address has undef value.
4454 if (isa<UndefValue>(Address) ||
4455 (Address->use_empty() && !isa<Argument>(Address))) {
4456 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4460 SDValue &N = NodeMap[Address];
4461 if (!N.getNode() && isa<Argument>(Address))
4462 // Check unused arguments map.
4463 N = UnusedArgNodeMap[Address];
4466 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4467 Address = BCI->getOperand(0);
4468 // Parameters are handled specially.
4469 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4471 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4473 if (isParameter && !AI) {
4474 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4476 // Byval parameter. We have a frame index at this point.
4477 SDV = DAG.getFrameIndexDbgValue(
4478 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4480 // Address is an argument, so try to emit its dbg value using
4481 // virtual register info from the FuncInfo.ValueMap.
4482 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4487 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4488 true, 0, dl, SDNodeOrder);
4490 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4492 // If Address is an argument then try to emit its dbg value using
4493 // virtual register info from the FuncInfo.ValueMap.
4494 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4496 // If variable is pinned by a alloca in dominating bb then
4497 // use StaticAllocaMap.
4498 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4499 if (AI->getParent() != DI.getParent()) {
4500 DenseMap<const AllocaInst*, int>::iterator SI =
4501 FuncInfo.StaticAllocaMap.find(AI);
4502 if (SI != FuncInfo.StaticAllocaMap.end()) {
4503 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4504 0, dl, SDNodeOrder);
4505 DAG.AddDbgValue(SDV, nullptr, false);
4510 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4515 case Intrinsic::dbg_value: {
4516 const DbgValueInst &DI = cast<DbgValueInst>(I);
4517 assert(DI.getVariable() && "Missing variable");
4519 DILocalVariable *Variable = DI.getVariable();
4520 DIExpression *Expression = DI.getExpression();
4521 uint64_t Offset = DI.getOffset();
4522 const Value *V = DI.getValue();
4527 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4528 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4530 DAG.AddDbgValue(SDV, nullptr, false);
4532 // Do not use getValue() in here; we don't want to generate code at
4533 // this point if it hasn't been done yet.
4534 SDValue N = NodeMap[V];
4535 if (!N.getNode() && isa<Argument>(V))
4536 // Check unused arguments map.
4537 N = UnusedArgNodeMap[V];
4539 // A dbg.value for an alloca is always indirect.
4540 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4541 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4543 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4544 IsIndirect, Offset, dl, SDNodeOrder);
4545 DAG.AddDbgValue(SDV, N.getNode(), false);
4547 } else if (!V->use_empty() ) {
4548 // Do not call getValue(V) yet, as we don't want to generate code.
4549 // Remember it for later.
4550 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4551 DanglingDebugInfoMap[V] = DDI;
4553 // We may expand this to cover more cases. One case where we have no
4554 // data available is an unreferenced parameter.
4555 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4559 // Build a debug info table entry.
4560 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4561 V = BCI->getOperand(0);
4562 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4563 // Don't handle byval struct arguments or VLAs, for example.
4565 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4566 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4569 DenseMap<const AllocaInst*, int>::iterator SI =
4570 FuncInfo.StaticAllocaMap.find(AI);
4571 if (SI == FuncInfo.StaticAllocaMap.end())
4572 return nullptr; // VLAs.
4576 case Intrinsic::eh_typeid_for: {
4577 // Find the type id for the given typeinfo.
4578 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4579 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4580 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4585 case Intrinsic::eh_return_i32:
4586 case Intrinsic::eh_return_i64:
4587 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4588 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4591 getValue(I.getArgOperand(0)),
4592 getValue(I.getArgOperand(1))));
4594 case Intrinsic::eh_unwind_init:
4595 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4597 case Intrinsic::eh_dwarf_cfa: {
4598 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4599 TLI.getPointerTy(DAG.getDataLayout()));
4600 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4601 CfaArg.getValueType(),
4602 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4603 CfaArg.getValueType()),
4605 SDValue FA = DAG.getNode(
4606 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4607 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4608 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4612 case Intrinsic::eh_sjlj_callsite: {
4613 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4614 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4615 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4616 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4618 MMI.setCurrentCallSite(CI->getZExtValue());
4621 case Intrinsic::eh_sjlj_functioncontext: {
4622 // Get and store the index of the function context.
4623 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4625 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4626 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4627 MFI->setFunctionContextIndex(FI);
4630 case Intrinsic::eh_sjlj_setjmp: {
4633 Ops[1] = getValue(I.getArgOperand(0));
4634 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4635 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4636 setValue(&I, Op.getValue(0));
4637 DAG.setRoot(Op.getValue(1));
4640 case Intrinsic::eh_sjlj_longjmp: {
4641 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4642 getRoot(), getValue(I.getArgOperand(0))));
4645 case Intrinsic::eh_sjlj_setup_dispatch: {
4646 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4651 case Intrinsic::masked_gather:
4652 visitMaskedGather(I);
4654 case Intrinsic::masked_load:
4657 case Intrinsic::masked_scatter:
4658 visitMaskedScatter(I);
4660 case Intrinsic::masked_store:
4661 visitMaskedStore(I);
4663 case Intrinsic::x86_mmx_pslli_w:
4664 case Intrinsic::x86_mmx_pslli_d:
4665 case Intrinsic::x86_mmx_pslli_q:
4666 case Intrinsic::x86_mmx_psrli_w:
4667 case Intrinsic::x86_mmx_psrli_d:
4668 case Intrinsic::x86_mmx_psrli_q:
4669 case Intrinsic::x86_mmx_psrai_w:
4670 case Intrinsic::x86_mmx_psrai_d: {
4671 SDValue ShAmt = getValue(I.getArgOperand(1));
4672 if (isa<ConstantSDNode>(ShAmt)) {
4673 visitTargetIntrinsic(I, Intrinsic);
4676 unsigned NewIntrinsic = 0;
4677 EVT ShAmtVT = MVT::v2i32;
4678 switch (Intrinsic) {
4679 case Intrinsic::x86_mmx_pslli_w:
4680 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4682 case Intrinsic::x86_mmx_pslli_d:
4683 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4685 case Intrinsic::x86_mmx_pslli_q:
4686 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4688 case Intrinsic::x86_mmx_psrli_w:
4689 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4691 case Intrinsic::x86_mmx_psrli_d:
4692 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4694 case Intrinsic::x86_mmx_psrli_q:
4695 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4697 case Intrinsic::x86_mmx_psrai_w:
4698 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4700 case Intrinsic::x86_mmx_psrai_d:
4701 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4703 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4706 // The vector shift intrinsics with scalars uses 32b shift amounts but
4707 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4709 // We must do this early because v2i32 is not a legal type.
4712 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4713 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4714 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4715 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4716 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4717 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4718 getValue(I.getArgOperand(0)), ShAmt);
4722 case Intrinsic::convertff:
4723 case Intrinsic::convertfsi:
4724 case Intrinsic::convertfui:
4725 case Intrinsic::convertsif:
4726 case Intrinsic::convertuif:
4727 case Intrinsic::convertss:
4728 case Intrinsic::convertsu:
4729 case Intrinsic::convertus:
4730 case Intrinsic::convertuu: {
4731 ISD::CvtCode Code = ISD::CVT_INVALID;
4732 switch (Intrinsic) {
4733 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4734 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4735 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4736 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4737 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4738 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4739 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4740 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4741 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4742 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4744 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4745 const Value *Op1 = I.getArgOperand(0);
4746 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4747 DAG.getValueType(DestVT),
4748 DAG.getValueType(getValue(Op1).getValueType()),
4749 getValue(I.getArgOperand(1)),
4750 getValue(I.getArgOperand(2)),
4755 case Intrinsic::powi:
4756 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4757 getValue(I.getArgOperand(1)), DAG));
4759 case Intrinsic::log:
4760 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4762 case Intrinsic::log2:
4763 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4765 case Intrinsic::log10:
4766 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4768 case Intrinsic::exp:
4769 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4771 case Intrinsic::exp2:
4772 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4774 case Intrinsic::pow:
4775 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4776 getValue(I.getArgOperand(1)), DAG, TLI));
4778 case Intrinsic::sqrt:
4779 case Intrinsic::fabs:
4780 case Intrinsic::sin:
4781 case Intrinsic::cos:
4782 case Intrinsic::floor:
4783 case Intrinsic::ceil:
4784 case Intrinsic::trunc:
4785 case Intrinsic::rint:
4786 case Intrinsic::nearbyint:
4787 case Intrinsic::round: {
4789 switch (Intrinsic) {
4790 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4791 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4792 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4793 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4794 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4795 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4796 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4797 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4798 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4799 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4800 case Intrinsic::round: Opcode = ISD::FROUND; break;
4803 setValue(&I, DAG.getNode(Opcode, sdl,
4804 getValue(I.getArgOperand(0)).getValueType(),
4805 getValue(I.getArgOperand(0))));
4808 case Intrinsic::minnum:
4809 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4810 getValue(I.getArgOperand(0)).getValueType(),
4811 getValue(I.getArgOperand(0)),
4812 getValue(I.getArgOperand(1))));
4814 case Intrinsic::maxnum:
4815 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4816 getValue(I.getArgOperand(0)).getValueType(),
4817 getValue(I.getArgOperand(0)),
4818 getValue(I.getArgOperand(1))));
4820 case Intrinsic::copysign:
4821 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4822 getValue(I.getArgOperand(0)).getValueType(),
4823 getValue(I.getArgOperand(0)),
4824 getValue(I.getArgOperand(1))));
4826 case Intrinsic::fma:
4827 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4828 getValue(I.getArgOperand(0)).getValueType(),
4829 getValue(I.getArgOperand(0)),
4830 getValue(I.getArgOperand(1)),
4831 getValue(I.getArgOperand(2))));
4833 case Intrinsic::fmuladd: {
4834 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4835 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4836 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4837 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4838 getValue(I.getArgOperand(0)).getValueType(),
4839 getValue(I.getArgOperand(0)),
4840 getValue(I.getArgOperand(1)),
4841 getValue(I.getArgOperand(2))));
4843 // TODO: Intrinsic calls should have fast-math-flags.
4844 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4845 getValue(I.getArgOperand(0)).getValueType(),
4846 getValue(I.getArgOperand(0)),
4847 getValue(I.getArgOperand(1)));
4848 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4849 getValue(I.getArgOperand(0)).getValueType(),
4851 getValue(I.getArgOperand(2)));
4856 case Intrinsic::convert_to_fp16:
4857 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4858 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4859 getValue(I.getArgOperand(0)),
4860 DAG.getTargetConstant(0, sdl,
4863 case Intrinsic::convert_from_fp16:
4864 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4865 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4866 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4867 getValue(I.getArgOperand(0)))));
4869 case Intrinsic::pcmarker: {
4870 SDValue Tmp = getValue(I.getArgOperand(0));
4871 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4874 case Intrinsic::readcyclecounter: {
4875 SDValue Op = getRoot();
4876 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4877 DAG.getVTList(MVT::i64, MVT::Other), Op);
4879 DAG.setRoot(Res.getValue(1));
4882 case Intrinsic::bswap:
4883 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4884 getValue(I.getArgOperand(0)).getValueType(),
4885 getValue(I.getArgOperand(0))));
4887 case Intrinsic::uabsdiff:
4888 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4889 getValue(I.getArgOperand(0)).getValueType(),
4890 getValue(I.getArgOperand(0)),
4891 getValue(I.getArgOperand(1))));
4893 case Intrinsic::sabsdiff:
4894 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4895 getValue(I.getArgOperand(0)).getValueType(),
4896 getValue(I.getArgOperand(0)),
4897 getValue(I.getArgOperand(1))));
4899 case Intrinsic::cttz: {
4900 SDValue Arg = getValue(I.getArgOperand(0));
4901 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4902 EVT Ty = Arg.getValueType();
4903 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4907 case Intrinsic::ctlz: {
4908 SDValue Arg = getValue(I.getArgOperand(0));
4909 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4910 EVT Ty = Arg.getValueType();
4911 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4915 case Intrinsic::ctpop: {
4916 SDValue Arg = getValue(I.getArgOperand(0));
4917 EVT Ty = Arg.getValueType();
4918 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4921 case Intrinsic::stacksave: {
4922 SDValue Op = getRoot();
4924 ISD::STACKSAVE, sdl,
4925 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4927 DAG.setRoot(Res.getValue(1));
4930 case Intrinsic::stackrestore: {
4931 Res = getValue(I.getArgOperand(0));
4932 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4935 case Intrinsic::stackprotector: {
4936 // Emit code into the DAG to store the stack guard onto the stack.
4937 MachineFunction &MF = DAG.getMachineFunction();
4938 MachineFrameInfo *MFI = MF.getFrameInfo();
4939 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4940 SDValue Src, Chain = getRoot();
4941 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4942 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4944 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4945 // global variable __stack_chk_guard.
4947 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4948 if (BC->getOpcode() == Instruction::BitCast)
4949 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4951 if (GV && TLI.useLoadStackGuardNode()) {
4952 // Emit a LOAD_STACK_GUARD node.
4953 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4955 MachinePointerInfo MPInfo(GV);
4956 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4957 unsigned Flags = MachineMemOperand::MOLoad |
4958 MachineMemOperand::MOInvariant;
4959 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4960 PtrTy.getSizeInBits() / 8,
4961 DAG.getEVTAlignment(PtrTy));
4962 Node->setMemRefs(MemRefs, MemRefs + 1);
4964 // Copy the guard value to a virtual register so that it can be
4965 // retrieved in the epilogue.
4966 Src = SDValue(Node, 0);
4967 const TargetRegisterClass *RC =
4968 TLI.getRegClassFor(Src.getSimpleValueType());
4969 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4971 SPDescriptor.setGuardReg(Reg);
4972 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4974 Src = getValue(I.getArgOperand(0)); // The guard's value.
4977 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4979 int FI = FuncInfo.StaticAllocaMap[Slot];
4980 MFI->setStackProtectorIndex(FI);
4982 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4984 // Store the stack protector onto the stack.
4985 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4986 DAG.getMachineFunction(), FI),
4992 case Intrinsic::objectsize: {
4993 // If we don't know by now, we're never going to know.
4994 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4996 assert(CI && "Non-constant type in __builtin_object_size?");
4998 SDValue Arg = getValue(I.getCalledValue());
4999 EVT Ty = Arg.getValueType();
5002 Res = DAG.getConstant(-1ULL, sdl, Ty);
5004 Res = DAG.getConstant(0, sdl, Ty);
5009 case Intrinsic::annotation:
5010 case Intrinsic::ptr_annotation:
5011 // Drop the intrinsic, but forward the value
5012 setValue(&I, getValue(I.getOperand(0)));
5014 case Intrinsic::assume:
5015 case Intrinsic::var_annotation:
5016 // Discard annotate attributes and assumptions
5019 case Intrinsic::init_trampoline: {
5020 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5024 Ops[1] = getValue(I.getArgOperand(0));
5025 Ops[2] = getValue(I.getArgOperand(1));
5026 Ops[3] = getValue(I.getArgOperand(2));
5027 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5028 Ops[5] = DAG.getSrcValue(F);
5030 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5035 case Intrinsic::adjust_trampoline: {
5036 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5037 TLI.getPointerTy(DAG.getDataLayout()),
5038 getValue(I.getArgOperand(0))));
5041 case Intrinsic::gcroot:
5043 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5044 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5046 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5047 GFI->addStackRoot(FI->getIndex(), TypeMap);
5050 case Intrinsic::gcread:
5051 case Intrinsic::gcwrite:
5052 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5053 case Intrinsic::flt_rounds:
5054 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5057 case Intrinsic::expect: {
5058 // Just replace __builtin_expect(exp, c) with EXP.
5059 setValue(&I, getValue(I.getArgOperand(0)));
5063 case Intrinsic::debugtrap:
5064 case Intrinsic::trap: {
5065 StringRef TrapFuncName =
5067 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5068 .getValueAsString();
5069 if (TrapFuncName.empty()) {
5070 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5071 ISD::TRAP : ISD::DEBUGTRAP;
5072 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5075 TargetLowering::ArgListTy Args;
5077 TargetLowering::CallLoweringInfo CLI(DAG);
5078 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5079 CallingConv::C, I.getType(),
5080 DAG.getExternalSymbol(TrapFuncName.data(),
5081 TLI.getPointerTy(DAG.getDataLayout())),
5082 std::move(Args), 0);
5084 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5085 DAG.setRoot(Result.second);
5089 case Intrinsic::uadd_with_overflow:
5090 case Intrinsic::sadd_with_overflow:
5091 case Intrinsic::usub_with_overflow:
5092 case Intrinsic::ssub_with_overflow:
5093 case Intrinsic::umul_with_overflow:
5094 case Intrinsic::smul_with_overflow: {
5096 switch (Intrinsic) {
5097 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5098 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5099 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5100 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5101 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5102 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5103 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5105 SDValue Op1 = getValue(I.getArgOperand(0));
5106 SDValue Op2 = getValue(I.getArgOperand(1));
5108 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5109 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5112 case Intrinsic::prefetch: {
5114 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5116 Ops[1] = getValue(I.getArgOperand(0));
5117 Ops[2] = getValue(I.getArgOperand(1));
5118 Ops[3] = getValue(I.getArgOperand(2));
5119 Ops[4] = getValue(I.getArgOperand(3));
5120 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5121 DAG.getVTList(MVT::Other), Ops,
5122 EVT::getIntegerVT(*Context, 8),
5123 MachinePointerInfo(I.getArgOperand(0)),
5125 false, /* volatile */
5127 rw==1)); /* write */
5130 case Intrinsic::lifetime_start:
5131 case Intrinsic::lifetime_end: {
5132 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5133 // Stack coloring is not enabled in O0, discard region information.
5134 if (TM.getOptLevel() == CodeGenOpt::None)
5137 SmallVector<Value *, 4> Allocas;
5138 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5140 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5141 E = Allocas.end(); Object != E; ++Object) {
5142 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5144 // Could not find an Alloca.
5145 if (!LifetimeObject)
5148 // First check that the Alloca is static, otherwise it won't have a
5149 // valid frame index.
5150 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5151 if (SI == FuncInfo.StaticAllocaMap.end())
5154 int FI = SI->second;
5159 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5160 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5162 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5167 case Intrinsic::invariant_start:
5168 // Discard region information.
5169 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5171 case Intrinsic::invariant_end:
5172 // Discard region information.
5174 case Intrinsic::stackprotectorcheck: {
5175 // Do not actually emit anything for this basic block. Instead we initialize
5176 // the stack protector descriptor and export the guard variable so we can
5177 // access it in FinishBasicBlock.
5178 const BasicBlock *BB = I.getParent();
5179 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5180 ExportFromCurrentBlock(SPDescriptor.getGuard());
5182 // Flush our exports since we are going to process a terminator.
5183 (void)getControlRoot();
5186 case Intrinsic::clear_cache:
5187 return TLI.getClearCacheBuiltinName();
5188 case Intrinsic::donothing:
5191 case Intrinsic::experimental_stackmap: {
5195 case Intrinsic::experimental_patchpoint_void:
5196 case Intrinsic::experimental_patchpoint_i64: {
5197 visitPatchpoint(&I);
5200 case Intrinsic::experimental_gc_statepoint: {
5204 case Intrinsic::experimental_gc_result_int:
5205 case Intrinsic::experimental_gc_result_float:
5206 case Intrinsic::experimental_gc_result_ptr:
5207 case Intrinsic::experimental_gc_result: {
5211 case Intrinsic::experimental_gc_relocate: {
5215 case Intrinsic::instrprof_increment:
5216 llvm_unreachable("instrprof failed to lower an increment");
5218 case Intrinsic::localescape: {
5219 MachineFunction &MF = DAG.getMachineFunction();
5220 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5222 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5223 // is the same on all targets.
5224 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5225 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5226 if (isa<ConstantPointerNull>(Arg))
5227 continue; // Skip null pointers. They represent a hole in index space.
5228 AllocaInst *Slot = cast<AllocaInst>(Arg);
5229 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5230 "can only escape static allocas");
5231 int FI = FuncInfo.StaticAllocaMap[Slot];
5232 MCSymbol *FrameAllocSym =
5233 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5234 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5235 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5236 TII->get(TargetOpcode::LOCAL_ESCAPE))
5237 .addSym(FrameAllocSym)
5244 case Intrinsic::localrecover: {
5245 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5246 MachineFunction &MF = DAG.getMachineFunction();
5247 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5249 // Get the symbol that defines the frame offset.
5250 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5251 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5252 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5253 MCSymbol *FrameAllocSym =
5254 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5255 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5257 // Create a MCSymbol for the label to avoid any target lowering
5258 // that would make this PC relative.
5259 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5261 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5263 // Add the offset to the FP.
5264 Value *FP = I.getArgOperand(1);
5265 SDValue FPVal = getValue(FP);
5266 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5272 case Intrinsic::eh_exceptionpointer:
5273 case Intrinsic::eh_exceptioncode: {
5274 // Get the exception pointer vreg, copy from it, and resize it to fit.
5275 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5276 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5277 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5278 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5280 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5281 if (Intrinsic == Intrinsic::eh_exceptioncode)
5282 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5289 std::pair<SDValue, SDValue>
5290 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5291 const BasicBlock *EHPadBB) {
5292 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5293 MCSymbol *BeginLabel = nullptr;
5296 // Insert a label before the invoke call to mark the try range. This can be
5297 // used to detect deletion of the invoke via the MachineModuleInfo.
5298 BeginLabel = MMI.getContext().createTempSymbol();
5300 // For SjLj, keep track of which landing pads go with which invokes
5301 // so as to maintain the ordering of pads in the LSDA.
5302 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5303 if (CallSiteIndex) {
5304 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5305 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5307 // Now that the call site is handled, stop tracking it.
5308 MMI.setCurrentCallSite(0);
5311 // Both PendingLoads and PendingExports must be flushed here;
5312 // this call might not return.
5314 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5316 CLI.setChain(getRoot());
5318 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5319 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5321 assert((CLI.IsTailCall || Result.second.getNode()) &&
5322 "Non-null chain expected with non-tail call!");
5323 assert((Result.second.getNode() || !Result.first.getNode()) &&
5324 "Null value expected with tail call!");
5326 if (!Result.second.getNode()) {
5327 // As a special case, a null chain means that a tail call has been emitted
5328 // and the DAG root is already updated.
5331 // Since there's no actual continuation from this block, nothing can be
5332 // relying on us setting vregs for them.
5333 PendingExports.clear();
5335 DAG.setRoot(Result.second);
5339 // Insert a label at the end of the invoke call to mark the try range. This
5340 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5341 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5342 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5344 // Inform MachineModuleInfo of range.
5345 if (MMI.hasEHFunclets()) {
5346 WinEHFuncInfo &EHInfo =
5347 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5348 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5350 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5357 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5359 const BasicBlock *EHPadBB) {
5360 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5361 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5362 Type *RetTy = FTy->getReturnType();
5364 TargetLowering::ArgListTy Args;
5365 TargetLowering::ArgListEntry Entry;
5366 Args.reserve(CS.arg_size());
5368 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5370 const Value *V = *i;
5373 if (V->getType()->isEmptyTy())
5376 SDValue ArgNode = getValue(V);
5377 Entry.Node = ArgNode; Entry.Ty = V->getType();
5379 // Skip the first return-type Attribute to get to params.
5380 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5381 Args.push_back(Entry);
5383 // If we have an explicit sret argument that is an Instruction, (i.e., it
5384 // might point to function-local memory), we can't meaningfully tail-call.
5385 if (Entry.isSRet && isa<Instruction>(V))
5389 // Check if target-independent constraints permit a tail call here.
5390 // Target-dependent constraints are checked within TLI->LowerCallTo.
5391 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5394 TargetLowering::CallLoweringInfo CLI(DAG);
5395 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5396 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5397 .setTailCall(isTailCall);
5398 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5400 if (Result.first.getNode())
5401 setValue(CS.getInstruction(), Result.first);
5404 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5405 /// value is equal or not-equal to zero.
5406 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5407 for (const User *U : V->users()) {
5408 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5409 if (IC->isEquality())
5410 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5411 if (C->isNullValue())
5413 // Unknown instruction.
5419 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5421 SelectionDAGBuilder &Builder) {
5423 // Check to see if this load can be trivially constant folded, e.g. if the
5424 // input is from a string literal.
5425 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5426 // Cast pointer to the type we really want to load.
5427 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5428 PointerType::getUnqual(LoadTy));
5430 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5431 const_cast<Constant *>(LoadInput), *Builder.DL))
5432 return Builder.getValue(LoadCst);
5435 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5436 // still constant memory, the input chain can be the entry node.
5438 bool ConstantMemory = false;
5440 // Do not serialize (non-volatile) loads of constant memory with anything.
5441 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5442 Root = Builder.DAG.getEntryNode();
5443 ConstantMemory = true;
5445 // Do not serialize non-volatile loads against each other.
5446 Root = Builder.DAG.getRoot();
5449 SDValue Ptr = Builder.getValue(PtrVal);
5450 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5451 Ptr, MachinePointerInfo(PtrVal),
5453 false /*nontemporal*/,
5454 false /*isinvariant*/, 1 /* align=1 */);
5456 if (!ConstantMemory)
5457 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5461 /// processIntegerCallValue - Record the value for an instruction that
5462 /// produces an integer result, converting the type where necessary.
5463 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5466 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5469 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5471 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5472 setValue(&I, Value);
5475 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5476 /// If so, return true and lower it, otherwise return false and it will be
5477 /// lowered like a normal call.
5478 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5479 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5480 if (I.getNumArgOperands() != 3)
5483 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5484 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5485 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5486 !I.getType()->isIntegerTy())
5489 const Value *Size = I.getArgOperand(2);
5490 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5491 if (CSize && CSize->getZExtValue() == 0) {
5492 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5494 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5498 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5499 std::pair<SDValue, SDValue> Res =
5500 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5501 getValue(LHS), getValue(RHS), getValue(Size),
5502 MachinePointerInfo(LHS),
5503 MachinePointerInfo(RHS));
5504 if (Res.first.getNode()) {
5505 processIntegerCallValue(I, Res.first, true);
5506 PendingLoads.push_back(Res.second);
5510 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5511 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5512 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5513 bool ActuallyDoIt = true;
5516 switch (CSize->getZExtValue()) {
5518 LoadVT = MVT::Other;
5520 ActuallyDoIt = false;
5524 LoadTy = Type::getInt16Ty(CSize->getContext());
5528 LoadTy = Type::getInt32Ty(CSize->getContext());
5532 LoadTy = Type::getInt64Ty(CSize->getContext());
5536 LoadVT = MVT::v4i32;
5537 LoadTy = Type::getInt32Ty(CSize->getContext());
5538 LoadTy = VectorType::get(LoadTy, 4);
5543 // This turns into unaligned loads. We only do this if the target natively
5544 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5545 // we'll only produce a small number of byte loads.
5547 // Require that we can find a legal MVT, and only do this if the target
5548 // supports unaligned loads of that type. Expanding into byte loads would
5550 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5551 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5552 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5553 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5554 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5555 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5556 // TODO: Check alignment of src and dest ptrs.
5557 if (!TLI.isTypeLegal(LoadVT) ||
5558 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5559 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5560 ActuallyDoIt = false;
5564 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5565 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5567 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5569 processIntegerCallValue(I, Res, false);
5578 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5579 /// form. If so, return true and lower it, otherwise return false and it
5580 /// will be lowered like a normal call.
5581 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5582 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5583 if (I.getNumArgOperands() != 3)
5586 const Value *Src = I.getArgOperand(0);
5587 const Value *Char = I.getArgOperand(1);
5588 const Value *Length = I.getArgOperand(2);
5589 if (!Src->getType()->isPointerTy() ||
5590 !Char->getType()->isIntegerTy() ||
5591 !Length->getType()->isIntegerTy() ||
5592 !I.getType()->isPointerTy())
5595 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5596 std::pair<SDValue, SDValue> Res =
5597 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5598 getValue(Src), getValue(Char), getValue(Length),
5599 MachinePointerInfo(Src));
5600 if (Res.first.getNode()) {
5601 setValue(&I, Res.first);
5602 PendingLoads.push_back(Res.second);
5609 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5610 /// optimized form. If so, return true and lower it, otherwise return false
5611 /// and it will be lowered like a normal call.
5612 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5613 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5614 if (I.getNumArgOperands() != 2)
5617 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5618 if (!Arg0->getType()->isPointerTy() ||
5619 !Arg1->getType()->isPointerTy() ||
5620 !I.getType()->isPointerTy())
5623 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5624 std::pair<SDValue, SDValue> Res =
5625 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5626 getValue(Arg0), getValue(Arg1),
5627 MachinePointerInfo(Arg0),
5628 MachinePointerInfo(Arg1), isStpcpy);
5629 if (Res.first.getNode()) {
5630 setValue(&I, Res.first);
5631 DAG.setRoot(Res.second);
5638 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5639 /// If so, return true and lower it, otherwise return false and it will be
5640 /// lowered like a normal call.
5641 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5642 // Verify that the prototype makes sense. int strcmp(void*,void*)
5643 if (I.getNumArgOperands() != 2)
5646 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5647 if (!Arg0->getType()->isPointerTy() ||
5648 !Arg1->getType()->isPointerTy() ||
5649 !I.getType()->isIntegerTy())
5652 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5653 std::pair<SDValue, SDValue> Res =
5654 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5655 getValue(Arg0), getValue(Arg1),
5656 MachinePointerInfo(Arg0),
5657 MachinePointerInfo(Arg1));
5658 if (Res.first.getNode()) {
5659 processIntegerCallValue(I, Res.first, true);
5660 PendingLoads.push_back(Res.second);
5667 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5668 /// form. If so, return true and lower it, otherwise return false and it
5669 /// will be lowered like a normal call.
5670 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5671 // Verify that the prototype makes sense. size_t strlen(char *)
5672 if (I.getNumArgOperands() != 1)
5675 const Value *Arg0 = I.getArgOperand(0);
5676 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5679 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5680 std::pair<SDValue, SDValue> Res =
5681 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5682 getValue(Arg0), MachinePointerInfo(Arg0));
5683 if (Res.first.getNode()) {
5684 processIntegerCallValue(I, Res.first, false);
5685 PendingLoads.push_back(Res.second);
5692 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5693 /// form. If so, return true and lower it, otherwise return false and it
5694 /// will be lowered like a normal call.
5695 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5696 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5697 if (I.getNumArgOperands() != 2)
5700 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5701 if (!Arg0->getType()->isPointerTy() ||
5702 !Arg1->getType()->isIntegerTy() ||
5703 !I.getType()->isIntegerTy())
5706 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5707 std::pair<SDValue, SDValue> Res =
5708 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5709 getValue(Arg0), getValue(Arg1),
5710 MachinePointerInfo(Arg0));
5711 if (Res.first.getNode()) {
5712 processIntegerCallValue(I, Res.first, false);
5713 PendingLoads.push_back(Res.second);
5720 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5721 /// operation (as expected), translate it to an SDNode with the specified opcode
5722 /// and return true.
5723 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5725 // Sanity check that it really is a unary floating-point call.
5726 if (I.getNumArgOperands() != 1 ||
5727 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5728 I.getType() != I.getArgOperand(0)->getType() ||
5729 !I.onlyReadsMemory())
5732 SDValue Tmp = getValue(I.getArgOperand(0));
5733 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5737 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5738 /// operation (as expected), translate it to an SDNode with the specified opcode
5739 /// and return true.
5740 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5742 // Sanity check that it really is a binary floating-point call.
5743 if (I.getNumArgOperands() != 2 ||
5744 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5745 I.getType() != I.getArgOperand(0)->getType() ||
5746 I.getType() != I.getArgOperand(1)->getType() ||
5747 !I.onlyReadsMemory())
5750 SDValue Tmp0 = getValue(I.getArgOperand(0));
5751 SDValue Tmp1 = getValue(I.getArgOperand(1));
5752 EVT VT = Tmp0.getValueType();
5753 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5757 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5758 // Handle inline assembly differently.
5759 if (isa<InlineAsm>(I.getCalledValue())) {
5764 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5765 ComputeUsesVAFloatArgument(I, &MMI);
5767 const char *RenameFn = nullptr;
5768 if (Function *F = I.getCalledFunction()) {
5769 if (F->isDeclaration()) {
5770 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5771 if (unsigned IID = II->getIntrinsicID(F)) {
5772 RenameFn = visitIntrinsicCall(I, IID);
5777 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5778 RenameFn = visitIntrinsicCall(I, IID);
5784 // Check for well-known libc/libm calls. If the function is internal, it
5785 // can't be a library call.
5787 if (!F->hasLocalLinkage() && F->hasName() &&
5788 LibInfo->getLibFunc(F->getName(), Func) &&
5789 LibInfo->hasOptimizedCodeGen(Func)) {
5792 case LibFunc::copysign:
5793 case LibFunc::copysignf:
5794 case LibFunc::copysignl:
5795 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5796 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5797 I.getType() == I.getArgOperand(0)->getType() &&
5798 I.getType() == I.getArgOperand(1)->getType() &&
5799 I.onlyReadsMemory()) {
5800 SDValue LHS = getValue(I.getArgOperand(0));
5801 SDValue RHS = getValue(I.getArgOperand(1));
5802 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5803 LHS.getValueType(), LHS, RHS));
5808 case LibFunc::fabsf:
5809 case LibFunc::fabsl:
5810 if (visitUnaryFloatCall(I, ISD::FABS))
5814 case LibFunc::fminf:
5815 case LibFunc::fminl:
5816 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5820 case LibFunc::fmaxf:
5821 case LibFunc::fmaxl:
5822 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5828 if (visitUnaryFloatCall(I, ISD::FSIN))
5834 if (visitUnaryFloatCall(I, ISD::FCOS))
5838 case LibFunc::sqrtf:
5839 case LibFunc::sqrtl:
5840 case LibFunc::sqrt_finite:
5841 case LibFunc::sqrtf_finite:
5842 case LibFunc::sqrtl_finite:
5843 if (visitUnaryFloatCall(I, ISD::FSQRT))
5846 case LibFunc::floor:
5847 case LibFunc::floorf:
5848 case LibFunc::floorl:
5849 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5852 case LibFunc::nearbyint:
5853 case LibFunc::nearbyintf:
5854 case LibFunc::nearbyintl:
5855 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5859 case LibFunc::ceilf:
5860 case LibFunc::ceill:
5861 if (visitUnaryFloatCall(I, ISD::FCEIL))
5865 case LibFunc::rintf:
5866 case LibFunc::rintl:
5867 if (visitUnaryFloatCall(I, ISD::FRINT))
5870 case LibFunc::round:
5871 case LibFunc::roundf:
5872 case LibFunc::roundl:
5873 if (visitUnaryFloatCall(I, ISD::FROUND))
5876 case LibFunc::trunc:
5877 case LibFunc::truncf:
5878 case LibFunc::truncl:
5879 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5883 case LibFunc::log2f:
5884 case LibFunc::log2l:
5885 if (visitUnaryFloatCall(I, ISD::FLOG2))
5889 case LibFunc::exp2f:
5890 case LibFunc::exp2l:
5891 if (visitUnaryFloatCall(I, ISD::FEXP2))
5894 case LibFunc::memcmp:
5895 if (visitMemCmpCall(I))
5898 case LibFunc::memchr:
5899 if (visitMemChrCall(I))
5902 case LibFunc::strcpy:
5903 if (visitStrCpyCall(I, false))
5906 case LibFunc::stpcpy:
5907 if (visitStrCpyCall(I, true))
5910 case LibFunc::strcmp:
5911 if (visitStrCmpCall(I))
5914 case LibFunc::strlen:
5915 if (visitStrLenCall(I))
5918 case LibFunc::strnlen:
5919 if (visitStrNLenCall(I))
5928 Callee = getValue(I.getCalledValue());
5930 Callee = DAG.getExternalSymbol(
5932 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5934 // Check if we can potentially perform a tail call. More detailed checking is
5935 // be done within LowerCallTo, after more information about the call is known.
5936 LowerCallTo(&I, Callee, I.isTailCall());
5941 /// AsmOperandInfo - This contains information for each constraint that we are
5943 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5945 /// CallOperand - If this is the result output operand or a clobber
5946 /// this is null, otherwise it is the incoming operand to the CallInst.
5947 /// This gets modified as the asm is processed.
5948 SDValue CallOperand;
5950 /// AssignedRegs - If this is a register or register class operand, this
5951 /// contains the set of register corresponding to the operand.
5952 RegsForValue AssignedRegs;
5954 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5955 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5958 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5959 /// corresponds to. If there is no Value* for this operand, it returns
5961 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5962 const DataLayout &DL) const {
5963 if (!CallOperandVal) return MVT::Other;
5965 if (isa<BasicBlock>(CallOperandVal))
5966 return TLI.getPointerTy(DL);
5968 llvm::Type *OpTy = CallOperandVal->getType();
5970 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5971 // If this is an indirect operand, the operand is a pointer to the
5974 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5976 report_fatal_error("Indirect operand for inline asm not a pointer!");
5977 OpTy = PtrTy->getElementType();
5980 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5981 if (StructType *STy = dyn_cast<StructType>(OpTy))
5982 if (STy->getNumElements() == 1)
5983 OpTy = STy->getElementType(0);
5985 // If OpTy is not a single value, it may be a struct/union that we
5986 // can tile with integers.
5987 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5988 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5997 OpTy = IntegerType::get(Context, BitSize);
6002 return TLI.getValueType(DL, OpTy, true);
6006 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6008 } // end anonymous namespace
6010 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6011 /// specified operand. We prefer to assign virtual registers, to allow the
6012 /// register allocator to handle the assignment process. However, if the asm
6013 /// uses features that we can't model on machineinstrs, we have SDISel do the
6014 /// allocation. This produces generally horrible, but correct, code.
6016 /// OpInfo describes the operand.
6018 static void GetRegistersForValue(SelectionDAG &DAG,
6019 const TargetLowering &TLI,
6021 SDISelAsmOperandInfo &OpInfo) {
6022 LLVMContext &Context = *DAG.getContext();
6024 MachineFunction &MF = DAG.getMachineFunction();
6025 SmallVector<unsigned, 4> Regs;
6027 // If this is a constraint for a single physreg, or a constraint for a
6028 // register class, find it.
6029 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6030 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6031 OpInfo.ConstraintCode,
6032 OpInfo.ConstraintVT);
6034 unsigned NumRegs = 1;
6035 if (OpInfo.ConstraintVT != MVT::Other) {
6036 // If this is a FP input in an integer register (or visa versa) insert a bit
6037 // cast of the input value. More generally, handle any case where the input
6038 // value disagrees with the register class we plan to stick this in.
6039 if (OpInfo.Type == InlineAsm::isInput &&
6040 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6041 // Try to convert to the first EVT that the reg class contains. If the
6042 // types are identical size, use a bitcast to convert (e.g. two differing
6044 MVT RegVT = *PhysReg.second->vt_begin();
6045 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6046 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6047 RegVT, OpInfo.CallOperand);
6048 OpInfo.ConstraintVT = RegVT;
6049 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6050 // If the input is a FP value and we want it in FP registers, do a
6051 // bitcast to the corresponding integer type. This turns an f64 value
6052 // into i64, which can be passed with two i32 values on a 32-bit
6054 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6055 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6056 RegVT, OpInfo.CallOperand);
6057 OpInfo.ConstraintVT = RegVT;
6061 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6065 EVT ValueVT = OpInfo.ConstraintVT;
6067 // If this is a constraint for a specific physical register, like {r17},
6069 if (unsigned AssignedReg = PhysReg.first) {
6070 const TargetRegisterClass *RC = PhysReg.second;
6071 if (OpInfo.ConstraintVT == MVT::Other)
6072 ValueVT = *RC->vt_begin();
6074 // Get the actual register value type. This is important, because the user
6075 // may have asked for (e.g.) the AX register in i32 type. We need to
6076 // remember that AX is actually i16 to get the right extension.
6077 RegVT = *RC->vt_begin();
6079 // This is a explicit reference to a physical register.
6080 Regs.push_back(AssignedReg);
6082 // If this is an expanded reference, add the rest of the regs to Regs.
6084 TargetRegisterClass::iterator I = RC->begin();
6085 for (; *I != AssignedReg; ++I)
6086 assert(I != RC->end() && "Didn't find reg!");
6088 // Already added the first reg.
6090 for (; NumRegs; --NumRegs, ++I) {
6091 assert(I != RC->end() && "Ran out of registers to allocate!");
6096 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6100 // Otherwise, if this was a reference to an LLVM register class, create vregs
6101 // for this reference.
6102 if (const TargetRegisterClass *RC = PhysReg.second) {
6103 RegVT = *RC->vt_begin();
6104 if (OpInfo.ConstraintVT == MVT::Other)
6107 // Create the appropriate number of virtual registers.
6108 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6109 for (; NumRegs; --NumRegs)
6110 Regs.push_back(RegInfo.createVirtualRegister(RC));
6112 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6116 // Otherwise, we couldn't allocate enough registers for this.
6119 /// visitInlineAsm - Handle a call to an InlineAsm object.
6121 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6122 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6124 /// ConstraintOperands - Information about all of the constraints.
6125 SDISelAsmOperandInfoVector ConstraintOperands;
6127 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6128 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6129 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6131 bool hasMemory = false;
6133 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6134 unsigned ResNo = 0; // ResNo - The result number of the next output.
6135 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6136 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6137 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6139 MVT OpVT = MVT::Other;
6141 // Compute the value type for each operand.
6142 switch (OpInfo.Type) {
6143 case InlineAsm::isOutput:
6144 // Indirect outputs just consume an argument.
6145 if (OpInfo.isIndirect) {
6146 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6150 // The return value of the call is this value. As such, there is no
6151 // corresponding argument.
6152 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6153 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6154 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6155 STy->getElementType(ResNo));
6157 assert(ResNo == 0 && "Asm only has one result!");
6158 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6162 case InlineAsm::isInput:
6163 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6165 case InlineAsm::isClobber:
6170 // If this is an input or an indirect output, process the call argument.
6171 // BasicBlocks are labels, currently appearing only in asm's.
6172 if (OpInfo.CallOperandVal) {
6173 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6174 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6176 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6179 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6180 DAG.getDataLayout()).getSimpleVT();
6183 OpInfo.ConstraintVT = OpVT;
6185 // Indirect operand accesses access memory.
6186 if (OpInfo.isIndirect)
6189 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6190 TargetLowering::ConstraintType
6191 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6192 if (CType == TargetLowering::C_Memory) {
6200 SDValue Chain, Flag;
6202 // We won't need to flush pending loads if this asm doesn't touch
6203 // memory and is nonvolatile.
6204 if (hasMemory || IA->hasSideEffects())
6207 Chain = DAG.getRoot();
6209 // Second pass over the constraints: compute which constraint option to use
6210 // and assign registers to constraints that want a specific physreg.
6211 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6212 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6214 // If this is an output operand with a matching input operand, look up the
6215 // matching input. If their types mismatch, e.g. one is an integer, the
6216 // other is floating point, or their sizes are different, flag it as an
6218 if (OpInfo.hasMatchingInput()) {
6219 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6221 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6222 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6223 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6224 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6225 OpInfo.ConstraintVT);
6226 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6227 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6228 Input.ConstraintVT);
6229 if ((OpInfo.ConstraintVT.isInteger() !=
6230 Input.ConstraintVT.isInteger()) ||
6231 (MatchRC.second != InputRC.second)) {
6232 report_fatal_error("Unsupported asm: input constraint"
6233 " with a matching output constraint of"
6234 " incompatible type!");
6236 Input.ConstraintVT = OpInfo.ConstraintVT;
6240 // Compute the constraint code and ConstraintType to use.
6241 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6243 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6244 OpInfo.Type == InlineAsm::isClobber)
6247 // If this is a memory input, and if the operand is not indirect, do what we
6248 // need to to provide an address for the memory input.
6249 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6250 !OpInfo.isIndirect) {
6251 assert((OpInfo.isMultipleAlternative ||
6252 (OpInfo.Type == InlineAsm::isInput)) &&
6253 "Can only indirectify direct input operands!");
6255 // Memory operands really want the address of the value. If we don't have
6256 // an indirect input, put it in the constpool if we can, otherwise spill
6257 // it to a stack slot.
6258 // TODO: This isn't quite right. We need to handle these according to
6259 // the addressing mode that the constraint wants. Also, this may take
6260 // an additional register for the computation and we don't want that
6263 // If the operand is a float, integer, or vector constant, spill to a
6264 // constant pool entry to get its address.
6265 const Value *OpVal = OpInfo.CallOperandVal;
6266 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6267 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6268 OpInfo.CallOperand = DAG.getConstantPool(
6269 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6271 // Otherwise, create a stack slot and emit a store to it before the
6273 Type *Ty = OpVal->getType();
6274 auto &DL = DAG.getDataLayout();
6275 uint64_t TySize = DL.getTypeAllocSize(Ty);
6276 unsigned Align = DL.getPrefTypeAlignment(Ty);
6277 MachineFunction &MF = DAG.getMachineFunction();
6278 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6280 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6281 Chain = DAG.getStore(
6282 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6283 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6285 OpInfo.CallOperand = StackSlot;
6288 // There is no longer a Value* corresponding to this operand.
6289 OpInfo.CallOperandVal = nullptr;
6291 // It is now an indirect operand.
6292 OpInfo.isIndirect = true;
6295 // If this constraint is for a specific register, allocate it before
6297 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6298 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6301 // Second pass - Loop over all of the operands, assigning virtual or physregs
6302 // to register class operands.
6303 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6304 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6306 // C_Register operands have already been allocated, Other/Memory don't need
6308 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6309 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6312 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6313 std::vector<SDValue> AsmNodeOperands;
6314 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6315 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6316 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6318 // If we have a !srcloc metadata node associated with it, we want to attach
6319 // this to the ultimately generated inline asm machineinstr. To do this, we
6320 // pass in the third operand as this (potentially null) inline asm MDNode.
6321 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6322 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6324 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6325 // bits as operand 3.
6326 unsigned ExtraInfo = 0;
6327 if (IA->hasSideEffects())
6328 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6329 if (IA->isAlignStack())
6330 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6331 // Set the asm dialect.
6332 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6334 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6335 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6336 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6338 // Compute the constraint code and ConstraintType to use.
6339 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6341 // Ideally, we would only check against memory constraints. However, the
6342 // meaning of an other constraint can be target-specific and we can't easily
6343 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6344 // for other constriants as well.
6345 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6346 OpInfo.ConstraintType == TargetLowering::C_Other) {
6347 if (OpInfo.Type == InlineAsm::isInput)
6348 ExtraInfo |= InlineAsm::Extra_MayLoad;
6349 else if (OpInfo.Type == InlineAsm::isOutput)
6350 ExtraInfo |= InlineAsm::Extra_MayStore;
6351 else if (OpInfo.Type == InlineAsm::isClobber)
6352 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6356 AsmNodeOperands.push_back(DAG.getTargetConstant(
6357 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6359 // Loop over all of the inputs, copying the operand values into the
6360 // appropriate registers and processing the output regs.
6361 RegsForValue RetValRegs;
6363 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6364 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6366 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6367 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6369 switch (OpInfo.Type) {
6370 case InlineAsm::isOutput: {
6371 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6372 OpInfo.ConstraintType != TargetLowering::C_Register) {
6373 // Memory output, or 'other' output (e.g. 'X' constraint).
6374 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6376 unsigned ConstraintID =
6377 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6378 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6379 "Failed to convert memory constraint code to constraint id.");
6381 // Add information to the INLINEASM node to know about this output.
6382 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6383 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6384 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6386 AsmNodeOperands.push_back(OpInfo.CallOperand);
6390 // Otherwise, this is a register or register class output.
6392 // Copy the output from the appropriate register. Find a register that
6394 if (OpInfo.AssignedRegs.Regs.empty()) {
6395 LLVMContext &Ctx = *DAG.getContext();
6396 Ctx.emitError(CS.getInstruction(),
6397 "couldn't allocate output register for constraint '" +
6398 Twine(OpInfo.ConstraintCode) + "'");
6402 // If this is an indirect operand, store through the pointer after the
6404 if (OpInfo.isIndirect) {
6405 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6406 OpInfo.CallOperandVal));
6408 // This is the result value of the call.
6409 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6410 // Concatenate this output onto the outputs list.
6411 RetValRegs.append(OpInfo.AssignedRegs);
6414 // Add information to the INLINEASM node to know that this register is
6417 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6418 ? InlineAsm::Kind_RegDefEarlyClobber
6419 : InlineAsm::Kind_RegDef,
6420 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6423 case InlineAsm::isInput: {
6424 SDValue InOperandVal = OpInfo.CallOperand;
6426 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6427 // If this is required to match an output register we have already set,
6428 // just use its register.
6429 unsigned OperandNo = OpInfo.getMatchedOperand();
6431 // Scan until we find the definition we already emitted of this operand.
6432 // When we find it, create a RegsForValue operand.
6433 unsigned CurOp = InlineAsm::Op_FirstOperand;
6434 for (; OperandNo; --OperandNo) {
6435 // Advance to the next operand.
6437 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6438 assert((InlineAsm::isRegDefKind(OpFlag) ||
6439 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6440 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6441 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6445 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6446 if (InlineAsm::isRegDefKind(OpFlag) ||
6447 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6448 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6449 if (OpInfo.isIndirect) {
6450 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6451 LLVMContext &Ctx = *DAG.getContext();
6452 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6453 " don't know how to handle tied "
6454 "indirect register inputs");
6458 RegsForValue MatchedRegs;
6459 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6460 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6461 MatchedRegs.RegVTs.push_back(RegVT);
6462 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6463 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6465 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6466 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6468 LLVMContext &Ctx = *DAG.getContext();
6469 Ctx.emitError(CS.getInstruction(),
6470 "inline asm error: This value"
6471 " type register class is not natively supported!");
6475 SDLoc dl = getCurSDLoc();
6476 // Use the produced MatchedRegs object to
6477 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6478 Chain, &Flag, CS.getInstruction());
6479 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6480 true, OpInfo.getMatchedOperand(), dl,
6481 DAG, AsmNodeOperands);
6485 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6486 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6487 "Unexpected number of operands");
6488 // Add information to the INLINEASM node to know about this input.
6489 // See InlineAsm.h isUseOperandTiedToDef.
6490 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6491 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6492 OpInfo.getMatchedOperand());
6493 AsmNodeOperands.push_back(DAG.getTargetConstant(
6494 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6495 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6499 // Treat indirect 'X' constraint as memory.
6500 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6502 OpInfo.ConstraintType = TargetLowering::C_Memory;
6504 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6505 std::vector<SDValue> Ops;
6506 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6509 LLVMContext &Ctx = *DAG.getContext();
6510 Ctx.emitError(CS.getInstruction(),
6511 "invalid operand for inline asm constraint '" +
6512 Twine(OpInfo.ConstraintCode) + "'");
6516 // Add information to the INLINEASM node to know about this input.
6517 unsigned ResOpType =
6518 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6519 AsmNodeOperands.push_back(DAG.getTargetConstant(
6520 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6521 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6525 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6526 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6527 assert(InOperandVal.getValueType() ==
6528 TLI.getPointerTy(DAG.getDataLayout()) &&
6529 "Memory operands expect pointer values");
6531 unsigned ConstraintID =
6532 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6533 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6534 "Failed to convert memory constraint code to constraint id.");
6536 // Add information to the INLINEASM node to know about this input.
6537 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6538 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6539 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6542 AsmNodeOperands.push_back(InOperandVal);
6546 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6547 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6548 "Unknown constraint type!");
6550 // TODO: Support this.
6551 if (OpInfo.isIndirect) {
6552 LLVMContext &Ctx = *DAG.getContext();
6553 Ctx.emitError(CS.getInstruction(),
6554 "Don't know how to handle indirect register inputs yet "
6555 "for constraint '" +
6556 Twine(OpInfo.ConstraintCode) + "'");
6560 // Copy the input into the appropriate registers.
6561 if (OpInfo.AssignedRegs.Regs.empty()) {
6562 LLVMContext &Ctx = *DAG.getContext();
6563 Ctx.emitError(CS.getInstruction(),
6564 "couldn't allocate input reg for constraint '" +
6565 Twine(OpInfo.ConstraintCode) + "'");
6569 SDLoc dl = getCurSDLoc();
6571 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6572 Chain, &Flag, CS.getInstruction());
6574 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6575 dl, DAG, AsmNodeOperands);
6578 case InlineAsm::isClobber: {
6579 // Add the clobbered value to the operand list, so that the register
6580 // allocator is aware that the physreg got clobbered.
6581 if (!OpInfo.AssignedRegs.Regs.empty())
6582 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6583 false, 0, getCurSDLoc(), DAG,
6590 // Finish up input operands. Set the input chain and add the flag last.
6591 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6592 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6594 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6595 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6596 Flag = Chain.getValue(1);
6598 // If this asm returns a register value, copy the result from that register
6599 // and set it as the value of the call.
6600 if (!RetValRegs.Regs.empty()) {
6601 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6602 Chain, &Flag, CS.getInstruction());
6604 // FIXME: Why don't we do this for inline asms with MRVs?
6605 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6606 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6608 // If any of the results of the inline asm is a vector, it may have the
6609 // wrong width/num elts. This can happen for register classes that can
6610 // contain multiple different value types. The preg or vreg allocated may
6611 // not have the same VT as was expected. Convert it to the right type
6612 // with bit_convert.
6613 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6614 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6617 } else if (ResultType != Val.getValueType() &&
6618 ResultType.isInteger() && Val.getValueType().isInteger()) {
6619 // If a result value was tied to an input value, the computed result may
6620 // have a wider width than the expected result. Extract the relevant
6622 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6625 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6628 setValue(CS.getInstruction(), Val);
6629 // Don't need to use this as a chain in this case.
6630 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6634 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6636 // Process indirect outputs, first output all of the flagged copies out of
6638 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6639 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6640 const Value *Ptr = IndirectStoresToEmit[i].second;
6641 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6643 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6646 // Emit the non-flagged stores from the physregs.
6647 SmallVector<SDValue, 8> OutChains;
6648 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6649 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6650 StoresToEmit[i].first,
6651 getValue(StoresToEmit[i].second),
6652 MachinePointerInfo(StoresToEmit[i].second),
6654 OutChains.push_back(Val);
6657 if (!OutChains.empty())
6658 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6663 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6664 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6665 MVT::Other, getRoot(),
6666 getValue(I.getArgOperand(0)),
6667 DAG.getSrcValue(I.getArgOperand(0))));
6670 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6671 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6672 const DataLayout &DL = DAG.getDataLayout();
6673 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6674 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6675 DAG.getSrcValue(I.getOperand(0)),
6676 DL.getABITypeAlignment(I.getType()));
6678 DAG.setRoot(V.getValue(1));
6681 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6682 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6683 MVT::Other, getRoot(),
6684 getValue(I.getArgOperand(0)),
6685 DAG.getSrcValue(I.getArgOperand(0))));
6688 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6689 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6690 MVT::Other, getRoot(),
6691 getValue(I.getArgOperand(0)),
6692 getValue(I.getArgOperand(1)),
6693 DAG.getSrcValue(I.getArgOperand(0)),
6694 DAG.getSrcValue(I.getArgOperand(1))));
6697 /// \brief Lower an argument list according to the target calling convention.
6699 /// \return A tuple of <return-value, token-chain>
6701 /// This is a helper for lowering intrinsics that follow a target calling
6702 /// convention or require stack pointer adjustment. Only a subset of the
6703 /// intrinsic's operands need to participate in the calling convention.
6704 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6705 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6706 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6707 TargetLowering::ArgListTy Args;
6708 Args.reserve(NumArgs);
6710 // Populate the argument list.
6711 // Attributes for args start at offset 1, after the return attribute.
6712 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6713 ArgI != ArgE; ++ArgI) {
6714 const Value *V = CS->getOperand(ArgI);
6716 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6718 TargetLowering::ArgListEntry Entry;
6719 Entry.Node = getValue(V);
6720 Entry.Ty = V->getType();
6721 Entry.setAttributes(&CS, AttrI);
6722 Args.push_back(Entry);
6725 TargetLowering::CallLoweringInfo CLI(DAG);
6726 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6727 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6728 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6730 return lowerInvokable(CLI, EHPadBB);
6733 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6734 /// or patchpoint target node's operand list.
6736 /// Constants are converted to TargetConstants purely as an optimization to
6737 /// avoid constant materialization and register allocation.
6739 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6740 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6741 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6742 /// address materialization and register allocation, but may also be required
6743 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6744 /// alloca in the entry block, then the runtime may assume that the alloca's
6745 /// StackMap location can be read immediately after compilation and that the
6746 /// location is valid at any point during execution (this is similar to the
6747 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6748 /// only available in a register, then the runtime would need to trap when
6749 /// execution reaches the StackMap in order to read the alloca's location.
6750 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6751 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6752 SelectionDAGBuilder &Builder) {
6753 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6754 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6755 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6757 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6759 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6760 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6761 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6762 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6763 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6765 Ops.push_back(OpVal);
6769 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6770 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6771 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6772 // [live variables...])
6774 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6776 SDValue Chain, InFlag, Callee, NullPtr;
6777 SmallVector<SDValue, 32> Ops;
6779 SDLoc DL = getCurSDLoc();
6780 Callee = getValue(CI.getCalledValue());
6781 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6783 // The stackmap intrinsic only records the live variables (the arguemnts
6784 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6785 // intrinsic, this won't be lowered to a function call. This means we don't
6786 // have to worry about calling conventions and target specific lowering code.
6787 // Instead we perform the call lowering right here.
6789 // chain, flag = CALLSEQ_START(chain, 0)
6790 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6791 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6793 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6794 InFlag = Chain.getValue(1);
6796 // Add the <id> and <numBytes> constants.
6797 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6798 Ops.push_back(DAG.getTargetConstant(
6799 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6800 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6801 Ops.push_back(DAG.getTargetConstant(
6802 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6805 // Push live variables for the stack map.
6806 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6808 // We are not pushing any register mask info here on the operands list,
6809 // because the stackmap doesn't clobber anything.
6811 // Push the chain and the glue flag.
6812 Ops.push_back(Chain);
6813 Ops.push_back(InFlag);
6815 // Create the STACKMAP node.
6816 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6817 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6818 Chain = SDValue(SM, 0);
6819 InFlag = Chain.getValue(1);
6821 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6823 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6825 // Set the root to the target-lowered call chain.
6828 // Inform the Frame Information that we have a stackmap in this function.
6829 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6832 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6833 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6834 const BasicBlock *EHPadBB) {
6835 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6840 // [live variables...])
6842 CallingConv::ID CC = CS.getCallingConv();
6843 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6844 bool HasDef = !CS->getType()->isVoidTy();
6845 SDLoc dl = getCurSDLoc();
6846 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6848 // Handle immediate and symbolic callees.
6849 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6850 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6852 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6853 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6854 SDLoc(SymbolicCallee),
6855 SymbolicCallee->getValueType(0));
6857 // Get the real number of arguments participating in the call <numArgs>
6858 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6859 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6861 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6862 // Intrinsics include all meta-operands up to but not including CC.
6863 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6864 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6865 "Not enough arguments provided to the patchpoint intrinsic");
6867 // For AnyRegCC the arguments are lowered later on manually.
6868 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6870 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6871 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6872 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6874 SDNode *CallEnd = Result.second.getNode();
6875 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6876 CallEnd = CallEnd->getOperand(0).getNode();
6878 /// Get a call instruction from the call sequence chain.
6879 /// Tail calls are not allowed.
6880 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6881 "Expected a callseq node.");
6882 SDNode *Call = CallEnd->getOperand(0).getNode();
6883 bool HasGlue = Call->getGluedNode();
6885 // Replace the target specific call node with the patchable intrinsic.
6886 SmallVector<SDValue, 8> Ops;
6888 // Add the <id> and <numBytes> constants.
6889 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6890 Ops.push_back(DAG.getTargetConstant(
6891 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6892 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6893 Ops.push_back(DAG.getTargetConstant(
6894 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6898 Ops.push_back(Callee);
6900 // Adjust <numArgs> to account for any arguments that have been passed on the
6902 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6903 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6904 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6905 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6907 // Add the calling convention
6908 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6910 // Add the arguments we omitted previously. The register allocator should
6911 // place these in any free register.
6913 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6914 Ops.push_back(getValue(CS.getArgument(i)));
6916 // Push the arguments from the call instruction up to the register mask.
6917 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6918 Ops.append(Call->op_begin() + 2, e);
6920 // Push live variables for the stack map.
6921 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6923 // Push the register mask info.
6925 Ops.push_back(*(Call->op_end()-2));
6927 Ops.push_back(*(Call->op_end()-1));
6929 // Push the chain (this is originally the first operand of the call, but
6930 // becomes now the last or second to last operand).
6931 Ops.push_back(*(Call->op_begin()));
6933 // Push the glue flag (last operand).
6935 Ops.push_back(*(Call->op_end()-1));
6938 if (IsAnyRegCC && HasDef) {
6939 // Create the return types based on the intrinsic definition
6940 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6941 SmallVector<EVT, 3> ValueVTs;
6942 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6943 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6945 // There is always a chain and a glue type at the end
6946 ValueVTs.push_back(MVT::Other);
6947 ValueVTs.push_back(MVT::Glue);
6948 NodeTys = DAG.getVTList(ValueVTs);
6950 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6952 // Replace the target specific call node with a PATCHPOINT node.
6953 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6956 // Update the NodeMap.
6959 setValue(CS.getInstruction(), SDValue(MN, 0));
6961 setValue(CS.getInstruction(), Result.first);
6964 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6965 // call sequence. Furthermore the location of the chain and glue can change
6966 // when the AnyReg calling convention is used and the intrinsic returns a
6968 if (IsAnyRegCC && HasDef) {
6969 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6970 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6971 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6973 DAG.ReplaceAllUsesWith(Call, MN);
6974 DAG.DeleteNode(Call);
6976 // Inform the Frame Information that we have a patchpoint in this function.
6977 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6980 /// Returns an AttributeSet representing the attributes applied to the return
6981 /// value of the given call.
6982 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6983 SmallVector<Attribute::AttrKind, 2> Attrs;
6985 Attrs.push_back(Attribute::SExt);
6987 Attrs.push_back(Attribute::ZExt);
6989 Attrs.push_back(Attribute::InReg);
6991 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6995 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6996 /// implementation, which just calls LowerCall.
6997 /// FIXME: When all targets are
6998 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6999 std::pair<SDValue, SDValue>
7000 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7001 // Handle the incoming return values from the call.
7003 Type *OrigRetTy = CLI.RetTy;
7004 SmallVector<EVT, 4> RetTys;
7005 SmallVector<uint64_t, 4> Offsets;
7006 auto &DL = CLI.DAG.getDataLayout();
7007 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7009 SmallVector<ISD::OutputArg, 4> Outs;
7010 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7012 bool CanLowerReturn =
7013 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7014 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7016 SDValue DemoteStackSlot;
7017 int DemoteStackIdx = -100;
7018 if (!CanLowerReturn) {
7019 // FIXME: equivalent assert?
7020 // assert(!CS.hasInAllocaArgument() &&
7021 // "sret demotion is incompatible with inalloca");
7022 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7023 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7024 MachineFunction &MF = CLI.DAG.getMachineFunction();
7025 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7026 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7028 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7030 Entry.Node = DemoteStackSlot;
7031 Entry.Ty = StackSlotPtrType;
7032 Entry.isSExt = false;
7033 Entry.isZExt = false;
7034 Entry.isInReg = false;
7035 Entry.isSRet = true;
7036 Entry.isNest = false;
7037 Entry.isByVal = false;
7038 Entry.isReturned = false;
7039 Entry.Alignment = Align;
7040 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7041 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7043 // sret demotion isn't compatible with tail-calls, since the sret argument
7044 // points into the callers stack frame.
7045 CLI.IsTailCall = false;
7047 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7049 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7050 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7051 for (unsigned i = 0; i != NumRegs; ++i) {
7052 ISD::InputArg MyFlags;
7053 MyFlags.VT = RegisterVT;
7055 MyFlags.Used = CLI.IsReturnValueUsed;
7057 MyFlags.Flags.setSExt();
7059 MyFlags.Flags.setZExt();
7061 MyFlags.Flags.setInReg();
7062 CLI.Ins.push_back(MyFlags);
7067 // Handle all of the outgoing arguments.
7069 CLI.OutVals.clear();
7070 ArgListTy &Args = CLI.getArgs();
7071 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7072 SmallVector<EVT, 4> ValueVTs;
7073 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7074 Type *FinalType = Args[i].Ty;
7075 if (Args[i].isByVal)
7076 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7077 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7078 FinalType, CLI.CallConv, CLI.IsVarArg);
7079 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7081 EVT VT = ValueVTs[Value];
7082 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7083 SDValue Op = SDValue(Args[i].Node.getNode(),
7084 Args[i].Node.getResNo() + Value);
7085 ISD::ArgFlagsTy Flags;
7086 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7092 if (Args[i].isInReg)
7096 if (Args[i].isByVal)
7098 if (Args[i].isInAlloca) {
7099 Flags.setInAlloca();
7100 // Set the byval flag for CCAssignFn callbacks that don't know about
7101 // inalloca. This way we can know how many bytes we should've allocated
7102 // and how many bytes a callee cleanup function will pop. If we port
7103 // inalloca to more targets, we'll have to add custom inalloca handling
7104 // in the various CC lowering callbacks.
7107 if (Args[i].isByVal || Args[i].isInAlloca) {
7108 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7109 Type *ElementTy = Ty->getElementType();
7110 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7111 // For ByVal, alignment should come from FE. BE will guess if this
7112 // info is not there but there are cases it cannot get right.
7113 unsigned FrameAlign;
7114 if (Args[i].Alignment)
7115 FrameAlign = Args[i].Alignment;
7117 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7118 Flags.setByValAlign(FrameAlign);
7123 Flags.setInConsecutiveRegs();
7124 Flags.setOrigAlign(OriginalAlignment);
7126 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7127 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7128 SmallVector<SDValue, 4> Parts(NumParts);
7129 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7132 ExtendKind = ISD::SIGN_EXTEND;
7133 else if (Args[i].isZExt)
7134 ExtendKind = ISD::ZERO_EXTEND;
7136 // Conservatively only handle 'returned' on non-vectors for now
7137 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7138 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7139 "unexpected use of 'returned'");
7140 // Before passing 'returned' to the target lowering code, ensure that
7141 // either the register MVT and the actual EVT are the same size or that
7142 // the return value and argument are extended in the same way; in these
7143 // cases it's safe to pass the argument register value unchanged as the
7144 // return register value (although it's at the target's option whether
7146 // TODO: allow code generation to take advantage of partially preserved
7147 // registers rather than clobbering the entire register when the
7148 // parameter extension method is not compatible with the return
7150 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7151 (ExtendKind != ISD::ANY_EXTEND &&
7152 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7153 Flags.setReturned();
7156 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7157 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7159 for (unsigned j = 0; j != NumParts; ++j) {
7160 // if it isn't first piece, alignment must be 1
7161 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7162 i < CLI.NumFixedArgs,
7163 i, j*Parts[j].getValueType().getStoreSize());
7164 if (NumParts > 1 && j == 0)
7165 MyFlags.Flags.setSplit();
7167 MyFlags.Flags.setOrigAlign(1);
7169 CLI.Outs.push_back(MyFlags);
7170 CLI.OutVals.push_back(Parts[j]);
7173 if (NeedsRegBlock && Value == NumValues - 1)
7174 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7178 SmallVector<SDValue, 4> InVals;
7179 CLI.Chain = LowerCall(CLI, InVals);
7181 // Verify that the target's LowerCall behaved as expected.
7182 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7183 "LowerCall didn't return a valid chain!");
7184 assert((!CLI.IsTailCall || InVals.empty()) &&
7185 "LowerCall emitted a return value for a tail call!");
7186 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7187 "LowerCall didn't emit the correct number of values!");
7189 // For a tail call, the return value is merely live-out and there aren't
7190 // any nodes in the DAG representing it. Return a special value to
7191 // indicate that a tail call has been emitted and no more Instructions
7192 // should be processed in the current block.
7193 if (CLI.IsTailCall) {
7194 CLI.DAG.setRoot(CLI.Chain);
7195 return std::make_pair(SDValue(), SDValue());
7198 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7199 assert(InVals[i].getNode() &&
7200 "LowerCall emitted a null value!");
7201 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7202 "LowerCall emitted a value with the wrong type!");
7205 SmallVector<SDValue, 4> ReturnValues;
7206 if (!CanLowerReturn) {
7207 // The instruction result is the result of loading from the
7208 // hidden sret parameter.
7209 SmallVector<EVT, 1> PVTs;
7210 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7212 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7213 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7214 EVT PtrVT = PVTs[0];
7216 unsigned NumValues = RetTys.size();
7217 ReturnValues.resize(NumValues);
7218 SmallVector<SDValue, 4> Chains(NumValues);
7220 for (unsigned i = 0; i < NumValues; ++i) {
7221 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7222 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7224 SDValue L = CLI.DAG.getLoad(
7225 RetTys[i], CLI.DL, CLI.Chain, Add,
7226 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7227 DemoteStackIdx, Offsets[i]),
7228 false, false, false, 1);
7229 ReturnValues[i] = L;
7230 Chains[i] = L.getValue(1);
7233 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7235 // Collect the legal value parts into potentially illegal values
7236 // that correspond to the original function's return values.
7237 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7239 AssertOp = ISD::AssertSext;
7240 else if (CLI.RetZExt)
7241 AssertOp = ISD::AssertZext;
7242 unsigned CurReg = 0;
7243 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7245 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7246 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7248 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7249 NumRegs, RegisterVT, VT, nullptr,
7254 // For a function returning void, there is no return value. We can't create
7255 // such a node, so we just return a null return value in that case. In
7256 // that case, nothing will actually look at the value.
7257 if (ReturnValues.empty())
7258 return std::make_pair(SDValue(), CLI.Chain);
7261 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7262 CLI.DAG.getVTList(RetTys), ReturnValues);
7263 return std::make_pair(Res, CLI.Chain);
7266 void TargetLowering::LowerOperationWrapper(SDNode *N,
7267 SmallVectorImpl<SDValue> &Results,
7268 SelectionDAG &DAG) const {
7269 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7271 Results.push_back(Res);
7274 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7275 llvm_unreachable("LowerOperation not implemented for this target!");
7279 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7280 SDValue Op = getNonRegisterValue(V);
7281 assert((Op.getOpcode() != ISD::CopyFromReg ||
7282 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7283 "Copy from a reg to the same reg!");
7284 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7286 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7287 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7289 SDValue Chain = DAG.getEntryNode();
7291 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7292 FuncInfo.PreferredExtendType.end())
7294 : FuncInfo.PreferredExtendType[V];
7295 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7296 PendingExports.push_back(Chain);
7299 #include "llvm/CodeGen/SelectionDAGISel.h"
7301 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7302 /// entry block, return true. This includes arguments used by switches, since
7303 /// the switch may expand into multiple basic blocks.
7304 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7305 // With FastISel active, we may be splitting blocks, so force creation
7306 // of virtual registers for all non-dead arguments.
7308 return A->use_empty();
7310 const BasicBlock &Entry = A->getParent()->front();
7311 for (const User *U : A->users())
7312 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7313 return false; // Use not in entry block.
7318 void SelectionDAGISel::LowerArguments(const Function &F) {
7319 SelectionDAG &DAG = SDB->DAG;
7320 SDLoc dl = SDB->getCurSDLoc();
7321 const DataLayout &DL = DAG.getDataLayout();
7322 SmallVector<ISD::InputArg, 16> Ins;
7324 if (!FuncInfo->CanLowerReturn) {
7325 // Put in an sret pointer parameter before all the other parameters.
7326 SmallVector<EVT, 1> ValueVTs;
7327 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7328 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7330 // NOTE: Assuming that a pointer will never break down to more than one VT
7332 ISD::ArgFlagsTy Flags;
7334 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7335 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7336 ISD::InputArg::NoArgIndex, 0);
7337 Ins.push_back(RetArg);
7340 // Set up the incoming argument description vector.
7342 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7343 I != E; ++I, ++Idx) {
7344 SmallVector<EVT, 4> ValueVTs;
7345 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7346 bool isArgValueUsed = !I->use_empty();
7347 unsigned PartBase = 0;
7348 Type *FinalType = I->getType();
7349 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7350 FinalType = cast<PointerType>(FinalType)->getElementType();
7351 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7352 FinalType, F.getCallingConv(), F.isVarArg());
7353 for (unsigned Value = 0, NumValues = ValueVTs.size();
7354 Value != NumValues; ++Value) {
7355 EVT VT = ValueVTs[Value];
7356 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7357 ISD::ArgFlagsTy Flags;
7358 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7360 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7362 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7364 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7366 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7368 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7370 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7371 Flags.setInAlloca();
7372 // Set the byval flag for CCAssignFn callbacks that don't know about
7373 // inalloca. This way we can know how many bytes we should've allocated
7374 // and how many bytes a callee cleanup function will pop. If we port
7375 // inalloca to more targets, we'll have to add custom inalloca handling
7376 // in the various CC lowering callbacks.
7379 if (Flags.isByVal() || Flags.isInAlloca()) {
7380 PointerType *Ty = cast<PointerType>(I->getType());
7381 Type *ElementTy = Ty->getElementType();
7382 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7383 // For ByVal, alignment should be passed from FE. BE will guess if
7384 // this info is not there but there are cases it cannot get right.
7385 unsigned FrameAlign;
7386 if (F.getParamAlignment(Idx))
7387 FrameAlign = F.getParamAlignment(Idx);
7389 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7390 Flags.setByValAlign(FrameAlign);
7392 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7395 Flags.setInConsecutiveRegs();
7396 Flags.setOrigAlign(OriginalAlignment);
7398 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7399 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7400 for (unsigned i = 0; i != NumRegs; ++i) {
7401 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7402 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7403 if (NumRegs > 1 && i == 0)
7404 MyFlags.Flags.setSplit();
7405 // if it isn't first piece, alignment must be 1
7407 MyFlags.Flags.setOrigAlign(1);
7408 Ins.push_back(MyFlags);
7410 if (NeedsRegBlock && Value == NumValues - 1)
7411 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7412 PartBase += VT.getStoreSize();
7416 // Call the target to set up the argument values.
7417 SmallVector<SDValue, 8> InVals;
7418 SDValue NewRoot = TLI->LowerFormalArguments(
7419 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7421 // Verify that the target's LowerFormalArguments behaved as expected.
7422 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7423 "LowerFormalArguments didn't return a valid chain!");
7424 assert(InVals.size() == Ins.size() &&
7425 "LowerFormalArguments didn't emit the correct number of values!");
7427 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7428 assert(InVals[i].getNode() &&
7429 "LowerFormalArguments emitted a null value!");
7430 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7431 "LowerFormalArguments emitted a value with the wrong type!");
7435 // Update the DAG with the new chain value resulting from argument lowering.
7436 DAG.setRoot(NewRoot);
7438 // Set up the argument values.
7441 if (!FuncInfo->CanLowerReturn) {
7442 // Create a virtual register for the sret pointer, and put in a copy
7443 // from the sret argument into it.
7444 SmallVector<EVT, 1> ValueVTs;
7445 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7446 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7447 MVT VT = ValueVTs[0].getSimpleVT();
7448 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7449 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7450 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7451 RegVT, VT, nullptr, AssertOp);
7453 MachineFunction& MF = SDB->DAG.getMachineFunction();
7454 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7455 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7456 FuncInfo->DemoteRegister = SRetReg;
7458 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7459 DAG.setRoot(NewRoot);
7461 // i indexes lowered arguments. Bump it past the hidden sret argument.
7462 // Idx indexes LLVM arguments. Don't touch it.
7466 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7468 SmallVector<SDValue, 4> ArgValues;
7469 SmallVector<EVT, 4> ValueVTs;
7470 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7471 unsigned NumValues = ValueVTs.size();
7473 // If this argument is unused then remember its value. It is used to generate
7474 // debugging information.
7475 if (I->use_empty() && NumValues) {
7476 SDB->setUnusedArgValue(&*I, InVals[i]);
7478 // Also remember any frame index for use in FastISel.
7479 if (FrameIndexSDNode *FI =
7480 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7481 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7484 for (unsigned Val = 0; Val != NumValues; ++Val) {
7485 EVT VT = ValueVTs[Val];
7486 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7487 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7489 if (!I->use_empty()) {
7490 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7491 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7492 AssertOp = ISD::AssertSext;
7493 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7494 AssertOp = ISD::AssertZext;
7496 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7497 NumParts, PartVT, VT,
7498 nullptr, AssertOp));
7504 // We don't need to do anything else for unused arguments.
7505 if (ArgValues.empty())
7508 // Note down frame index.
7509 if (FrameIndexSDNode *FI =
7510 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7511 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7513 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7514 SDB->getCurSDLoc());
7516 SDB->setValue(&*I, Res);
7517 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7518 if (LoadSDNode *LNode =
7519 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7520 if (FrameIndexSDNode *FI =
7521 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7522 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7525 // If this argument is live outside of the entry block, insert a copy from
7526 // wherever we got it to the vreg that other BB's will reference it as.
7527 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7528 // If we can, though, try to skip creating an unnecessary vreg.
7529 // FIXME: This isn't very clean... it would be nice to make this more
7530 // general. It's also subtly incompatible with the hacks FastISel
7532 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7533 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7534 FuncInfo->ValueMap[&*I] = Reg;
7538 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7539 FuncInfo->InitializeRegForValue(&*I);
7540 SDB->CopyToExportRegsIfNeeded(&*I);
7544 assert(i == InVals.size() && "Argument register count mismatch!");
7546 // Finally, if the target has anything special to do, allow it to do so.
7547 EmitFunctionEntryCode();
7550 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7551 /// ensure constants are generated when needed. Remember the virtual registers
7552 /// that need to be added to the Machine PHI nodes as input. We cannot just
7553 /// directly add them, because expansion might result in multiple MBB's for one
7554 /// BB. As such, the start of the BB might correspond to a different MBB than
7558 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7559 const TerminatorInst *TI = LLVMBB->getTerminator();
7561 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7563 // Check PHI nodes in successors that expect a value to be available from this
7565 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7566 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7567 if (!isa<PHINode>(SuccBB->begin())) continue;
7568 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7570 // If this terminator has multiple identical successors (common for
7571 // switches), only handle each succ once.
7572 if (!SuccsHandled.insert(SuccMBB).second)
7575 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7577 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7578 // nodes and Machine PHI nodes, but the incoming operands have not been
7580 for (BasicBlock::const_iterator I = SuccBB->begin();
7581 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7582 // Ignore dead phi's.
7583 if (PN->use_empty()) continue;
7586 if (PN->getType()->isEmptyTy())
7590 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7592 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7593 unsigned &RegOut = ConstantsOut[C];
7595 RegOut = FuncInfo.CreateRegs(C->getType());
7596 CopyValueToVirtualRegister(C, RegOut);
7600 DenseMap<const Value *, unsigned>::iterator I =
7601 FuncInfo.ValueMap.find(PHIOp);
7602 if (I != FuncInfo.ValueMap.end())
7605 assert(isa<AllocaInst>(PHIOp) &&
7606 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7607 "Didn't codegen value into a register!??");
7608 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7609 CopyValueToVirtualRegister(PHIOp, Reg);
7613 // Remember that this register needs to added to the machine PHI node as
7614 // the input for this MBB.
7615 SmallVector<EVT, 4> ValueVTs;
7616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7617 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7618 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7619 EVT VT = ValueVTs[vti];
7620 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7621 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7622 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7623 Reg += NumRegisters;
7628 ConstantsOut.clear();
7631 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7634 SelectionDAGBuilder::StackProtectorDescriptor::
7635 AddSuccessorMBB(const BasicBlock *BB,
7636 MachineBasicBlock *ParentMBB,
7638 MachineBasicBlock *SuccMBB) {
7639 // If SuccBB has not been created yet, create it.
7641 MachineFunction *MF = ParentMBB->getParent();
7642 MachineFunction::iterator BBI(ParentMBB);
7643 SuccMBB = MF->CreateMachineBasicBlock(BB);
7644 MF->insert(++BBI, SuccMBB);
7646 // Add it as a successor of ParentMBB.
7647 ParentMBB->addSuccessor(
7648 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7652 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7653 MachineFunction::iterator I(MBB);
7654 if (++I == FuncInfo.MF->end())
7659 /// During lowering new call nodes can be created (such as memset, etc.).
7660 /// Those will become new roots of the current DAG, but complications arise
7661 /// when they are tail calls. In such cases, the call lowering will update
7662 /// the root, but the builder still needs to know that a tail call has been
7663 /// lowered in order to avoid generating an additional return.
7664 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7665 // If the node is null, we do have a tail call.
7666 if (MaybeTC.getNode() != nullptr)
7667 DAG.setRoot(MaybeTC);
7672 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7673 unsigned *TotalCases, unsigned First,
7675 assert(Last >= First);
7676 assert(TotalCases[Last] >= TotalCases[First]);
7678 APInt LowCase = Clusters[First].Low->getValue();
7679 APInt HighCase = Clusters[Last].High->getValue();
7680 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7682 // FIXME: A range of consecutive cases has 100% density, but only requires one
7683 // comparison to lower. We should discriminate against such consecutive ranges
7686 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7687 uint64_t Range = Diff + 1;
7690 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7692 assert(NumCases < UINT64_MAX / 100);
7693 assert(Range >= NumCases);
7695 return NumCases * 100 >= Range * MinJumpTableDensity;
7698 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7699 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7700 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7703 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7704 unsigned First, unsigned Last,
7705 const SwitchInst *SI,
7706 MachineBasicBlock *DefaultMBB,
7707 CaseCluster &JTCluster) {
7708 assert(First <= Last);
7710 uint32_t Weight = 0;
7711 unsigned NumCmps = 0;
7712 std::vector<MachineBasicBlock*> Table;
7713 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7714 for (unsigned I = First; I <= Last; ++I) {
7715 assert(Clusters[I].Kind == CC_Range);
7716 Weight += Clusters[I].Weight;
7717 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7718 APInt Low = Clusters[I].Low->getValue();
7719 APInt High = Clusters[I].High->getValue();
7720 NumCmps += (Low == High) ? 1 : 2;
7722 // Fill the gap between this and the previous cluster.
7723 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7724 assert(PreviousHigh.slt(Low));
7725 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7726 for (uint64_t J = 0; J < Gap; J++)
7727 Table.push_back(DefaultMBB);
7729 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7730 for (uint64_t J = 0; J < ClusterSize; ++J)
7731 Table.push_back(Clusters[I].MBB);
7732 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7735 unsigned NumDests = JTWeights.size();
7736 if (isSuitableForBitTests(NumDests, NumCmps,
7737 Clusters[First].Low->getValue(),
7738 Clusters[Last].High->getValue())) {
7739 // Clusters[First..Last] should be lowered as bit tests instead.
7743 // Create the MBB that will load from and jump through the table.
7744 // Note: We create it here, but it's not inserted into the function yet.
7745 MachineFunction *CurMF = FuncInfo.MF;
7746 MachineBasicBlock *JumpTableMBB =
7747 CurMF->CreateMachineBasicBlock(SI->getParent());
7749 // Add successors. Note: use table order for determinism.
7750 SmallPtrSet<MachineBasicBlock *, 8> Done;
7751 for (MachineBasicBlock *Succ : Table) {
7752 if (Done.count(Succ))
7754 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7758 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7759 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7760 ->createJumpTableIndex(Table);
7762 // Set up the jump table info.
7763 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7764 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7765 Clusters[Last].High->getValue(), SI->getCondition(),
7767 JTCases.emplace_back(std::move(JTH), std::move(JT));
7769 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7770 JTCases.size() - 1, Weight);
7774 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7775 const SwitchInst *SI,
7776 MachineBasicBlock *DefaultMBB) {
7778 // Clusters must be non-empty, sorted, and only contain Range clusters.
7779 assert(!Clusters.empty());
7780 for (CaseCluster &C : Clusters)
7781 assert(C.Kind == CC_Range);
7782 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7783 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7786 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7787 if (!areJTsAllowed(TLI))
7790 const int64_t N = Clusters.size();
7791 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7793 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7794 SmallVector<unsigned, 8> TotalCases(N);
7796 for (unsigned i = 0; i < N; ++i) {
7797 APInt Hi = Clusters[i].High->getValue();
7798 APInt Lo = Clusters[i].Low->getValue();
7799 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7801 TotalCases[i] += TotalCases[i - 1];
7804 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7805 // Cheap case: the whole range might be suitable for jump table.
7806 CaseCluster JTCluster;
7807 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7808 Clusters[0] = JTCluster;
7814 // The algorithm below is not suitable for -O0.
7815 if (TM.getOptLevel() == CodeGenOpt::None)
7818 // Split Clusters into minimum number of dense partitions. The algorithm uses
7819 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7820 // for the Case Statement'" (1994), but builds the MinPartitions array in
7821 // reverse order to make it easier to reconstruct the partitions in ascending
7822 // order. In the choice between two optimal partitionings, it picks the one
7823 // which yields more jump tables.
7825 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7826 SmallVector<unsigned, 8> MinPartitions(N);
7827 // LastElement[i] is the last element of the partition starting at i.
7828 SmallVector<unsigned, 8> LastElement(N);
7829 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7830 SmallVector<unsigned, 8> NumTables(N);
7832 // Base case: There is only one way to partition Clusters[N-1].
7833 MinPartitions[N - 1] = 1;
7834 LastElement[N - 1] = N - 1;
7835 assert(MinJumpTableSize > 1);
7836 NumTables[N - 1] = 0;
7838 // Note: loop indexes are signed to avoid underflow.
7839 for (int64_t i = N - 2; i >= 0; i--) {
7840 // Find optimal partitioning of Clusters[i..N-1].
7841 // Baseline: Put Clusters[i] into a partition on its own.
7842 MinPartitions[i] = MinPartitions[i + 1] + 1;
7844 NumTables[i] = NumTables[i + 1];
7846 // Search for a solution that results in fewer partitions.
7847 for (int64_t j = N - 1; j > i; j--) {
7848 // Try building a partition from Clusters[i..j].
7849 if (isDense(Clusters, &TotalCases[0], i, j)) {
7850 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7851 bool IsTable = j - i + 1 >= MinJumpTableSize;
7852 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7854 // If this j leads to fewer partitions, or same number of partitions
7855 // with more lookup tables, it is a better partitioning.
7856 if (NumPartitions < MinPartitions[i] ||
7857 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7858 MinPartitions[i] = NumPartitions;
7860 NumTables[i] = Tables;
7866 // Iterate over the partitions, replacing some with jump tables in-place.
7867 unsigned DstIndex = 0;
7868 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7869 Last = LastElement[First];
7870 assert(Last >= First);
7871 assert(DstIndex <= First);
7872 unsigned NumClusters = Last - First + 1;
7874 CaseCluster JTCluster;
7875 if (NumClusters >= MinJumpTableSize &&
7876 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7877 Clusters[DstIndex++] = JTCluster;
7879 for (unsigned I = First; I <= Last; ++I)
7880 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7883 Clusters.resize(DstIndex);
7886 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7887 // FIXME: Using the pointer type doesn't seem ideal.
7888 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7889 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7893 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7896 const APInt &High) {
7897 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7898 // range of cases both require only one branch to lower. Just looking at the
7899 // number of clusters and destinations should be enough to decide whether to
7902 // To lower a range with bit tests, the range must fit the bitwidth of a
7904 if (!rangeFitsInWord(Low, High))
7907 // Decide whether it's profitable to lower this range with bit tests. Each
7908 // destination requires a bit test and branch, and there is an overall range
7909 // check branch. For a small number of clusters, separate comparisons might be
7910 // cheaper, and for many destinations, splitting the range might be better.
7911 return (NumDests == 1 && NumCmps >= 3) ||
7912 (NumDests == 2 && NumCmps >= 5) ||
7913 (NumDests == 3 && NumCmps >= 6);
7916 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7917 unsigned First, unsigned Last,
7918 const SwitchInst *SI,
7919 CaseCluster &BTCluster) {
7920 assert(First <= Last);
7924 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7925 unsigned NumCmps = 0;
7926 for (int64_t I = First; I <= Last; ++I) {
7927 assert(Clusters[I].Kind == CC_Range);
7928 Dests.set(Clusters[I].MBB->getNumber());
7929 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7931 unsigned NumDests = Dests.count();
7933 APInt Low = Clusters[First].Low->getValue();
7934 APInt High = Clusters[Last].High->getValue();
7935 assert(Low.slt(High));
7937 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7943 const int BitWidth = DAG.getTargetLoweringInfo()
7944 .getPointerTy(DAG.getDataLayout())
7946 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7948 // Check if the clusters cover a contiguous range such that no value in the
7949 // range will jump to the default statement.
7950 bool ContiguousRange = true;
7951 for (int64_t I = First + 1; I <= Last; ++I) {
7952 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7953 ContiguousRange = false;
7958 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7959 // Optimize the case where all the case values fit in a word without having
7960 // to subtract minValue. In this case, we can optimize away the subtraction.
7961 LowBound = APInt::getNullValue(Low.getBitWidth());
7963 ContiguousRange = false;
7966 CmpRange = High - Low;
7970 uint32_t TotalWeight = 0;
7971 for (unsigned i = First; i <= Last; ++i) {
7972 // Find the CaseBits for this destination.
7974 for (j = 0; j < CBV.size(); ++j)
7975 if (CBV[j].BB == Clusters[i].MBB)
7977 if (j == CBV.size())
7978 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7979 CaseBits *CB = &CBV[j];
7981 // Update Mask, Bits and ExtraWeight.
7982 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7983 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7984 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7985 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7986 CB->Bits += Hi - Lo + 1;
7987 CB->ExtraWeight += Clusters[i].Weight;
7988 TotalWeight += Clusters[i].Weight;
7989 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7993 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7994 // Sort by weight first, number of bits second.
7995 if (a.ExtraWeight != b.ExtraWeight)
7996 return a.ExtraWeight > b.ExtraWeight;
7997 return a.Bits > b.Bits;
8000 for (auto &CB : CBV) {
8001 MachineBasicBlock *BitTestBB =
8002 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
8003 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
8005 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
8006 SI->getCondition(), -1U, MVT::Other, false,
8007 ContiguousRange, nullptr, nullptr, std::move(BTI),
8010 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
8011 BitTestCases.size() - 1, TotalWeight);
8015 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8016 const SwitchInst *SI) {
8017 // Partition Clusters into as few subsets as possible, where each subset has a
8018 // range that fits in a machine word and has <= 3 unique destinations.
8021 // Clusters must be sorted and contain Range or JumpTable clusters.
8022 assert(!Clusters.empty());
8023 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8024 for (const CaseCluster &C : Clusters)
8025 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8026 for (unsigned i = 1; i < Clusters.size(); ++i)
8027 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8030 // The algorithm below is not suitable for -O0.
8031 if (TM.getOptLevel() == CodeGenOpt::None)
8034 // If target does not have legal shift left, do not emit bit tests at all.
8035 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8036 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8037 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8040 int BitWidth = PTy.getSizeInBits();
8041 const int64_t N = Clusters.size();
8043 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8044 SmallVector<unsigned, 8> MinPartitions(N);
8045 // LastElement[i] is the last element of the partition starting at i.
8046 SmallVector<unsigned, 8> LastElement(N);
8048 // FIXME: This might not be the best algorithm for finding bit test clusters.
8050 // Base case: There is only one way to partition Clusters[N-1].
8051 MinPartitions[N - 1] = 1;
8052 LastElement[N - 1] = N - 1;
8054 // Note: loop indexes are signed to avoid underflow.
8055 for (int64_t i = N - 2; i >= 0; --i) {
8056 // Find optimal partitioning of Clusters[i..N-1].
8057 // Baseline: Put Clusters[i] into a partition on its own.
8058 MinPartitions[i] = MinPartitions[i + 1] + 1;
8061 // Search for a solution that results in fewer partitions.
8062 // Note: the search is limited by BitWidth, reducing time complexity.
8063 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8064 // Try building a partition from Clusters[i..j].
8067 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8068 Clusters[j].High->getValue()))
8071 // Check nbr of destinations and cluster types.
8072 // FIXME: This works, but doesn't seem very efficient.
8073 bool RangesOnly = true;
8074 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8075 for (int64_t k = i; k <= j; k++) {
8076 if (Clusters[k].Kind != CC_Range) {
8080 Dests.set(Clusters[k].MBB->getNumber());
8082 if (!RangesOnly || Dests.count() > 3)
8085 // Check if it's a better partition.
8086 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8087 if (NumPartitions < MinPartitions[i]) {
8088 // Found a better partition.
8089 MinPartitions[i] = NumPartitions;
8095 // Iterate over the partitions, replacing with bit-test clusters in-place.
8096 unsigned DstIndex = 0;
8097 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8098 Last = LastElement[First];
8099 assert(First <= Last);
8100 assert(DstIndex <= First);
8102 CaseCluster BitTestCluster;
8103 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8104 Clusters[DstIndex++] = BitTestCluster;
8106 size_t NumClusters = Last - First + 1;
8107 std::memmove(&Clusters[DstIndex], &Clusters[First],
8108 sizeof(Clusters[0]) * NumClusters);
8109 DstIndex += NumClusters;
8112 Clusters.resize(DstIndex);
8115 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8116 MachineBasicBlock *SwitchMBB,
8117 MachineBasicBlock *DefaultMBB) {
8118 MachineFunction *CurMF = FuncInfo.MF;
8119 MachineBasicBlock *NextMBB = nullptr;
8120 MachineFunction::iterator BBI(W.MBB);
8121 if (++BBI != FuncInfo.MF->end())
8124 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8126 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8128 if (Size == 2 && W.MBB == SwitchMBB) {
8129 // If any two of the cases has the same destination, and if one value
8130 // is the same as the other, but has one bit unset that the other has set,
8131 // use bit manipulation to do two compares at once. For example:
8132 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8133 // TODO: This could be extended to merge any 2 cases in switches with 3
8135 // TODO: Handle cases where W.CaseBB != SwitchBB.
8136 CaseCluster &Small = *W.FirstCluster;
8137 CaseCluster &Big = *W.LastCluster;
8139 if (Small.Low == Small.High && Big.Low == Big.High &&
8140 Small.MBB == Big.MBB) {
8141 const APInt &SmallValue = Small.Low->getValue();
8142 const APInt &BigValue = Big.Low->getValue();
8144 // Check that there is only one bit different.
8145 APInt CommonBit = BigValue ^ SmallValue;
8146 if (CommonBit.isPowerOf2()) {
8147 SDValue CondLHS = getValue(Cond);
8148 EVT VT = CondLHS.getValueType();
8149 SDLoc DL = getCurSDLoc();
8151 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8152 DAG.getConstant(CommonBit, DL, VT));
8153 SDValue Cond = DAG.getSetCC(
8154 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8157 // Update successor info.
8158 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8159 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8160 addSuccessorWithWeight(
8161 SwitchMBB, DefaultMBB,
8162 // The default destination is the first successor in IR.
8163 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8166 // Insert the true branch.
8168 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8169 DAG.getBasicBlock(Small.MBB));
8170 // Insert the false branch.
8171 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8172 DAG.getBasicBlock(DefaultMBB));
8174 DAG.setRoot(BrCond);
8180 if (TM.getOptLevel() != CodeGenOpt::None) {
8181 // Order cases by weight so the most likely case will be checked first.
8182 std::sort(W.FirstCluster, W.LastCluster + 1,
8183 [](const CaseCluster &a, const CaseCluster &b) {
8184 return a.Weight > b.Weight;
8187 // Rearrange the case blocks so that the last one falls through if possible
8188 // without without changing the order of weights.
8189 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8191 if (I->Weight > W.LastCluster->Weight)
8193 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8194 std::swap(*I, *W.LastCluster);
8200 // Compute total weight.
8201 uint32_t DefaultWeight = W.DefaultWeight;
8202 uint32_t UnhandledWeights = DefaultWeight;
8203 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8204 UnhandledWeights += I->Weight;
8205 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8208 MachineBasicBlock *CurMBB = W.MBB;
8209 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8210 MachineBasicBlock *Fallthrough;
8211 if (I == W.LastCluster) {
8212 // For the last cluster, fall through to the default destination.
8213 Fallthrough = DefaultMBB;
8215 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8216 CurMF->insert(BBI, Fallthrough);
8217 // Put Cond in a virtual register to make it available from the new blocks.
8218 ExportFromCurrentBlock(Cond);
8220 UnhandledWeights -= I->Weight;
8223 case CC_JumpTable: {
8224 // FIXME: Optimize away range check based on pivot comparisons.
8225 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8226 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8228 // The jump block hasn't been inserted yet; insert it here.
8229 MachineBasicBlock *JumpMBB = JT->MBB;
8230 CurMF->insert(BBI, JumpMBB);
8232 uint32_t JumpWeight = I->Weight;
8233 uint32_t FallthroughWeight = UnhandledWeights;
8235 // If the default statement is a target of the jump table, we evenly
8236 // distribute the default weight to successors of CurMBB. Also update
8237 // the weight on the edge from JumpMBB to Fallthrough.
8238 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8239 SE = JumpMBB->succ_end();
8241 if (*SI == DefaultMBB) {
8242 JumpWeight += DefaultWeight / 2;
8243 FallthroughWeight -= DefaultWeight / 2;
8244 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8249 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8250 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8252 // The jump table header will be inserted in our current block, do the
8253 // range check, and fall through to our fallthrough block.
8254 JTH->HeaderBB = CurMBB;
8255 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8257 // If we're in the right place, emit the jump table header right now.
8258 if (CurMBB == SwitchMBB) {
8259 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8260 JTH->Emitted = true;
8265 // FIXME: Optimize away range check based on pivot comparisons.
8266 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8268 // The bit test blocks haven't been inserted yet; insert them here.
8269 for (BitTestCase &BTC : BTB->Cases)
8270 CurMF->insert(BBI, BTC.ThisBB);
8272 // Fill in fields of the BitTestBlock.
8273 BTB->Parent = CurMBB;
8274 BTB->Default = Fallthrough;
8276 BTB->DefaultWeight = UnhandledWeights;
8277 // If the cases in bit test don't form a contiguous range, we evenly
8278 // distribute the weight on the edge to Fallthrough to two successors
8280 if (!BTB->ContiguousRange) {
8281 BTB->Weight += DefaultWeight / 2;
8282 BTB->DefaultWeight -= DefaultWeight / 2;
8285 // If we're in the right place, emit the bit test header right now.
8286 if (CurMBB == SwitchMBB) {
8287 visitBitTestHeader(*BTB, SwitchMBB);
8288 BTB->Emitted = true;
8293 const Value *RHS, *LHS, *MHS;
8295 if (I->Low == I->High) {
8296 // Check Cond == I->Low.
8302 // Check I->Low <= Cond <= I->High.
8309 // The false weight is the sum of all unhandled cases.
8310 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8313 if (CurMBB == SwitchMBB)
8314 visitSwitchCase(CB, SwitchMBB);
8316 SwitchCases.push_back(CB);
8321 CurMBB = Fallthrough;
8325 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8326 CaseClusterIt First,
8327 CaseClusterIt Last) {
8328 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8329 if (X.Weight != CC.Weight)
8330 return X.Weight > CC.Weight;
8332 // Ties are broken by comparing the case value.
8333 return X.Low->getValue().slt(CC.Low->getValue());
8337 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8338 const SwitchWorkListItem &W,
8340 MachineBasicBlock *SwitchMBB) {
8341 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8342 "Clusters not sorted?");
8344 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8346 // Balance the tree based on branch weights to create a near-optimal (in terms
8347 // of search time given key frequency) binary search tree. See e.g. Kurt
8348 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8349 CaseClusterIt LastLeft = W.FirstCluster;
8350 CaseClusterIt FirstRight = W.LastCluster;
8351 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8352 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8354 // Move LastLeft and FirstRight towards each other from opposite directions to
8355 // find a partitioning of the clusters which balances the weight on both
8356 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8357 // taken to ensure 0-weight nodes are distributed evenly.
8359 while (LastLeft + 1 < FirstRight) {
8360 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8361 LeftWeight += (++LastLeft)->Weight;
8363 RightWeight += (--FirstRight)->Weight;
8368 // Our binary search tree differs from a typical BST in that ours can have up
8369 // to three values in each leaf. The pivot selection above doesn't take that
8370 // into account, which means the tree might require more nodes and be less
8371 // efficient. We compensate for this here.
8373 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8374 unsigned NumRight = W.LastCluster - FirstRight + 1;
8376 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8377 // If one side has less than 3 clusters, and the other has more than 3,
8378 // consider taking a cluster from the other side.
8380 if (NumLeft < NumRight) {
8381 // Consider moving the first cluster on the right to the left side.
8382 CaseCluster &CC = *FirstRight;
8383 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8384 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8385 if (LeftSideRank <= RightSideRank) {
8386 // Moving the cluster to the left does not demote it.
8392 assert(NumRight < NumLeft);
8393 // Consider moving the last element on the left to the right side.
8394 CaseCluster &CC = *LastLeft;
8395 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8396 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8397 if (RightSideRank <= LeftSideRank) {
8398 // Moving the cluster to the right does not demot it.
8408 assert(LastLeft + 1 == FirstRight);
8409 assert(LastLeft >= W.FirstCluster);
8410 assert(FirstRight <= W.LastCluster);
8412 // Use the first element on the right as pivot since we will make less-than
8413 // comparisons against it.
8414 CaseClusterIt PivotCluster = FirstRight;
8415 assert(PivotCluster > W.FirstCluster);
8416 assert(PivotCluster <= W.LastCluster);
8418 CaseClusterIt FirstLeft = W.FirstCluster;
8419 CaseClusterIt LastRight = W.LastCluster;
8421 const ConstantInt *Pivot = PivotCluster->Low;
8423 // New blocks will be inserted immediately after the current one.
8424 MachineFunction::iterator BBI(W.MBB);
8427 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8428 // we can branch to its destination directly if it's squeezed exactly in
8429 // between the known lower bound and Pivot - 1.
8430 MachineBasicBlock *LeftMBB;
8431 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8432 FirstLeft->Low == W.GE &&
8433 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8434 LeftMBB = FirstLeft->MBB;
8436 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8437 FuncInfo.MF->insert(BBI, LeftMBB);
8439 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8440 // Put Cond in a virtual register to make it available from the new blocks.
8441 ExportFromCurrentBlock(Cond);
8444 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8445 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8446 // directly if RHS.High equals the current upper bound.
8447 MachineBasicBlock *RightMBB;
8448 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8449 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8450 RightMBB = FirstRight->MBB;
8452 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8453 FuncInfo.MF->insert(BBI, RightMBB);
8455 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8456 // Put Cond in a virtual register to make it available from the new blocks.
8457 ExportFromCurrentBlock(Cond);
8460 // Create the CaseBlock record that will be used to lower the branch.
8461 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8462 LeftWeight, RightWeight);
8464 if (W.MBB == SwitchMBB)
8465 visitSwitchCase(CB, SwitchMBB);
8467 SwitchCases.push_back(CB);
8470 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8471 // Extract cases from the switch.
8472 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8473 CaseClusterVector Clusters;
8474 Clusters.reserve(SI.getNumCases());
8475 for (auto I : SI.cases()) {
8476 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8477 const ConstantInt *CaseVal = I.getCaseValue();
8479 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8480 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8483 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8485 // Cluster adjacent cases with the same destination. We do this at all
8486 // optimization levels because it's cheap to do and will make codegen faster
8487 // if there are many clusters.
8488 sortAndRangeify(Clusters);
8490 if (TM.getOptLevel() != CodeGenOpt::None) {
8491 // Replace an unreachable default with the most popular destination.
8492 // FIXME: Exploit unreachable default more aggressively.
8493 bool UnreachableDefault =
8494 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8495 if (UnreachableDefault && !Clusters.empty()) {
8496 DenseMap<const BasicBlock *, unsigned> Popularity;
8497 unsigned MaxPop = 0;
8498 const BasicBlock *MaxBB = nullptr;
8499 for (auto I : SI.cases()) {
8500 const BasicBlock *BB = I.getCaseSuccessor();
8501 if (++Popularity[BB] > MaxPop) {
8502 MaxPop = Popularity[BB];
8507 assert(MaxPop > 0 && MaxBB);
8508 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8510 // Remove cases that were pointing to the destination that is now the
8512 CaseClusterVector New;
8513 New.reserve(Clusters.size());
8514 for (CaseCluster &CC : Clusters) {
8515 if (CC.MBB != DefaultMBB)
8518 Clusters = std::move(New);
8522 // If there is only the default destination, jump there directly.
8523 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8524 if (Clusters.empty()) {
8525 SwitchMBB->addSuccessor(DefaultMBB);
8526 if (DefaultMBB != NextBlock(SwitchMBB)) {
8527 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8528 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8533 findJumpTables(Clusters, &SI, DefaultMBB);
8534 findBitTestClusters(Clusters, &SI);
8537 dbgs() << "Case clusters: ";
8538 for (const CaseCluster &C : Clusters) {
8539 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8540 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8542 C.Low->getValue().print(dbgs(), true);
8543 if (C.Low != C.High) {
8545 C.High->getValue().print(dbgs(), true);
8552 assert(!Clusters.empty());
8553 SwitchWorkList WorkList;
8554 CaseClusterIt First = Clusters.begin();
8555 CaseClusterIt Last = Clusters.end() - 1;
8556 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8557 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8559 while (!WorkList.empty()) {
8560 SwitchWorkListItem W = WorkList.back();
8561 WorkList.pop_back();
8562 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8564 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8565 // For optimized builds, lower large range as a balanced binary tree.
8566 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8570 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);