1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/GCMetadata.h"
28 #include "llvm/CodeGen/GCStrategy.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/StackMaps.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/Instructions.h"
47 #include "llvm/IR/IntrinsicInst.h"
48 #include "llvm/IR/Intrinsics.h"
49 #include "llvm/IR/LLVMContext.h"
50 #include "llvm/IR/Module.h"
51 #include "llvm/IR/Statepoint.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetFrameLowering.h"
59 #include "llvm/Target/TargetInstrInfo.h"
60 #include "llvm/Target/TargetIntrinsicInfo.h"
61 #include "llvm/Target/TargetLowering.h"
62 #include "llvm/Target/TargetOptions.h"
63 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #include "llvm/Target/TargetSubtargetInfo.h"
68 #define DEBUG_TYPE "isel"
70 /// LimitFloatPrecision - Generate low-precision inline sequences for
71 /// some float libcalls (6, 8 or 12 bits).
72 static unsigned LimitFloatPrecision;
74 static cl::opt<unsigned, true>
75 LimitFPPrecision("limit-float-precision",
76 cl::desc("Generate low-precision inline sequences "
77 "for some float libcalls"),
78 cl::location(LimitFloatPrecision),
81 // Limit the width of DAG chains. This is important in general to prevent
82 // prevent DAG-based analysis from blowing up. For example, alias analysis and
83 // load clustering may not complete in reasonable time. It is difficult to
84 // recognize and avoid this situation within each individual analysis, and
85 // future analyses are likely to have the same behavior. Limiting DAG width is
86 // the safe approach, and will be especially important with global DAGs.
88 // MaxParallelChains default is arbitrarily high to avoid affecting
89 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
90 // sequence over this should have been converted to llvm.memcpy by the
91 // frontend. It easy to induce this behavior with .ll code such as:
92 // %buffer = alloca [4096 x i8]
93 // %data = load [4096 x i8]* %argPtr
94 // store [4096 x i8] %data, [4096 x i8]* %buffer
95 static const unsigned MaxParallelChains = 64;
97 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
98 const SDValue *Parts, unsigned NumParts,
99 MVT PartVT, EVT ValueVT, const Value *V);
101 /// getCopyFromParts - Create a value that contains the specified legal parts
102 /// combined into the value they represent. If the parts combine to a type
103 /// larger then ValueVT then AssertOp can be used to specify whether the extra
104 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
105 /// (ISD::AssertSext).
106 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
107 const SDValue *Parts,
108 unsigned NumParts, MVT PartVT, EVT ValueVT,
110 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
111 if (ValueVT.isVector())
112 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
115 assert(NumParts > 0 && "No parts to assemble!");
116 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
117 SDValue Val = Parts[0];
120 // Assemble the value from multiple parts.
121 if (ValueVT.isInteger()) {
122 unsigned PartBits = PartVT.getSizeInBits();
123 unsigned ValueBits = ValueVT.getSizeInBits();
125 // Assemble the power of 2 part.
126 unsigned RoundParts = NumParts & (NumParts - 1) ?
127 1 << Log2_32(NumParts) : NumParts;
128 unsigned RoundBits = PartBits * RoundParts;
129 EVT RoundVT = RoundBits == ValueBits ?
130 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
133 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
135 if (RoundParts > 2) {
136 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
138 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
139 RoundParts / 2, PartVT, HalfVT, V);
141 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
142 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
145 if (TLI.isBigEndian())
148 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
150 if (RoundParts < NumParts) {
151 // Assemble the trailing non-power-of-2 part.
152 unsigned OddParts = NumParts - RoundParts;
153 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
154 Hi = getCopyFromParts(DAG, DL,
155 Parts + RoundParts, OddParts, PartVT, OddVT, V);
157 // Combine the round and odd parts.
159 if (TLI.isBigEndian())
161 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
162 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
163 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
164 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
165 TLI.getPointerTy()));
166 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
167 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
169 } else if (PartVT.isFloatingPoint()) {
170 // FP split into multiple FP parts (for ppcf128)
171 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
174 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
175 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
176 if (TLI.hasBigEndianPartOrdering(ValueVT))
178 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
180 // FP split into integer parts (soft fp)
181 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
182 !PartVT.isVector() && "Unexpected split");
183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
188 // There is now one part, held in Val. Correct it to match ValueVT.
189 EVT PartEVT = Val.getValueType();
191 if (PartEVT == ValueVT)
194 if (PartEVT.isInteger() && ValueVT.isInteger()) {
195 if (ValueVT.bitsLT(PartEVT)) {
196 // For a truncate, see if we have any information to
197 // indicate whether the truncated bits will always be
198 // zero or sign-extension.
199 if (AssertOp != ISD::DELETED_NODE)
200 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
201 DAG.getValueType(ValueVT));
202 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
204 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
207 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
208 // FP_ROUND's are always exact here.
209 if (ValueVT.bitsLT(Val.getValueType()))
210 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
211 DAG.getTargetConstant(1, DL, TLI.getPointerTy()));
213 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
216 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
217 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
219 llvm_unreachable("Unknown mismatch!");
222 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
223 const Twine &ErrMsg) {
224 const Instruction *I = dyn_cast_or_null<Instruction>(V);
226 return Ctx.emitError(ErrMsg);
228 const char *AsmError = ", possible invalid constraint for vector type";
229 if (const CallInst *CI = dyn_cast<CallInst>(I))
230 if (isa<InlineAsm>(CI->getCalledValue()))
231 return Ctx.emitError(I, ErrMsg + AsmError);
233 return Ctx.emitError(I, ErrMsg);
236 /// getCopyFromPartsVector - Create a value that contains the specified legal
237 /// parts combined into the value they represent. If the parts combine to a
238 /// type larger then ValueVT then AssertOp can be used to specify whether the
239 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
240 /// ValueVT (ISD::AssertSext).
241 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
242 const SDValue *Parts, unsigned NumParts,
243 MVT PartVT, EVT ValueVT, const Value *V) {
244 assert(ValueVT.isVector() && "Not a vector value");
245 assert(NumParts > 0 && "No parts to assemble!");
246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
247 SDValue Val = Parts[0];
249 // Handle a multi-element vector.
253 unsigned NumIntermediates;
255 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
256 NumIntermediates, RegisterVT);
257 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
258 NumParts = NumRegs; // Silence a compiler warning.
259 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
260 assert(RegisterVT == Parts[0].getSimpleValueType() &&
261 "Part type doesn't match part!");
263 // Assemble the parts into intermediate operands.
264 SmallVector<SDValue, 8> Ops(NumIntermediates);
265 if (NumIntermediates == NumParts) {
266 // If the register was not expanded, truncate or copy the value,
268 for (unsigned i = 0; i != NumParts; ++i)
269 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
270 PartVT, IntermediateVT, V);
271 } else if (NumParts > 0) {
272 // If the intermediate type was expanded, build the intermediate
273 // operands from the parts.
274 assert(NumParts % NumIntermediates == 0 &&
275 "Must expand into a divisible number of parts!");
276 unsigned Factor = NumParts / NumIntermediates;
277 for (unsigned i = 0; i != NumIntermediates; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
279 PartVT, IntermediateVT, V);
282 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
283 // intermediate operands.
284 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
289 // There is now one part, held in Val. Correct it to match ValueVT.
290 EVT PartEVT = Val.getValueType();
292 if (PartEVT == ValueVT)
295 if (PartEVT.isVector()) {
296 // If the element type of the source/dest vectors are the same, but the
297 // parts vector has more elements than the value vector, then we have a
298 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
300 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
301 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
302 "Cannot narrow, it would be a lossy transformation");
303 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
304 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
307 // Vector/Vector bitcast.
308 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
309 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
311 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
312 "Cannot handle this kind of promotion");
313 // Promoted vector extract
314 bool Smaller = ValueVT.bitsLE(PartEVT);
315 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
320 // Trivial bitcast if the types are the same size and the destination
321 // vector type is legal.
322 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
323 TLI.isTypeLegal(ValueVT))
324 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
326 // Handle cases such as i8 -> <1 x i1>
327 if (ValueVT.getVectorNumElements() != 1) {
328 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
329 "non-trivial scalar-to-vector conversion");
330 return DAG.getUNDEF(ValueVT);
333 if (ValueVT.getVectorNumElements() == 1 &&
334 ValueVT.getVectorElementType() != PartEVT) {
335 bool Smaller = ValueVT.bitsLE(PartEVT);
336 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
337 DL, ValueVT.getScalarType(), Val);
340 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
343 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
344 SDValue Val, SDValue *Parts, unsigned NumParts,
345 MVT PartVT, const Value *V);
347 /// getCopyToParts - Create a series of nodes that contain the specified value
348 /// split into legal parts. If the parts contain more bits than Val, then, for
349 /// integers, ExtendKind can be used to specify how to generate the extra bits.
350 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
351 SDValue Val, SDValue *Parts, unsigned NumParts,
352 MVT PartVT, const Value *V,
353 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
354 EVT ValueVT = Val.getValueType();
356 // Handle the vector case separately.
357 if (ValueVT.isVector())
358 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
361 unsigned PartBits = PartVT.getSizeInBits();
362 unsigned OrigNumParts = NumParts;
363 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
368 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
369 EVT PartEVT = PartVT;
370 if (PartEVT == ValueVT) {
371 assert(NumParts == 1 && "No-op copy with multiple parts!");
376 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
377 // If the parts cover more bits than the value has, promote the value.
378 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
379 assert(NumParts == 1 && "Do not know what to promote to!");
380 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
382 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
383 ValueVT.isInteger() &&
384 "Unknown mismatch!");
385 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
386 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
387 if (PartVT == MVT::x86mmx)
388 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (PartBits == ValueVT.getSizeInBits()) {
391 // Different types of the same size.
392 assert(NumParts == 1 && PartEVT != ValueVT);
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
395 // If the parts cover less bits than value has, truncate the value.
396 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
397 ValueVT.isInteger() &&
398 "Unknown mismatch!");
399 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
400 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
401 if (PartVT == MVT::x86mmx)
402 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
405 // The value may have changed - recompute ValueVT.
406 ValueVT = Val.getValueType();
407 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
408 "Failed to tile the value with PartVT!");
411 if (PartEVT != ValueVT)
412 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
413 "scalar-to-vector conversion failed");
419 // Expand the value into multiple parts.
420 if (NumParts & (NumParts - 1)) {
421 // The number of parts is not a power of 2. Split off and copy the tail.
422 assert(PartVT.isInteger() && ValueVT.isInteger() &&
423 "Do not know what to expand to!");
424 unsigned RoundParts = 1 << Log2_32(NumParts);
425 unsigned RoundBits = RoundParts * PartBits;
426 unsigned OddParts = NumParts - RoundParts;
427 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
428 DAG.getIntPtrConstant(RoundBits, DL));
429 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
431 if (TLI.isBigEndian())
432 // The odd parts were reversed by getCopyToParts - unreverse them.
433 std::reverse(Parts + RoundParts, Parts + NumParts);
435 NumParts = RoundParts;
436 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
437 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
440 // The number of parts is a power of 2. Repeatedly bisect the value using
442 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
443 EVT::getIntegerVT(*DAG.getContext(),
444 ValueVT.getSizeInBits()),
447 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
448 for (unsigned i = 0; i < NumParts; i += StepSize) {
449 unsigned ThisBits = StepSize * PartBits / 2;
450 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
451 SDValue &Part0 = Parts[i];
452 SDValue &Part1 = Parts[i+StepSize/2];
454 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
455 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
456 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
457 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
459 if (ThisBits == PartBits && ThisVT != PartVT) {
460 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
461 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
466 if (TLI.isBigEndian())
467 std::reverse(Parts, Parts + OrigNumParts);
471 /// getCopyToPartsVector - Create a series of nodes that contain the specified
472 /// value split into legal parts.
473 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
474 SDValue Val, SDValue *Parts, unsigned NumParts,
475 MVT PartVT, const Value *V) {
476 EVT ValueVT = Val.getValueType();
477 assert(ValueVT.isVector() && "Not a vector");
478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
481 EVT PartEVT = PartVT;
482 if (PartEVT == ValueVT) {
484 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
485 // Bitconvert vector->vector case.
486 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
487 } else if (PartVT.isVector() &&
488 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
489 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
490 EVT ElementVT = PartVT.getVectorElementType();
491 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
493 SmallVector<SDValue, 16> Ops;
494 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
495 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
496 ElementVT, Val, DAG.getConstant(i, DL,
497 TLI.getVectorIdxTy())));
499 for (unsigned i = ValueVT.getVectorNumElements(),
500 e = PartVT.getVectorNumElements(); i != e; ++i)
501 Ops.push_back(DAG.getUNDEF(ElementVT));
503 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
505 // FIXME: Use CONCAT for 2x -> 4x.
507 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
508 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
509 } else if (PartVT.isVector() &&
510 PartEVT.getVectorElementType().bitsGE(
511 ValueVT.getVectorElementType()) &&
512 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
514 // Promoted vector extract
515 bool Smaller = PartEVT.bitsLE(ValueVT);
516 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
519 // Vector -> scalar conversion.
520 assert(ValueVT.getVectorNumElements() == 1 &&
521 "Only trivial vector-to-scalar conversions should get here!");
522 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
526 bool Smaller = ValueVT.bitsLE(PartVT);
527 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
552 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy()));
557 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &tli,
587 unsigned Reg, Type *Ty) {
588 ComputeValueVTs(tli, Ty, ValueVTs);
590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
591 EVT ValueVT = ValueVTs[Value];
592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
593 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
602 /// this value and returns the result as a ValueVT value. This uses
603 /// Chain/Flag as the input and updates them for the output Chain/Flag.
604 /// If the Flag pointer is NULL, no flag is used.
605 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
606 FunctionLoweringInfo &FuncInfo,
608 SDValue &Chain, SDValue *Flag,
609 const Value *V) const {
610 // A Value with type {} or [0 x %t] needs no registers.
611 if (ValueVTs.empty())
614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
616 // Assemble the legal parts into the final values.
617 SmallVector<SDValue, 4> Values(ValueVTs.size());
618 SmallVector<SDValue, 8> Parts;
619 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 // Copy the legal parts from the registers.
621 EVT ValueVT = ValueVTs[Value];
622 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
623 MVT RegisterVT = RegVTs[Value];
625 Parts.resize(NumRegs);
626 for (unsigned i = 0; i != NumRegs; ++i) {
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
631 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
632 *Flag = P.getValue(2);
635 Chain = P.getValue(1);
638 // If the source register was virtual and if we know something about it,
639 // add an assert node.
640 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
641 !RegisterVT.isInteger() || RegisterVT.isVector())
644 const FunctionLoweringInfo::LiveOutInfo *LOI =
645 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
649 unsigned RegSize = RegisterVT.getSizeInBits();
650 unsigned NumSignBits = LOI->NumSignBits;
651 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
653 if (NumZeroBits == RegSize) {
654 // The current value is a zero.
655 // Explicitly express that as it would be easier for
656 // optimizations to kick in.
657 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
661 // FIXME: We capture more information than the dag can represent. For
662 // now, just use the tightest assertzext/assertsext possible.
664 EVT FromVT(MVT::Other);
665 if (NumSignBits == RegSize)
666 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
667 else if (NumZeroBits >= RegSize-1)
668 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
669 else if (NumSignBits > RegSize-8)
670 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
671 else if (NumZeroBits >= RegSize-8)
672 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
673 else if (NumSignBits > RegSize-16)
674 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
675 else if (NumZeroBits >= RegSize-16)
676 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
677 else if (NumSignBits > RegSize-32)
678 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
679 else if (NumZeroBits >= RegSize-32)
680 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
684 // Add an assertion node.
685 assert(FromVT != MVT::Other);
686 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
687 RegisterVT, P, DAG.getValueType(FromVT));
690 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
691 NumRegs, RegisterVT, ValueVT, V);
696 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
699 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
700 /// specified value into the registers specified by this object. This uses
701 /// Chain/Flag as the input and updates them for the output Chain/Flag.
702 /// If the Flag pointer is NULL, no flag is used.
703 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
704 SDValue &Chain, SDValue *Flag, const Value *V,
705 ISD::NodeType PreferredExtendType) const {
706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
707 ISD::NodeType ExtendKind = PreferredExtendType;
709 // Get the list of the values's legal parts.
710 unsigned NumRegs = Regs.size();
711 SmallVector<SDValue, 8> Parts(NumRegs);
712 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
713 EVT ValueVT = ValueVTs[Value];
714 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
715 MVT RegisterVT = RegVTs[Value];
717 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
718 ExtendKind = ISD::ZERO_EXTEND;
720 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
721 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
725 // Copy the parts into the registers.
726 SmallVector<SDValue, 8> Chains(NumRegs);
727 for (unsigned i = 0; i != NumRegs; ++i) {
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
732 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
733 *Flag = Part.getValue(1);
736 Chains[i] = Part.getValue(0);
739 if (NumRegs == 1 || Flag)
740 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
741 // flagged to it. That is the CopyToReg nodes and the user are considered
742 // a single scheduling unit. If we create a TokenFactor and return it as
743 // chain, then the TokenFactor is both a predecessor (operand) of the
744 // user as well as a successor (the TF operands are flagged to the user).
745 // c1, f1 = CopyToReg
746 // c2, f2 = CopyToReg
747 // c3 = TokenFactor c1, c2
750 Chain = Chains[NumRegs-1];
752 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
755 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
756 /// operand list. This adds the code marker and includes the number of
757 /// values added into it.
758 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
759 unsigned MatchingIdx, SDLoc dl,
761 std::vector<SDValue> &Ops) const {
762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
764 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
766 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
767 else if (!Regs.empty() &&
768 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
769 // Put the register class of the virtual registers in the flag word. That
770 // way, later passes can recompute register class constraints for inline
771 // assembly as well as normal instructions.
772 // Don't do this for tied operands that can use the regclass information
774 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
775 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
776 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
779 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
782 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
783 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
784 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
785 MVT RegisterVT = RegVTs[Value];
786 for (unsigned i = 0; i != NumRegs; ++i) {
787 assert(Reg < Regs.size() && "Mismatch in # registers expected");
788 unsigned TheReg = Regs[Reg++];
789 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
791 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
792 // If we clobbered the stack pointer, MFI should know about it.
793 assert(DAG.getMachineFunction().getFrameInfo()->
794 hasInlineAsmWithSPAdjust());
800 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
801 const TargetLibraryInfo *li) {
805 DL = DAG.getTarget().getDataLayout();
806 Context = DAG.getContext();
807 LPadToCallSiteMap.clear();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
823 SDNodeOrder = LowestSDNodeOrder;
824 StatepointLowering.clear();
827 /// clearDanglingDebugInfo - Clear the dangling debug information
828 /// map. This function is separated from the clear so that debug
829 /// information that is dangling in a basic block can be properly
830 /// resolved in a different basic block. This allows the
831 /// SelectionDAG to resolve dangling debug information attached
833 void SelectionDAGBuilder::clearDanglingDebugInfo() {
834 DanglingDebugInfoMap.clear();
837 /// getRoot - Return the current virtual root of the Selection DAG,
838 /// flushing any PendingLoad items. This must be done before emitting
839 /// a store or any other node that may need to be ordered after any
840 /// prior load instructions.
842 SDValue SelectionDAGBuilder::getRoot() {
843 if (PendingLoads.empty())
844 return DAG.getRoot();
846 if (PendingLoads.size() == 1) {
847 SDValue Root = PendingLoads[0];
849 PendingLoads.clear();
853 // Otherwise, we have to make a token factor node.
854 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
856 PendingLoads.clear();
861 /// getControlRoot - Similar to getRoot, but instead of flushing all the
862 /// PendingLoad items, flush all the PendingExports items. It is necessary
863 /// to do this before emitting a terminator instruction.
865 SDValue SelectionDAGBuilder::getControlRoot() {
866 SDValue Root = DAG.getRoot();
868 if (PendingExports.empty())
871 // Turn all of the CopyToReg chains into one factored node.
872 if (Root.getOpcode() != ISD::EntryToken) {
873 unsigned i = 0, e = PendingExports.size();
874 for (; i != e; ++i) {
875 assert(PendingExports[i].getNode()->getNumOperands() > 1);
876 if (PendingExports[i].getNode()->getOperand(0) == Root)
877 break; // Don't add the root if we already indirectly depend on it.
881 PendingExports.push_back(Root);
884 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
886 PendingExports.clear();
891 void SelectionDAGBuilder::visit(const Instruction &I) {
892 // Set up outgoing PHI node register values before emitting the terminator.
893 if (isa<TerminatorInst>(&I))
894 HandlePHINodesInSuccessorBlocks(I.getParent());
900 visit(I.getOpcode(), I);
902 if (!isa<TerminatorInst>(&I) && !HasTailCall)
903 CopyToExportRegsIfNeeded(&I);
908 void SelectionDAGBuilder::visitPHI(const PHINode &) {
909 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
912 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
913 // Note: this doesn't use InstVisitor, because it has to work with
914 // ConstantExpr's in addition to instructions.
916 default: llvm_unreachable("Unknown instruction type encountered!");
917 // Build the switch statement using the Instruction.def file.
918 #define HANDLE_INST(NUM, OPCODE, CLASS) \
919 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
920 #include "llvm/IR/Instruction.def"
924 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
925 // generate the debug data structures now that we've seen its definition.
926 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
928 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
930 const DbgValueInst *DI = DDI.getDI();
931 DebugLoc dl = DDI.getdl();
932 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
933 DILocalVariable *Variable = DI->getVariable();
934 DIExpression *Expr = DI->getExpression();
935 assert(Variable->isValidLocationForIntrinsic(dl) &&
936 "Expected inlined-at fields to agree");
937 uint64_t Offset = DI->getOffset();
938 // A dbg.value for an alloca is always indirect.
939 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
942 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
944 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
945 IsIndirect, Offset, dl, DbgSDNodeOrder);
946 DAG.AddDbgValue(SDV, Val.getNode(), false);
949 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
950 DanglingDebugInfoMap[V] = DanglingDebugInfo();
954 /// getCopyFromRegs - If there was virtual register allocated for the value V
955 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
956 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
957 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
960 if (It != FuncInfo.ValueMap.end()) {
961 unsigned InReg = It->second;
962 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
964 SDValue Chain = DAG.getEntryNode();
965 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
966 resolveDanglingDebugInfo(V, Result);
972 /// getValue - Return an SDValue for the given Value.
973 SDValue SelectionDAGBuilder::getValue(const Value *V) {
974 // If we already have an SDValue for this value, use it. It's important
975 // to do this first, so that we don't create a CopyFromReg if we already
976 // have a regular SDValue.
977 SDValue &N = NodeMap[V];
978 if (N.getNode()) return N;
980 // If there's a virtual register allocated and initialized for this
982 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
983 if (copyFromReg.getNode()) {
987 // Otherwise create a new SDValue and remember it.
988 SDValue Val = getValueImpl(V);
990 resolveDanglingDebugInfo(V, Val);
994 // Return true if SDValue exists for the given Value
995 bool SelectionDAGBuilder::findValue(const Value *V) const {
996 return (NodeMap.find(V) != NodeMap.end()) ||
997 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1000 /// getNonRegisterValue - Return an SDValue for the given Value, but
1001 /// don't look in FuncInfo.ValueMap for a virtual register.
1002 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1003 // If we already have an SDValue for this value, use it.
1004 SDValue &N = NodeMap[V];
1005 if (N.getNode()) return N;
1007 // Otherwise create a new SDValue and remember it.
1008 SDValue Val = getValueImpl(V);
1010 resolveDanglingDebugInfo(V, Val);
1014 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1015 /// Create an SDValue for the given value.
1016 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1017 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1019 if (const Constant *C = dyn_cast<Constant>(V)) {
1020 EVT VT = TLI.getValueType(V->getType(), true);
1022 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1023 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1025 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1026 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1028 if (isa<ConstantPointerNull>(C)) {
1029 unsigned AS = V->getType()->getPointerAddressSpace();
1030 return DAG.getConstant(0, getCurSDLoc(), TLI.getPointerTy(AS));
1033 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1034 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1036 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1037 return DAG.getUNDEF(VT);
1039 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1040 visit(CE->getOpcode(), *CE);
1041 SDValue N1 = NodeMap[V];
1042 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1046 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1047 SmallVector<SDValue, 4> Constants;
1048 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1050 SDNode *Val = getValue(*OI).getNode();
1051 // If the operand is an empty aggregate, there are no values.
1053 // Add each leaf value from the operand to the Constants list
1054 // to form a flattened list of all the values.
1055 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1056 Constants.push_back(SDValue(Val, i));
1059 return DAG.getMergeValues(Constants, getCurSDLoc());
1062 if (const ConstantDataSequential *CDS =
1063 dyn_cast<ConstantDataSequential>(C)) {
1064 SmallVector<SDValue, 4> Ops;
1065 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1066 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1067 // Add each leaf value from the operand to the Constants list
1068 // to form a flattened list of all the values.
1069 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1070 Ops.push_back(SDValue(Val, i));
1073 if (isa<ArrayType>(CDS->getType()))
1074 return DAG.getMergeValues(Ops, getCurSDLoc());
1075 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1079 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1080 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1081 "Unknown struct or array constant!");
1083 SmallVector<EVT, 4> ValueVTs;
1084 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1085 unsigned NumElts = ValueVTs.size();
1087 return SDValue(); // empty struct
1088 SmallVector<SDValue, 4> Constants(NumElts);
1089 for (unsigned i = 0; i != NumElts; ++i) {
1090 EVT EltVT = ValueVTs[i];
1091 if (isa<UndefValue>(C))
1092 Constants[i] = DAG.getUNDEF(EltVT);
1093 else if (EltVT.isFloatingPoint())
1094 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1096 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1099 return DAG.getMergeValues(Constants, getCurSDLoc());
1102 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1103 return DAG.getBlockAddress(BA, VT);
1105 VectorType *VecTy = cast<VectorType>(V->getType());
1106 unsigned NumElements = VecTy->getNumElements();
1108 // Now that we know the number and type of the elements, get that number of
1109 // elements into the Ops array based on what kind of constant it is.
1110 SmallVector<SDValue, 16> Ops;
1111 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1112 for (unsigned i = 0; i != NumElements; ++i)
1113 Ops.push_back(getValue(CV->getOperand(i)));
1115 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1116 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1119 if (EltVT.isFloatingPoint())
1120 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1122 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1123 Ops.assign(NumElements, Op);
1126 // Create a BUILD_VECTOR node.
1127 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1130 // If this is a static alloca, generate it as the frameindex instead of
1132 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1133 DenseMap<const AllocaInst*, int>::iterator SI =
1134 FuncInfo.StaticAllocaMap.find(AI);
1135 if (SI != FuncInfo.StaticAllocaMap.end())
1136 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1139 // If this is an instruction which fast-isel has deferred, select it now.
1140 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1141 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1142 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1143 SDValue Chain = DAG.getEntryNode();
1144 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1147 llvm_unreachable("Can't get register for value!");
1150 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1151 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1152 SDValue Chain = getControlRoot();
1153 SmallVector<ISD::OutputArg, 8> Outs;
1154 SmallVector<SDValue, 8> OutVals;
1156 if (!FuncInfo.CanLowerReturn) {
1157 unsigned DemoteReg = FuncInfo.DemoteRegister;
1158 const Function *F = I.getParent()->getParent();
1160 // Emit a store of the return value through the virtual register.
1161 // Leave Outs empty so that LowerReturn won't try to load return
1162 // registers the usual way.
1163 SmallVector<EVT, 1> PtrValueVTs;
1164 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1167 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1168 SDValue RetOp = getValue(I.getOperand(0));
1170 SmallVector<EVT, 4> ValueVTs;
1171 SmallVector<uint64_t, 4> Offsets;
1172 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1173 unsigned NumValues = ValueVTs.size();
1175 SmallVector<SDValue, 4> Chains(NumValues);
1176 for (unsigned i = 0; i != NumValues; ++i) {
1177 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1178 RetPtr.getValueType(), RetPtr,
1179 DAG.getIntPtrConstant(Offsets[i],
1182 DAG.getStore(Chain, getCurSDLoc(),
1183 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1184 // FIXME: better loc info would be nice.
1185 Add, MachinePointerInfo(), false, false, 0);
1188 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1189 MVT::Other, Chains);
1190 } else if (I.getNumOperands() != 0) {
1191 SmallVector<EVT, 4> ValueVTs;
1192 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1193 unsigned NumValues = ValueVTs.size();
1195 SDValue RetOp = getValue(I.getOperand(0));
1197 const Function *F = I.getParent()->getParent();
1199 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1200 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1202 ExtendKind = ISD::SIGN_EXTEND;
1203 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1205 ExtendKind = ISD::ZERO_EXTEND;
1207 LLVMContext &Context = F->getContext();
1208 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1211 for (unsigned j = 0; j != NumValues; ++j) {
1212 EVT VT = ValueVTs[j];
1214 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1215 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1217 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1218 MVT PartVT = TLI.getRegisterType(Context, VT);
1219 SmallVector<SDValue, 4> Parts(NumParts);
1220 getCopyToParts(DAG, getCurSDLoc(),
1221 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1222 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1224 // 'inreg' on function refers to return value
1225 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1229 // Propagate extension type if any
1230 if (ExtendKind == ISD::SIGN_EXTEND)
1232 else if (ExtendKind == ISD::ZERO_EXTEND)
1235 for (unsigned i = 0; i < NumParts; ++i) {
1236 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1237 VT, /*isfixed=*/true, 0, 0));
1238 OutVals.push_back(Parts[i]);
1244 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1245 CallingConv::ID CallConv =
1246 DAG.getMachineFunction().getFunction()->getCallingConv();
1247 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1248 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1250 // Verify that the target's LowerReturn behaved as expected.
1251 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1252 "LowerReturn didn't return a valid chain!");
1254 // Update the DAG with the new chain value resulting from return lowering.
1258 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1259 /// created for it, emit nodes to copy the value into the virtual
1261 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1263 if (V->getType()->isEmptyTy())
1266 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1267 if (VMI != FuncInfo.ValueMap.end()) {
1268 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1269 CopyValueToVirtualRegister(V, VMI->second);
1273 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1274 /// the current basic block, add it to ValueMap now so that we'll get a
1276 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1277 // No need to export constants.
1278 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1280 // Already exported?
1281 if (FuncInfo.isExportedInst(V)) return;
1283 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1284 CopyValueToVirtualRegister(V, Reg);
1287 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1288 const BasicBlock *FromBB) {
1289 // The operands of the setcc have to be in this block. We don't know
1290 // how to export them from some other block.
1291 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1292 // Can export from current BB.
1293 if (VI->getParent() == FromBB)
1296 // Is already exported, noop.
1297 return FuncInfo.isExportedInst(V);
1300 // If this is an argument, we can export it if the BB is the entry block or
1301 // if it is already exported.
1302 if (isa<Argument>(V)) {
1303 if (FromBB == &FromBB->getParent()->getEntryBlock())
1306 // Otherwise, can only export this if it is already exported.
1307 return FuncInfo.isExportedInst(V);
1310 // Otherwise, constants can always be exported.
1314 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1315 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1316 const MachineBasicBlock *Dst) const {
1317 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1320 const BasicBlock *SrcBB = Src->getBasicBlock();
1321 const BasicBlock *DstBB = Dst->getBasicBlock();
1322 return BPI->getEdgeWeight(SrcBB, DstBB);
1325 void SelectionDAGBuilder::
1326 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1327 uint32_t Weight /* = 0 */) {
1329 Weight = getEdgeWeight(Src, Dst);
1330 Src->addSuccessor(Dst, Weight);
1334 static bool InBlock(const Value *V, const BasicBlock *BB) {
1335 if (const Instruction *I = dyn_cast<Instruction>(V))
1336 return I->getParent() == BB;
1340 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1341 /// This function emits a branch and is used at the leaves of an OR or an
1342 /// AND operator tree.
1345 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1346 MachineBasicBlock *TBB,
1347 MachineBasicBlock *FBB,
1348 MachineBasicBlock *CurBB,
1349 MachineBasicBlock *SwitchBB,
1352 const BasicBlock *BB = CurBB->getBasicBlock();
1354 // If the leaf of the tree is a comparison, merge the condition into
1356 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1357 // The operands of the cmp have to be in this block. We don't know
1358 // how to export them from some other block. If this is the first block
1359 // of the sequence, no exporting is needed.
1360 if (CurBB == SwitchBB ||
1361 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1362 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1363 ISD::CondCode Condition;
1364 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1365 Condition = getICmpCondCode(IC->getPredicate());
1366 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1367 Condition = getFCmpCondCode(FC->getPredicate());
1368 if (TM.Options.NoNaNsFPMath)
1369 Condition = getFCmpCodeWithoutNaN(Condition);
1371 (void)Condition; // silence warning.
1372 llvm_unreachable("Unknown compare instruction");
1375 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1376 TBB, FBB, CurBB, TWeight, FWeight);
1377 SwitchCases.push_back(CB);
1382 // Create a CaseBlock record representing this branch.
1383 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1384 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1385 SwitchCases.push_back(CB);
1388 /// Scale down both weights to fit into uint32_t.
1389 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1390 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1391 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1392 NewTrue = NewTrue / Scale;
1393 NewFalse = NewFalse / Scale;
1396 /// FindMergedConditions - If Cond is an expression like
1397 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1398 MachineBasicBlock *TBB,
1399 MachineBasicBlock *FBB,
1400 MachineBasicBlock *CurBB,
1401 MachineBasicBlock *SwitchBB,
1402 unsigned Opc, uint32_t TWeight,
1404 // If this node is not part of the or/and tree, emit it as a branch.
1405 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1406 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1407 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1408 BOp->getParent() != CurBB->getBasicBlock() ||
1409 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1410 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1411 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1416 // Create TmpBB after CurBB.
1417 MachineFunction::iterator BBI = CurBB;
1418 MachineFunction &MF = DAG.getMachineFunction();
1419 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1420 CurBB->getParent()->insert(++BBI, TmpBB);
1422 if (Opc == Instruction::Or) {
1423 // Codegen X | Y as:
1432 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1433 // The requirement is that
1434 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1435 // = TrueProb for orignal BB.
1436 // Assuming the orignal weights are A and B, one choice is to set BB1's
1437 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1439 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1440 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1441 // TmpBB, but the math is more complicated.
1443 uint64_t NewTrueWeight = TWeight;
1444 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1445 ScaleWeights(NewTrueWeight, NewFalseWeight);
1446 // Emit the LHS condition.
1447 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1448 NewTrueWeight, NewFalseWeight);
1450 NewTrueWeight = TWeight;
1451 NewFalseWeight = 2 * (uint64_t)FWeight;
1452 ScaleWeights(NewTrueWeight, NewFalseWeight);
1453 // Emit the RHS condition into TmpBB.
1454 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1455 NewTrueWeight, NewFalseWeight);
1457 assert(Opc == Instruction::And && "Unknown merge op!");
1458 // Codegen X & Y as:
1466 // This requires creation of TmpBB after CurBB.
1468 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1469 // The requirement is that
1470 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1471 // = FalseProb for orignal BB.
1472 // Assuming the orignal weights are A and B, one choice is to set BB1's
1473 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1475 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1477 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1478 uint64_t NewFalseWeight = FWeight;
1479 ScaleWeights(NewTrueWeight, NewFalseWeight);
1480 // Emit the LHS condition.
1481 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1482 NewTrueWeight, NewFalseWeight);
1484 NewTrueWeight = 2 * (uint64_t)TWeight;
1485 NewFalseWeight = FWeight;
1486 ScaleWeights(NewTrueWeight, NewFalseWeight);
1487 // Emit the RHS condition into TmpBB.
1488 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1489 NewTrueWeight, NewFalseWeight);
1493 /// If the set of cases should be emitted as a series of branches, return true.
1494 /// If we should emit this as a bunch of and/or'd together conditions, return
1497 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1498 if (Cases.size() != 2) return true;
1500 // If this is two comparisons of the same values or'd or and'd together, they
1501 // will get folded into a single comparison, so don't emit two blocks.
1502 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1503 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1504 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1505 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1509 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1510 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1511 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1512 Cases[0].CC == Cases[1].CC &&
1513 isa<Constant>(Cases[0].CmpRHS) &&
1514 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1515 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1517 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1524 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1525 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1527 // Update machine-CFG edges.
1528 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1530 if (I.isUnconditional()) {
1531 // Update machine-CFG edges.
1532 BrMBB->addSuccessor(Succ0MBB);
1534 // If this is not a fall-through branch or optimizations are switched off,
1536 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1537 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1538 MVT::Other, getControlRoot(),
1539 DAG.getBasicBlock(Succ0MBB)));
1544 // If this condition is one of the special cases we handle, do special stuff
1546 const Value *CondVal = I.getCondition();
1547 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1549 // If this is a series of conditions that are or'd or and'd together, emit
1550 // this as a sequence of branches instead of setcc's with and/or operations.
1551 // As long as jumps are not expensive, this should improve performance.
1552 // For example, instead of something like:
1565 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1566 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1567 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1568 BOp->getOpcode() == Instruction::Or)) {
1569 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1570 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1571 getEdgeWeight(BrMBB, Succ1MBB));
1572 // If the compares in later blocks need to use values not currently
1573 // exported from this block, export them now. This block should always
1574 // be the first entry.
1575 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1577 // Allow some cases to be rejected.
1578 if (ShouldEmitAsBranches(SwitchCases)) {
1579 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1580 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1581 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1584 // Emit the branch for this block.
1585 visitSwitchCase(SwitchCases[0], BrMBB);
1586 SwitchCases.erase(SwitchCases.begin());
1590 // Okay, we decided not to do this, remove any inserted MBB's and clear
1592 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1593 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1595 SwitchCases.clear();
1599 // Create a CaseBlock record representing this branch.
1600 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1601 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1603 // Use visitSwitchCase to actually insert the fast branch sequence for this
1605 visitSwitchCase(CB, BrMBB);
1608 /// visitSwitchCase - Emits the necessary code to represent a single node in
1609 /// the binary search tree resulting from lowering a switch instruction.
1610 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1611 MachineBasicBlock *SwitchBB) {
1613 SDValue CondLHS = getValue(CB.CmpLHS);
1614 SDLoc dl = getCurSDLoc();
1616 // Build the setcc now.
1618 // Fold "(X == true)" to X and "(X == false)" to !X to
1619 // handle common cases produced by branch lowering.
1620 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1621 CB.CC == ISD::SETEQ)
1623 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1624 CB.CC == ISD::SETEQ) {
1625 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1626 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1628 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1630 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1632 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1633 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1635 SDValue CmpOp = getValue(CB.CmpMHS);
1636 EVT VT = CmpOp.getValueType();
1638 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1639 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1642 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1643 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1644 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1645 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1649 // Update successor info
1650 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1651 // TrueBB and FalseBB are always different unless the incoming IR is
1652 // degenerate. This only happens when running llc on weird IR.
1653 if (CB.TrueBB != CB.FalseBB)
1654 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1656 // If the lhs block is the next block, invert the condition so that we can
1657 // fall through to the lhs instead of the rhs block.
1658 if (CB.TrueBB == NextBlock(SwitchBB)) {
1659 std::swap(CB.TrueBB, CB.FalseBB);
1660 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1661 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1664 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1665 MVT::Other, getControlRoot(), Cond,
1666 DAG.getBasicBlock(CB.TrueBB));
1668 // Insert the false branch. Do this even if it's a fall through branch,
1669 // this makes it easier to do DAG optimizations which require inverting
1670 // the branch condition.
1671 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1672 DAG.getBasicBlock(CB.FalseBB));
1674 DAG.setRoot(BrCond);
1677 /// visitJumpTable - Emit JumpTable node in the current MBB
1678 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1679 // Emit the code for the jump table
1680 assert(JT.Reg != -1U && "Should lower JT Header first!");
1681 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1682 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1684 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1685 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1686 MVT::Other, Index.getValue(1),
1688 DAG.setRoot(BrJumpTable);
1691 /// visitJumpTableHeader - This function emits necessary code to produce index
1692 /// in the JumpTable from switch case.
1693 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1694 JumpTableHeader &JTH,
1695 MachineBasicBlock *SwitchBB) {
1696 SDLoc dl = getCurSDLoc();
1698 // Subtract the lowest switch case value from the value being switched on and
1699 // conditional branch to default mbb if the result is greater than the
1700 // difference between smallest and largest cases.
1701 SDValue SwitchOp = getValue(JTH.SValue);
1702 EVT VT = SwitchOp.getValueType();
1703 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1704 DAG.getConstant(JTH.First, dl, VT));
1706 // The SDNode we just created, which holds the value being switched on minus
1707 // the smallest case value, needs to be copied to a virtual register so it
1708 // can be used as an index into the jump table in a subsequent basic block.
1709 // This value may be smaller or larger than the target's pointer type, and
1710 // therefore require extension or truncating.
1711 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1712 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy());
1714 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1715 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1716 JumpTableReg, SwitchOp);
1717 JT.Reg = JumpTableReg;
1719 // Emit the range check for the jump table, and branch to the default block
1720 // for the switch statement if the value being switched on exceeds the largest
1721 // case in the switch.
1723 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1724 Sub.getValueType()),
1725 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT),
1728 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1729 MVT::Other, CopyTo, CMP,
1730 DAG.getBasicBlock(JT.Default));
1732 // Avoid emitting unnecessary branches to the next block.
1733 if (JT.MBB != NextBlock(SwitchBB))
1734 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1735 DAG.getBasicBlock(JT.MBB));
1737 DAG.setRoot(BrCond);
1740 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1741 /// tail spliced into a stack protector check success bb.
1743 /// For a high level explanation of how this fits into the stack protector
1744 /// generation see the comment on the declaration of class
1745 /// StackProtectorDescriptor.
1746 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1747 MachineBasicBlock *ParentBB) {
1749 // First create the loads to the guard/stack slot for the comparison.
1750 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1751 EVT PtrTy = TLI.getPointerTy();
1753 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1754 int FI = MFI->getStackProtectorIndex();
1756 const Value *IRGuard = SPD.getGuard();
1757 SDValue GuardPtr = getValue(IRGuard);
1758 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1761 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1764 SDLoc dl = getCurSDLoc();
1766 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1767 // guard value from the virtual register holding the value. Otherwise, emit a
1768 // volatile load to retrieve the stack guard value.
1769 unsigned GuardReg = SPD.getGuardReg();
1771 if (GuardReg && TLI.useLoadStackGuardNode())
1772 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1775 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1776 GuardPtr, MachinePointerInfo(IRGuard, 0),
1777 true, false, false, Align);
1779 SDValue StackSlot = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1781 MachinePointerInfo::getFixedStack(FI),
1782 true, false, false, Align);
1784 // Perform the comparison via a subtract/getsetcc.
1785 EVT VT = Guard.getValueType();
1786 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1789 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1790 Sub.getValueType()),
1791 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1793 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1794 // branch to failure MBB.
1795 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1796 MVT::Other, StackSlot.getOperand(0),
1797 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1798 // Otherwise branch to success MBB.
1799 SDValue Br = DAG.getNode(ISD::BR, dl,
1801 DAG.getBasicBlock(SPD.getSuccessMBB()));
1806 /// Codegen the failure basic block for a stack protector check.
1808 /// A failure stack protector machine basic block consists simply of a call to
1809 /// __stack_chk_fail().
1811 /// For a high level explanation of how this fits into the stack protector
1812 /// generation see the comment on the declaration of class
1813 /// StackProtectorDescriptor.
1815 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1818 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1819 nullptr, 0, false, getCurSDLoc(), false, false).second;
1823 /// visitBitTestHeader - This function emits necessary code to produce value
1824 /// suitable for "bit tests"
1825 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1826 MachineBasicBlock *SwitchBB) {
1827 SDLoc dl = getCurSDLoc();
1829 // Subtract the minimum value
1830 SDValue SwitchOp = getValue(B.SValue);
1831 EVT VT = SwitchOp.getValueType();
1832 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1833 DAG.getConstant(B.First, dl, VT));
1836 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1838 DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(),
1839 Sub.getValueType()),
1840 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1842 // Determine the type of the test operands.
1843 bool UsePtrType = false;
1844 if (!TLI.isTypeLegal(VT))
1847 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1848 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1849 // Switch table case range are encoded into series of masks.
1850 // Just use pointer type, it's guaranteed to fit.
1856 VT = TLI.getPointerTy();
1857 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
1860 B.RegVT = VT.getSimpleVT();
1861 B.Reg = FuncInfo.CreateReg(B.RegVT);
1862 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
1864 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1866 addSuccessorWithWeight(SwitchBB, B.Default);
1867 addSuccessorWithWeight(SwitchBB, MBB);
1869 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
1870 MVT::Other, CopyTo, RangeCmp,
1871 DAG.getBasicBlock(B.Default));
1873 // Avoid emitting unnecessary branches to the next block.
1874 if (MBB != NextBlock(SwitchBB))
1875 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
1876 DAG.getBasicBlock(MBB));
1878 DAG.setRoot(BrRange);
1881 /// visitBitTestCase - this function produces one "bit test"
1882 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1883 MachineBasicBlock* NextMBB,
1884 uint32_t BranchWeightToNext,
1887 MachineBasicBlock *SwitchBB) {
1888 SDLoc dl = getCurSDLoc();
1890 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
1892 unsigned PopCount = countPopulation(B.Mask);
1893 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1894 if (PopCount == 1) {
1895 // Testing for a single bit; just compare the shift count with what it
1896 // would need to be to shift a 1 bit in that position.
1898 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1899 DAG.getConstant(countTrailingZeros(B.Mask), dl, VT), ISD::SETEQ);
1900 } else if (PopCount == BB.Range) {
1901 // There is only one zero bit in the range, test for it directly.
1903 dl, TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1904 DAG.getConstant(countTrailingOnes(B.Mask), dl, VT), ISD::SETNE);
1906 // Make desired shift
1907 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
1908 DAG.getConstant(1, dl, VT), ShiftOp);
1910 // Emit bit tests and jumps
1911 SDValue AndOp = DAG.getNode(ISD::AND, dl,
1912 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
1913 Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1914 DAG.getConstant(0, dl, VT), ISD::SETNE);
1917 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1918 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1919 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1920 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1922 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
1923 MVT::Other, getControlRoot(),
1924 Cmp, DAG.getBasicBlock(B.TargetBB));
1926 // Avoid emitting unnecessary branches to the next block.
1927 if (NextMBB != NextBlock(SwitchBB))
1928 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
1929 DAG.getBasicBlock(NextMBB));
1934 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1935 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1937 // Retrieve successors.
1938 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1939 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1941 const Value *Callee(I.getCalledValue());
1942 const Function *Fn = dyn_cast<Function>(Callee);
1943 if (isa<InlineAsm>(Callee))
1945 else if (Fn && Fn->isIntrinsic()) {
1946 switch (Fn->getIntrinsicID()) {
1948 llvm_unreachable("Cannot invoke this intrinsic");
1949 case Intrinsic::donothing:
1950 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
1952 case Intrinsic::experimental_patchpoint_void:
1953 case Intrinsic::experimental_patchpoint_i64:
1954 visitPatchpoint(&I, LandingPad);
1956 case Intrinsic::experimental_gc_statepoint:
1957 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
1961 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1963 // If the value of the invoke is used outside of its defining block, make it
1964 // available as a virtual register.
1965 // We already took care of the exported value for the statepoint instruction
1966 // during call to the LowerStatepoint.
1967 if (!isStatepoint(I)) {
1968 CopyToExportRegsIfNeeded(&I);
1971 // Update successor info
1972 addSuccessorWithWeight(InvokeMBB, Return);
1973 addSuccessorWithWeight(InvokeMBB, LandingPad);
1975 // Drop into normal successor.
1976 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1977 MVT::Other, getControlRoot(),
1978 DAG.getBasicBlock(Return)));
1981 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1982 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1985 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1986 assert(FuncInfo.MBB->isLandingPad() &&
1987 "Call to landingpad not in landing pad!");
1989 MachineBasicBlock *MBB = FuncInfo.MBB;
1990 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1991 AddLandingPadInfo(LP, MMI, MBB);
1993 // If there aren't registers to copy the values into (e.g., during SjLj
1994 // exceptions), then don't bother to create these DAG nodes.
1995 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1996 if (TLI.getExceptionPointerRegister() == 0 &&
1997 TLI.getExceptionSelectorRegister() == 0)
2000 SmallVector<EVT, 2> ValueVTs;
2001 SDLoc dl = getCurSDLoc();
2002 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2003 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2005 // Get the two live-in registers as SDValues. The physregs have already been
2006 // copied into virtual registers.
2008 if (FuncInfo.ExceptionPointerVirtReg) {
2009 Ops[0] = DAG.getZExtOrTrunc(
2010 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2011 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2014 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy());
2016 Ops[1] = DAG.getZExtOrTrunc(
2017 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2018 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2022 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2023 DAG.getVTList(ValueVTs), Ops);
2028 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2029 MachineBasicBlock *LPadBB) {
2030 SDValue Chain = getControlRoot();
2031 SDLoc dl = getCurSDLoc();
2033 // Get the typeid that we will dispatch on later.
2034 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2035 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2036 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2037 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2038 SDValue Sel = DAG.getConstant(TypeID, dl, TLI.getPointerTy());
2039 Chain = DAG.getCopyToReg(Chain, dl, VReg, Sel);
2041 // Branch to the main landing pad block.
2042 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2043 ClauseMBB->addSuccessor(LPadBB);
2044 DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, Chain,
2045 DAG.getBasicBlock(LPadBB)));
2049 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2051 for (const CaseCluster &CC : Clusters)
2052 assert(CC.Low == CC.High && "Input clusters must be single-case");
2055 std::sort(Clusters.begin(), Clusters.end(),
2056 [](const CaseCluster &a, const CaseCluster &b) {
2057 return a.Low->getValue().slt(b.Low->getValue());
2060 // Merge adjacent clusters with the same destination.
2061 const unsigned N = Clusters.size();
2062 unsigned DstIndex = 0;
2063 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2064 CaseCluster &CC = Clusters[SrcIndex];
2065 const ConstantInt *CaseVal = CC.Low;
2066 MachineBasicBlock *Succ = CC.MBB;
2068 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2069 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2070 // If this case has the same successor and is a neighbour, merge it into
2071 // the previous cluster.
2072 Clusters[DstIndex - 1].High = CaseVal;
2073 Clusters[DstIndex - 1].Weight += CC.Weight;
2074 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2076 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2077 sizeof(Clusters[SrcIndex]));
2080 Clusters.resize(DstIndex);
2083 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2084 MachineBasicBlock *Last) {
2086 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2087 if (JTCases[i].first.HeaderBB == First)
2088 JTCases[i].first.HeaderBB = Last;
2090 // Update BitTestCases.
2091 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2092 if (BitTestCases[i].Parent == First)
2093 BitTestCases[i].Parent = Last;
2096 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2097 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2099 // Update machine-CFG edges with unique successors.
2100 SmallSet<BasicBlock*, 32> Done;
2101 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2102 BasicBlock *BB = I.getSuccessor(i);
2103 bool Inserted = Done.insert(BB).second;
2107 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2108 addSuccessorWithWeight(IndirectBrMBB, Succ);
2111 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2112 MVT::Other, getControlRoot(),
2113 getValue(I.getAddress())));
2116 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2117 if (DAG.getTarget().Options.TrapUnreachable)
2118 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2121 void SelectionDAGBuilder::visitFSub(const User &I) {
2122 // -0.0 - X --> fneg
2123 Type *Ty = I.getType();
2124 if (isa<Constant>(I.getOperand(0)) &&
2125 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2126 SDValue Op2 = getValue(I.getOperand(1));
2127 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2128 Op2.getValueType(), Op2));
2132 visitBinary(I, ISD::FSUB);
2135 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2136 SDValue Op1 = getValue(I.getOperand(0));
2137 SDValue Op2 = getValue(I.getOperand(1));
2142 if (const OverflowingBinaryOperator *OFBinOp =
2143 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2144 nuw = OFBinOp->hasNoUnsignedWrap();
2145 nsw = OFBinOp->hasNoSignedWrap();
2147 if (const PossiblyExactOperator *ExactOp =
2148 dyn_cast<const PossiblyExactOperator>(&I))
2149 exact = ExactOp->isExact();
2151 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2152 Op1, Op2, nuw, nsw, exact);
2153 setValue(&I, BinNodeValue);
2156 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2157 SDValue Op1 = getValue(I.getOperand(0));
2158 SDValue Op2 = getValue(I.getOperand(1));
2161 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2163 // Coerce the shift amount to the right type if we can.
2164 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2165 unsigned ShiftSize = ShiftTy.getSizeInBits();
2166 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2167 SDLoc DL = getCurSDLoc();
2169 // If the operand is smaller than the shift count type, promote it.
2170 if (ShiftSize > Op2Size)
2171 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2173 // If the operand is larger than the shift count type but the shift
2174 // count type has enough bits to represent any shift value, truncate
2175 // it now. This is a common case and it exposes the truncate to
2176 // optimization early.
2177 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2178 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2179 // Otherwise we'll need to temporarily settle for some other convenient
2180 // type. Type legalization will make adjustments once the shiftee is split.
2182 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2189 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2191 if (const OverflowingBinaryOperator *OFBinOp =
2192 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2193 nuw = OFBinOp->hasNoUnsignedWrap();
2194 nsw = OFBinOp->hasNoSignedWrap();
2196 if (const PossiblyExactOperator *ExactOp =
2197 dyn_cast<const PossiblyExactOperator>(&I))
2198 exact = ExactOp->isExact();
2201 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2206 void SelectionDAGBuilder::visitSDiv(const User &I) {
2207 SDValue Op1 = getValue(I.getOperand(0));
2208 SDValue Op2 = getValue(I.getOperand(1));
2210 // Turn exact SDivs into multiplications.
2211 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2213 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2214 !isa<ConstantSDNode>(Op1) &&
2215 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2216 setValue(&I, DAG.getTargetLoweringInfo()
2217 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2219 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2223 void SelectionDAGBuilder::visitICmp(const User &I) {
2224 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2225 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2226 predicate = IC->getPredicate();
2227 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2228 predicate = ICmpInst::Predicate(IC->getPredicate());
2229 SDValue Op1 = getValue(I.getOperand(0));
2230 SDValue Op2 = getValue(I.getOperand(1));
2231 ISD::CondCode Opcode = getICmpCondCode(predicate);
2233 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2234 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2237 void SelectionDAGBuilder::visitFCmp(const User &I) {
2238 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2239 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2240 predicate = FC->getPredicate();
2241 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2242 predicate = FCmpInst::Predicate(FC->getPredicate());
2243 SDValue Op1 = getValue(I.getOperand(0));
2244 SDValue Op2 = getValue(I.getOperand(1));
2245 ISD::CondCode Condition = getFCmpCondCode(predicate);
2246 if (TM.Options.NoNaNsFPMath)
2247 Condition = getFCmpCodeWithoutNaN(Condition);
2248 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2249 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2252 void SelectionDAGBuilder::visitSelect(const User &I) {
2253 SmallVector<EVT, 4> ValueVTs;
2254 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2255 unsigned NumValues = ValueVTs.size();
2256 if (NumValues == 0) return;
2258 SmallVector<SDValue, 4> Values(NumValues);
2259 SDValue Cond = getValue(I.getOperand(0));
2260 SDValue LHSVal = getValue(I.getOperand(1));
2261 SDValue RHSVal = getValue(I.getOperand(2));
2262 auto BaseOps = {Cond};
2263 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2264 ISD::VSELECT : ISD::SELECT;
2266 // Min/max matching is only viable if all output VTs are the same.
2267 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2269 SelectPatternFlavor SPF = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2270 ISD::NodeType Opc = ISD::DELETED_NODE;
2272 case SPF_UMAX: Opc = ISD::UMAX; break;
2273 case SPF_UMIN: Opc = ISD::UMIN; break;
2274 case SPF_SMAX: Opc = ISD::SMAX; break;
2275 case SPF_SMIN: Opc = ISD::SMIN; break;
2279 EVT VT = ValueVTs[0];
2280 LLVMContext &Ctx = *DAG.getContext();
2281 auto &TLI = DAG.getTargetLoweringInfo();
2282 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2283 VT = TLI.getTypeToTransformTo(Ctx, VT);
2285 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT)) {
2287 LHSVal = getValue(LHS);
2288 RHSVal = getValue(RHS);
2293 for (unsigned i = 0; i != NumValues; ++i) {
2294 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2295 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2296 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2297 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2298 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2302 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2303 DAG.getVTList(ValueVTs), Values));
2306 void SelectionDAGBuilder::visitTrunc(const User &I) {
2307 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2308 SDValue N = getValue(I.getOperand(0));
2309 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2310 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2313 void SelectionDAGBuilder::visitZExt(const User &I) {
2314 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2315 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2316 SDValue N = getValue(I.getOperand(0));
2317 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2318 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2321 void SelectionDAGBuilder::visitSExt(const User &I) {
2322 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2323 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2324 SDValue N = getValue(I.getOperand(0));
2325 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2326 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2329 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2330 // FPTrunc is never a no-op cast, no need to check
2331 SDValue N = getValue(I.getOperand(0));
2332 SDLoc dl = getCurSDLoc();
2333 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2334 EVT DestVT = TLI.getValueType(I.getType());
2335 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2336 DAG.getTargetConstant(0, dl, TLI.getPointerTy())));
2339 void SelectionDAGBuilder::visitFPExt(const User &I) {
2340 // FPExt is never a no-op cast, no need to check
2341 SDValue N = getValue(I.getOperand(0));
2342 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2343 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2346 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2347 // FPToUI is never a no-op cast, no need to check
2348 SDValue N = getValue(I.getOperand(0));
2349 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2350 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2353 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2354 // FPToSI is never a no-op cast, no need to check
2355 SDValue N = getValue(I.getOperand(0));
2356 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2357 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2360 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2361 // UIToFP is never a no-op cast, no need to check
2362 SDValue N = getValue(I.getOperand(0));
2363 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2364 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2367 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2368 // SIToFP is never a no-op cast, no need to check
2369 SDValue N = getValue(I.getOperand(0));
2370 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2371 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2374 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2375 // What to do depends on the size of the integer and the size of the pointer.
2376 // We can either truncate, zero extend, or no-op, accordingly.
2377 SDValue N = getValue(I.getOperand(0));
2378 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2379 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2382 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2383 // What to do depends on the size of the integer and the size of the pointer.
2384 // We can either truncate, zero extend, or no-op, accordingly.
2385 SDValue N = getValue(I.getOperand(0));
2386 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2387 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2390 void SelectionDAGBuilder::visitBitCast(const User &I) {
2391 SDValue N = getValue(I.getOperand(0));
2392 SDLoc dl = getCurSDLoc();
2393 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2395 // BitCast assures us that source and destination are the same size so this is
2396 // either a BITCAST or a no-op.
2397 if (DestVT != N.getValueType())
2398 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2399 DestVT, N)); // convert types.
2400 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2401 // might fold any kind of constant expression to an integer constant and that
2402 // is not what we are looking for. Only regcognize a bitcast of a genuine
2403 // constant integer as an opaque constant.
2404 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2405 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2408 setValue(&I, N); // noop cast.
2411 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2413 const Value *SV = I.getOperand(0);
2414 SDValue N = getValue(SV);
2415 EVT DestVT = TLI.getValueType(I.getType());
2417 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2418 unsigned DestAS = I.getType()->getPointerAddressSpace();
2420 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2421 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2426 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2428 SDValue InVec = getValue(I.getOperand(0));
2429 SDValue InVal = getValue(I.getOperand(1));
2430 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
2431 getCurSDLoc(), TLI.getVectorIdxTy());
2432 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2433 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
2436 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2438 SDValue InVec = getValue(I.getOperand(0));
2439 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
2440 getCurSDLoc(), TLI.getVectorIdxTy());
2441 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2442 TLI.getValueType(I.getType()), InVec, InIdx));
2445 // Utility for visitShuffleVector - Return true if every element in Mask,
2446 // beginning from position Pos and ending in Pos+Size, falls within the
2447 // specified sequential range [L, L+Pos). or is undef.
2448 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2449 unsigned Pos, unsigned Size, int Low) {
2450 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2451 if (Mask[i] >= 0 && Mask[i] != Low)
2456 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2457 SDValue Src1 = getValue(I.getOperand(0));
2458 SDValue Src2 = getValue(I.getOperand(1));
2460 SmallVector<int, 8> Mask;
2461 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2462 unsigned MaskNumElts = Mask.size();
2464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2465 EVT VT = TLI.getValueType(I.getType());
2466 EVT SrcVT = Src1.getValueType();
2467 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2469 if (SrcNumElts == MaskNumElts) {
2470 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2475 // Normalize the shuffle vector since mask and vector length don't match.
2476 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2477 // Mask is longer than the source vectors and is a multiple of the source
2478 // vectors. We can use concatenate vector to make the mask and vectors
2480 if (SrcNumElts*2 == MaskNumElts) {
2481 // First check for Src1 in low and Src2 in high
2482 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2483 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2484 // The shuffle is concatenating two vectors together.
2485 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2489 // Then check for Src2 in low and Src1 in high
2490 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2491 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2492 // The shuffle is concatenating two vectors together.
2493 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2499 // Pad both vectors with undefs to make them the same length as the mask.
2500 unsigned NumConcat = MaskNumElts / SrcNumElts;
2501 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2502 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2503 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2505 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2506 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2510 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2511 getCurSDLoc(), VT, MOps1);
2512 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2513 getCurSDLoc(), VT, MOps2);
2515 // Readjust mask for new input vector length.
2516 SmallVector<int, 8> MappedOps;
2517 for (unsigned i = 0; i != MaskNumElts; ++i) {
2519 if (Idx >= (int)SrcNumElts)
2520 Idx -= SrcNumElts - MaskNumElts;
2521 MappedOps.push_back(Idx);
2524 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2529 if (SrcNumElts > MaskNumElts) {
2530 // Analyze the access pattern of the vector to see if we can extract
2531 // two subvectors and do the shuffle. The analysis is done by calculating
2532 // the range of elements the mask access on both vectors.
2533 int MinRange[2] = { static_cast<int>(SrcNumElts),
2534 static_cast<int>(SrcNumElts)};
2535 int MaxRange[2] = {-1, -1};
2537 for (unsigned i = 0; i != MaskNumElts; ++i) {
2543 if (Idx >= (int)SrcNumElts) {
2547 if (Idx > MaxRange[Input])
2548 MaxRange[Input] = Idx;
2549 if (Idx < MinRange[Input])
2550 MinRange[Input] = Idx;
2553 // Check if the access is smaller than the vector size and can we find
2554 // a reasonable extract index.
2555 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2557 int StartIdx[2]; // StartIdx to extract from
2558 for (unsigned Input = 0; Input < 2; ++Input) {
2559 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2560 RangeUse[Input] = 0; // Unused
2561 StartIdx[Input] = 0;
2565 // Find a good start index that is a multiple of the mask length. Then
2566 // see if the rest of the elements are in range.
2567 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2568 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2569 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2570 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2573 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2574 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2577 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2578 // Extract appropriate subvector and generate a vector shuffle
2579 for (unsigned Input = 0; Input < 2; ++Input) {
2580 SDValue &Src = Input == 0 ? Src1 : Src2;
2581 if (RangeUse[Input] == 0)
2582 Src = DAG.getUNDEF(VT);
2584 SDLoc dl = getCurSDLoc();
2586 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2587 DAG.getConstant(StartIdx[Input], dl, TLI.getVectorIdxTy()));
2591 // Calculate new mask.
2592 SmallVector<int, 8> MappedOps;
2593 for (unsigned i = 0; i != MaskNumElts; ++i) {
2596 if (Idx < (int)SrcNumElts)
2599 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2601 MappedOps.push_back(Idx);
2604 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2610 // We can't use either concat vectors or extract subvectors so fall back to
2611 // replacing the shuffle with extract and build vector.
2612 // to insert and build vector.
2613 EVT EltVT = VT.getVectorElementType();
2614 EVT IdxVT = TLI.getVectorIdxTy();
2615 SDLoc dl = getCurSDLoc();
2616 SmallVector<SDValue,8> Ops;
2617 for (unsigned i = 0; i != MaskNumElts; ++i) {
2622 Res = DAG.getUNDEF(EltVT);
2624 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2625 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2627 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2628 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2634 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2637 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2638 const Value *Op0 = I.getOperand(0);
2639 const Value *Op1 = I.getOperand(1);
2640 Type *AggTy = I.getType();
2641 Type *ValTy = Op1->getType();
2642 bool IntoUndef = isa<UndefValue>(Op0);
2643 bool FromUndef = isa<UndefValue>(Op1);
2645 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2647 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2648 SmallVector<EVT, 4> AggValueVTs;
2649 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2650 SmallVector<EVT, 4> ValValueVTs;
2651 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2653 unsigned NumAggValues = AggValueVTs.size();
2654 unsigned NumValValues = ValValueVTs.size();
2655 SmallVector<SDValue, 4> Values(NumAggValues);
2657 // Ignore an insertvalue that produces an empty object
2658 if (!NumAggValues) {
2659 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2663 SDValue Agg = getValue(Op0);
2665 // Copy the beginning value(s) from the original aggregate.
2666 for (; i != LinearIndex; ++i)
2667 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2668 SDValue(Agg.getNode(), Agg.getResNo() + i);
2669 // Copy values from the inserted value(s).
2671 SDValue Val = getValue(Op1);
2672 for (; i != LinearIndex + NumValValues; ++i)
2673 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2674 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2676 // Copy remaining value(s) from the original aggregate.
2677 for (; i != NumAggValues; ++i)
2678 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2679 SDValue(Agg.getNode(), Agg.getResNo() + i);
2681 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2682 DAG.getVTList(AggValueVTs), Values));
2685 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2686 const Value *Op0 = I.getOperand(0);
2687 Type *AggTy = Op0->getType();
2688 Type *ValTy = I.getType();
2689 bool OutOfUndef = isa<UndefValue>(Op0);
2691 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2693 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2694 SmallVector<EVT, 4> ValValueVTs;
2695 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2697 unsigned NumValValues = ValValueVTs.size();
2699 // Ignore a extractvalue that produces an empty object
2700 if (!NumValValues) {
2701 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2705 SmallVector<SDValue, 4> Values(NumValValues);
2707 SDValue Agg = getValue(Op0);
2708 // Copy out the selected value(s).
2709 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2710 Values[i - LinearIndex] =
2712 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2713 SDValue(Agg.getNode(), Agg.getResNo() + i);
2715 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2716 DAG.getVTList(ValValueVTs), Values));
2719 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2720 Value *Op0 = I.getOperand(0);
2721 // Note that the pointer operand may be a vector of pointers. Take the scalar
2722 // element which holds a pointer.
2723 Type *Ty = Op0->getType()->getScalarType();
2724 unsigned AS = Ty->getPointerAddressSpace();
2725 SDValue N = getValue(Op0);
2726 SDLoc dl = getCurSDLoc();
2728 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2730 const Value *Idx = *OI;
2731 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2732 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2735 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2736 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2737 DAG.getConstant(Offset, dl, N.getValueType()));
2740 Ty = StTy->getElementType(Field);
2742 Ty = cast<SequentialType>(Ty)->getElementType();
2743 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
2744 unsigned PtrSize = PtrTy.getSizeInBits();
2745 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2747 // If this is a constant subscript, handle it quickly.
2748 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
2751 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2752 SDValue OffsVal = DAG.getConstant(Offs, dl, PtrTy);
2753 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2757 // N = N + Idx * ElementSize;
2758 SDValue IdxN = getValue(Idx);
2760 // If the index is smaller or larger than intptr_t, truncate or extend
2762 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2764 // If this is a multiply by a power of two, turn it into a shl
2765 // immediately. This is a very common case.
2766 if (ElementSize != 1) {
2767 if (ElementSize.isPowerOf2()) {
2768 unsigned Amt = ElementSize.logBase2();
2769 IdxN = DAG.getNode(ISD::SHL, dl,
2770 N.getValueType(), IdxN,
2771 DAG.getConstant(Amt, dl, IdxN.getValueType()));
2773 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
2774 IdxN = DAG.getNode(ISD::MUL, dl,
2775 N.getValueType(), IdxN, Scale);
2779 N = DAG.getNode(ISD::ADD, dl,
2780 N.getValueType(), N, IdxN);
2787 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2788 // If this is a fixed sized alloca in the entry block of the function,
2789 // allocate it statically on the stack.
2790 if (FuncInfo.StaticAllocaMap.count(&I))
2791 return; // getValue will auto-populate this.
2793 SDLoc dl = getCurSDLoc();
2794 Type *Ty = I.getAllocatedType();
2795 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2796 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
2798 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
2801 SDValue AllocSize = getValue(I.getArraySize());
2803 EVT IntPtr = TLI.getPointerTy();
2804 if (AllocSize.getValueType() != IntPtr)
2805 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
2807 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
2809 DAG.getConstant(TySize, dl, IntPtr));
2811 // Handle alignment. If the requested alignment is less than or equal to
2812 // the stack alignment, ignore it. If the size is greater than or equal to
2813 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2814 unsigned StackAlign =
2815 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
2816 if (Align <= StackAlign)
2819 // Round the size of the allocation up to the stack alignment size
2820 // by add SA-1 to the size.
2821 AllocSize = DAG.getNode(ISD::ADD, dl,
2822 AllocSize.getValueType(), AllocSize,
2823 DAG.getIntPtrConstant(StackAlign - 1, dl));
2825 // Mask out the low bits for alignment purposes.
2826 AllocSize = DAG.getNode(ISD::AND, dl,
2827 AllocSize.getValueType(), AllocSize,
2828 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
2831 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
2832 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2833 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
2835 DAG.setRoot(DSA.getValue(1));
2837 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
2840 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2842 return visitAtomicLoad(I);
2844 const Value *SV = I.getOperand(0);
2845 SDValue Ptr = getValue(SV);
2847 Type *Ty = I.getType();
2849 bool isVolatile = I.isVolatile();
2850 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2852 // The IR notion of invariant_load only guarantees that all *non-faulting*
2853 // invariant loads result in the same value. The MI notion of invariant load
2854 // guarantees that the load can be legally moved to any location within its
2855 // containing function. The MI notion of invariant_load is stronger than the
2856 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
2857 // with a guarantee that the location being loaded from is dereferenceable
2858 // throughout the function's lifetime.
2860 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
2861 isDereferenceablePointer(SV, *DAG.getTarget().getDataLayout());
2862 unsigned Alignment = I.getAlignment();
2865 I.getAAMetadata(AAInfo);
2866 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
2868 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2869 SmallVector<EVT, 4> ValueVTs;
2870 SmallVector<uint64_t, 4> Offsets;
2871 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2872 unsigned NumValues = ValueVTs.size();
2877 bool ConstantMemory = false;
2878 if (isVolatile || NumValues > MaxParallelChains)
2879 // Serialize volatile loads with other side effects.
2881 else if (AA->pointsToConstantMemory(
2882 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
2883 // Do not serialize (non-volatile) loads of constant memory with anything.
2884 Root = DAG.getEntryNode();
2885 ConstantMemory = true;
2887 // Do not serialize non-volatile loads against each other.
2888 Root = DAG.getRoot();
2891 SDLoc dl = getCurSDLoc();
2894 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
2896 SmallVector<SDValue, 4> Values(NumValues);
2897 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2899 EVT PtrVT = Ptr.getValueType();
2900 unsigned ChainI = 0;
2901 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2902 // Serializing loads here may result in excessive register pressure, and
2903 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
2904 // could recover a bit by hoisting nodes upward in the chain by recognizing
2905 // they are side-effect free or do not alias. The optimizer should really
2906 // avoid this case by converting large object/array copies to llvm.memcpy
2907 // (MaxParallelChains should always remain as failsafe).
2908 if (ChainI == MaxParallelChains) {
2909 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
2910 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2911 makeArrayRef(Chains.data(), ChainI));
2915 SDValue A = DAG.getNode(ISD::ADD, dl,
2917 DAG.getConstant(Offsets[i], dl, PtrVT));
2918 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
2919 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2920 isNonTemporal, isInvariant, Alignment, AAInfo,
2924 Chains[ChainI] = L.getValue(1);
2927 if (!ConstantMemory) {
2928 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2929 makeArrayRef(Chains.data(), ChainI));
2933 PendingLoads.push_back(Chain);
2936 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
2937 DAG.getVTList(ValueVTs), Values));
2940 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2942 return visitAtomicStore(I);
2944 const Value *SrcV = I.getOperand(0);
2945 const Value *PtrV = I.getOperand(1);
2947 SmallVector<EVT, 4> ValueVTs;
2948 SmallVector<uint64_t, 4> Offsets;
2949 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
2950 ValueVTs, &Offsets);
2951 unsigned NumValues = ValueVTs.size();
2955 // Get the lowered operands. Note that we do this after
2956 // checking if NumResults is zero, because with zero results
2957 // the operands won't have values in the map.
2958 SDValue Src = getValue(SrcV);
2959 SDValue Ptr = getValue(PtrV);
2961 SDValue Root = getRoot();
2962 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
2964 EVT PtrVT = Ptr.getValueType();
2965 bool isVolatile = I.isVolatile();
2966 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2967 unsigned Alignment = I.getAlignment();
2968 SDLoc dl = getCurSDLoc();
2971 I.getAAMetadata(AAInfo);
2973 unsigned ChainI = 0;
2974 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
2975 // See visitLoad comments.
2976 if (ChainI == MaxParallelChains) {
2977 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2978 makeArrayRef(Chains.data(), ChainI));
2982 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
2983 DAG.getConstant(Offsets[i], dl, PtrVT));
2984 SDValue St = DAG.getStore(Root, dl,
2985 SDValue(Src.getNode(), Src.getResNo() + i),
2986 Add, MachinePointerInfo(PtrV, Offsets[i]),
2987 isVolatile, isNonTemporal, Alignment, AAInfo);
2988 Chains[ChainI] = St;
2991 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2992 makeArrayRef(Chains.data(), ChainI));
2993 DAG.setRoot(StoreNode);
2996 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
2997 SDLoc sdl = getCurSDLoc();
2999 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3000 Value *PtrOperand = I.getArgOperand(1);
3001 SDValue Ptr = getValue(PtrOperand);
3002 SDValue Src0 = getValue(I.getArgOperand(0));
3003 SDValue Mask = getValue(I.getArgOperand(3));
3004 EVT VT = Src0.getValueType();
3005 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3007 Alignment = DAG.getEVTAlignment(VT);
3010 I.getAAMetadata(AAInfo);
3012 MachineMemOperand *MMO =
3013 DAG.getMachineFunction().
3014 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3015 MachineMemOperand::MOStore, VT.getStoreSize(),
3017 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3019 DAG.setRoot(StoreNode);
3020 setValue(&I, StoreNode);
3023 // Gather/scatter receive a vector of pointers.
3024 // This vector of pointers may be represented as a base pointer + vector of
3025 // indices, it depends on GEP and instruction preceeding GEP
3026 // that calculates indices
3027 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3028 SelectionDAGBuilder* SDB) {
3030 assert (Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3031 GetElementPtrInst *Gep = dyn_cast<GetElementPtrInst>(Ptr);
3032 if (!Gep || Gep->getNumOperands() > 2)
3034 ShuffleVectorInst *ShuffleInst =
3035 dyn_cast<ShuffleVectorInst>(Gep->getPointerOperand());
3036 if (!ShuffleInst || !ShuffleInst->getMask()->isNullValue() ||
3037 cast<Instruction>(ShuffleInst->getOperand(0))->getOpcode() !=
3038 Instruction::InsertElement)
3041 Ptr = cast<InsertElementInst>(ShuffleInst->getOperand(0))->getOperand(1);
3043 SelectionDAG& DAG = SDB->DAG;
3044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3045 // Check is the Ptr is inside current basic block
3046 // If not, look for the shuffle instruction
3047 if (SDB->findValue(Ptr))
3048 Base = SDB->getValue(Ptr);
3049 else if (SDB->findValue(ShuffleInst)) {
3050 SDValue ShuffleNode = SDB->getValue(ShuffleInst);
3051 SDLoc sdl = ShuffleNode;
3052 Base = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, sdl,
3053 ShuffleNode.getValueType().getScalarType(), ShuffleNode,
3054 DAG.getConstant(0, sdl, TLI.getVectorIdxTy()));
3055 SDB->setValue(Ptr, Base);
3060 Value *IndexVal = Gep->getOperand(1);
3061 if (SDB->findValue(IndexVal)) {
3062 Index = SDB->getValue(IndexVal);
3064 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3065 IndexVal = Sext->getOperand(0);
3066 if (SDB->findValue(IndexVal))
3067 Index = SDB->getValue(IndexVal);
3074 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3075 SDLoc sdl = getCurSDLoc();
3077 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3078 Value *Ptr = I.getArgOperand(1);
3079 SDValue Src0 = getValue(I.getArgOperand(0));
3080 SDValue Mask = getValue(I.getArgOperand(3));
3081 EVT VT = Src0.getValueType();
3082 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3084 Alignment = DAG.getEVTAlignment(VT);
3085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3088 I.getAAMetadata(AAInfo);
3092 Value *BasePtr = Ptr;
3093 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3095 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3096 MachineMemOperand *MMO = DAG.getMachineFunction().
3097 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3098 MachineMemOperand::MOStore, VT.getStoreSize(),
3101 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3102 Index = getValue(Ptr);
3104 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3105 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3107 DAG.setRoot(Scatter);
3108 setValue(&I, Scatter);
3111 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3112 SDLoc sdl = getCurSDLoc();
3114 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3115 Value *PtrOperand = I.getArgOperand(0);
3116 SDValue Ptr = getValue(PtrOperand);
3117 SDValue Src0 = getValue(I.getArgOperand(3));
3118 SDValue Mask = getValue(I.getArgOperand(2));
3120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3121 EVT VT = TLI.getValueType(I.getType());
3122 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3124 Alignment = DAG.getEVTAlignment(VT);
3127 I.getAAMetadata(AAInfo);
3128 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3130 SDValue InChain = DAG.getRoot();
3131 if (AA->pointsToConstantMemory(
3132 AliasAnalysis::Location(PtrOperand,
3133 AA->getTypeStoreSize(I.getType()),
3135 // Do not serialize (non-volatile) loads of constant memory with anything.
3136 InChain = DAG.getEntryNode();
3139 MachineMemOperand *MMO =
3140 DAG.getMachineFunction().
3141 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3142 MachineMemOperand::MOLoad, VT.getStoreSize(),
3143 Alignment, AAInfo, Ranges);
3145 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3147 SDValue OutChain = Load.getValue(1);
3148 DAG.setRoot(OutChain);
3152 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3153 SDLoc sdl = getCurSDLoc();
3155 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3156 Value *Ptr = I.getArgOperand(0);
3157 SDValue Src0 = getValue(I.getArgOperand(3));
3158 SDValue Mask = getValue(I.getArgOperand(2));
3160 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3161 EVT VT = TLI.getValueType(I.getType());
3162 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3164 Alignment = DAG.getEVTAlignment(VT);
3167 I.getAAMetadata(AAInfo);
3168 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3170 SDValue Root = DAG.getRoot();
3173 Value *BasePtr = Ptr;
3174 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3175 bool ConstantMemory = false;
3176 if (UniformBase && AA->pointsToConstantMemory(
3177 AliasAnalysis::Location(BasePtr,
3178 AA->getTypeStoreSize(I.getType()),
3180 // Do not serialize (non-volatile) loads of constant memory with anything.
3181 Root = DAG.getEntryNode();
3182 ConstantMemory = true;
3185 MachineMemOperand *MMO =
3186 DAG.getMachineFunction().
3187 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3188 MachineMemOperand::MOLoad, VT.getStoreSize(),
3189 Alignment, AAInfo, Ranges);
3192 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy());
3193 Index = getValue(Ptr);
3195 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3196 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3199 SDValue OutChain = Gather.getValue(1);
3200 if (!ConstantMemory)
3201 PendingLoads.push_back(OutChain);
3202 setValue(&I, Gather);
3205 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3206 SDLoc dl = getCurSDLoc();
3207 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3208 AtomicOrdering FailureOrder = I.getFailureOrdering();
3209 SynchronizationScope Scope = I.getSynchScope();
3211 SDValue InChain = getRoot();
3213 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3214 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3215 SDValue L = DAG.getAtomicCmpSwap(
3216 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3217 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3218 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3219 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3221 SDValue OutChain = L.getValue(2);
3224 DAG.setRoot(OutChain);
3227 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3228 SDLoc dl = getCurSDLoc();
3230 switch (I.getOperation()) {
3231 default: llvm_unreachable("Unknown atomicrmw operation");
3232 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3233 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3234 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3235 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3236 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3237 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3238 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3239 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3240 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3241 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3242 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3244 AtomicOrdering Order = I.getOrdering();
3245 SynchronizationScope Scope = I.getSynchScope();
3247 SDValue InChain = getRoot();
3250 DAG.getAtomic(NT, dl,
3251 getValue(I.getValOperand()).getSimpleValueType(),
3253 getValue(I.getPointerOperand()),
3254 getValue(I.getValOperand()),
3255 I.getPointerOperand(),
3256 /* Alignment=*/ 0, Order, Scope);
3258 SDValue OutChain = L.getValue(1);
3261 DAG.setRoot(OutChain);
3264 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3265 SDLoc dl = getCurSDLoc();
3266 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3269 Ops[1] = DAG.getConstant(I.getOrdering(), dl, TLI.getPointerTy());
3270 Ops[2] = DAG.getConstant(I.getSynchScope(), dl, TLI.getPointerTy());
3271 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3274 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3275 SDLoc dl = getCurSDLoc();
3276 AtomicOrdering Order = I.getOrdering();
3277 SynchronizationScope Scope = I.getSynchScope();
3279 SDValue InChain = getRoot();
3281 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3282 EVT VT = TLI.getValueType(I.getType());
3284 if (I.getAlignment() < VT.getSizeInBits() / 8)
3285 report_fatal_error("Cannot generate unaligned atomic load");
3287 MachineMemOperand *MMO =
3288 DAG.getMachineFunction().
3289 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3290 MachineMemOperand::MOVolatile |
3291 MachineMemOperand::MOLoad,
3293 I.getAlignment() ? I.getAlignment() :
3294 DAG.getEVTAlignment(VT));
3296 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3298 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3299 getValue(I.getPointerOperand()), MMO,
3302 SDValue OutChain = L.getValue(1);
3305 DAG.setRoot(OutChain);
3308 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3309 SDLoc dl = getCurSDLoc();
3311 AtomicOrdering Order = I.getOrdering();
3312 SynchronizationScope Scope = I.getSynchScope();
3314 SDValue InChain = getRoot();
3316 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3317 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3319 if (I.getAlignment() < VT.getSizeInBits() / 8)
3320 report_fatal_error("Cannot generate unaligned atomic store");
3323 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3325 getValue(I.getPointerOperand()),
3326 getValue(I.getValueOperand()),
3327 I.getPointerOperand(), I.getAlignment(),
3330 DAG.setRoot(OutChain);
3333 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3335 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3336 unsigned Intrinsic) {
3337 bool HasChain = !I.doesNotAccessMemory();
3338 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3340 // Build the operand list.
3341 SmallVector<SDValue, 8> Ops;
3342 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3344 // We don't need to serialize loads against other loads.
3345 Ops.push_back(DAG.getRoot());
3347 Ops.push_back(getRoot());
3351 // Info is set by getTgtMemInstrinsic
3352 TargetLowering::IntrinsicInfo Info;
3353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3354 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3356 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3357 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3358 Info.opc == ISD::INTRINSIC_W_CHAIN)
3359 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3360 TLI.getPointerTy()));
3362 // Add all operands of the call to the operand list.
3363 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3364 SDValue Op = getValue(I.getArgOperand(i));
3368 SmallVector<EVT, 4> ValueVTs;
3369 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3372 ValueVTs.push_back(MVT::Other);
3374 SDVTList VTs = DAG.getVTList(ValueVTs);
3378 if (IsTgtIntrinsic) {
3379 // This is target intrinsic that touches memory
3380 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3381 VTs, Ops, Info.memVT,
3382 MachinePointerInfo(Info.ptrVal, Info.offset),
3383 Info.align, Info.vol,
3384 Info.readMem, Info.writeMem, Info.size);
3385 } else if (!HasChain) {
3386 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3387 } else if (!I.getType()->isVoidTy()) {
3388 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3390 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3394 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3396 PendingLoads.push_back(Chain);
3401 if (!I.getType()->isVoidTy()) {
3402 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3403 EVT VT = TLI.getValueType(PTy);
3404 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3407 setValue(&I, Result);
3411 /// GetSignificand - Get the significand and build it into a floating-point
3412 /// number with exponent of 1:
3414 /// Op = (Op & 0x007fffff) | 0x3f800000;
3416 /// where Op is the hexadecimal representation of floating point value.
3418 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3419 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3420 DAG.getConstant(0x007fffff, dl, MVT::i32));
3421 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3422 DAG.getConstant(0x3f800000, dl, MVT::i32));
3423 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3426 /// GetExponent - Get the exponent:
3428 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3430 /// where Op is the hexadecimal representation of floating point value.
3432 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3434 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3435 DAG.getConstant(0x7f800000, dl, MVT::i32));
3436 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3437 DAG.getConstant(23, dl, TLI.getPointerTy()));
3438 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3439 DAG.getConstant(127, dl, MVT::i32));
3440 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3443 /// getF32Constant - Get 32-bit floating point constant.
3445 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3446 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3450 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3451 SelectionDAG &DAG) {
3452 // IntegerPartOfX = ((int32_t)(t0);
3453 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3455 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3456 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3457 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3459 // IntegerPartOfX <<= 23;
3460 IntegerPartOfX = DAG.getNode(
3461 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3462 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy()));
3464 SDValue TwoToFractionalPartOfX;
3465 if (LimitFloatPrecision <= 6) {
3466 // For floating-point precision of 6:
3468 // TwoToFractionalPartOfX =
3470 // (0.735607626f + 0.252464424f * x) * x;
3472 // error 0.0144103317, which is 6 bits
3473 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3474 getF32Constant(DAG, 0x3e814304, dl));
3475 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3476 getF32Constant(DAG, 0x3f3c50c8, dl));
3477 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3478 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3479 getF32Constant(DAG, 0x3f7f5e7e, dl));
3480 } else if (LimitFloatPrecision <= 12) {
3481 // For floating-point precision of 12:
3483 // TwoToFractionalPartOfX =
3486 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3488 // error 0.000107046256, which is 13 to 14 bits
3489 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3490 getF32Constant(DAG, 0x3da235e3, dl));
3491 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3492 getF32Constant(DAG, 0x3e65b8f3, dl));
3493 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3494 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3495 getF32Constant(DAG, 0x3f324b07, dl));
3496 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3497 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3498 getF32Constant(DAG, 0x3f7ff8fd, dl));
3499 } else { // LimitFloatPrecision <= 18
3500 // For floating-point precision of 18:
3502 // TwoToFractionalPartOfX =
3506 // (0.554906021e-1f +
3507 // (0.961591928e-2f +
3508 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3509 // error 2.47208000*10^(-7), which is better than 18 bits
3510 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3511 getF32Constant(DAG, 0x3924b03e, dl));
3512 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3513 getF32Constant(DAG, 0x3ab24b87, dl));
3514 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3515 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3516 getF32Constant(DAG, 0x3c1d8c17, dl));
3517 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3518 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3519 getF32Constant(DAG, 0x3d634a1d, dl));
3520 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3521 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3522 getF32Constant(DAG, 0x3e75fe14, dl));
3523 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3524 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3525 getF32Constant(DAG, 0x3f317234, dl));
3526 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3527 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3528 getF32Constant(DAG, 0x3f800000, dl));
3531 // Add the exponent into the result in integer domain.
3532 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3533 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3534 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3537 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3538 /// limited-precision mode.
3539 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3540 const TargetLowering &TLI) {
3541 if (Op.getValueType() == MVT::f32 &&
3542 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3544 // Put the exponent in the right bit position for later addition to the
3547 // #define LOG2OFe 1.4426950f
3548 // t0 = Op * LOG2OFe
3549 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3550 getF32Constant(DAG, 0x3fb8aa3b, dl));
3551 return getLimitedPrecisionExp2(t0, dl, DAG);
3554 // No special expansion.
3555 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3558 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3559 /// limited-precision mode.
3560 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3561 const TargetLowering &TLI) {
3562 if (Op.getValueType() == MVT::f32 &&
3563 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3564 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3566 // Scale the exponent by log(2) [0.69314718f].
3567 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3568 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3569 getF32Constant(DAG, 0x3f317218, dl));
3571 // Get the significand and build it into a floating-point number with
3573 SDValue X = GetSignificand(DAG, Op1, dl);
3575 SDValue LogOfMantissa;
3576 if (LimitFloatPrecision <= 6) {
3577 // For floating-point precision of 6:
3581 // (1.4034025f - 0.23903021f * x) * x;
3583 // error 0.0034276066, which is better than 8 bits
3584 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3585 getF32Constant(DAG, 0xbe74c456, dl));
3586 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3587 getF32Constant(DAG, 0x3fb3a2b1, dl));
3588 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3589 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3590 getF32Constant(DAG, 0x3f949a29, dl));
3591 } else if (LimitFloatPrecision <= 12) {
3592 // For floating-point precision of 12:
3598 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3600 // error 0.000061011436, which is 14 bits
3601 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3602 getF32Constant(DAG, 0xbd67b6d6, dl));
3603 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3604 getF32Constant(DAG, 0x3ee4f4b8, dl));
3605 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3606 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3607 getF32Constant(DAG, 0x3fbc278b, dl));
3608 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3609 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3610 getF32Constant(DAG, 0x40348e95, dl));
3611 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3612 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3613 getF32Constant(DAG, 0x3fdef31a, dl));
3614 } else { // LimitFloatPrecision <= 18
3615 // For floating-point precision of 18:
3623 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3625 // error 0.0000023660568, which is better than 18 bits
3626 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3627 getF32Constant(DAG, 0xbc91e5ac, dl));
3628 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3629 getF32Constant(DAG, 0x3e4350aa, dl));
3630 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3631 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3632 getF32Constant(DAG, 0x3f60d3e3, dl));
3633 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3634 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3635 getF32Constant(DAG, 0x4011cdf0, dl));
3636 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3637 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3638 getF32Constant(DAG, 0x406cfd1c, dl));
3639 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3640 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3641 getF32Constant(DAG, 0x408797cb, dl));
3642 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3643 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3644 getF32Constant(DAG, 0x4006dcab, dl));
3647 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3650 // No special expansion.
3651 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3654 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3655 /// limited-precision mode.
3656 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3657 const TargetLowering &TLI) {
3658 if (Op.getValueType() == MVT::f32 &&
3659 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3660 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3662 // Get the exponent.
3663 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3665 // Get the significand and build it into a floating-point number with
3667 SDValue X = GetSignificand(DAG, Op1, dl);
3669 // Different possible minimax approximations of significand in
3670 // floating-point for various degrees of accuracy over [1,2].
3671 SDValue Log2ofMantissa;
3672 if (LimitFloatPrecision <= 6) {
3673 // For floating-point precision of 6:
3675 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3677 // error 0.0049451742, which is more than 7 bits
3678 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3679 getF32Constant(DAG, 0xbeb08fe0, dl));
3680 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3681 getF32Constant(DAG, 0x40019463, dl));
3682 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3683 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3684 getF32Constant(DAG, 0x3fd6633d, dl));
3685 } else if (LimitFloatPrecision <= 12) {
3686 // For floating-point precision of 12:
3692 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3694 // error 0.0000876136000, which is better than 13 bits
3695 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3696 getF32Constant(DAG, 0xbda7262e, dl));
3697 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3698 getF32Constant(DAG, 0x3f25280b, dl));
3699 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3700 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3701 getF32Constant(DAG, 0x4007b923, dl));
3702 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3703 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3704 getF32Constant(DAG, 0x40823e2f, dl));
3705 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3706 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3707 getF32Constant(DAG, 0x4020d29c, dl));
3708 } else { // LimitFloatPrecision <= 18
3709 // For floating-point precision of 18:
3718 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3720 // error 0.0000018516, which is better than 18 bits
3721 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3722 getF32Constant(DAG, 0xbcd2769e, dl));
3723 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3724 getF32Constant(DAG, 0x3e8ce0b9, dl));
3725 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3726 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3727 getF32Constant(DAG, 0x3fa22ae7, dl));
3728 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3729 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3730 getF32Constant(DAG, 0x40525723, dl));
3731 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3732 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3733 getF32Constant(DAG, 0x40aaf200, dl));
3734 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3735 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3736 getF32Constant(DAG, 0x40c39dad, dl));
3737 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3738 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3739 getF32Constant(DAG, 0x4042902c, dl));
3742 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3745 // No special expansion.
3746 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
3749 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
3750 /// limited-precision mode.
3751 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3752 const TargetLowering &TLI) {
3753 if (Op.getValueType() == MVT::f32 &&
3754 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3755 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3757 // Scale the exponent by log10(2) [0.30102999f].
3758 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3759 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3760 getF32Constant(DAG, 0x3e9a209a, dl));
3762 // Get the significand and build it into a floating-point number with
3764 SDValue X = GetSignificand(DAG, Op1, dl);
3766 SDValue Log10ofMantissa;
3767 if (LimitFloatPrecision <= 6) {
3768 // For floating-point precision of 6:
3770 // Log10ofMantissa =
3772 // (0.60948995f - 0.10380950f * x) * x;
3774 // error 0.0014886165, which is 6 bits
3775 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3776 getF32Constant(DAG, 0xbdd49a13, dl));
3777 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3778 getF32Constant(DAG, 0x3f1c0789, dl));
3779 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3780 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3781 getF32Constant(DAG, 0x3f011300, dl));
3782 } else if (LimitFloatPrecision <= 12) {
3783 // For floating-point precision of 12:
3785 // Log10ofMantissa =
3788 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3790 // error 0.00019228036, which is better than 12 bits
3791 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3792 getF32Constant(DAG, 0x3d431f31, dl));
3793 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3794 getF32Constant(DAG, 0x3ea21fb2, dl));
3795 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3796 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3797 getF32Constant(DAG, 0x3f6ae232, dl));
3798 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3799 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3800 getF32Constant(DAG, 0x3f25f7c3, dl));
3801 } else { // LimitFloatPrecision <= 18
3802 // For floating-point precision of 18:
3804 // Log10ofMantissa =
3809 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3811 // error 0.0000037995730, which is better than 18 bits
3812 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3813 getF32Constant(DAG, 0x3c5d51ce, dl));
3814 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3815 getF32Constant(DAG, 0x3e00685a, dl));
3816 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3817 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3818 getF32Constant(DAG, 0x3efb6798, dl));
3819 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3820 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3821 getF32Constant(DAG, 0x3f88d192, dl));
3822 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3823 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3824 getF32Constant(DAG, 0x3fc4316c, dl));
3825 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3826 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3827 getF32Constant(DAG, 0x3f57ce70, dl));
3830 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
3833 // No special expansion.
3834 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
3837 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3838 /// limited-precision mode.
3839 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3840 const TargetLowering &TLI) {
3841 if (Op.getValueType() == MVT::f32 &&
3842 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
3843 return getLimitedPrecisionExp2(Op, dl, DAG);
3845 // No special expansion.
3846 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
3849 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3850 /// limited-precision mode with x == 10.0f.
3851 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
3852 SelectionDAG &DAG, const TargetLowering &TLI) {
3853 bool IsExp10 = false;
3854 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
3855 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3856 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
3858 IsExp10 = LHSC->isExactlyValue(Ten);
3863 // Put the exponent in the right bit position for later addition to the
3866 // #define LOG2OF10 3.3219281f
3867 // t0 = Op * LOG2OF10;
3868 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
3869 getF32Constant(DAG, 0x40549a78, dl));
3870 return getLimitedPrecisionExp2(t0, dl, DAG);
3873 // No special expansion.
3874 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
3878 /// ExpandPowI - Expand a llvm.powi intrinsic.
3879 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
3880 SelectionDAG &DAG) {
3881 // If RHS is a constant, we can expand this out to a multiplication tree,
3882 // otherwise we end up lowering to a call to __powidf2 (for example). When
3883 // optimizing for size, we only want to do this if the expansion would produce
3884 // a small number of multiplies, otherwise we do the full expansion.
3885 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3886 // Get the exponent as a positive value.
3887 unsigned Val = RHSC->getSExtValue();
3888 if ((int)Val < 0) Val = -Val;
3890 // powi(x, 0) -> 1.0
3892 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
3894 const Function *F = DAG.getMachineFunction().getFunction();
3895 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
3896 // If optimizing for size, don't insert too many multiplies. This
3897 // inserts up to 5 multiplies.
3898 countPopulation(Val) + Log2_32(Val) < 7) {
3899 // We use the simple binary decomposition method to generate the multiply
3900 // sequence. There are more optimal ways to do this (for example,
3901 // powi(x,15) generates one more multiply than it should), but this has
3902 // the benefit of being both really simple and much better than a libcall.
3903 SDValue Res; // Logically starts equal to 1.0
3904 SDValue CurSquare = LHS;
3908 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3910 Res = CurSquare; // 1.0*CurSquare.
3913 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3914 CurSquare, CurSquare);
3918 // If the original was negative, invert the result, producing 1/(x*x*x).
3919 if (RHSC->getSExtValue() < 0)
3920 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3921 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
3926 // Otherwise, expand to a libcall.
3927 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3930 // getTruncatedArgReg - Find underlying register used for an truncated
3932 static unsigned getTruncatedArgReg(const SDValue &N) {
3933 if (N.getOpcode() != ISD::TRUNCATE)
3936 const SDValue &Ext = N.getOperand(0);
3937 if (Ext.getOpcode() == ISD::AssertZext ||
3938 Ext.getOpcode() == ISD::AssertSext) {
3939 const SDValue &CFR = Ext.getOperand(0);
3940 if (CFR.getOpcode() == ISD::CopyFromReg)
3941 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
3942 if (CFR.getOpcode() == ISD::TRUNCATE)
3943 return getTruncatedArgReg(CFR);
3948 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3949 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3950 /// At the end of instruction selection, they will be inserted to the entry BB.
3951 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
3952 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
3953 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
3954 const Argument *Arg = dyn_cast<Argument>(V);
3958 MachineFunction &MF = DAG.getMachineFunction();
3959 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
3961 // Ignore inlined function arguments here.
3963 // FIXME: Should we be checking DL->inlinedAt() to determine this?
3964 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
3967 Optional<MachineOperand> Op;
3968 // Some arguments' frame index is recorded during argument lowering.
3969 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
3970 Op = MachineOperand::CreateFI(FI);
3972 if (!Op && N.getNode()) {
3974 if (N.getOpcode() == ISD::CopyFromReg)
3975 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3977 Reg = getTruncatedArgReg(N);
3978 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3979 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3980 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3985 Op = MachineOperand::CreateReg(Reg, false);
3989 // Check if ValueMap has reg number.
3990 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
3991 if (VMI != FuncInfo.ValueMap.end())
3992 Op = MachineOperand::CreateReg(VMI->second, false);
3995 if (!Op && N.getNode())
3996 // Check if frame index is available.
3997 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
3998 if (FrameIndexSDNode *FINode =
3999 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4000 Op = MachineOperand::CreateFI(FINode->getIndex());
4005 assert(Variable->isValidLocationForIntrinsic(DL) &&
4006 "Expected inlined-at fields to agree");
4008 FuncInfo.ArgDbgValues.push_back(
4009 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4010 Op->getReg(), Offset, Variable, Expr));
4012 FuncInfo.ArgDbgValues.push_back(
4013 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4016 .addMetadata(Variable)
4017 .addMetadata(Expr));
4022 // VisualStudio defines setjmp as _setjmp
4023 #if defined(_MSC_VER) && defined(setjmp) && \
4024 !defined(setjmp_undefined_for_msvc)
4025 # pragma push_macro("setjmp")
4027 # define setjmp_undefined_for_msvc
4030 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4031 /// we want to emit this as a call to a named external function, return the name
4032 /// otherwise lower it and return null.
4034 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4035 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4036 SDLoc sdl = getCurSDLoc();
4037 DebugLoc dl = getCurDebugLoc();
4040 switch (Intrinsic) {
4042 // By default, turn this into a target intrinsic node.
4043 visitTargetIntrinsic(I, Intrinsic);
4045 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4046 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4047 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4048 case Intrinsic::returnaddress:
4049 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4050 getValue(I.getArgOperand(0))));
4052 case Intrinsic::frameaddress:
4053 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4054 getValue(I.getArgOperand(0))));
4056 case Intrinsic::read_register: {
4057 Value *Reg = I.getArgOperand(0);
4058 SDValue Chain = getRoot();
4060 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4061 EVT VT = TLI.getValueType(I.getType());
4062 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4063 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4065 DAG.setRoot(Res.getValue(1));
4068 case Intrinsic::write_register: {
4069 Value *Reg = I.getArgOperand(0);
4070 Value *RegValue = I.getArgOperand(1);
4071 SDValue Chain = getRoot();
4073 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4074 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4075 RegName, getValue(RegValue)));
4078 case Intrinsic::setjmp:
4079 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4080 case Intrinsic::longjmp:
4081 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4082 case Intrinsic::memcpy: {
4083 // FIXME: this definition of "user defined address space" is x86-specific
4084 // Assert for address < 256 since we support only user defined address
4086 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4088 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4090 "Unknown address space");
4091 SDValue Op1 = getValue(I.getArgOperand(0));
4092 SDValue Op2 = getValue(I.getArgOperand(1));
4093 SDValue Op3 = getValue(I.getArgOperand(2));
4094 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4096 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4097 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4098 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4099 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4101 MachinePointerInfo(I.getArgOperand(0)),
4102 MachinePointerInfo(I.getArgOperand(1)));
4103 updateDAGForMaybeTailCall(MC);
4106 case Intrinsic::memset: {
4107 // FIXME: this definition of "user defined address space" is x86-specific
4108 // Assert for address < 256 since we support only user defined address
4110 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4112 "Unknown address space");
4113 SDValue Op1 = getValue(I.getArgOperand(0));
4114 SDValue Op2 = getValue(I.getArgOperand(1));
4115 SDValue Op3 = getValue(I.getArgOperand(2));
4116 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4118 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4119 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4120 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4121 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4122 isTC, MachinePointerInfo(I.getArgOperand(0)));
4123 updateDAGForMaybeTailCall(MS);
4126 case Intrinsic::memmove: {
4127 // FIXME: this definition of "user defined address space" is x86-specific
4128 // Assert for address < 256 since we support only user defined address
4130 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4132 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4134 "Unknown address space");
4135 SDValue Op1 = getValue(I.getArgOperand(0));
4136 SDValue Op2 = getValue(I.getArgOperand(1));
4137 SDValue Op3 = getValue(I.getArgOperand(2));
4138 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4140 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4141 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4142 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4143 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4144 isTC, MachinePointerInfo(I.getArgOperand(0)),
4145 MachinePointerInfo(I.getArgOperand(1)));
4146 updateDAGForMaybeTailCall(MM);
4149 case Intrinsic::dbg_declare: {
4150 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4151 DILocalVariable *Variable = DI.getVariable();
4152 DIExpression *Expression = DI.getExpression();
4153 const Value *Address = DI.getAddress();
4154 assert(Variable && "Missing variable");
4156 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4160 // Check if address has undef value.
4161 if (isa<UndefValue>(Address) ||
4162 (Address->use_empty() && !isa<Argument>(Address))) {
4163 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4167 SDValue &N = NodeMap[Address];
4168 if (!N.getNode() && isa<Argument>(Address))
4169 // Check unused arguments map.
4170 N = UnusedArgNodeMap[Address];
4173 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4174 Address = BCI->getOperand(0);
4175 // Parameters are handled specially.
4176 bool isParameter = Variable->getTag() == dwarf::DW_TAG_arg_variable ||
4177 isa<Argument>(Address);
4179 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4181 if (isParameter && !AI) {
4182 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4184 // Byval parameter. We have a frame index at this point.
4185 SDV = DAG.getFrameIndexDbgValue(
4186 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4188 // Address is an argument, so try to emit its dbg value using
4189 // virtual register info from the FuncInfo.ValueMap.
4190 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4195 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4196 true, 0, dl, SDNodeOrder);
4198 // Can't do anything with other non-AI cases yet.
4199 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4200 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4201 DEBUG(Address->dump());
4204 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4206 // If Address is an argument then try to emit its dbg value using
4207 // virtual register info from the FuncInfo.ValueMap.
4208 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4210 // If variable is pinned by a alloca in dominating bb then
4211 // use StaticAllocaMap.
4212 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4213 if (AI->getParent() != DI.getParent()) {
4214 DenseMap<const AllocaInst*, int>::iterator SI =
4215 FuncInfo.StaticAllocaMap.find(AI);
4216 if (SI != FuncInfo.StaticAllocaMap.end()) {
4217 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4218 0, dl, SDNodeOrder);
4219 DAG.AddDbgValue(SDV, nullptr, false);
4224 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4229 case Intrinsic::dbg_value: {
4230 const DbgValueInst &DI = cast<DbgValueInst>(I);
4231 assert(DI.getVariable() && "Missing variable");
4233 DILocalVariable *Variable = DI.getVariable();
4234 DIExpression *Expression = DI.getExpression();
4235 uint64_t Offset = DI.getOffset();
4236 const Value *V = DI.getValue();
4241 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4242 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4244 DAG.AddDbgValue(SDV, nullptr, false);
4246 // Do not use getValue() in here; we don't want to generate code at
4247 // this point if it hasn't been done yet.
4248 SDValue N = NodeMap[V];
4249 if (!N.getNode() && isa<Argument>(V))
4250 // Check unused arguments map.
4251 N = UnusedArgNodeMap[V];
4253 // A dbg.value for an alloca is always indirect.
4254 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4255 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4257 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4258 IsIndirect, Offset, dl, SDNodeOrder);
4259 DAG.AddDbgValue(SDV, N.getNode(), false);
4261 } else if (!V->use_empty() ) {
4262 // Do not call getValue(V) yet, as we don't want to generate code.
4263 // Remember it for later.
4264 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4265 DanglingDebugInfoMap[V] = DDI;
4267 // We may expand this to cover more cases. One case where we have no
4268 // data available is an unreferenced parameter.
4269 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4273 // Build a debug info table entry.
4274 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4275 V = BCI->getOperand(0);
4276 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4277 // Don't handle byval struct arguments or VLAs, for example.
4279 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4280 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4283 DenseMap<const AllocaInst*, int>::iterator SI =
4284 FuncInfo.StaticAllocaMap.find(AI);
4285 if (SI == FuncInfo.StaticAllocaMap.end())
4286 return nullptr; // VLAs.
4290 case Intrinsic::eh_typeid_for: {
4291 // Find the type id for the given typeinfo.
4292 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4293 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4294 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4299 case Intrinsic::eh_return_i32:
4300 case Intrinsic::eh_return_i64:
4301 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4302 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4305 getValue(I.getArgOperand(0)),
4306 getValue(I.getArgOperand(1))));
4308 case Intrinsic::eh_unwind_init:
4309 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4311 case Intrinsic::eh_dwarf_cfa: {
4312 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4313 TLI.getPointerTy());
4314 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4315 CfaArg.getValueType(),
4316 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4317 CfaArg.getValueType()),
4319 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4320 DAG.getConstant(0, sdl, TLI.getPointerTy()));
4321 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4325 case Intrinsic::eh_sjlj_callsite: {
4326 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4327 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4328 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4329 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4331 MMI.setCurrentCallSite(CI->getZExtValue());
4334 case Intrinsic::eh_sjlj_functioncontext: {
4335 // Get and store the index of the function context.
4336 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4338 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4339 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4340 MFI->setFunctionContextIndex(FI);
4343 case Intrinsic::eh_sjlj_setjmp: {
4346 Ops[1] = getValue(I.getArgOperand(0));
4347 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4348 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4349 setValue(&I, Op.getValue(0));
4350 DAG.setRoot(Op.getValue(1));
4353 case Intrinsic::eh_sjlj_longjmp: {
4354 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4355 getRoot(), getValue(I.getArgOperand(0))));
4359 case Intrinsic::masked_gather:
4360 visitMaskedGather(I);
4362 case Intrinsic::masked_load:
4365 case Intrinsic::masked_scatter:
4366 visitMaskedScatter(I);
4368 case Intrinsic::masked_store:
4369 visitMaskedStore(I);
4371 case Intrinsic::x86_mmx_pslli_w:
4372 case Intrinsic::x86_mmx_pslli_d:
4373 case Intrinsic::x86_mmx_pslli_q:
4374 case Intrinsic::x86_mmx_psrli_w:
4375 case Intrinsic::x86_mmx_psrli_d:
4376 case Intrinsic::x86_mmx_psrli_q:
4377 case Intrinsic::x86_mmx_psrai_w:
4378 case Intrinsic::x86_mmx_psrai_d: {
4379 SDValue ShAmt = getValue(I.getArgOperand(1));
4380 if (isa<ConstantSDNode>(ShAmt)) {
4381 visitTargetIntrinsic(I, Intrinsic);
4384 unsigned NewIntrinsic = 0;
4385 EVT ShAmtVT = MVT::v2i32;
4386 switch (Intrinsic) {
4387 case Intrinsic::x86_mmx_pslli_w:
4388 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4390 case Intrinsic::x86_mmx_pslli_d:
4391 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4393 case Intrinsic::x86_mmx_pslli_q:
4394 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4396 case Intrinsic::x86_mmx_psrli_w:
4397 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4399 case Intrinsic::x86_mmx_psrli_d:
4400 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4402 case Intrinsic::x86_mmx_psrli_q:
4403 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4405 case Intrinsic::x86_mmx_psrai_w:
4406 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4408 case Intrinsic::x86_mmx_psrai_d:
4409 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4411 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4414 // The vector shift intrinsics with scalars uses 32b shift amounts but
4415 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4417 // We must do this early because v2i32 is not a legal type.
4420 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4421 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4422 EVT DestVT = TLI.getValueType(I.getType());
4423 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4424 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4425 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4426 getValue(I.getArgOperand(0)), ShAmt);
4430 case Intrinsic::convertff:
4431 case Intrinsic::convertfsi:
4432 case Intrinsic::convertfui:
4433 case Intrinsic::convertsif:
4434 case Intrinsic::convertuif:
4435 case Intrinsic::convertss:
4436 case Intrinsic::convertsu:
4437 case Intrinsic::convertus:
4438 case Intrinsic::convertuu: {
4439 ISD::CvtCode Code = ISD::CVT_INVALID;
4440 switch (Intrinsic) {
4441 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4442 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4443 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4444 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4445 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4446 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4447 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4448 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4449 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4450 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4452 EVT DestVT = TLI.getValueType(I.getType());
4453 const Value *Op1 = I.getArgOperand(0);
4454 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4455 DAG.getValueType(DestVT),
4456 DAG.getValueType(getValue(Op1).getValueType()),
4457 getValue(I.getArgOperand(1)),
4458 getValue(I.getArgOperand(2)),
4463 case Intrinsic::powi:
4464 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4465 getValue(I.getArgOperand(1)), DAG));
4467 case Intrinsic::log:
4468 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4470 case Intrinsic::log2:
4471 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4473 case Intrinsic::log10:
4474 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4476 case Intrinsic::exp:
4477 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4479 case Intrinsic::exp2:
4480 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4482 case Intrinsic::pow:
4483 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4484 getValue(I.getArgOperand(1)), DAG, TLI));
4486 case Intrinsic::sqrt:
4487 case Intrinsic::fabs:
4488 case Intrinsic::sin:
4489 case Intrinsic::cos:
4490 case Intrinsic::floor:
4491 case Intrinsic::ceil:
4492 case Intrinsic::trunc:
4493 case Intrinsic::rint:
4494 case Intrinsic::nearbyint:
4495 case Intrinsic::round: {
4497 switch (Intrinsic) {
4498 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4499 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4500 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4501 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4502 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4503 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4504 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4505 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4506 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4507 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4508 case Intrinsic::round: Opcode = ISD::FROUND; break;
4511 setValue(&I, DAG.getNode(Opcode, sdl,
4512 getValue(I.getArgOperand(0)).getValueType(),
4513 getValue(I.getArgOperand(0))));
4516 case Intrinsic::minnum:
4517 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4518 getValue(I.getArgOperand(0)).getValueType(),
4519 getValue(I.getArgOperand(0)),
4520 getValue(I.getArgOperand(1))));
4522 case Intrinsic::maxnum:
4523 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4524 getValue(I.getArgOperand(0)).getValueType(),
4525 getValue(I.getArgOperand(0)),
4526 getValue(I.getArgOperand(1))));
4528 case Intrinsic::copysign:
4529 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4530 getValue(I.getArgOperand(0)).getValueType(),
4531 getValue(I.getArgOperand(0)),
4532 getValue(I.getArgOperand(1))));
4534 case Intrinsic::fma:
4535 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4536 getValue(I.getArgOperand(0)).getValueType(),
4537 getValue(I.getArgOperand(0)),
4538 getValue(I.getArgOperand(1)),
4539 getValue(I.getArgOperand(2))));
4541 case Intrinsic::fmuladd: {
4542 EVT VT = TLI.getValueType(I.getType());
4543 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4544 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4545 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4546 getValue(I.getArgOperand(0)).getValueType(),
4547 getValue(I.getArgOperand(0)),
4548 getValue(I.getArgOperand(1)),
4549 getValue(I.getArgOperand(2))));
4551 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4552 getValue(I.getArgOperand(0)).getValueType(),
4553 getValue(I.getArgOperand(0)),
4554 getValue(I.getArgOperand(1)));
4555 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4556 getValue(I.getArgOperand(0)).getValueType(),
4558 getValue(I.getArgOperand(2)));
4563 case Intrinsic::convert_to_fp16:
4564 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4565 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4566 getValue(I.getArgOperand(0)),
4567 DAG.getTargetConstant(0, sdl,
4570 case Intrinsic::convert_from_fp16:
4572 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
4573 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4574 getValue(I.getArgOperand(0)))));
4576 case Intrinsic::pcmarker: {
4577 SDValue Tmp = getValue(I.getArgOperand(0));
4578 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4581 case Intrinsic::readcyclecounter: {
4582 SDValue Op = getRoot();
4583 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4584 DAG.getVTList(MVT::i64, MVT::Other), Op);
4586 DAG.setRoot(Res.getValue(1));
4589 case Intrinsic::bswap:
4590 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4591 getValue(I.getArgOperand(0)).getValueType(),
4592 getValue(I.getArgOperand(0))));
4594 case Intrinsic::cttz: {
4595 SDValue Arg = getValue(I.getArgOperand(0));
4596 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4597 EVT Ty = Arg.getValueType();
4598 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4602 case Intrinsic::ctlz: {
4603 SDValue Arg = getValue(I.getArgOperand(0));
4604 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4605 EVT Ty = Arg.getValueType();
4606 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4610 case Intrinsic::ctpop: {
4611 SDValue Arg = getValue(I.getArgOperand(0));
4612 EVT Ty = Arg.getValueType();
4613 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4616 case Intrinsic::stacksave: {
4617 SDValue Op = getRoot();
4618 Res = DAG.getNode(ISD::STACKSAVE, sdl,
4619 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
4621 DAG.setRoot(Res.getValue(1));
4624 case Intrinsic::stackrestore: {
4625 Res = getValue(I.getArgOperand(0));
4626 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4629 case Intrinsic::stackprotector: {
4630 // Emit code into the DAG to store the stack guard onto the stack.
4631 MachineFunction &MF = DAG.getMachineFunction();
4632 MachineFrameInfo *MFI = MF.getFrameInfo();
4633 EVT PtrTy = TLI.getPointerTy();
4634 SDValue Src, Chain = getRoot();
4635 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4636 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4638 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4639 // global variable __stack_chk_guard.
4641 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4642 if (BC->getOpcode() == Instruction::BitCast)
4643 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4645 if (GV && TLI.useLoadStackGuardNode()) {
4646 // Emit a LOAD_STACK_GUARD node.
4647 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4649 MachinePointerInfo MPInfo(GV);
4650 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4651 unsigned Flags = MachineMemOperand::MOLoad |
4652 MachineMemOperand::MOInvariant;
4653 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4654 PtrTy.getSizeInBits() / 8,
4655 DAG.getEVTAlignment(PtrTy));
4656 Node->setMemRefs(MemRefs, MemRefs + 1);
4658 // Copy the guard value to a virtual register so that it can be
4659 // retrieved in the epilogue.
4660 Src = SDValue(Node, 0);
4661 const TargetRegisterClass *RC =
4662 TLI.getRegClassFor(Src.getSimpleValueType());
4663 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4665 SPDescriptor.setGuardReg(Reg);
4666 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4668 Src = getValue(I.getArgOperand(0)); // The guard's value.
4671 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4673 int FI = FuncInfo.StaticAllocaMap[Slot];
4674 MFI->setStackProtectorIndex(FI);
4676 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4678 // Store the stack protector onto the stack.
4679 Res = DAG.getStore(Chain, sdl, Src, FIN,
4680 MachinePointerInfo::getFixedStack(FI),
4686 case Intrinsic::objectsize: {
4687 // If we don't know by now, we're never going to know.
4688 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4690 assert(CI && "Non-constant type in __builtin_object_size?");
4692 SDValue Arg = getValue(I.getCalledValue());
4693 EVT Ty = Arg.getValueType();
4696 Res = DAG.getConstant(-1ULL, sdl, Ty);
4698 Res = DAG.getConstant(0, sdl, Ty);
4703 case Intrinsic::annotation:
4704 case Intrinsic::ptr_annotation:
4705 // Drop the intrinsic, but forward the value
4706 setValue(&I, getValue(I.getOperand(0)));
4708 case Intrinsic::assume:
4709 case Intrinsic::var_annotation:
4710 // Discard annotate attributes and assumptions
4713 case Intrinsic::init_trampoline: {
4714 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4718 Ops[1] = getValue(I.getArgOperand(0));
4719 Ops[2] = getValue(I.getArgOperand(1));
4720 Ops[3] = getValue(I.getArgOperand(2));
4721 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4722 Ops[5] = DAG.getSrcValue(F);
4724 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
4729 case Intrinsic::adjust_trampoline: {
4730 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
4732 getValue(I.getArgOperand(0))));
4735 case Intrinsic::gcroot:
4737 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
4738 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4740 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4741 GFI->addStackRoot(FI->getIndex(), TypeMap);
4744 case Intrinsic::gcread:
4745 case Intrinsic::gcwrite:
4746 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4747 case Intrinsic::flt_rounds:
4748 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
4751 case Intrinsic::expect: {
4752 // Just replace __builtin_expect(exp, c) with EXP.
4753 setValue(&I, getValue(I.getArgOperand(0)));
4757 case Intrinsic::debugtrap:
4758 case Intrinsic::trap: {
4759 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
4760 if (TrapFuncName.empty()) {
4761 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
4762 ISD::TRAP : ISD::DEBUGTRAP;
4763 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
4766 TargetLowering::ArgListTy Args;
4768 TargetLowering::CallLoweringInfo CLI(DAG);
4769 CLI.setDebugLoc(sdl).setChain(getRoot())
4770 .setCallee(CallingConv::C, I.getType(),
4771 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
4772 std::move(Args), 0);
4774 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
4775 DAG.setRoot(Result.second);
4779 case Intrinsic::uadd_with_overflow:
4780 case Intrinsic::sadd_with_overflow:
4781 case Intrinsic::usub_with_overflow:
4782 case Intrinsic::ssub_with_overflow:
4783 case Intrinsic::umul_with_overflow:
4784 case Intrinsic::smul_with_overflow: {
4786 switch (Intrinsic) {
4787 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4788 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
4789 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
4790 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
4791 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
4792 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
4793 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
4795 SDValue Op1 = getValue(I.getArgOperand(0));
4796 SDValue Op2 = getValue(I.getArgOperand(1));
4798 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
4799 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
4802 case Intrinsic::prefetch: {
4804 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4806 Ops[1] = getValue(I.getArgOperand(0));
4807 Ops[2] = getValue(I.getArgOperand(1));
4808 Ops[3] = getValue(I.getArgOperand(2));
4809 Ops[4] = getValue(I.getArgOperand(3));
4810 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
4811 DAG.getVTList(MVT::Other), Ops,
4812 EVT::getIntegerVT(*Context, 8),
4813 MachinePointerInfo(I.getArgOperand(0)),
4815 false, /* volatile */
4817 rw==1)); /* write */
4820 case Intrinsic::lifetime_start:
4821 case Intrinsic::lifetime_end: {
4822 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
4823 // Stack coloring is not enabled in O0, discard region information.
4824 if (TM.getOptLevel() == CodeGenOpt::None)
4827 SmallVector<Value *, 4> Allocas;
4828 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
4830 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
4831 E = Allocas.end(); Object != E; ++Object) {
4832 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
4834 // Could not find an Alloca.
4835 if (!LifetimeObject)
4838 // First check that the Alloca is static, otherwise it won't have a
4839 // valid frame index.
4840 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
4841 if (SI == FuncInfo.StaticAllocaMap.end())
4844 int FI = SI->second;
4848 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
4849 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
4851 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
4856 case Intrinsic::invariant_start:
4857 // Discard region information.
4858 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4860 case Intrinsic::invariant_end:
4861 // Discard region information.
4863 case Intrinsic::stackprotectorcheck: {
4864 // Do not actually emit anything for this basic block. Instead we initialize
4865 // the stack protector descriptor and export the guard variable so we can
4866 // access it in FinishBasicBlock.
4867 const BasicBlock *BB = I.getParent();
4868 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
4869 ExportFromCurrentBlock(SPDescriptor.getGuard());
4871 // Flush our exports since we are going to process a terminator.
4872 (void)getControlRoot();
4875 case Intrinsic::clear_cache:
4876 return TLI.getClearCacheBuiltinName();
4877 case Intrinsic::eh_actions:
4878 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4880 case Intrinsic::donothing:
4883 case Intrinsic::experimental_stackmap: {
4887 case Intrinsic::experimental_patchpoint_void:
4888 case Intrinsic::experimental_patchpoint_i64: {
4889 visitPatchpoint(&I);
4892 case Intrinsic::experimental_gc_statepoint: {
4896 case Intrinsic::experimental_gc_result_int:
4897 case Intrinsic::experimental_gc_result_float:
4898 case Intrinsic::experimental_gc_result_ptr:
4899 case Intrinsic::experimental_gc_result: {
4903 case Intrinsic::experimental_gc_relocate: {
4907 case Intrinsic::instrprof_increment:
4908 llvm_unreachable("instrprof failed to lower an increment");
4910 case Intrinsic::frameescape: {
4911 MachineFunction &MF = DAG.getMachineFunction();
4912 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4914 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
4915 // is the same on all targets.
4916 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
4917 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
4918 if (isa<ConstantPointerNull>(Arg))
4919 continue; // Skip null pointers. They represent a hole in index space.
4920 AllocaInst *Slot = cast<AllocaInst>(Arg);
4921 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
4922 "can only escape static allocas");
4923 int FI = FuncInfo.StaticAllocaMap[Slot];
4924 MCSymbol *FrameAllocSym =
4925 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4926 GlobalValue::getRealLinkageName(MF.getName()), Idx);
4927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
4928 TII->get(TargetOpcode::FRAME_ALLOC))
4929 .addSym(FrameAllocSym)
4936 case Intrinsic::framerecover: {
4937 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
4938 MachineFunction &MF = DAG.getMachineFunction();
4939 MVT PtrVT = TLI.getPointerTy(0);
4941 // Get the symbol that defines the frame offset.
4942 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
4943 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
4944 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
4945 MCSymbol *FrameAllocSym =
4946 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
4947 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
4949 // Create a TargetExternalSymbol for the label to avoid any target lowering
4950 // that would make this PC relative.
4951 StringRef Name = FrameAllocSym->getName();
4952 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
4953 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
4955 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
4957 // Add the offset to the FP.
4958 Value *FP = I.getArgOperand(1);
4959 SDValue FPVal = getValue(FP);
4960 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
4965 case Intrinsic::eh_begincatch:
4966 case Intrinsic::eh_endcatch:
4967 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
4968 case Intrinsic::eh_exceptioncode: {
4969 unsigned Reg = TLI.getExceptionPointerRegister();
4970 assert(Reg && "cannot get exception code on this platform");
4971 MVT PtrVT = TLI.getPointerTy();
4972 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
4973 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
4975 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
4976 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
4983 std::pair<SDValue, SDValue>
4984 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
4985 MachineBasicBlock *LandingPad) {
4986 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4987 MCSymbol *BeginLabel = nullptr;
4990 // Insert a label before the invoke call to mark the try range. This can be
4991 // used to detect deletion of the invoke via the MachineModuleInfo.
4992 BeginLabel = MMI.getContext().createTempSymbol();
4994 // For SjLj, keep track of which landing pads go with which invokes
4995 // so as to maintain the ordering of pads in the LSDA.
4996 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4997 if (CallSiteIndex) {
4998 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4999 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5001 // Now that the call site is handled, stop tracking it.
5002 MMI.setCurrentCallSite(0);
5005 // Both PendingLoads and PendingExports must be flushed here;
5006 // this call might not return.
5008 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5010 CLI.setChain(getRoot());
5012 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5013 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5015 assert((CLI.IsTailCall || Result.second.getNode()) &&
5016 "Non-null chain expected with non-tail call!");
5017 assert((Result.second.getNode() || !Result.first.getNode()) &&
5018 "Null value expected with tail call!");
5020 if (!Result.second.getNode()) {
5021 // As a special case, a null chain means that a tail call has been emitted
5022 // and the DAG root is already updated.
5025 // Since there's no actual continuation from this block, nothing can be
5026 // relying on us setting vregs for them.
5027 PendingExports.clear();
5029 DAG.setRoot(Result.second);
5033 // Insert a label at the end of the invoke call to mark the try range. This
5034 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5035 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5036 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5038 // Inform MachineModuleInfo of range.
5039 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5045 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5047 MachineBasicBlock *LandingPad) {
5048 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5049 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5050 Type *RetTy = FTy->getReturnType();
5052 TargetLowering::ArgListTy Args;
5053 TargetLowering::ArgListEntry Entry;
5054 Args.reserve(CS.arg_size());
5056 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5058 const Value *V = *i;
5061 if (V->getType()->isEmptyTy())
5064 SDValue ArgNode = getValue(V);
5065 Entry.Node = ArgNode; Entry.Ty = V->getType();
5067 // Skip the first return-type Attribute to get to params.
5068 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5069 Args.push_back(Entry);
5071 // If we have an explicit sret argument that is an Instruction, (i.e., it
5072 // might point to function-local memory), we can't meaningfully tail-call.
5073 if (Entry.isSRet && isa<Instruction>(V))
5077 // Check if target-independent constraints permit a tail call here.
5078 // Target-dependent constraints are checked within TLI->LowerCallTo.
5079 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5082 TargetLowering::CallLoweringInfo CLI(DAG);
5083 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5084 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5085 .setTailCall(isTailCall);
5086 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5088 if (Result.first.getNode())
5089 setValue(CS.getInstruction(), Result.first);
5092 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5093 /// value is equal or not-equal to zero.
5094 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5095 for (const User *U : V->users()) {
5096 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5097 if (IC->isEquality())
5098 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5099 if (C->isNullValue())
5101 // Unknown instruction.
5107 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5109 SelectionDAGBuilder &Builder) {
5111 // Check to see if this load can be trivially constant folded, e.g. if the
5112 // input is from a string literal.
5113 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5114 // Cast pointer to the type we really want to load.
5115 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5116 PointerType::getUnqual(LoadTy));
5118 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5119 const_cast<Constant *>(LoadInput), *Builder.DL))
5120 return Builder.getValue(LoadCst);
5123 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5124 // still constant memory, the input chain can be the entry node.
5126 bool ConstantMemory = false;
5128 // Do not serialize (non-volatile) loads of constant memory with anything.
5129 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5130 Root = Builder.DAG.getEntryNode();
5131 ConstantMemory = true;
5133 // Do not serialize non-volatile loads against each other.
5134 Root = Builder.DAG.getRoot();
5137 SDValue Ptr = Builder.getValue(PtrVal);
5138 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5139 Ptr, MachinePointerInfo(PtrVal),
5141 false /*nontemporal*/,
5142 false /*isinvariant*/, 1 /* align=1 */);
5144 if (!ConstantMemory)
5145 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5149 /// processIntegerCallValue - Record the value for an instruction that
5150 /// produces an integer result, converting the type where necessary.
5151 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5154 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5156 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5158 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5159 setValue(&I, Value);
5162 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5163 /// If so, return true and lower it, otherwise return false and it will be
5164 /// lowered like a normal call.
5165 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5166 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5167 if (I.getNumArgOperands() != 3)
5170 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5171 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5172 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5173 !I.getType()->isIntegerTy())
5176 const Value *Size = I.getArgOperand(2);
5177 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5178 if (CSize && CSize->getZExtValue() == 0) {
5179 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5180 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5184 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5185 std::pair<SDValue, SDValue> Res =
5186 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5187 getValue(LHS), getValue(RHS), getValue(Size),
5188 MachinePointerInfo(LHS),
5189 MachinePointerInfo(RHS));
5190 if (Res.first.getNode()) {
5191 processIntegerCallValue(I, Res.first, true);
5192 PendingLoads.push_back(Res.second);
5196 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5197 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5198 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5199 bool ActuallyDoIt = true;
5202 switch (CSize->getZExtValue()) {
5204 LoadVT = MVT::Other;
5206 ActuallyDoIt = false;
5210 LoadTy = Type::getInt16Ty(CSize->getContext());
5214 LoadTy = Type::getInt32Ty(CSize->getContext());
5218 LoadTy = Type::getInt64Ty(CSize->getContext());
5222 LoadVT = MVT::v4i32;
5223 LoadTy = Type::getInt32Ty(CSize->getContext());
5224 LoadTy = VectorType::get(LoadTy, 4);
5229 // This turns into unaligned loads. We only do this if the target natively
5230 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5231 // we'll only produce a small number of byte loads.
5233 // Require that we can find a legal MVT, and only do this if the target
5234 // supports unaligned loads of that type. Expanding into byte loads would
5236 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5237 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5238 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5239 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5240 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5241 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5242 // TODO: Check alignment of src and dest ptrs.
5243 if (!TLI.isTypeLegal(LoadVT) ||
5244 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5245 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5246 ActuallyDoIt = false;
5250 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5251 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5253 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5255 processIntegerCallValue(I, Res, false);
5264 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5265 /// form. If so, return true and lower it, otherwise return false and it
5266 /// will be lowered like a normal call.
5267 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5268 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5269 if (I.getNumArgOperands() != 3)
5272 const Value *Src = I.getArgOperand(0);
5273 const Value *Char = I.getArgOperand(1);
5274 const Value *Length = I.getArgOperand(2);
5275 if (!Src->getType()->isPointerTy() ||
5276 !Char->getType()->isIntegerTy() ||
5277 !Length->getType()->isIntegerTy() ||
5278 !I.getType()->isPointerTy())
5281 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5282 std::pair<SDValue, SDValue> Res =
5283 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5284 getValue(Src), getValue(Char), getValue(Length),
5285 MachinePointerInfo(Src));
5286 if (Res.first.getNode()) {
5287 setValue(&I, Res.first);
5288 PendingLoads.push_back(Res.second);
5295 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5296 /// optimized form. If so, return true and lower it, otherwise return false
5297 /// and it will be lowered like a normal call.
5298 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5299 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5300 if (I.getNumArgOperands() != 2)
5303 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5304 if (!Arg0->getType()->isPointerTy() ||
5305 !Arg1->getType()->isPointerTy() ||
5306 !I.getType()->isPointerTy())
5309 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5310 std::pair<SDValue, SDValue> Res =
5311 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5312 getValue(Arg0), getValue(Arg1),
5313 MachinePointerInfo(Arg0),
5314 MachinePointerInfo(Arg1), isStpcpy);
5315 if (Res.first.getNode()) {
5316 setValue(&I, Res.first);
5317 DAG.setRoot(Res.second);
5324 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5325 /// If so, return true and lower it, otherwise return false and it will be
5326 /// lowered like a normal call.
5327 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5328 // Verify that the prototype makes sense. int strcmp(void*,void*)
5329 if (I.getNumArgOperands() != 2)
5332 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5333 if (!Arg0->getType()->isPointerTy() ||
5334 !Arg1->getType()->isPointerTy() ||
5335 !I.getType()->isIntegerTy())
5338 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5339 std::pair<SDValue, SDValue> Res =
5340 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5341 getValue(Arg0), getValue(Arg1),
5342 MachinePointerInfo(Arg0),
5343 MachinePointerInfo(Arg1));
5344 if (Res.first.getNode()) {
5345 processIntegerCallValue(I, Res.first, true);
5346 PendingLoads.push_back(Res.second);
5353 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5354 /// form. If so, return true and lower it, otherwise return false and it
5355 /// will be lowered like a normal call.
5356 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5357 // Verify that the prototype makes sense. size_t strlen(char *)
5358 if (I.getNumArgOperands() != 1)
5361 const Value *Arg0 = I.getArgOperand(0);
5362 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5365 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5366 std::pair<SDValue, SDValue> Res =
5367 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5368 getValue(Arg0), MachinePointerInfo(Arg0));
5369 if (Res.first.getNode()) {
5370 processIntegerCallValue(I, Res.first, false);
5371 PendingLoads.push_back(Res.second);
5378 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5379 /// form. If so, return true and lower it, otherwise return false and it
5380 /// will be lowered like a normal call.
5381 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5382 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5383 if (I.getNumArgOperands() != 2)
5386 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5387 if (!Arg0->getType()->isPointerTy() ||
5388 !Arg1->getType()->isIntegerTy() ||
5389 !I.getType()->isIntegerTy())
5392 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5393 std::pair<SDValue, SDValue> Res =
5394 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5395 getValue(Arg0), getValue(Arg1),
5396 MachinePointerInfo(Arg0));
5397 if (Res.first.getNode()) {
5398 processIntegerCallValue(I, Res.first, false);
5399 PendingLoads.push_back(Res.second);
5406 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5407 /// operation (as expected), translate it to an SDNode with the specified opcode
5408 /// and return true.
5409 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5411 // Sanity check that it really is a unary floating-point call.
5412 if (I.getNumArgOperands() != 1 ||
5413 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5414 I.getType() != I.getArgOperand(0)->getType() ||
5415 !I.onlyReadsMemory())
5418 SDValue Tmp = getValue(I.getArgOperand(0));
5419 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5423 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5424 /// operation (as expected), translate it to an SDNode with the specified opcode
5425 /// and return true.
5426 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5428 // Sanity check that it really is a binary floating-point call.
5429 if (I.getNumArgOperands() != 2 ||
5430 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5431 I.getType() != I.getArgOperand(0)->getType() ||
5432 I.getType() != I.getArgOperand(1)->getType() ||
5433 !I.onlyReadsMemory())
5436 SDValue Tmp0 = getValue(I.getArgOperand(0));
5437 SDValue Tmp1 = getValue(I.getArgOperand(1));
5438 EVT VT = Tmp0.getValueType();
5439 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5443 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5444 // Handle inline assembly differently.
5445 if (isa<InlineAsm>(I.getCalledValue())) {
5450 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5451 ComputeUsesVAFloatArgument(I, &MMI);
5453 const char *RenameFn = nullptr;
5454 if (Function *F = I.getCalledFunction()) {
5455 if (F->isDeclaration()) {
5456 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5457 if (unsigned IID = II->getIntrinsicID(F)) {
5458 RenameFn = visitIntrinsicCall(I, IID);
5463 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5464 RenameFn = visitIntrinsicCall(I, IID);
5470 // Check for well-known libc/libm calls. If the function is internal, it
5471 // can't be a library call.
5473 if (!F->hasLocalLinkage() && F->hasName() &&
5474 LibInfo->getLibFunc(F->getName(), Func) &&
5475 LibInfo->hasOptimizedCodeGen(Func)) {
5478 case LibFunc::copysign:
5479 case LibFunc::copysignf:
5480 case LibFunc::copysignl:
5481 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5482 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5483 I.getType() == I.getArgOperand(0)->getType() &&
5484 I.getType() == I.getArgOperand(1)->getType() &&
5485 I.onlyReadsMemory()) {
5486 SDValue LHS = getValue(I.getArgOperand(0));
5487 SDValue RHS = getValue(I.getArgOperand(1));
5488 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5489 LHS.getValueType(), LHS, RHS));
5494 case LibFunc::fabsf:
5495 case LibFunc::fabsl:
5496 if (visitUnaryFloatCall(I, ISD::FABS))
5500 case LibFunc::fminf:
5501 case LibFunc::fminl:
5502 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5506 case LibFunc::fmaxf:
5507 case LibFunc::fmaxl:
5508 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5514 if (visitUnaryFloatCall(I, ISD::FSIN))
5520 if (visitUnaryFloatCall(I, ISD::FCOS))
5524 case LibFunc::sqrtf:
5525 case LibFunc::sqrtl:
5526 case LibFunc::sqrt_finite:
5527 case LibFunc::sqrtf_finite:
5528 case LibFunc::sqrtl_finite:
5529 if (visitUnaryFloatCall(I, ISD::FSQRT))
5532 case LibFunc::floor:
5533 case LibFunc::floorf:
5534 case LibFunc::floorl:
5535 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5538 case LibFunc::nearbyint:
5539 case LibFunc::nearbyintf:
5540 case LibFunc::nearbyintl:
5541 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5545 case LibFunc::ceilf:
5546 case LibFunc::ceill:
5547 if (visitUnaryFloatCall(I, ISD::FCEIL))
5551 case LibFunc::rintf:
5552 case LibFunc::rintl:
5553 if (visitUnaryFloatCall(I, ISD::FRINT))
5556 case LibFunc::round:
5557 case LibFunc::roundf:
5558 case LibFunc::roundl:
5559 if (visitUnaryFloatCall(I, ISD::FROUND))
5562 case LibFunc::trunc:
5563 case LibFunc::truncf:
5564 case LibFunc::truncl:
5565 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5569 case LibFunc::log2f:
5570 case LibFunc::log2l:
5571 if (visitUnaryFloatCall(I, ISD::FLOG2))
5575 case LibFunc::exp2f:
5576 case LibFunc::exp2l:
5577 if (visitUnaryFloatCall(I, ISD::FEXP2))
5580 case LibFunc::memcmp:
5581 if (visitMemCmpCall(I))
5584 case LibFunc::memchr:
5585 if (visitMemChrCall(I))
5588 case LibFunc::strcpy:
5589 if (visitStrCpyCall(I, false))
5592 case LibFunc::stpcpy:
5593 if (visitStrCpyCall(I, true))
5596 case LibFunc::strcmp:
5597 if (visitStrCmpCall(I))
5600 case LibFunc::strlen:
5601 if (visitStrLenCall(I))
5604 case LibFunc::strnlen:
5605 if (visitStrNLenCall(I))
5614 Callee = getValue(I.getCalledValue());
5616 Callee = DAG.getExternalSymbol(RenameFn,
5617 DAG.getTargetLoweringInfo().getPointerTy());
5619 // Check if we can potentially perform a tail call. More detailed checking is
5620 // be done within LowerCallTo, after more information about the call is known.
5621 LowerCallTo(&I, Callee, I.isTailCall());
5626 /// AsmOperandInfo - This contains information for each constraint that we are
5628 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5630 /// CallOperand - If this is the result output operand or a clobber
5631 /// this is null, otherwise it is the incoming operand to the CallInst.
5632 /// This gets modified as the asm is processed.
5633 SDValue CallOperand;
5635 /// AssignedRegs - If this is a register or register class operand, this
5636 /// contains the set of register corresponding to the operand.
5637 RegsForValue AssignedRegs;
5639 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5640 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5643 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5644 /// corresponds to. If there is no Value* for this operand, it returns
5646 EVT getCallOperandValEVT(LLVMContext &Context,
5647 const TargetLowering &TLI,
5648 const DataLayout *DL) const {
5649 if (!CallOperandVal) return MVT::Other;
5651 if (isa<BasicBlock>(CallOperandVal))
5652 return TLI.getPointerTy();
5654 llvm::Type *OpTy = CallOperandVal->getType();
5656 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5657 // If this is an indirect operand, the operand is a pointer to the
5660 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5662 report_fatal_error("Indirect operand for inline asm not a pointer!");
5663 OpTy = PtrTy->getElementType();
5666 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5667 if (StructType *STy = dyn_cast<StructType>(OpTy))
5668 if (STy->getNumElements() == 1)
5669 OpTy = STy->getElementType(0);
5671 // If OpTy is not a single value, it may be a struct/union that we
5672 // can tile with integers.
5673 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5674 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
5683 OpTy = IntegerType::get(Context, BitSize);
5688 return TLI.getValueType(OpTy, true);
5692 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5694 } // end anonymous namespace
5696 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5697 /// specified operand. We prefer to assign virtual registers, to allow the
5698 /// register allocator to handle the assignment process. However, if the asm
5699 /// uses features that we can't model on machineinstrs, we have SDISel do the
5700 /// allocation. This produces generally horrible, but correct, code.
5702 /// OpInfo describes the operand.
5704 static void GetRegistersForValue(SelectionDAG &DAG,
5705 const TargetLowering &TLI,
5707 SDISelAsmOperandInfo &OpInfo) {
5708 LLVMContext &Context = *DAG.getContext();
5710 MachineFunction &MF = DAG.getMachineFunction();
5711 SmallVector<unsigned, 4> Regs;
5713 // If this is a constraint for a single physreg, or a constraint for a
5714 // register class, find it.
5715 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
5716 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
5717 OpInfo.ConstraintCode,
5718 OpInfo.ConstraintVT);
5720 unsigned NumRegs = 1;
5721 if (OpInfo.ConstraintVT != MVT::Other) {
5722 // If this is a FP input in an integer register (or visa versa) insert a bit
5723 // cast of the input value. More generally, handle any case where the input
5724 // value disagrees with the register class we plan to stick this in.
5725 if (OpInfo.Type == InlineAsm::isInput &&
5726 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5727 // Try to convert to the first EVT that the reg class contains. If the
5728 // types are identical size, use a bitcast to convert (e.g. two differing
5730 MVT RegVT = *PhysReg.second->vt_begin();
5731 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
5732 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5733 RegVT, OpInfo.CallOperand);
5734 OpInfo.ConstraintVT = RegVT;
5735 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5736 // If the input is a FP value and we want it in FP registers, do a
5737 // bitcast to the corresponding integer type. This turns an f64 value
5738 // into i64, which can be passed with two i32 values on a 32-bit
5740 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
5741 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5742 RegVT, OpInfo.CallOperand);
5743 OpInfo.ConstraintVT = RegVT;
5747 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5751 EVT ValueVT = OpInfo.ConstraintVT;
5753 // If this is a constraint for a specific physical register, like {r17},
5755 if (unsigned AssignedReg = PhysReg.first) {
5756 const TargetRegisterClass *RC = PhysReg.second;
5757 if (OpInfo.ConstraintVT == MVT::Other)
5758 ValueVT = *RC->vt_begin();
5760 // Get the actual register value type. This is important, because the user
5761 // may have asked for (e.g.) the AX register in i32 type. We need to
5762 // remember that AX is actually i16 to get the right extension.
5763 RegVT = *RC->vt_begin();
5765 // This is a explicit reference to a physical register.
5766 Regs.push_back(AssignedReg);
5768 // If this is an expanded reference, add the rest of the regs to Regs.
5770 TargetRegisterClass::iterator I = RC->begin();
5771 for (; *I != AssignedReg; ++I)
5772 assert(I != RC->end() && "Didn't find reg!");
5774 // Already added the first reg.
5776 for (; NumRegs; --NumRegs, ++I) {
5777 assert(I != RC->end() && "Ran out of registers to allocate!");
5782 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5786 // Otherwise, if this was a reference to an LLVM register class, create vregs
5787 // for this reference.
5788 if (const TargetRegisterClass *RC = PhysReg.second) {
5789 RegVT = *RC->vt_begin();
5790 if (OpInfo.ConstraintVT == MVT::Other)
5793 // Create the appropriate number of virtual registers.
5794 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5795 for (; NumRegs; --NumRegs)
5796 Regs.push_back(RegInfo.createVirtualRegister(RC));
5798 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5802 // Otherwise, we couldn't allocate enough registers for this.
5805 /// visitInlineAsm - Handle a call to an InlineAsm object.
5807 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5808 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5810 /// ConstraintOperands - Information about all of the constraints.
5811 SDISelAsmOperandInfoVector ConstraintOperands;
5813 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5814 TargetLowering::AsmOperandInfoVector TargetConstraints =
5815 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
5817 bool hasMemory = false;
5819 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5820 unsigned ResNo = 0; // ResNo - The result number of the next output.
5821 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5822 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5823 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5825 MVT OpVT = MVT::Other;
5827 // Compute the value type for each operand.
5828 switch (OpInfo.Type) {
5829 case InlineAsm::isOutput:
5830 // Indirect outputs just consume an argument.
5831 if (OpInfo.isIndirect) {
5832 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5836 // The return value of the call is this value. As such, there is no
5837 // corresponding argument.
5838 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5839 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5840 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
5842 assert(ResNo == 0 && "Asm only has one result!");
5843 OpVT = TLI.getSimpleValueType(CS.getType());
5847 case InlineAsm::isInput:
5848 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5850 case InlineAsm::isClobber:
5855 // If this is an input or an indirect output, process the call argument.
5856 // BasicBlocks are labels, currently appearing only in asm's.
5857 if (OpInfo.CallOperandVal) {
5858 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5859 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5861 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5865 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
5868 OpInfo.ConstraintVT = OpVT;
5870 // Indirect operand accesses access memory.
5871 if (OpInfo.isIndirect)
5874 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5875 TargetLowering::ConstraintType
5876 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5877 if (CType == TargetLowering::C_Memory) {
5885 SDValue Chain, Flag;
5887 // We won't need to flush pending loads if this asm doesn't touch
5888 // memory and is nonvolatile.
5889 if (hasMemory || IA->hasSideEffects())
5892 Chain = DAG.getRoot();
5894 // Second pass over the constraints: compute which constraint option to use
5895 // and assign registers to constraints that want a specific physreg.
5896 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5897 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5899 // If this is an output operand with a matching input operand, look up the
5900 // matching input. If their types mismatch, e.g. one is an integer, the
5901 // other is floating point, or their sizes are different, flag it as an
5903 if (OpInfo.hasMatchingInput()) {
5904 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5906 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5907 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
5908 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
5909 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
5910 OpInfo.ConstraintVT);
5911 std::pair<unsigned, const TargetRegisterClass *> InputRC =
5912 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
5913 Input.ConstraintVT);
5914 if ((OpInfo.ConstraintVT.isInteger() !=
5915 Input.ConstraintVT.isInteger()) ||
5916 (MatchRC.second != InputRC.second)) {
5917 report_fatal_error("Unsupported asm: input constraint"
5918 " with a matching output constraint of"
5919 " incompatible type!");
5921 Input.ConstraintVT = OpInfo.ConstraintVT;
5925 // Compute the constraint code and ConstraintType to use.
5926 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5928 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5929 OpInfo.Type == InlineAsm::isClobber)
5932 // If this is a memory input, and if the operand is not indirect, do what we
5933 // need to to provide an address for the memory input.
5934 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5935 !OpInfo.isIndirect) {
5936 assert((OpInfo.isMultipleAlternative ||
5937 (OpInfo.Type == InlineAsm::isInput)) &&
5938 "Can only indirectify direct input operands!");
5940 // Memory operands really want the address of the value. If we don't have
5941 // an indirect input, put it in the constpool if we can, otherwise spill
5942 // it to a stack slot.
5943 // TODO: This isn't quite right. We need to handle these according to
5944 // the addressing mode that the constraint wants. Also, this may take
5945 // an additional register for the computation and we don't want that
5948 // If the operand is a float, integer, or vector constant, spill to a
5949 // constant pool entry to get its address.
5950 const Value *OpVal = OpInfo.CallOperandVal;
5951 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5952 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5953 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5954 TLI.getPointerTy());
5956 // Otherwise, create a stack slot and emit a store to it before the
5958 Type *Ty = OpVal->getType();
5959 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
5960 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
5961 MachineFunction &MF = DAG.getMachineFunction();
5962 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5963 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5964 Chain = DAG.getStore(Chain, getCurSDLoc(),
5965 OpInfo.CallOperand, StackSlot,
5966 MachinePointerInfo::getFixedStack(SSFI),
5968 OpInfo.CallOperand = StackSlot;
5971 // There is no longer a Value* corresponding to this operand.
5972 OpInfo.CallOperandVal = nullptr;
5974 // It is now an indirect operand.
5975 OpInfo.isIndirect = true;
5978 // If this constraint is for a specific register, allocate it before
5980 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5981 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5984 // Second pass - Loop over all of the operands, assigning virtual or physregs
5985 // to register class operands.
5986 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5987 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5989 // C_Register operands have already been allocated, Other/Memory don't need
5991 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5992 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
5995 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5996 std::vector<SDValue> AsmNodeOperands;
5997 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5998 AsmNodeOperands.push_back(
5999 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6000 TLI.getPointerTy()));
6002 // If we have a !srcloc metadata node associated with it, we want to attach
6003 // this to the ultimately generated inline asm machineinstr. To do this, we
6004 // pass in the third operand as this (potentially null) inline asm MDNode.
6005 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6006 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6008 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6009 // bits as operand 3.
6010 unsigned ExtraInfo = 0;
6011 if (IA->hasSideEffects())
6012 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6013 if (IA->isAlignStack())
6014 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6015 // Set the asm dialect.
6016 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6018 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6019 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6020 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6022 // Compute the constraint code and ConstraintType to use.
6023 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6025 // Ideally, we would only check against memory constraints. However, the
6026 // meaning of an other constraint can be target-specific and we can't easily
6027 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6028 // for other constriants as well.
6029 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6030 OpInfo.ConstraintType == TargetLowering::C_Other) {
6031 if (OpInfo.Type == InlineAsm::isInput)
6032 ExtraInfo |= InlineAsm::Extra_MayLoad;
6033 else if (OpInfo.Type == InlineAsm::isOutput)
6034 ExtraInfo |= InlineAsm::Extra_MayStore;
6035 else if (OpInfo.Type == InlineAsm::isClobber)
6036 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6040 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, getCurSDLoc(),
6041 TLI.getPointerTy()));
6043 // Loop over all of the inputs, copying the operand values into the
6044 // appropriate registers and processing the output regs.
6045 RegsForValue RetValRegs;
6047 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6048 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6050 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6051 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6053 switch (OpInfo.Type) {
6054 case InlineAsm::isOutput: {
6055 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6056 OpInfo.ConstraintType != TargetLowering::C_Register) {
6057 // Memory output, or 'other' output (e.g. 'X' constraint).
6058 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6060 unsigned ConstraintID =
6061 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6062 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6063 "Failed to convert memory constraint code to constraint id.");
6065 // Add information to the INLINEASM node to know about this output.
6066 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6067 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6068 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6070 AsmNodeOperands.push_back(OpInfo.CallOperand);
6074 // Otherwise, this is a register or register class output.
6076 // Copy the output from the appropriate register. Find a register that
6078 if (OpInfo.AssignedRegs.Regs.empty()) {
6079 LLVMContext &Ctx = *DAG.getContext();
6080 Ctx.emitError(CS.getInstruction(),
6081 "couldn't allocate output register for constraint '" +
6082 Twine(OpInfo.ConstraintCode) + "'");
6086 // If this is an indirect operand, store through the pointer after the
6088 if (OpInfo.isIndirect) {
6089 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6090 OpInfo.CallOperandVal));
6092 // This is the result value of the call.
6093 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6094 // Concatenate this output onto the outputs list.
6095 RetValRegs.append(OpInfo.AssignedRegs);
6098 // Add information to the INLINEASM node to know that this register is
6101 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6102 ? InlineAsm::Kind_RegDefEarlyClobber
6103 : InlineAsm::Kind_RegDef,
6104 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6107 case InlineAsm::isInput: {
6108 SDValue InOperandVal = OpInfo.CallOperand;
6110 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6111 // If this is required to match an output register we have already set,
6112 // just use its register.
6113 unsigned OperandNo = OpInfo.getMatchedOperand();
6115 // Scan until we find the definition we already emitted of this operand.
6116 // When we find it, create a RegsForValue operand.
6117 unsigned CurOp = InlineAsm::Op_FirstOperand;
6118 for (; OperandNo; --OperandNo) {
6119 // Advance to the next operand.
6121 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6122 assert((InlineAsm::isRegDefKind(OpFlag) ||
6123 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6124 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6125 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6129 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6130 if (InlineAsm::isRegDefKind(OpFlag) ||
6131 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6132 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6133 if (OpInfo.isIndirect) {
6134 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6135 LLVMContext &Ctx = *DAG.getContext();
6136 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6137 " don't know how to handle tied "
6138 "indirect register inputs");
6142 RegsForValue MatchedRegs;
6143 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6144 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6145 MatchedRegs.RegVTs.push_back(RegVT);
6146 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6147 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6149 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6150 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6152 LLVMContext &Ctx = *DAG.getContext();
6153 Ctx.emitError(CS.getInstruction(),
6154 "inline asm error: This value"
6155 " type register class is not natively supported!");
6159 SDLoc dl = getCurSDLoc();
6160 // Use the produced MatchedRegs object to
6161 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6162 Chain, &Flag, CS.getInstruction());
6163 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6164 true, OpInfo.getMatchedOperand(), dl,
6165 DAG, AsmNodeOperands);
6169 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6170 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6171 "Unexpected number of operands");
6172 // Add information to the INLINEASM node to know about this input.
6173 // See InlineAsm.h isUseOperandTiedToDef.
6174 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6175 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6176 OpInfo.getMatchedOperand());
6177 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, getCurSDLoc(),
6178 TLI.getPointerTy()));
6179 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6183 // Treat indirect 'X' constraint as memory.
6184 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6186 OpInfo.ConstraintType = TargetLowering::C_Memory;
6188 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6189 std::vector<SDValue> Ops;
6190 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6193 LLVMContext &Ctx = *DAG.getContext();
6194 Ctx.emitError(CS.getInstruction(),
6195 "invalid operand for inline asm constraint '" +
6196 Twine(OpInfo.ConstraintCode) + "'");
6200 // Add information to the INLINEASM node to know about this input.
6201 unsigned ResOpType =
6202 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6203 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6205 TLI.getPointerTy()));
6206 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6210 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6211 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6212 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6213 "Memory operands expect pointer values");
6215 unsigned ConstraintID =
6216 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6217 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6218 "Failed to convert memory constraint code to constraint id.");
6220 // Add information to the INLINEASM node to know about this input.
6221 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6222 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6223 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6226 AsmNodeOperands.push_back(InOperandVal);
6230 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6231 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6232 "Unknown constraint type!");
6234 // TODO: Support this.
6235 if (OpInfo.isIndirect) {
6236 LLVMContext &Ctx = *DAG.getContext();
6237 Ctx.emitError(CS.getInstruction(),
6238 "Don't know how to handle indirect register inputs yet "
6239 "for constraint '" +
6240 Twine(OpInfo.ConstraintCode) + "'");
6244 // Copy the input into the appropriate registers.
6245 if (OpInfo.AssignedRegs.Regs.empty()) {
6246 LLVMContext &Ctx = *DAG.getContext();
6247 Ctx.emitError(CS.getInstruction(),
6248 "couldn't allocate input reg for constraint '" +
6249 Twine(OpInfo.ConstraintCode) + "'");
6253 SDLoc dl = getCurSDLoc();
6255 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6256 Chain, &Flag, CS.getInstruction());
6258 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6259 dl, DAG, AsmNodeOperands);
6262 case InlineAsm::isClobber: {
6263 // Add the clobbered value to the operand list, so that the register
6264 // allocator is aware that the physreg got clobbered.
6265 if (!OpInfo.AssignedRegs.Regs.empty())
6266 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6267 false, 0, getCurSDLoc(), DAG,
6274 // Finish up input operands. Set the input chain and add the flag last.
6275 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6276 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6278 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6279 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6280 Flag = Chain.getValue(1);
6282 // If this asm returns a register value, copy the result from that register
6283 // and set it as the value of the call.
6284 if (!RetValRegs.Regs.empty()) {
6285 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6286 Chain, &Flag, CS.getInstruction());
6288 // FIXME: Why don't we do this for inline asms with MRVs?
6289 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6290 EVT ResultType = TLI.getValueType(CS.getType());
6292 // If any of the results of the inline asm is a vector, it may have the
6293 // wrong width/num elts. This can happen for register classes that can
6294 // contain multiple different value types. The preg or vreg allocated may
6295 // not have the same VT as was expected. Convert it to the right type
6296 // with bit_convert.
6297 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6298 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6301 } else if (ResultType != Val.getValueType() &&
6302 ResultType.isInteger() && Val.getValueType().isInteger()) {
6303 // If a result value was tied to an input value, the computed result may
6304 // have a wider width than the expected result. Extract the relevant
6306 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6309 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6312 setValue(CS.getInstruction(), Val);
6313 // Don't need to use this as a chain in this case.
6314 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6318 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6320 // Process indirect outputs, first output all of the flagged copies out of
6322 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6323 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6324 const Value *Ptr = IndirectStoresToEmit[i].second;
6325 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6327 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6330 // Emit the non-flagged stores from the physregs.
6331 SmallVector<SDValue, 8> OutChains;
6332 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6333 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6334 StoresToEmit[i].first,
6335 getValue(StoresToEmit[i].second),
6336 MachinePointerInfo(StoresToEmit[i].second),
6338 OutChains.push_back(Val);
6341 if (!OutChains.empty())
6342 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6347 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6348 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6349 MVT::Other, getRoot(),
6350 getValue(I.getArgOperand(0)),
6351 DAG.getSrcValue(I.getArgOperand(0))));
6354 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6355 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6356 const DataLayout &DL = *TLI.getDataLayout();
6357 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6358 getRoot(), getValue(I.getOperand(0)),
6359 DAG.getSrcValue(I.getOperand(0)),
6360 DL.getABITypeAlignment(I.getType()));
6362 DAG.setRoot(V.getValue(1));
6365 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6366 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6367 MVT::Other, getRoot(),
6368 getValue(I.getArgOperand(0)),
6369 DAG.getSrcValue(I.getArgOperand(0))));
6372 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6373 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6374 MVT::Other, getRoot(),
6375 getValue(I.getArgOperand(0)),
6376 getValue(I.getArgOperand(1)),
6377 DAG.getSrcValue(I.getArgOperand(0)),
6378 DAG.getSrcValue(I.getArgOperand(1))));
6381 /// \brief Lower an argument list according to the target calling convention.
6383 /// \return A tuple of <return-value, token-chain>
6385 /// This is a helper for lowering intrinsics that follow a target calling
6386 /// convention or require stack pointer adjustment. Only a subset of the
6387 /// intrinsic's operands need to participate in the calling convention.
6388 std::pair<SDValue, SDValue>
6389 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6390 unsigned NumArgs, SDValue Callee,
6392 MachineBasicBlock *LandingPad,
6393 bool IsPatchPoint) {
6394 TargetLowering::ArgListTy Args;
6395 Args.reserve(NumArgs);
6397 // Populate the argument list.
6398 // Attributes for args start at offset 1, after the return attribute.
6399 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6400 ArgI != ArgE; ++ArgI) {
6401 const Value *V = CS->getOperand(ArgI);
6403 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6405 TargetLowering::ArgListEntry Entry;
6406 Entry.Node = getValue(V);
6407 Entry.Ty = V->getType();
6408 Entry.setAttributes(&CS, AttrI);
6409 Args.push_back(Entry);
6412 TargetLowering::CallLoweringInfo CLI(DAG);
6413 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6414 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6415 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6417 return lowerInvokable(CLI, LandingPad);
6420 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6421 /// or patchpoint target node's operand list.
6423 /// Constants are converted to TargetConstants purely as an optimization to
6424 /// avoid constant materialization and register allocation.
6426 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6427 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6428 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6429 /// address materialization and register allocation, but may also be required
6430 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6431 /// alloca in the entry block, then the runtime may assume that the alloca's
6432 /// StackMap location can be read immediately after compilation and that the
6433 /// location is valid at any point during execution (this is similar to the
6434 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6435 /// only available in a register, then the runtime would need to trap when
6436 /// execution reaches the StackMap in order to read the alloca's location.
6437 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6438 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6439 SelectionDAGBuilder &Builder) {
6440 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6441 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6442 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6444 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6446 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6447 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6448 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6450 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6452 Ops.push_back(OpVal);
6456 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6457 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6458 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6459 // [live variables...])
6461 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6463 SDValue Chain, InFlag, Callee, NullPtr;
6464 SmallVector<SDValue, 32> Ops;
6466 SDLoc DL = getCurSDLoc();
6467 Callee = getValue(CI.getCalledValue());
6468 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6470 // The stackmap intrinsic only records the live variables (the arguemnts
6471 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6472 // intrinsic, this won't be lowered to a function call. This means we don't
6473 // have to worry about calling conventions and target specific lowering code.
6474 // Instead we perform the call lowering right here.
6476 // chain, flag = CALLSEQ_START(chain, 0)
6477 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6478 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6480 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6481 InFlag = Chain.getValue(1);
6483 // Add the <id> and <numBytes> constants.
6484 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6485 Ops.push_back(DAG.getTargetConstant(
6486 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6487 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6488 Ops.push_back(DAG.getTargetConstant(
6489 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6492 // Push live variables for the stack map.
6493 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6495 // We are not pushing any register mask info here on the operands list,
6496 // because the stackmap doesn't clobber anything.
6498 // Push the chain and the glue flag.
6499 Ops.push_back(Chain);
6500 Ops.push_back(InFlag);
6502 // Create the STACKMAP node.
6503 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6504 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6505 Chain = SDValue(SM, 0);
6506 InFlag = Chain.getValue(1);
6508 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6510 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6512 // Set the root to the target-lowered call chain.
6515 // Inform the Frame Information that we have a stackmap in this function.
6516 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6519 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6520 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6521 MachineBasicBlock *LandingPad) {
6522 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6527 // [live variables...])
6529 CallingConv::ID CC = CS.getCallingConv();
6530 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6531 bool HasDef = !CS->getType()->isVoidTy();
6532 SDLoc dl = getCurSDLoc();
6533 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6535 // Handle immediate and symbolic callees.
6536 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6537 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6539 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6540 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6541 SDLoc(SymbolicCallee),
6542 SymbolicCallee->getValueType(0));
6544 // Get the real number of arguments participating in the call <numArgs>
6545 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6546 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6548 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6549 // Intrinsics include all meta-operands up to but not including CC.
6550 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6551 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6552 "Not enough arguments provided to the patchpoint intrinsic");
6554 // For AnyRegCC the arguments are lowered later on manually.
6555 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6557 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6558 std::pair<SDValue, SDValue> Result =
6559 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy,
6562 SDNode *CallEnd = Result.second.getNode();
6563 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6564 CallEnd = CallEnd->getOperand(0).getNode();
6566 /// Get a call instruction from the call sequence chain.
6567 /// Tail calls are not allowed.
6568 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6569 "Expected a callseq node.");
6570 SDNode *Call = CallEnd->getOperand(0).getNode();
6571 bool HasGlue = Call->getGluedNode();
6573 // Replace the target specific call node with the patchable intrinsic.
6574 SmallVector<SDValue, 8> Ops;
6576 // Add the <id> and <numBytes> constants.
6577 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6578 Ops.push_back(DAG.getTargetConstant(
6579 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6580 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6581 Ops.push_back(DAG.getTargetConstant(
6582 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6586 Ops.push_back(Callee);
6588 // Adjust <numArgs> to account for any arguments that have been passed on the
6590 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6591 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6592 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6593 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6595 // Add the calling convention
6596 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6598 // Add the arguments we omitted previously. The register allocator should
6599 // place these in any free register.
6601 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6602 Ops.push_back(getValue(CS.getArgument(i)));
6604 // Push the arguments from the call instruction up to the register mask.
6605 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6606 Ops.append(Call->op_begin() + 2, e);
6608 // Push live variables for the stack map.
6609 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6611 // Push the register mask info.
6613 Ops.push_back(*(Call->op_end()-2));
6615 Ops.push_back(*(Call->op_end()-1));
6617 // Push the chain (this is originally the first operand of the call, but
6618 // becomes now the last or second to last operand).
6619 Ops.push_back(*(Call->op_begin()));
6621 // Push the glue flag (last operand).
6623 Ops.push_back(*(Call->op_end()-1));
6626 if (IsAnyRegCC && HasDef) {
6627 // Create the return types based on the intrinsic definition
6628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6629 SmallVector<EVT, 3> ValueVTs;
6630 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
6631 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6633 // There is always a chain and a glue type at the end
6634 ValueVTs.push_back(MVT::Other);
6635 ValueVTs.push_back(MVT::Glue);
6636 NodeTys = DAG.getVTList(ValueVTs);
6638 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6640 // Replace the target specific call node with a PATCHPOINT node.
6641 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6644 // Update the NodeMap.
6647 setValue(CS.getInstruction(), SDValue(MN, 0));
6649 setValue(CS.getInstruction(), Result.first);
6652 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6653 // call sequence. Furthermore the location of the chain and glue can change
6654 // when the AnyReg calling convention is used and the intrinsic returns a
6656 if (IsAnyRegCC && HasDef) {
6657 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6658 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6659 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6661 DAG.ReplaceAllUsesWith(Call, MN);
6662 DAG.DeleteNode(Call);
6664 // Inform the Frame Information that we have a patchpoint in this function.
6665 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6668 /// Returns an AttributeSet representing the attributes applied to the return
6669 /// value of the given call.
6670 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6671 SmallVector<Attribute::AttrKind, 2> Attrs;
6673 Attrs.push_back(Attribute::SExt);
6675 Attrs.push_back(Attribute::ZExt);
6677 Attrs.push_back(Attribute::InReg);
6679 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6683 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6684 /// implementation, which just calls LowerCall.
6685 /// FIXME: When all targets are
6686 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6687 std::pair<SDValue, SDValue>
6688 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6689 // Handle the incoming return values from the call.
6691 Type *OrigRetTy = CLI.RetTy;
6692 SmallVector<EVT, 4> RetTys;
6693 SmallVector<uint64_t, 4> Offsets;
6694 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
6696 SmallVector<ISD::OutputArg, 4> Outs;
6697 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
6699 bool CanLowerReturn =
6700 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6701 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6703 SDValue DemoteStackSlot;
6704 int DemoteStackIdx = -100;
6705 if (!CanLowerReturn) {
6706 // FIXME: equivalent assert?
6707 // assert(!CS.hasInAllocaArgument() &&
6708 // "sret demotion is incompatible with inalloca");
6709 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
6710 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
6711 MachineFunction &MF = CLI.DAG.getMachineFunction();
6712 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6713 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6715 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
6717 Entry.Node = DemoteStackSlot;
6718 Entry.Ty = StackSlotPtrType;
6719 Entry.isSExt = false;
6720 Entry.isZExt = false;
6721 Entry.isInReg = false;
6722 Entry.isSRet = true;
6723 Entry.isNest = false;
6724 Entry.isByVal = false;
6725 Entry.isReturned = false;
6726 Entry.Alignment = Align;
6727 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
6728 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
6730 // sret demotion isn't compatible with tail-calls, since the sret argument
6731 // points into the callers stack frame.
6732 CLI.IsTailCall = false;
6734 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6736 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6737 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6738 for (unsigned i = 0; i != NumRegs; ++i) {
6739 ISD::InputArg MyFlags;
6740 MyFlags.VT = RegisterVT;
6742 MyFlags.Used = CLI.IsReturnValueUsed;
6744 MyFlags.Flags.setSExt();
6746 MyFlags.Flags.setZExt();
6748 MyFlags.Flags.setInReg();
6749 CLI.Ins.push_back(MyFlags);
6754 // Handle all of the outgoing arguments.
6756 CLI.OutVals.clear();
6757 ArgListTy &Args = CLI.getArgs();
6758 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6759 SmallVector<EVT, 4> ValueVTs;
6760 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6761 Type *FinalType = Args[i].Ty;
6762 if (Args[i].isByVal)
6763 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
6764 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
6765 FinalType, CLI.CallConv, CLI.IsVarArg);
6766 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
6768 EVT VT = ValueVTs[Value];
6769 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
6770 SDValue Op = SDValue(Args[i].Node.getNode(),
6771 Args[i].Node.getResNo() + Value);
6772 ISD::ArgFlagsTy Flags;
6773 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
6779 if (Args[i].isInReg)
6783 if (Args[i].isByVal)
6785 if (Args[i].isInAlloca) {
6786 Flags.setInAlloca();
6787 // Set the byval flag for CCAssignFn callbacks that don't know about
6788 // inalloca. This way we can know how many bytes we should've allocated
6789 // and how many bytes a callee cleanup function will pop. If we port
6790 // inalloca to more targets, we'll have to add custom inalloca handling
6791 // in the various CC lowering callbacks.
6794 if (Args[i].isByVal || Args[i].isInAlloca) {
6795 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6796 Type *ElementTy = Ty->getElementType();
6797 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
6798 // For ByVal, alignment should come from FE. BE will guess if this
6799 // info is not there but there are cases it cannot get right.
6800 unsigned FrameAlign;
6801 if (Args[i].Alignment)
6802 FrameAlign = Args[i].Alignment;
6804 FrameAlign = getByValTypeAlignment(ElementTy);
6805 Flags.setByValAlign(FrameAlign);
6810 Flags.setInConsecutiveRegs();
6811 Flags.setOrigAlign(OriginalAlignment);
6813 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
6814 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
6815 SmallVector<SDValue, 4> Parts(NumParts);
6816 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6819 ExtendKind = ISD::SIGN_EXTEND;
6820 else if (Args[i].isZExt)
6821 ExtendKind = ISD::ZERO_EXTEND;
6823 // Conservatively only handle 'returned' on non-vectors for now
6824 if (Args[i].isReturned && !Op.getValueType().isVector()) {
6825 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
6826 "unexpected use of 'returned'");
6827 // Before passing 'returned' to the target lowering code, ensure that
6828 // either the register MVT and the actual EVT are the same size or that
6829 // the return value and argument are extended in the same way; in these
6830 // cases it's safe to pass the argument register value unchanged as the
6831 // return register value (although it's at the target's option whether
6833 // TODO: allow code generation to take advantage of partially preserved
6834 // registers rather than clobbering the entire register when the
6835 // parameter extension method is not compatible with the return
6837 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
6838 (ExtendKind != ISD::ANY_EXTEND &&
6839 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
6840 Flags.setReturned();
6843 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
6844 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
6846 for (unsigned j = 0; j != NumParts; ++j) {
6847 // if it isn't first piece, alignment must be 1
6848 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
6849 i < CLI.NumFixedArgs,
6850 i, j*Parts[j].getValueType().getStoreSize());
6851 if (NumParts > 1 && j == 0)
6852 MyFlags.Flags.setSplit();
6854 MyFlags.Flags.setOrigAlign(1);
6856 CLI.Outs.push_back(MyFlags);
6857 CLI.OutVals.push_back(Parts[j]);
6860 if (NeedsRegBlock && Value == NumValues - 1)
6861 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
6865 SmallVector<SDValue, 4> InVals;
6866 CLI.Chain = LowerCall(CLI, InVals);
6868 // Verify that the target's LowerCall behaved as expected.
6869 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
6870 "LowerCall didn't return a valid chain!");
6871 assert((!CLI.IsTailCall || InVals.empty()) &&
6872 "LowerCall emitted a return value for a tail call!");
6873 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
6874 "LowerCall didn't emit the correct number of values!");
6876 // For a tail call, the return value is merely live-out and there aren't
6877 // any nodes in the DAG representing it. Return a special value to
6878 // indicate that a tail call has been emitted and no more Instructions
6879 // should be processed in the current block.
6880 if (CLI.IsTailCall) {
6881 CLI.DAG.setRoot(CLI.Chain);
6882 return std::make_pair(SDValue(), SDValue());
6885 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
6886 assert(InVals[i].getNode() &&
6887 "LowerCall emitted a null value!");
6888 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
6889 "LowerCall emitted a value with the wrong type!");
6892 SmallVector<SDValue, 4> ReturnValues;
6893 if (!CanLowerReturn) {
6894 // The instruction result is the result of loading from the
6895 // hidden sret parameter.
6896 SmallVector<EVT, 1> PVTs;
6897 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
6899 ComputeValueVTs(*this, PtrRetTy, PVTs);
6900 assert(PVTs.size() == 1 && "Pointers should fit in one register");
6901 EVT PtrVT = PVTs[0];
6903 unsigned NumValues = RetTys.size();
6904 ReturnValues.resize(NumValues);
6905 SmallVector<SDValue, 4> Chains(NumValues);
6907 for (unsigned i = 0; i < NumValues; ++i) {
6908 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
6909 CLI.DAG.getConstant(Offsets[i], CLI.DL,
6911 SDValue L = CLI.DAG.getLoad(
6912 RetTys[i], CLI.DL, CLI.Chain, Add,
6913 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
6915 ReturnValues[i] = L;
6916 Chains[i] = L.getValue(1);
6919 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
6921 // Collect the legal value parts into potentially illegal values
6922 // that correspond to the original function's return values.
6923 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6925 AssertOp = ISD::AssertSext;
6926 else if (CLI.RetZExt)
6927 AssertOp = ISD::AssertZext;
6928 unsigned CurReg = 0;
6929 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6931 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
6932 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
6934 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
6935 NumRegs, RegisterVT, VT, nullptr,
6940 // For a function returning void, there is no return value. We can't create
6941 // such a node, so we just return a null return value in that case. In
6942 // that case, nothing will actually look at the value.
6943 if (ReturnValues.empty())
6944 return std::make_pair(SDValue(), CLI.Chain);
6947 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
6948 CLI.DAG.getVTList(RetTys), ReturnValues);
6949 return std::make_pair(Res, CLI.Chain);
6952 void TargetLowering::LowerOperationWrapper(SDNode *N,
6953 SmallVectorImpl<SDValue> &Results,
6954 SelectionDAG &DAG) const {
6955 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6957 Results.push_back(Res);
6960 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6961 llvm_unreachable("LowerOperation not implemented for this target!");
6965 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6966 SDValue Op = getNonRegisterValue(V);
6967 assert((Op.getOpcode() != ISD::CopyFromReg ||
6968 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6969 "Copy from a reg to the same reg!");
6970 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6973 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6974 SDValue Chain = DAG.getEntryNode();
6976 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
6977 FuncInfo.PreferredExtendType.end())
6979 : FuncInfo.PreferredExtendType[V];
6980 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
6981 PendingExports.push_back(Chain);
6984 #include "llvm/CodeGen/SelectionDAGISel.h"
6986 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6987 /// entry block, return true. This includes arguments used by switches, since
6988 /// the switch may expand into multiple basic blocks.
6989 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6990 // With FastISel active, we may be splitting blocks, so force creation
6991 // of virtual registers for all non-dead arguments.
6993 return A->use_empty();
6995 const BasicBlock *Entry = A->getParent()->begin();
6996 for (const User *U : A->users())
6997 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6998 return false; // Use not in entry block.
7003 void SelectionDAGISel::LowerArguments(const Function &F) {
7004 SelectionDAG &DAG = SDB->DAG;
7005 SDLoc dl = SDB->getCurSDLoc();
7006 const DataLayout *DL = TLI->getDataLayout();
7007 SmallVector<ISD::InputArg, 16> Ins;
7009 if (!FuncInfo->CanLowerReturn) {
7010 // Put in an sret pointer parameter before all the other parameters.
7011 SmallVector<EVT, 1> ValueVTs;
7012 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7014 // NOTE: Assuming that a pointer will never break down to more than one VT
7016 ISD::ArgFlagsTy Flags;
7018 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7019 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7020 ISD::InputArg::NoArgIndex, 0);
7021 Ins.push_back(RetArg);
7024 // Set up the incoming argument description vector.
7026 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7027 I != E; ++I, ++Idx) {
7028 SmallVector<EVT, 4> ValueVTs;
7029 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7030 bool isArgValueUsed = !I->use_empty();
7031 unsigned PartBase = 0;
7032 Type *FinalType = I->getType();
7033 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7034 FinalType = cast<PointerType>(FinalType)->getElementType();
7035 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7036 FinalType, F.getCallingConv(), F.isVarArg());
7037 for (unsigned Value = 0, NumValues = ValueVTs.size();
7038 Value != NumValues; ++Value) {
7039 EVT VT = ValueVTs[Value];
7040 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7041 ISD::ArgFlagsTy Flags;
7042 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7044 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7046 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7048 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7050 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7052 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7054 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7055 Flags.setInAlloca();
7056 // Set the byval flag for CCAssignFn callbacks that don't know about
7057 // inalloca. This way we can know how many bytes we should've allocated
7058 // and how many bytes a callee cleanup function will pop. If we port
7059 // inalloca to more targets, we'll have to add custom inalloca handling
7060 // in the various CC lowering callbacks.
7063 if (Flags.isByVal() || Flags.isInAlloca()) {
7064 PointerType *Ty = cast<PointerType>(I->getType());
7065 Type *ElementTy = Ty->getElementType();
7066 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7067 // For ByVal, alignment should be passed from FE. BE will guess if
7068 // this info is not there but there are cases it cannot get right.
7069 unsigned FrameAlign;
7070 if (F.getParamAlignment(Idx))
7071 FrameAlign = F.getParamAlignment(Idx);
7073 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7074 Flags.setByValAlign(FrameAlign);
7076 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7079 Flags.setInConsecutiveRegs();
7080 Flags.setOrigAlign(OriginalAlignment);
7082 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7083 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7084 for (unsigned i = 0; i != NumRegs; ++i) {
7085 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7086 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7087 if (NumRegs > 1 && i == 0)
7088 MyFlags.Flags.setSplit();
7089 // if it isn't first piece, alignment must be 1
7091 MyFlags.Flags.setOrigAlign(1);
7092 Ins.push_back(MyFlags);
7094 if (NeedsRegBlock && Value == NumValues - 1)
7095 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7096 PartBase += VT.getStoreSize();
7100 // Call the target to set up the argument values.
7101 SmallVector<SDValue, 8> InVals;
7102 SDValue NewRoot = TLI->LowerFormalArguments(
7103 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7105 // Verify that the target's LowerFormalArguments behaved as expected.
7106 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7107 "LowerFormalArguments didn't return a valid chain!");
7108 assert(InVals.size() == Ins.size() &&
7109 "LowerFormalArguments didn't emit the correct number of values!");
7111 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7112 assert(InVals[i].getNode() &&
7113 "LowerFormalArguments emitted a null value!");
7114 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7115 "LowerFormalArguments emitted a value with the wrong type!");
7119 // Update the DAG with the new chain value resulting from argument lowering.
7120 DAG.setRoot(NewRoot);
7122 // Set up the argument values.
7125 if (!FuncInfo->CanLowerReturn) {
7126 // Create a virtual register for the sret pointer, and put in a copy
7127 // from the sret argument into it.
7128 SmallVector<EVT, 1> ValueVTs;
7129 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7130 MVT VT = ValueVTs[0].getSimpleVT();
7131 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7132 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7133 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7134 RegVT, VT, nullptr, AssertOp);
7136 MachineFunction& MF = SDB->DAG.getMachineFunction();
7137 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7138 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7139 FuncInfo->DemoteRegister = SRetReg;
7141 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7142 DAG.setRoot(NewRoot);
7144 // i indexes lowered arguments. Bump it past the hidden sret argument.
7145 // Idx indexes LLVM arguments. Don't touch it.
7149 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7151 SmallVector<SDValue, 4> ArgValues;
7152 SmallVector<EVT, 4> ValueVTs;
7153 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7154 unsigned NumValues = ValueVTs.size();
7156 // If this argument is unused then remember its value. It is used to generate
7157 // debugging information.
7158 if (I->use_empty() && NumValues) {
7159 SDB->setUnusedArgValue(I, InVals[i]);
7161 // Also remember any frame index for use in FastISel.
7162 if (FrameIndexSDNode *FI =
7163 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7164 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7167 for (unsigned Val = 0; Val != NumValues; ++Val) {
7168 EVT VT = ValueVTs[Val];
7169 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7170 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7172 if (!I->use_empty()) {
7173 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7174 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7175 AssertOp = ISD::AssertSext;
7176 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7177 AssertOp = ISD::AssertZext;
7179 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7180 NumParts, PartVT, VT,
7181 nullptr, AssertOp));
7187 // We don't need to do anything else for unused arguments.
7188 if (ArgValues.empty())
7191 // Note down frame index.
7192 if (FrameIndexSDNode *FI =
7193 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7194 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7196 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7197 SDB->getCurSDLoc());
7199 SDB->setValue(I, Res);
7200 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7201 if (LoadSDNode *LNode =
7202 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7203 if (FrameIndexSDNode *FI =
7204 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7205 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7208 // If this argument is live outside of the entry block, insert a copy from
7209 // wherever we got it to the vreg that other BB's will reference it as.
7210 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7211 // If we can, though, try to skip creating an unnecessary vreg.
7212 // FIXME: This isn't very clean... it would be nice to make this more
7213 // general. It's also subtly incompatible with the hacks FastISel
7215 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7216 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7217 FuncInfo->ValueMap[I] = Reg;
7221 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7222 FuncInfo->InitializeRegForValue(I);
7223 SDB->CopyToExportRegsIfNeeded(I);
7227 assert(i == InVals.size() && "Argument register count mismatch!");
7229 // Finally, if the target has anything special to do, allow it to do so.
7230 EmitFunctionEntryCode();
7233 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7234 /// ensure constants are generated when needed. Remember the virtual registers
7235 /// that need to be added to the Machine PHI nodes as input. We cannot just
7236 /// directly add them, because expansion might result in multiple MBB's for one
7237 /// BB. As such, the start of the BB might correspond to a different MBB than
7241 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7242 const TerminatorInst *TI = LLVMBB->getTerminator();
7244 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7246 // Check PHI nodes in successors that expect a value to be available from this
7248 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7249 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7250 if (!isa<PHINode>(SuccBB->begin())) continue;
7251 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7253 // If this terminator has multiple identical successors (common for
7254 // switches), only handle each succ once.
7255 if (!SuccsHandled.insert(SuccMBB).second)
7258 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7260 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7261 // nodes and Machine PHI nodes, but the incoming operands have not been
7263 for (BasicBlock::const_iterator I = SuccBB->begin();
7264 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7265 // Ignore dead phi's.
7266 if (PN->use_empty()) continue;
7269 if (PN->getType()->isEmptyTy())
7273 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7275 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7276 unsigned &RegOut = ConstantsOut[C];
7278 RegOut = FuncInfo.CreateRegs(C->getType());
7279 CopyValueToVirtualRegister(C, RegOut);
7283 DenseMap<const Value *, unsigned>::iterator I =
7284 FuncInfo.ValueMap.find(PHIOp);
7285 if (I != FuncInfo.ValueMap.end())
7288 assert(isa<AllocaInst>(PHIOp) &&
7289 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7290 "Didn't codegen value into a register!??");
7291 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7292 CopyValueToVirtualRegister(PHIOp, Reg);
7296 // Remember that this register needs to added to the machine PHI node as
7297 // the input for this MBB.
7298 SmallVector<EVT, 4> ValueVTs;
7299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7300 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7301 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7302 EVT VT = ValueVTs[vti];
7303 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7304 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7305 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7306 Reg += NumRegisters;
7311 ConstantsOut.clear();
7314 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7317 SelectionDAGBuilder::StackProtectorDescriptor::
7318 AddSuccessorMBB(const BasicBlock *BB,
7319 MachineBasicBlock *ParentMBB,
7321 MachineBasicBlock *SuccMBB) {
7322 // If SuccBB has not been created yet, create it.
7324 MachineFunction *MF = ParentMBB->getParent();
7325 MachineFunction::iterator BBI = ParentMBB;
7326 SuccMBB = MF->CreateMachineBasicBlock(BB);
7327 MF->insert(++BBI, SuccMBB);
7329 // Add it as a successor of ParentMBB.
7330 ParentMBB->addSuccessor(
7331 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7335 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7336 MachineFunction::iterator I = MBB;
7337 if (++I == FuncInfo.MF->end())
7342 /// During lowering new call nodes can be created (such as memset, etc.).
7343 /// Those will become new roots of the current DAG, but complications arise
7344 /// when they are tail calls. In such cases, the call lowering will update
7345 /// the root, but the builder still needs to know that a tail call has been
7346 /// lowered in order to avoid generating an additional return.
7347 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7348 // If the node is null, we do have a tail call.
7349 if (MaybeTC.getNode() != nullptr)
7350 DAG.setRoot(MaybeTC);
7355 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7356 unsigned *TotalCases, unsigned First,
7358 assert(Last >= First);
7359 assert(TotalCases[Last] >= TotalCases[First]);
7361 APInt LowCase = Clusters[First].Low->getValue();
7362 APInt HighCase = Clusters[Last].High->getValue();
7363 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7365 // FIXME: A range of consecutive cases has 100% density, but only requires one
7366 // comparison to lower. We should discriminate against such consecutive ranges
7369 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7370 uint64_t Range = Diff + 1;
7373 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7375 assert(NumCases < UINT64_MAX / 100);
7376 assert(Range >= NumCases);
7378 return NumCases * 100 >= Range * MinJumpTableDensity;
7381 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7382 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7383 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7386 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7387 unsigned First, unsigned Last,
7388 const SwitchInst *SI,
7389 MachineBasicBlock *DefaultMBB,
7390 CaseCluster &JTCluster) {
7391 assert(First <= Last);
7393 uint32_t Weight = 0;
7394 unsigned NumCmps = 0;
7395 std::vector<MachineBasicBlock*> Table;
7396 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7397 for (unsigned I = First; I <= Last; ++I) {
7398 assert(Clusters[I].Kind == CC_Range);
7399 Weight += Clusters[I].Weight;
7400 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7401 APInt Low = Clusters[I].Low->getValue();
7402 APInt High = Clusters[I].High->getValue();
7403 NumCmps += (Low == High) ? 1 : 2;
7405 // Fill the gap between this and the previous cluster.
7406 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7407 assert(PreviousHigh.slt(Low));
7408 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7409 for (uint64_t J = 0; J < Gap; J++)
7410 Table.push_back(DefaultMBB);
7412 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7413 for (uint64_t J = 0; J < ClusterSize; ++J)
7414 Table.push_back(Clusters[I].MBB);
7415 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7418 unsigned NumDests = JTWeights.size();
7419 if (isSuitableForBitTests(NumDests, NumCmps,
7420 Clusters[First].Low->getValue(),
7421 Clusters[Last].High->getValue())) {
7422 // Clusters[First..Last] should be lowered as bit tests instead.
7426 // Create the MBB that will load from and jump through the table.
7427 // Note: We create it here, but it's not inserted into the function yet.
7428 MachineFunction *CurMF = FuncInfo.MF;
7429 MachineBasicBlock *JumpTableMBB =
7430 CurMF->CreateMachineBasicBlock(SI->getParent());
7432 // Add successors. Note: use table order for determinism.
7433 SmallPtrSet<MachineBasicBlock *, 8> Done;
7434 for (MachineBasicBlock *Succ : Table) {
7435 if (Done.count(Succ))
7437 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7441 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7442 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7443 ->createJumpTableIndex(Table);
7445 // Set up the jump table info.
7446 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7447 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7448 Clusters[Last].High->getValue(), SI->getCondition(),
7450 JTCases.emplace_back(std::move(JTH), std::move(JT));
7452 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7453 JTCases.size() - 1, Weight);
7457 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7458 const SwitchInst *SI,
7459 MachineBasicBlock *DefaultMBB) {
7461 // Clusters must be non-empty, sorted, and only contain Range clusters.
7462 assert(!Clusters.empty());
7463 for (CaseCluster &C : Clusters)
7464 assert(C.Kind == CC_Range);
7465 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7466 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7469 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7470 if (!areJTsAllowed(TLI))
7473 const int64_t N = Clusters.size();
7474 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7476 // Split Clusters into minimum number of dense partitions. The algorithm uses
7477 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7478 // for the Case Statement'" (1994), but builds the MinPartitions array in
7479 // reverse order to make it easier to reconstruct the partitions in ascending
7480 // order. In the choice between two optimal partitionings, it picks the one
7481 // which yields more jump tables.
7483 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7484 SmallVector<unsigned, 8> MinPartitions(N);
7485 // LastElement[i] is the last element of the partition starting at i.
7486 SmallVector<unsigned, 8> LastElement(N);
7487 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7488 SmallVector<unsigned, 8> NumTables(N);
7489 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7490 SmallVector<unsigned, 8> TotalCases(N);
7492 for (unsigned i = 0; i < N; ++i) {
7493 APInt Hi = Clusters[i].High->getValue();
7494 APInt Lo = Clusters[i].Low->getValue();
7495 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7497 TotalCases[i] += TotalCases[i - 1];
7500 // Base case: There is only one way to partition Clusters[N-1].
7501 MinPartitions[N - 1] = 1;
7502 LastElement[N - 1] = N - 1;
7503 assert(MinJumpTableSize > 1);
7504 NumTables[N - 1] = 0;
7506 // Note: loop indexes are signed to avoid underflow.
7507 for (int64_t i = N - 2; i >= 0; i--) {
7508 // Find optimal partitioning of Clusters[i..N-1].
7509 // Baseline: Put Clusters[i] into a partition on its own.
7510 MinPartitions[i] = MinPartitions[i + 1] + 1;
7512 NumTables[i] = NumTables[i + 1];
7514 // Search for a solution that results in fewer partitions.
7515 for (int64_t j = N - 1; j > i; j--) {
7516 // Try building a partition from Clusters[i..j].
7517 if (isDense(Clusters, &TotalCases[0], i, j)) {
7518 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7519 bool IsTable = j - i + 1 >= MinJumpTableSize;
7520 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7522 // If this j leads to fewer partitions, or same number of partitions
7523 // with more lookup tables, it is a better partitioning.
7524 if (NumPartitions < MinPartitions[i] ||
7525 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7526 MinPartitions[i] = NumPartitions;
7528 NumTables[i] = Tables;
7534 // Iterate over the partitions, replacing some with jump tables in-place.
7535 unsigned DstIndex = 0;
7536 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7537 Last = LastElement[First];
7538 assert(Last >= First);
7539 assert(DstIndex <= First);
7540 unsigned NumClusters = Last - First + 1;
7542 CaseCluster JTCluster;
7543 if (NumClusters >= MinJumpTableSize &&
7544 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7545 Clusters[DstIndex++] = JTCluster;
7547 for (unsigned I = First; I <= Last; ++I)
7548 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7551 Clusters.resize(DstIndex);
7554 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7555 // FIXME: Using the pointer type doesn't seem ideal.
7556 uint64_t BW = DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7557 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7561 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7564 const APInt &High) {
7565 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7566 // range of cases both require only one branch to lower. Just looking at the
7567 // number of clusters and destinations should be enough to decide whether to
7570 // To lower a range with bit tests, the range must fit the bitwidth of a
7572 if (!rangeFitsInWord(Low, High))
7575 // Decide whether it's profitable to lower this range with bit tests. Each
7576 // destination requires a bit test and branch, and there is an overall range
7577 // check branch. For a small number of clusters, separate comparisons might be
7578 // cheaper, and for many destinations, splitting the range might be better.
7579 return (NumDests == 1 && NumCmps >= 3) ||
7580 (NumDests == 2 && NumCmps >= 5) ||
7581 (NumDests == 3 && NumCmps >= 6);
7584 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7585 unsigned First, unsigned Last,
7586 const SwitchInst *SI,
7587 CaseCluster &BTCluster) {
7588 assert(First <= Last);
7592 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7593 unsigned NumCmps = 0;
7594 for (int64_t I = First; I <= Last; ++I) {
7595 assert(Clusters[I].Kind == CC_Range);
7596 Dests.set(Clusters[I].MBB->getNumber());
7597 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7599 unsigned NumDests = Dests.count();
7601 APInt Low = Clusters[First].Low->getValue();
7602 APInt High = Clusters[Last].High->getValue();
7603 assert(Low.slt(High));
7605 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7611 const int BitWidth =
7612 DAG.getTargetLoweringInfo().getPointerTy().getSizeInBits();
7613 assert((High - Low + 1).sle(BitWidth) && "Case range must fit in bit mask!");
7615 if (Low.isNonNegative() && High.slt(BitWidth)) {
7616 // Optimize the case where all the case values fit in a
7617 // word without having to subtract minValue. In this case,
7618 // we can optimize away the subtraction.
7619 LowBound = APInt::getNullValue(Low.getBitWidth());
7623 CmpRange = High - Low;
7627 uint32_t TotalWeight = 0;
7628 for (unsigned i = First; i <= Last; ++i) {
7629 // Find the CaseBits for this destination.
7631 for (j = 0; j < CBV.size(); ++j)
7632 if (CBV[j].BB == Clusters[i].MBB)
7634 if (j == CBV.size())
7635 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7636 CaseBits *CB = &CBV[j];
7638 // Update Mask, Bits and ExtraWeight.
7639 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7640 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7641 for (uint64_t j = Lo; j <= Hi; ++j) {
7642 CB->Mask |= 1ULL << j;
7645 CB->ExtraWeight += Clusters[i].Weight;
7646 TotalWeight += Clusters[i].Weight;
7647 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7651 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7652 // Sort by weight first, number of bits second.
7653 if (a.ExtraWeight != b.ExtraWeight)
7654 return a.ExtraWeight > b.ExtraWeight;
7655 return a.Bits > b.Bits;
7658 for (auto &CB : CBV) {
7659 MachineBasicBlock *BitTestBB =
7660 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7661 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7663 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7664 SI->getCondition(), -1U, MVT::Other, false, nullptr,
7665 nullptr, std::move(BTI));
7667 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7668 BitTestCases.size() - 1, TotalWeight);
7672 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7673 const SwitchInst *SI) {
7674 // Partition Clusters into as few subsets as possible, where each subset has a
7675 // range that fits in a machine word and has <= 3 unique destinations.
7678 // Clusters must be sorted and contain Range or JumpTable clusters.
7679 assert(!Clusters.empty());
7680 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7681 for (const CaseCluster &C : Clusters)
7682 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7683 for (unsigned i = 1; i < Clusters.size(); ++i)
7684 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
7687 // If target does not have legal shift left, do not emit bit tests at all.
7688 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7689 EVT PTy = TLI.getPointerTy();
7690 if (!TLI.isOperationLegal(ISD::SHL, PTy))
7693 int BitWidth = PTy.getSizeInBits();
7694 const int64_t N = Clusters.size();
7696 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7697 SmallVector<unsigned, 8> MinPartitions(N);
7698 // LastElement[i] is the last element of the partition starting at i.
7699 SmallVector<unsigned, 8> LastElement(N);
7701 // FIXME: This might not be the best algorithm for finding bit test clusters.
7703 // Base case: There is only one way to partition Clusters[N-1].
7704 MinPartitions[N - 1] = 1;
7705 LastElement[N - 1] = N - 1;
7707 // Note: loop indexes are signed to avoid underflow.
7708 for (int64_t i = N - 2; i >= 0; --i) {
7709 // Find optimal partitioning of Clusters[i..N-1].
7710 // Baseline: Put Clusters[i] into a partition on its own.
7711 MinPartitions[i] = MinPartitions[i + 1] + 1;
7714 // Search for a solution that results in fewer partitions.
7715 // Note: the search is limited by BitWidth, reducing time complexity.
7716 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
7717 // Try building a partition from Clusters[i..j].
7720 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
7721 Clusters[j].High->getValue()))
7724 // Check nbr of destinations and cluster types.
7725 // FIXME: This works, but doesn't seem very efficient.
7726 bool RangesOnly = true;
7727 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7728 for (int64_t k = i; k <= j; k++) {
7729 if (Clusters[k].Kind != CC_Range) {
7733 Dests.set(Clusters[k].MBB->getNumber());
7735 if (!RangesOnly || Dests.count() > 3)
7738 // Check if it's a better partition.
7739 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7740 if (NumPartitions < MinPartitions[i]) {
7741 // Found a better partition.
7742 MinPartitions[i] = NumPartitions;
7748 // Iterate over the partitions, replacing with bit-test clusters in-place.
7749 unsigned DstIndex = 0;
7750 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7751 Last = LastElement[First];
7752 assert(First <= Last);
7753 assert(DstIndex <= First);
7755 CaseCluster BitTestCluster;
7756 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
7757 Clusters[DstIndex++] = BitTestCluster;
7759 for (unsigned I = First; I <= Last; ++I)
7760 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7763 Clusters.resize(DstIndex);
7766 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
7767 MachineBasicBlock *SwitchMBB,
7768 MachineBasicBlock *DefaultMBB) {
7769 MachineFunction *CurMF = FuncInfo.MF;
7770 MachineBasicBlock *NextMBB = nullptr;
7771 MachineFunction::iterator BBI = W.MBB;
7772 if (++BBI != FuncInfo.MF->end())
7775 unsigned Size = W.LastCluster - W.FirstCluster + 1;
7777 BranchProbabilityInfo *BPI = FuncInfo.BPI;
7779 if (Size == 2 && W.MBB == SwitchMBB) {
7780 // If any two of the cases has the same destination, and if one value
7781 // is the same as the other, but has one bit unset that the other has set,
7782 // use bit manipulation to do two compares at once. For example:
7783 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
7784 // TODO: This could be extended to merge any 2 cases in switches with 3
7786 // TODO: Handle cases where W.CaseBB != SwitchBB.
7787 CaseCluster &Small = *W.FirstCluster;
7788 CaseCluster &Big = *W.LastCluster;
7790 if (Small.Low == Small.High && Big.Low == Big.High &&
7791 Small.MBB == Big.MBB) {
7792 const APInt &SmallValue = Small.Low->getValue();
7793 const APInt &BigValue = Big.Low->getValue();
7795 // Check that there is only one bit different.
7796 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
7797 (SmallValue | BigValue) == BigValue) {
7798 // Isolate the common bit.
7799 APInt CommonBit = BigValue & ~SmallValue;
7800 assert((SmallValue | CommonBit) == BigValue &&
7801 CommonBit.countPopulation() == 1 && "Not a common bit?");
7803 SDValue CondLHS = getValue(Cond);
7804 EVT VT = CondLHS.getValueType();
7805 SDLoc DL = getCurSDLoc();
7807 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
7808 DAG.getConstant(CommonBit, DL, VT));
7809 SDValue Cond = DAG.getSetCC(DL, MVT::i1, Or,
7810 DAG.getConstant(BigValue, DL, VT),
7813 // Update successor info.
7814 // Both Small and Big will jump to Small.BB, so we sum up the weights.
7815 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
7816 addSuccessorWithWeight(
7817 SwitchMBB, DefaultMBB,
7818 // The default destination is the first successor in IR.
7819 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
7822 // Insert the true branch.
7824 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
7825 DAG.getBasicBlock(Small.MBB));
7826 // Insert the false branch.
7827 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
7828 DAG.getBasicBlock(DefaultMBB));
7830 DAG.setRoot(BrCond);
7836 if (TM.getOptLevel() != CodeGenOpt::None) {
7837 // Order cases by weight so the most likely case will be checked first.
7838 std::sort(W.FirstCluster, W.LastCluster + 1,
7839 [](const CaseCluster &a, const CaseCluster &b) {
7840 return a.Weight > b.Weight;
7843 // Rearrange the case blocks so that the last one falls through if possible
7844 // without without changing the order of weights.
7845 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
7847 if (I->Weight > W.LastCluster->Weight)
7849 if (I->Kind == CC_Range && I->MBB == NextMBB) {
7850 std::swap(*I, *W.LastCluster);
7856 // Compute total weight.
7857 uint32_t UnhandledWeights = 0;
7858 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
7859 UnhandledWeights += I->Weight;
7860 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
7863 MachineBasicBlock *CurMBB = W.MBB;
7864 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
7865 MachineBasicBlock *Fallthrough;
7866 if (I == W.LastCluster) {
7867 // For the last cluster, fall through to the default destination.
7868 Fallthrough = DefaultMBB;
7870 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
7871 CurMF->insert(BBI, Fallthrough);
7872 // Put Cond in a virtual register to make it available from the new blocks.
7873 ExportFromCurrentBlock(Cond);
7877 case CC_JumpTable: {
7878 // FIXME: Optimize away range check based on pivot comparisons.
7879 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
7880 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
7882 // The jump block hasn't been inserted yet; insert it here.
7883 MachineBasicBlock *JumpMBB = JT->MBB;
7884 CurMF->insert(BBI, JumpMBB);
7885 addSuccessorWithWeight(CurMBB, Fallthrough);
7886 addSuccessorWithWeight(CurMBB, JumpMBB);
7888 // The jump table header will be inserted in our current block, do the
7889 // range check, and fall through to our fallthrough block.
7890 JTH->HeaderBB = CurMBB;
7891 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
7893 // If we're in the right place, emit the jump table header right now.
7894 if (CurMBB == SwitchMBB) {
7895 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
7896 JTH->Emitted = true;
7901 // FIXME: Optimize away range check based on pivot comparisons.
7902 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
7904 // The bit test blocks haven't been inserted yet; insert them here.
7905 for (BitTestCase &BTC : BTB->Cases)
7906 CurMF->insert(BBI, BTC.ThisBB);
7908 // Fill in fields of the BitTestBlock.
7909 BTB->Parent = CurMBB;
7910 BTB->Default = Fallthrough;
7912 // If we're in the right place, emit the bit test header header right now.
7913 if (CurMBB ==SwitchMBB) {
7914 visitBitTestHeader(*BTB, SwitchMBB);
7915 BTB->Emitted = true;
7920 const Value *RHS, *LHS, *MHS;
7922 if (I->Low == I->High) {
7923 // Check Cond == I->Low.
7929 // Check I->Low <= Cond <= I->High.
7936 // The false weight is the sum of all unhandled cases.
7937 UnhandledWeights -= I->Weight;
7938 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
7941 if (CurMBB == SwitchMBB)
7942 visitSwitchCase(CB, SwitchMBB);
7944 SwitchCases.push_back(CB);
7949 CurMBB = Fallthrough;
7953 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
7954 const SwitchWorkListItem &W,
7956 MachineBasicBlock *SwitchMBB) {
7957 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
7958 "Clusters not sorted?");
7960 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
7962 // Balance the tree based on branch weights to create a near-optimal (in terms
7963 // of search time given key frequency) binary search tree. See e.g. Kurt
7964 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
7965 CaseClusterIt LastLeft = W.FirstCluster;
7966 CaseClusterIt FirstRight = W.LastCluster;
7967 uint32_t LeftWeight = LastLeft->Weight;
7968 uint32_t RightWeight = FirstRight->Weight;
7970 // Move LastLeft and FirstRight towards each other from opposite directions to
7971 // find a partitioning of the clusters which balances the weight on both
7972 // sides. If LeftWeight and RightWeight are equal, alternate which side is
7973 // taken to ensure 0-weight nodes are distributed evenly.
7975 while (LastLeft + 1 < FirstRight) {
7976 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
7977 LeftWeight += (++LastLeft)->Weight;
7979 RightWeight += (--FirstRight)->Weight;
7982 assert(LastLeft + 1 == FirstRight);
7983 assert(LastLeft >= W.FirstCluster);
7984 assert(FirstRight <= W.LastCluster);
7986 // Use the first element on the right as pivot since we will make less-than
7987 // comparisons against it.
7988 CaseClusterIt PivotCluster = FirstRight;
7989 assert(PivotCluster > W.FirstCluster);
7990 assert(PivotCluster <= W.LastCluster);
7992 CaseClusterIt FirstLeft = W.FirstCluster;
7993 CaseClusterIt LastRight = W.LastCluster;
7995 const ConstantInt *Pivot = PivotCluster->Low;
7997 // New blocks will be inserted immediately after the current one.
7998 MachineFunction::iterator BBI = W.MBB;
8001 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8002 // we can branch to its destination directly if it's squeezed exactly in
8003 // between the known lower bound and Pivot - 1.
8004 MachineBasicBlock *LeftMBB;
8005 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8006 FirstLeft->Low == W.GE &&
8007 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8008 LeftMBB = FirstLeft->MBB;
8010 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8011 FuncInfo.MF->insert(BBI, LeftMBB);
8012 WorkList.push_back({LeftMBB, FirstLeft, LastLeft, W.GE, Pivot});
8013 // Put Cond in a virtual register to make it available from the new blocks.
8014 ExportFromCurrentBlock(Cond);
8017 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8018 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8019 // directly if RHS.High equals the current upper bound.
8020 MachineBasicBlock *RightMBB;
8021 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8022 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8023 RightMBB = FirstRight->MBB;
8025 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8026 FuncInfo.MF->insert(BBI, RightMBB);
8027 WorkList.push_back({RightMBB, FirstRight, LastRight, Pivot, W.LT});
8028 // Put Cond in a virtual register to make it available from the new blocks.
8029 ExportFromCurrentBlock(Cond);
8032 // Create the CaseBlock record that will be used to lower the branch.
8033 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8034 LeftWeight, RightWeight);
8036 if (W.MBB == SwitchMBB)
8037 visitSwitchCase(CB, SwitchMBB);
8039 SwitchCases.push_back(CB);
8042 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8043 // Extract cases from the switch.
8044 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8045 CaseClusterVector Clusters;
8046 Clusters.reserve(SI.getNumCases());
8047 for (auto I : SI.cases()) {
8048 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8049 const ConstantInt *CaseVal = I.getCaseValue();
8051 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8052 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8055 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8057 // Cluster adjacent cases with the same destination. We do this at all
8058 // optimization levels because it's cheap to do and will make codegen faster
8059 // if there are many clusters.
8060 sortAndRangeify(Clusters);
8062 if (TM.getOptLevel() != CodeGenOpt::None) {
8063 // Replace an unreachable default with the most popular destination.
8064 // FIXME: Exploit unreachable default more aggressively.
8065 bool UnreachableDefault =
8066 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8067 if (UnreachableDefault && !Clusters.empty()) {
8068 DenseMap<const BasicBlock *, unsigned> Popularity;
8069 unsigned MaxPop = 0;
8070 const BasicBlock *MaxBB = nullptr;
8071 for (auto I : SI.cases()) {
8072 const BasicBlock *BB = I.getCaseSuccessor();
8073 if (++Popularity[BB] > MaxPop) {
8074 MaxPop = Popularity[BB];
8079 assert(MaxPop > 0 && MaxBB);
8080 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8082 // Remove cases that were pointing to the destination that is now the
8084 CaseClusterVector New;
8085 New.reserve(Clusters.size());
8086 for (CaseCluster &CC : Clusters) {
8087 if (CC.MBB != DefaultMBB)
8090 Clusters = std::move(New);
8094 // If there is only the default destination, jump there directly.
8095 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8096 if (Clusters.empty()) {
8097 SwitchMBB->addSuccessor(DefaultMBB);
8098 if (DefaultMBB != NextBlock(SwitchMBB)) {
8099 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8100 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8105 if (TM.getOptLevel() != CodeGenOpt::None) {
8106 findJumpTables(Clusters, &SI, DefaultMBB);
8107 findBitTestClusters(Clusters, &SI);
8112 dbgs() << "Case clusters: ";
8113 for (const CaseCluster &C : Clusters) {
8114 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8115 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8117 C.Low->getValue().print(dbgs(), true);
8118 if (C.Low != C.High) {
8120 C.High->getValue().print(dbgs(), true);
8127 assert(!Clusters.empty());
8128 SwitchWorkList WorkList;
8129 CaseClusterIt First = Clusters.begin();
8130 CaseClusterIt Last = Clusters.end() - 1;
8131 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr});
8133 while (!WorkList.empty()) {
8134 SwitchWorkListItem W = WorkList.back();
8135 WorkList.pop_back();
8136 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8138 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8139 // For optimized builds, lower large range as a balanced binary tree.
8140 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8144 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);