1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
48 #include "llvm/Target/TargetData.h"
49 #include "llvm/Target/TargetFrameInfo.h"
50 #include "llvm/Target/TargetInstrInfo.h"
51 #include "llvm/Target/TargetIntrinsicInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "llvm/Support/Compiler.h"
55 #include "llvm/Support/CommandLine.h"
56 #include "llvm/Support/Debug.h"
57 #include "llvm/Support/ErrorHandling.h"
58 #include "llvm/Support/MathExtras.h"
59 #include "llvm/Support/raw_ostream.h"
63 /// LimitFloatPrecision - Generate low-precision inline sequences for
64 /// some float libcalls (6, 8 or 12 bits).
65 static unsigned LimitFloatPrecision;
67 static cl::opt<unsigned, true>
68 LimitFPPrecision("limit-float-precision",
69 cl::desc("Generate low-precision inline sequences "
70 "for some float libcalls"),
71 cl::location(LimitFloatPrecision),
74 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
75 const SDValue *Parts, unsigned NumParts,
76 EVT PartVT, EVT ValueVT);
78 /// getCopyFromParts - Create a value that contains the specified legal parts
79 /// combined into the value they represent. If the parts combine to a type
80 /// larger then ValueVT then AssertOp can be used to specify whether the extra
81 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
82 /// (ISD::AssertSext).
83 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
85 unsigned NumParts, EVT PartVT, EVT ValueVT,
86 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
87 if (ValueVT.isVector())
88 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
90 assert(NumParts > 0 && "No parts to assemble!");
91 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
92 SDValue Val = Parts[0];
95 // Assemble the value from multiple parts.
96 if (ValueVT.isInteger()) {
97 unsigned PartBits = PartVT.getSizeInBits();
98 unsigned ValueBits = ValueVT.getSizeInBits();
100 // Assemble the power of 2 part.
101 unsigned RoundParts = NumParts & (NumParts - 1) ?
102 1 << Log2_32(NumParts) : NumParts;
103 unsigned RoundBits = PartBits * RoundParts;
104 EVT RoundVT = RoundBits == ValueBits ?
105 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
108 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
110 if (RoundParts > 2) {
111 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
113 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
114 RoundParts / 2, PartVT, HalfVT);
116 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[0]);
117 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, HalfVT, Parts[1]);
120 if (TLI.isBigEndian())
123 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
125 if (RoundParts < NumParts) {
126 // Assemble the trailing non-power-of-2 part.
127 unsigned OddParts = NumParts - RoundParts;
128 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
129 Hi = getCopyFromParts(DAG, DL,
130 Parts + RoundParts, OddParts, PartVT, OddVT);
132 // Combine the round and odd parts.
134 if (TLI.isBigEndian())
136 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
137 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
138 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
139 DAG.getConstant(Lo.getValueType().getSizeInBits(),
140 TLI.getPointerTy()));
141 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
142 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
144 } else if (PartVT.isFloatingPoint()) {
145 // FP split into multiple FP parts (for ppcf128)
146 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
149 Lo = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[0]);
150 Hi = DAG.getNode(ISD::BIT_CONVERT, DL, EVT(MVT::f64), Parts[1]);
151 if (TLI.isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
155 // FP split into integer parts (soft fp)
156 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
157 !PartVT.isVector() && "Unexpected split");
158 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
159 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
163 // There is now one part, held in Val. Correct it to match ValueVT.
164 PartVT = Val.getValueType();
166 if (PartVT == ValueVT)
169 if (PartVT.isInteger() && ValueVT.isInteger()) {
170 if (ValueVT.bitsLT(PartVT)) {
171 // For a truncate, see if we have any information to
172 // indicate whether the truncated bits will always be
173 // zero or sign-extension.
174 if (AssertOp != ISD::DELETED_NODE)
175 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
176 DAG.getValueType(ValueVT));
177 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
179 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
182 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
183 // FP_ROUND's are always exact here.
184 if (ValueVT.bitsLT(Val.getValueType()))
185 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
186 DAG.getIntPtrConstant(1));
188 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
191 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
192 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
194 llvm_unreachable("Unknown mismatch!");
198 /// getCopyFromParts - Create a value that contains the specified legal parts
199 /// combined into the value they represent. If the parts combine to a type
200 /// larger then ValueVT then AssertOp can be used to specify whether the extra
201 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
202 /// (ISD::AssertSext).
203 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
204 const SDValue *Parts, unsigned NumParts,
205 EVT PartVT, EVT ValueVT) {
206 assert(ValueVT.isVector() && "Not a vector value");
207 assert(NumParts > 0 && "No parts to assemble!");
208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
209 SDValue Val = Parts[0];
211 // Handle a multi-element vector.
213 EVT IntermediateVT, RegisterVT;
214 unsigned NumIntermediates;
216 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
217 NumIntermediates, RegisterVT);
218 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
219 NumParts = NumRegs; // Silence a compiler warning.
220 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
221 assert(RegisterVT == Parts[0].getValueType() &&
222 "Part type doesn't match part!");
224 // Assemble the parts into intermediate operands.
225 SmallVector<SDValue, 8> Ops(NumIntermediates);
226 if (NumIntermediates == NumParts) {
227 // If the register was not expanded, truncate or copy the value,
229 for (unsigned i = 0; i != NumParts; ++i)
230 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
231 PartVT, IntermediateVT);
232 } else if (NumParts > 0) {
233 // If the intermediate type was expanded, build the intermediate
234 // operands from the parts.
235 assert(NumParts % NumIntermediates == 0 &&
236 "Must expand into a divisible number of parts!");
237 unsigned Factor = NumParts / NumIntermediates;
238 for (unsigned i = 0; i != NumIntermediates; ++i)
239 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
240 PartVT, IntermediateVT);
243 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
244 // intermediate operands.
245 Val = DAG.getNode(IntermediateVT.isVector() ?
246 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
247 ValueVT, &Ops[0], NumIntermediates);
250 // There is now one part, held in Val. Correct it to match ValueVT.
251 PartVT = Val.getValueType();
253 if (PartVT == ValueVT)
256 if (PartVT.isVector()) {
257 // If the element type of the source/dest vectors are the same, but the
258 // parts vector has more elements than the value vector, then we have a
259 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
261 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
262 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
263 "Cannot narrow, it would be a lossy transformation");
264 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
265 DAG.getIntPtrConstant(0));
268 // Vector/Vector bitcast.
269 return DAG.getNode(ISD::BIT_CONVERT, DL, ValueVT, Val);
272 assert(ValueVT.getVectorElementType() == PartVT &&
273 ValueVT.getVectorNumElements() == 1 &&
274 "Only trivial scalar-to-vector conversions should get here!");
275 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
281 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
282 SDValue Val, SDValue *Parts, unsigned NumParts,
285 /// getCopyToParts - Create a series of nodes that contain the specified value
286 /// split into legal parts. If the parts contain more bits than Val, then, for
287 /// integers, ExtendKind can be used to specify how to generate the extra bits.
288 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
289 SDValue Val, SDValue *Parts, unsigned NumParts,
291 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
292 EVT ValueVT = Val.getValueType();
294 // Handle the vector case separately.
295 if (ValueVT.isVector())
296 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
299 unsigned PartBits = PartVT.getSizeInBits();
300 unsigned OrigNumParts = NumParts;
301 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
306 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
307 if (PartVT == ValueVT) {
308 assert(NumParts == 1 && "No-op copy with multiple parts!");
313 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
314 // If the parts cover more bits than the value has, promote the value.
315 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
316 assert(NumParts == 1 && "Do not know what to promote to!");
317 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
319 assert(PartVT.isInteger() && ValueVT.isInteger() &&
320 "Unknown mismatch!");
321 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
322 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
324 } else if (PartBits == ValueVT.getSizeInBits()) {
325 // Different types of the same size.
326 assert(NumParts == 1 && PartVT != ValueVT);
327 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
328 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
329 // If the parts cover less bits than value has, truncate the value.
330 assert(PartVT.isInteger() && ValueVT.isInteger() &&
331 "Unknown mismatch!");
332 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
333 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
336 // The value may have changed - recompute ValueVT.
337 ValueVT = Val.getValueType();
338 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
339 "Failed to tile the value with PartVT!");
342 assert(PartVT == ValueVT && "Type conversion failed!");
347 // Expand the value into multiple parts.
348 if (NumParts & (NumParts - 1)) {
349 // The number of parts is not a power of 2. Split off and copy the tail.
350 assert(PartVT.isInteger() && ValueVT.isInteger() &&
351 "Do not know what to expand to!");
352 unsigned RoundParts = 1 << Log2_32(NumParts);
353 unsigned RoundBits = RoundParts * PartBits;
354 unsigned OddParts = NumParts - RoundParts;
355 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
356 DAG.getIntPtrConstant(RoundBits));
357 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
359 if (TLI.isBigEndian())
360 // The odd parts were reversed by getCopyToParts - unreverse them.
361 std::reverse(Parts + RoundParts, Parts + NumParts);
363 NumParts = RoundParts;
364 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
365 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
368 // The number of parts is a power of 2. Repeatedly bisect the value using
370 Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DL,
371 EVT::getIntegerVT(*DAG.getContext(),
372 ValueVT.getSizeInBits()),
375 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
376 for (unsigned i = 0; i < NumParts; i += StepSize) {
377 unsigned ThisBits = StepSize * PartBits / 2;
378 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
379 SDValue &Part0 = Parts[i];
380 SDValue &Part1 = Parts[i+StepSize/2];
382 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
383 ThisVT, Part0, DAG.getIntPtrConstant(1));
384 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
385 ThisVT, Part0, DAG.getIntPtrConstant(0));
387 if (ThisBits == PartBits && ThisVT != PartVT) {
388 Part0 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part0);
389 Part1 = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Part1);
394 if (TLI.isBigEndian())
395 std::reverse(Parts, Parts + OrigNumParts);
399 /// getCopyToPartsVector - Create a series of nodes that contain the specified
400 /// value split into legal parts.
401 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
402 SDValue Val, SDValue *Parts, unsigned NumParts,
404 EVT ValueVT = Val.getValueType();
405 assert(ValueVT.isVector() && "Not a vector");
406 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
409 if (PartVT == ValueVT) {
411 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
412 // Bitconvert vector->vector case.
413 Val = DAG.getNode(ISD::BIT_CONVERT, DL, PartVT, Val);
414 } else if (PartVT.isVector() &&
415 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
416 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
417 EVT ElementVT = PartVT.getVectorElementType();
418 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
420 SmallVector<SDValue, 16> Ops;
421 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
422 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
423 ElementVT, Val, DAG.getIntPtrConstant(i)));
425 for (unsigned i = ValueVT.getVectorNumElements(),
426 e = PartVT.getVectorNumElements(); i != e; ++i)
427 Ops.push_back(DAG.getUNDEF(ElementVT));
429 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
431 // FIXME: Use CONCAT for 2x -> 4x.
433 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
434 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
436 // Vector -> scalar conversion.
437 assert(ValueVT.getVectorElementType() == PartVT &&
438 ValueVT.getVectorNumElements() == 1 &&
439 "Only trivial vector-to-scalar conversions should get here!");
440 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
441 PartVT, Val, DAG.getIntPtrConstant(0));
448 // Handle a multi-element vector.
449 EVT IntermediateVT, RegisterVT;
450 unsigned NumIntermediates;
451 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
453 NumIntermediates, RegisterVT);
454 unsigned NumElements = ValueVT.getVectorNumElements();
456 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
457 NumParts = NumRegs; // Silence a compiler warning.
458 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
460 // Split the vector into intermediate operands.
461 SmallVector<SDValue, 8> Ops(NumIntermediates);
462 for (unsigned i = 0; i != NumIntermediates; ++i) {
463 if (IntermediateVT.isVector())
464 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
466 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
468 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
469 IntermediateVT, Val, DAG.getIntPtrConstant(i));
472 // Split the intermediate operands into legal parts.
473 if (NumParts == NumIntermediates) {
474 // If the register was not expanded, promote or copy the value,
476 for (unsigned i = 0; i != NumParts; ++i)
477 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
478 } else if (NumParts > 0) {
479 // If the intermediate type was expanded, split each the value into
481 assert(NumParts % NumIntermediates == 0 &&
482 "Must expand into a divisible number of parts!");
483 unsigned Factor = NumParts / NumIntermediates;
484 for (unsigned i = 0; i != NumIntermediates; ++i)
485 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
493 /// RegsForValue - This struct represents the registers (physical or virtual)
494 /// that a particular set of values is assigned, and the type information
495 /// about the value. The most common situation is to represent one value at a
496 /// time, but struct or array values are handled element-wise as multiple
497 /// values. The splitting of aggregates is performed recursively, so that we
498 /// never have aggregate-typed registers. The values at this point do not
499 /// necessarily have legal types, so each value may require one or more
500 /// registers of some legal type.
502 struct RegsForValue {
503 /// ValueVTs - The value types of the values, which may not be legal, and
504 /// may need be promoted or synthesized from one or more registers.
506 SmallVector<EVT, 4> ValueVTs;
508 /// RegVTs - The value types of the registers. This is the same size as
509 /// ValueVTs and it records, for each value, what the type of the assigned
510 /// register or registers are. (Individual values are never synthesized
511 /// from more than one type of register.)
513 /// With virtual registers, the contents of RegVTs is redundant with TLI's
514 /// getRegisterType member function, however when with physical registers
515 /// it is necessary to have a separate record of the types.
517 SmallVector<EVT, 4> RegVTs;
519 /// Regs - This list holds the registers assigned to the values.
520 /// Each legal or promoted value requires one register, and each
521 /// expanded value requires multiple registers.
523 SmallVector<unsigned, 4> Regs;
527 RegsForValue(const SmallVector<unsigned, 4> ®s,
528 EVT regvt, EVT valuevt)
529 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
531 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
532 unsigned Reg, const Type *Ty) {
533 ComputeValueVTs(tli, Ty, ValueVTs);
535 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
536 EVT ValueVT = ValueVTs[Value];
537 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
538 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
539 for (unsigned i = 0; i != NumRegs; ++i)
540 Regs.push_back(Reg + i);
541 RegVTs.push_back(RegisterVT);
546 /// areValueTypesLegal - Return true if types of all the values are legal.
547 bool areValueTypesLegal(const TargetLowering &TLI) {
548 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
549 EVT RegisterVT = RegVTs[Value];
550 if (!TLI.isTypeLegal(RegisterVT))
556 /// append - Add the specified values to this one.
557 void append(const RegsForValue &RHS) {
558 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
559 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
560 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
563 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
564 /// this value and returns the result as a ValueVTs value. This uses
565 /// Chain/Flag as the input and updates them for the output Chain/Flag.
566 /// If the Flag pointer is NULL, no flag is used.
567 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
569 SDValue &Chain, SDValue *Flag) const;
571 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
572 /// specified value into the registers specified by this object. This uses
573 /// Chain/Flag as the input and updates them for the output Chain/Flag.
574 /// If the Flag pointer is NULL, no flag is used.
575 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
576 SDValue &Chain, SDValue *Flag) const;
578 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
579 /// operand list. This adds the code marker, matching input operand index
580 /// (if applicable), and includes the number of values added into it.
581 void AddInlineAsmOperands(unsigned Kind,
582 bool HasMatching, unsigned MatchingIdx,
584 std::vector<SDValue> &Ops) const;
588 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
589 /// this value and returns the result as a ValueVT value. This uses
590 /// Chain/Flag as the input and updates them for the output Chain/Flag.
591 /// If the Flag pointer is NULL, no flag is used.
592 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
593 FunctionLoweringInfo &FuncInfo,
595 SDValue &Chain, SDValue *Flag) const {
596 // A Value with type {} or [0 x %t] needs no registers.
597 if (ValueVTs.empty())
600 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
602 // Assemble the legal parts into the final values.
603 SmallVector<SDValue, 4> Values(ValueVTs.size());
604 SmallVector<SDValue, 8> Parts;
605 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
606 // Copy the legal parts from the registers.
607 EVT ValueVT = ValueVTs[Value];
608 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
609 EVT RegisterVT = RegVTs[Value];
611 Parts.resize(NumRegs);
612 for (unsigned i = 0; i != NumRegs; ++i) {
615 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
617 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
618 *Flag = P.getValue(2);
621 Chain = P.getValue(1);
623 // If the source register was virtual and if we know something about it,
624 // add an assert node.
625 if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
626 RegisterVT.isInteger() && !RegisterVT.isVector()) {
627 unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
628 if (FuncInfo.LiveOutRegInfo.size() > SlotNo) {
629 const FunctionLoweringInfo::LiveOutInfo &LOI =
630 FuncInfo.LiveOutRegInfo[SlotNo];
632 unsigned RegSize = RegisterVT.getSizeInBits();
633 unsigned NumSignBits = LOI.NumSignBits;
634 unsigned NumZeroBits = LOI.KnownZero.countLeadingOnes();
636 // FIXME: We capture more information than the dag can represent. For
637 // now, just use the tightest assertzext/assertsext possible.
639 EVT FromVT(MVT::Other);
640 if (NumSignBits == RegSize)
641 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
642 else if (NumZeroBits >= RegSize-1)
643 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
644 else if (NumSignBits > RegSize-8)
645 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
646 else if (NumZeroBits >= RegSize-8)
647 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
648 else if (NumSignBits > RegSize-16)
649 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
650 else if (NumZeroBits >= RegSize-16)
651 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
652 else if (NumSignBits > RegSize-32)
653 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
654 else if (NumZeroBits >= RegSize-32)
655 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
657 if (FromVT != MVT::Other)
658 P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
659 RegisterVT, P, DAG.getValueType(FromVT));
666 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
667 NumRegs, RegisterVT, ValueVT);
672 return DAG.getNode(ISD::MERGE_VALUES, dl,
673 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
674 &Values[0], ValueVTs.size());
677 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
678 /// specified value into the registers specified by this object. This uses
679 /// Chain/Flag as the input and updates them for the output Chain/Flag.
680 /// If the Flag pointer is NULL, no flag is used.
681 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
682 SDValue &Chain, SDValue *Flag) const {
683 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
685 // Get the list of the values's legal parts.
686 unsigned NumRegs = Regs.size();
687 SmallVector<SDValue, 8> Parts(NumRegs);
688 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
689 EVT ValueVT = ValueVTs[Value];
690 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
691 EVT RegisterVT = RegVTs[Value];
693 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
694 &Parts[Part], NumParts, RegisterVT);
698 // Copy the parts into the registers.
699 SmallVector<SDValue, 8> Chains(NumRegs);
700 for (unsigned i = 0; i != NumRegs; ++i) {
703 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
705 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
706 *Flag = Part.getValue(1);
709 Chains[i] = Part.getValue(0);
712 if (NumRegs == 1 || Flag)
713 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
714 // flagged to it. That is the CopyToReg nodes and the user are considered
715 // a single scheduling unit. If we create a TokenFactor and return it as
716 // chain, then the TokenFactor is both a predecessor (operand) of the
717 // user as well as a successor (the TF operands are flagged to the user).
718 // c1, f1 = CopyToReg
719 // c2, f2 = CopyToReg
720 // c3 = TokenFactor c1, c2
723 Chain = Chains[NumRegs-1];
725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
728 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
729 /// operand list. This adds the code marker and includes the number of
730 /// values added into it.
731 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
732 unsigned MatchingIdx,
734 std::vector<SDValue> &Ops) const {
735 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
737 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
739 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
740 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
743 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
744 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
745 EVT RegisterVT = RegVTs[Value];
746 for (unsigned i = 0; i != NumRegs; ++i) {
747 assert(Reg < Regs.size() && "Mismatch in # registers expected");
748 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
753 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
756 TD = DAG.getTarget().getTargetData();
759 /// clear - Clear out the current SelectionDAG and the associated
760 /// state and prepare this SelectionDAGBuilder object to be used
761 /// for a new block. This doesn't clear out information about
762 /// additional blocks that are needed to complete switch lowering
763 /// or PHI node updating; that information is cleared out as it is
765 void SelectionDAGBuilder::clear() {
767 UnusedArgNodeMap.clear();
768 PendingLoads.clear();
769 PendingExports.clear();
770 DanglingDebugInfoMap.clear();
771 CurDebugLoc = DebugLoc();
775 /// getRoot - Return the current virtual root of the Selection DAG,
776 /// flushing any PendingLoad items. This must be done before emitting
777 /// a store or any other node that may need to be ordered after any
778 /// prior load instructions.
780 SDValue SelectionDAGBuilder::getRoot() {
781 if (PendingLoads.empty())
782 return DAG.getRoot();
784 if (PendingLoads.size() == 1) {
785 SDValue Root = PendingLoads[0];
787 PendingLoads.clear();
791 // Otherwise, we have to make a token factor node.
792 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
793 &PendingLoads[0], PendingLoads.size());
794 PendingLoads.clear();
799 /// getControlRoot - Similar to getRoot, but instead of flushing all the
800 /// PendingLoad items, flush all the PendingExports items. It is necessary
801 /// to do this before emitting a terminator instruction.
803 SDValue SelectionDAGBuilder::getControlRoot() {
804 SDValue Root = DAG.getRoot();
806 if (PendingExports.empty())
809 // Turn all of the CopyToReg chains into one factored node.
810 if (Root.getOpcode() != ISD::EntryToken) {
811 unsigned i = 0, e = PendingExports.size();
812 for (; i != e; ++i) {
813 assert(PendingExports[i].getNode()->getNumOperands() > 1);
814 if (PendingExports[i].getNode()->getOperand(0) == Root)
815 break; // Don't add the root if we already indirectly depend on it.
819 PendingExports.push_back(Root);
822 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
824 PendingExports.size());
825 PendingExports.clear();
830 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
831 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
832 DAG.AssignOrdering(Node, SDNodeOrder);
834 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
835 AssignOrderingToNode(Node->getOperand(I).getNode());
838 void SelectionDAGBuilder::visit(const Instruction &I) {
839 // Set up outgoing PHI node register values before emitting the terminator.
840 if (isa<TerminatorInst>(&I))
841 HandlePHINodesInSuccessorBlocks(I.getParent());
843 CurDebugLoc = I.getDebugLoc();
845 visit(I.getOpcode(), I);
847 if (!isa<TerminatorInst>(&I) && !HasTailCall)
848 CopyToExportRegsIfNeeded(&I);
850 CurDebugLoc = DebugLoc();
853 void SelectionDAGBuilder::visitPHI(const PHINode &) {
854 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
857 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
858 // Note: this doesn't use InstVisitor, because it has to work with
859 // ConstantExpr's in addition to instructions.
861 default: llvm_unreachable("Unknown instruction type encountered!");
862 // Build the switch statement using the Instruction.def file.
863 #define HANDLE_INST(NUM, OPCODE, CLASS) \
864 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
865 #include "llvm/Instruction.def"
868 // Assign the ordering to the freshly created DAG nodes.
869 if (NodeMap.count(&I)) {
871 AssignOrderingToNode(getValue(&I).getNode());
875 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
876 // generate the debug data structures now that we've seen its definition.
877 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
879 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
881 const DbgValueInst *DI = DDI.getDI();
882 DebugLoc dl = DDI.getdl();
883 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
884 MDNode *Variable = DI->getVariable();
885 uint64_t Offset = DI->getOffset();
888 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
889 SDV = DAG.getDbgValue(Variable, Val.getNode(),
890 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
891 DAG.AddDbgValue(SDV, Val.getNode(), false);
894 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
895 Offset, dl, SDNodeOrder);
896 DAG.AddDbgValue(SDV, 0, false);
898 DanglingDebugInfoMap[V] = DanglingDebugInfo();
902 // getValue - Return an SDValue for the given Value.
903 SDValue SelectionDAGBuilder::getValue(const Value *V) {
904 // If we already have an SDValue for this value, use it. It's important
905 // to do this first, so that we don't create a CopyFromReg if we already
906 // have a regular SDValue.
907 SDValue &N = NodeMap[V];
908 if (N.getNode()) return N;
910 // If there's a virtual register allocated and initialized for this
912 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
913 if (It != FuncInfo.ValueMap.end()) {
914 unsigned InReg = It->second;
915 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
916 SDValue Chain = DAG.getEntryNode();
917 return N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
920 // Otherwise create a new SDValue and remember it.
921 SDValue Val = getValueImpl(V);
923 resolveDanglingDebugInfo(V, Val);
927 /// getNonRegisterValue - Return an SDValue for the given Value, but
928 /// don't look in FuncInfo.ValueMap for a virtual register.
929 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
930 // If we already have an SDValue for this value, use it.
931 SDValue &N = NodeMap[V];
932 if (N.getNode()) return N;
934 // Otherwise create a new SDValue and remember it.
935 SDValue Val = getValueImpl(V);
937 resolveDanglingDebugInfo(V, Val);
941 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
942 /// Create an SDValue for the given value.
943 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
944 if (const Constant *C = dyn_cast<Constant>(V)) {
945 EVT VT = TLI.getValueType(V->getType(), true);
947 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
948 return DAG.getConstant(*CI, VT);
950 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
951 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
953 if (isa<ConstantPointerNull>(C))
954 return DAG.getConstant(0, TLI.getPointerTy());
956 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
957 return DAG.getConstantFP(*CFP, VT);
959 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
960 return DAG.getUNDEF(VT);
962 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
963 visit(CE->getOpcode(), *CE);
964 SDValue N1 = NodeMap[V];
965 assert(N1.getNode() && "visit didn't populate the NodeMap!");
969 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
970 SmallVector<SDValue, 4> Constants;
971 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
973 SDNode *Val = getValue(*OI).getNode();
974 // If the operand is an empty aggregate, there are no values.
976 // Add each leaf value from the operand to the Constants list
977 // to form a flattened list of all the values.
978 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
979 Constants.push_back(SDValue(Val, i));
982 return DAG.getMergeValues(&Constants[0], Constants.size(),
986 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
987 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
988 "Unknown struct or array constant!");
990 SmallVector<EVT, 4> ValueVTs;
991 ComputeValueVTs(TLI, C->getType(), ValueVTs);
992 unsigned NumElts = ValueVTs.size();
994 return SDValue(); // empty struct
995 SmallVector<SDValue, 4> Constants(NumElts);
996 for (unsigned i = 0; i != NumElts; ++i) {
997 EVT EltVT = ValueVTs[i];
998 if (isa<UndefValue>(C))
999 Constants[i] = DAG.getUNDEF(EltVT);
1000 else if (EltVT.isFloatingPoint())
1001 Constants[i] = DAG.getConstantFP(0, EltVT);
1003 Constants[i] = DAG.getConstant(0, EltVT);
1006 return DAG.getMergeValues(&Constants[0], NumElts,
1010 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1011 return DAG.getBlockAddress(BA, VT);
1013 const VectorType *VecTy = cast<VectorType>(V->getType());
1014 unsigned NumElements = VecTy->getNumElements();
1016 // Now that we know the number and type of the elements, get that number of
1017 // elements into the Ops array based on what kind of constant it is.
1018 SmallVector<SDValue, 16> Ops;
1019 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1020 for (unsigned i = 0; i != NumElements; ++i)
1021 Ops.push_back(getValue(CP->getOperand(i)));
1023 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1024 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1027 if (EltVT.isFloatingPoint())
1028 Op = DAG.getConstantFP(0, EltVT);
1030 Op = DAG.getConstant(0, EltVT);
1031 Ops.assign(NumElements, Op);
1034 // Create a BUILD_VECTOR node.
1035 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1036 VT, &Ops[0], Ops.size());
1039 // If this is a static alloca, generate it as the frameindex instead of
1041 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1042 DenseMap<const AllocaInst*, int>::iterator SI =
1043 FuncInfo.StaticAllocaMap.find(AI);
1044 if (SI != FuncInfo.StaticAllocaMap.end())
1045 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1048 // If this is an instruction which fast-isel has deferred, select it now.
1049 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1050 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1051 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1052 SDValue Chain = DAG.getEntryNode();
1053 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1056 llvm_unreachable("Can't get register for value!");
1060 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1061 SDValue Chain = getControlRoot();
1062 SmallVector<ISD::OutputArg, 8> Outs;
1063 SmallVector<SDValue, 8> OutVals;
1065 if (!FuncInfo.CanLowerReturn) {
1066 unsigned DemoteReg = FuncInfo.DemoteRegister;
1067 const Function *F = I.getParent()->getParent();
1069 // Emit a store of the return value through the virtual register.
1070 // Leave Outs empty so that LowerReturn won't try to load return
1071 // registers the usual way.
1072 SmallVector<EVT, 1> PtrValueVTs;
1073 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1076 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1077 SDValue RetOp = getValue(I.getOperand(0));
1079 SmallVector<EVT, 4> ValueVTs;
1080 SmallVector<uint64_t, 4> Offsets;
1081 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1082 unsigned NumValues = ValueVTs.size();
1084 SmallVector<SDValue, 4> Chains(NumValues);
1085 for (unsigned i = 0; i != NumValues; ++i) {
1086 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1087 RetPtr.getValueType(), RetPtr,
1088 DAG.getIntPtrConstant(Offsets[i]));
1090 DAG.getStore(Chain, getCurDebugLoc(),
1091 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1092 // FIXME: better loc info would be nice.
1093 Add, MachinePointerInfo(), false, false, 0);
1096 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1097 MVT::Other, &Chains[0], NumValues);
1098 } else if (I.getNumOperands() != 0) {
1099 SmallVector<EVT, 4> ValueVTs;
1100 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1101 unsigned NumValues = ValueVTs.size();
1103 SDValue RetOp = getValue(I.getOperand(0));
1104 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1105 EVT VT = ValueVTs[j];
1107 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1109 const Function *F = I.getParent()->getParent();
1110 if (F->paramHasAttr(0, Attribute::SExt))
1111 ExtendKind = ISD::SIGN_EXTEND;
1112 else if (F->paramHasAttr(0, Attribute::ZExt))
1113 ExtendKind = ISD::ZERO_EXTEND;
1115 // FIXME: C calling convention requires the return type to be promoted
1116 // to at least 32-bit. But this is not necessary for non-C calling
1117 // conventions. The frontend should mark functions whose return values
1118 // require promoting with signext or zeroext attributes.
1119 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1120 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1121 if (VT.bitsLT(MinVT))
1125 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1126 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1127 SmallVector<SDValue, 4> Parts(NumParts);
1128 getCopyToParts(DAG, getCurDebugLoc(),
1129 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1130 &Parts[0], NumParts, PartVT, ExtendKind);
1132 // 'inreg' on function refers to return value
1133 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1134 if (F->paramHasAttr(0, Attribute::InReg))
1137 // Propagate extension type if any
1138 if (F->paramHasAttr(0, Attribute::SExt))
1140 else if (F->paramHasAttr(0, Attribute::ZExt))
1143 for (unsigned i = 0; i < NumParts; ++i) {
1144 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1146 OutVals.push_back(Parts[i]);
1152 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1153 CallingConv::ID CallConv =
1154 DAG.getMachineFunction().getFunction()->getCallingConv();
1155 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1156 Outs, OutVals, getCurDebugLoc(), DAG);
1158 // Verify that the target's LowerReturn behaved as expected.
1159 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1160 "LowerReturn didn't return a valid chain!");
1162 // Update the DAG with the new chain value resulting from return lowering.
1166 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1167 /// created for it, emit nodes to copy the value into the virtual
1169 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1170 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1171 if (VMI != FuncInfo.ValueMap.end()) {
1172 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1173 CopyValueToVirtualRegister(V, VMI->second);
1177 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1178 /// the current basic block, add it to ValueMap now so that we'll get a
1180 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1181 // No need to export constants.
1182 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1184 // Already exported?
1185 if (FuncInfo.isExportedInst(V)) return;
1187 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1188 CopyValueToVirtualRegister(V, Reg);
1191 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1192 const BasicBlock *FromBB) {
1193 // The operands of the setcc have to be in this block. We don't know
1194 // how to export them from some other block.
1195 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1196 // Can export from current BB.
1197 if (VI->getParent() == FromBB)
1200 // Is already exported, noop.
1201 return FuncInfo.isExportedInst(V);
1204 // If this is an argument, we can export it if the BB is the entry block or
1205 // if it is already exported.
1206 if (isa<Argument>(V)) {
1207 if (FromBB == &FromBB->getParent()->getEntryBlock())
1210 // Otherwise, can only export this if it is already exported.
1211 return FuncInfo.isExportedInst(V);
1214 // Otherwise, constants can always be exported.
1218 static bool InBlock(const Value *V, const BasicBlock *BB) {
1219 if (const Instruction *I = dyn_cast<Instruction>(V))
1220 return I->getParent() == BB;
1224 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1225 /// This function emits a branch and is used at the leaves of an OR or an
1226 /// AND operator tree.
1229 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1230 MachineBasicBlock *TBB,
1231 MachineBasicBlock *FBB,
1232 MachineBasicBlock *CurBB,
1233 MachineBasicBlock *SwitchBB) {
1234 const BasicBlock *BB = CurBB->getBasicBlock();
1236 // If the leaf of the tree is a comparison, merge the condition into
1238 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1239 // The operands of the cmp have to be in this block. We don't know
1240 // how to export them from some other block. If this is the first block
1241 // of the sequence, no exporting is needed.
1242 if (CurBB == SwitchBB ||
1243 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1244 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1245 ISD::CondCode Condition;
1246 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1247 Condition = getICmpCondCode(IC->getPredicate());
1248 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1249 Condition = getFCmpCondCode(FC->getPredicate());
1251 Condition = ISD::SETEQ; // silence warning.
1252 llvm_unreachable("Unknown compare instruction");
1255 CaseBlock CB(Condition, BOp->getOperand(0),
1256 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1257 SwitchCases.push_back(CB);
1262 // Create a CaseBlock record representing this branch.
1263 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1264 NULL, TBB, FBB, CurBB);
1265 SwitchCases.push_back(CB);
1268 /// FindMergedConditions - If Cond is an expression like
1269 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1270 MachineBasicBlock *TBB,
1271 MachineBasicBlock *FBB,
1272 MachineBasicBlock *CurBB,
1273 MachineBasicBlock *SwitchBB,
1275 // If this node is not part of the or/and tree, emit it as a branch.
1276 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1277 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1278 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1279 BOp->getParent() != CurBB->getBasicBlock() ||
1280 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1281 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1282 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1286 // Create TmpBB after CurBB.
1287 MachineFunction::iterator BBI = CurBB;
1288 MachineFunction &MF = DAG.getMachineFunction();
1289 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1290 CurBB->getParent()->insert(++BBI, TmpBB);
1292 if (Opc == Instruction::Or) {
1293 // Codegen X | Y as:
1301 // Emit the LHS condition.
1302 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1304 // Emit the RHS condition into TmpBB.
1305 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1307 assert(Opc == Instruction::And && "Unknown merge op!");
1308 // Codegen X & Y as:
1315 // This requires creation of TmpBB after CurBB.
1317 // Emit the LHS condition.
1318 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1320 // Emit the RHS condition into TmpBB.
1321 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1325 /// If the set of cases should be emitted as a series of branches, return true.
1326 /// If we should emit this as a bunch of and/or'd together conditions, return
1329 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1330 if (Cases.size() != 2) return true;
1332 // If this is two comparisons of the same values or'd or and'd together, they
1333 // will get folded into a single comparison, so don't emit two blocks.
1334 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1335 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1336 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1337 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1341 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1342 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1343 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1344 Cases[0].CC == Cases[1].CC &&
1345 isa<Constant>(Cases[0].CmpRHS) &&
1346 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1347 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1349 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1356 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1357 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1359 // Update machine-CFG edges.
1360 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1362 // Figure out which block is immediately after the current one.
1363 MachineBasicBlock *NextBlock = 0;
1364 MachineFunction::iterator BBI = BrMBB;
1365 if (++BBI != FuncInfo.MF->end())
1368 if (I.isUnconditional()) {
1369 // Update machine-CFG edges.
1370 BrMBB->addSuccessor(Succ0MBB);
1372 // If this is not a fall-through branch, emit the branch.
1373 if (Succ0MBB != NextBlock)
1374 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1375 MVT::Other, getControlRoot(),
1376 DAG.getBasicBlock(Succ0MBB)));
1381 // If this condition is one of the special cases we handle, do special stuff
1383 const Value *CondVal = I.getCondition();
1384 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1386 // If this is a series of conditions that are or'd or and'd together, emit
1387 // this as a sequence of branches instead of setcc's with and/or operations.
1388 // For example, instead of something like:
1401 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1402 if (BOp->hasOneUse() &&
1403 (BOp->getOpcode() == Instruction::And ||
1404 BOp->getOpcode() == Instruction::Or)) {
1405 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1407 // If the compares in later blocks need to use values not currently
1408 // exported from this block, export them now. This block should always
1409 // be the first entry.
1410 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1412 // Allow some cases to be rejected.
1413 if (ShouldEmitAsBranches(SwitchCases)) {
1414 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1415 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1416 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1419 // Emit the branch for this block.
1420 visitSwitchCase(SwitchCases[0], BrMBB);
1421 SwitchCases.erase(SwitchCases.begin());
1425 // Okay, we decided not to do this, remove any inserted MBB's and clear
1427 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1428 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1430 SwitchCases.clear();
1434 // Create a CaseBlock record representing this branch.
1435 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1436 NULL, Succ0MBB, Succ1MBB, BrMBB);
1438 // Use visitSwitchCase to actually insert the fast branch sequence for this
1440 visitSwitchCase(CB, BrMBB);
1443 /// visitSwitchCase - Emits the necessary code to represent a single node in
1444 /// the binary search tree resulting from lowering a switch instruction.
1445 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1446 MachineBasicBlock *SwitchBB) {
1448 SDValue CondLHS = getValue(CB.CmpLHS);
1449 DebugLoc dl = getCurDebugLoc();
1451 // Build the setcc now.
1452 if (CB.CmpMHS == NULL) {
1453 // Fold "(X == true)" to X and "(X == false)" to !X to
1454 // handle common cases produced by branch lowering.
1455 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1456 CB.CC == ISD::SETEQ)
1458 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1459 CB.CC == ISD::SETEQ) {
1460 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1461 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1463 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1465 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1467 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1468 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1470 SDValue CmpOp = getValue(CB.CmpMHS);
1471 EVT VT = CmpOp.getValueType();
1473 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1474 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1477 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1478 VT, CmpOp, DAG.getConstant(Low, VT));
1479 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1480 DAG.getConstant(High-Low, VT), ISD::SETULE);
1484 // Update successor info
1485 SwitchBB->addSuccessor(CB.TrueBB);
1486 SwitchBB->addSuccessor(CB.FalseBB);
1488 // Set NextBlock to be the MBB immediately after the current one, if any.
1489 // This is used to avoid emitting unnecessary branches to the next block.
1490 MachineBasicBlock *NextBlock = 0;
1491 MachineFunction::iterator BBI = SwitchBB;
1492 if (++BBI != FuncInfo.MF->end())
1495 // If the lhs block is the next block, invert the condition so that we can
1496 // fall through to the lhs instead of the rhs block.
1497 if (CB.TrueBB == NextBlock) {
1498 std::swap(CB.TrueBB, CB.FalseBB);
1499 SDValue True = DAG.getConstant(1, Cond.getValueType());
1500 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1503 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1504 MVT::Other, getControlRoot(), Cond,
1505 DAG.getBasicBlock(CB.TrueBB));
1507 // Insert the false branch. Do this even if it's a fall through branch,
1508 // this makes it easier to do DAG optimizations which require inverting
1509 // the branch condition.
1510 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1511 DAG.getBasicBlock(CB.FalseBB));
1513 DAG.setRoot(BrCond);
1516 /// visitJumpTable - Emit JumpTable node in the current MBB
1517 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1518 // Emit the code for the jump table
1519 assert(JT.Reg != -1U && "Should lower JT Header first!");
1520 EVT PTy = TLI.getPointerTy();
1521 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1523 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1524 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1525 MVT::Other, Index.getValue(1),
1527 DAG.setRoot(BrJumpTable);
1530 /// visitJumpTableHeader - This function emits necessary code to produce index
1531 /// in the JumpTable from switch case.
1532 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1533 JumpTableHeader &JTH,
1534 MachineBasicBlock *SwitchBB) {
1535 // Subtract the lowest switch case value from the value being switched on and
1536 // conditional branch to default mbb if the result is greater than the
1537 // difference between smallest and largest cases.
1538 SDValue SwitchOp = getValue(JTH.SValue);
1539 EVT VT = SwitchOp.getValueType();
1540 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1541 DAG.getConstant(JTH.First, VT));
1543 // The SDNode we just created, which holds the value being switched on minus
1544 // the smallest case value, needs to be copied to a virtual register so it
1545 // can be used as an index into the jump table in a subsequent basic block.
1546 // This value may be smaller or larger than the target's pointer type, and
1547 // therefore require extension or truncating.
1548 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1550 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1551 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1552 JumpTableReg, SwitchOp);
1553 JT.Reg = JumpTableReg;
1555 // Emit the range check for the jump table, and branch to the default block
1556 // for the switch statement if the value being switched on exceeds the largest
1557 // case in the switch.
1558 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1559 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1560 DAG.getConstant(JTH.Last-JTH.First,VT),
1563 // Set NextBlock to be the MBB immediately after the current one, if any.
1564 // This is used to avoid emitting unnecessary branches to the next block.
1565 MachineBasicBlock *NextBlock = 0;
1566 MachineFunction::iterator BBI = SwitchBB;
1568 if (++BBI != FuncInfo.MF->end())
1571 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1572 MVT::Other, CopyTo, CMP,
1573 DAG.getBasicBlock(JT.Default));
1575 if (JT.MBB != NextBlock)
1576 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1577 DAG.getBasicBlock(JT.MBB));
1579 DAG.setRoot(BrCond);
1582 /// visitBitTestHeader - This function emits necessary code to produce value
1583 /// suitable for "bit tests"
1584 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1585 MachineBasicBlock *SwitchBB) {
1586 // Subtract the minimum value
1587 SDValue SwitchOp = getValue(B.SValue);
1588 EVT VT = SwitchOp.getValueType();
1589 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1590 DAG.getConstant(B.First, VT));
1593 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1594 TLI.getSetCCResultType(Sub.getValueType()),
1595 Sub, DAG.getConstant(B.Range, VT),
1598 SDValue ShiftOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(),
1599 TLI.getPointerTy());
1601 B.Reg = FuncInfo.CreateReg(TLI.getPointerTy());
1602 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1605 // Set NextBlock to be the MBB immediately after the current one, if any.
1606 // This is used to avoid emitting unnecessary branches to the next block.
1607 MachineBasicBlock *NextBlock = 0;
1608 MachineFunction::iterator BBI = SwitchBB;
1609 if (++BBI != FuncInfo.MF->end())
1612 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1614 SwitchBB->addSuccessor(B.Default);
1615 SwitchBB->addSuccessor(MBB);
1617 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1618 MVT::Other, CopyTo, RangeCmp,
1619 DAG.getBasicBlock(B.Default));
1621 if (MBB != NextBlock)
1622 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1623 DAG.getBasicBlock(MBB));
1625 DAG.setRoot(BrRange);
1628 /// visitBitTestCase - this function produces one "bit test"
1629 void SelectionDAGBuilder::visitBitTestCase(MachineBasicBlock* NextMBB,
1632 MachineBasicBlock *SwitchBB) {
1633 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), Reg,
1634 TLI.getPointerTy());
1636 if (CountPopulation_64(B.Mask) == 1) {
1637 // Testing for a single bit; just compare the shift count with what it
1638 // would need to be to shift a 1 bit in that position.
1639 Cmp = DAG.getSetCC(getCurDebugLoc(),
1640 TLI.getSetCCResultType(ShiftOp.getValueType()),
1642 DAG.getConstant(CountTrailingZeros_64(B.Mask),
1643 TLI.getPointerTy()),
1646 // Make desired shift
1647 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(),
1649 DAG.getConstant(1, TLI.getPointerTy()),
1652 // Emit bit tests and jumps
1653 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1654 TLI.getPointerTy(), SwitchVal,
1655 DAG.getConstant(B.Mask, TLI.getPointerTy()));
1656 Cmp = DAG.getSetCC(getCurDebugLoc(),
1657 TLI.getSetCCResultType(AndOp.getValueType()),
1658 AndOp, DAG.getConstant(0, TLI.getPointerTy()),
1662 SwitchBB->addSuccessor(B.TargetBB);
1663 SwitchBB->addSuccessor(NextMBB);
1665 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1666 MVT::Other, getControlRoot(),
1667 Cmp, DAG.getBasicBlock(B.TargetBB));
1669 // Set NextBlock to be the MBB immediately after the current one, if any.
1670 // This is used to avoid emitting unnecessary branches to the next block.
1671 MachineBasicBlock *NextBlock = 0;
1672 MachineFunction::iterator BBI = SwitchBB;
1673 if (++BBI != FuncInfo.MF->end())
1676 if (NextMBB != NextBlock)
1677 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1678 DAG.getBasicBlock(NextMBB));
1683 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1684 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1686 // Retrieve successors.
1687 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1688 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1690 const Value *Callee(I.getCalledValue());
1691 if (isa<InlineAsm>(Callee))
1694 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1696 // If the value of the invoke is used outside of its defining block, make it
1697 // available as a virtual register.
1698 CopyToExportRegsIfNeeded(&I);
1700 // Update successor info
1701 InvokeMBB->addSuccessor(Return);
1702 InvokeMBB->addSuccessor(LandingPad);
1704 // Drop into normal successor.
1705 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1706 MVT::Other, getControlRoot(),
1707 DAG.getBasicBlock(Return)));
1710 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1713 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1714 /// small case ranges).
1715 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1716 CaseRecVector& WorkList,
1718 MachineBasicBlock *Default,
1719 MachineBasicBlock *SwitchBB) {
1720 Case& BackCase = *(CR.Range.second-1);
1722 // Size is the number of Cases represented by this range.
1723 size_t Size = CR.Range.second - CR.Range.first;
1727 // Get the MachineFunction which holds the current MBB. This is used when
1728 // inserting any additional MBBs necessary to represent the switch.
1729 MachineFunction *CurMF = FuncInfo.MF;
1731 // Figure out which block is immediately after the current one.
1732 MachineBasicBlock *NextBlock = 0;
1733 MachineFunction::iterator BBI = CR.CaseBB;
1735 if (++BBI != FuncInfo.MF->end())
1738 // TODO: If any two of the cases has the same destination, and if one value
1739 // is the same as the other, but has one bit unset that the other has set,
1740 // use bit manipulation to do two compares at once. For example:
1741 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1743 // Rearrange the case blocks so that the last one falls through if possible.
1744 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1745 // The last case block won't fall through into 'NextBlock' if we emit the
1746 // branches in this order. See if rearranging a case value would help.
1747 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1748 if (I->BB == NextBlock) {
1749 std::swap(*I, BackCase);
1755 // Create a CaseBlock record representing a conditional branch to
1756 // the Case's target mbb if the value being switched on SV is equal
1758 MachineBasicBlock *CurBlock = CR.CaseBB;
1759 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1760 MachineBasicBlock *FallThrough;
1762 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1763 CurMF->insert(BBI, FallThrough);
1765 // Put SV in a virtual register to make it available from the new blocks.
1766 ExportFromCurrentBlock(SV);
1768 // If the last case doesn't match, go to the default block.
1769 FallThrough = Default;
1772 const Value *RHS, *LHS, *MHS;
1774 if (I->High == I->Low) {
1775 // This is just small small case range :) containing exactly 1 case
1777 LHS = SV; RHS = I->High; MHS = NULL;
1780 LHS = I->Low; MHS = SV; RHS = I->High;
1782 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1784 // If emitting the first comparison, just call visitSwitchCase to emit the
1785 // code into the current block. Otherwise, push the CaseBlock onto the
1786 // vector to be later processed by SDISel, and insert the node's MBB
1787 // before the next MBB.
1788 if (CurBlock == SwitchBB)
1789 visitSwitchCase(CB, SwitchBB);
1791 SwitchCases.push_back(CB);
1793 CurBlock = FallThrough;
1799 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1800 return !DisableJumpTables &&
1801 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1802 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1805 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1806 APInt LastExt(Last), FirstExt(First);
1807 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1808 LastExt.sext(BitWidth); FirstExt.sext(BitWidth);
1809 return (LastExt - FirstExt + 1ULL);
1812 /// handleJTSwitchCase - Emit jumptable for current switch case range
1813 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1814 CaseRecVector& WorkList,
1816 MachineBasicBlock* Default,
1817 MachineBasicBlock *SwitchBB) {
1818 Case& FrontCase = *CR.Range.first;
1819 Case& BackCase = *(CR.Range.second-1);
1821 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1822 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1824 APInt TSize(First.getBitWidth(), 0);
1825 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1829 if (!areJTsAllowed(TLI) || TSize.ult(4))
1832 APInt Range = ComputeRange(First, Last);
1833 double Density = TSize.roundToDouble() / Range.roundToDouble();
1837 DEBUG(dbgs() << "Lowering jump table\n"
1838 << "First entry: " << First << ". Last entry: " << Last << '\n'
1839 << "Range: " << Range
1840 << "Size: " << TSize << ". Density: " << Density << "\n\n");
1842 // Get the MachineFunction which holds the current MBB. This is used when
1843 // inserting any additional MBBs necessary to represent the switch.
1844 MachineFunction *CurMF = FuncInfo.MF;
1846 // Figure out which block is immediately after the current one.
1847 MachineFunction::iterator BBI = CR.CaseBB;
1850 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1852 // Create a new basic block to hold the code for loading the address
1853 // of the jump table, and jumping to it. Update successor information;
1854 // we will either branch to the default case for the switch, or the jump
1856 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1857 CurMF->insert(BBI, JumpTableBB);
1858 CR.CaseBB->addSuccessor(Default);
1859 CR.CaseBB->addSuccessor(JumpTableBB);
1861 // Build a vector of destination BBs, corresponding to each target
1862 // of the jump table. If the value of the jump table slot corresponds to
1863 // a case statement, push the case's BB onto the vector, otherwise, push
1865 std::vector<MachineBasicBlock*> DestBBs;
1867 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1868 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1869 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1871 if (Low.sle(TEI) && TEI.sle(High)) {
1872 DestBBs.push_back(I->BB);
1876 DestBBs.push_back(Default);
1880 // Update successor info. Add one edge to each unique successor.
1881 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1882 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1883 E = DestBBs.end(); I != E; ++I) {
1884 if (!SuccsHandled[(*I)->getNumber()]) {
1885 SuccsHandled[(*I)->getNumber()] = true;
1886 JumpTableBB->addSuccessor(*I);
1890 // Create a jump table index for this jump table.
1891 unsigned JTEncoding = TLI.getJumpTableEncoding();
1892 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1893 ->createJumpTableIndex(DestBBs);
1895 // Set the jump table information so that we can codegen it as a second
1896 // MachineBasicBlock
1897 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1898 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1899 if (CR.CaseBB == SwitchBB)
1900 visitJumpTableHeader(JT, JTH, SwitchBB);
1902 JTCases.push_back(JumpTableBlock(JTH, JT));
1907 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1909 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1910 CaseRecVector& WorkList,
1912 MachineBasicBlock *Default,
1913 MachineBasicBlock *SwitchBB) {
1914 // Get the MachineFunction which holds the current MBB. This is used when
1915 // inserting any additional MBBs necessary to represent the switch.
1916 MachineFunction *CurMF = FuncInfo.MF;
1918 // Figure out which block is immediately after the current one.
1919 MachineFunction::iterator BBI = CR.CaseBB;
1922 Case& FrontCase = *CR.Range.first;
1923 Case& BackCase = *(CR.Range.second-1);
1924 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1926 // Size is the number of Cases represented by this range.
1927 unsigned Size = CR.Range.second - CR.Range.first;
1929 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1930 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1932 CaseItr Pivot = CR.Range.first + Size/2;
1934 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
1935 // (heuristically) allow us to emit JumpTable's later.
1936 APInt TSize(First.getBitWidth(), 0);
1937 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1941 APInt LSize = FrontCase.size();
1942 APInt RSize = TSize-LSize;
1943 DEBUG(dbgs() << "Selecting best pivot: \n"
1944 << "First: " << First << ", Last: " << Last <<'\n'
1945 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
1946 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
1948 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
1949 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
1950 APInt Range = ComputeRange(LEnd, RBegin);
1951 assert((Range - 2ULL).isNonNegative() &&
1952 "Invalid case distance");
1953 double LDensity = (double)LSize.roundToDouble() /
1954 (LEnd - First + 1ULL).roundToDouble();
1955 double RDensity = (double)RSize.roundToDouble() /
1956 (Last - RBegin + 1ULL).roundToDouble();
1957 double Metric = Range.logBase2()*(LDensity+RDensity);
1958 // Should always split in some non-trivial place
1959 DEBUG(dbgs() <<"=>Step\n"
1960 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
1961 << "LDensity: " << LDensity
1962 << ", RDensity: " << RDensity << '\n'
1963 << "Metric: " << Metric << '\n');
1964 if (FMetric < Metric) {
1967 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
1973 if (areJTsAllowed(TLI)) {
1974 // If our case is dense we *really* should handle it earlier!
1975 assert((FMetric > 0) && "Should handle dense range earlier!");
1977 Pivot = CR.Range.first + Size/2;
1980 CaseRange LHSR(CR.Range.first, Pivot);
1981 CaseRange RHSR(Pivot, CR.Range.second);
1982 Constant *C = Pivot->Low;
1983 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
1985 // We know that we branch to the LHS if the Value being switched on is
1986 // less than the Pivot value, C. We use this to optimize our binary
1987 // tree a bit, by recognizing that if SV is greater than or equal to the
1988 // LHS's Case Value, and that Case Value is exactly one less than the
1989 // Pivot's Value, then we can branch directly to the LHS's Target,
1990 // rather than creating a leaf node for it.
1991 if ((LHSR.second - LHSR.first) == 1 &&
1992 LHSR.first->High == CR.GE &&
1993 cast<ConstantInt>(C)->getValue() ==
1994 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
1995 TrueBB = LHSR.first->BB;
1997 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1998 CurMF->insert(BBI, TrueBB);
1999 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2001 // Put SV in a virtual register to make it available from the new blocks.
2002 ExportFromCurrentBlock(SV);
2005 // Similar to the optimization above, if the Value being switched on is
2006 // known to be less than the Constant CR.LT, and the current Case Value
2007 // is CR.LT - 1, then we can branch directly to the target block for
2008 // the current Case Value, rather than emitting a RHS leaf node for it.
2009 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2010 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2011 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2012 FalseBB = RHSR.first->BB;
2014 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2015 CurMF->insert(BBI, FalseBB);
2016 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2018 // Put SV in a virtual register to make it available from the new blocks.
2019 ExportFromCurrentBlock(SV);
2022 // Create a CaseBlock record representing a conditional branch to
2023 // the LHS node if the value being switched on SV is less than C.
2024 // Otherwise, branch to LHS.
2025 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2027 if (CR.CaseBB == SwitchBB)
2028 visitSwitchCase(CB, SwitchBB);
2030 SwitchCases.push_back(CB);
2035 /// handleBitTestsSwitchCase - if current case range has few destination and
2036 /// range span less, than machine word bitwidth, encode case range into series
2037 /// of masks and emit bit tests with these masks.
2038 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2039 CaseRecVector& WorkList,
2041 MachineBasicBlock* Default,
2042 MachineBasicBlock *SwitchBB){
2043 EVT PTy = TLI.getPointerTy();
2044 unsigned IntPtrBits = PTy.getSizeInBits();
2046 Case& FrontCase = *CR.Range.first;
2047 Case& BackCase = *(CR.Range.second-1);
2049 // Get the MachineFunction which holds the current MBB. This is used when
2050 // inserting any additional MBBs necessary to represent the switch.
2051 MachineFunction *CurMF = FuncInfo.MF;
2053 // If target does not have legal shift left, do not emit bit tests at all.
2054 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2058 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2060 // Single case counts one, case range - two.
2061 numCmps += (I->Low == I->High ? 1 : 2);
2064 // Count unique destinations
2065 SmallSet<MachineBasicBlock*, 4> Dests;
2066 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2067 Dests.insert(I->BB);
2068 if (Dests.size() > 3)
2069 // Don't bother the code below, if there are too much unique destinations
2072 DEBUG(dbgs() << "Total number of unique destinations: "
2073 << Dests.size() << '\n'
2074 << "Total number of comparisons: " << numCmps << '\n');
2076 // Compute span of values.
2077 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2078 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2079 APInt cmpRange = maxValue - minValue;
2081 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2082 << "Low bound: " << minValue << '\n'
2083 << "High bound: " << maxValue << '\n');
2085 if (cmpRange.uge(IntPtrBits) ||
2086 (!(Dests.size() == 1 && numCmps >= 3) &&
2087 !(Dests.size() == 2 && numCmps >= 5) &&
2088 !(Dests.size() >= 3 && numCmps >= 6)))
2091 DEBUG(dbgs() << "Emitting bit tests\n");
2092 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2094 // Optimize the case where all the case values fit in a
2095 // word without having to subtract minValue. In this case,
2096 // we can optimize away the subtraction.
2097 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2098 cmpRange = maxValue;
2100 lowBound = minValue;
2103 CaseBitsVector CasesBits;
2104 unsigned i, count = 0;
2106 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2107 MachineBasicBlock* Dest = I->BB;
2108 for (i = 0; i < count; ++i)
2109 if (Dest == CasesBits[i].BB)
2113 assert((count < 3) && "Too much destinations to test!");
2114 CasesBits.push_back(CaseBits(0, Dest, 0));
2118 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2119 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2121 uint64_t lo = (lowValue - lowBound).getZExtValue();
2122 uint64_t hi = (highValue - lowBound).getZExtValue();
2124 for (uint64_t j = lo; j <= hi; j++) {
2125 CasesBits[i].Mask |= 1ULL << j;
2126 CasesBits[i].Bits++;
2130 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2134 // Figure out which block is immediately after the current one.
2135 MachineFunction::iterator BBI = CR.CaseBB;
2138 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2140 DEBUG(dbgs() << "Cases:\n");
2141 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2142 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2143 << ", Bits: " << CasesBits[i].Bits
2144 << ", BB: " << CasesBits[i].BB << '\n');
2146 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2147 CurMF->insert(BBI, CaseBB);
2148 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2152 // Put SV in a virtual register to make it available from the new blocks.
2153 ExportFromCurrentBlock(SV);
2156 BitTestBlock BTB(lowBound, cmpRange, SV,
2157 -1U, (CR.CaseBB == SwitchBB),
2158 CR.CaseBB, Default, BTC);
2160 if (CR.CaseBB == SwitchBB)
2161 visitBitTestHeader(BTB, SwitchBB);
2163 BitTestCases.push_back(BTB);
2168 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2169 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2170 const SwitchInst& SI) {
2173 // Start with "simple" cases
2174 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2175 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2176 Cases.push_back(Case(SI.getSuccessorValue(i),
2177 SI.getSuccessorValue(i),
2180 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2182 // Merge case into clusters
2183 if (Cases.size() >= 2)
2184 // Must recompute end() each iteration because it may be
2185 // invalidated by erase if we hold on to it
2186 for (CaseItr I = Cases.begin(), J = ++(Cases.begin()); J != Cases.end(); ) {
2187 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2188 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2189 MachineBasicBlock* nextBB = J->BB;
2190 MachineBasicBlock* currentBB = I->BB;
2192 // If the two neighboring cases go to the same destination, merge them
2193 // into a single case.
2194 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2202 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2203 if (I->Low != I->High)
2204 // A range counts double, since it requires two compares.
2211 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2212 MachineBasicBlock *Last) {
2214 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2215 if (JTCases[i].first.HeaderBB == First)
2216 JTCases[i].first.HeaderBB = Last;
2218 // Update BitTestCases.
2219 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2220 if (BitTestCases[i].Parent == First)
2221 BitTestCases[i].Parent = Last;
2224 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2225 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2227 // Figure out which block is immediately after the current one.
2228 MachineBasicBlock *NextBlock = 0;
2229 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2231 // If there is only the default destination, branch to it if it is not the
2232 // next basic block. Otherwise, just fall through.
2233 if (SI.getNumOperands() == 2) {
2234 // Update machine-CFG edges.
2236 // If this is not a fall-through branch, emit the branch.
2237 SwitchMBB->addSuccessor(Default);
2238 if (Default != NextBlock)
2239 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2240 MVT::Other, getControlRoot(),
2241 DAG.getBasicBlock(Default)));
2246 // If there are any non-default case statements, create a vector of Cases
2247 // representing each one, and sort the vector so that we can efficiently
2248 // create a binary search tree from them.
2250 size_t numCmps = Clusterify(Cases, SI);
2251 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2252 << ". Total compares: " << numCmps << '\n');
2255 // Get the Value to be switched on and default basic blocks, which will be
2256 // inserted into CaseBlock records, representing basic blocks in the binary
2258 const Value *SV = SI.getOperand(0);
2260 // Push the initial CaseRec onto the worklist
2261 CaseRecVector WorkList;
2262 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2263 CaseRange(Cases.begin(),Cases.end())));
2265 while (!WorkList.empty()) {
2266 // Grab a record representing a case range to process off the worklist
2267 CaseRec CR = WorkList.back();
2268 WorkList.pop_back();
2270 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2273 // If the range has few cases (two or less) emit a series of specific
2275 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2278 // If the switch has more than 5 blocks, and at least 40% dense, and the
2279 // target supports indirect branches, then emit a jump table rather than
2280 // lowering the switch to a binary tree of conditional branches.
2281 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2284 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2285 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2286 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2290 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2291 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2293 // Update machine-CFG edges with unique successors.
2294 SmallVector<BasicBlock*, 32> succs;
2295 succs.reserve(I.getNumSuccessors());
2296 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2297 succs.push_back(I.getSuccessor(i));
2298 array_pod_sort(succs.begin(), succs.end());
2299 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2300 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2301 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2303 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2304 MVT::Other, getControlRoot(),
2305 getValue(I.getAddress())));
2308 void SelectionDAGBuilder::visitFSub(const User &I) {
2309 // -0.0 - X --> fneg
2310 const Type *Ty = I.getType();
2311 if (Ty->isVectorTy()) {
2312 if (ConstantVector *CV = dyn_cast<ConstantVector>(I.getOperand(0))) {
2313 const VectorType *DestTy = cast<VectorType>(I.getType());
2314 const Type *ElTy = DestTy->getElementType();
2315 unsigned VL = DestTy->getNumElements();
2316 std::vector<Constant*> NZ(VL, ConstantFP::getNegativeZero(ElTy));
2317 Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size());
2319 SDValue Op2 = getValue(I.getOperand(1));
2320 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2321 Op2.getValueType(), Op2));
2327 if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
2328 if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) {
2329 SDValue Op2 = getValue(I.getOperand(1));
2330 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2331 Op2.getValueType(), Op2));
2335 visitBinary(I, ISD::FSUB);
2338 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2339 SDValue Op1 = getValue(I.getOperand(0));
2340 SDValue Op2 = getValue(I.getOperand(1));
2341 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2342 Op1.getValueType(), Op1, Op2));
2345 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2346 SDValue Op1 = getValue(I.getOperand(0));
2347 SDValue Op2 = getValue(I.getOperand(1));
2348 if (!I.getType()->isVectorTy() &&
2349 Op2.getValueType() != TLI.getShiftAmountTy()) {
2350 // If the operand is smaller than the shift count type, promote it.
2351 EVT PTy = TLI.getPointerTy();
2352 EVT STy = TLI.getShiftAmountTy();
2353 if (STy.bitsGT(Op2.getValueType()))
2354 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2355 TLI.getShiftAmountTy(), Op2);
2356 // If the operand is larger than the shift count type but the shift
2357 // count type has enough bits to represent any shift value, truncate
2358 // it now. This is a common case and it exposes the truncate to
2359 // optimization early.
2360 else if (STy.getSizeInBits() >=
2361 Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2362 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2363 TLI.getShiftAmountTy(), Op2);
2364 // Otherwise we'll need to temporarily settle for some other
2365 // convenient type; type legalization will make adjustments as
2367 else if (PTy.bitsLT(Op2.getValueType()))
2368 Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2369 TLI.getPointerTy(), Op2);
2370 else if (PTy.bitsGT(Op2.getValueType()))
2371 Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
2372 TLI.getPointerTy(), Op2);
2375 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2376 Op1.getValueType(), Op1, Op2));
2379 void SelectionDAGBuilder::visitICmp(const User &I) {
2380 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2381 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2382 predicate = IC->getPredicate();
2383 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2384 predicate = ICmpInst::Predicate(IC->getPredicate());
2385 SDValue Op1 = getValue(I.getOperand(0));
2386 SDValue Op2 = getValue(I.getOperand(1));
2387 ISD::CondCode Opcode = getICmpCondCode(predicate);
2389 EVT DestVT = TLI.getValueType(I.getType());
2390 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2393 void SelectionDAGBuilder::visitFCmp(const User &I) {
2394 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2395 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2396 predicate = FC->getPredicate();
2397 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2398 predicate = FCmpInst::Predicate(FC->getPredicate());
2399 SDValue Op1 = getValue(I.getOperand(0));
2400 SDValue Op2 = getValue(I.getOperand(1));
2401 ISD::CondCode Condition = getFCmpCondCode(predicate);
2402 EVT DestVT = TLI.getValueType(I.getType());
2403 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2406 void SelectionDAGBuilder::visitSelect(const User &I) {
2407 SmallVector<EVT, 4> ValueVTs;
2408 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2409 unsigned NumValues = ValueVTs.size();
2410 if (NumValues == 0) return;
2412 SmallVector<SDValue, 4> Values(NumValues);
2413 SDValue Cond = getValue(I.getOperand(0));
2414 SDValue TrueVal = getValue(I.getOperand(1));
2415 SDValue FalseVal = getValue(I.getOperand(2));
2417 for (unsigned i = 0; i != NumValues; ++i)
2418 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2419 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2421 SDValue(TrueVal.getNode(),
2422 TrueVal.getResNo() + i),
2423 SDValue(FalseVal.getNode(),
2424 FalseVal.getResNo() + i));
2426 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2427 DAG.getVTList(&ValueVTs[0], NumValues),
2428 &Values[0], NumValues));
2431 void SelectionDAGBuilder::visitTrunc(const User &I) {
2432 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2433 SDValue N = getValue(I.getOperand(0));
2434 EVT DestVT = TLI.getValueType(I.getType());
2435 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2438 void SelectionDAGBuilder::visitZExt(const User &I) {
2439 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2440 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2441 SDValue N = getValue(I.getOperand(0));
2442 EVT DestVT = TLI.getValueType(I.getType());
2443 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2446 void SelectionDAGBuilder::visitSExt(const User &I) {
2447 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2448 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2449 SDValue N = getValue(I.getOperand(0));
2450 EVT DestVT = TLI.getValueType(I.getType());
2451 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2454 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2455 // FPTrunc is never a no-op cast, no need to check
2456 SDValue N = getValue(I.getOperand(0));
2457 EVT DestVT = TLI.getValueType(I.getType());
2458 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2459 DestVT, N, DAG.getIntPtrConstant(0)));
2462 void SelectionDAGBuilder::visitFPExt(const User &I){
2463 // FPTrunc is never a no-op cast, no need to check
2464 SDValue N = getValue(I.getOperand(0));
2465 EVT DestVT = TLI.getValueType(I.getType());
2466 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2469 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2470 // FPToUI is never a no-op cast, no need to check
2471 SDValue N = getValue(I.getOperand(0));
2472 EVT DestVT = TLI.getValueType(I.getType());
2473 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2476 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2477 // FPToSI is never a no-op cast, no need to check
2478 SDValue N = getValue(I.getOperand(0));
2479 EVT DestVT = TLI.getValueType(I.getType());
2480 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2483 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2484 // UIToFP is never a no-op cast, no need to check
2485 SDValue N = getValue(I.getOperand(0));
2486 EVT DestVT = TLI.getValueType(I.getType());
2487 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2490 void SelectionDAGBuilder::visitSIToFP(const User &I){
2491 // SIToFP is never a no-op cast, no need to check
2492 SDValue N = getValue(I.getOperand(0));
2493 EVT DestVT = TLI.getValueType(I.getType());
2494 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2497 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2498 // What to do depends on the size of the integer and the size of the pointer.
2499 // We can either truncate, zero extend, or no-op, accordingly.
2500 SDValue N = getValue(I.getOperand(0));
2501 EVT DestVT = TLI.getValueType(I.getType());
2502 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2505 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2506 // What to do depends on the size of the integer and the size of the pointer.
2507 // We can either truncate, zero extend, or no-op, accordingly.
2508 SDValue N = getValue(I.getOperand(0));
2509 EVT DestVT = TLI.getValueType(I.getType());
2510 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2513 void SelectionDAGBuilder::visitBitCast(const User &I) {
2514 SDValue N = getValue(I.getOperand(0));
2515 EVT DestVT = TLI.getValueType(I.getType());
2517 // BitCast assures us that source and destination are the same size so this is
2518 // either a BIT_CONVERT or a no-op.
2519 if (DestVT != N.getValueType())
2520 setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
2521 DestVT, N)); // convert types.
2523 setValue(&I, N); // noop cast.
2526 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2527 SDValue InVec = getValue(I.getOperand(0));
2528 SDValue InVal = getValue(I.getOperand(1));
2529 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2531 getValue(I.getOperand(2)));
2532 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2533 TLI.getValueType(I.getType()),
2534 InVec, InVal, InIdx));
2537 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2538 SDValue InVec = getValue(I.getOperand(0));
2539 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2541 getValue(I.getOperand(1)));
2542 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2543 TLI.getValueType(I.getType()), InVec, InIdx));
2546 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2547 // from SIndx and increasing to the element length (undefs are allowed).
2548 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2549 unsigned MaskNumElts = Mask.size();
2550 for (unsigned i = 0; i != MaskNumElts; ++i)
2551 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2556 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2557 SmallVector<int, 8> Mask;
2558 SDValue Src1 = getValue(I.getOperand(0));
2559 SDValue Src2 = getValue(I.getOperand(1));
2561 // Convert the ConstantVector mask operand into an array of ints, with -1
2562 // representing undef values.
2563 SmallVector<Constant*, 8> MaskElts;
2564 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2565 unsigned MaskNumElts = MaskElts.size();
2566 for (unsigned i = 0; i != MaskNumElts; ++i) {
2567 if (isa<UndefValue>(MaskElts[i]))
2570 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2573 EVT VT = TLI.getValueType(I.getType());
2574 EVT SrcVT = Src1.getValueType();
2575 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2577 if (SrcNumElts == MaskNumElts) {
2578 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2583 // Normalize the shuffle vector since mask and vector length don't match.
2584 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2585 // Mask is longer than the source vectors and is a multiple of the source
2586 // vectors. We can use concatenate vector to make the mask and vectors
2588 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2589 // The shuffle is concatenating two vectors together.
2590 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2595 // Pad both vectors with undefs to make them the same length as the mask.
2596 unsigned NumConcat = MaskNumElts / SrcNumElts;
2597 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2598 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2599 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2601 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2602 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2606 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2607 getCurDebugLoc(), VT,
2608 &MOps1[0], NumConcat);
2609 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2610 getCurDebugLoc(), VT,
2611 &MOps2[0], NumConcat);
2613 // Readjust mask for new input vector length.
2614 SmallVector<int, 8> MappedOps;
2615 for (unsigned i = 0; i != MaskNumElts; ++i) {
2617 if (Idx < (int)SrcNumElts)
2618 MappedOps.push_back(Idx);
2620 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2623 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2628 if (SrcNumElts > MaskNumElts) {
2629 // Analyze the access pattern of the vector to see if we can extract
2630 // two subvectors and do the shuffle. The analysis is done by calculating
2631 // the range of elements the mask access on both vectors.
2632 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2633 int MaxRange[2] = {-1, -1};
2635 for (unsigned i = 0; i != MaskNumElts; ++i) {
2641 if (Idx >= (int)SrcNumElts) {
2645 if (Idx > MaxRange[Input])
2646 MaxRange[Input] = Idx;
2647 if (Idx < MinRange[Input])
2648 MinRange[Input] = Idx;
2651 // Check if the access is smaller than the vector size and can we find
2652 // a reasonable extract index.
2653 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2655 int StartIdx[2]; // StartIdx to extract from
2656 for (int Input=0; Input < 2; ++Input) {
2657 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2658 RangeUse[Input] = 0; // Unused
2659 StartIdx[Input] = 0;
2660 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2661 // Fits within range but we should see if we can find a good
2662 // start index that is a multiple of the mask length.
2663 if (MaxRange[Input] < (int)MaskNumElts) {
2664 RangeUse[Input] = 1; // Extract from beginning of the vector
2665 StartIdx[Input] = 0;
2667 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2668 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2669 StartIdx[Input] + MaskNumElts < SrcNumElts)
2670 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2675 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2676 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2679 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2680 // Extract appropriate subvector and generate a vector shuffle
2681 for (int Input=0; Input < 2; ++Input) {
2682 SDValue &Src = Input == 0 ? Src1 : Src2;
2683 if (RangeUse[Input] == 0)
2684 Src = DAG.getUNDEF(VT);
2686 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2687 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2690 // Calculate new mask.
2691 SmallVector<int, 8> MappedOps;
2692 for (unsigned i = 0; i != MaskNumElts; ++i) {
2695 MappedOps.push_back(Idx);
2696 else if (Idx < (int)SrcNumElts)
2697 MappedOps.push_back(Idx - StartIdx[0]);
2699 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2702 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2708 // We can't use either concat vectors or extract subvectors so fall back to
2709 // replacing the shuffle with extract and build vector.
2710 // to insert and build vector.
2711 EVT EltVT = VT.getVectorElementType();
2712 EVT PtrVT = TLI.getPointerTy();
2713 SmallVector<SDValue,8> Ops;
2714 for (unsigned i = 0; i != MaskNumElts; ++i) {
2716 Ops.push_back(DAG.getUNDEF(EltVT));
2721 if (Idx < (int)SrcNumElts)
2722 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2723 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2725 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2727 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2733 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2734 VT, &Ops[0], Ops.size()));
2737 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2738 const Value *Op0 = I.getOperand(0);
2739 const Value *Op1 = I.getOperand(1);
2740 const Type *AggTy = I.getType();
2741 const Type *ValTy = Op1->getType();
2742 bool IntoUndef = isa<UndefValue>(Op0);
2743 bool FromUndef = isa<UndefValue>(Op1);
2745 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2747 SmallVector<EVT, 4> AggValueVTs;
2748 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2749 SmallVector<EVT, 4> ValValueVTs;
2750 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2752 unsigned NumAggValues = AggValueVTs.size();
2753 unsigned NumValValues = ValValueVTs.size();
2754 SmallVector<SDValue, 4> Values(NumAggValues);
2756 SDValue Agg = getValue(Op0);
2757 SDValue Val = getValue(Op1);
2759 // Copy the beginning value(s) from the original aggregate.
2760 for (; i != LinearIndex; ++i)
2761 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2762 SDValue(Agg.getNode(), Agg.getResNo() + i);
2763 // Copy values from the inserted value(s).
2764 for (; i != LinearIndex + NumValValues; ++i)
2765 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2766 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2767 // Copy remaining value(s) from the original aggregate.
2768 for (; i != NumAggValues; ++i)
2769 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2770 SDValue(Agg.getNode(), Agg.getResNo() + i);
2772 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2773 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2774 &Values[0], NumAggValues));
2777 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2778 const Value *Op0 = I.getOperand(0);
2779 const Type *AggTy = Op0->getType();
2780 const Type *ValTy = I.getType();
2781 bool OutOfUndef = isa<UndefValue>(Op0);
2783 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2785 SmallVector<EVT, 4> ValValueVTs;
2786 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2788 unsigned NumValValues = ValValueVTs.size();
2789 SmallVector<SDValue, 4> Values(NumValValues);
2791 SDValue Agg = getValue(Op0);
2792 // Copy out the selected value(s).
2793 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2794 Values[i - LinearIndex] =
2796 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2797 SDValue(Agg.getNode(), Agg.getResNo() + i);
2799 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2800 DAG.getVTList(&ValValueVTs[0], NumValValues),
2801 &Values[0], NumValValues));
2804 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2805 SDValue N = getValue(I.getOperand(0));
2806 const Type *Ty = I.getOperand(0)->getType();
2808 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2810 const Value *Idx = *OI;
2811 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2812 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2815 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2816 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2817 DAG.getIntPtrConstant(Offset));
2820 Ty = StTy->getElementType(Field);
2822 Ty = cast<SequentialType>(Ty)->getElementType();
2824 // If this is a constant subscript, handle it quickly.
2825 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2826 if (CI->isZero()) continue;
2828 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2830 EVT PTy = TLI.getPointerTy();
2831 unsigned PtrBits = PTy.getSizeInBits();
2833 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2835 DAG.getConstant(Offs, MVT::i64));
2837 OffsVal = DAG.getIntPtrConstant(Offs);
2839 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2844 // N = N + Idx * ElementSize;
2845 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2846 TD->getTypeAllocSize(Ty));
2847 SDValue IdxN = getValue(Idx);
2849 // If the index is smaller or larger than intptr_t, truncate or extend
2851 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2853 // If this is a multiply by a power of two, turn it into a shl
2854 // immediately. This is a very common case.
2855 if (ElementSize != 1) {
2856 if (ElementSize.isPowerOf2()) {
2857 unsigned Amt = ElementSize.logBase2();
2858 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2859 N.getValueType(), IdxN,
2860 DAG.getConstant(Amt, TLI.getPointerTy()));
2862 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2863 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2864 N.getValueType(), IdxN, Scale);
2868 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2869 N.getValueType(), N, IdxN);
2876 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2877 // If this is a fixed sized alloca in the entry block of the function,
2878 // allocate it statically on the stack.
2879 if (FuncInfo.StaticAllocaMap.count(&I))
2880 return; // getValue will auto-populate this.
2882 const Type *Ty = I.getAllocatedType();
2883 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2885 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2888 SDValue AllocSize = getValue(I.getArraySize());
2890 EVT IntPtr = TLI.getPointerTy();
2891 if (AllocSize.getValueType() != IntPtr)
2892 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2894 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2896 DAG.getConstant(TySize, IntPtr));
2898 // Handle alignment. If the requested alignment is less than or equal to
2899 // the stack alignment, ignore it. If the size is greater than or equal to
2900 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2901 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
2902 if (Align <= StackAlign)
2905 // Round the size of the allocation up to the stack alignment size
2906 // by add SA-1 to the size.
2907 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2908 AllocSize.getValueType(), AllocSize,
2909 DAG.getIntPtrConstant(StackAlign-1));
2911 // Mask out the low bits for alignment purposes.
2912 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2913 AllocSize.getValueType(), AllocSize,
2914 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2916 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2917 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2918 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2921 DAG.setRoot(DSA.getValue(1));
2923 // Inform the Frame Information that we have just allocated a variable-sized
2925 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2928 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2929 const Value *SV = I.getOperand(0);
2930 SDValue Ptr = getValue(SV);
2932 const Type *Ty = I.getType();
2934 bool isVolatile = I.isVolatile();
2935 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2936 unsigned Alignment = I.getAlignment();
2938 SmallVector<EVT, 4> ValueVTs;
2939 SmallVector<uint64_t, 4> Offsets;
2940 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
2941 unsigned NumValues = ValueVTs.size();
2946 bool ConstantMemory = false;
2948 // Serialize volatile loads with other side effects.
2950 else if (AA->pointsToConstantMemory(SV)) {
2951 // Do not serialize (non-volatile) loads of constant memory with anything.
2952 Root = DAG.getEntryNode();
2953 ConstantMemory = true;
2955 // Do not serialize non-volatile loads against each other.
2956 Root = DAG.getRoot();
2959 SmallVector<SDValue, 4> Values(NumValues);
2960 SmallVector<SDValue, 4> Chains(NumValues);
2961 EVT PtrVT = Ptr.getValueType();
2962 for (unsigned i = 0; i != NumValues; ++i) {
2963 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2965 DAG.getConstant(Offsets[i], PtrVT));
2966 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
2967 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
2968 isNonTemporal, Alignment);
2971 Chains[i] = L.getValue(1);
2974 if (!ConstantMemory) {
2975 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
2976 MVT::Other, &Chains[0], NumValues);
2980 PendingLoads.push_back(Chain);
2983 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2984 DAG.getVTList(&ValueVTs[0], NumValues),
2985 &Values[0], NumValues));
2988 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
2989 const Value *SrcV = I.getOperand(0);
2990 const Value *PtrV = I.getOperand(1);
2992 SmallVector<EVT, 4> ValueVTs;
2993 SmallVector<uint64_t, 4> Offsets;
2994 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
2995 unsigned NumValues = ValueVTs.size();
2999 // Get the lowered operands. Note that we do this after
3000 // checking if NumResults is zero, because with zero results
3001 // the operands won't have values in the map.
3002 SDValue Src = getValue(SrcV);
3003 SDValue Ptr = getValue(PtrV);
3005 SDValue Root = getRoot();
3006 SmallVector<SDValue, 4> Chains(NumValues);
3007 EVT PtrVT = Ptr.getValueType();
3008 bool isVolatile = I.isVolatile();
3009 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3010 unsigned Alignment = I.getAlignment();
3012 for (unsigned i = 0; i != NumValues; ++i) {
3013 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3014 DAG.getConstant(Offsets[i], PtrVT));
3015 Chains[i] = DAG.getStore(Root, getCurDebugLoc(),
3016 SDValue(Src.getNode(), Src.getResNo() + i),
3017 Add, MachinePointerInfo(PtrV, Offsets[i]),
3018 isVolatile, isNonTemporal, Alignment);
3021 DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3022 MVT::Other, &Chains[0], NumValues));
3025 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3027 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3028 unsigned Intrinsic) {
3029 bool HasChain = !I.doesNotAccessMemory();
3030 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3032 // Build the operand list.
3033 SmallVector<SDValue, 8> Ops;
3034 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3036 // We don't need to serialize loads against other loads.
3037 Ops.push_back(DAG.getRoot());
3039 Ops.push_back(getRoot());
3043 // Info is set by getTgtMemInstrinsic
3044 TargetLowering::IntrinsicInfo Info;
3045 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3047 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3048 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3049 Info.opc == ISD::INTRINSIC_W_CHAIN)
3050 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3052 // Add all operands of the call to the operand list.
3053 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3054 SDValue Op = getValue(I.getArgOperand(i));
3055 assert(TLI.isTypeLegal(Op.getValueType()) &&
3056 "Intrinsic uses a non-legal type?");
3060 SmallVector<EVT, 4> ValueVTs;
3061 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3063 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3064 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3065 "Intrinsic uses a non-legal type?");
3070 ValueVTs.push_back(MVT::Other);
3072 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3076 if (IsTgtIntrinsic) {
3077 // This is target intrinsic that touches memory
3078 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3079 VTs, &Ops[0], Ops.size(),
3081 MachinePointerInfo(Info.ptrVal, Info.offset),
3082 Info.align, Info.vol,
3083 Info.readMem, Info.writeMem);
3084 } else if (!HasChain) {
3085 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3086 VTs, &Ops[0], Ops.size());
3087 } else if (!I.getType()->isVoidTy()) {
3088 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3089 VTs, &Ops[0], Ops.size());
3091 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3092 VTs, &Ops[0], Ops.size());
3096 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3098 PendingLoads.push_back(Chain);
3103 if (!I.getType()->isVoidTy()) {
3104 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3105 EVT VT = TLI.getValueType(PTy);
3106 Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
3109 setValue(&I, Result);
3113 /// GetSignificand - Get the significand and build it into a floating-point
3114 /// number with exponent of 1:
3116 /// Op = (Op & 0x007fffff) | 0x3f800000;
3118 /// where Op is the hexidecimal representation of floating point value.
3120 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3121 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3122 DAG.getConstant(0x007fffff, MVT::i32));
3123 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3124 DAG.getConstant(0x3f800000, MVT::i32));
3125 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
3128 /// GetExponent - Get the exponent:
3130 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3132 /// where Op is the hexidecimal representation of floating point value.
3134 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3136 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3137 DAG.getConstant(0x7f800000, MVT::i32));
3138 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3139 DAG.getConstant(23, TLI.getPointerTy()));
3140 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3141 DAG.getConstant(127, MVT::i32));
3142 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3145 /// getF32Constant - Get 32-bit floating point constant.
3147 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3148 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3151 /// Inlined utility function to implement binary input atomic intrinsics for
3152 /// visitIntrinsicCall: I is a call instruction
3153 /// Op is the associated NodeType for I
3155 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3157 SDValue Root = getRoot();
3159 DAG.getAtomic(Op, getCurDebugLoc(),
3160 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3162 getValue(I.getArgOperand(0)),
3163 getValue(I.getArgOperand(1)),
3164 I.getArgOperand(0));
3166 DAG.setRoot(L.getValue(1));
3170 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3172 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3173 SDValue Op1 = getValue(I.getArgOperand(0));
3174 SDValue Op2 = getValue(I.getArgOperand(1));
3176 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3177 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3181 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3182 /// limited-precision mode.
3184 SelectionDAGBuilder::visitExp(const CallInst &I) {
3186 DebugLoc dl = getCurDebugLoc();
3188 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3189 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3190 SDValue Op = getValue(I.getArgOperand(0));
3192 // Put the exponent in the right bit position for later addition to the
3195 // #define LOG2OFe 1.4426950f
3196 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3197 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3198 getF32Constant(DAG, 0x3fb8aa3b));
3199 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3201 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3202 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3203 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3205 // IntegerPartOfX <<= 23;
3206 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3207 DAG.getConstant(23, TLI.getPointerTy()));
3209 if (LimitFloatPrecision <= 6) {
3210 // For floating-point precision of 6:
3212 // TwoToFractionalPartOfX =
3214 // (0.735607626f + 0.252464424f * x) * x;
3216 // error 0.0144103317, which is 6 bits
3217 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3218 getF32Constant(DAG, 0x3e814304));
3219 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3220 getF32Constant(DAG, 0x3f3c50c8));
3221 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3222 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3223 getF32Constant(DAG, 0x3f7f5e7e));
3224 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
3226 // Add the exponent into the result in integer domain.
3227 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3228 TwoToFracPartOfX, IntegerPartOfX);
3230 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
3231 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3232 // For floating-point precision of 12:
3234 // TwoToFractionalPartOfX =
3237 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3239 // 0.000107046256 error, which is 13 to 14 bits
3240 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3241 getF32Constant(DAG, 0x3da235e3));
3242 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3243 getF32Constant(DAG, 0x3e65b8f3));
3244 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3245 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3246 getF32Constant(DAG, 0x3f324b07));
3247 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3248 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3249 getF32Constant(DAG, 0x3f7ff8fd));
3250 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
3252 // Add the exponent into the result in integer domain.
3253 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3254 TwoToFracPartOfX, IntegerPartOfX);
3256 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
3257 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3258 // For floating-point precision of 18:
3260 // TwoToFractionalPartOfX =
3264 // (0.554906021e-1f +
3265 // (0.961591928e-2f +
3266 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3268 // error 2.47208000*10^(-7), which is better than 18 bits
3269 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3270 getF32Constant(DAG, 0x3924b03e));
3271 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3272 getF32Constant(DAG, 0x3ab24b87));
3273 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3274 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3275 getF32Constant(DAG, 0x3c1d8c17));
3276 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3277 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3278 getF32Constant(DAG, 0x3d634a1d));
3279 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3280 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3281 getF32Constant(DAG, 0x3e75fe14));
3282 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3283 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3284 getF32Constant(DAG, 0x3f317234));
3285 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3286 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3287 getF32Constant(DAG, 0x3f800000));
3288 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
3291 // Add the exponent into the result in integer domain.
3292 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3293 TwoToFracPartOfX, IntegerPartOfX);
3295 result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
3298 // No special expansion.
3299 result = DAG.getNode(ISD::FEXP, dl,
3300 getValue(I.getArgOperand(0)).getValueType(),
3301 getValue(I.getArgOperand(0)));
3304 setValue(&I, result);
3307 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3308 /// limited-precision mode.
3310 SelectionDAGBuilder::visitLog(const CallInst &I) {
3312 DebugLoc dl = getCurDebugLoc();
3314 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3315 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3316 SDValue Op = getValue(I.getArgOperand(0));
3317 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3319 // Scale the exponent by log(2) [0.69314718f].
3320 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3321 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3322 getF32Constant(DAG, 0x3f317218));
3324 // Get the significand and build it into a floating-point number with
3326 SDValue X = GetSignificand(DAG, Op1, dl);
3328 if (LimitFloatPrecision <= 6) {
3329 // For floating-point precision of 6:
3333 // (1.4034025f - 0.23903021f * x) * x;
3335 // error 0.0034276066, which is better than 8 bits
3336 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3337 getF32Constant(DAG, 0xbe74c456));
3338 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3339 getF32Constant(DAG, 0x3fb3a2b1));
3340 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3341 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3342 getF32Constant(DAG, 0x3f949a29));
3344 result = DAG.getNode(ISD::FADD, dl,
3345 MVT::f32, LogOfExponent, LogOfMantissa);
3346 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3347 // For floating-point precision of 12:
3353 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3355 // error 0.000061011436, which is 14 bits
3356 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3357 getF32Constant(DAG, 0xbd67b6d6));
3358 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3359 getF32Constant(DAG, 0x3ee4f4b8));
3360 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3361 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3362 getF32Constant(DAG, 0x3fbc278b));
3363 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3364 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3365 getF32Constant(DAG, 0x40348e95));
3366 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3367 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3368 getF32Constant(DAG, 0x3fdef31a));
3370 result = DAG.getNode(ISD::FADD, dl,
3371 MVT::f32, LogOfExponent, LogOfMantissa);
3372 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3373 // For floating-point precision of 18:
3381 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3383 // error 0.0000023660568, which is better than 18 bits
3384 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3385 getF32Constant(DAG, 0xbc91e5ac));
3386 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3387 getF32Constant(DAG, 0x3e4350aa));
3388 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3389 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3390 getF32Constant(DAG, 0x3f60d3e3));
3391 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3392 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3393 getF32Constant(DAG, 0x4011cdf0));
3394 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3395 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3396 getF32Constant(DAG, 0x406cfd1c));
3397 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3398 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3399 getF32Constant(DAG, 0x408797cb));
3400 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3401 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3402 getF32Constant(DAG, 0x4006dcab));
3404 result = DAG.getNode(ISD::FADD, dl,
3405 MVT::f32, LogOfExponent, LogOfMantissa);
3408 // No special expansion.
3409 result = DAG.getNode(ISD::FLOG, dl,
3410 getValue(I.getArgOperand(0)).getValueType(),
3411 getValue(I.getArgOperand(0)));
3414 setValue(&I, result);
3417 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3418 /// limited-precision mode.
3420 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3422 DebugLoc dl = getCurDebugLoc();
3424 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3425 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3426 SDValue Op = getValue(I.getArgOperand(0));
3427 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3429 // Get the exponent.
3430 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3432 // Get the significand and build it into a floating-point number with
3434 SDValue X = GetSignificand(DAG, Op1, dl);
3436 // Different possible minimax approximations of significand in
3437 // floating-point for various degrees of accuracy over [1,2].
3438 if (LimitFloatPrecision <= 6) {
3439 // For floating-point precision of 6:
3441 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3443 // error 0.0049451742, which is more than 7 bits
3444 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3445 getF32Constant(DAG, 0xbeb08fe0));
3446 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3447 getF32Constant(DAG, 0x40019463));
3448 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3449 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3450 getF32Constant(DAG, 0x3fd6633d));
3452 result = DAG.getNode(ISD::FADD, dl,
3453 MVT::f32, LogOfExponent, Log2ofMantissa);
3454 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3455 // For floating-point precision of 12:
3461 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3463 // error 0.0000876136000, which is better than 13 bits
3464 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3465 getF32Constant(DAG, 0xbda7262e));
3466 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3467 getF32Constant(DAG, 0x3f25280b));
3468 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3469 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3470 getF32Constant(DAG, 0x4007b923));
3471 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3472 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3473 getF32Constant(DAG, 0x40823e2f));
3474 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3475 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3476 getF32Constant(DAG, 0x4020d29c));
3478 result = DAG.getNode(ISD::FADD, dl,
3479 MVT::f32, LogOfExponent, Log2ofMantissa);
3480 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3481 // For floating-point precision of 18:
3490 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3492 // error 0.0000018516, which is better than 18 bits
3493 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3494 getF32Constant(DAG, 0xbcd2769e));
3495 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3496 getF32Constant(DAG, 0x3e8ce0b9));
3497 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3498 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3499 getF32Constant(DAG, 0x3fa22ae7));
3500 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3501 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3502 getF32Constant(DAG, 0x40525723));
3503 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3504 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3505 getF32Constant(DAG, 0x40aaf200));
3506 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3507 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3508 getF32Constant(DAG, 0x40c39dad));
3509 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3510 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3511 getF32Constant(DAG, 0x4042902c));
3513 result = DAG.getNode(ISD::FADD, dl,
3514 MVT::f32, LogOfExponent, Log2ofMantissa);
3517 // No special expansion.
3518 result = DAG.getNode(ISD::FLOG2, dl,
3519 getValue(I.getArgOperand(0)).getValueType(),
3520 getValue(I.getArgOperand(0)));
3523 setValue(&I, result);
3526 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3527 /// limited-precision mode.
3529 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3531 DebugLoc dl = getCurDebugLoc();
3533 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3534 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3535 SDValue Op = getValue(I.getArgOperand(0));
3536 SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
3538 // Scale the exponent by log10(2) [0.30102999f].
3539 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3540 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3541 getF32Constant(DAG, 0x3e9a209a));
3543 // Get the significand and build it into a floating-point number with
3545 SDValue X = GetSignificand(DAG, Op1, dl);
3547 if (LimitFloatPrecision <= 6) {
3548 // For floating-point precision of 6:
3550 // Log10ofMantissa =
3552 // (0.60948995f - 0.10380950f * x) * x;
3554 // error 0.0014886165, which is 6 bits
3555 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3556 getF32Constant(DAG, 0xbdd49a13));
3557 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3558 getF32Constant(DAG, 0x3f1c0789));
3559 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3560 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3561 getF32Constant(DAG, 0x3f011300));
3563 result = DAG.getNode(ISD::FADD, dl,
3564 MVT::f32, LogOfExponent, Log10ofMantissa);
3565 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3566 // For floating-point precision of 12:
3568 // Log10ofMantissa =
3571 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3573 // error 0.00019228036, which is better than 12 bits
3574 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3575 getF32Constant(DAG, 0x3d431f31));
3576 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3577 getF32Constant(DAG, 0x3ea21fb2));
3578 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3579 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3580 getF32Constant(DAG, 0x3f6ae232));
3581 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3582 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3583 getF32Constant(DAG, 0x3f25f7c3));
3585 result = DAG.getNode(ISD::FADD, dl,
3586 MVT::f32, LogOfExponent, Log10ofMantissa);
3587 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3588 // For floating-point precision of 18:
3590 // Log10ofMantissa =
3595 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3597 // error 0.0000037995730, which is better than 18 bits
3598 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3599 getF32Constant(DAG, 0x3c5d51ce));
3600 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3601 getF32Constant(DAG, 0x3e00685a));
3602 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3603 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3604 getF32Constant(DAG, 0x3efb6798));
3605 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3606 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3607 getF32Constant(DAG, 0x3f88d192));
3608 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3609 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3610 getF32Constant(DAG, 0x3fc4316c));
3611 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3612 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3613 getF32Constant(DAG, 0x3f57ce70));
3615 result = DAG.getNode(ISD::FADD, dl,
3616 MVT::f32, LogOfExponent, Log10ofMantissa);
3619 // No special expansion.
3620 result = DAG.getNode(ISD::FLOG10, dl,
3621 getValue(I.getArgOperand(0)).getValueType(),
3622 getValue(I.getArgOperand(0)));
3625 setValue(&I, result);
3628 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3629 /// limited-precision mode.
3631 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3633 DebugLoc dl = getCurDebugLoc();
3635 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3636 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3637 SDValue Op = getValue(I.getArgOperand(0));
3639 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3641 // FractionalPartOfX = x - (float)IntegerPartOfX;
3642 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3643 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3645 // IntegerPartOfX <<= 23;
3646 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3647 DAG.getConstant(23, TLI.getPointerTy()));
3649 if (LimitFloatPrecision <= 6) {
3650 // For floating-point precision of 6:
3652 // TwoToFractionalPartOfX =
3654 // (0.735607626f + 0.252464424f * x) * x;
3656 // error 0.0144103317, which is 6 bits
3657 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3658 getF32Constant(DAG, 0x3e814304));
3659 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3660 getF32Constant(DAG, 0x3f3c50c8));
3661 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3662 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3663 getF32Constant(DAG, 0x3f7f5e7e));
3664 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3665 SDValue TwoToFractionalPartOfX =
3666 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3668 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3669 MVT::f32, TwoToFractionalPartOfX);
3670 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3671 // For floating-point precision of 12:
3673 // TwoToFractionalPartOfX =
3676 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3678 // error 0.000107046256, which is 13 to 14 bits
3679 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3680 getF32Constant(DAG, 0x3da235e3));
3681 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3682 getF32Constant(DAG, 0x3e65b8f3));
3683 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3684 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3685 getF32Constant(DAG, 0x3f324b07));
3686 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3687 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3688 getF32Constant(DAG, 0x3f7ff8fd));
3689 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3690 SDValue TwoToFractionalPartOfX =
3691 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3693 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3694 MVT::f32, TwoToFractionalPartOfX);
3695 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3696 // For floating-point precision of 18:
3698 // TwoToFractionalPartOfX =
3702 // (0.554906021e-1f +
3703 // (0.961591928e-2f +
3704 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3705 // error 2.47208000*10^(-7), which is better than 18 bits
3706 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3707 getF32Constant(DAG, 0x3924b03e));
3708 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3709 getF32Constant(DAG, 0x3ab24b87));
3710 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3711 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3712 getF32Constant(DAG, 0x3c1d8c17));
3713 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3714 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3715 getF32Constant(DAG, 0x3d634a1d));
3716 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3717 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3718 getF32Constant(DAG, 0x3e75fe14));
3719 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3720 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3721 getF32Constant(DAG, 0x3f317234));
3722 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3723 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3724 getF32Constant(DAG, 0x3f800000));
3725 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3726 SDValue TwoToFractionalPartOfX =
3727 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3729 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3730 MVT::f32, TwoToFractionalPartOfX);
3733 // No special expansion.
3734 result = DAG.getNode(ISD::FEXP2, dl,
3735 getValue(I.getArgOperand(0)).getValueType(),
3736 getValue(I.getArgOperand(0)));
3739 setValue(&I, result);
3742 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3743 /// limited-precision mode with x == 10.0f.
3745 SelectionDAGBuilder::visitPow(const CallInst &I) {
3747 const Value *Val = I.getArgOperand(0);
3748 DebugLoc dl = getCurDebugLoc();
3749 bool IsExp10 = false;
3751 if (getValue(Val).getValueType() == MVT::f32 &&
3752 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3753 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3754 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3755 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3757 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3762 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3763 SDValue Op = getValue(I.getArgOperand(1));
3765 // Put the exponent in the right bit position for later addition to the
3768 // #define LOG2OF10 3.3219281f
3769 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3770 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3771 getF32Constant(DAG, 0x40549a78));
3772 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3774 // FractionalPartOfX = x - (float)IntegerPartOfX;
3775 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3776 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3778 // IntegerPartOfX <<= 23;
3779 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3780 DAG.getConstant(23, TLI.getPointerTy()));
3782 if (LimitFloatPrecision <= 6) {
3783 // For floating-point precision of 6:
3785 // twoToFractionalPartOfX =
3787 // (0.735607626f + 0.252464424f * x) * x;
3789 // error 0.0144103317, which is 6 bits
3790 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3791 getF32Constant(DAG, 0x3e814304));
3792 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3793 getF32Constant(DAG, 0x3f3c50c8));
3794 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3795 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3796 getF32Constant(DAG, 0x3f7f5e7e));
3797 SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
3798 SDValue TwoToFractionalPartOfX =
3799 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3801 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3802 MVT::f32, TwoToFractionalPartOfX);
3803 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3804 // For floating-point precision of 12:
3806 // TwoToFractionalPartOfX =
3809 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3811 // error 0.000107046256, which is 13 to 14 bits
3812 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3813 getF32Constant(DAG, 0x3da235e3));
3814 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3815 getF32Constant(DAG, 0x3e65b8f3));
3816 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3817 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3818 getF32Constant(DAG, 0x3f324b07));
3819 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3820 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3821 getF32Constant(DAG, 0x3f7ff8fd));
3822 SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
3823 SDValue TwoToFractionalPartOfX =
3824 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3826 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3827 MVT::f32, TwoToFractionalPartOfX);
3828 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3829 // For floating-point precision of 18:
3831 // TwoToFractionalPartOfX =
3835 // (0.554906021e-1f +
3836 // (0.961591928e-2f +
3837 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3838 // error 2.47208000*10^(-7), which is better than 18 bits
3839 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3840 getF32Constant(DAG, 0x3924b03e));
3841 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3842 getF32Constant(DAG, 0x3ab24b87));
3843 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3844 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3845 getF32Constant(DAG, 0x3c1d8c17));
3846 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3847 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3848 getF32Constant(DAG, 0x3d634a1d));
3849 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3850 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3851 getF32Constant(DAG, 0x3e75fe14));
3852 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3853 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3854 getF32Constant(DAG, 0x3f317234));
3855 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3856 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3857 getF32Constant(DAG, 0x3f800000));
3858 SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
3859 SDValue TwoToFractionalPartOfX =
3860 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3862 result = DAG.getNode(ISD::BIT_CONVERT, dl,
3863 MVT::f32, TwoToFractionalPartOfX);
3866 // No special expansion.
3867 result = DAG.getNode(ISD::FPOW, dl,
3868 getValue(I.getArgOperand(0)).getValueType(),
3869 getValue(I.getArgOperand(0)),
3870 getValue(I.getArgOperand(1)));
3873 setValue(&I, result);
3877 /// ExpandPowI - Expand a llvm.powi intrinsic.
3878 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3879 SelectionDAG &DAG) {
3880 // If RHS is a constant, we can expand this out to a multiplication tree,
3881 // otherwise we end up lowering to a call to __powidf2 (for example). When
3882 // optimizing for size, we only want to do this if the expansion would produce
3883 // a small number of multiplies, otherwise we do the full expansion.
3884 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3885 // Get the exponent as a positive value.
3886 unsigned Val = RHSC->getSExtValue();
3887 if ((int)Val < 0) Val = -Val;
3889 // powi(x, 0) -> 1.0
3891 return DAG.getConstantFP(1.0, LHS.getValueType());
3893 const Function *F = DAG.getMachineFunction().getFunction();
3894 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3895 // If optimizing for size, don't insert too many multiplies. This
3896 // inserts up to 5 multiplies.
3897 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3898 // We use the simple binary decomposition method to generate the multiply
3899 // sequence. There are more optimal ways to do this (for example,
3900 // powi(x,15) generates one more multiply than it should), but this has
3901 // the benefit of being both really simple and much better than a libcall.
3902 SDValue Res; // Logically starts equal to 1.0
3903 SDValue CurSquare = LHS;
3907 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
3909 Res = CurSquare; // 1.0*CurSquare.
3912 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
3913 CurSquare, CurSquare);
3917 // If the original was negative, invert the result, producing 1/(x*x*x).
3918 if (RHSC->getSExtValue() < 0)
3919 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
3920 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
3925 // Otherwise, expand to a libcall.
3926 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
3929 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
3930 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
3931 /// At the end of instruction selection, they will be inserted to the entry BB.
3933 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
3936 const Argument *Arg = dyn_cast<Argument>(V);
3940 MachineFunction &MF = DAG.getMachineFunction();
3941 // Ignore inlined function arguments here.
3942 DIVariable DV(Variable);
3943 if (DV.isInlinedFnArgument(MF.getFunction()))
3946 MachineBasicBlock *MBB = FuncInfo.MBB;
3947 if (MBB != &MF.front())
3951 if (Arg->hasByValAttr()) {
3952 // Byval arguments' frame index is recorded during argument lowering.
3953 // Use this info directly.
3954 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
3955 Reg = TRI->getFrameRegister(MF);
3956 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
3957 // If byval argument ofset is not recorded then ignore this.
3962 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
3963 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
3964 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
3965 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3966 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
3973 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
3974 if (VMI == FuncInfo.ValueMap.end())
3979 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
3980 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
3981 TII->get(TargetOpcode::DBG_VALUE))
3982 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
3983 FuncInfo.ArgDbgValues.push_back(&*MIB);
3987 // VisualStudio defines setjmp as _setjmp
3988 #if defined(_MSC_VER) && defined(setjmp) && \
3989 !defined(setjmp_undefined_for_msvc)
3990 # pragma push_macro("setjmp")
3992 # define setjmp_undefined_for_msvc
3995 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
3996 /// we want to emit this as a call to a named external function, return the name
3997 /// otherwise lower it and return null.
3999 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4000 DebugLoc dl = getCurDebugLoc();
4003 switch (Intrinsic) {
4005 // By default, turn this into a target intrinsic node.
4006 visitTargetIntrinsic(I, Intrinsic);
4008 case Intrinsic::vastart: visitVAStart(I); return 0;
4009 case Intrinsic::vaend: visitVAEnd(I); return 0;
4010 case Intrinsic::vacopy: visitVACopy(I); return 0;
4011 case Intrinsic::returnaddress:
4012 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4013 getValue(I.getArgOperand(0))));
4015 case Intrinsic::frameaddress:
4016 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4017 getValue(I.getArgOperand(0))));
4019 case Intrinsic::setjmp:
4020 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4021 case Intrinsic::longjmp:
4022 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4023 case Intrinsic::memcpy: {
4024 // Assert for address < 256 since we support only user defined address
4026 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4028 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4030 "Unknown address space");
4031 SDValue Op1 = getValue(I.getArgOperand(0));
4032 SDValue Op2 = getValue(I.getArgOperand(1));
4033 SDValue Op3 = getValue(I.getArgOperand(2));
4034 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4035 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4036 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4037 MachinePointerInfo(I.getArgOperand(0)),
4038 MachinePointerInfo(I.getArgOperand(1))));
4041 case Intrinsic::memset: {
4042 // Assert for address < 256 since we support only user defined address
4044 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4046 "Unknown address space");
4047 SDValue Op1 = getValue(I.getArgOperand(0));
4048 SDValue Op2 = getValue(I.getArgOperand(1));
4049 SDValue Op3 = getValue(I.getArgOperand(2));
4050 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4051 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4052 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4053 MachinePointerInfo(I.getArgOperand(0))));
4056 case Intrinsic::memmove: {
4057 // Assert for address < 256 since we support only user defined address
4059 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4061 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4063 "Unknown address space");
4064 SDValue Op1 = getValue(I.getArgOperand(0));
4065 SDValue Op2 = getValue(I.getArgOperand(1));
4066 SDValue Op3 = getValue(I.getArgOperand(2));
4067 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4068 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4070 // If the source and destination are known to not be aliases, we can
4071 // lower memmove as memcpy.
4072 uint64_t Size = -1ULL;
4073 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op3))
4074 Size = C->getZExtValue();
4075 if (AA->alias(I.getArgOperand(0), Size, I.getArgOperand(1), Size) ==
4076 AliasAnalysis::NoAlias) {
4077 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4078 false, MachinePointerInfo(I.getArgOperand(0)),
4079 MachinePointerInfo(I.getArgOperand(1))));
4083 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4084 MachinePointerInfo(I.getArgOperand(0)),
4085 MachinePointerInfo(I.getArgOperand(1))));
4088 case Intrinsic::dbg_declare: {
4089 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4090 MDNode *Variable = DI.getVariable();
4091 const Value *Address = DI.getAddress();
4092 if (!Address || !DIVariable(DI.getVariable()).Verify())
4095 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4096 // but do not always have a corresponding SDNode built. The SDNodeOrder
4097 // absolute, but not relative, values are different depending on whether
4098 // debug info exists.
4101 // Check if address has undef value.
4102 if (isa<UndefValue>(Address) ||
4103 (Address->use_empty() && !isa<Argument>(Address))) {
4105 DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4106 0, dl, SDNodeOrder);
4107 DAG.AddDbgValue(SDV, 0, false);
4111 SDValue &N = NodeMap[Address];
4112 if (!N.getNode() && isa<Argument>(Address))
4113 // Check unused arguments map.
4114 N = UnusedArgNodeMap[Address];
4117 // Parameters are handled specially.
4119 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4120 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4121 Address = BCI->getOperand(0);
4122 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4124 if (isParameter && !AI) {
4125 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4127 // Byval parameter. We have a frame index at this point.
4128 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4129 0, dl, SDNodeOrder);
4131 // Can't do anything with other non-AI cases yet. This might be a
4132 // parameter of a callee function that got inlined, for example.
4135 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4136 0, dl, SDNodeOrder);
4138 // Can't do anything with other non-AI cases yet.
4140 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4142 // If Address is an argument then try to emit its dbg value using
4143 // virtual register info from the FuncInfo.ValueMap.
4144 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4145 // If variable is pinned by a alloca in dominating bb then
4146 // use StaticAllocaMap.
4147 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4148 if (AI->getParent() != DI.getParent()) {
4149 DenseMap<const AllocaInst*, int>::iterator SI =
4150 FuncInfo.StaticAllocaMap.find(AI);
4151 if (SI != FuncInfo.StaticAllocaMap.end()) {
4152 SDV = DAG.getDbgValue(Variable, SI->second,
4153 0, dl, SDNodeOrder);
4154 DAG.AddDbgValue(SDV, 0, false);
4159 // Otherwise add undef to help track missing debug info.
4160 SDV = DAG.getDbgValue(Variable, UndefValue::get(Address->getType()),
4161 0, dl, SDNodeOrder);
4162 DAG.AddDbgValue(SDV, 0, false);
4167 case Intrinsic::dbg_value: {
4168 const DbgValueInst &DI = cast<DbgValueInst>(I);
4169 if (!DIVariable(DI.getVariable()).Verify())
4172 MDNode *Variable = DI.getVariable();
4173 uint64_t Offset = DI.getOffset();
4174 const Value *V = DI.getValue();
4178 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4179 // but do not always have a corresponding SDNode built. The SDNodeOrder
4180 // absolute, but not relative, values are different depending on whether
4181 // debug info exists.
4184 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4185 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4186 DAG.AddDbgValue(SDV, 0, false);
4188 // Do not use getValue() in here; we don't want to generate code at
4189 // this point if it hasn't been done yet.
4190 SDValue N = NodeMap[V];
4191 if (!N.getNode() && isa<Argument>(V))
4192 // Check unused arguments map.
4193 N = UnusedArgNodeMap[V];
4195 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4196 SDV = DAG.getDbgValue(Variable, N.getNode(),
4197 N.getResNo(), Offset, dl, SDNodeOrder);
4198 DAG.AddDbgValue(SDV, N.getNode(), false);
4200 } else if (isa<PHINode>(V) && !V->use_empty() ) {
4201 // Do not call getValue(V) yet, as we don't want to generate code.
4202 // Remember it for later.
4203 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4204 DanglingDebugInfoMap[V] = DDI;
4206 // We may expand this to cover more cases. One case where we have no
4207 // data available is an unreferenced parameter; we need this fallback.
4208 SDV = DAG.getDbgValue(Variable, UndefValue::get(V->getType()),
4209 Offset, dl, SDNodeOrder);
4210 DAG.AddDbgValue(SDV, 0, false);
4214 // Build a debug info table entry.
4215 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4216 V = BCI->getOperand(0);
4217 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4218 // Don't handle byval struct arguments or VLAs, for example.
4221 DenseMap<const AllocaInst*, int>::iterator SI =
4222 FuncInfo.StaticAllocaMap.find(AI);
4223 if (SI == FuncInfo.StaticAllocaMap.end())
4225 int FI = SI->second;
4227 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4228 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4229 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4232 case Intrinsic::eh_exception: {
4233 // Insert the EXCEPTIONADDR instruction.
4234 assert(FuncInfo.MBB->isLandingPad() &&
4235 "Call to eh.exception not in landing pad!");
4236 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4238 Ops[0] = DAG.getRoot();
4239 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4241 DAG.setRoot(Op.getValue(1));
4245 case Intrinsic::eh_selector: {
4246 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4247 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4248 if (CallMBB->isLandingPad())
4249 AddCatchInfo(I, &MMI, CallMBB);
4252 FuncInfo.CatchInfoLost.insert(&I);
4254 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4255 unsigned Reg = TLI.getExceptionSelectorRegister();
4256 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4259 // Insert the EHSELECTION instruction.
4260 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4262 Ops[0] = getValue(I.getArgOperand(0));
4264 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4265 DAG.setRoot(Op.getValue(1));
4266 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4270 case Intrinsic::eh_typeid_for: {
4271 // Find the type id for the given typeinfo.
4272 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4273 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4274 Res = DAG.getConstant(TypeID, MVT::i32);
4279 case Intrinsic::eh_return_i32:
4280 case Intrinsic::eh_return_i64:
4281 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4282 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4285 getValue(I.getArgOperand(0)),
4286 getValue(I.getArgOperand(1))));
4288 case Intrinsic::eh_unwind_init:
4289 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4291 case Intrinsic::eh_dwarf_cfa: {
4292 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4293 TLI.getPointerTy());
4294 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4296 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4297 TLI.getPointerTy()),
4299 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4301 DAG.getConstant(0, TLI.getPointerTy()));
4302 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4306 case Intrinsic::eh_sjlj_callsite: {
4307 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4308 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4309 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4310 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4312 MMI.setCurrentCallSite(CI->getZExtValue());
4315 case Intrinsic::eh_sjlj_setjmp: {
4316 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4317 getValue(I.getArgOperand(0))));
4320 case Intrinsic::eh_sjlj_longjmp: {
4321 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4323 getValue(I.getArgOperand(0))));
4327 case Intrinsic::x86_mmx_pslli_w:
4328 case Intrinsic::x86_mmx_pslli_d:
4329 case Intrinsic::x86_mmx_pslli_q:
4330 case Intrinsic::x86_mmx_psrli_w:
4331 case Intrinsic::x86_mmx_psrli_d:
4332 case Intrinsic::x86_mmx_psrli_q:
4333 case Intrinsic::x86_mmx_psrai_w:
4334 case Intrinsic::x86_mmx_psrai_d: {
4335 SDValue ShAmt = getValue(I.getArgOperand(1));
4336 if (isa<ConstantSDNode>(ShAmt)) {
4337 visitTargetIntrinsic(I, Intrinsic);
4340 unsigned NewIntrinsic = 0;
4341 EVT ShAmtVT = MVT::v2i32;
4342 switch (Intrinsic) {
4343 case Intrinsic::x86_mmx_pslli_w:
4344 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4346 case Intrinsic::x86_mmx_pslli_d:
4347 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4349 case Intrinsic::x86_mmx_pslli_q:
4350 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4352 case Intrinsic::x86_mmx_psrli_w:
4353 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4355 case Intrinsic::x86_mmx_psrli_d:
4356 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4358 case Intrinsic::x86_mmx_psrli_q:
4359 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4361 case Intrinsic::x86_mmx_psrai_w:
4362 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4364 case Intrinsic::x86_mmx_psrai_d:
4365 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4367 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4370 // The vector shift intrinsics with scalars uses 32b shift amounts but
4371 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4373 // We must do this early because v2i32 is not a legal type.
4374 DebugLoc dl = getCurDebugLoc();
4377 ShOps[1] = DAG.getConstant(0, MVT::i32);
4378 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4379 EVT DestVT = TLI.getValueType(I.getType());
4380 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, DestVT, ShAmt);
4381 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4382 DAG.getConstant(NewIntrinsic, MVT::i32),
4383 getValue(I.getArgOperand(0)), ShAmt);
4387 case Intrinsic::convertff:
4388 case Intrinsic::convertfsi:
4389 case Intrinsic::convertfui:
4390 case Intrinsic::convertsif:
4391 case Intrinsic::convertuif:
4392 case Intrinsic::convertss:
4393 case Intrinsic::convertsu:
4394 case Intrinsic::convertus:
4395 case Intrinsic::convertuu: {
4396 ISD::CvtCode Code = ISD::CVT_INVALID;
4397 switch (Intrinsic) {
4398 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4399 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4400 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4401 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4402 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4403 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4404 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4405 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4406 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4408 EVT DestVT = TLI.getValueType(I.getType());
4409 const Value *Op1 = I.getArgOperand(0);
4410 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4411 DAG.getValueType(DestVT),
4412 DAG.getValueType(getValue(Op1).getValueType()),
4413 getValue(I.getArgOperand(1)),
4414 getValue(I.getArgOperand(2)),
4419 case Intrinsic::sqrt:
4420 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4421 getValue(I.getArgOperand(0)).getValueType(),
4422 getValue(I.getArgOperand(0))));
4424 case Intrinsic::powi:
4425 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4426 getValue(I.getArgOperand(1)), DAG));
4428 case Intrinsic::sin:
4429 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4430 getValue(I.getArgOperand(0)).getValueType(),
4431 getValue(I.getArgOperand(0))));
4433 case Intrinsic::cos:
4434 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4435 getValue(I.getArgOperand(0)).getValueType(),
4436 getValue(I.getArgOperand(0))));
4438 case Intrinsic::log:
4441 case Intrinsic::log2:
4444 case Intrinsic::log10:
4447 case Intrinsic::exp:
4450 case Intrinsic::exp2:
4453 case Intrinsic::pow:
4456 case Intrinsic::convert_to_fp16:
4457 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4458 MVT::i16, getValue(I.getArgOperand(0))));
4460 case Intrinsic::convert_from_fp16:
4461 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4462 MVT::f32, getValue(I.getArgOperand(0))));
4464 case Intrinsic::pcmarker: {
4465 SDValue Tmp = getValue(I.getArgOperand(0));
4466 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4469 case Intrinsic::readcyclecounter: {
4470 SDValue Op = getRoot();
4471 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4472 DAG.getVTList(MVT::i64, MVT::Other),
4475 DAG.setRoot(Res.getValue(1));
4478 case Intrinsic::bswap:
4479 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4480 getValue(I.getArgOperand(0)).getValueType(),
4481 getValue(I.getArgOperand(0))));
4483 case Intrinsic::cttz: {
4484 SDValue Arg = getValue(I.getArgOperand(0));
4485 EVT Ty = Arg.getValueType();
4486 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4489 case Intrinsic::ctlz: {
4490 SDValue Arg = getValue(I.getArgOperand(0));
4491 EVT Ty = Arg.getValueType();
4492 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4495 case Intrinsic::ctpop: {
4496 SDValue Arg = getValue(I.getArgOperand(0));
4497 EVT Ty = Arg.getValueType();
4498 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4501 case Intrinsic::stacksave: {
4502 SDValue Op = getRoot();
4503 Res = DAG.getNode(ISD::STACKSAVE, dl,
4504 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4506 DAG.setRoot(Res.getValue(1));
4509 case Intrinsic::stackrestore: {
4510 Res = getValue(I.getArgOperand(0));
4511 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4514 case Intrinsic::stackprotector: {
4515 // Emit code into the DAG to store the stack guard onto the stack.
4516 MachineFunction &MF = DAG.getMachineFunction();
4517 MachineFrameInfo *MFI = MF.getFrameInfo();
4518 EVT PtrTy = TLI.getPointerTy();
4520 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4521 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4523 int FI = FuncInfo.StaticAllocaMap[Slot];
4524 MFI->setStackProtectorIndex(FI);
4526 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4528 // Store the stack protector onto the stack.
4529 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4530 MachinePointerInfo::getFixedStack(FI),
4536 case Intrinsic::objectsize: {
4537 // If we don't know by now, we're never going to know.
4538 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4540 assert(CI && "Non-constant type in __builtin_object_size?");
4542 SDValue Arg = getValue(I.getCalledValue());
4543 EVT Ty = Arg.getValueType();
4546 Res = DAG.getConstant(-1ULL, Ty);
4548 Res = DAG.getConstant(0, Ty);
4553 case Intrinsic::var_annotation:
4554 // Discard annotate attributes
4557 case Intrinsic::init_trampoline: {
4558 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4562 Ops[1] = getValue(I.getArgOperand(0));
4563 Ops[2] = getValue(I.getArgOperand(1));
4564 Ops[3] = getValue(I.getArgOperand(2));
4565 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4566 Ops[5] = DAG.getSrcValue(F);
4568 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4569 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4573 DAG.setRoot(Res.getValue(1));
4576 case Intrinsic::gcroot:
4578 const Value *Alloca = I.getArgOperand(0);
4579 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4581 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4582 GFI->addStackRoot(FI->getIndex(), TypeMap);
4585 case Intrinsic::gcread:
4586 case Intrinsic::gcwrite:
4587 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4589 case Intrinsic::flt_rounds:
4590 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4592 case Intrinsic::trap:
4593 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4595 case Intrinsic::uadd_with_overflow:
4596 return implVisitAluOverflow(I, ISD::UADDO);
4597 case Intrinsic::sadd_with_overflow:
4598 return implVisitAluOverflow(I, ISD::SADDO);
4599 case Intrinsic::usub_with_overflow:
4600 return implVisitAluOverflow(I, ISD::USUBO);
4601 case Intrinsic::ssub_with_overflow:
4602 return implVisitAluOverflow(I, ISD::SSUBO);
4603 case Intrinsic::umul_with_overflow:
4604 return implVisitAluOverflow(I, ISD::UMULO);
4605 case Intrinsic::smul_with_overflow:
4606 return implVisitAluOverflow(I, ISD::SMULO);
4608 case Intrinsic::prefetch: {
4611 Ops[1] = getValue(I.getArgOperand(0));
4612 Ops[2] = getValue(I.getArgOperand(1));
4613 Ops[3] = getValue(I.getArgOperand(2));
4614 DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
4618 case Intrinsic::memory_barrier: {
4621 for (int x = 1; x < 6; ++x)
4622 Ops[x] = getValue(I.getArgOperand(x - 1));
4624 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4627 case Intrinsic::atomic_cmp_swap: {
4628 SDValue Root = getRoot();
4630 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4631 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4633 getValue(I.getArgOperand(0)),
4634 getValue(I.getArgOperand(1)),
4635 getValue(I.getArgOperand(2)),
4636 MachinePointerInfo(I.getArgOperand(0)));
4638 DAG.setRoot(L.getValue(1));
4641 case Intrinsic::atomic_load_add:
4642 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4643 case Intrinsic::atomic_load_sub:
4644 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4645 case Intrinsic::atomic_load_or:
4646 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4647 case Intrinsic::atomic_load_xor:
4648 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4649 case Intrinsic::atomic_load_and:
4650 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4651 case Intrinsic::atomic_load_nand:
4652 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4653 case Intrinsic::atomic_load_max:
4654 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4655 case Intrinsic::atomic_load_min:
4656 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4657 case Intrinsic::atomic_load_umin:
4658 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4659 case Intrinsic::atomic_load_umax:
4660 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4661 case Intrinsic::atomic_swap:
4662 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4664 case Intrinsic::invariant_start:
4665 case Intrinsic::lifetime_start:
4666 // Discard region information.
4667 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4669 case Intrinsic::invariant_end:
4670 case Intrinsic::lifetime_end:
4671 // Discard region information.
4676 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4678 MachineBasicBlock *LandingPad) {
4679 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4680 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4681 const Type *RetTy = FTy->getReturnType();
4682 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4683 MCSymbol *BeginLabel = 0;
4685 TargetLowering::ArgListTy Args;
4686 TargetLowering::ArgListEntry Entry;
4687 Args.reserve(CS.arg_size());
4689 // Check whether the function can return without sret-demotion.
4690 SmallVector<ISD::OutputArg, 4> Outs;
4691 SmallVector<uint64_t, 4> Offsets;
4692 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4693 Outs, TLI, &Offsets);
4695 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4696 FTy->isVarArg(), Outs, FTy->getContext());
4698 SDValue DemoteStackSlot;
4699 int DemoteStackIdx = -100;
4701 if (!CanLowerReturn) {
4702 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4703 FTy->getReturnType());
4704 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4705 FTy->getReturnType());
4706 MachineFunction &MF = DAG.getMachineFunction();
4707 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4708 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4710 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4711 Entry.Node = DemoteStackSlot;
4712 Entry.Ty = StackSlotPtrType;
4713 Entry.isSExt = false;
4714 Entry.isZExt = false;
4715 Entry.isInReg = false;
4716 Entry.isSRet = true;
4717 Entry.isNest = false;
4718 Entry.isByVal = false;
4719 Entry.Alignment = Align;
4720 Args.push_back(Entry);
4721 RetTy = Type::getVoidTy(FTy->getContext());
4724 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4726 SDValue ArgNode = getValue(*i);
4727 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4729 unsigned attrInd = i - CS.arg_begin() + 1;
4730 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4731 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4732 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4733 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4734 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4735 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4736 Entry.Alignment = CS.getParamAlignment(attrInd);
4737 Args.push_back(Entry);
4741 // Insert a label before the invoke call to mark the try range. This can be
4742 // used to detect deletion of the invoke via the MachineModuleInfo.
4743 BeginLabel = MMI.getContext().CreateTempSymbol();
4745 // For SjLj, keep track of which landing pads go with which invokes
4746 // so as to maintain the ordering of pads in the LSDA.
4747 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4748 if (CallSiteIndex) {
4749 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4750 // Now that the call site is handled, stop tracking it.
4751 MMI.setCurrentCallSite(0);
4754 // Both PendingLoads and PendingExports must be flushed here;
4755 // this call might not return.
4757 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4760 // Check if target-independent constraints permit a tail call here.
4761 // Target-dependent constraints are checked within TLI.LowerCallTo.
4763 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4766 // If there's a possibility that fast-isel has already selected some amount
4767 // of the current basic block, don't emit a tail call.
4768 if (isTailCall && EnableFastISel)
4771 std::pair<SDValue,SDValue> Result =
4772 TLI.LowerCallTo(getRoot(), RetTy,
4773 CS.paramHasAttr(0, Attribute::SExt),
4774 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4775 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4776 CS.getCallingConv(),
4778 !CS.getInstruction()->use_empty(),
4779 Callee, Args, DAG, getCurDebugLoc());
4780 assert((isTailCall || Result.second.getNode()) &&
4781 "Non-null chain expected with non-tail call!");
4782 assert((Result.second.getNode() || !Result.first.getNode()) &&
4783 "Null value expected with tail call!");
4784 if (Result.first.getNode()) {
4785 setValue(CS.getInstruction(), Result.first);
4786 } else if (!CanLowerReturn && Result.second.getNode()) {
4787 // The instruction result is the result of loading from the
4788 // hidden sret parameter.
4789 SmallVector<EVT, 1> PVTs;
4790 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4792 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4793 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4794 EVT PtrVT = PVTs[0];
4795 unsigned NumValues = Outs.size();
4796 SmallVector<SDValue, 4> Values(NumValues);
4797 SmallVector<SDValue, 4> Chains(NumValues);
4799 for (unsigned i = 0; i < NumValues; ++i) {
4800 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4802 DAG.getConstant(Offsets[i], PtrVT));
4803 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4805 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4808 Chains[i] = L.getValue(1);
4811 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4812 MVT::Other, &Chains[0], NumValues);
4813 PendingLoads.push_back(Chain);
4815 // Collect the legal value parts into potentially illegal values
4816 // that correspond to the original function's return values.
4817 SmallVector<EVT, 4> RetTys;
4818 RetTy = FTy->getReturnType();
4819 ComputeValueVTs(TLI, RetTy, RetTys);
4820 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4821 SmallVector<SDValue, 4> ReturnValues;
4822 unsigned CurReg = 0;
4823 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4825 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4826 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4828 SDValue ReturnValue =
4829 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4830 RegisterVT, VT, AssertOp);
4831 ReturnValues.push_back(ReturnValue);
4835 setValue(CS.getInstruction(),
4836 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4837 DAG.getVTList(&RetTys[0], RetTys.size()),
4838 &ReturnValues[0], ReturnValues.size()));
4842 // As a special case, a null chain means that a tail call has been emitted and
4843 // the DAG root is already updated.
4844 if (Result.second.getNode())
4845 DAG.setRoot(Result.second);
4850 // Insert a label at the end of the invoke call to mark the try range. This
4851 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4852 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4853 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4855 // Inform MachineModuleInfo of range.
4856 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4860 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4861 /// value is equal or not-equal to zero.
4862 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4863 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4865 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4866 if (IC->isEquality())
4867 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4868 if (C->isNullValue())
4870 // Unknown instruction.
4876 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4878 SelectionDAGBuilder &Builder) {
4880 // Check to see if this load can be trivially constant folded, e.g. if the
4881 // input is from a string literal.
4882 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4883 // Cast pointer to the type we really want to load.
4884 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4885 PointerType::getUnqual(LoadTy));
4887 if (const Constant *LoadCst =
4888 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4890 return Builder.getValue(LoadCst);
4893 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4894 // still constant memory, the input chain can be the entry node.
4896 bool ConstantMemory = false;
4898 // Do not serialize (non-volatile) loads of constant memory with anything.
4899 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4900 Root = Builder.DAG.getEntryNode();
4901 ConstantMemory = true;
4903 // Do not serialize non-volatile loads against each other.
4904 Root = Builder.DAG.getRoot();
4907 SDValue Ptr = Builder.getValue(PtrVal);
4908 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
4909 Ptr, MachinePointerInfo(PtrVal),
4911 false /*nontemporal*/, 1 /* align=1 */);
4913 if (!ConstantMemory)
4914 Builder.PendingLoads.push_back(LoadVal.getValue(1));
4919 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
4920 /// If so, return true and lower it, otherwise return false and it will be
4921 /// lowered like a normal call.
4922 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
4923 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
4924 if (I.getNumArgOperands() != 3)
4927 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
4928 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
4929 !I.getArgOperand(2)->getType()->isIntegerTy() ||
4930 !I.getType()->isIntegerTy())
4933 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
4935 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
4936 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
4937 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
4938 bool ActuallyDoIt = true;
4941 switch (Size->getZExtValue()) {
4943 LoadVT = MVT::Other;
4945 ActuallyDoIt = false;
4949 LoadTy = Type::getInt16Ty(Size->getContext());
4953 LoadTy = Type::getInt32Ty(Size->getContext());
4957 LoadTy = Type::getInt64Ty(Size->getContext());
4961 LoadVT = MVT::v4i32;
4962 LoadTy = Type::getInt32Ty(Size->getContext());
4963 LoadTy = VectorType::get(LoadTy, 4);
4968 // This turns into unaligned loads. We only do this if the target natively
4969 // supports the MVT we'll be loading or if it is small enough (<= 4) that
4970 // we'll only produce a small number of byte loads.
4972 // Require that we can find a legal MVT, and only do this if the target
4973 // supports unaligned loads of that type. Expanding into byte loads would
4975 if (ActuallyDoIt && Size->getZExtValue() > 4) {
4976 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
4977 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
4978 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
4979 ActuallyDoIt = false;
4983 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
4984 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
4986 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
4988 EVT CallVT = TLI.getValueType(I.getType(), true);
4989 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
4999 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5000 // Handle inline assembly differently.
5001 if (isa<InlineAsm>(I.getCalledValue())) {
5006 const char *RenameFn = 0;
5007 if (Function *F = I.getCalledFunction()) {
5008 if (F->isDeclaration()) {
5009 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5010 if (unsigned IID = II->getIntrinsicID(F)) {
5011 RenameFn = visitIntrinsicCall(I, IID);
5016 if (unsigned IID = F->getIntrinsicID()) {
5017 RenameFn = visitIntrinsicCall(I, IID);
5023 // See if any floating point values are being passed to this external
5024 // function. This is used to emit an undefined reference to fltused on
5026 if (!F->hasLocalLinkage() && F->hasName()) {
5027 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5028 for (unsigned i = 0, e = I.getNumArgOperands(); i != e &&
5029 !MMI.callsExternalFunctionWithFloatingPointArguments(); ++i) {
5030 const Type* T = I.getArgOperand(i)->getType();
5031 for (po_iterator<const Type*> i = po_begin(T),
5034 if (i->isFloatingPointTy()) {
5035 MMI.setCallsExternalFunctionWithFloatingPointArguments(true);
5042 // Check for well-known libc/libm calls. If the function is internal, it
5043 // can't be a library call.
5044 if (!F->hasLocalLinkage() && F->hasName()) {
5045 StringRef Name = F->getName();
5046 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5047 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5048 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5049 I.getType() == I.getArgOperand(0)->getType() &&
5050 I.getType() == I.getArgOperand(1)->getType()) {
5051 SDValue LHS = getValue(I.getArgOperand(0));
5052 SDValue RHS = getValue(I.getArgOperand(1));
5053 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5054 LHS.getValueType(), LHS, RHS));
5057 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5058 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5059 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5060 I.getType() == I.getArgOperand(0)->getType()) {
5061 SDValue Tmp = getValue(I.getArgOperand(0));
5062 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5063 Tmp.getValueType(), Tmp));
5066 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5067 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5068 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5069 I.getType() == I.getArgOperand(0)->getType() &&
5070 I.onlyReadsMemory()) {
5071 SDValue Tmp = getValue(I.getArgOperand(0));
5072 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5073 Tmp.getValueType(), Tmp));
5076 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5077 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5078 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5079 I.getType() == I.getArgOperand(0)->getType() &&
5080 I.onlyReadsMemory()) {
5081 SDValue Tmp = getValue(I.getArgOperand(0));
5082 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5083 Tmp.getValueType(), Tmp));
5086 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5087 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5088 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5089 I.getType() == I.getArgOperand(0)->getType() &&
5090 I.onlyReadsMemory()) {
5091 SDValue Tmp = getValue(I.getArgOperand(0));
5092 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5093 Tmp.getValueType(), Tmp));
5096 } else if (Name == "memcmp") {
5097 if (visitMemCmpCall(I))
5105 Callee = getValue(I.getCalledValue());
5107 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5109 // Check if we can potentially perform a tail call. More detailed checking is
5110 // be done within LowerCallTo, after more information about the call is known.
5111 LowerCallTo(&I, Callee, I.isTailCall());
5116 /// AsmOperandInfo - This contains information for each constraint that we are
5118 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5119 public TargetLowering::AsmOperandInfo {
5121 /// CallOperand - If this is the result output operand or a clobber
5122 /// this is null, otherwise it is the incoming operand to the CallInst.
5123 /// This gets modified as the asm is processed.
5124 SDValue CallOperand;
5126 /// AssignedRegs - If this is a register or register class operand, this
5127 /// contains the set of register corresponding to the operand.
5128 RegsForValue AssignedRegs;
5130 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5131 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5134 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5135 /// busy in OutputRegs/InputRegs.
5136 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5137 std::set<unsigned> &OutputRegs,
5138 std::set<unsigned> &InputRegs,
5139 const TargetRegisterInfo &TRI) const {
5141 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5142 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5145 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5146 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5150 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5151 /// corresponds to. If there is no Value* for this operand, it returns
5153 EVT getCallOperandValEVT(LLVMContext &Context,
5154 const TargetLowering &TLI,
5155 const TargetData *TD) const {
5156 if (CallOperandVal == 0) return MVT::Other;
5158 if (isa<BasicBlock>(CallOperandVal))
5159 return TLI.getPointerTy();
5161 const llvm::Type *OpTy = CallOperandVal->getType();
5163 // If this is an indirect operand, the operand is a pointer to the
5166 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5168 report_fatal_error("Indirect operand for inline asm not a pointer!");
5169 OpTy = PtrTy->getElementType();
5172 // If OpTy is not a single value, it may be a struct/union that we
5173 // can tile with integers.
5174 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5175 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5184 OpTy = IntegerType::get(Context, BitSize);
5189 return TLI.getValueType(OpTy, true);
5193 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5195 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5196 const TargetRegisterInfo &TRI) {
5197 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5199 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5200 for (; *Aliases; ++Aliases)
5201 Regs.insert(*Aliases);
5205 } // end llvm namespace.
5207 /// isAllocatableRegister - If the specified register is safe to allocate,
5208 /// i.e. it isn't a stack pointer or some other special register, return the
5209 /// register class for the register. Otherwise, return null.
5210 static const TargetRegisterClass *
5211 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5212 const TargetLowering &TLI,
5213 const TargetRegisterInfo *TRI) {
5214 EVT FoundVT = MVT::Other;
5215 const TargetRegisterClass *FoundRC = 0;
5216 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5217 E = TRI->regclass_end(); RCI != E; ++RCI) {
5218 EVT ThisVT = MVT::Other;
5220 const TargetRegisterClass *RC = *RCI;
5221 // If none of the value types for this register class are valid, we
5222 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5223 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5225 if (TLI.isTypeLegal(*I)) {
5226 // If we have already found this register in a different register class,
5227 // choose the one with the largest VT specified. For example, on
5228 // PowerPC, we favor f64 register classes over f32.
5229 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5236 if (ThisVT == MVT::Other) continue;
5238 // NOTE: This isn't ideal. In particular, this might allocate the
5239 // frame pointer in functions that need it (due to them not being taken
5240 // out of allocation, because a variable sized allocation hasn't been seen
5241 // yet). This is a slight code pessimization, but should still work.
5242 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5243 E = RC->allocation_order_end(MF); I != E; ++I)
5245 // We found a matching register class. Keep looking at others in case
5246 // we find one with larger registers that this physreg is also in.
5255 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5256 /// specified operand. We prefer to assign virtual registers, to allow the
5257 /// register allocator to handle the assignment process. However, if the asm
5258 /// uses features that we can't model on machineinstrs, we have SDISel do the
5259 /// allocation. This produces generally horrible, but correct, code.
5261 /// OpInfo describes the operand.
5262 /// Input and OutputRegs are the set of already allocated physical registers.
5264 void SelectionDAGBuilder::
5265 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5266 std::set<unsigned> &OutputRegs,
5267 std::set<unsigned> &InputRegs) {
5268 LLVMContext &Context = FuncInfo.Fn->getContext();
5270 // Compute whether this value requires an input register, an output register,
5272 bool isOutReg = false;
5273 bool isInReg = false;
5274 switch (OpInfo.Type) {
5275 case InlineAsm::isOutput:
5278 // If there is an input constraint that matches this, we need to reserve
5279 // the input register so no other inputs allocate to it.
5280 isInReg = OpInfo.hasMatchingInput();
5282 case InlineAsm::isInput:
5286 case InlineAsm::isClobber:
5293 MachineFunction &MF = DAG.getMachineFunction();
5294 SmallVector<unsigned, 4> Regs;
5296 // If this is a constraint for a single physreg, or a constraint for a
5297 // register class, find it.
5298 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5299 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5300 OpInfo.ConstraintVT);
5302 unsigned NumRegs = 1;
5303 if (OpInfo.ConstraintVT != MVT::Other) {
5304 // If this is a FP input in an integer register (or visa versa) insert a bit
5305 // cast of the input value. More generally, handle any case where the input
5306 // value disagrees with the register class we plan to stick this in.
5307 if (OpInfo.Type == InlineAsm::isInput &&
5308 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5309 // Try to convert to the first EVT that the reg class contains. If the
5310 // types are identical size, use a bitcast to convert (e.g. two differing
5312 EVT RegVT = *PhysReg.second->vt_begin();
5313 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5314 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5315 RegVT, OpInfo.CallOperand);
5316 OpInfo.ConstraintVT = RegVT;
5317 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5318 // If the input is a FP value and we want it in FP registers, do a
5319 // bitcast to the corresponding integer type. This turns an f64 value
5320 // into i64, which can be passed with two i32 values on a 32-bit
5322 RegVT = EVT::getIntegerVT(Context,
5323 OpInfo.ConstraintVT.getSizeInBits());
5324 OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5325 RegVT, OpInfo.CallOperand);
5326 OpInfo.ConstraintVT = RegVT;
5330 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5334 EVT ValueVT = OpInfo.ConstraintVT;
5336 // If this is a constraint for a specific physical register, like {r17},
5338 if (unsigned AssignedReg = PhysReg.first) {
5339 const TargetRegisterClass *RC = PhysReg.second;
5340 if (OpInfo.ConstraintVT == MVT::Other)
5341 ValueVT = *RC->vt_begin();
5343 // Get the actual register value type. This is important, because the user
5344 // may have asked for (e.g.) the AX register in i32 type. We need to
5345 // remember that AX is actually i16 to get the right extension.
5346 RegVT = *RC->vt_begin();
5348 // This is a explicit reference to a physical register.
5349 Regs.push_back(AssignedReg);
5351 // If this is an expanded reference, add the rest of the regs to Regs.
5353 TargetRegisterClass::iterator I = RC->begin();
5354 for (; *I != AssignedReg; ++I)
5355 assert(I != RC->end() && "Didn't find reg!");
5357 // Already added the first reg.
5359 for (; NumRegs; --NumRegs, ++I) {
5360 assert(I != RC->end() && "Ran out of registers to allocate!");
5365 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5366 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5367 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5371 // Otherwise, if this was a reference to an LLVM register class, create vregs
5372 // for this reference.
5373 if (const TargetRegisterClass *RC = PhysReg.second) {
5374 RegVT = *RC->vt_begin();
5375 if (OpInfo.ConstraintVT == MVT::Other)
5378 // Create the appropriate number of virtual registers.
5379 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5380 for (; NumRegs; --NumRegs)
5381 Regs.push_back(RegInfo.createVirtualRegister(RC));
5383 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5387 // This is a reference to a register class that doesn't directly correspond
5388 // to an LLVM register class. Allocate NumRegs consecutive, available,
5389 // registers from the class.
5390 std::vector<unsigned> RegClassRegs
5391 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5392 OpInfo.ConstraintVT);
5394 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5395 unsigned NumAllocated = 0;
5396 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5397 unsigned Reg = RegClassRegs[i];
5398 // See if this register is available.
5399 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5400 (isInReg && InputRegs.count(Reg))) { // Already used.
5401 // Make sure we find consecutive registers.
5406 // Check to see if this register is allocatable (i.e. don't give out the
5408 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5409 if (!RC) { // Couldn't allocate this register.
5410 // Reset NumAllocated to make sure we return consecutive registers.
5415 // Okay, this register is good, we can use it.
5418 // If we allocated enough consecutive registers, succeed.
5419 if (NumAllocated == NumRegs) {
5420 unsigned RegStart = (i-NumAllocated)+1;
5421 unsigned RegEnd = i+1;
5422 // Mark all of the allocated registers used.
5423 for (unsigned i = RegStart; i != RegEnd; ++i)
5424 Regs.push_back(RegClassRegs[i]);
5426 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5427 OpInfo.ConstraintVT);
5428 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5433 // Otherwise, we couldn't allocate enough registers for this.
5436 /// visitInlineAsm - Handle a call to an InlineAsm object.
5438 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5439 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5441 /// ConstraintOperands - Information about all of the constraints.
5442 std::vector<SDISelAsmOperandInfo> ConstraintOperands;
5444 std::set<unsigned> OutputRegs, InputRegs;
5446 std::vector<TargetLowering::AsmOperandInfo> TargetConstraints = TLI.ParseConstraints(CS);
5447 bool hasMemory = false;
5449 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5450 unsigned ResNo = 0; // ResNo - The result number of the next output.
5451 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5452 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5453 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5455 EVT OpVT = MVT::Other;
5457 // Compute the value type for each operand.
5458 switch (OpInfo.Type) {
5459 case InlineAsm::isOutput:
5460 // Indirect outputs just consume an argument.
5461 if (OpInfo.isIndirect) {
5462 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5466 // The return value of the call is this value. As such, there is no
5467 // corresponding argument.
5468 assert(!CS.getType()->isVoidTy() &&
5470 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5471 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5473 assert(ResNo == 0 && "Asm only has one result!");
5474 OpVT = TLI.getValueType(CS.getType());
5478 case InlineAsm::isInput:
5479 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5481 case InlineAsm::isClobber:
5486 // If this is an input or an indirect output, process the call argument.
5487 // BasicBlocks are labels, currently appearing only in asm's.
5488 if (OpInfo.CallOperandVal) {
5489 // Strip bitcasts, if any. This mostly comes up for functions.
5490 OpInfo.CallOperandVal = OpInfo.CallOperandVal->stripPointerCasts();
5492 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5493 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5495 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5498 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5501 OpInfo.ConstraintVT = OpVT;
5503 // Indirect operand accesses access memory.
5504 if (OpInfo.isIndirect)
5507 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5508 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5509 if (CType == TargetLowering::C_Memory) {
5517 SDValue Chain, Flag;
5519 // We won't need to flush pending loads if this asm doesn't touch
5520 // memory and is nonvolatile.
5521 if (hasMemory || IA->hasSideEffects())
5524 Chain = DAG.getRoot();
5526 // Second pass over the constraints: compute which constraint option to use
5527 // and assign registers to constraints that want a specific physreg.
5528 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5529 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5531 // If this is an output operand with a matching input operand, look up the
5532 // matching input. If their types mismatch, e.g. one is an integer, the
5533 // other is floating point, or their sizes are different, flag it as an
5535 if (OpInfo.hasMatchingInput()) {
5536 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5538 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5539 if ((OpInfo.ConstraintVT.isInteger() !=
5540 Input.ConstraintVT.isInteger()) ||
5541 (OpInfo.ConstraintVT.getSizeInBits() !=
5542 Input.ConstraintVT.getSizeInBits())) {
5543 report_fatal_error("Unsupported asm: input constraint"
5544 " with a matching output constraint of"
5545 " incompatible type!");
5547 Input.ConstraintVT = OpInfo.ConstraintVT;
5551 // Compute the constraint code and ConstraintType to use.
5552 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5554 // If this is a memory input, and if the operand is not indirect, do what we
5555 // need to to provide an address for the memory input.
5556 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5557 !OpInfo.isIndirect) {
5558 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5559 "Can only indirectify direct input operands!");
5561 // Memory operands really want the address of the value. If we don't have
5562 // an indirect input, put it in the constpool if we can, otherwise spill
5563 // it to a stack slot.
5565 // If the operand is a float, integer, or vector constant, spill to a
5566 // constant pool entry to get its address.
5567 const Value *OpVal = OpInfo.CallOperandVal;
5568 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5569 isa<ConstantVector>(OpVal)) {
5570 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5571 TLI.getPointerTy());
5573 // Otherwise, create a stack slot and emit a store to it before the
5575 const Type *Ty = OpVal->getType();
5576 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5577 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5578 MachineFunction &MF = DAG.getMachineFunction();
5579 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5580 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5581 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5582 OpInfo.CallOperand, StackSlot,
5583 MachinePointerInfo::getFixedStack(SSFI),
5585 OpInfo.CallOperand = StackSlot;
5588 // There is no longer a Value* corresponding to this operand.
5589 OpInfo.CallOperandVal = 0;
5591 // It is now an indirect operand.
5592 OpInfo.isIndirect = true;
5595 // If this constraint is for a specific register, allocate it before
5597 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5598 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5601 // Second pass - Loop over all of the operands, assigning virtual or physregs
5602 // to register class operands.
5603 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5604 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5606 // C_Register operands have already been allocated, Other/Memory don't need
5608 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5609 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5612 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5613 std::vector<SDValue> AsmNodeOperands;
5614 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5615 AsmNodeOperands.push_back(
5616 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5617 TLI.getPointerTy()));
5619 // If we have a !srcloc metadata node associated with it, we want to attach
5620 // this to the ultimately generated inline asm machineinstr. To do this, we
5621 // pass in the third operand as this (potentially null) inline asm MDNode.
5622 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5623 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5625 // Remember the AlignStack bit as operand 3.
5626 AsmNodeOperands.push_back(DAG.getTargetConstant(IA->isAlignStack() ? 1 : 0,
5629 // Loop over all of the inputs, copying the operand values into the
5630 // appropriate registers and processing the output regs.
5631 RegsForValue RetValRegs;
5633 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5634 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5636 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5637 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5639 switch (OpInfo.Type) {
5640 case InlineAsm::isOutput: {
5641 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5642 OpInfo.ConstraintType != TargetLowering::C_Register) {
5643 // Memory output, or 'other' output (e.g. 'X' constraint).
5644 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5646 // Add information to the INLINEASM node to know about this output.
5647 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5648 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5649 TLI.getPointerTy()));
5650 AsmNodeOperands.push_back(OpInfo.CallOperand);
5654 // Otherwise, this is a register or register class output.
5656 // Copy the output from the appropriate register. Find a register that
5658 if (OpInfo.AssignedRegs.Regs.empty())
5659 report_fatal_error("Couldn't allocate output reg for constraint '" +
5660 Twine(OpInfo.ConstraintCode) + "'!");
5662 // If this is an indirect operand, store through the pointer after the
5664 if (OpInfo.isIndirect) {
5665 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5666 OpInfo.CallOperandVal));
5668 // This is the result value of the call.
5669 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5670 // Concatenate this output onto the outputs list.
5671 RetValRegs.append(OpInfo.AssignedRegs);
5674 // Add information to the INLINEASM node to know that this register is
5676 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5677 InlineAsm::Kind_RegDefEarlyClobber :
5678 InlineAsm::Kind_RegDef,
5685 case InlineAsm::isInput: {
5686 SDValue InOperandVal = OpInfo.CallOperand;
5688 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5689 // If this is required to match an output register we have already set,
5690 // just use its register.
5691 unsigned OperandNo = OpInfo.getMatchedOperand();
5693 // Scan until we find the definition we already emitted of this operand.
5694 // When we find it, create a RegsForValue operand.
5695 unsigned CurOp = InlineAsm::Op_FirstOperand;
5696 for (; OperandNo; --OperandNo) {
5697 // Advance to the next operand.
5699 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5700 assert((InlineAsm::isRegDefKind(OpFlag) ||
5701 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5702 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5703 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5707 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5708 if (InlineAsm::isRegDefKind(OpFlag) ||
5709 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5710 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5711 if (OpInfo.isIndirect) {
5712 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5713 LLVMContext &Ctx = *DAG.getContext();
5714 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5715 " don't know how to handle tied "
5716 "indirect register inputs");
5719 RegsForValue MatchedRegs;
5720 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5721 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5722 MatchedRegs.RegVTs.push_back(RegVT);
5723 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5724 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5726 MatchedRegs.Regs.push_back
5727 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5729 // Use the produced MatchedRegs object to
5730 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5732 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5733 true, OpInfo.getMatchedOperand(),
5734 DAG, AsmNodeOperands);
5738 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5739 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5740 "Unexpected number of operands");
5741 // Add information to the INLINEASM node to know about this input.
5742 // See InlineAsm.h isUseOperandTiedToDef.
5743 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5744 OpInfo.getMatchedOperand());
5745 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5746 TLI.getPointerTy()));
5747 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5751 // Treat indirect 'X' constraint as memory.
5752 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5754 OpInfo.ConstraintType = TargetLowering::C_Memory;
5756 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5757 std::vector<SDValue> Ops;
5758 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5761 report_fatal_error("Invalid operand for inline asm constraint '" +
5762 Twine(OpInfo.ConstraintCode) + "'!");
5764 // Add information to the INLINEASM node to know about this input.
5765 unsigned ResOpType =
5766 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5767 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5768 TLI.getPointerTy()));
5769 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5773 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5774 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5775 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5776 "Memory operands expect pointer values");
5778 // Add information to the INLINEASM node to know about this input.
5779 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5780 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5781 TLI.getPointerTy()));
5782 AsmNodeOperands.push_back(InOperandVal);
5786 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5787 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5788 "Unknown constraint type!");
5789 assert(!OpInfo.isIndirect &&
5790 "Don't know how to handle indirect register inputs yet!");
5792 // Copy the input into the appropriate registers.
5793 if (OpInfo.AssignedRegs.Regs.empty() ||
5794 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5795 report_fatal_error("Couldn't allocate input reg for constraint '" +
5796 Twine(OpInfo.ConstraintCode) + "'!");
5798 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5801 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5802 DAG, AsmNodeOperands);
5805 case InlineAsm::isClobber: {
5806 // Add the clobbered value to the operand list, so that the register
5807 // allocator is aware that the physreg got clobbered.
5808 if (!OpInfo.AssignedRegs.Regs.empty())
5809 OpInfo.AssignedRegs.AddInlineAsmOperands(
5810 InlineAsm::Kind_RegDefEarlyClobber,
5818 // Finish up input operands. Set the input chain and add the flag last.
5819 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5820 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5822 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5823 DAG.getVTList(MVT::Other, MVT::Flag),
5824 &AsmNodeOperands[0], AsmNodeOperands.size());
5825 Flag = Chain.getValue(1);
5827 // If this asm returns a register value, copy the result from that register
5828 // and set it as the value of the call.
5829 if (!RetValRegs.Regs.empty()) {
5830 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5833 // FIXME: Why don't we do this for inline asms with MRVs?
5834 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5835 EVT ResultType = TLI.getValueType(CS.getType());
5837 // If any of the results of the inline asm is a vector, it may have the
5838 // wrong width/num elts. This can happen for register classes that can
5839 // contain multiple different value types. The preg or vreg allocated may
5840 // not have the same VT as was expected. Convert it to the right type
5841 // with bit_convert.
5842 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5843 Val = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
5846 } else if (ResultType != Val.getValueType() &&
5847 ResultType.isInteger() && Val.getValueType().isInteger()) {
5848 // If a result value was tied to an input value, the computed result may
5849 // have a wider width than the expected result. Extract the relevant
5851 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5854 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5857 setValue(CS.getInstruction(), Val);
5858 // Don't need to use this as a chain in this case.
5859 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5863 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5865 // Process indirect outputs, first output all of the flagged copies out of
5867 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5868 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5869 const Value *Ptr = IndirectStoresToEmit[i].second;
5870 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5872 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5875 // Emit the non-flagged stores from the physregs.
5876 SmallVector<SDValue, 8> OutChains;
5877 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5878 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5879 StoresToEmit[i].first,
5880 getValue(StoresToEmit[i].second),
5881 MachinePointerInfo(StoresToEmit[i].second),
5883 OutChains.push_back(Val);
5886 if (!OutChains.empty())
5887 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5888 &OutChains[0], OutChains.size());
5893 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5894 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5895 MVT::Other, getRoot(),
5896 getValue(I.getArgOperand(0)),
5897 DAG.getSrcValue(I.getArgOperand(0))));
5900 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
5901 const TargetData &TD = *TLI.getTargetData();
5902 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
5903 getRoot(), getValue(I.getOperand(0)),
5904 DAG.getSrcValue(I.getOperand(0)),
5905 TD.getABITypeAlignment(I.getType()));
5907 DAG.setRoot(V.getValue(1));
5910 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
5911 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
5912 MVT::Other, getRoot(),
5913 getValue(I.getArgOperand(0)),
5914 DAG.getSrcValue(I.getArgOperand(0))));
5917 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
5918 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
5919 MVT::Other, getRoot(),
5920 getValue(I.getArgOperand(0)),
5921 getValue(I.getArgOperand(1)),
5922 DAG.getSrcValue(I.getArgOperand(0)),
5923 DAG.getSrcValue(I.getArgOperand(1))));
5926 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
5927 /// implementation, which just calls LowerCall.
5928 /// FIXME: When all targets are
5929 /// migrated to using LowerCall, this hook should be integrated into SDISel.
5930 std::pair<SDValue, SDValue>
5931 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
5932 bool RetSExt, bool RetZExt, bool isVarArg,
5933 bool isInreg, unsigned NumFixedArgs,
5934 CallingConv::ID CallConv, bool isTailCall,
5935 bool isReturnValueUsed,
5937 ArgListTy &Args, SelectionDAG &DAG,
5938 DebugLoc dl) const {
5939 // Handle all of the outgoing arguments.
5940 SmallVector<ISD::OutputArg, 32> Outs;
5941 SmallVector<SDValue, 32> OutVals;
5942 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
5943 SmallVector<EVT, 4> ValueVTs;
5944 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
5945 for (unsigned Value = 0, NumValues = ValueVTs.size();
5946 Value != NumValues; ++Value) {
5947 EVT VT = ValueVTs[Value];
5948 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
5949 SDValue Op = SDValue(Args[i].Node.getNode(),
5950 Args[i].Node.getResNo() + Value);
5951 ISD::ArgFlagsTy Flags;
5952 unsigned OriginalAlignment =
5953 getTargetData()->getABITypeAlignment(ArgTy);
5959 if (Args[i].isInReg)
5963 if (Args[i].isByVal) {
5965 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
5966 const Type *ElementTy = Ty->getElementType();
5967 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
5968 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
5969 // For ByVal, alignment should come from FE. BE will guess if this
5970 // info is not there but there are cases it cannot get right.
5971 if (Args[i].Alignment)
5972 FrameAlign = Args[i].Alignment;
5973 Flags.setByValAlign(FrameAlign);
5974 Flags.setByValSize(FrameSize);
5978 Flags.setOrigAlign(OriginalAlignment);
5980 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
5981 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
5982 SmallVector<SDValue, 4> Parts(NumParts);
5983 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
5986 ExtendKind = ISD::SIGN_EXTEND;
5987 else if (Args[i].isZExt)
5988 ExtendKind = ISD::ZERO_EXTEND;
5990 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
5991 PartVT, ExtendKind);
5993 for (unsigned j = 0; j != NumParts; ++j) {
5994 // if it isn't first piece, alignment must be 1
5995 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
5997 if (NumParts > 1 && j == 0)
5998 MyFlags.Flags.setSplit();
6000 MyFlags.Flags.setOrigAlign(1);
6002 Outs.push_back(MyFlags);
6003 OutVals.push_back(Parts[j]);
6008 // Handle the incoming return values from the call.
6009 SmallVector<ISD::InputArg, 32> Ins;
6010 SmallVector<EVT, 4> RetTys;
6011 ComputeValueVTs(*this, RetTy, RetTys);
6012 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6014 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6015 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6016 for (unsigned i = 0; i != NumRegs; ++i) {
6017 ISD::InputArg MyFlags;
6018 MyFlags.VT = RegisterVT;
6019 MyFlags.Used = isReturnValueUsed;
6021 MyFlags.Flags.setSExt();
6023 MyFlags.Flags.setZExt();
6025 MyFlags.Flags.setInReg();
6026 Ins.push_back(MyFlags);
6030 SmallVector<SDValue, 4> InVals;
6031 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6032 Outs, OutVals, Ins, dl, DAG, InVals);
6034 // Verify that the target's LowerCall behaved as expected.
6035 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6036 "LowerCall didn't return a valid chain!");
6037 assert((!isTailCall || InVals.empty()) &&
6038 "LowerCall emitted a return value for a tail call!");
6039 assert((isTailCall || InVals.size() == Ins.size()) &&
6040 "LowerCall didn't emit the correct number of values!");
6042 // For a tail call, the return value is merely live-out and there aren't
6043 // any nodes in the DAG representing it. Return a special value to
6044 // indicate that a tail call has been emitted and no more Instructions
6045 // should be processed in the current block.
6048 return std::make_pair(SDValue(), SDValue());
6051 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6052 assert(InVals[i].getNode() &&
6053 "LowerCall emitted a null value!");
6054 assert(Ins[i].VT == InVals[i].getValueType() &&
6055 "LowerCall emitted a value with the wrong type!");
6058 // Collect the legal value parts into potentially illegal values
6059 // that correspond to the original function's return values.
6060 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6062 AssertOp = ISD::AssertSext;
6064 AssertOp = ISD::AssertZext;
6065 SmallVector<SDValue, 4> ReturnValues;
6066 unsigned CurReg = 0;
6067 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6069 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6070 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6072 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6073 NumRegs, RegisterVT, VT,
6078 // For a function returning void, there is no return value. We can't create
6079 // such a node, so we just return a null return value in that case. In
6080 // that case, nothing will actualy look at the value.
6081 if (ReturnValues.empty())
6082 return std::make_pair(SDValue(), Chain);
6084 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6085 DAG.getVTList(&RetTys[0], RetTys.size()),
6086 &ReturnValues[0], ReturnValues.size());
6087 return std::make_pair(Res, Chain);
6090 void TargetLowering::LowerOperationWrapper(SDNode *N,
6091 SmallVectorImpl<SDValue> &Results,
6092 SelectionDAG &DAG) const {
6093 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6095 Results.push_back(Res);
6098 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6099 llvm_unreachable("LowerOperation not implemented for this target!");
6104 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6105 SDValue Op = getNonRegisterValue(V);
6106 assert((Op.getOpcode() != ISD::CopyFromReg ||
6107 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6108 "Copy from a reg to the same reg!");
6109 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6111 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6112 SDValue Chain = DAG.getEntryNode();
6113 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6114 PendingExports.push_back(Chain);
6117 #include "llvm/CodeGen/SelectionDAGISel.h"
6119 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6120 // If this is the entry block, emit arguments.
6121 const Function &F = *LLVMBB->getParent();
6122 SelectionDAG &DAG = SDB->DAG;
6123 DebugLoc dl = SDB->getCurDebugLoc();
6124 const TargetData *TD = TLI.getTargetData();
6125 SmallVector<ISD::InputArg, 16> Ins;
6127 // Check whether the function can return without sret-demotion.
6128 SmallVector<ISD::OutputArg, 4> Outs;
6129 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6132 if (!FuncInfo->CanLowerReturn) {
6133 // Put in an sret pointer parameter before all the other parameters.
6134 SmallVector<EVT, 1> ValueVTs;
6135 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6137 // NOTE: Assuming that a pointer will never break down to more than one VT
6139 ISD::ArgFlagsTy Flags;
6141 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6142 ISD::InputArg RetArg(Flags, RegisterVT, true);
6143 Ins.push_back(RetArg);
6146 // Set up the incoming argument description vector.
6148 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6149 I != E; ++I, ++Idx) {
6150 SmallVector<EVT, 4> ValueVTs;
6151 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6152 bool isArgValueUsed = !I->use_empty();
6153 for (unsigned Value = 0, NumValues = ValueVTs.size();
6154 Value != NumValues; ++Value) {
6155 EVT VT = ValueVTs[Value];
6156 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6157 ISD::ArgFlagsTy Flags;
6158 unsigned OriginalAlignment =
6159 TD->getABITypeAlignment(ArgTy);
6161 if (F.paramHasAttr(Idx, Attribute::ZExt))
6163 if (F.paramHasAttr(Idx, Attribute::SExt))
6165 if (F.paramHasAttr(Idx, Attribute::InReg))
6167 if (F.paramHasAttr(Idx, Attribute::StructRet))
6169 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6171 const PointerType *Ty = cast<PointerType>(I->getType());
6172 const Type *ElementTy = Ty->getElementType();
6173 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6174 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6175 // For ByVal, alignment should be passed from FE. BE will guess if
6176 // this info is not there but there are cases it cannot get right.
6177 if (F.getParamAlignment(Idx))
6178 FrameAlign = F.getParamAlignment(Idx);
6179 Flags.setByValAlign(FrameAlign);
6180 Flags.setByValSize(FrameSize);
6182 if (F.paramHasAttr(Idx, Attribute::Nest))
6184 Flags.setOrigAlign(OriginalAlignment);
6186 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6187 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6188 for (unsigned i = 0; i != NumRegs; ++i) {
6189 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6190 if (NumRegs > 1 && i == 0)
6191 MyFlags.Flags.setSplit();
6192 // if it isn't first piece, alignment must be 1
6194 MyFlags.Flags.setOrigAlign(1);
6195 Ins.push_back(MyFlags);
6200 // Call the target to set up the argument values.
6201 SmallVector<SDValue, 8> InVals;
6202 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6206 // Verify that the target's LowerFormalArguments behaved as expected.
6207 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6208 "LowerFormalArguments didn't return a valid chain!");
6209 assert(InVals.size() == Ins.size() &&
6210 "LowerFormalArguments didn't emit the correct number of values!");
6212 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6213 assert(InVals[i].getNode() &&
6214 "LowerFormalArguments emitted a null value!");
6215 assert(Ins[i].VT == InVals[i].getValueType() &&
6216 "LowerFormalArguments emitted a value with the wrong type!");
6220 // Update the DAG with the new chain value resulting from argument lowering.
6221 DAG.setRoot(NewRoot);
6223 // Set up the argument values.
6226 if (!FuncInfo->CanLowerReturn) {
6227 // Create a virtual register for the sret pointer, and put in a copy
6228 // from the sret argument into it.
6229 SmallVector<EVT, 1> ValueVTs;
6230 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6231 EVT VT = ValueVTs[0];
6232 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6233 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6234 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6235 RegVT, VT, AssertOp);
6237 MachineFunction& MF = SDB->DAG.getMachineFunction();
6238 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6239 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6240 FuncInfo->DemoteRegister = SRetReg;
6241 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6243 DAG.setRoot(NewRoot);
6245 // i indexes lowered arguments. Bump it past the hidden sret argument.
6246 // Idx indexes LLVM arguments. Don't touch it.
6250 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6252 SmallVector<SDValue, 4> ArgValues;
6253 SmallVector<EVT, 4> ValueVTs;
6254 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6255 unsigned NumValues = ValueVTs.size();
6257 // If this argument is unused then remember its value. It is used to generate
6258 // debugging information.
6259 if (I->use_empty() && NumValues)
6260 SDB->setUnusedArgValue(I, InVals[i]);
6262 for (unsigned Value = 0; Value != NumValues; ++Value) {
6263 EVT VT = ValueVTs[Value];
6264 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6265 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6267 if (!I->use_empty()) {
6268 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6269 if (F.paramHasAttr(Idx, Attribute::SExt))
6270 AssertOp = ISD::AssertSext;
6271 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6272 AssertOp = ISD::AssertZext;
6274 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6275 NumParts, PartVT, VT,
6282 // Note down frame index for byval arguments.
6283 if (I->hasByValAttr() && !ArgValues.empty())
6284 if (FrameIndexSDNode *FI =
6285 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6286 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6288 if (!I->use_empty()) {
6290 if (!ArgValues.empty())
6291 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6292 SDB->getCurDebugLoc());
6293 SDB->setValue(I, Res);
6295 // If this argument is live outside of the entry block, insert a copy from
6296 // whereever we got it to the vreg that other BB's will reference it as.
6297 SDB->CopyToExportRegsIfNeeded(I);
6301 assert(i == InVals.size() && "Argument register count mismatch!");
6303 // Finally, if the target has anything special to do, allow it to do so.
6304 // FIXME: this should insert code into the DAG!
6305 EmitFunctionEntryCode();
6308 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6309 /// ensure constants are generated when needed. Remember the virtual registers
6310 /// that need to be added to the Machine PHI nodes as input. We cannot just
6311 /// directly add them, because expansion might result in multiple MBB's for one
6312 /// BB. As such, the start of the BB might correspond to a different MBB than
6316 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6317 const TerminatorInst *TI = LLVMBB->getTerminator();
6319 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6321 // Check successor nodes' PHI nodes that expect a constant to be available
6323 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6324 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6325 if (!isa<PHINode>(SuccBB->begin())) continue;
6326 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6328 // If this terminator has multiple identical successors (common for
6329 // switches), only handle each succ once.
6330 if (!SuccsHandled.insert(SuccMBB)) continue;
6332 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6334 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6335 // nodes and Machine PHI nodes, but the incoming operands have not been
6337 for (BasicBlock::const_iterator I = SuccBB->begin();
6338 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6339 // Ignore dead phi's.
6340 if (PN->use_empty()) continue;
6343 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6345 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6346 unsigned &RegOut = ConstantsOut[C];
6348 RegOut = FuncInfo.CreateRegs(C->getType());
6349 CopyValueToVirtualRegister(C, RegOut);
6353 DenseMap<const Value *, unsigned>::iterator I =
6354 FuncInfo.ValueMap.find(PHIOp);
6355 if (I != FuncInfo.ValueMap.end())
6358 assert(isa<AllocaInst>(PHIOp) &&
6359 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6360 "Didn't codegen value into a register!??");
6361 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6362 CopyValueToVirtualRegister(PHIOp, Reg);
6366 // Remember that this register needs to added to the machine PHI node as
6367 // the input for this MBB.
6368 SmallVector<EVT, 4> ValueVTs;
6369 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6370 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6371 EVT VT = ValueVTs[vti];
6372 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6373 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6374 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6375 Reg += NumRegisters;
6379 ConstantsOut.clear();