1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static const unsigned MaxParallelChains = 64;
89 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
90 const SDValue *Parts, unsigned NumParts,
91 EVT PartVT, EVT ValueVT);
93 /// getCopyFromParts - Create a value that contains the specified legal parts
94 /// combined into the value they represent. If the parts combine to a type
95 /// larger then ValueVT then AssertOp can be used to specify whether the extra
96 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
97 /// (ISD::AssertSext).
98 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 unsigned NumParts, EVT PartVT, EVT ValueVT,
101 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
102 if (ValueVT.isVector())
103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 assert(NumParts > 0 && "No parts to assemble!");
106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
107 SDValue Val = Parts[0];
110 // Assemble the value from multiple parts.
111 if (ValueVT.isInteger()) {
112 unsigned PartBits = PartVT.getSizeInBits();
113 unsigned ValueBits = ValueVT.getSizeInBits();
115 // Assemble the power of 2 part.
116 unsigned RoundParts = NumParts & (NumParts - 1) ?
117 1 << Log2_32(NumParts) : NumParts;
118 unsigned RoundBits = PartBits * RoundParts;
119 EVT RoundVT = RoundBits == ValueBits ?
120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
125 if (RoundParts > 2) {
126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
129 RoundParts / 2, PartVT, HalfVT);
131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
135 if (TLI.isBigEndian())
138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
140 if (RoundParts < NumParts) {
141 // Assemble the trailing non-power-of-2 part.
142 unsigned OddParts = NumParts - RoundParts;
143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
144 Hi = getCopyFromParts(DAG, DL,
145 Parts + RoundParts, OddParts, PartVT, OddVT);
147 // Combine the round and odd parts.
149 if (TLI.isBigEndian())
151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
154 DAG.getConstant(Lo.getValueType().getSizeInBits(),
155 TLI.getPointerTy()));
156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
159 } else if (PartVT.isFloatingPoint()) {
160 // FP split into multiple FP parts (for ppcf128)
161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
166 if (TLI.isBigEndian())
168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
170 // FP split into integer parts (soft fp)
171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
172 !PartVT.isVector() && "Unexpected split");
173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
178 // There is now one part, held in Val. Correct it to match ValueVT.
179 PartVT = Val.getValueType();
181 if (PartVT == ValueVT)
184 if (PartVT.isInteger() && ValueVT.isInteger()) {
185 if (ValueVT.bitsLT(PartVT)) {
186 // For a truncate, see if we have any information to
187 // indicate whether the truncated bits will always be
188 // zero or sign-extension.
189 if (AssertOp != ISD::DELETED_NODE)
190 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
191 DAG.getValueType(ValueVT));
192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
198 // FP_ROUND's are always exact here.
199 if (ValueVT.bitsLT(Val.getValueType()))
200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
201 DAG.getIntPtrConstant(1));
203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
209 llvm_unreachable("Unknown mismatch!");
213 /// getCopyFromParts - Create a value that contains the specified legal parts
214 /// combined into the value they represent. If the parts combine to a type
215 /// larger then ValueVT then AssertOp can be used to specify whether the extra
216 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
217 /// (ISD::AssertSext).
218 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
219 const SDValue *Parts, unsigned NumParts,
220 EVT PartVT, EVT ValueVT) {
221 assert(ValueVT.isVector() && "Not a vector value");
222 assert(NumParts > 0 && "No parts to assemble!");
223 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
224 SDValue Val = Parts[0];
226 // Handle a multi-element vector.
228 EVT IntermediateVT, RegisterVT;
229 unsigned NumIntermediates;
231 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
232 NumIntermediates, RegisterVT);
233 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
234 NumParts = NumRegs; // Silence a compiler warning.
235 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
236 assert(RegisterVT == Parts[0].getValueType() &&
237 "Part type doesn't match part!");
239 // Assemble the parts into intermediate operands.
240 SmallVector<SDValue, 8> Ops(NumIntermediates);
241 if (NumIntermediates == NumParts) {
242 // If the register was not expanded, truncate or copy the value,
244 for (unsigned i = 0; i != NumParts; ++i)
245 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
246 PartVT, IntermediateVT);
247 } else if (NumParts > 0) {
248 // If the intermediate type was expanded, build the intermediate
249 // operands from the parts.
250 assert(NumParts % NumIntermediates == 0 &&
251 "Must expand into a divisible number of parts!");
252 unsigned Factor = NumParts / NumIntermediates;
253 for (unsigned i = 0; i != NumIntermediates; ++i)
254 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
255 PartVT, IntermediateVT);
258 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
259 // intermediate operands.
260 Val = DAG.getNode(IntermediateVT.isVector() ?
261 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
262 ValueVT, &Ops[0], NumIntermediates);
265 // There is now one part, held in Val. Correct it to match ValueVT.
266 PartVT = Val.getValueType();
268 if (PartVT == ValueVT)
271 if (PartVT.isVector()) {
272 // If the element type of the source/dest vectors are the same, but the
273 // parts vector has more elements than the value vector, then we have a
274 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
276 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
277 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
278 "Cannot narrow, it would be a lossy transformation");
279 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
280 DAG.getIntPtrConstant(0));
283 // Vector/Vector bitcast.
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
287 assert(ValueVT.getVectorElementType() == PartVT &&
288 ValueVT.getVectorNumElements() == 1 &&
289 "Only trivial scalar-to-vector conversions should get here!");
290 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
296 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
297 SDValue Val, SDValue *Parts, unsigned NumParts,
300 /// getCopyToParts - Create a series of nodes that contain the specified value
301 /// split into legal parts. If the parts contain more bits than Val, then, for
302 /// integers, ExtendKind can be used to specify how to generate the extra bits.
303 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
304 SDValue Val, SDValue *Parts, unsigned NumParts,
306 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
307 EVT ValueVT = Val.getValueType();
309 // Handle the vector case separately.
310 if (ValueVT.isVector())
311 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
313 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
314 unsigned PartBits = PartVT.getSizeInBits();
315 unsigned OrigNumParts = NumParts;
316 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
321 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
322 if (PartVT == ValueVT) {
323 assert(NumParts == 1 && "No-op copy with multiple parts!");
328 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
329 // If the parts cover more bits than the value has, promote the value.
330 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
331 assert(NumParts == 1 && "Do not know what to promote to!");
332 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
334 assert(PartVT.isInteger() && ValueVT.isInteger() &&
335 "Unknown mismatch!");
336 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
337 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
339 } else if (PartBits == ValueVT.getSizeInBits()) {
340 // Different types of the same size.
341 assert(NumParts == 1 && PartVT != ValueVT);
342 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
343 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
344 // If the parts cover less bits than value has, truncate the value.
345 assert(PartVT.isInteger() && ValueVT.isInteger() &&
346 "Unknown mismatch!");
347 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
348 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
351 // The value may have changed - recompute ValueVT.
352 ValueVT = Val.getValueType();
353 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
354 "Failed to tile the value with PartVT!");
357 assert(PartVT == ValueVT && "Type conversion failed!");
362 // Expand the value into multiple parts.
363 if (NumParts & (NumParts - 1)) {
364 // The number of parts is not a power of 2. Split off and copy the tail.
365 assert(PartVT.isInteger() && ValueVT.isInteger() &&
366 "Do not know what to expand to!");
367 unsigned RoundParts = 1 << Log2_32(NumParts);
368 unsigned RoundBits = RoundParts * PartBits;
369 unsigned OddParts = NumParts - RoundParts;
370 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
371 DAG.getIntPtrConstant(RoundBits));
372 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
374 if (TLI.isBigEndian())
375 // The odd parts were reversed by getCopyToParts - unreverse them.
376 std::reverse(Parts + RoundParts, Parts + NumParts);
378 NumParts = RoundParts;
379 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
380 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
383 // The number of parts is a power of 2. Repeatedly bisect the value using
385 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
386 EVT::getIntegerVT(*DAG.getContext(),
387 ValueVT.getSizeInBits()),
390 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
391 for (unsigned i = 0; i < NumParts; i += StepSize) {
392 unsigned ThisBits = StepSize * PartBits / 2;
393 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
394 SDValue &Part0 = Parts[i];
395 SDValue &Part1 = Parts[i+StepSize/2];
397 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
398 ThisVT, Part0, DAG.getIntPtrConstant(1));
399 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
400 ThisVT, Part0, DAG.getIntPtrConstant(0));
402 if (ThisBits == PartBits && ThisVT != PartVT) {
403 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
404 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
409 if (TLI.isBigEndian())
410 std::reverse(Parts, Parts + OrigNumParts);
414 /// getCopyToPartsVector - Create a series of nodes that contain the specified
415 /// value split into legal parts.
416 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
417 SDValue Val, SDValue *Parts, unsigned NumParts,
419 EVT ValueVT = Val.getValueType();
420 assert(ValueVT.isVector() && "Not a vector");
421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
424 if (PartVT == ValueVT) {
426 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
427 // Bitconvert vector->vector case.
428 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
429 } else if (PartVT.isVector() &&
430 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
431 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
432 EVT ElementVT = PartVT.getVectorElementType();
433 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
435 SmallVector<SDValue, 16> Ops;
436 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
437 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
438 ElementVT, Val, DAG.getIntPtrConstant(i)));
440 for (unsigned i = ValueVT.getVectorNumElements(),
441 e = PartVT.getVectorNumElements(); i != e; ++i)
442 Ops.push_back(DAG.getUNDEF(ElementVT));
444 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
446 // FIXME: Use CONCAT for 2x -> 4x.
448 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
449 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
451 // Vector -> scalar conversion.
452 assert(ValueVT.getVectorElementType() == PartVT &&
453 ValueVT.getVectorNumElements() == 1 &&
454 "Only trivial vector-to-scalar conversions should get here!");
455 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
456 PartVT, Val, DAG.getIntPtrConstant(0));
463 // Handle a multi-element vector.
464 EVT IntermediateVT, RegisterVT;
465 unsigned NumIntermediates;
466 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
468 NumIntermediates, RegisterVT);
469 unsigned NumElements = ValueVT.getVectorNumElements();
471 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
472 NumParts = NumRegs; // Silence a compiler warning.
473 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
475 // Split the vector into intermediate operands.
476 SmallVector<SDValue, 8> Ops(NumIntermediates);
477 for (unsigned i = 0; i != NumIntermediates; ++i) {
478 if (IntermediateVT.isVector())
479 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
481 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
483 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
484 IntermediateVT, Val, DAG.getIntPtrConstant(i));
487 // Split the intermediate operands into legal parts.
488 if (NumParts == NumIntermediates) {
489 // If the register was not expanded, promote or copy the value,
491 for (unsigned i = 0; i != NumParts; ++i)
492 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
493 } else if (NumParts > 0) {
494 // If the intermediate type was expanded, split each the value into
496 assert(NumParts % NumIntermediates == 0 &&
497 "Must expand into a divisible number of parts!");
498 unsigned Factor = NumParts / NumIntermediates;
499 for (unsigned i = 0; i != NumIntermediates; ++i)
500 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
508 /// RegsForValue - This struct represents the registers (physical or virtual)
509 /// that a particular set of values is assigned, and the type information
510 /// about the value. The most common situation is to represent one value at a
511 /// time, but struct or array values are handled element-wise as multiple
512 /// values. The splitting of aggregates is performed recursively, so that we
513 /// never have aggregate-typed registers. The values at this point do not
514 /// necessarily have legal types, so each value may require one or more
515 /// registers of some legal type.
517 struct RegsForValue {
518 /// ValueVTs - The value types of the values, which may not be legal, and
519 /// may need be promoted or synthesized from one or more registers.
521 SmallVector<EVT, 4> ValueVTs;
523 /// RegVTs - The value types of the registers. This is the same size as
524 /// ValueVTs and it records, for each value, what the type of the assigned
525 /// register or registers are. (Individual values are never synthesized
526 /// from more than one type of register.)
528 /// With virtual registers, the contents of RegVTs is redundant with TLI's
529 /// getRegisterType member function, however when with physical registers
530 /// it is necessary to have a separate record of the types.
532 SmallVector<EVT, 4> RegVTs;
534 /// Regs - This list holds the registers assigned to the values.
535 /// Each legal or promoted value requires one register, and each
536 /// expanded value requires multiple registers.
538 SmallVector<unsigned, 4> Regs;
542 RegsForValue(const SmallVector<unsigned, 4> ®s,
543 EVT regvt, EVT valuevt)
544 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
546 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
547 unsigned Reg, const Type *Ty) {
548 ComputeValueVTs(tli, Ty, ValueVTs);
550 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
551 EVT ValueVT = ValueVTs[Value];
552 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
553 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
554 for (unsigned i = 0; i != NumRegs; ++i)
555 Regs.push_back(Reg + i);
556 RegVTs.push_back(RegisterVT);
561 /// areValueTypesLegal - Return true if types of all the values are legal.
562 bool areValueTypesLegal(const TargetLowering &TLI) {
563 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
564 EVT RegisterVT = RegVTs[Value];
565 if (!TLI.isTypeLegal(RegisterVT))
571 /// append - Add the specified values to this one.
572 void append(const RegsForValue &RHS) {
573 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
574 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
575 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
578 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
579 /// this value and returns the result as a ValueVTs value. This uses
580 /// Chain/Flag as the input and updates them for the output Chain/Flag.
581 /// If the Flag pointer is NULL, no flag is used.
582 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
584 SDValue &Chain, SDValue *Flag) const;
586 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
587 /// specified value into the registers specified by this object. This uses
588 /// Chain/Flag as the input and updates them for the output Chain/Flag.
589 /// If the Flag pointer is NULL, no flag is used.
590 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
591 SDValue &Chain, SDValue *Flag) const;
593 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
594 /// operand list. This adds the code marker, matching input operand index
595 /// (if applicable), and includes the number of values added into it.
596 void AddInlineAsmOperands(unsigned Kind,
597 bool HasMatching, unsigned MatchingIdx,
599 std::vector<SDValue> &Ops) const;
603 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
604 /// this value and returns the result as a ValueVT value. This uses
605 /// Chain/Flag as the input and updates them for the output Chain/Flag.
606 /// If the Flag pointer is NULL, no flag is used.
607 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
608 FunctionLoweringInfo &FuncInfo,
610 SDValue &Chain, SDValue *Flag) const {
611 // A Value with type {} or [0 x %t] needs no registers.
612 if (ValueVTs.empty())
615 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
617 // Assemble the legal parts into the final values.
618 SmallVector<SDValue, 4> Values(ValueVTs.size());
619 SmallVector<SDValue, 8> Parts;
620 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
621 // Copy the legal parts from the registers.
622 EVT ValueVT = ValueVTs[Value];
623 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
624 EVT RegisterVT = RegVTs[Value];
626 Parts.resize(NumRegs);
627 for (unsigned i = 0; i != NumRegs; ++i) {
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
633 *Flag = P.getValue(2);
636 Chain = P.getValue(1);
639 // If the source register was virtual and if we know something about it,
640 // add an assert node.
641 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
642 !RegisterVT.isInteger() || RegisterVT.isVector())
645 const FunctionLoweringInfo::LiveOutInfo *LOI =
646 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
650 unsigned RegSize = RegisterVT.getSizeInBits();
651 unsigned NumSignBits = LOI->NumSignBits;
652 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
654 // FIXME: We capture more information than the dag can represent. For
655 // now, just use the tightest assertzext/assertsext possible.
657 EVT FromVT(MVT::Other);
658 if (NumSignBits == RegSize)
659 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
660 else if (NumZeroBits >= RegSize-1)
661 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
662 else if (NumSignBits > RegSize-8)
663 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
664 else if (NumZeroBits >= RegSize-8)
665 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
666 else if (NumSignBits > RegSize-16)
667 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
668 else if (NumZeroBits >= RegSize-16)
669 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
670 else if (NumSignBits > RegSize-32)
671 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
672 else if (NumZeroBits >= RegSize-32)
673 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
677 // Add an assertion node.
678 assert(FromVT != MVT::Other);
679 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
680 RegisterVT, P, DAG.getValueType(FromVT));
683 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
684 NumRegs, RegisterVT, ValueVT);
689 return DAG.getNode(ISD::MERGE_VALUES, dl,
690 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
691 &Values[0], ValueVTs.size());
694 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
695 /// specified value into the registers specified by this object. This uses
696 /// Chain/Flag as the input and updates them for the output Chain/Flag.
697 /// If the Flag pointer is NULL, no flag is used.
698 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
699 SDValue &Chain, SDValue *Flag) const {
700 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
702 // Get the list of the values's legal parts.
703 unsigned NumRegs = Regs.size();
704 SmallVector<SDValue, 8> Parts(NumRegs);
705 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
706 EVT ValueVT = ValueVTs[Value];
707 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
708 EVT RegisterVT = RegVTs[Value];
710 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
711 &Parts[Part], NumParts, RegisterVT);
715 // Copy the parts into the registers.
716 SmallVector<SDValue, 8> Chains(NumRegs);
717 for (unsigned i = 0; i != NumRegs; ++i) {
720 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
722 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
723 *Flag = Part.getValue(1);
726 Chains[i] = Part.getValue(0);
729 if (NumRegs == 1 || Flag)
730 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
731 // flagged to it. That is the CopyToReg nodes and the user are considered
732 // a single scheduling unit. If we create a TokenFactor and return it as
733 // chain, then the TokenFactor is both a predecessor (operand) of the
734 // user as well as a successor (the TF operands are flagged to the user).
735 // c1, f1 = CopyToReg
736 // c2, f2 = CopyToReg
737 // c3 = TokenFactor c1, c2
740 Chain = Chains[NumRegs-1];
742 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
745 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
746 /// operand list. This adds the code marker and includes the number of
747 /// values added into it.
748 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
749 unsigned MatchingIdx,
751 std::vector<SDValue> &Ops) const {
752 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
754 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
756 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
757 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
760 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
761 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
762 EVT RegisterVT = RegVTs[Value];
763 for (unsigned i = 0; i != NumRegs; ++i) {
764 assert(Reg < Regs.size() && "Mismatch in # registers expected");
765 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
770 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
773 TD = DAG.getTarget().getTargetData();
776 /// clear - Clear out the current SelectionDAG and the associated
777 /// state and prepare this SelectionDAGBuilder object to be used
778 /// for a new block. This doesn't clear out information about
779 /// additional blocks that are needed to complete switch lowering
780 /// or PHI node updating; that information is cleared out as it is
782 void SelectionDAGBuilder::clear() {
784 UnusedArgNodeMap.clear();
785 PendingLoads.clear();
786 PendingExports.clear();
787 DanglingDebugInfoMap.clear();
788 CurDebugLoc = DebugLoc();
792 /// getRoot - Return the current virtual root of the Selection DAG,
793 /// flushing any PendingLoad items. This must be done before emitting
794 /// a store or any other node that may need to be ordered after any
795 /// prior load instructions.
797 SDValue SelectionDAGBuilder::getRoot() {
798 if (PendingLoads.empty())
799 return DAG.getRoot();
801 if (PendingLoads.size() == 1) {
802 SDValue Root = PendingLoads[0];
804 PendingLoads.clear();
808 // Otherwise, we have to make a token factor node.
809 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
810 &PendingLoads[0], PendingLoads.size());
811 PendingLoads.clear();
816 /// getControlRoot - Similar to getRoot, but instead of flushing all the
817 /// PendingLoad items, flush all the PendingExports items. It is necessary
818 /// to do this before emitting a terminator instruction.
820 SDValue SelectionDAGBuilder::getControlRoot() {
821 SDValue Root = DAG.getRoot();
823 if (PendingExports.empty())
826 // Turn all of the CopyToReg chains into one factored node.
827 if (Root.getOpcode() != ISD::EntryToken) {
828 unsigned i = 0, e = PendingExports.size();
829 for (; i != e; ++i) {
830 assert(PendingExports[i].getNode()->getNumOperands() > 1);
831 if (PendingExports[i].getNode()->getOperand(0) == Root)
832 break; // Don't add the root if we already indirectly depend on it.
836 PendingExports.push_back(Root);
839 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
841 PendingExports.size());
842 PendingExports.clear();
847 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
848 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
849 DAG.AssignOrdering(Node, SDNodeOrder);
851 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
852 AssignOrderingToNode(Node->getOperand(I).getNode());
855 void SelectionDAGBuilder::visit(const Instruction &I) {
856 // Set up outgoing PHI node register values before emitting the terminator.
857 if (isa<TerminatorInst>(&I))
858 HandlePHINodesInSuccessorBlocks(I.getParent());
860 CurDebugLoc = I.getDebugLoc();
862 visit(I.getOpcode(), I);
864 if (!isa<TerminatorInst>(&I) && !HasTailCall)
865 CopyToExportRegsIfNeeded(&I);
867 CurDebugLoc = DebugLoc();
870 void SelectionDAGBuilder::visitPHI(const PHINode &) {
871 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
874 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
875 // Note: this doesn't use InstVisitor, because it has to work with
876 // ConstantExpr's in addition to instructions.
878 default: llvm_unreachable("Unknown instruction type encountered!");
879 // Build the switch statement using the Instruction.def file.
880 #define HANDLE_INST(NUM, OPCODE, CLASS) \
881 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
882 #include "llvm/Instruction.def"
885 // Assign the ordering to the freshly created DAG nodes.
886 if (NodeMap.count(&I)) {
888 AssignOrderingToNode(getValue(&I).getNode());
892 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
893 // generate the debug data structures now that we've seen its definition.
894 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
896 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
898 const DbgValueInst *DI = DDI.getDI();
899 DebugLoc dl = DDI.getdl();
900 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
901 MDNode *Variable = DI->getVariable();
902 uint64_t Offset = DI->getOffset();
905 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
906 SDV = DAG.getDbgValue(Variable, Val.getNode(),
907 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
908 DAG.AddDbgValue(SDV, Val.getNode(), false);
911 DEBUG(dbgs() << "Dropping debug info for " << DI);
912 DanglingDebugInfoMap[V] = DanglingDebugInfo();
916 // getValue - Return an SDValue for the given Value.
917 SDValue SelectionDAGBuilder::getValue(const Value *V) {
918 // If we already have an SDValue for this value, use it. It's important
919 // to do this first, so that we don't create a CopyFromReg if we already
920 // have a regular SDValue.
921 SDValue &N = NodeMap[V];
922 if (N.getNode()) return N;
924 // If there's a virtual register allocated and initialized for this
926 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
927 if (It != FuncInfo.ValueMap.end()) {
928 unsigned InReg = It->second;
929 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
930 SDValue Chain = DAG.getEntryNode();
931 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
932 resolveDanglingDebugInfo(V, N);
936 // Otherwise create a new SDValue and remember it.
937 SDValue Val = getValueImpl(V);
939 resolveDanglingDebugInfo(V, Val);
943 /// getNonRegisterValue - Return an SDValue for the given Value, but
944 /// don't look in FuncInfo.ValueMap for a virtual register.
945 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
946 // If we already have an SDValue for this value, use it.
947 SDValue &N = NodeMap[V];
948 if (N.getNode()) return N;
950 // Otherwise create a new SDValue and remember it.
951 SDValue Val = getValueImpl(V);
953 resolveDanglingDebugInfo(V, Val);
957 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
958 /// Create an SDValue for the given value.
959 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
960 if (const Constant *C = dyn_cast<Constant>(V)) {
961 EVT VT = TLI.getValueType(V->getType(), true);
963 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
964 return DAG.getConstant(*CI, VT);
966 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
967 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
969 if (isa<ConstantPointerNull>(C))
970 return DAG.getConstant(0, TLI.getPointerTy());
972 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
973 return DAG.getConstantFP(*CFP, VT);
975 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
976 return DAG.getUNDEF(VT);
978 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
979 visit(CE->getOpcode(), *CE);
980 SDValue N1 = NodeMap[V];
981 assert(N1.getNode() && "visit didn't populate the NodeMap!");
985 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
986 SmallVector<SDValue, 4> Constants;
987 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
989 SDNode *Val = getValue(*OI).getNode();
990 // If the operand is an empty aggregate, there are no values.
992 // Add each leaf value from the operand to the Constants list
993 // to form a flattened list of all the values.
994 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
995 Constants.push_back(SDValue(Val, i));
998 return DAG.getMergeValues(&Constants[0], Constants.size(),
1002 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1003 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1004 "Unknown struct or array constant!");
1006 SmallVector<EVT, 4> ValueVTs;
1007 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1008 unsigned NumElts = ValueVTs.size();
1010 return SDValue(); // empty struct
1011 SmallVector<SDValue, 4> Constants(NumElts);
1012 for (unsigned i = 0; i != NumElts; ++i) {
1013 EVT EltVT = ValueVTs[i];
1014 if (isa<UndefValue>(C))
1015 Constants[i] = DAG.getUNDEF(EltVT);
1016 else if (EltVT.isFloatingPoint())
1017 Constants[i] = DAG.getConstantFP(0, EltVT);
1019 Constants[i] = DAG.getConstant(0, EltVT);
1022 return DAG.getMergeValues(&Constants[0], NumElts,
1026 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1027 return DAG.getBlockAddress(BA, VT);
1029 const VectorType *VecTy = cast<VectorType>(V->getType());
1030 unsigned NumElements = VecTy->getNumElements();
1032 // Now that we know the number and type of the elements, get that number of
1033 // elements into the Ops array based on what kind of constant it is.
1034 SmallVector<SDValue, 16> Ops;
1035 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1036 for (unsigned i = 0; i != NumElements; ++i)
1037 Ops.push_back(getValue(CP->getOperand(i)));
1039 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1040 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1043 if (EltVT.isFloatingPoint())
1044 Op = DAG.getConstantFP(0, EltVT);
1046 Op = DAG.getConstant(0, EltVT);
1047 Ops.assign(NumElements, Op);
1050 // Create a BUILD_VECTOR node.
1051 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1052 VT, &Ops[0], Ops.size());
1055 // If this is a static alloca, generate it as the frameindex instead of
1057 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1058 DenseMap<const AllocaInst*, int>::iterator SI =
1059 FuncInfo.StaticAllocaMap.find(AI);
1060 if (SI != FuncInfo.StaticAllocaMap.end())
1061 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1064 // If this is an instruction which fast-isel has deferred, select it now.
1065 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1066 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1067 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1068 SDValue Chain = DAG.getEntryNode();
1069 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1072 llvm_unreachable("Can't get register for value!");
1076 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1077 SDValue Chain = getControlRoot();
1078 SmallVector<ISD::OutputArg, 8> Outs;
1079 SmallVector<SDValue, 8> OutVals;
1081 if (!FuncInfo.CanLowerReturn) {
1082 unsigned DemoteReg = FuncInfo.DemoteRegister;
1083 const Function *F = I.getParent()->getParent();
1085 // Emit a store of the return value through the virtual register.
1086 // Leave Outs empty so that LowerReturn won't try to load return
1087 // registers the usual way.
1088 SmallVector<EVT, 1> PtrValueVTs;
1089 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1092 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1093 SDValue RetOp = getValue(I.getOperand(0));
1095 SmallVector<EVT, 4> ValueVTs;
1096 SmallVector<uint64_t, 4> Offsets;
1097 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1098 unsigned NumValues = ValueVTs.size();
1100 SmallVector<SDValue, 4> Chains(NumValues);
1101 for (unsigned i = 0; i != NumValues; ++i) {
1102 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1103 RetPtr.getValueType(), RetPtr,
1104 DAG.getIntPtrConstant(Offsets[i]));
1106 DAG.getStore(Chain, getCurDebugLoc(),
1107 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1108 // FIXME: better loc info would be nice.
1109 Add, MachinePointerInfo(), false, false, 0);
1112 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1113 MVT::Other, &Chains[0], NumValues);
1114 } else if (I.getNumOperands() != 0) {
1115 SmallVector<EVT, 4> ValueVTs;
1116 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1117 unsigned NumValues = ValueVTs.size();
1119 SDValue RetOp = getValue(I.getOperand(0));
1120 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1121 EVT VT = ValueVTs[j];
1123 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1125 const Function *F = I.getParent()->getParent();
1126 if (F->paramHasAttr(0, Attribute::SExt))
1127 ExtendKind = ISD::SIGN_EXTEND;
1128 else if (F->paramHasAttr(0, Attribute::ZExt))
1129 ExtendKind = ISD::ZERO_EXTEND;
1131 // FIXME: C calling convention requires the return type to be promoted
1132 // to at least 32-bit. But this is not necessary for non-C calling
1133 // conventions. The frontend should mark functions whose return values
1134 // require promoting with signext or zeroext attributes.
1135 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1136 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1137 if (VT.bitsLT(MinVT))
1141 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1142 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1143 SmallVector<SDValue, 4> Parts(NumParts);
1144 getCopyToParts(DAG, getCurDebugLoc(),
1145 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1146 &Parts[0], NumParts, PartVT, ExtendKind);
1148 // 'inreg' on function refers to return value
1149 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1150 if (F->paramHasAttr(0, Attribute::InReg))
1153 // Propagate extension type if any
1154 if (F->paramHasAttr(0, Attribute::SExt))
1156 else if (F->paramHasAttr(0, Attribute::ZExt))
1159 for (unsigned i = 0; i < NumParts; ++i) {
1160 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1162 OutVals.push_back(Parts[i]);
1168 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1169 CallingConv::ID CallConv =
1170 DAG.getMachineFunction().getFunction()->getCallingConv();
1171 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1172 Outs, OutVals, getCurDebugLoc(), DAG);
1174 // Verify that the target's LowerReturn behaved as expected.
1175 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1176 "LowerReturn didn't return a valid chain!");
1178 // Update the DAG with the new chain value resulting from return lowering.
1182 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1183 /// created for it, emit nodes to copy the value into the virtual
1185 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1186 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1187 if (VMI != FuncInfo.ValueMap.end()) {
1188 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1189 CopyValueToVirtualRegister(V, VMI->second);
1193 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1194 /// the current basic block, add it to ValueMap now so that we'll get a
1196 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1197 // No need to export constants.
1198 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1200 // Already exported?
1201 if (FuncInfo.isExportedInst(V)) return;
1203 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1204 CopyValueToVirtualRegister(V, Reg);
1207 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1208 const BasicBlock *FromBB) {
1209 // The operands of the setcc have to be in this block. We don't know
1210 // how to export them from some other block.
1211 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1212 // Can export from current BB.
1213 if (VI->getParent() == FromBB)
1216 // Is already exported, noop.
1217 return FuncInfo.isExportedInst(V);
1220 // If this is an argument, we can export it if the BB is the entry block or
1221 // if it is already exported.
1222 if (isa<Argument>(V)) {
1223 if (FromBB == &FromBB->getParent()->getEntryBlock())
1226 // Otherwise, can only export this if it is already exported.
1227 return FuncInfo.isExportedInst(V);
1230 // Otherwise, constants can always be exported.
1234 static bool InBlock(const Value *V, const BasicBlock *BB) {
1235 if (const Instruction *I = dyn_cast<Instruction>(V))
1236 return I->getParent() == BB;
1240 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1241 /// This function emits a branch and is used at the leaves of an OR or an
1242 /// AND operator tree.
1245 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1246 MachineBasicBlock *TBB,
1247 MachineBasicBlock *FBB,
1248 MachineBasicBlock *CurBB,
1249 MachineBasicBlock *SwitchBB) {
1250 const BasicBlock *BB = CurBB->getBasicBlock();
1252 // If the leaf of the tree is a comparison, merge the condition into
1254 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1255 // The operands of the cmp have to be in this block. We don't know
1256 // how to export them from some other block. If this is the first block
1257 // of the sequence, no exporting is needed.
1258 if (CurBB == SwitchBB ||
1259 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1260 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1261 ISD::CondCode Condition;
1262 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1263 Condition = getICmpCondCode(IC->getPredicate());
1264 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1265 Condition = getFCmpCondCode(FC->getPredicate());
1267 Condition = ISD::SETEQ; // silence warning.
1268 llvm_unreachable("Unknown compare instruction");
1271 CaseBlock CB(Condition, BOp->getOperand(0),
1272 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1273 SwitchCases.push_back(CB);
1278 // Create a CaseBlock record representing this branch.
1279 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1280 NULL, TBB, FBB, CurBB);
1281 SwitchCases.push_back(CB);
1284 /// FindMergedConditions - If Cond is an expression like
1285 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1286 MachineBasicBlock *TBB,
1287 MachineBasicBlock *FBB,
1288 MachineBasicBlock *CurBB,
1289 MachineBasicBlock *SwitchBB,
1291 // If this node is not part of the or/and tree, emit it as a branch.
1292 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1293 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1294 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1295 BOp->getParent() != CurBB->getBasicBlock() ||
1296 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1297 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1298 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1302 // Create TmpBB after CurBB.
1303 MachineFunction::iterator BBI = CurBB;
1304 MachineFunction &MF = DAG.getMachineFunction();
1305 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1306 CurBB->getParent()->insert(++BBI, TmpBB);
1308 if (Opc == Instruction::Or) {
1309 // Codegen X | Y as:
1317 // Emit the LHS condition.
1318 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1320 // Emit the RHS condition into TmpBB.
1321 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1323 assert(Opc == Instruction::And && "Unknown merge op!");
1324 // Codegen X & Y as:
1331 // This requires creation of TmpBB after CurBB.
1333 // Emit the LHS condition.
1334 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1336 // Emit the RHS condition into TmpBB.
1337 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1341 /// If the set of cases should be emitted as a series of branches, return true.
1342 /// If we should emit this as a bunch of and/or'd together conditions, return
1345 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1346 if (Cases.size() != 2) return true;
1348 // If this is two comparisons of the same values or'd or and'd together, they
1349 // will get folded into a single comparison, so don't emit two blocks.
1350 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1351 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1352 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1353 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1357 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1358 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1359 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1360 Cases[0].CC == Cases[1].CC &&
1361 isa<Constant>(Cases[0].CmpRHS) &&
1362 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1363 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1365 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1372 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1373 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1375 // Update machine-CFG edges.
1376 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1378 // Figure out which block is immediately after the current one.
1379 MachineBasicBlock *NextBlock = 0;
1380 MachineFunction::iterator BBI = BrMBB;
1381 if (++BBI != FuncInfo.MF->end())
1384 if (I.isUnconditional()) {
1385 // Update machine-CFG edges.
1386 BrMBB->addSuccessor(Succ0MBB);
1388 // If this is not a fall-through branch, emit the branch.
1389 if (Succ0MBB != NextBlock)
1390 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1391 MVT::Other, getControlRoot(),
1392 DAG.getBasicBlock(Succ0MBB)));
1397 // If this condition is one of the special cases we handle, do special stuff
1399 const Value *CondVal = I.getCondition();
1400 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1402 // If this is a series of conditions that are or'd or and'd together, emit
1403 // this as a sequence of branches instead of setcc's with and/or operations.
1404 // As long as jumps are not expensive, this should improve performance.
1405 // For example, instead of something like:
1418 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1419 if (!TLI.isJumpExpensive() &&
1421 (BOp->getOpcode() == Instruction::And ||
1422 BOp->getOpcode() == Instruction::Or)) {
1423 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1425 // If the compares in later blocks need to use values not currently
1426 // exported from this block, export them now. This block should always
1427 // be the first entry.
1428 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1430 // Allow some cases to be rejected.
1431 if (ShouldEmitAsBranches(SwitchCases)) {
1432 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1433 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1434 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1437 // Emit the branch for this block.
1438 visitSwitchCase(SwitchCases[0], BrMBB);
1439 SwitchCases.erase(SwitchCases.begin());
1443 // Okay, we decided not to do this, remove any inserted MBB's and clear
1445 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1446 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1448 SwitchCases.clear();
1452 // Create a CaseBlock record representing this branch.
1453 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1454 NULL, Succ0MBB, Succ1MBB, BrMBB);
1456 // Use visitSwitchCase to actually insert the fast branch sequence for this
1458 visitSwitchCase(CB, BrMBB);
1461 /// visitSwitchCase - Emits the necessary code to represent a single node in
1462 /// the binary search tree resulting from lowering a switch instruction.
1463 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1464 MachineBasicBlock *SwitchBB) {
1466 SDValue CondLHS = getValue(CB.CmpLHS);
1467 DebugLoc dl = getCurDebugLoc();
1469 // Build the setcc now.
1470 if (CB.CmpMHS == NULL) {
1471 // Fold "(X == true)" to X and "(X == false)" to !X to
1472 // handle common cases produced by branch lowering.
1473 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1474 CB.CC == ISD::SETEQ)
1476 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1477 CB.CC == ISD::SETEQ) {
1478 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1479 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1481 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1483 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1485 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1486 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1488 SDValue CmpOp = getValue(CB.CmpMHS);
1489 EVT VT = CmpOp.getValueType();
1491 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1492 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1495 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1496 VT, CmpOp, DAG.getConstant(Low, VT));
1497 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1498 DAG.getConstant(High-Low, VT), ISD::SETULE);
1502 // Update successor info
1503 SwitchBB->addSuccessor(CB.TrueBB);
1504 SwitchBB->addSuccessor(CB.FalseBB);
1506 // Set NextBlock to be the MBB immediately after the current one, if any.
1507 // This is used to avoid emitting unnecessary branches to the next block.
1508 MachineBasicBlock *NextBlock = 0;
1509 MachineFunction::iterator BBI = SwitchBB;
1510 if (++BBI != FuncInfo.MF->end())
1513 // If the lhs block is the next block, invert the condition so that we can
1514 // fall through to the lhs instead of the rhs block.
1515 if (CB.TrueBB == NextBlock) {
1516 std::swap(CB.TrueBB, CB.FalseBB);
1517 SDValue True = DAG.getConstant(1, Cond.getValueType());
1518 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1521 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1522 MVT::Other, getControlRoot(), Cond,
1523 DAG.getBasicBlock(CB.TrueBB));
1525 // Insert the false branch. Do this even if it's a fall through branch,
1526 // this makes it easier to do DAG optimizations which require inverting
1527 // the branch condition.
1528 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1529 DAG.getBasicBlock(CB.FalseBB));
1531 DAG.setRoot(BrCond);
1534 /// visitJumpTable - Emit JumpTable node in the current MBB
1535 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1536 // Emit the code for the jump table
1537 assert(JT.Reg != -1U && "Should lower JT Header first!");
1538 EVT PTy = TLI.getPointerTy();
1539 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1541 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1542 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1543 MVT::Other, Index.getValue(1),
1545 DAG.setRoot(BrJumpTable);
1548 /// visitJumpTableHeader - This function emits necessary code to produce index
1549 /// in the JumpTable from switch case.
1550 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1551 JumpTableHeader &JTH,
1552 MachineBasicBlock *SwitchBB) {
1553 // Subtract the lowest switch case value from the value being switched on and
1554 // conditional branch to default mbb if the result is greater than the
1555 // difference between smallest and largest cases.
1556 SDValue SwitchOp = getValue(JTH.SValue);
1557 EVT VT = SwitchOp.getValueType();
1558 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1559 DAG.getConstant(JTH.First, VT));
1561 // The SDNode we just created, which holds the value being switched on minus
1562 // the smallest case value, needs to be copied to a virtual register so it
1563 // can be used as an index into the jump table in a subsequent basic block.
1564 // This value may be smaller or larger than the target's pointer type, and
1565 // therefore require extension or truncating.
1566 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1568 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1569 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1570 JumpTableReg, SwitchOp);
1571 JT.Reg = JumpTableReg;
1573 // Emit the range check for the jump table, and branch to the default block
1574 // for the switch statement if the value being switched on exceeds the largest
1575 // case in the switch.
1576 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1577 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1578 DAG.getConstant(JTH.Last-JTH.First,VT),
1581 // Set NextBlock to be the MBB immediately after the current one, if any.
1582 // This is used to avoid emitting unnecessary branches to the next block.
1583 MachineBasicBlock *NextBlock = 0;
1584 MachineFunction::iterator BBI = SwitchBB;
1586 if (++BBI != FuncInfo.MF->end())
1589 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1590 MVT::Other, CopyTo, CMP,
1591 DAG.getBasicBlock(JT.Default));
1593 if (JT.MBB != NextBlock)
1594 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1595 DAG.getBasicBlock(JT.MBB));
1597 DAG.setRoot(BrCond);
1600 /// visitBitTestHeader - This function emits necessary code to produce value
1601 /// suitable for "bit tests"
1602 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1603 MachineBasicBlock *SwitchBB) {
1604 // Subtract the minimum value
1605 SDValue SwitchOp = getValue(B.SValue);
1606 EVT VT = SwitchOp.getValueType();
1607 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1608 DAG.getConstant(B.First, VT));
1611 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1612 TLI.getSetCCResultType(Sub.getValueType()),
1613 Sub, DAG.getConstant(B.Range, VT),
1616 // Determine the type of the test operands.
1617 bool UsePtrType = false;
1618 if (!TLI.isTypeLegal(VT))
1621 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1622 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1623 // Switch table case range are encoded into series of masks.
1624 // Just use pointer type, it's guaranteed to fit.
1630 VT = TLI.getPointerTy();
1631 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1635 B.Reg = FuncInfo.CreateReg(VT);
1636 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1639 // Set NextBlock to be the MBB immediately after the current one, if any.
1640 // This is used to avoid emitting unnecessary branches to the next block.
1641 MachineBasicBlock *NextBlock = 0;
1642 MachineFunction::iterator BBI = SwitchBB;
1643 if (++BBI != FuncInfo.MF->end())
1646 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1648 SwitchBB->addSuccessor(B.Default);
1649 SwitchBB->addSuccessor(MBB);
1651 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1652 MVT::Other, CopyTo, RangeCmp,
1653 DAG.getBasicBlock(B.Default));
1655 if (MBB != NextBlock)
1656 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1657 DAG.getBasicBlock(MBB));
1659 DAG.setRoot(BrRange);
1662 /// visitBitTestCase - this function produces one "bit test"
1663 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1664 MachineBasicBlock* NextMBB,
1667 MachineBasicBlock *SwitchBB) {
1669 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1672 if (CountPopulation_64(B.Mask) == 1) {
1673 // Testing for a single bit; just compare the shift count with what it
1674 // would need to be to shift a 1 bit in that position.
1675 Cmp = DAG.getSetCC(getCurDebugLoc(),
1676 TLI.getSetCCResultType(VT),
1678 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1681 // Make desired shift
1682 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1683 DAG.getConstant(1, VT), ShiftOp);
1685 // Emit bit tests and jumps
1686 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1687 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1688 Cmp = DAG.getSetCC(getCurDebugLoc(),
1689 TLI.getSetCCResultType(VT),
1690 AndOp, DAG.getConstant(0, VT),
1694 SwitchBB->addSuccessor(B.TargetBB);
1695 SwitchBB->addSuccessor(NextMBB);
1697 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1698 MVT::Other, getControlRoot(),
1699 Cmp, DAG.getBasicBlock(B.TargetBB));
1701 // Set NextBlock to be the MBB immediately after the current one, if any.
1702 // This is used to avoid emitting unnecessary branches to the next block.
1703 MachineBasicBlock *NextBlock = 0;
1704 MachineFunction::iterator BBI = SwitchBB;
1705 if (++BBI != FuncInfo.MF->end())
1708 if (NextMBB != NextBlock)
1709 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1710 DAG.getBasicBlock(NextMBB));
1715 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1716 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1718 // Retrieve successors.
1719 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1720 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1722 const Value *Callee(I.getCalledValue());
1723 if (isa<InlineAsm>(Callee))
1726 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1728 // If the value of the invoke is used outside of its defining block, make it
1729 // available as a virtual register.
1730 CopyToExportRegsIfNeeded(&I);
1732 // Update successor info
1733 InvokeMBB->addSuccessor(Return);
1734 InvokeMBB->addSuccessor(LandingPad);
1736 // Drop into normal successor.
1737 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1738 MVT::Other, getControlRoot(),
1739 DAG.getBasicBlock(Return)));
1742 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1745 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1746 /// small case ranges).
1747 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1748 CaseRecVector& WorkList,
1750 MachineBasicBlock *Default,
1751 MachineBasicBlock *SwitchBB) {
1752 Case& BackCase = *(CR.Range.second-1);
1754 // Size is the number of Cases represented by this range.
1755 size_t Size = CR.Range.second - CR.Range.first;
1759 // Get the MachineFunction which holds the current MBB. This is used when
1760 // inserting any additional MBBs necessary to represent the switch.
1761 MachineFunction *CurMF = FuncInfo.MF;
1763 // Figure out which block is immediately after the current one.
1764 MachineBasicBlock *NextBlock = 0;
1765 MachineFunction::iterator BBI = CR.CaseBB;
1767 if (++BBI != FuncInfo.MF->end())
1770 // If any two of the cases has the same destination, and if one value
1771 // is the same as the other, but has one bit unset that the other has set,
1772 // use bit manipulation to do two compares at once. For example:
1773 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1774 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1775 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1776 if (Size == 2 && CR.CaseBB == SwitchBB) {
1777 Case &Small = *CR.Range.first;
1778 Case &Big = *(CR.Range.second-1);
1780 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1781 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1782 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1784 // Check that there is only one bit different.
1785 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1786 (SmallValue | BigValue) == BigValue) {
1787 // Isolate the common bit.
1788 APInt CommonBit = BigValue & ~SmallValue;
1789 assert((SmallValue | CommonBit) == BigValue &&
1790 CommonBit.countPopulation() == 1 && "Not a common bit?");
1792 SDValue CondLHS = getValue(SV);
1793 EVT VT = CondLHS.getValueType();
1794 DebugLoc DL = getCurDebugLoc();
1796 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1797 DAG.getConstant(CommonBit, VT));
1798 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1799 Or, DAG.getConstant(BigValue, VT),
1802 // Update successor info.
1803 SwitchBB->addSuccessor(Small.BB);
1804 SwitchBB->addSuccessor(Default);
1806 // Insert the true branch.
1807 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1808 getControlRoot(), Cond,
1809 DAG.getBasicBlock(Small.BB));
1811 // Insert the false branch.
1812 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1813 DAG.getBasicBlock(Default));
1815 DAG.setRoot(BrCond);
1821 // Rearrange the case blocks so that the last one falls through if possible.
1822 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1823 // The last case block won't fall through into 'NextBlock' if we emit the
1824 // branches in this order. See if rearranging a case value would help.
1825 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1826 if (I->BB == NextBlock) {
1827 std::swap(*I, BackCase);
1833 // Create a CaseBlock record representing a conditional branch to
1834 // the Case's target mbb if the value being switched on SV is equal
1836 MachineBasicBlock *CurBlock = CR.CaseBB;
1837 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1838 MachineBasicBlock *FallThrough;
1840 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1841 CurMF->insert(BBI, FallThrough);
1843 // Put SV in a virtual register to make it available from the new blocks.
1844 ExportFromCurrentBlock(SV);
1846 // If the last case doesn't match, go to the default block.
1847 FallThrough = Default;
1850 const Value *RHS, *LHS, *MHS;
1852 if (I->High == I->Low) {
1853 // This is just small small case range :) containing exactly 1 case
1855 LHS = SV; RHS = I->High; MHS = NULL;
1858 LHS = I->Low; MHS = SV; RHS = I->High;
1860 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1862 // If emitting the first comparison, just call visitSwitchCase to emit the
1863 // code into the current block. Otherwise, push the CaseBlock onto the
1864 // vector to be later processed by SDISel, and insert the node's MBB
1865 // before the next MBB.
1866 if (CurBlock == SwitchBB)
1867 visitSwitchCase(CB, SwitchBB);
1869 SwitchCases.push_back(CB);
1871 CurBlock = FallThrough;
1877 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1878 return !DisableJumpTables &&
1879 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1880 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1883 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1884 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1885 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1886 return (LastExt - FirstExt + 1ULL);
1889 /// handleJTSwitchCase - Emit jumptable for current switch case range
1890 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1891 CaseRecVector& WorkList,
1893 MachineBasicBlock* Default,
1894 MachineBasicBlock *SwitchBB) {
1895 Case& FrontCase = *CR.Range.first;
1896 Case& BackCase = *(CR.Range.second-1);
1898 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1899 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1901 APInt TSize(First.getBitWidth(), 0);
1902 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1906 if (!areJTsAllowed(TLI) || TSize.ult(4))
1909 APInt Range = ComputeRange(First, Last);
1910 double Density = TSize.roundToDouble() / Range.roundToDouble();
1914 DEBUG(dbgs() << "Lowering jump table\n"
1915 << "First entry: " << First << ". Last entry: " << Last << '\n'
1916 << "Range: " << Range
1917 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
1919 // Get the MachineFunction which holds the current MBB. This is used when
1920 // inserting any additional MBBs necessary to represent the switch.
1921 MachineFunction *CurMF = FuncInfo.MF;
1923 // Figure out which block is immediately after the current one.
1924 MachineFunction::iterator BBI = CR.CaseBB;
1927 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1929 // Create a new basic block to hold the code for loading the address
1930 // of the jump table, and jumping to it. Update successor information;
1931 // we will either branch to the default case for the switch, or the jump
1933 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1934 CurMF->insert(BBI, JumpTableBB);
1935 CR.CaseBB->addSuccessor(Default);
1936 CR.CaseBB->addSuccessor(JumpTableBB);
1938 // Build a vector of destination BBs, corresponding to each target
1939 // of the jump table. If the value of the jump table slot corresponds to
1940 // a case statement, push the case's BB onto the vector, otherwise, push
1942 std::vector<MachineBasicBlock*> DestBBs;
1944 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1945 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1946 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1948 if (Low.sle(TEI) && TEI.sle(High)) {
1949 DestBBs.push_back(I->BB);
1953 DestBBs.push_back(Default);
1957 // Update successor info. Add one edge to each unique successor.
1958 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1959 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1960 E = DestBBs.end(); I != E; ++I) {
1961 if (!SuccsHandled[(*I)->getNumber()]) {
1962 SuccsHandled[(*I)->getNumber()] = true;
1963 JumpTableBB->addSuccessor(*I);
1967 // Create a jump table index for this jump table.
1968 unsigned JTEncoding = TLI.getJumpTableEncoding();
1969 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1970 ->createJumpTableIndex(DestBBs);
1972 // Set the jump table information so that we can codegen it as a second
1973 // MachineBasicBlock
1974 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1975 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1976 if (CR.CaseBB == SwitchBB)
1977 visitJumpTableHeader(JT, JTH, SwitchBB);
1979 JTCases.push_back(JumpTableBlock(JTH, JT));
1984 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1986 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1987 CaseRecVector& WorkList,
1989 MachineBasicBlock *Default,
1990 MachineBasicBlock *SwitchBB) {
1991 // Get the MachineFunction which holds the current MBB. This is used when
1992 // inserting any additional MBBs necessary to represent the switch.
1993 MachineFunction *CurMF = FuncInfo.MF;
1995 // Figure out which block is immediately after the current one.
1996 MachineFunction::iterator BBI = CR.CaseBB;
1999 Case& FrontCase = *CR.Range.first;
2000 Case& BackCase = *(CR.Range.second-1);
2001 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2003 // Size is the number of Cases represented by this range.
2004 unsigned Size = CR.Range.second - CR.Range.first;
2006 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2007 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2009 CaseItr Pivot = CR.Range.first + Size/2;
2011 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2012 // (heuristically) allow us to emit JumpTable's later.
2013 APInt TSize(First.getBitWidth(), 0);
2014 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2018 APInt LSize = FrontCase.size();
2019 APInt RSize = TSize-LSize;
2020 DEBUG(dbgs() << "Selecting best pivot: \n"
2021 << "First: " << First << ", Last: " << Last <<'\n'
2022 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2023 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2025 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2026 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2027 APInt Range = ComputeRange(LEnd, RBegin);
2028 assert((Range - 2ULL).isNonNegative() &&
2029 "Invalid case distance");
2030 double LDensity = (double)LSize.roundToDouble() /
2031 (LEnd - First + 1ULL).roundToDouble();
2032 double RDensity = (double)RSize.roundToDouble() /
2033 (Last - RBegin + 1ULL).roundToDouble();
2034 double Metric = Range.logBase2()*(LDensity+RDensity);
2035 // Should always split in some non-trivial place
2036 DEBUG(dbgs() <<"=>Step\n"
2037 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2038 << "LDensity: " << LDensity
2039 << ", RDensity: " << RDensity << '\n'
2040 << "Metric: " << Metric << '\n');
2041 if (FMetric < Metric) {
2044 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2050 if (areJTsAllowed(TLI)) {
2051 // If our case is dense we *really* should handle it earlier!
2052 assert((FMetric > 0) && "Should handle dense range earlier!");
2054 Pivot = CR.Range.first + Size/2;
2057 CaseRange LHSR(CR.Range.first, Pivot);
2058 CaseRange RHSR(Pivot, CR.Range.second);
2059 Constant *C = Pivot->Low;
2060 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2062 // We know that we branch to the LHS if the Value being switched on is
2063 // less than the Pivot value, C. We use this to optimize our binary
2064 // tree a bit, by recognizing that if SV is greater than or equal to the
2065 // LHS's Case Value, and that Case Value is exactly one less than the
2066 // Pivot's Value, then we can branch directly to the LHS's Target,
2067 // rather than creating a leaf node for it.
2068 if ((LHSR.second - LHSR.first) == 1 &&
2069 LHSR.first->High == CR.GE &&
2070 cast<ConstantInt>(C)->getValue() ==
2071 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2072 TrueBB = LHSR.first->BB;
2074 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2075 CurMF->insert(BBI, TrueBB);
2076 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2078 // Put SV in a virtual register to make it available from the new blocks.
2079 ExportFromCurrentBlock(SV);
2082 // Similar to the optimization above, if the Value being switched on is
2083 // known to be less than the Constant CR.LT, and the current Case Value
2084 // is CR.LT - 1, then we can branch directly to the target block for
2085 // the current Case Value, rather than emitting a RHS leaf node for it.
2086 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2087 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2088 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2089 FalseBB = RHSR.first->BB;
2091 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2092 CurMF->insert(BBI, FalseBB);
2093 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2095 // Put SV in a virtual register to make it available from the new blocks.
2096 ExportFromCurrentBlock(SV);
2099 // Create a CaseBlock record representing a conditional branch to
2100 // the LHS node if the value being switched on SV is less than C.
2101 // Otherwise, branch to LHS.
2102 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2104 if (CR.CaseBB == SwitchBB)
2105 visitSwitchCase(CB, SwitchBB);
2107 SwitchCases.push_back(CB);
2112 /// handleBitTestsSwitchCase - if current case range has few destination and
2113 /// range span less, than machine word bitwidth, encode case range into series
2114 /// of masks and emit bit tests with these masks.
2115 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2116 CaseRecVector& WorkList,
2118 MachineBasicBlock* Default,
2119 MachineBasicBlock *SwitchBB){
2120 EVT PTy = TLI.getPointerTy();
2121 unsigned IntPtrBits = PTy.getSizeInBits();
2123 Case& FrontCase = *CR.Range.first;
2124 Case& BackCase = *(CR.Range.second-1);
2126 // Get the MachineFunction which holds the current MBB. This is used when
2127 // inserting any additional MBBs necessary to represent the switch.
2128 MachineFunction *CurMF = FuncInfo.MF;
2130 // If target does not have legal shift left, do not emit bit tests at all.
2131 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2135 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2137 // Single case counts one, case range - two.
2138 numCmps += (I->Low == I->High ? 1 : 2);
2141 // Count unique destinations
2142 SmallSet<MachineBasicBlock*, 4> Dests;
2143 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2144 Dests.insert(I->BB);
2145 if (Dests.size() > 3)
2146 // Don't bother the code below, if there are too much unique destinations
2149 DEBUG(dbgs() << "Total number of unique destinations: "
2150 << Dests.size() << '\n'
2151 << "Total number of comparisons: " << numCmps << '\n');
2153 // Compute span of values.
2154 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2155 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2156 APInt cmpRange = maxValue - minValue;
2158 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2159 << "Low bound: " << minValue << '\n'
2160 << "High bound: " << maxValue << '\n');
2162 if (cmpRange.uge(IntPtrBits) ||
2163 (!(Dests.size() == 1 && numCmps >= 3) &&
2164 !(Dests.size() == 2 && numCmps >= 5) &&
2165 !(Dests.size() >= 3 && numCmps >= 6)))
2168 DEBUG(dbgs() << "Emitting bit tests\n");
2169 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2171 // Optimize the case where all the case values fit in a
2172 // word without having to subtract minValue. In this case,
2173 // we can optimize away the subtraction.
2174 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2175 cmpRange = maxValue;
2177 lowBound = minValue;
2180 CaseBitsVector CasesBits;
2181 unsigned i, count = 0;
2183 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2184 MachineBasicBlock* Dest = I->BB;
2185 for (i = 0; i < count; ++i)
2186 if (Dest == CasesBits[i].BB)
2190 assert((count < 3) && "Too much destinations to test!");
2191 CasesBits.push_back(CaseBits(0, Dest, 0));
2195 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2196 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2198 uint64_t lo = (lowValue - lowBound).getZExtValue();
2199 uint64_t hi = (highValue - lowBound).getZExtValue();
2201 for (uint64_t j = lo; j <= hi; j++) {
2202 CasesBits[i].Mask |= 1ULL << j;
2203 CasesBits[i].Bits++;
2207 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2211 // Figure out which block is immediately after the current one.
2212 MachineFunction::iterator BBI = CR.CaseBB;
2215 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2217 DEBUG(dbgs() << "Cases:\n");
2218 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2219 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2220 << ", Bits: " << CasesBits[i].Bits
2221 << ", BB: " << CasesBits[i].BB << '\n');
2223 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2224 CurMF->insert(BBI, CaseBB);
2225 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2229 // Put SV in a virtual register to make it available from the new blocks.
2230 ExportFromCurrentBlock(SV);
2233 BitTestBlock BTB(lowBound, cmpRange, SV,
2234 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2235 CR.CaseBB, Default, BTC);
2237 if (CR.CaseBB == SwitchBB)
2238 visitBitTestHeader(BTB, SwitchBB);
2240 BitTestCases.push_back(BTB);
2245 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2246 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2247 const SwitchInst& SI) {
2250 // Start with "simple" cases
2251 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2252 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2253 Cases.push_back(Case(SI.getSuccessorValue(i),
2254 SI.getSuccessorValue(i),
2257 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2259 // Merge case into clusters
2260 if (Cases.size() >= 2)
2261 // Must recompute end() each iteration because it may be
2262 // invalidated by erase if we hold on to it
2263 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2264 J != Cases.end(); ) {
2265 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2266 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2267 MachineBasicBlock* nextBB = J->BB;
2268 MachineBasicBlock* currentBB = I->BB;
2270 // If the two neighboring cases go to the same destination, merge them
2271 // into a single case.
2272 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2280 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2281 if (I->Low != I->High)
2282 // A range counts double, since it requires two compares.
2289 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2290 MachineBasicBlock *Last) {
2292 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2293 if (JTCases[i].first.HeaderBB == First)
2294 JTCases[i].first.HeaderBB = Last;
2296 // Update BitTestCases.
2297 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2298 if (BitTestCases[i].Parent == First)
2299 BitTestCases[i].Parent = Last;
2302 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2303 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2305 // Figure out which block is immediately after the current one.
2306 MachineBasicBlock *NextBlock = 0;
2307 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2309 // If there is only the default destination, branch to it if it is not the
2310 // next basic block. Otherwise, just fall through.
2311 if (SI.getNumOperands() == 2) {
2312 // Update machine-CFG edges.
2314 // If this is not a fall-through branch, emit the branch.
2315 SwitchMBB->addSuccessor(Default);
2316 if (Default != NextBlock)
2317 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2318 MVT::Other, getControlRoot(),
2319 DAG.getBasicBlock(Default)));
2324 // If there are any non-default case statements, create a vector of Cases
2325 // representing each one, and sort the vector so that we can efficiently
2326 // create a binary search tree from them.
2328 size_t numCmps = Clusterify(Cases, SI);
2329 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2330 << ". Total compares: " << numCmps << '\n');
2333 // Get the Value to be switched on and default basic blocks, which will be
2334 // inserted into CaseBlock records, representing basic blocks in the binary
2336 const Value *SV = SI.getOperand(0);
2338 // Push the initial CaseRec onto the worklist
2339 CaseRecVector WorkList;
2340 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2341 CaseRange(Cases.begin(),Cases.end())));
2343 while (!WorkList.empty()) {
2344 // Grab a record representing a case range to process off the worklist
2345 CaseRec CR = WorkList.back();
2346 WorkList.pop_back();
2348 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2351 // If the range has few cases (two or less) emit a series of specific
2353 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2356 // If the switch has more than 5 blocks, and at least 40% dense, and the
2357 // target supports indirect branches, then emit a jump table rather than
2358 // lowering the switch to a binary tree of conditional branches.
2359 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2362 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2363 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2364 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2368 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2369 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2371 // Update machine-CFG edges with unique successors.
2372 SmallVector<BasicBlock*, 32> succs;
2373 succs.reserve(I.getNumSuccessors());
2374 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2375 succs.push_back(I.getSuccessor(i));
2376 array_pod_sort(succs.begin(), succs.end());
2377 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2378 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2379 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2381 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2382 MVT::Other, getControlRoot(),
2383 getValue(I.getAddress())));
2386 void SelectionDAGBuilder::visitFSub(const User &I) {
2387 // -0.0 - X --> fneg
2388 const Type *Ty = I.getType();
2389 if (isa<Constant>(I.getOperand(0)) &&
2390 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2391 SDValue Op2 = getValue(I.getOperand(1));
2392 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2393 Op2.getValueType(), Op2));
2397 visitBinary(I, ISD::FSUB);
2400 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2401 SDValue Op1 = getValue(I.getOperand(0));
2402 SDValue Op2 = getValue(I.getOperand(1));
2403 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2404 Op1.getValueType(), Op1, Op2));
2407 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2408 SDValue Op1 = getValue(I.getOperand(0));
2409 SDValue Op2 = getValue(I.getOperand(1));
2411 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2413 // Coerce the shift amount to the right type if we can.
2414 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2415 unsigned ShiftSize = ShiftTy.getSizeInBits();
2416 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2417 DebugLoc DL = getCurDebugLoc();
2419 // If the operand is smaller than the shift count type, promote it.
2420 if (ShiftSize > Op2Size)
2421 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2423 // If the operand is larger than the shift count type but the shift
2424 // count type has enough bits to represent any shift value, truncate
2425 // it now. This is a common case and it exposes the truncate to
2426 // optimization early.
2427 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2428 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2429 // Otherwise we'll need to temporarily settle for some other convenient
2430 // type. Type legalization will make adjustments once the shiftee is split.
2432 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2435 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2436 Op1.getValueType(), Op1, Op2));
2439 void SelectionDAGBuilder::visitICmp(const User &I) {
2440 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2441 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2442 predicate = IC->getPredicate();
2443 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2444 predicate = ICmpInst::Predicate(IC->getPredicate());
2445 SDValue Op1 = getValue(I.getOperand(0));
2446 SDValue Op2 = getValue(I.getOperand(1));
2447 ISD::CondCode Opcode = getICmpCondCode(predicate);
2449 EVT DestVT = TLI.getValueType(I.getType());
2450 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2453 void SelectionDAGBuilder::visitFCmp(const User &I) {
2454 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2455 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2456 predicate = FC->getPredicate();
2457 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2458 predicate = FCmpInst::Predicate(FC->getPredicate());
2459 SDValue Op1 = getValue(I.getOperand(0));
2460 SDValue Op2 = getValue(I.getOperand(1));
2461 ISD::CondCode Condition = getFCmpCondCode(predicate);
2462 EVT DestVT = TLI.getValueType(I.getType());
2463 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2466 void SelectionDAGBuilder::visitSelect(const User &I) {
2467 SmallVector<EVT, 4> ValueVTs;
2468 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2469 unsigned NumValues = ValueVTs.size();
2470 if (NumValues == 0) return;
2472 SmallVector<SDValue, 4> Values(NumValues);
2473 SDValue Cond = getValue(I.getOperand(0));
2474 SDValue TrueVal = getValue(I.getOperand(1));
2475 SDValue FalseVal = getValue(I.getOperand(2));
2477 for (unsigned i = 0; i != NumValues; ++i)
2478 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2479 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2481 SDValue(TrueVal.getNode(),
2482 TrueVal.getResNo() + i),
2483 SDValue(FalseVal.getNode(),
2484 FalseVal.getResNo() + i));
2486 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2487 DAG.getVTList(&ValueVTs[0], NumValues),
2488 &Values[0], NumValues));
2491 void SelectionDAGBuilder::visitTrunc(const User &I) {
2492 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2493 SDValue N = getValue(I.getOperand(0));
2494 EVT DestVT = TLI.getValueType(I.getType());
2495 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2498 void SelectionDAGBuilder::visitZExt(const User &I) {
2499 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2500 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2501 SDValue N = getValue(I.getOperand(0));
2502 EVT DestVT = TLI.getValueType(I.getType());
2503 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2506 void SelectionDAGBuilder::visitSExt(const User &I) {
2507 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2508 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2509 SDValue N = getValue(I.getOperand(0));
2510 EVT DestVT = TLI.getValueType(I.getType());
2511 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2514 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2515 // FPTrunc is never a no-op cast, no need to check
2516 SDValue N = getValue(I.getOperand(0));
2517 EVT DestVT = TLI.getValueType(I.getType());
2518 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2519 DestVT, N, DAG.getIntPtrConstant(0)));
2522 void SelectionDAGBuilder::visitFPExt(const User &I){
2523 // FPTrunc is never a no-op cast, no need to check
2524 SDValue N = getValue(I.getOperand(0));
2525 EVT DestVT = TLI.getValueType(I.getType());
2526 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2529 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2530 // FPToUI is never a no-op cast, no need to check
2531 SDValue N = getValue(I.getOperand(0));
2532 EVT DestVT = TLI.getValueType(I.getType());
2533 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2536 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2537 // FPToSI is never a no-op cast, no need to check
2538 SDValue N = getValue(I.getOperand(0));
2539 EVT DestVT = TLI.getValueType(I.getType());
2540 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2543 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2544 // UIToFP is never a no-op cast, no need to check
2545 SDValue N = getValue(I.getOperand(0));
2546 EVT DestVT = TLI.getValueType(I.getType());
2547 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2550 void SelectionDAGBuilder::visitSIToFP(const User &I){
2551 // SIToFP is never a no-op cast, no need to check
2552 SDValue N = getValue(I.getOperand(0));
2553 EVT DestVT = TLI.getValueType(I.getType());
2554 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2557 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2558 // What to do depends on the size of the integer and the size of the pointer.
2559 // We can either truncate, zero extend, or no-op, accordingly.
2560 SDValue N = getValue(I.getOperand(0));
2561 EVT DestVT = TLI.getValueType(I.getType());
2562 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2565 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2566 // What to do depends on the size of the integer and the size of the pointer.
2567 // We can either truncate, zero extend, or no-op, accordingly.
2568 SDValue N = getValue(I.getOperand(0));
2569 EVT DestVT = TLI.getValueType(I.getType());
2570 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2573 void SelectionDAGBuilder::visitBitCast(const User &I) {
2574 SDValue N = getValue(I.getOperand(0));
2575 EVT DestVT = TLI.getValueType(I.getType());
2577 // BitCast assures us that source and destination are the same size so this is
2578 // either a BITCAST or a no-op.
2579 if (DestVT != N.getValueType())
2580 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2581 DestVT, N)); // convert types.
2583 setValue(&I, N); // noop cast.
2586 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2587 SDValue InVec = getValue(I.getOperand(0));
2588 SDValue InVal = getValue(I.getOperand(1));
2589 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2591 getValue(I.getOperand(2)));
2592 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2593 TLI.getValueType(I.getType()),
2594 InVec, InVal, InIdx));
2597 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2598 SDValue InVec = getValue(I.getOperand(0));
2599 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2601 getValue(I.getOperand(1)));
2602 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2603 TLI.getValueType(I.getType()), InVec, InIdx));
2606 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2607 // from SIndx and increasing to the element length (undefs are allowed).
2608 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2609 unsigned MaskNumElts = Mask.size();
2610 for (unsigned i = 0; i != MaskNumElts; ++i)
2611 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2616 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2617 SmallVector<int, 8> Mask;
2618 SDValue Src1 = getValue(I.getOperand(0));
2619 SDValue Src2 = getValue(I.getOperand(1));
2621 // Convert the ConstantVector mask operand into an array of ints, with -1
2622 // representing undef values.
2623 SmallVector<Constant*, 8> MaskElts;
2624 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2625 unsigned MaskNumElts = MaskElts.size();
2626 for (unsigned i = 0; i != MaskNumElts; ++i) {
2627 if (isa<UndefValue>(MaskElts[i]))
2630 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2633 EVT VT = TLI.getValueType(I.getType());
2634 EVT SrcVT = Src1.getValueType();
2635 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2637 if (SrcNumElts == MaskNumElts) {
2638 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2643 // Normalize the shuffle vector since mask and vector length don't match.
2644 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2645 // Mask is longer than the source vectors and is a multiple of the source
2646 // vectors. We can use concatenate vector to make the mask and vectors
2648 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2649 // The shuffle is concatenating two vectors together.
2650 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2655 // Pad both vectors with undefs to make them the same length as the mask.
2656 unsigned NumConcat = MaskNumElts / SrcNumElts;
2657 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2658 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2659 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2661 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2662 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2666 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2667 getCurDebugLoc(), VT,
2668 &MOps1[0], NumConcat);
2669 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2670 getCurDebugLoc(), VT,
2671 &MOps2[0], NumConcat);
2673 // Readjust mask for new input vector length.
2674 SmallVector<int, 8> MappedOps;
2675 for (unsigned i = 0; i != MaskNumElts; ++i) {
2677 if (Idx < (int)SrcNumElts)
2678 MappedOps.push_back(Idx);
2680 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2683 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2688 if (SrcNumElts > MaskNumElts) {
2689 // Analyze the access pattern of the vector to see if we can extract
2690 // two subvectors and do the shuffle. The analysis is done by calculating
2691 // the range of elements the mask access on both vectors.
2692 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2693 int MaxRange[2] = {-1, -1};
2695 for (unsigned i = 0; i != MaskNumElts; ++i) {
2701 if (Idx >= (int)SrcNumElts) {
2705 if (Idx > MaxRange[Input])
2706 MaxRange[Input] = Idx;
2707 if (Idx < MinRange[Input])
2708 MinRange[Input] = Idx;
2711 // Check if the access is smaller than the vector size and can we find
2712 // a reasonable extract index.
2713 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2715 int StartIdx[2]; // StartIdx to extract from
2716 for (int Input=0; Input < 2; ++Input) {
2717 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2718 RangeUse[Input] = 0; // Unused
2719 StartIdx[Input] = 0;
2720 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2721 // Fits within range but we should see if we can find a good
2722 // start index that is a multiple of the mask length.
2723 if (MaxRange[Input] < (int)MaskNumElts) {
2724 RangeUse[Input] = 1; // Extract from beginning of the vector
2725 StartIdx[Input] = 0;
2727 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2728 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2729 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2730 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2735 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2736 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2739 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2740 // Extract appropriate subvector and generate a vector shuffle
2741 for (int Input=0; Input < 2; ++Input) {
2742 SDValue &Src = Input == 0 ? Src1 : Src2;
2743 if (RangeUse[Input] == 0)
2744 Src = DAG.getUNDEF(VT);
2746 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2747 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2750 // Calculate new mask.
2751 SmallVector<int, 8> MappedOps;
2752 for (unsigned i = 0; i != MaskNumElts; ++i) {
2755 MappedOps.push_back(Idx);
2756 else if (Idx < (int)SrcNumElts)
2757 MappedOps.push_back(Idx - StartIdx[0]);
2759 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2762 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2768 // We can't use either concat vectors or extract subvectors so fall back to
2769 // replacing the shuffle with extract and build vector.
2770 // to insert and build vector.
2771 EVT EltVT = VT.getVectorElementType();
2772 EVT PtrVT = TLI.getPointerTy();
2773 SmallVector<SDValue,8> Ops;
2774 for (unsigned i = 0; i != MaskNumElts; ++i) {
2776 Ops.push_back(DAG.getUNDEF(EltVT));
2781 if (Idx < (int)SrcNumElts)
2782 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2783 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2785 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2787 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2793 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2794 VT, &Ops[0], Ops.size()));
2797 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2798 const Value *Op0 = I.getOperand(0);
2799 const Value *Op1 = I.getOperand(1);
2800 const Type *AggTy = I.getType();
2801 const Type *ValTy = Op1->getType();
2802 bool IntoUndef = isa<UndefValue>(Op0);
2803 bool FromUndef = isa<UndefValue>(Op1);
2805 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2807 SmallVector<EVT, 4> AggValueVTs;
2808 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2809 SmallVector<EVT, 4> ValValueVTs;
2810 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2812 unsigned NumAggValues = AggValueVTs.size();
2813 unsigned NumValValues = ValValueVTs.size();
2814 SmallVector<SDValue, 4> Values(NumAggValues);
2816 SDValue Agg = getValue(Op0);
2817 SDValue Val = getValue(Op1);
2819 // Copy the beginning value(s) from the original aggregate.
2820 for (; i != LinearIndex; ++i)
2821 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2822 SDValue(Agg.getNode(), Agg.getResNo() + i);
2823 // Copy values from the inserted value(s).
2824 for (; i != LinearIndex + NumValValues; ++i)
2825 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2826 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2827 // Copy remaining value(s) from the original aggregate.
2828 for (; i != NumAggValues; ++i)
2829 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2830 SDValue(Agg.getNode(), Agg.getResNo() + i);
2832 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2833 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2834 &Values[0], NumAggValues));
2837 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2838 const Value *Op0 = I.getOperand(0);
2839 const Type *AggTy = Op0->getType();
2840 const Type *ValTy = I.getType();
2841 bool OutOfUndef = isa<UndefValue>(Op0);
2843 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2845 SmallVector<EVT, 4> ValValueVTs;
2846 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2848 unsigned NumValValues = ValValueVTs.size();
2849 SmallVector<SDValue, 4> Values(NumValValues);
2851 SDValue Agg = getValue(Op0);
2852 // Copy out the selected value(s).
2853 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2854 Values[i - LinearIndex] =
2856 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2857 SDValue(Agg.getNode(), Agg.getResNo() + i);
2859 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2860 DAG.getVTList(&ValValueVTs[0], NumValValues),
2861 &Values[0], NumValValues));
2864 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2865 SDValue N = getValue(I.getOperand(0));
2866 const Type *Ty = I.getOperand(0)->getType();
2868 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2870 const Value *Idx = *OI;
2871 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2872 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2875 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2876 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2877 DAG.getIntPtrConstant(Offset));
2880 Ty = StTy->getElementType(Field);
2882 Ty = cast<SequentialType>(Ty)->getElementType();
2884 // If this is a constant subscript, handle it quickly.
2885 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2886 if (CI->isZero()) continue;
2888 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2890 EVT PTy = TLI.getPointerTy();
2891 unsigned PtrBits = PTy.getSizeInBits();
2893 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2895 DAG.getConstant(Offs, MVT::i64));
2897 OffsVal = DAG.getIntPtrConstant(Offs);
2899 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2904 // N = N + Idx * ElementSize;
2905 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2906 TD->getTypeAllocSize(Ty));
2907 SDValue IdxN = getValue(Idx);
2909 // If the index is smaller or larger than intptr_t, truncate or extend
2911 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2913 // If this is a multiply by a power of two, turn it into a shl
2914 // immediately. This is a very common case.
2915 if (ElementSize != 1) {
2916 if (ElementSize.isPowerOf2()) {
2917 unsigned Amt = ElementSize.logBase2();
2918 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2919 N.getValueType(), IdxN,
2920 DAG.getConstant(Amt, TLI.getPointerTy()));
2922 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2923 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2924 N.getValueType(), IdxN, Scale);
2928 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2929 N.getValueType(), N, IdxN);
2936 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2937 // If this is a fixed sized alloca in the entry block of the function,
2938 // allocate it statically on the stack.
2939 if (FuncInfo.StaticAllocaMap.count(&I))
2940 return; // getValue will auto-populate this.
2942 const Type *Ty = I.getAllocatedType();
2943 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2945 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2948 SDValue AllocSize = getValue(I.getArraySize());
2950 EVT IntPtr = TLI.getPointerTy();
2951 if (AllocSize.getValueType() != IntPtr)
2952 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2954 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2956 DAG.getConstant(TySize, IntPtr));
2958 // Handle alignment. If the requested alignment is less than or equal to
2959 // the stack alignment, ignore it. If the size is greater than or equal to
2960 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2961 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
2962 if (Align <= StackAlign)
2965 // Round the size of the allocation up to the stack alignment size
2966 // by add SA-1 to the size.
2967 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2968 AllocSize.getValueType(), AllocSize,
2969 DAG.getIntPtrConstant(StackAlign-1));
2971 // Mask out the low bits for alignment purposes.
2972 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2973 AllocSize.getValueType(), AllocSize,
2974 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2976 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2977 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2978 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2981 DAG.setRoot(DSA.getValue(1));
2983 // Inform the Frame Information that we have just allocated a variable-sized
2985 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2988 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2989 const Value *SV = I.getOperand(0);
2990 SDValue Ptr = getValue(SV);
2992 const Type *Ty = I.getType();
2994 bool isVolatile = I.isVolatile();
2995 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2996 unsigned Alignment = I.getAlignment();
2997 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
2999 SmallVector<EVT, 4> ValueVTs;
3000 SmallVector<uint64_t, 4> Offsets;
3001 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3002 unsigned NumValues = ValueVTs.size();
3007 bool ConstantMemory = false;
3008 if (I.isVolatile() || NumValues > MaxParallelChains)
3009 // Serialize volatile loads with other side effects.
3011 else if (AA->pointsToConstantMemory(
3012 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3013 // Do not serialize (non-volatile) loads of constant memory with anything.
3014 Root = DAG.getEntryNode();
3015 ConstantMemory = true;
3017 // Do not serialize non-volatile loads against each other.
3018 Root = DAG.getRoot();
3021 SmallVector<SDValue, 4> Values(NumValues);
3022 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3024 EVT PtrVT = Ptr.getValueType();
3025 unsigned ChainI = 0;
3026 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3027 // Serializing loads here may result in excessive register pressure, and
3028 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3029 // could recover a bit by hoisting nodes upward in the chain by recognizing
3030 // they are side-effect free or do not alias. The optimizer should really
3031 // avoid this case by converting large object/array copies to llvm.memcpy
3032 // (MaxParallelChains should always remain as failsafe).
3033 if (ChainI == MaxParallelChains) {
3034 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3035 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3036 MVT::Other, &Chains[0], ChainI);
3040 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3042 DAG.getConstant(Offsets[i], PtrVT));
3043 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3044 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3045 isNonTemporal, Alignment, TBAAInfo);
3048 Chains[ChainI] = L.getValue(1);
3051 if (!ConstantMemory) {
3052 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3053 MVT::Other, &Chains[0], ChainI);
3057 PendingLoads.push_back(Chain);
3060 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3061 DAG.getVTList(&ValueVTs[0], NumValues),
3062 &Values[0], NumValues));
3065 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3066 const Value *SrcV = I.getOperand(0);
3067 const Value *PtrV = I.getOperand(1);
3069 SmallVector<EVT, 4> ValueVTs;
3070 SmallVector<uint64_t, 4> Offsets;
3071 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3072 unsigned NumValues = ValueVTs.size();
3076 // Get the lowered operands. Note that we do this after
3077 // checking if NumResults is zero, because with zero results
3078 // the operands won't have values in the map.
3079 SDValue Src = getValue(SrcV);
3080 SDValue Ptr = getValue(PtrV);
3082 SDValue Root = getRoot();
3083 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3085 EVT PtrVT = Ptr.getValueType();
3086 bool isVolatile = I.isVolatile();
3087 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3088 unsigned Alignment = I.getAlignment();
3089 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3091 unsigned ChainI = 0;
3092 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3093 // See visitLoad comments.
3094 if (ChainI == MaxParallelChains) {
3095 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3096 MVT::Other, &Chains[0], ChainI);
3100 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3101 DAG.getConstant(Offsets[i], PtrVT));
3102 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3103 SDValue(Src.getNode(), Src.getResNo() + i),
3104 Add, MachinePointerInfo(PtrV, Offsets[i]),
3105 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3106 Chains[ChainI] = St;
3109 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3110 MVT::Other, &Chains[0], ChainI);
3112 AssignOrderingToNode(StoreNode.getNode());
3113 DAG.setRoot(StoreNode);
3116 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3118 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3119 unsigned Intrinsic) {
3120 bool HasChain = !I.doesNotAccessMemory();
3121 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3123 // Build the operand list.
3124 SmallVector<SDValue, 8> Ops;
3125 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3127 // We don't need to serialize loads against other loads.
3128 Ops.push_back(DAG.getRoot());
3130 Ops.push_back(getRoot());
3134 // Info is set by getTgtMemInstrinsic
3135 TargetLowering::IntrinsicInfo Info;
3136 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3138 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3139 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3140 Info.opc == ISD::INTRINSIC_W_CHAIN)
3141 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3143 // Add all operands of the call to the operand list.
3144 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3145 SDValue Op = getValue(I.getArgOperand(i));
3146 assert(TLI.isTypeLegal(Op.getValueType()) &&
3147 "Intrinsic uses a non-legal type?");
3151 SmallVector<EVT, 4> ValueVTs;
3152 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3154 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3155 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3156 "Intrinsic uses a non-legal type?");
3161 ValueVTs.push_back(MVT::Other);
3163 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3167 if (IsTgtIntrinsic) {
3168 // This is target intrinsic that touches memory
3169 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3170 VTs, &Ops[0], Ops.size(),
3172 MachinePointerInfo(Info.ptrVal, Info.offset),
3173 Info.align, Info.vol,
3174 Info.readMem, Info.writeMem);
3175 } else if (!HasChain) {
3176 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3177 VTs, &Ops[0], Ops.size());
3178 } else if (!I.getType()->isVoidTy()) {
3179 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3180 VTs, &Ops[0], Ops.size());
3182 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3183 VTs, &Ops[0], Ops.size());
3187 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3189 PendingLoads.push_back(Chain);
3194 if (!I.getType()->isVoidTy()) {
3195 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3196 EVT VT = TLI.getValueType(PTy);
3197 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3200 setValue(&I, Result);
3204 /// GetSignificand - Get the significand and build it into a floating-point
3205 /// number with exponent of 1:
3207 /// Op = (Op & 0x007fffff) | 0x3f800000;
3209 /// where Op is the hexidecimal representation of floating point value.
3211 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3212 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3213 DAG.getConstant(0x007fffff, MVT::i32));
3214 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3215 DAG.getConstant(0x3f800000, MVT::i32));
3216 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3219 /// GetExponent - Get the exponent:
3221 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3223 /// where Op is the hexidecimal representation of floating point value.
3225 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3227 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3228 DAG.getConstant(0x7f800000, MVT::i32));
3229 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3230 DAG.getConstant(23, TLI.getPointerTy()));
3231 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3232 DAG.getConstant(127, MVT::i32));
3233 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3236 /// getF32Constant - Get 32-bit floating point constant.
3238 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3239 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3242 /// Inlined utility function to implement binary input atomic intrinsics for
3243 /// visitIntrinsicCall: I is a call instruction
3244 /// Op is the associated NodeType for I
3246 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3248 SDValue Root = getRoot();
3250 DAG.getAtomic(Op, getCurDebugLoc(),
3251 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3253 getValue(I.getArgOperand(0)),
3254 getValue(I.getArgOperand(1)),
3255 I.getArgOperand(0));
3257 DAG.setRoot(L.getValue(1));
3261 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3263 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3264 SDValue Op1 = getValue(I.getArgOperand(0));
3265 SDValue Op2 = getValue(I.getArgOperand(1));
3267 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3268 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3272 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3273 /// limited-precision mode.
3275 SelectionDAGBuilder::visitExp(const CallInst &I) {
3277 DebugLoc dl = getCurDebugLoc();
3279 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3280 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3281 SDValue Op = getValue(I.getArgOperand(0));
3283 // Put the exponent in the right bit position for later addition to the
3286 // #define LOG2OFe 1.4426950f
3287 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3288 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3289 getF32Constant(DAG, 0x3fb8aa3b));
3290 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3292 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3293 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3294 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3296 // IntegerPartOfX <<= 23;
3297 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3298 DAG.getConstant(23, TLI.getPointerTy()));
3300 if (LimitFloatPrecision <= 6) {
3301 // For floating-point precision of 6:
3303 // TwoToFractionalPartOfX =
3305 // (0.735607626f + 0.252464424f * x) * x;
3307 // error 0.0144103317, which is 6 bits
3308 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3309 getF32Constant(DAG, 0x3e814304));
3310 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3311 getF32Constant(DAG, 0x3f3c50c8));
3312 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3313 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3314 getF32Constant(DAG, 0x3f7f5e7e));
3315 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3317 // Add the exponent into the result in integer domain.
3318 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3319 TwoToFracPartOfX, IntegerPartOfX);
3321 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3322 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3323 // For floating-point precision of 12:
3325 // TwoToFractionalPartOfX =
3328 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3330 // 0.000107046256 error, which is 13 to 14 bits
3331 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3332 getF32Constant(DAG, 0x3da235e3));
3333 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3334 getF32Constant(DAG, 0x3e65b8f3));
3335 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3336 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3337 getF32Constant(DAG, 0x3f324b07));
3338 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3339 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3340 getF32Constant(DAG, 0x3f7ff8fd));
3341 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3343 // Add the exponent into the result in integer domain.
3344 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3345 TwoToFracPartOfX, IntegerPartOfX);
3347 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3348 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3349 // For floating-point precision of 18:
3351 // TwoToFractionalPartOfX =
3355 // (0.554906021e-1f +
3356 // (0.961591928e-2f +
3357 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3359 // error 2.47208000*10^(-7), which is better than 18 bits
3360 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3361 getF32Constant(DAG, 0x3924b03e));
3362 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3363 getF32Constant(DAG, 0x3ab24b87));
3364 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3365 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3366 getF32Constant(DAG, 0x3c1d8c17));
3367 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3368 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3369 getF32Constant(DAG, 0x3d634a1d));
3370 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3371 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3372 getF32Constant(DAG, 0x3e75fe14));
3373 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3374 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3375 getF32Constant(DAG, 0x3f317234));
3376 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3377 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3378 getF32Constant(DAG, 0x3f800000));
3379 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3382 // Add the exponent into the result in integer domain.
3383 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3384 TwoToFracPartOfX, IntegerPartOfX);
3386 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3389 // No special expansion.
3390 result = DAG.getNode(ISD::FEXP, dl,
3391 getValue(I.getArgOperand(0)).getValueType(),
3392 getValue(I.getArgOperand(0)));
3395 setValue(&I, result);
3398 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3399 /// limited-precision mode.
3401 SelectionDAGBuilder::visitLog(const CallInst &I) {
3403 DebugLoc dl = getCurDebugLoc();
3405 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3406 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3407 SDValue Op = getValue(I.getArgOperand(0));
3408 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3410 // Scale the exponent by log(2) [0.69314718f].
3411 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3412 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3413 getF32Constant(DAG, 0x3f317218));
3415 // Get the significand and build it into a floating-point number with
3417 SDValue X = GetSignificand(DAG, Op1, dl);
3419 if (LimitFloatPrecision <= 6) {
3420 // For floating-point precision of 6:
3424 // (1.4034025f - 0.23903021f * x) * x;
3426 // error 0.0034276066, which is better than 8 bits
3427 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3428 getF32Constant(DAG, 0xbe74c456));
3429 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3430 getF32Constant(DAG, 0x3fb3a2b1));
3431 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3432 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3433 getF32Constant(DAG, 0x3f949a29));
3435 result = DAG.getNode(ISD::FADD, dl,
3436 MVT::f32, LogOfExponent, LogOfMantissa);
3437 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3438 // For floating-point precision of 12:
3444 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3446 // error 0.000061011436, which is 14 bits
3447 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3448 getF32Constant(DAG, 0xbd67b6d6));
3449 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3450 getF32Constant(DAG, 0x3ee4f4b8));
3451 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3452 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3453 getF32Constant(DAG, 0x3fbc278b));
3454 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3455 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3456 getF32Constant(DAG, 0x40348e95));
3457 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3458 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3459 getF32Constant(DAG, 0x3fdef31a));
3461 result = DAG.getNode(ISD::FADD, dl,
3462 MVT::f32, LogOfExponent, LogOfMantissa);
3463 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3464 // For floating-point precision of 18:
3472 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3474 // error 0.0000023660568, which is better than 18 bits
3475 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3476 getF32Constant(DAG, 0xbc91e5ac));
3477 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3478 getF32Constant(DAG, 0x3e4350aa));
3479 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3480 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3481 getF32Constant(DAG, 0x3f60d3e3));
3482 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3483 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3484 getF32Constant(DAG, 0x4011cdf0));
3485 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3486 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3487 getF32Constant(DAG, 0x406cfd1c));
3488 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3489 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3490 getF32Constant(DAG, 0x408797cb));
3491 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3492 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3493 getF32Constant(DAG, 0x4006dcab));
3495 result = DAG.getNode(ISD::FADD, dl,
3496 MVT::f32, LogOfExponent, LogOfMantissa);
3499 // No special expansion.
3500 result = DAG.getNode(ISD::FLOG, dl,
3501 getValue(I.getArgOperand(0)).getValueType(),
3502 getValue(I.getArgOperand(0)));
3505 setValue(&I, result);
3508 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3509 /// limited-precision mode.
3511 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3513 DebugLoc dl = getCurDebugLoc();
3515 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3516 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3517 SDValue Op = getValue(I.getArgOperand(0));
3518 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3520 // Get the exponent.
3521 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3523 // Get the significand and build it into a floating-point number with
3525 SDValue X = GetSignificand(DAG, Op1, dl);
3527 // Different possible minimax approximations of significand in
3528 // floating-point for various degrees of accuracy over [1,2].
3529 if (LimitFloatPrecision <= 6) {
3530 // For floating-point precision of 6:
3532 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3534 // error 0.0049451742, which is more than 7 bits
3535 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3536 getF32Constant(DAG, 0xbeb08fe0));
3537 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3538 getF32Constant(DAG, 0x40019463));
3539 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3540 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3541 getF32Constant(DAG, 0x3fd6633d));
3543 result = DAG.getNode(ISD::FADD, dl,
3544 MVT::f32, LogOfExponent, Log2ofMantissa);
3545 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3546 // For floating-point precision of 12:
3552 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3554 // error 0.0000876136000, which is better than 13 bits
3555 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3556 getF32Constant(DAG, 0xbda7262e));
3557 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3558 getF32Constant(DAG, 0x3f25280b));
3559 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3560 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3561 getF32Constant(DAG, 0x4007b923));
3562 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3563 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3564 getF32Constant(DAG, 0x40823e2f));
3565 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3566 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3567 getF32Constant(DAG, 0x4020d29c));
3569 result = DAG.getNode(ISD::FADD, dl,
3570 MVT::f32, LogOfExponent, Log2ofMantissa);
3571 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3572 // For floating-point precision of 18:
3581 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3583 // error 0.0000018516, which is better than 18 bits
3584 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3585 getF32Constant(DAG, 0xbcd2769e));
3586 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3587 getF32Constant(DAG, 0x3e8ce0b9));
3588 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3589 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3590 getF32Constant(DAG, 0x3fa22ae7));
3591 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3592 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3593 getF32Constant(DAG, 0x40525723));
3594 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3595 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3596 getF32Constant(DAG, 0x40aaf200));
3597 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3598 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3599 getF32Constant(DAG, 0x40c39dad));
3600 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3601 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3602 getF32Constant(DAG, 0x4042902c));
3604 result = DAG.getNode(ISD::FADD, dl,
3605 MVT::f32, LogOfExponent, Log2ofMantissa);
3608 // No special expansion.
3609 result = DAG.getNode(ISD::FLOG2, dl,
3610 getValue(I.getArgOperand(0)).getValueType(),
3611 getValue(I.getArgOperand(0)));
3614 setValue(&I, result);
3617 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3618 /// limited-precision mode.
3620 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3622 DebugLoc dl = getCurDebugLoc();
3624 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3625 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3626 SDValue Op = getValue(I.getArgOperand(0));
3627 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3629 // Scale the exponent by log10(2) [0.30102999f].
3630 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3631 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3632 getF32Constant(DAG, 0x3e9a209a));
3634 // Get the significand and build it into a floating-point number with
3636 SDValue X = GetSignificand(DAG, Op1, dl);
3638 if (LimitFloatPrecision <= 6) {
3639 // For floating-point precision of 6:
3641 // Log10ofMantissa =
3643 // (0.60948995f - 0.10380950f * x) * x;
3645 // error 0.0014886165, which is 6 bits
3646 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3647 getF32Constant(DAG, 0xbdd49a13));
3648 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3649 getF32Constant(DAG, 0x3f1c0789));
3650 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3651 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3652 getF32Constant(DAG, 0x3f011300));
3654 result = DAG.getNode(ISD::FADD, dl,
3655 MVT::f32, LogOfExponent, Log10ofMantissa);
3656 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3657 // For floating-point precision of 12:
3659 // Log10ofMantissa =
3662 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3664 // error 0.00019228036, which is better than 12 bits
3665 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3666 getF32Constant(DAG, 0x3d431f31));
3667 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3668 getF32Constant(DAG, 0x3ea21fb2));
3669 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3670 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3671 getF32Constant(DAG, 0x3f6ae232));
3672 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3673 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3674 getF32Constant(DAG, 0x3f25f7c3));
3676 result = DAG.getNode(ISD::FADD, dl,
3677 MVT::f32, LogOfExponent, Log10ofMantissa);
3678 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3679 // For floating-point precision of 18:
3681 // Log10ofMantissa =
3686 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3688 // error 0.0000037995730, which is better than 18 bits
3689 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3690 getF32Constant(DAG, 0x3c5d51ce));
3691 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3692 getF32Constant(DAG, 0x3e00685a));
3693 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3694 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3695 getF32Constant(DAG, 0x3efb6798));
3696 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3697 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3698 getF32Constant(DAG, 0x3f88d192));
3699 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3700 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3701 getF32Constant(DAG, 0x3fc4316c));
3702 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3703 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3704 getF32Constant(DAG, 0x3f57ce70));
3706 result = DAG.getNode(ISD::FADD, dl,
3707 MVT::f32, LogOfExponent, Log10ofMantissa);
3710 // No special expansion.
3711 result = DAG.getNode(ISD::FLOG10, dl,
3712 getValue(I.getArgOperand(0)).getValueType(),
3713 getValue(I.getArgOperand(0)));
3716 setValue(&I, result);
3719 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3720 /// limited-precision mode.
3722 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3724 DebugLoc dl = getCurDebugLoc();
3726 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3727 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3728 SDValue Op = getValue(I.getArgOperand(0));
3730 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3732 // FractionalPartOfX = x - (float)IntegerPartOfX;
3733 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3734 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3736 // IntegerPartOfX <<= 23;
3737 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3738 DAG.getConstant(23, TLI.getPointerTy()));
3740 if (LimitFloatPrecision <= 6) {
3741 // For floating-point precision of 6:
3743 // TwoToFractionalPartOfX =
3745 // (0.735607626f + 0.252464424f * x) * x;
3747 // error 0.0144103317, which is 6 bits
3748 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3749 getF32Constant(DAG, 0x3e814304));
3750 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3751 getF32Constant(DAG, 0x3f3c50c8));
3752 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3753 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3754 getF32Constant(DAG, 0x3f7f5e7e));
3755 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3756 SDValue TwoToFractionalPartOfX =
3757 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3759 result = DAG.getNode(ISD::BITCAST, dl,
3760 MVT::f32, TwoToFractionalPartOfX);
3761 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3762 // For floating-point precision of 12:
3764 // TwoToFractionalPartOfX =
3767 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3769 // error 0.000107046256, which is 13 to 14 bits
3770 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3771 getF32Constant(DAG, 0x3da235e3));
3772 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3773 getF32Constant(DAG, 0x3e65b8f3));
3774 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3775 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3776 getF32Constant(DAG, 0x3f324b07));
3777 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3778 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3779 getF32Constant(DAG, 0x3f7ff8fd));
3780 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3781 SDValue TwoToFractionalPartOfX =
3782 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3784 result = DAG.getNode(ISD::BITCAST, dl,
3785 MVT::f32, TwoToFractionalPartOfX);
3786 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3787 // For floating-point precision of 18:
3789 // TwoToFractionalPartOfX =
3793 // (0.554906021e-1f +
3794 // (0.961591928e-2f +
3795 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3796 // error 2.47208000*10^(-7), which is better than 18 bits
3797 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3798 getF32Constant(DAG, 0x3924b03e));
3799 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3800 getF32Constant(DAG, 0x3ab24b87));
3801 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3802 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3803 getF32Constant(DAG, 0x3c1d8c17));
3804 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3805 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3806 getF32Constant(DAG, 0x3d634a1d));
3807 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3808 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3809 getF32Constant(DAG, 0x3e75fe14));
3810 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3811 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3812 getF32Constant(DAG, 0x3f317234));
3813 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3814 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3815 getF32Constant(DAG, 0x3f800000));
3816 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3817 SDValue TwoToFractionalPartOfX =
3818 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3820 result = DAG.getNode(ISD::BITCAST, dl,
3821 MVT::f32, TwoToFractionalPartOfX);
3824 // No special expansion.
3825 result = DAG.getNode(ISD::FEXP2, dl,
3826 getValue(I.getArgOperand(0)).getValueType(),
3827 getValue(I.getArgOperand(0)));
3830 setValue(&I, result);
3833 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3834 /// limited-precision mode with x == 10.0f.
3836 SelectionDAGBuilder::visitPow(const CallInst &I) {
3838 const Value *Val = I.getArgOperand(0);
3839 DebugLoc dl = getCurDebugLoc();
3840 bool IsExp10 = false;
3842 if (getValue(Val).getValueType() == MVT::f32 &&
3843 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3844 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3845 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3846 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3848 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3853 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3854 SDValue Op = getValue(I.getArgOperand(1));
3856 // Put the exponent in the right bit position for later addition to the
3859 // #define LOG2OF10 3.3219281f
3860 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3861 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3862 getF32Constant(DAG, 0x40549a78));
3863 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3865 // FractionalPartOfX = x - (float)IntegerPartOfX;
3866 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3867 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3869 // IntegerPartOfX <<= 23;
3870 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3871 DAG.getConstant(23, TLI.getPointerTy()));
3873 if (LimitFloatPrecision <= 6) {
3874 // For floating-point precision of 6:
3876 // twoToFractionalPartOfX =
3878 // (0.735607626f + 0.252464424f * x) * x;
3880 // error 0.0144103317, which is 6 bits
3881 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3882 getF32Constant(DAG, 0x3e814304));
3883 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3884 getF32Constant(DAG, 0x3f3c50c8));
3885 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3886 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3887 getF32Constant(DAG, 0x3f7f5e7e));
3888 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3889 SDValue TwoToFractionalPartOfX =
3890 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3892 result = DAG.getNode(ISD::BITCAST, dl,
3893 MVT::f32, TwoToFractionalPartOfX);
3894 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3895 // For floating-point precision of 12:
3897 // TwoToFractionalPartOfX =
3900 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3902 // error 0.000107046256, which is 13 to 14 bits
3903 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3904 getF32Constant(DAG, 0x3da235e3));
3905 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3906 getF32Constant(DAG, 0x3e65b8f3));
3907 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3908 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3909 getF32Constant(DAG, 0x3f324b07));
3910 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3911 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3912 getF32Constant(DAG, 0x3f7ff8fd));
3913 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3914 SDValue TwoToFractionalPartOfX =
3915 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3917 result = DAG.getNode(ISD::BITCAST, dl,
3918 MVT::f32, TwoToFractionalPartOfX);
3919 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3920 // For floating-point precision of 18:
3922 // TwoToFractionalPartOfX =
3926 // (0.554906021e-1f +
3927 // (0.961591928e-2f +
3928 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3929 // error 2.47208000*10^(-7), which is better than 18 bits
3930 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3931 getF32Constant(DAG, 0x3924b03e));
3932 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3933 getF32Constant(DAG, 0x3ab24b87));
3934 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3935 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3936 getF32Constant(DAG, 0x3c1d8c17));
3937 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3938 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3939 getF32Constant(DAG, 0x3d634a1d));
3940 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3941 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3942 getF32Constant(DAG, 0x3e75fe14));
3943 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3944 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3945 getF32Constant(DAG, 0x3f317234));
3946 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3947 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3948 getF32Constant(DAG, 0x3f800000));
3949 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3950 SDValue TwoToFractionalPartOfX =
3951 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3953 result = DAG.getNode(ISD::BITCAST, dl,
3954 MVT::f32, TwoToFractionalPartOfX);
3957 // No special expansion.
3958 result = DAG.getNode(ISD::FPOW, dl,
3959 getValue(I.getArgOperand(0)).getValueType(),
3960 getValue(I.getArgOperand(0)),
3961 getValue(I.getArgOperand(1)));
3964 setValue(&I, result);
3968 /// ExpandPowI - Expand a llvm.powi intrinsic.
3969 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3970 SelectionDAG &DAG) {
3971 // If RHS is a constant, we can expand this out to a multiplication tree,
3972 // otherwise we end up lowering to a call to __powidf2 (for example). When
3973 // optimizing for size, we only want to do this if the expansion would produce
3974 // a small number of multiplies, otherwise we do the full expansion.
3975 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3976 // Get the exponent as a positive value.
3977 unsigned Val = RHSC->getSExtValue();
3978 if ((int)Val < 0) Val = -Val;
3980 // powi(x, 0) -> 1.0
3982 return DAG.getConstantFP(1.0, LHS.getValueType());
3984 const Function *F = DAG.getMachineFunction().getFunction();
3985 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3986 // If optimizing for size, don't insert too many multiplies. This
3987 // inserts up to 5 multiplies.
3988 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3989 // We use the simple binary decomposition method to generate the multiply
3990 // sequence. There are more optimal ways to do this (for example,
3991 // powi(x,15) generates one more multiply than it should), but this has
3992 // the benefit of being both really simple and much better than a libcall.
3993 SDValue Res; // Logically starts equal to 1.0
3994 SDValue CurSquare = LHS;
3998 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4000 Res = CurSquare; // 1.0*CurSquare.
4003 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4004 CurSquare, CurSquare);
4008 // If the original was negative, invert the result, producing 1/(x*x*x).
4009 if (RHSC->getSExtValue() < 0)
4010 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4011 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4016 // Otherwise, expand to a libcall.
4017 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4020 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4021 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4022 /// At the end of instruction selection, they will be inserted to the entry BB.
4024 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4027 const Argument *Arg = dyn_cast<Argument>(V);
4031 MachineFunction &MF = DAG.getMachineFunction();
4032 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4033 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4035 // Ignore inlined function arguments here.
4036 DIVariable DV(Variable);
4037 if (DV.isInlinedFnArgument(MF.getFunction()))
4040 MachineBasicBlock *MBB = FuncInfo.MBB;
4041 if (MBB != &MF.front())
4045 if (Arg->hasByValAttr()) {
4046 // Byval arguments' frame index is recorded during argument lowering.
4047 // Use this info directly.
4048 Reg = TRI->getFrameRegister(MF);
4049 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4050 // If byval argument ofset is not recorded then ignore this.
4055 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4056 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4057 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4058 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4059 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4066 // Check if ValueMap has reg number.
4067 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4068 if (VMI != FuncInfo.ValueMap.end())
4072 if (!Reg && N.getNode()) {
4073 // Check if frame index is available.
4074 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4075 if (FrameIndexSDNode *FINode =
4076 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4077 Reg = TRI->getFrameRegister(MF);
4078 Offset = FINode->getIndex();
4085 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4086 TII->get(TargetOpcode::DBG_VALUE))
4087 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4088 FuncInfo.ArgDbgValues.push_back(&*MIB);
4092 // VisualStudio defines setjmp as _setjmp
4093 #if defined(_MSC_VER) && defined(setjmp) && \
4094 !defined(setjmp_undefined_for_msvc)
4095 # pragma push_macro("setjmp")
4097 # define setjmp_undefined_for_msvc
4100 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4101 /// we want to emit this as a call to a named external function, return the name
4102 /// otherwise lower it and return null.
4104 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4105 DebugLoc dl = getCurDebugLoc();
4108 switch (Intrinsic) {
4110 // By default, turn this into a target intrinsic node.
4111 visitTargetIntrinsic(I, Intrinsic);
4113 case Intrinsic::vastart: visitVAStart(I); return 0;
4114 case Intrinsic::vaend: visitVAEnd(I); return 0;
4115 case Intrinsic::vacopy: visitVACopy(I); return 0;
4116 case Intrinsic::returnaddress:
4117 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4118 getValue(I.getArgOperand(0))));
4120 case Intrinsic::frameaddress:
4121 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4122 getValue(I.getArgOperand(0))));
4124 case Intrinsic::setjmp:
4125 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4126 case Intrinsic::longjmp:
4127 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4128 case Intrinsic::memcpy: {
4129 // Assert for address < 256 since we support only user defined address
4131 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4133 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4135 "Unknown address space");
4136 SDValue Op1 = getValue(I.getArgOperand(0));
4137 SDValue Op2 = getValue(I.getArgOperand(1));
4138 SDValue Op3 = getValue(I.getArgOperand(2));
4139 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4140 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4141 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4142 MachinePointerInfo(I.getArgOperand(0)),
4143 MachinePointerInfo(I.getArgOperand(1))));
4146 case Intrinsic::memset: {
4147 // Assert for address < 256 since we support only user defined address
4149 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4151 "Unknown address space");
4152 SDValue Op1 = getValue(I.getArgOperand(0));
4153 SDValue Op2 = getValue(I.getArgOperand(1));
4154 SDValue Op3 = getValue(I.getArgOperand(2));
4155 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4156 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4157 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4158 MachinePointerInfo(I.getArgOperand(0))));
4161 case Intrinsic::memmove: {
4162 // Assert for address < 256 since we support only user defined address
4164 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4166 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4168 "Unknown address space");
4169 SDValue Op1 = getValue(I.getArgOperand(0));
4170 SDValue Op2 = getValue(I.getArgOperand(1));
4171 SDValue Op3 = getValue(I.getArgOperand(2));
4172 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4173 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4174 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4175 MachinePointerInfo(I.getArgOperand(0)),
4176 MachinePointerInfo(I.getArgOperand(1))));
4179 case Intrinsic::dbg_declare: {
4180 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4181 MDNode *Variable = DI.getVariable();
4182 const Value *Address = DI.getAddress();
4183 if (!Address || !DIVariable(DI.getVariable()).Verify())
4186 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4187 // but do not always have a corresponding SDNode built. The SDNodeOrder
4188 // absolute, but not relative, values are different depending on whether
4189 // debug info exists.
4192 // Check if address has undef value.
4193 if (isa<UndefValue>(Address) ||
4194 (Address->use_empty() && !isa<Argument>(Address))) {
4195 DEBUG(dbgs() << "Dropping debug info for " << DI);
4199 SDValue &N = NodeMap[Address];
4200 if (!N.getNode() && isa<Argument>(Address))
4201 // Check unused arguments map.
4202 N = UnusedArgNodeMap[Address];
4205 // Parameters are handled specially.
4207 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4208 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4209 Address = BCI->getOperand(0);
4210 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4212 if (isParameter && !AI) {
4213 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4215 // Byval parameter. We have a frame index at this point.
4216 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4217 0, dl, SDNodeOrder);
4219 // Can't do anything with other non-AI cases yet. This might be a
4220 // parameter of a callee function that got inlined, for example.
4221 DEBUG(dbgs() << "Dropping debug info for " << DI);
4225 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4226 0, dl, SDNodeOrder);
4228 // Can't do anything with other non-AI cases yet.
4229 DEBUG(dbgs() << "Dropping debug info for " << DI);
4232 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4234 // If Address is an argument then try to emit its dbg value using
4235 // virtual register info from the FuncInfo.ValueMap.
4236 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4237 // If variable is pinned by a alloca in dominating bb then
4238 // use StaticAllocaMap.
4239 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4240 if (AI->getParent() != DI.getParent()) {
4241 DenseMap<const AllocaInst*, int>::iterator SI =
4242 FuncInfo.StaticAllocaMap.find(AI);
4243 if (SI != FuncInfo.StaticAllocaMap.end()) {
4244 SDV = DAG.getDbgValue(Variable, SI->second,
4245 0, dl, SDNodeOrder);
4246 DAG.AddDbgValue(SDV, 0, false);
4251 DEBUG(dbgs() << "Dropping debug info for " << DI);
4256 case Intrinsic::dbg_value: {
4257 const DbgValueInst &DI = cast<DbgValueInst>(I);
4258 if (!DIVariable(DI.getVariable()).Verify())
4261 MDNode *Variable = DI.getVariable();
4262 uint64_t Offset = DI.getOffset();
4263 const Value *V = DI.getValue();
4267 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4268 // but do not always have a corresponding SDNode built. The SDNodeOrder
4269 // absolute, but not relative, values are different depending on whether
4270 // debug info exists.
4273 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4274 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4275 DAG.AddDbgValue(SDV, 0, false);
4277 // Do not use getValue() in here; we don't want to generate code at
4278 // this point if it hasn't been done yet.
4279 SDValue N = NodeMap[V];
4280 if (!N.getNode() && isa<Argument>(V))
4281 // Check unused arguments map.
4282 N = UnusedArgNodeMap[V];
4284 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4285 SDV = DAG.getDbgValue(Variable, N.getNode(),
4286 N.getResNo(), Offset, dl, SDNodeOrder);
4287 DAG.AddDbgValue(SDV, N.getNode(), false);
4289 } else if (!V->use_empty() ) {
4290 // Do not call getValue(V) yet, as we don't want to generate code.
4291 // Remember it for later.
4292 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4293 DanglingDebugInfoMap[V] = DDI;
4295 // We may expand this to cover more cases. One case where we have no
4296 // data available is an unreferenced parameter.
4297 DEBUG(dbgs() << "Dropping debug info for " << DI);
4301 // Build a debug info table entry.
4302 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4303 V = BCI->getOperand(0);
4304 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4305 // Don't handle byval struct arguments or VLAs, for example.
4308 DenseMap<const AllocaInst*, int>::iterator SI =
4309 FuncInfo.StaticAllocaMap.find(AI);
4310 if (SI == FuncInfo.StaticAllocaMap.end())
4312 int FI = SI->second;
4314 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4315 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4316 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4319 case Intrinsic::eh_exception: {
4320 // Insert the EXCEPTIONADDR instruction.
4321 assert(FuncInfo.MBB->isLandingPad() &&
4322 "Call to eh.exception not in landing pad!");
4323 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4325 Ops[0] = DAG.getRoot();
4326 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4328 DAG.setRoot(Op.getValue(1));
4332 case Intrinsic::eh_selector: {
4333 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4334 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4335 if (CallMBB->isLandingPad())
4336 AddCatchInfo(I, &MMI, CallMBB);
4339 FuncInfo.CatchInfoLost.insert(&I);
4341 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4342 unsigned Reg = TLI.getExceptionSelectorRegister();
4343 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4346 // Insert the EHSELECTION instruction.
4347 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4349 Ops[0] = getValue(I.getArgOperand(0));
4351 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4352 DAG.setRoot(Op.getValue(1));
4353 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4357 case Intrinsic::eh_typeid_for: {
4358 // Find the type id for the given typeinfo.
4359 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4360 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4361 Res = DAG.getConstant(TypeID, MVT::i32);
4366 case Intrinsic::eh_return_i32:
4367 case Intrinsic::eh_return_i64:
4368 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4369 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4372 getValue(I.getArgOperand(0)),
4373 getValue(I.getArgOperand(1))));
4375 case Intrinsic::eh_unwind_init:
4376 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4378 case Intrinsic::eh_dwarf_cfa: {
4379 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4380 TLI.getPointerTy());
4381 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4383 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4384 TLI.getPointerTy()),
4386 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4388 DAG.getConstant(0, TLI.getPointerTy()));
4389 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4393 case Intrinsic::eh_sjlj_callsite: {
4394 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4395 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4396 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4397 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4399 MMI.setCurrentCallSite(CI->getZExtValue());
4402 case Intrinsic::eh_sjlj_setjmp: {
4403 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4404 getValue(I.getArgOperand(0))));
4407 case Intrinsic::eh_sjlj_longjmp: {
4408 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4409 getRoot(), getValue(I.getArgOperand(0))));
4412 case Intrinsic::eh_sjlj_dispatch_setup: {
4413 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4414 getRoot(), getValue(I.getArgOperand(0))));
4418 case Intrinsic::x86_mmx_pslli_w:
4419 case Intrinsic::x86_mmx_pslli_d:
4420 case Intrinsic::x86_mmx_pslli_q:
4421 case Intrinsic::x86_mmx_psrli_w:
4422 case Intrinsic::x86_mmx_psrli_d:
4423 case Intrinsic::x86_mmx_psrli_q:
4424 case Intrinsic::x86_mmx_psrai_w:
4425 case Intrinsic::x86_mmx_psrai_d: {
4426 SDValue ShAmt = getValue(I.getArgOperand(1));
4427 if (isa<ConstantSDNode>(ShAmt)) {
4428 visitTargetIntrinsic(I, Intrinsic);
4431 unsigned NewIntrinsic = 0;
4432 EVT ShAmtVT = MVT::v2i32;
4433 switch (Intrinsic) {
4434 case Intrinsic::x86_mmx_pslli_w:
4435 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4437 case Intrinsic::x86_mmx_pslli_d:
4438 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4440 case Intrinsic::x86_mmx_pslli_q:
4441 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4443 case Intrinsic::x86_mmx_psrli_w:
4444 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4446 case Intrinsic::x86_mmx_psrli_d:
4447 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4449 case Intrinsic::x86_mmx_psrli_q:
4450 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4452 case Intrinsic::x86_mmx_psrai_w:
4453 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4455 case Intrinsic::x86_mmx_psrai_d:
4456 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4458 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4461 // The vector shift intrinsics with scalars uses 32b shift amounts but
4462 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4464 // We must do this early because v2i32 is not a legal type.
4465 DebugLoc dl = getCurDebugLoc();
4468 ShOps[1] = DAG.getConstant(0, MVT::i32);
4469 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4470 EVT DestVT = TLI.getValueType(I.getType());
4471 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4472 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4473 DAG.getConstant(NewIntrinsic, MVT::i32),
4474 getValue(I.getArgOperand(0)), ShAmt);
4478 case Intrinsic::convertff:
4479 case Intrinsic::convertfsi:
4480 case Intrinsic::convertfui:
4481 case Intrinsic::convertsif:
4482 case Intrinsic::convertuif:
4483 case Intrinsic::convertss:
4484 case Intrinsic::convertsu:
4485 case Intrinsic::convertus:
4486 case Intrinsic::convertuu: {
4487 ISD::CvtCode Code = ISD::CVT_INVALID;
4488 switch (Intrinsic) {
4489 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4490 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4491 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4492 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4493 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4494 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4495 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4496 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4497 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4499 EVT DestVT = TLI.getValueType(I.getType());
4500 const Value *Op1 = I.getArgOperand(0);
4501 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4502 DAG.getValueType(DestVT),
4503 DAG.getValueType(getValue(Op1).getValueType()),
4504 getValue(I.getArgOperand(1)),
4505 getValue(I.getArgOperand(2)),
4510 case Intrinsic::sqrt:
4511 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4512 getValue(I.getArgOperand(0)).getValueType(),
4513 getValue(I.getArgOperand(0))));
4515 case Intrinsic::powi:
4516 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4517 getValue(I.getArgOperand(1)), DAG));
4519 case Intrinsic::sin:
4520 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4521 getValue(I.getArgOperand(0)).getValueType(),
4522 getValue(I.getArgOperand(0))));
4524 case Intrinsic::cos:
4525 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4526 getValue(I.getArgOperand(0)).getValueType(),
4527 getValue(I.getArgOperand(0))));
4529 case Intrinsic::log:
4532 case Intrinsic::log2:
4535 case Intrinsic::log10:
4538 case Intrinsic::exp:
4541 case Intrinsic::exp2:
4544 case Intrinsic::pow:
4547 case Intrinsic::convert_to_fp16:
4548 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4549 MVT::i16, getValue(I.getArgOperand(0))));
4551 case Intrinsic::convert_from_fp16:
4552 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4553 MVT::f32, getValue(I.getArgOperand(0))));
4555 case Intrinsic::pcmarker: {
4556 SDValue Tmp = getValue(I.getArgOperand(0));
4557 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4560 case Intrinsic::readcyclecounter: {
4561 SDValue Op = getRoot();
4562 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4563 DAG.getVTList(MVT::i64, MVT::Other),
4566 DAG.setRoot(Res.getValue(1));
4569 case Intrinsic::bswap:
4570 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4571 getValue(I.getArgOperand(0)).getValueType(),
4572 getValue(I.getArgOperand(0))));
4574 case Intrinsic::cttz: {
4575 SDValue Arg = getValue(I.getArgOperand(0));
4576 EVT Ty = Arg.getValueType();
4577 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4580 case Intrinsic::ctlz: {
4581 SDValue Arg = getValue(I.getArgOperand(0));
4582 EVT Ty = Arg.getValueType();
4583 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4586 case Intrinsic::ctpop: {
4587 SDValue Arg = getValue(I.getArgOperand(0));
4588 EVT Ty = Arg.getValueType();
4589 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4592 case Intrinsic::stacksave: {
4593 SDValue Op = getRoot();
4594 Res = DAG.getNode(ISD::STACKSAVE, dl,
4595 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4597 DAG.setRoot(Res.getValue(1));
4600 case Intrinsic::stackrestore: {
4601 Res = getValue(I.getArgOperand(0));
4602 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4605 case Intrinsic::stackprotector: {
4606 // Emit code into the DAG to store the stack guard onto the stack.
4607 MachineFunction &MF = DAG.getMachineFunction();
4608 MachineFrameInfo *MFI = MF.getFrameInfo();
4609 EVT PtrTy = TLI.getPointerTy();
4611 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4612 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4614 int FI = FuncInfo.StaticAllocaMap[Slot];
4615 MFI->setStackProtectorIndex(FI);
4617 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4619 // Store the stack protector onto the stack.
4620 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4621 MachinePointerInfo::getFixedStack(FI),
4627 case Intrinsic::objectsize: {
4628 // If we don't know by now, we're never going to know.
4629 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4631 assert(CI && "Non-constant type in __builtin_object_size?");
4633 SDValue Arg = getValue(I.getCalledValue());
4634 EVT Ty = Arg.getValueType();
4637 Res = DAG.getConstant(-1ULL, Ty);
4639 Res = DAG.getConstant(0, Ty);
4644 case Intrinsic::var_annotation:
4645 // Discard annotate attributes
4648 case Intrinsic::init_trampoline: {
4649 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4653 Ops[1] = getValue(I.getArgOperand(0));
4654 Ops[2] = getValue(I.getArgOperand(1));
4655 Ops[3] = getValue(I.getArgOperand(2));
4656 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4657 Ops[5] = DAG.getSrcValue(F);
4659 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4660 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4664 DAG.setRoot(Res.getValue(1));
4667 case Intrinsic::gcroot:
4669 const Value *Alloca = I.getArgOperand(0);
4670 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4672 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4673 GFI->addStackRoot(FI->getIndex(), TypeMap);
4676 case Intrinsic::gcread:
4677 case Intrinsic::gcwrite:
4678 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4680 case Intrinsic::flt_rounds:
4681 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4683 case Intrinsic::trap:
4684 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4686 case Intrinsic::uadd_with_overflow:
4687 return implVisitAluOverflow(I, ISD::UADDO);
4688 case Intrinsic::sadd_with_overflow:
4689 return implVisitAluOverflow(I, ISD::SADDO);
4690 case Intrinsic::usub_with_overflow:
4691 return implVisitAluOverflow(I, ISD::USUBO);
4692 case Intrinsic::ssub_with_overflow:
4693 return implVisitAluOverflow(I, ISD::SSUBO);
4694 case Intrinsic::umul_with_overflow:
4695 return implVisitAluOverflow(I, ISD::UMULO);
4696 case Intrinsic::smul_with_overflow:
4697 return implVisitAluOverflow(I, ISD::SMULO);
4699 case Intrinsic::prefetch: {
4701 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4703 Ops[1] = getValue(I.getArgOperand(0));
4704 Ops[2] = getValue(I.getArgOperand(1));
4705 Ops[3] = getValue(I.getArgOperand(2));
4706 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4707 DAG.getVTList(MVT::Other),
4709 EVT::getIntegerVT(*Context, 8),
4710 MachinePointerInfo(I.getArgOperand(0)),
4712 false, /* volatile */
4714 rw==1)); /* write */
4717 case Intrinsic::memory_barrier: {
4720 for (int x = 1; x < 6; ++x)
4721 Ops[x] = getValue(I.getArgOperand(x - 1));
4723 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4726 case Intrinsic::atomic_cmp_swap: {
4727 SDValue Root = getRoot();
4729 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4730 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4732 getValue(I.getArgOperand(0)),
4733 getValue(I.getArgOperand(1)),
4734 getValue(I.getArgOperand(2)),
4735 MachinePointerInfo(I.getArgOperand(0)));
4737 DAG.setRoot(L.getValue(1));
4740 case Intrinsic::atomic_load_add:
4741 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4742 case Intrinsic::atomic_load_sub:
4743 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4744 case Intrinsic::atomic_load_or:
4745 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4746 case Intrinsic::atomic_load_xor:
4747 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4748 case Intrinsic::atomic_load_and:
4749 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4750 case Intrinsic::atomic_load_nand:
4751 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4752 case Intrinsic::atomic_load_max:
4753 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4754 case Intrinsic::atomic_load_min:
4755 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4756 case Intrinsic::atomic_load_umin:
4757 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4758 case Intrinsic::atomic_load_umax:
4759 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4760 case Intrinsic::atomic_swap:
4761 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4763 case Intrinsic::invariant_start:
4764 case Intrinsic::lifetime_start:
4765 // Discard region information.
4766 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4768 case Intrinsic::invariant_end:
4769 case Intrinsic::lifetime_end:
4770 // Discard region information.
4775 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4777 MachineBasicBlock *LandingPad) {
4778 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4779 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4780 const Type *RetTy = FTy->getReturnType();
4781 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4782 MCSymbol *BeginLabel = 0;
4784 TargetLowering::ArgListTy Args;
4785 TargetLowering::ArgListEntry Entry;
4786 Args.reserve(CS.arg_size());
4788 // Check whether the function can return without sret-demotion.
4789 SmallVector<ISD::OutputArg, 4> Outs;
4790 SmallVector<uint64_t, 4> Offsets;
4791 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4792 Outs, TLI, &Offsets);
4794 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4795 FTy->isVarArg(), Outs, FTy->getContext());
4797 SDValue DemoteStackSlot;
4798 int DemoteStackIdx = -100;
4800 if (!CanLowerReturn) {
4801 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4802 FTy->getReturnType());
4803 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4804 FTy->getReturnType());
4805 MachineFunction &MF = DAG.getMachineFunction();
4806 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4807 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4809 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4810 Entry.Node = DemoteStackSlot;
4811 Entry.Ty = StackSlotPtrType;
4812 Entry.isSExt = false;
4813 Entry.isZExt = false;
4814 Entry.isInReg = false;
4815 Entry.isSRet = true;
4816 Entry.isNest = false;
4817 Entry.isByVal = false;
4818 Entry.Alignment = Align;
4819 Args.push_back(Entry);
4820 RetTy = Type::getVoidTy(FTy->getContext());
4823 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4825 SDValue ArgNode = getValue(*i);
4826 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4828 unsigned attrInd = i - CS.arg_begin() + 1;
4829 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4830 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4831 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4832 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4833 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4834 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4835 Entry.Alignment = CS.getParamAlignment(attrInd);
4836 Args.push_back(Entry);
4840 // Insert a label before the invoke call to mark the try range. This can be
4841 // used to detect deletion of the invoke via the MachineModuleInfo.
4842 BeginLabel = MMI.getContext().CreateTempSymbol();
4844 // For SjLj, keep track of which landing pads go with which invokes
4845 // so as to maintain the ordering of pads in the LSDA.
4846 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4847 if (CallSiteIndex) {
4848 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4849 // Now that the call site is handled, stop tracking it.
4850 MMI.setCurrentCallSite(0);
4853 // Both PendingLoads and PendingExports must be flushed here;
4854 // this call might not return.
4856 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4859 // Check if target-independent constraints permit a tail call here.
4860 // Target-dependent constraints are checked within TLI.LowerCallTo.
4862 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4865 // If there's a possibility that fast-isel has already selected some amount
4866 // of the current basic block, don't emit a tail call.
4867 if (isTailCall && EnableFastISel)
4870 std::pair<SDValue,SDValue> Result =
4871 TLI.LowerCallTo(getRoot(), RetTy,
4872 CS.paramHasAttr(0, Attribute::SExt),
4873 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4874 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4875 CS.getCallingConv(),
4877 !CS.getInstruction()->use_empty(),
4878 Callee, Args, DAG, getCurDebugLoc());
4879 assert((isTailCall || Result.second.getNode()) &&
4880 "Non-null chain expected with non-tail call!");
4881 assert((Result.second.getNode() || !Result.first.getNode()) &&
4882 "Null value expected with tail call!");
4883 if (Result.first.getNode()) {
4884 setValue(CS.getInstruction(), Result.first);
4885 } else if (!CanLowerReturn && Result.second.getNode()) {
4886 // The instruction result is the result of loading from the
4887 // hidden sret parameter.
4888 SmallVector<EVT, 1> PVTs;
4889 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4891 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4892 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4893 EVT PtrVT = PVTs[0];
4894 unsigned NumValues = Outs.size();
4895 SmallVector<SDValue, 4> Values(NumValues);
4896 SmallVector<SDValue, 4> Chains(NumValues);
4898 for (unsigned i = 0; i < NumValues; ++i) {
4899 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4901 DAG.getConstant(Offsets[i], PtrVT));
4902 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4904 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4907 Chains[i] = L.getValue(1);
4910 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4911 MVT::Other, &Chains[0], NumValues);
4912 PendingLoads.push_back(Chain);
4914 // Collect the legal value parts into potentially illegal values
4915 // that correspond to the original function's return values.
4916 SmallVector<EVT, 4> RetTys;
4917 RetTy = FTy->getReturnType();
4918 ComputeValueVTs(TLI, RetTy, RetTys);
4919 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4920 SmallVector<SDValue, 4> ReturnValues;
4921 unsigned CurReg = 0;
4922 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4924 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4925 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4927 SDValue ReturnValue =
4928 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4929 RegisterVT, VT, AssertOp);
4930 ReturnValues.push_back(ReturnValue);
4934 setValue(CS.getInstruction(),
4935 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4936 DAG.getVTList(&RetTys[0], RetTys.size()),
4937 &ReturnValues[0], ReturnValues.size()));
4941 // As a special case, a null chain means that a tail call has been emitted and
4942 // the DAG root is already updated.
4943 if (Result.second.getNode())
4944 DAG.setRoot(Result.second);
4949 // Insert a label at the end of the invoke call to mark the try range. This
4950 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4951 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4952 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4954 // Inform MachineModuleInfo of range.
4955 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4959 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4960 /// value is equal or not-equal to zero.
4961 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4962 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4964 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4965 if (IC->isEquality())
4966 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4967 if (C->isNullValue())
4969 // Unknown instruction.
4975 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4977 SelectionDAGBuilder &Builder) {
4979 // Check to see if this load can be trivially constant folded, e.g. if the
4980 // input is from a string literal.
4981 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4982 // Cast pointer to the type we really want to load.
4983 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4984 PointerType::getUnqual(LoadTy));
4986 if (const Constant *LoadCst =
4987 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4989 return Builder.getValue(LoadCst);
4992 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4993 // still constant memory, the input chain can be the entry node.
4995 bool ConstantMemory = false;
4997 // Do not serialize (non-volatile) loads of constant memory with anything.
4998 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
4999 Root = Builder.DAG.getEntryNode();
5000 ConstantMemory = true;
5002 // Do not serialize non-volatile loads against each other.
5003 Root = Builder.DAG.getRoot();
5006 SDValue Ptr = Builder.getValue(PtrVal);
5007 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5008 Ptr, MachinePointerInfo(PtrVal),
5010 false /*nontemporal*/, 1 /* align=1 */);
5012 if (!ConstantMemory)
5013 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5018 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5019 /// If so, return true and lower it, otherwise return false and it will be
5020 /// lowered like a normal call.
5021 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5022 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5023 if (I.getNumArgOperands() != 3)
5026 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5027 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5028 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5029 !I.getType()->isIntegerTy())
5032 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5034 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5035 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5036 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5037 bool ActuallyDoIt = true;
5040 switch (Size->getZExtValue()) {
5042 LoadVT = MVT::Other;
5044 ActuallyDoIt = false;
5048 LoadTy = Type::getInt16Ty(Size->getContext());
5052 LoadTy = Type::getInt32Ty(Size->getContext());
5056 LoadTy = Type::getInt64Ty(Size->getContext());
5060 LoadVT = MVT::v4i32;
5061 LoadTy = Type::getInt32Ty(Size->getContext());
5062 LoadTy = VectorType::get(LoadTy, 4);
5067 // This turns into unaligned loads. We only do this if the target natively
5068 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5069 // we'll only produce a small number of byte loads.
5071 // Require that we can find a legal MVT, and only do this if the target
5072 // supports unaligned loads of that type. Expanding into byte loads would
5074 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5075 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5076 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5077 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5078 ActuallyDoIt = false;
5082 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5083 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5085 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5087 EVT CallVT = TLI.getValueType(I.getType(), true);
5088 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5098 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5099 // Handle inline assembly differently.
5100 if (isa<InlineAsm>(I.getCalledValue())) {
5105 // See if any floating point values are being passed to this function. This is
5106 // used to emit an undefined reference to fltused on Windows.
5107 const FunctionType *FT =
5108 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5109 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5110 if (FT->isVarArg() &&
5111 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5112 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5113 const Type* T = I.getArgOperand(i)->getType();
5114 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5116 if (!i->isFloatingPointTy()) continue;
5117 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5123 const char *RenameFn = 0;
5124 if (Function *F = I.getCalledFunction()) {
5125 if (F->isDeclaration()) {
5126 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5127 if (unsigned IID = II->getIntrinsicID(F)) {
5128 RenameFn = visitIntrinsicCall(I, IID);
5133 if (unsigned IID = F->getIntrinsicID()) {
5134 RenameFn = visitIntrinsicCall(I, IID);
5140 // Check for well-known libc/libm calls. If the function is internal, it
5141 // can't be a library call.
5142 if (!F->hasLocalLinkage() && F->hasName()) {
5143 StringRef Name = F->getName();
5144 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5145 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5146 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5147 I.getType() == I.getArgOperand(0)->getType() &&
5148 I.getType() == I.getArgOperand(1)->getType()) {
5149 SDValue LHS = getValue(I.getArgOperand(0));
5150 SDValue RHS = getValue(I.getArgOperand(1));
5151 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5152 LHS.getValueType(), LHS, RHS));
5155 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5156 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5157 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5158 I.getType() == I.getArgOperand(0)->getType()) {
5159 SDValue Tmp = getValue(I.getArgOperand(0));
5160 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5161 Tmp.getValueType(), Tmp));
5164 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5165 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5166 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5167 I.getType() == I.getArgOperand(0)->getType() &&
5168 I.onlyReadsMemory()) {
5169 SDValue Tmp = getValue(I.getArgOperand(0));
5170 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5171 Tmp.getValueType(), Tmp));
5174 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5175 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5176 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5177 I.getType() == I.getArgOperand(0)->getType() &&
5178 I.onlyReadsMemory()) {
5179 SDValue Tmp = getValue(I.getArgOperand(0));
5180 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5181 Tmp.getValueType(), Tmp));
5184 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5185 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5186 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5187 I.getType() == I.getArgOperand(0)->getType() &&
5188 I.onlyReadsMemory()) {
5189 SDValue Tmp = getValue(I.getArgOperand(0));
5190 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5191 Tmp.getValueType(), Tmp));
5194 } else if (Name == "memcmp") {
5195 if (visitMemCmpCall(I))
5203 Callee = getValue(I.getCalledValue());
5205 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5207 // Check if we can potentially perform a tail call. More detailed checking is
5208 // be done within LowerCallTo, after more information about the call is known.
5209 LowerCallTo(&I, Callee, I.isTailCall());
5214 /// AsmOperandInfo - This contains information for each constraint that we are
5216 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5217 public TargetLowering::AsmOperandInfo {
5219 /// CallOperand - If this is the result output operand or a clobber
5220 /// this is null, otherwise it is the incoming operand to the CallInst.
5221 /// This gets modified as the asm is processed.
5222 SDValue CallOperand;
5224 /// AssignedRegs - If this is a register or register class operand, this
5225 /// contains the set of register corresponding to the operand.
5226 RegsForValue AssignedRegs;
5228 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5229 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5232 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5233 /// busy in OutputRegs/InputRegs.
5234 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5235 std::set<unsigned> &OutputRegs,
5236 std::set<unsigned> &InputRegs,
5237 const TargetRegisterInfo &TRI) const {
5239 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5240 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5243 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5244 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5248 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5249 /// corresponds to. If there is no Value* for this operand, it returns
5251 EVT getCallOperandValEVT(LLVMContext &Context,
5252 const TargetLowering &TLI,
5253 const TargetData *TD) const {
5254 if (CallOperandVal == 0) return MVT::Other;
5256 if (isa<BasicBlock>(CallOperandVal))
5257 return TLI.getPointerTy();
5259 const llvm::Type *OpTy = CallOperandVal->getType();
5261 // If this is an indirect operand, the operand is a pointer to the
5264 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5266 report_fatal_error("Indirect operand for inline asm not a pointer!");
5267 OpTy = PtrTy->getElementType();
5270 // If OpTy is not a single value, it may be a struct/union that we
5271 // can tile with integers.
5272 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5273 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5282 OpTy = IntegerType::get(Context, BitSize);
5287 return TLI.getValueType(OpTy, true);
5291 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5293 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5294 const TargetRegisterInfo &TRI) {
5295 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5297 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5298 for (; *Aliases; ++Aliases)
5299 Regs.insert(*Aliases);
5303 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5305 } // end llvm namespace.
5307 /// isAllocatableRegister - If the specified register is safe to allocate,
5308 /// i.e. it isn't a stack pointer or some other special register, return the
5309 /// register class for the register. Otherwise, return null.
5310 static const TargetRegisterClass *
5311 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5312 const TargetLowering &TLI,
5313 const TargetRegisterInfo *TRI) {
5314 EVT FoundVT = MVT::Other;
5315 const TargetRegisterClass *FoundRC = 0;
5316 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5317 E = TRI->regclass_end(); RCI != E; ++RCI) {
5318 EVT ThisVT = MVT::Other;
5320 const TargetRegisterClass *RC = *RCI;
5321 // If none of the value types for this register class are valid, we
5322 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5323 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5325 if (TLI.isTypeLegal(*I)) {
5326 // If we have already found this register in a different register class,
5327 // choose the one with the largest VT specified. For example, on
5328 // PowerPC, we favor f64 register classes over f32.
5329 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5336 if (ThisVT == MVT::Other) continue;
5338 // NOTE: This isn't ideal. In particular, this might allocate the
5339 // frame pointer in functions that need it (due to them not being taken
5340 // out of allocation, because a variable sized allocation hasn't been seen
5341 // yet). This is a slight code pessimization, but should still work.
5342 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5343 E = RC->allocation_order_end(MF); I != E; ++I)
5345 // We found a matching register class. Keep looking at others in case
5346 // we find one with larger registers that this physreg is also in.
5355 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5356 /// specified operand. We prefer to assign virtual registers, to allow the
5357 /// register allocator to handle the assignment process. However, if the asm
5358 /// uses features that we can't model on machineinstrs, we have SDISel do the
5359 /// allocation. This produces generally horrible, but correct, code.
5361 /// OpInfo describes the operand.
5362 /// Input and OutputRegs are the set of already allocated physical registers.
5364 void SelectionDAGBuilder::
5365 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5366 std::set<unsigned> &OutputRegs,
5367 std::set<unsigned> &InputRegs) {
5368 LLVMContext &Context = FuncInfo.Fn->getContext();
5370 // Compute whether this value requires an input register, an output register,
5372 bool isOutReg = false;
5373 bool isInReg = false;
5374 switch (OpInfo.Type) {
5375 case InlineAsm::isOutput:
5378 // If there is an input constraint that matches this, we need to reserve
5379 // the input register so no other inputs allocate to it.
5380 isInReg = OpInfo.hasMatchingInput();
5382 case InlineAsm::isInput:
5386 case InlineAsm::isClobber:
5393 MachineFunction &MF = DAG.getMachineFunction();
5394 SmallVector<unsigned, 4> Regs;
5396 // If this is a constraint for a single physreg, or a constraint for a
5397 // register class, find it.
5398 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5399 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5400 OpInfo.ConstraintVT);
5402 unsigned NumRegs = 1;
5403 if (OpInfo.ConstraintVT != MVT::Other) {
5404 // If this is a FP input in an integer register (or visa versa) insert a bit
5405 // cast of the input value. More generally, handle any case where the input
5406 // value disagrees with the register class we plan to stick this in.
5407 if (OpInfo.Type == InlineAsm::isInput &&
5408 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5409 // Try to convert to the first EVT that the reg class contains. If the
5410 // types are identical size, use a bitcast to convert (e.g. two differing
5412 EVT RegVT = *PhysReg.second->vt_begin();
5413 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5414 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5415 RegVT, OpInfo.CallOperand);
5416 OpInfo.ConstraintVT = RegVT;
5417 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5418 // If the input is a FP value and we want it in FP registers, do a
5419 // bitcast to the corresponding integer type. This turns an f64 value
5420 // into i64, which can be passed with two i32 values on a 32-bit
5422 RegVT = EVT::getIntegerVT(Context,
5423 OpInfo.ConstraintVT.getSizeInBits());
5424 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5425 RegVT, OpInfo.CallOperand);
5426 OpInfo.ConstraintVT = RegVT;
5430 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5434 EVT ValueVT = OpInfo.ConstraintVT;
5436 // If this is a constraint for a specific physical register, like {r17},
5438 if (unsigned AssignedReg = PhysReg.first) {
5439 const TargetRegisterClass *RC = PhysReg.second;
5440 if (OpInfo.ConstraintVT == MVT::Other)
5441 ValueVT = *RC->vt_begin();
5443 // Get the actual register value type. This is important, because the user
5444 // may have asked for (e.g.) the AX register in i32 type. We need to
5445 // remember that AX is actually i16 to get the right extension.
5446 RegVT = *RC->vt_begin();
5448 // This is a explicit reference to a physical register.
5449 Regs.push_back(AssignedReg);
5451 // If this is an expanded reference, add the rest of the regs to Regs.
5453 TargetRegisterClass::iterator I = RC->begin();
5454 for (; *I != AssignedReg; ++I)
5455 assert(I != RC->end() && "Didn't find reg!");
5457 // Already added the first reg.
5459 for (; NumRegs; --NumRegs, ++I) {
5460 assert(I != RC->end() && "Ran out of registers to allocate!");
5465 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5466 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5467 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5471 // Otherwise, if this was a reference to an LLVM register class, create vregs
5472 // for this reference.
5473 if (const TargetRegisterClass *RC = PhysReg.second) {
5474 RegVT = *RC->vt_begin();
5475 if (OpInfo.ConstraintVT == MVT::Other)
5478 // Create the appropriate number of virtual registers.
5479 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5480 for (; NumRegs; --NumRegs)
5481 Regs.push_back(RegInfo.createVirtualRegister(RC));
5483 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5487 // This is a reference to a register class that doesn't directly correspond
5488 // to an LLVM register class. Allocate NumRegs consecutive, available,
5489 // registers from the class.
5490 std::vector<unsigned> RegClassRegs
5491 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5492 OpInfo.ConstraintVT);
5494 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5495 unsigned NumAllocated = 0;
5496 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5497 unsigned Reg = RegClassRegs[i];
5498 // See if this register is available.
5499 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5500 (isInReg && InputRegs.count(Reg))) { // Already used.
5501 // Make sure we find consecutive registers.
5506 // Check to see if this register is allocatable (i.e. don't give out the
5508 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5509 if (!RC) { // Couldn't allocate this register.
5510 // Reset NumAllocated to make sure we return consecutive registers.
5515 // Okay, this register is good, we can use it.
5518 // If we allocated enough consecutive registers, succeed.
5519 if (NumAllocated == NumRegs) {
5520 unsigned RegStart = (i-NumAllocated)+1;
5521 unsigned RegEnd = i+1;
5522 // Mark all of the allocated registers used.
5523 for (unsigned i = RegStart; i != RegEnd; ++i)
5524 Regs.push_back(RegClassRegs[i]);
5526 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5527 OpInfo.ConstraintVT);
5528 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5533 // Otherwise, we couldn't allocate enough registers for this.
5536 /// visitInlineAsm - Handle a call to an InlineAsm object.
5538 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5539 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5541 /// ConstraintOperands - Information about all of the constraints.
5542 SDISelAsmOperandInfoVector ConstraintOperands;
5544 std::set<unsigned> OutputRegs, InputRegs;
5546 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5547 bool hasMemory = false;
5549 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5550 unsigned ResNo = 0; // ResNo - The result number of the next output.
5551 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5552 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5553 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5555 EVT OpVT = MVT::Other;
5557 // Compute the value type for each operand.
5558 switch (OpInfo.Type) {
5559 case InlineAsm::isOutput:
5560 // Indirect outputs just consume an argument.
5561 if (OpInfo.isIndirect) {
5562 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5566 // The return value of the call is this value. As such, there is no
5567 // corresponding argument.
5568 assert(!CS.getType()->isVoidTy() &&
5570 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5571 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5573 assert(ResNo == 0 && "Asm only has one result!");
5574 OpVT = TLI.getValueType(CS.getType());
5578 case InlineAsm::isInput:
5579 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5581 case InlineAsm::isClobber:
5586 // If this is an input or an indirect output, process the call argument.
5587 // BasicBlocks are labels, currently appearing only in asm's.
5588 if (OpInfo.CallOperandVal) {
5589 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5590 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5592 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5595 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5598 OpInfo.ConstraintVT = OpVT;
5600 // Indirect operand accesses access memory.
5601 if (OpInfo.isIndirect)
5604 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5605 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5606 if (CType == TargetLowering::C_Memory) {
5614 SDValue Chain, Flag;
5616 // We won't need to flush pending loads if this asm doesn't touch
5617 // memory and is nonvolatile.
5618 if (hasMemory || IA->hasSideEffects())
5621 Chain = DAG.getRoot();
5623 // Second pass over the constraints: compute which constraint option to use
5624 // and assign registers to constraints that want a specific physreg.
5625 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5626 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5628 // If this is an output operand with a matching input operand, look up the
5629 // matching input. If their types mismatch, e.g. one is an integer, the
5630 // other is floating point, or their sizes are different, flag it as an
5632 if (OpInfo.hasMatchingInput()) {
5633 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5635 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5636 if ((OpInfo.ConstraintVT.isInteger() !=
5637 Input.ConstraintVT.isInteger()) ||
5638 (OpInfo.ConstraintVT.getSizeInBits() !=
5639 Input.ConstraintVT.getSizeInBits())) {
5640 report_fatal_error("Unsupported asm: input constraint"
5641 " with a matching output constraint of"
5642 " incompatible type!");
5644 Input.ConstraintVT = OpInfo.ConstraintVT;
5648 // Compute the constraint code and ConstraintType to use.
5649 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5651 // If this is a memory input, and if the operand is not indirect, do what we
5652 // need to to provide an address for the memory input.
5653 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5654 !OpInfo.isIndirect) {
5655 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5656 "Can only indirectify direct input operands!");
5658 // Memory operands really want the address of the value. If we don't have
5659 // an indirect input, put it in the constpool if we can, otherwise spill
5660 // it to a stack slot.
5662 // If the operand is a float, integer, or vector constant, spill to a
5663 // constant pool entry to get its address.
5664 const Value *OpVal = OpInfo.CallOperandVal;
5665 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5666 isa<ConstantVector>(OpVal)) {
5667 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5668 TLI.getPointerTy());
5670 // Otherwise, create a stack slot and emit a store to it before the
5672 const Type *Ty = OpVal->getType();
5673 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5674 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5675 MachineFunction &MF = DAG.getMachineFunction();
5676 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5677 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5678 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5679 OpInfo.CallOperand, StackSlot,
5680 MachinePointerInfo::getFixedStack(SSFI),
5682 OpInfo.CallOperand = StackSlot;
5685 // There is no longer a Value* corresponding to this operand.
5686 OpInfo.CallOperandVal = 0;
5688 // It is now an indirect operand.
5689 OpInfo.isIndirect = true;
5692 // If this constraint is for a specific register, allocate it before
5694 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5695 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5698 // Second pass - Loop over all of the operands, assigning virtual or physregs
5699 // to register class operands.
5700 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5701 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5703 // C_Register operands have already been allocated, Other/Memory don't need
5705 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5706 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5709 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5710 std::vector<SDValue> AsmNodeOperands;
5711 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5712 AsmNodeOperands.push_back(
5713 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5714 TLI.getPointerTy()));
5716 // If we have a !srcloc metadata node associated with it, we want to attach
5717 // this to the ultimately generated inline asm machineinstr. To do this, we
5718 // pass in the third operand as this (potentially null) inline asm MDNode.
5719 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5720 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5722 // Remember the HasSideEffect and AlignStack bits as operand 3.
5723 unsigned ExtraInfo = 0;
5724 if (IA->hasSideEffects())
5725 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5726 if (IA->isAlignStack())
5727 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5728 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5729 TLI.getPointerTy()));
5731 // Loop over all of the inputs, copying the operand values into the
5732 // appropriate registers and processing the output regs.
5733 RegsForValue RetValRegs;
5735 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5736 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5738 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5739 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5741 switch (OpInfo.Type) {
5742 case InlineAsm::isOutput: {
5743 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5744 OpInfo.ConstraintType != TargetLowering::C_Register) {
5745 // Memory output, or 'other' output (e.g. 'X' constraint).
5746 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5748 // Add information to the INLINEASM node to know about this output.
5749 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5750 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5751 TLI.getPointerTy()));
5752 AsmNodeOperands.push_back(OpInfo.CallOperand);
5756 // Otherwise, this is a register or register class output.
5758 // Copy the output from the appropriate register. Find a register that
5760 if (OpInfo.AssignedRegs.Regs.empty())
5761 report_fatal_error("Couldn't allocate output reg for constraint '" +
5762 Twine(OpInfo.ConstraintCode) + "'!");
5764 // If this is an indirect operand, store through the pointer after the
5766 if (OpInfo.isIndirect) {
5767 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5768 OpInfo.CallOperandVal));
5770 // This is the result value of the call.
5771 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5772 // Concatenate this output onto the outputs list.
5773 RetValRegs.append(OpInfo.AssignedRegs);
5776 // Add information to the INLINEASM node to know that this register is
5778 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5779 InlineAsm::Kind_RegDefEarlyClobber :
5780 InlineAsm::Kind_RegDef,
5787 case InlineAsm::isInput: {
5788 SDValue InOperandVal = OpInfo.CallOperand;
5790 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5791 // If this is required to match an output register we have already set,
5792 // just use its register.
5793 unsigned OperandNo = OpInfo.getMatchedOperand();
5795 // Scan until we find the definition we already emitted of this operand.
5796 // When we find it, create a RegsForValue operand.
5797 unsigned CurOp = InlineAsm::Op_FirstOperand;
5798 for (; OperandNo; --OperandNo) {
5799 // Advance to the next operand.
5801 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5802 assert((InlineAsm::isRegDefKind(OpFlag) ||
5803 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5804 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5805 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5809 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5810 if (InlineAsm::isRegDefKind(OpFlag) ||
5811 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5812 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5813 if (OpInfo.isIndirect) {
5814 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5815 LLVMContext &Ctx = *DAG.getContext();
5816 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5817 " don't know how to handle tied "
5818 "indirect register inputs");
5821 RegsForValue MatchedRegs;
5822 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5823 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5824 MatchedRegs.RegVTs.push_back(RegVT);
5825 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5826 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5828 MatchedRegs.Regs.push_back
5829 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5831 // Use the produced MatchedRegs object to
5832 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5834 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5835 true, OpInfo.getMatchedOperand(),
5836 DAG, AsmNodeOperands);
5840 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5841 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5842 "Unexpected number of operands");
5843 // Add information to the INLINEASM node to know about this input.
5844 // See InlineAsm.h isUseOperandTiedToDef.
5845 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5846 OpInfo.getMatchedOperand());
5847 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5848 TLI.getPointerTy()));
5849 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5853 // Treat indirect 'X' constraint as memory.
5854 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5856 OpInfo.ConstraintType = TargetLowering::C_Memory;
5858 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5859 std::vector<SDValue> Ops;
5860 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5863 report_fatal_error("Invalid operand for inline asm constraint '" +
5864 Twine(OpInfo.ConstraintCode) + "'!");
5866 // Add information to the INLINEASM node to know about this input.
5867 unsigned ResOpType =
5868 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5869 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5870 TLI.getPointerTy()));
5871 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5875 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5876 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5877 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5878 "Memory operands expect pointer values");
5880 // Add information to the INLINEASM node to know about this input.
5881 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5882 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5883 TLI.getPointerTy()));
5884 AsmNodeOperands.push_back(InOperandVal);
5888 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5889 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5890 "Unknown constraint type!");
5891 assert(!OpInfo.isIndirect &&
5892 "Don't know how to handle indirect register inputs yet!");
5894 // Copy the input into the appropriate registers.
5895 if (OpInfo.AssignedRegs.Regs.empty() ||
5896 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5897 report_fatal_error("Couldn't allocate input reg for constraint '" +
5898 Twine(OpInfo.ConstraintCode) + "'!");
5900 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5903 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5904 DAG, AsmNodeOperands);
5907 case InlineAsm::isClobber: {
5908 // Add the clobbered value to the operand list, so that the register
5909 // allocator is aware that the physreg got clobbered.
5910 if (!OpInfo.AssignedRegs.Regs.empty())
5911 OpInfo.AssignedRegs.AddInlineAsmOperands(
5912 InlineAsm::Kind_RegDefEarlyClobber,
5920 // Finish up input operands. Set the input chain and add the flag last.
5921 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5922 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5924 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5925 DAG.getVTList(MVT::Other, MVT::Glue),
5926 &AsmNodeOperands[0], AsmNodeOperands.size());
5927 Flag = Chain.getValue(1);
5929 // If this asm returns a register value, copy the result from that register
5930 // and set it as the value of the call.
5931 if (!RetValRegs.Regs.empty()) {
5932 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5935 // FIXME: Why don't we do this for inline asms with MRVs?
5936 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5937 EVT ResultType = TLI.getValueType(CS.getType());
5939 // If any of the results of the inline asm is a vector, it may have the
5940 // wrong width/num elts. This can happen for register classes that can
5941 // contain multiple different value types. The preg or vreg allocated may
5942 // not have the same VT as was expected. Convert it to the right type
5943 // with bit_convert.
5944 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5945 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5948 } else if (ResultType != Val.getValueType() &&
5949 ResultType.isInteger() && Val.getValueType().isInteger()) {
5950 // If a result value was tied to an input value, the computed result may
5951 // have a wider width than the expected result. Extract the relevant
5953 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5956 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5959 setValue(CS.getInstruction(), Val);
5960 // Don't need to use this as a chain in this case.
5961 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5965 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5967 // Process indirect outputs, first output all of the flagged copies out of
5969 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5970 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5971 const Value *Ptr = IndirectStoresToEmit[i].second;
5972 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5974 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5977 // Emit the non-flagged stores from the physregs.
5978 SmallVector<SDValue, 8> OutChains;
5979 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5980 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5981 StoresToEmit[i].first,
5982 getValue(StoresToEmit[i].second),
5983 MachinePointerInfo(StoresToEmit[i].second),
5985 OutChains.push_back(Val);
5988 if (!OutChains.empty())
5989 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5990 &OutChains[0], OutChains.size());
5995 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5996 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5997 MVT::Other, getRoot(),
5998 getValue(I.getArgOperand(0)),
5999 DAG.getSrcValue(I.getArgOperand(0))));
6002 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6003 const TargetData &TD = *TLI.getTargetData();
6004 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6005 getRoot(), getValue(I.getOperand(0)),
6006 DAG.getSrcValue(I.getOperand(0)),
6007 TD.getABITypeAlignment(I.getType()));
6009 DAG.setRoot(V.getValue(1));
6012 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6013 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6014 MVT::Other, getRoot(),
6015 getValue(I.getArgOperand(0)),
6016 DAG.getSrcValue(I.getArgOperand(0))));
6019 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6020 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6021 MVT::Other, getRoot(),
6022 getValue(I.getArgOperand(0)),
6023 getValue(I.getArgOperand(1)),
6024 DAG.getSrcValue(I.getArgOperand(0)),
6025 DAG.getSrcValue(I.getArgOperand(1))));
6028 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6029 /// implementation, which just calls LowerCall.
6030 /// FIXME: When all targets are
6031 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6032 std::pair<SDValue, SDValue>
6033 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6034 bool RetSExt, bool RetZExt, bool isVarArg,
6035 bool isInreg, unsigned NumFixedArgs,
6036 CallingConv::ID CallConv, bool isTailCall,
6037 bool isReturnValueUsed,
6039 ArgListTy &Args, SelectionDAG &DAG,
6040 DebugLoc dl) const {
6041 // Handle all of the outgoing arguments.
6042 SmallVector<ISD::OutputArg, 32> Outs;
6043 SmallVector<SDValue, 32> OutVals;
6044 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6045 SmallVector<EVT, 4> ValueVTs;
6046 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6047 for (unsigned Value = 0, NumValues = ValueVTs.size();
6048 Value != NumValues; ++Value) {
6049 EVT VT = ValueVTs[Value];
6050 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6051 SDValue Op = SDValue(Args[i].Node.getNode(),
6052 Args[i].Node.getResNo() + Value);
6053 ISD::ArgFlagsTy Flags;
6054 unsigned OriginalAlignment =
6055 getTargetData()->getABITypeAlignment(ArgTy);
6061 if (Args[i].isInReg)
6065 if (Args[i].isByVal) {
6067 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6068 const Type *ElementTy = Ty->getElementType();
6069 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6070 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6071 // For ByVal, alignment should come from FE. BE will guess if this
6072 // info is not there but there are cases it cannot get right.
6073 if (Args[i].Alignment)
6074 FrameAlign = Args[i].Alignment;
6075 Flags.setByValAlign(FrameAlign);
6076 Flags.setByValSize(FrameSize);
6080 Flags.setOrigAlign(OriginalAlignment);
6082 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6083 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6084 SmallVector<SDValue, 4> Parts(NumParts);
6085 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6088 ExtendKind = ISD::SIGN_EXTEND;
6089 else if (Args[i].isZExt)
6090 ExtendKind = ISD::ZERO_EXTEND;
6092 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6093 PartVT, ExtendKind);
6095 for (unsigned j = 0; j != NumParts; ++j) {
6096 // if it isn't first piece, alignment must be 1
6097 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6099 if (NumParts > 1 && j == 0)
6100 MyFlags.Flags.setSplit();
6102 MyFlags.Flags.setOrigAlign(1);
6104 Outs.push_back(MyFlags);
6105 OutVals.push_back(Parts[j]);
6110 // Handle the incoming return values from the call.
6111 SmallVector<ISD::InputArg, 32> Ins;
6112 SmallVector<EVT, 4> RetTys;
6113 ComputeValueVTs(*this, RetTy, RetTys);
6114 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6116 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6117 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6118 for (unsigned i = 0; i != NumRegs; ++i) {
6119 ISD::InputArg MyFlags;
6120 MyFlags.VT = RegisterVT.getSimpleVT();
6121 MyFlags.Used = isReturnValueUsed;
6123 MyFlags.Flags.setSExt();
6125 MyFlags.Flags.setZExt();
6127 MyFlags.Flags.setInReg();
6128 Ins.push_back(MyFlags);
6132 SmallVector<SDValue, 4> InVals;
6133 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6134 Outs, OutVals, Ins, dl, DAG, InVals);
6136 // Verify that the target's LowerCall behaved as expected.
6137 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6138 "LowerCall didn't return a valid chain!");
6139 assert((!isTailCall || InVals.empty()) &&
6140 "LowerCall emitted a return value for a tail call!");
6141 assert((isTailCall || InVals.size() == Ins.size()) &&
6142 "LowerCall didn't emit the correct number of values!");
6144 // For a tail call, the return value is merely live-out and there aren't
6145 // any nodes in the DAG representing it. Return a special value to
6146 // indicate that a tail call has been emitted and no more Instructions
6147 // should be processed in the current block.
6150 return std::make_pair(SDValue(), SDValue());
6153 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6154 assert(InVals[i].getNode() &&
6155 "LowerCall emitted a null value!");
6156 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6157 "LowerCall emitted a value with the wrong type!");
6160 // Collect the legal value parts into potentially illegal values
6161 // that correspond to the original function's return values.
6162 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6164 AssertOp = ISD::AssertSext;
6166 AssertOp = ISD::AssertZext;
6167 SmallVector<SDValue, 4> ReturnValues;
6168 unsigned CurReg = 0;
6169 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6171 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6172 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6174 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6175 NumRegs, RegisterVT, VT,
6180 // For a function returning void, there is no return value. We can't create
6181 // such a node, so we just return a null return value in that case. In
6182 // that case, nothing will actualy look at the value.
6183 if (ReturnValues.empty())
6184 return std::make_pair(SDValue(), Chain);
6186 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6187 DAG.getVTList(&RetTys[0], RetTys.size()),
6188 &ReturnValues[0], ReturnValues.size());
6189 return std::make_pair(Res, Chain);
6192 void TargetLowering::LowerOperationWrapper(SDNode *N,
6193 SmallVectorImpl<SDValue> &Results,
6194 SelectionDAG &DAG) const {
6195 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6197 Results.push_back(Res);
6200 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6201 llvm_unreachable("LowerOperation not implemented for this target!");
6206 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6207 SDValue Op = getNonRegisterValue(V);
6208 assert((Op.getOpcode() != ISD::CopyFromReg ||
6209 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6210 "Copy from a reg to the same reg!");
6211 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6213 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6214 SDValue Chain = DAG.getEntryNode();
6215 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6216 PendingExports.push_back(Chain);
6219 #include "llvm/CodeGen/SelectionDAGISel.h"
6221 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6222 // If this is the entry block, emit arguments.
6223 const Function &F = *LLVMBB->getParent();
6224 SelectionDAG &DAG = SDB->DAG;
6225 DebugLoc dl = SDB->getCurDebugLoc();
6226 const TargetData *TD = TLI.getTargetData();
6227 SmallVector<ISD::InputArg, 16> Ins;
6229 // Check whether the function can return without sret-demotion.
6230 SmallVector<ISD::OutputArg, 4> Outs;
6231 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6234 if (!FuncInfo->CanLowerReturn) {
6235 // Put in an sret pointer parameter before all the other parameters.
6236 SmallVector<EVT, 1> ValueVTs;
6237 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6239 // NOTE: Assuming that a pointer will never break down to more than one VT
6241 ISD::ArgFlagsTy Flags;
6243 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6244 ISD::InputArg RetArg(Flags, RegisterVT, true);
6245 Ins.push_back(RetArg);
6248 // Set up the incoming argument description vector.
6250 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6251 I != E; ++I, ++Idx) {
6252 SmallVector<EVT, 4> ValueVTs;
6253 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6254 bool isArgValueUsed = !I->use_empty();
6255 for (unsigned Value = 0, NumValues = ValueVTs.size();
6256 Value != NumValues; ++Value) {
6257 EVT VT = ValueVTs[Value];
6258 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6259 ISD::ArgFlagsTy Flags;
6260 unsigned OriginalAlignment =
6261 TD->getABITypeAlignment(ArgTy);
6263 if (F.paramHasAttr(Idx, Attribute::ZExt))
6265 if (F.paramHasAttr(Idx, Attribute::SExt))
6267 if (F.paramHasAttr(Idx, Attribute::InReg))
6269 if (F.paramHasAttr(Idx, Attribute::StructRet))
6271 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6273 const PointerType *Ty = cast<PointerType>(I->getType());
6274 const Type *ElementTy = Ty->getElementType();
6275 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6276 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6277 // For ByVal, alignment should be passed from FE. BE will guess if
6278 // this info is not there but there are cases it cannot get right.
6279 if (F.getParamAlignment(Idx))
6280 FrameAlign = F.getParamAlignment(Idx);
6281 Flags.setByValAlign(FrameAlign);
6282 Flags.setByValSize(FrameSize);
6284 if (F.paramHasAttr(Idx, Attribute::Nest))
6286 Flags.setOrigAlign(OriginalAlignment);
6288 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6289 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6290 for (unsigned i = 0; i != NumRegs; ++i) {
6291 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6292 if (NumRegs > 1 && i == 0)
6293 MyFlags.Flags.setSplit();
6294 // if it isn't first piece, alignment must be 1
6296 MyFlags.Flags.setOrigAlign(1);
6297 Ins.push_back(MyFlags);
6302 // Call the target to set up the argument values.
6303 SmallVector<SDValue, 8> InVals;
6304 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6308 // Verify that the target's LowerFormalArguments behaved as expected.
6309 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6310 "LowerFormalArguments didn't return a valid chain!");
6311 assert(InVals.size() == Ins.size() &&
6312 "LowerFormalArguments didn't emit the correct number of values!");
6314 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6315 assert(InVals[i].getNode() &&
6316 "LowerFormalArguments emitted a null value!");
6317 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6318 "LowerFormalArguments emitted a value with the wrong type!");
6322 // Update the DAG with the new chain value resulting from argument lowering.
6323 DAG.setRoot(NewRoot);
6325 // Set up the argument values.
6328 if (!FuncInfo->CanLowerReturn) {
6329 // Create a virtual register for the sret pointer, and put in a copy
6330 // from the sret argument into it.
6331 SmallVector<EVT, 1> ValueVTs;
6332 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6333 EVT VT = ValueVTs[0];
6334 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6335 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6336 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6337 RegVT, VT, AssertOp);
6339 MachineFunction& MF = SDB->DAG.getMachineFunction();
6340 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6341 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6342 FuncInfo->DemoteRegister = SRetReg;
6343 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6345 DAG.setRoot(NewRoot);
6347 // i indexes lowered arguments. Bump it past the hidden sret argument.
6348 // Idx indexes LLVM arguments. Don't touch it.
6352 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6354 SmallVector<SDValue, 4> ArgValues;
6355 SmallVector<EVT, 4> ValueVTs;
6356 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6357 unsigned NumValues = ValueVTs.size();
6359 // If this argument is unused then remember its value. It is used to generate
6360 // debugging information.
6361 if (I->use_empty() && NumValues)
6362 SDB->setUnusedArgValue(I, InVals[i]);
6364 for (unsigned Value = 0; Value != NumValues; ++Value) {
6365 EVT VT = ValueVTs[Value];
6366 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6367 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6369 if (!I->use_empty()) {
6370 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6371 if (F.paramHasAttr(Idx, Attribute::SExt))
6372 AssertOp = ISD::AssertSext;
6373 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6374 AssertOp = ISD::AssertZext;
6376 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6377 NumParts, PartVT, VT,
6384 // Note down frame index for byval arguments.
6385 if (I->hasByValAttr() && !ArgValues.empty())
6386 if (FrameIndexSDNode *FI =
6387 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6388 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6390 if (!I->use_empty()) {
6392 if (!ArgValues.empty())
6393 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6394 SDB->getCurDebugLoc());
6395 SDB->setValue(I, Res);
6397 // If this argument is live outside of the entry block, insert a copy from
6398 // whereever we got it to the vreg that other BB's will reference it as.
6399 SDB->CopyToExportRegsIfNeeded(I);
6403 assert(i == InVals.size() && "Argument register count mismatch!");
6405 // Finally, if the target has anything special to do, allow it to do so.
6406 // FIXME: this should insert code into the DAG!
6407 EmitFunctionEntryCode();
6410 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6411 /// ensure constants are generated when needed. Remember the virtual registers
6412 /// that need to be added to the Machine PHI nodes as input. We cannot just
6413 /// directly add them, because expansion might result in multiple MBB's for one
6414 /// BB. As such, the start of the BB might correspond to a different MBB than
6418 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6419 const TerminatorInst *TI = LLVMBB->getTerminator();
6421 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6423 // Check successor nodes' PHI nodes that expect a constant to be available
6425 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6426 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6427 if (!isa<PHINode>(SuccBB->begin())) continue;
6428 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6430 // If this terminator has multiple identical successors (common for
6431 // switches), only handle each succ once.
6432 if (!SuccsHandled.insert(SuccMBB)) continue;
6434 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6436 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6437 // nodes and Machine PHI nodes, but the incoming operands have not been
6439 for (BasicBlock::const_iterator I = SuccBB->begin();
6440 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6441 // Ignore dead phi's.
6442 if (PN->use_empty()) continue;
6445 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6447 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6448 unsigned &RegOut = ConstantsOut[C];
6450 RegOut = FuncInfo.CreateRegs(C->getType());
6451 CopyValueToVirtualRegister(C, RegOut);
6455 DenseMap<const Value *, unsigned>::iterator I =
6456 FuncInfo.ValueMap.find(PHIOp);
6457 if (I != FuncInfo.ValueMap.end())
6460 assert(isa<AllocaInst>(PHIOp) &&
6461 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6462 "Didn't codegen value into a register!??");
6463 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6464 CopyValueToVirtualRegister(PHIOp, Reg);
6468 // Remember that this register needs to added to the machine PHI node as
6469 // the input for this MBB.
6470 SmallVector<EVT, 4> ValueVTs;
6471 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6472 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6473 EVT VT = ValueVTs[vti];
6474 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6475 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6476 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6477 Reg += NumRegisters;
6481 ConstantsOut.clear();