1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
83 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
84 cl::desc("Enable fast-math-flags for DAG nodes"));
86 // Limit the width of DAG chains. This is important in general to prevent
87 // DAG-based analysis from blowing up. For example, alias analysis and
88 // load clustering may not complete in reasonable time. It is difficult to
89 // recognize and avoid this situation within each individual analysis, and
90 // future analyses are likely to have the same behavior. Limiting DAG width is
91 // the safe approach and will be especially important with global DAGs.
93 // MaxParallelChains default is arbitrarily high to avoid affecting
94 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
95 // sequence over this should have been converted to llvm.memcpy by the
96 // frontend. It easy to induce this behavior with .ll code such as:
97 // %buffer = alloca [4096 x i8]
98 // %data = load [4096 x i8]* %argPtr
99 // store [4096 x i8] %data, [4096 x i8]* %buffer
100 static const unsigned MaxParallelChains = 64;
102 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts, unsigned NumParts,
104 MVT PartVT, EVT ValueVT, const Value *V);
106 /// getCopyFromParts - Create a value that contains the specified legal parts
107 /// combined into the value they represent. If the parts combine to a type
108 /// larger then ValueVT then AssertOp can be used to specify whether the extra
109 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
110 /// (ISD::AssertSext).
111 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
112 const SDValue *Parts,
113 unsigned NumParts, MVT PartVT, EVT ValueVT,
115 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
116 if (ValueVT.isVector())
117 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
120 assert(NumParts > 0 && "No parts to assemble!");
121 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
122 SDValue Val = Parts[0];
125 // Assemble the value from multiple parts.
126 if (ValueVT.isInteger()) {
127 unsigned PartBits = PartVT.getSizeInBits();
128 unsigned ValueBits = ValueVT.getSizeInBits();
130 // Assemble the power of 2 part.
131 unsigned RoundParts = NumParts & (NumParts - 1) ?
132 1 << Log2_32(NumParts) : NumParts;
133 unsigned RoundBits = PartBits * RoundParts;
134 EVT RoundVT = RoundBits == ValueBits ?
135 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
138 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
140 if (RoundParts > 2) {
141 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
143 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
144 RoundParts / 2, PartVT, HalfVT, V);
146 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
147 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
150 if (DAG.getDataLayout().isBigEndian())
153 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
155 if (RoundParts < NumParts) {
156 // Assemble the trailing non-power-of-2 part.
157 unsigned OddParts = NumParts - RoundParts;
158 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
159 Hi = getCopyFromParts(DAG, DL,
160 Parts + RoundParts, OddParts, PartVT, OddVT, V);
162 // Combine the round and odd parts.
164 if (DAG.getDataLayout().isBigEndian())
166 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
167 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
169 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
170 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
171 TLI.getPointerTy(DAG.getDataLayout())));
172 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
173 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
175 } else if (PartVT.isFloatingPoint()) {
176 // FP split into multiple FP parts (for ppcf128)
177 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
180 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
181 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
182 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
184 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
186 // FP split into integer parts (soft fp)
187 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
188 !PartVT.isVector() && "Unexpected split");
189 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
190 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
194 // There is now one part, held in Val. Correct it to match ValueVT.
195 EVT PartEVT = Val.getValueType();
197 if (PartEVT == ValueVT)
200 if (PartEVT.isInteger() && ValueVT.isInteger()) {
201 if (ValueVT.bitsLT(PartEVT)) {
202 // For a truncate, see if we have any information to
203 // indicate whether the truncated bits will always be
204 // zero or sign-extension.
205 if (AssertOp != ISD::DELETED_NODE)
206 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
207 DAG.getValueType(ValueVT));
208 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
210 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
214 // FP_ROUND's are always exact here.
215 if (ValueVT.bitsLT(Val.getValueType()))
217 ISD::FP_ROUND, DL, ValueVT, Val,
218 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
220 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
223 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
224 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
226 llvm_unreachable("Unknown mismatch!");
229 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
230 const Twine &ErrMsg) {
231 const Instruction *I = dyn_cast_or_null<Instruction>(V);
233 return Ctx.emitError(ErrMsg);
235 const char *AsmError = ", possible invalid constraint for vector type";
236 if (const CallInst *CI = dyn_cast<CallInst>(I))
237 if (isa<InlineAsm>(CI->getCalledValue()))
238 return Ctx.emitError(I, ErrMsg + AsmError);
240 return Ctx.emitError(I, ErrMsg);
243 /// getCopyFromPartsVector - Create a value that contains the specified legal
244 /// parts combined into the value they represent. If the parts combine to a
245 /// type larger then ValueVT then AssertOp can be used to specify whether the
246 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
247 /// ValueVT (ISD::AssertSext).
248 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
249 const SDValue *Parts, unsigned NumParts,
250 MVT PartVT, EVT ValueVT, const Value *V) {
251 assert(ValueVT.isVector() && "Not a vector value");
252 assert(NumParts > 0 && "No parts to assemble!");
253 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
254 SDValue Val = Parts[0];
256 // Handle a multi-element vector.
260 unsigned NumIntermediates;
262 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
263 NumIntermediates, RegisterVT);
264 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
265 NumParts = NumRegs; // Silence a compiler warning.
266 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
267 assert(RegisterVT.getSizeInBits() ==
268 Parts[0].getSimpleValueType().getSizeInBits() &&
269 "Part type sizes don't match!");
271 // Assemble the parts into intermediate operands.
272 SmallVector<SDValue, 8> Ops(NumIntermediates);
273 if (NumIntermediates == NumParts) {
274 // If the register was not expanded, truncate or copy the value,
276 for (unsigned i = 0; i != NumParts; ++i)
277 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
278 PartVT, IntermediateVT, V);
279 } else if (NumParts > 0) {
280 // If the intermediate type was expanded, build the intermediate
281 // operands from the parts.
282 assert(NumParts % NumIntermediates == 0 &&
283 "Must expand into a divisible number of parts!");
284 unsigned Factor = NumParts / NumIntermediates;
285 for (unsigned i = 0; i != NumIntermediates; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
287 PartVT, IntermediateVT, V);
290 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
291 // intermediate operands.
292 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
297 // There is now one part, held in Val. Correct it to match ValueVT.
298 EVT PartEVT = Val.getValueType();
300 if (PartEVT == ValueVT)
303 if (PartEVT.isVector()) {
304 // If the element type of the source/dest vectors are the same, but the
305 // parts vector has more elements than the value vector, then we have a
306 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
308 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
309 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
310 "Cannot narrow, it would be a lossy transformation");
312 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
313 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
316 // Vector/Vector bitcast.
317 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
318 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
320 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
321 "Cannot handle this kind of promotion");
322 // Promoted vector extract
323 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
327 // Trivial bitcast if the types are the same size and the destination
328 // vector type is legal.
329 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
330 TLI.isTypeLegal(ValueVT))
331 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
333 // Handle cases such as i8 -> <1 x i1>
334 if (ValueVT.getVectorNumElements() != 1) {
335 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
336 "non-trivial scalar-to-vector conversion");
337 return DAG.getUNDEF(ValueVT);
340 if (ValueVT.getVectorNumElements() == 1 &&
341 ValueVT.getVectorElementType() != PartEVT)
342 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
344 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
347 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V);
351 /// getCopyToParts - Create a series of nodes that contain the specified value
352 /// split into legal parts. If the parts contain more bits than Val, then, for
353 /// integers, ExtendKind can be used to specify how to generate the extra bits.
354 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
355 SDValue Val, SDValue *Parts, unsigned NumParts,
356 MVT PartVT, const Value *V,
357 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
358 EVT ValueVT = Val.getValueType();
360 // Handle the vector case separately.
361 if (ValueVT.isVector())
362 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
364 unsigned PartBits = PartVT.getSizeInBits();
365 unsigned OrigNumParts = NumParts;
366 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
367 "Copying to an illegal type!");
372 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
373 EVT PartEVT = PartVT;
374 if (PartEVT == ValueVT) {
375 assert(NumParts == 1 && "No-op copy with multiple parts!");
380 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
381 // If the parts cover more bits than the value has, promote the value.
382 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
383 assert(NumParts == 1 && "Do not know what to promote to!");
384 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
386 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
387 ValueVT.isInteger() &&
388 "Unknown mismatch!");
389 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
390 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
391 if (PartVT == MVT::x86mmx)
392 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
394 } else if (PartBits == ValueVT.getSizeInBits()) {
395 // Different types of the same size.
396 assert(NumParts == 1 && PartEVT != ValueVT);
397 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
398 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
399 // If the parts cover less bits than value has, truncate the value.
400 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
401 ValueVT.isInteger() &&
402 "Unknown mismatch!");
403 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
404 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
405 if (PartVT == MVT::x86mmx)
406 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 // The value may have changed - recompute ValueVT.
410 ValueVT = Val.getValueType();
411 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
412 "Failed to tile the value with PartVT!");
415 if (PartEVT != ValueVT)
416 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
417 "scalar-to-vector conversion failed");
423 // Expand the value into multiple parts.
424 if (NumParts & (NumParts - 1)) {
425 // The number of parts is not a power of 2. Split off and copy the tail.
426 assert(PartVT.isInteger() && ValueVT.isInteger() &&
427 "Do not know what to expand to!");
428 unsigned RoundParts = 1 << Log2_32(NumParts);
429 unsigned RoundBits = RoundParts * PartBits;
430 unsigned OddParts = NumParts - RoundParts;
431 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
432 DAG.getIntPtrConstant(RoundBits, DL));
433 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
435 if (DAG.getDataLayout().isBigEndian())
436 // The odd parts were reversed by getCopyToParts - unreverse them.
437 std::reverse(Parts + RoundParts, Parts + NumParts);
439 NumParts = RoundParts;
440 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
441 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
444 // The number of parts is a power of 2. Repeatedly bisect the value using
446 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
447 EVT::getIntegerVT(*DAG.getContext(),
448 ValueVT.getSizeInBits()),
451 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
452 for (unsigned i = 0; i < NumParts; i += StepSize) {
453 unsigned ThisBits = StepSize * PartBits / 2;
454 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
455 SDValue &Part0 = Parts[i];
456 SDValue &Part1 = Parts[i+StepSize/2];
458 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
459 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
460 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
461 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
463 if (ThisBits == PartBits && ThisVT != PartVT) {
464 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
465 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
470 if (DAG.getDataLayout().isBigEndian())
471 std::reverse(Parts, Parts + OrigNumParts);
475 /// getCopyToPartsVector - Create a series of nodes that contain the specified
476 /// value split into legal parts.
477 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
478 SDValue Val, SDValue *Parts, unsigned NumParts,
479 MVT PartVT, const Value *V) {
480 EVT ValueVT = Val.getValueType();
481 assert(ValueVT.isVector() && "Not a vector");
482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
485 EVT PartEVT = PartVT;
486 if (PartEVT == ValueVT) {
488 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
489 // Bitconvert vector->vector case.
490 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
491 } else if (PartVT.isVector() &&
492 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
493 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
494 EVT ElementVT = PartVT.getVectorElementType();
495 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
497 SmallVector<SDValue, 16> Ops;
498 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
499 Ops.push_back(DAG.getNode(
500 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
501 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
503 for (unsigned i = ValueVT.getVectorNumElements(),
504 e = PartVT.getVectorNumElements(); i != e; ++i)
505 Ops.push_back(DAG.getUNDEF(ElementVT));
507 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
509 // FIXME: Use CONCAT for 2x -> 4x.
511 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
512 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
513 } else if (PartVT.isVector() &&
514 PartEVT.getVectorElementType().bitsGE(
515 ValueVT.getVectorElementType()) &&
516 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
518 // Promoted vector extract
519 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
521 // Vector -> scalar conversion.
522 assert(ValueVT.getVectorNumElements() == 1 &&
523 "Only trivial vector-to-scalar conversions should get here!");
525 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
526 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
528 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
553 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
554 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
555 TLI.getVectorIdxTy(DAG.getDataLayout())));
557 Ops[i] = DAG.getNode(
558 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
559 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
580 RegsForValue::RegsForValue() {}
582 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
587 const DataLayout &DL, unsigned Reg, Type *Ty) {
588 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
590 for (EVT ValueVT : ValueVTs) {
591 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
592 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
593 for (unsigned i = 0; i != NumRegs; ++i)
594 Regs.push_back(Reg + i);
595 RegVTs.push_back(RegisterVT);
600 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
601 /// this value and returns the result as a ValueVT value. This uses
602 /// Chain/Flag as the input and updates them for the output Chain/Flag.
603 /// If the Flag pointer is NULL, no flag is used.
604 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
605 FunctionLoweringInfo &FuncInfo,
607 SDValue &Chain, SDValue *Flag,
608 const Value *V) const {
609 // A Value with type {} or [0 x %t] needs no registers.
610 if (ValueVTs.empty())
613 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
615 // Assemble the legal parts into the final values.
616 SmallVector<SDValue, 4> Values(ValueVTs.size());
617 SmallVector<SDValue, 8> Parts;
618 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 // Copy the legal parts from the registers.
620 EVT ValueVT = ValueVTs[Value];
621 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
622 MVT RegisterVT = RegVTs[Value];
624 Parts.resize(NumRegs);
625 for (unsigned i = 0; i != NumRegs; ++i) {
628 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
630 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
631 *Flag = P.getValue(2);
634 Chain = P.getValue(1);
637 // If the source register was virtual and if we know something about it,
638 // add an assert node.
639 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
640 !RegisterVT.isInteger() || RegisterVT.isVector())
643 const FunctionLoweringInfo::LiveOutInfo *LOI =
644 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
648 unsigned RegSize = RegisterVT.getSizeInBits();
649 unsigned NumSignBits = LOI->NumSignBits;
650 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
652 if (NumZeroBits == RegSize) {
653 // The current value is a zero.
654 // Explicitly express that as it would be easier for
655 // optimizations to kick in.
656 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
660 // FIXME: We capture more information than the dag can represent. For
661 // now, just use the tightest assertzext/assertsext possible.
663 EVT FromVT(MVT::Other);
664 if (NumSignBits == RegSize)
665 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
666 else if (NumZeroBits >= RegSize-1)
667 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
668 else if (NumSignBits > RegSize-8)
669 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
670 else if (NumZeroBits >= RegSize-8)
671 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
672 else if (NumSignBits > RegSize-16)
673 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
674 else if (NumZeroBits >= RegSize-16)
675 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
676 else if (NumSignBits > RegSize-32)
677 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
678 else if (NumZeroBits >= RegSize-32)
679 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
683 // Add an assertion node.
684 assert(FromVT != MVT::Other);
685 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
686 RegisterVT, P, DAG.getValueType(FromVT));
689 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
690 NumRegs, RegisterVT, ValueVT, V);
695 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
698 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
699 /// specified value into the registers specified by this object. This uses
700 /// Chain/Flag as the input and updates them for the output Chain/Flag.
701 /// If the Flag pointer is NULL, no flag is used.
702 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
703 SDValue &Chain, SDValue *Flag, const Value *V,
704 ISD::NodeType PreferredExtendType) const {
705 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
706 ISD::NodeType ExtendKind = PreferredExtendType;
708 // Get the list of the values's legal parts.
709 unsigned NumRegs = Regs.size();
710 SmallVector<SDValue, 8> Parts(NumRegs);
711 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
712 EVT ValueVT = ValueVTs[Value];
713 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
714 MVT RegisterVT = RegVTs[Value];
716 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
717 ExtendKind = ISD::ZERO_EXTEND;
719 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
720 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
724 // Copy the parts into the registers.
725 SmallVector<SDValue, 8> Chains(NumRegs);
726 for (unsigned i = 0; i != NumRegs; ++i) {
729 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
731 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
732 *Flag = Part.getValue(1);
735 Chains[i] = Part.getValue(0);
738 if (NumRegs == 1 || Flag)
739 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
740 // flagged to it. That is the CopyToReg nodes and the user are considered
741 // a single scheduling unit. If we create a TokenFactor and return it as
742 // chain, then the TokenFactor is both a predecessor (operand) of the
743 // user as well as a successor (the TF operands are flagged to the user).
744 // c1, f1 = CopyToReg
745 // c2, f2 = CopyToReg
746 // c3 = TokenFactor c1, c2
749 Chain = Chains[NumRegs-1];
751 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
754 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
755 /// operand list. This adds the code marker and includes the number of
756 /// values added into it.
757 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
758 unsigned MatchingIdx, SDLoc dl,
760 std::vector<SDValue> &Ops) const {
761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
763 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
765 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
766 else if (!Regs.empty() &&
767 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
768 // Put the register class of the virtual registers in the flag word. That
769 // way, later passes can recompute register class constraints for inline
770 // assembly as well as normal instructions.
771 // Don't do this for tied operands that can use the regclass information
773 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
774 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
775 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
778 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
781 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
782 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
783 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
784 MVT RegisterVT = RegVTs[Value];
785 for (unsigned i = 0; i != NumRegs; ++i) {
786 assert(Reg < Regs.size() && "Mismatch in # registers expected");
787 unsigned TheReg = Regs[Reg++];
788 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
790 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
791 // If we clobbered the stack pointer, MFI should know about it.
792 assert(DAG.getMachineFunction().getFrameInfo()->
793 hasOpaqueSPAdjustment());
799 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
800 const TargetLibraryInfo *li) {
804 DL = &DAG.getDataLayout();
805 Context = DAG.getContext();
806 LPadToCallSiteMap.clear();
809 /// clear - Clear out the current SelectionDAG and the associated
810 /// state and prepare this SelectionDAGBuilder object to be used
811 /// for a new block. This doesn't clear out information about
812 /// additional blocks that are needed to complete switch lowering
813 /// or PHI node updating; that information is cleared out as it is
815 void SelectionDAGBuilder::clear() {
817 UnusedArgNodeMap.clear();
818 PendingLoads.clear();
819 PendingExports.clear();
822 SDNodeOrder = LowestSDNodeOrder;
823 StatepointLowering.clear();
826 /// clearDanglingDebugInfo - Clear the dangling debug information
827 /// map. This function is separated from the clear so that debug
828 /// information that is dangling in a basic block can be properly
829 /// resolved in a different basic block. This allows the
830 /// SelectionDAG to resolve dangling debug information attached
832 void SelectionDAGBuilder::clearDanglingDebugInfo() {
833 DanglingDebugInfoMap.clear();
836 /// getRoot - Return the current virtual root of the Selection DAG,
837 /// flushing any PendingLoad items. This must be done before emitting
838 /// a store or any other node that may need to be ordered after any
839 /// prior load instructions.
841 SDValue SelectionDAGBuilder::getRoot() {
842 if (PendingLoads.empty())
843 return DAG.getRoot();
845 if (PendingLoads.size() == 1) {
846 SDValue Root = PendingLoads[0];
848 PendingLoads.clear();
852 // Otherwise, we have to make a token factor node.
853 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
855 PendingLoads.clear();
860 /// getControlRoot - Similar to getRoot, but instead of flushing all the
861 /// PendingLoad items, flush all the PendingExports items. It is necessary
862 /// to do this before emitting a terminator instruction.
864 SDValue SelectionDAGBuilder::getControlRoot() {
865 SDValue Root = DAG.getRoot();
867 if (PendingExports.empty())
870 // Turn all of the CopyToReg chains into one factored node.
871 if (Root.getOpcode() != ISD::EntryToken) {
872 unsigned i = 0, e = PendingExports.size();
873 for (; i != e; ++i) {
874 assert(PendingExports[i].getNode()->getNumOperands() > 1);
875 if (PendingExports[i].getNode()->getOperand(0) == Root)
876 break; // Don't add the root if we already indirectly depend on it.
880 PendingExports.push_back(Root);
883 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
885 PendingExports.clear();
890 void SelectionDAGBuilder::visit(const Instruction &I) {
891 // Set up outgoing PHI node register values before emitting the terminator.
892 if (isa<TerminatorInst>(&I))
893 HandlePHINodesInSuccessorBlocks(I.getParent());
899 visit(I.getOpcode(), I);
901 if (!isa<TerminatorInst>(&I) && !HasTailCall)
902 CopyToExportRegsIfNeeded(&I);
907 void SelectionDAGBuilder::visitPHI(const PHINode &) {
908 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
911 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
912 // Note: this doesn't use InstVisitor, because it has to work with
913 // ConstantExpr's in addition to instructions.
915 default: llvm_unreachable("Unknown instruction type encountered!");
916 // Build the switch statement using the Instruction.def file.
917 #define HANDLE_INST(NUM, OPCODE, CLASS) \
918 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
919 #include "llvm/IR/Instruction.def"
923 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
924 // generate the debug data structures now that we've seen its definition.
925 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
927 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
929 const DbgValueInst *DI = DDI.getDI();
930 DebugLoc dl = DDI.getdl();
931 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
932 DILocalVariable *Variable = DI->getVariable();
933 DIExpression *Expr = DI->getExpression();
934 assert(Variable->isValidLocationForIntrinsic(dl) &&
935 "Expected inlined-at fields to agree");
936 uint64_t Offset = DI->getOffset();
937 // A dbg.value for an alloca is always indirect.
938 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
941 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
943 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
944 IsIndirect, Offset, dl, DbgSDNodeOrder);
945 DAG.AddDbgValue(SDV, Val.getNode(), false);
948 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
949 DanglingDebugInfoMap[V] = DanglingDebugInfo();
953 /// getCopyFromRegs - If there was virtual register allocated for the value V
954 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
955 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
956 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
959 if (It != FuncInfo.ValueMap.end()) {
960 unsigned InReg = It->second;
961 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
962 DAG.getDataLayout(), InReg, Ty);
963 SDValue Chain = DAG.getEntryNode();
964 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
965 resolveDanglingDebugInfo(V, Result);
971 /// getValue - Return an SDValue for the given Value.
972 SDValue SelectionDAGBuilder::getValue(const Value *V) {
973 // If we already have an SDValue for this value, use it. It's important
974 // to do this first, so that we don't create a CopyFromReg if we already
975 // have a regular SDValue.
976 SDValue &N = NodeMap[V];
977 if (N.getNode()) return N;
979 // If there's a virtual register allocated and initialized for this
981 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
982 if (copyFromReg.getNode()) {
986 // Otherwise create a new SDValue and remember it.
987 SDValue Val = getValueImpl(V);
989 resolveDanglingDebugInfo(V, Val);
993 // Return true if SDValue exists for the given Value
994 bool SelectionDAGBuilder::findValue(const Value *V) const {
995 return (NodeMap.find(V) != NodeMap.end()) ||
996 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
999 /// getNonRegisterValue - Return an SDValue for the given Value, but
1000 /// don't look in FuncInfo.ValueMap for a virtual register.
1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1002 // If we already have an SDValue for this value, use it.
1003 SDValue &N = NodeMap[V];
1005 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1006 // Remove the debug location from the node as the node is about to be used
1007 // in a location which may differ from the original debug location. This
1008 // is relevant to Constant and ConstantFP nodes because they can appear
1009 // as constant expressions inside PHI nodes.
1010 N->setDebugLoc(DebugLoc());
1015 // Otherwise create a new SDValue and remember it.
1016 SDValue Val = getValueImpl(V);
1018 resolveDanglingDebugInfo(V, Val);
1022 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1023 /// Create an SDValue for the given value.
1024 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1025 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1027 if (const Constant *C = dyn_cast<Constant>(V)) {
1028 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1030 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1031 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1033 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1034 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1036 if (isa<ConstantPointerNull>(C)) {
1037 unsigned AS = V->getType()->getPointerAddressSpace();
1038 return DAG.getConstant(0, getCurSDLoc(),
1039 TLI.getPointerTy(DAG.getDataLayout(), AS));
1042 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1043 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1045 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1046 return DAG.getUNDEF(VT);
1048 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1049 visit(CE->getOpcode(), *CE);
1050 SDValue N1 = NodeMap[V];
1051 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1055 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1056 SmallVector<SDValue, 4> Constants;
1057 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1059 SDNode *Val = getValue(*OI).getNode();
1060 // If the operand is an empty aggregate, there are no values.
1062 // Add each leaf value from the operand to the Constants list
1063 // to form a flattened list of all the values.
1064 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1065 Constants.push_back(SDValue(Val, i));
1068 return DAG.getMergeValues(Constants, getCurSDLoc());
1071 if (const ConstantDataSequential *CDS =
1072 dyn_cast<ConstantDataSequential>(C)) {
1073 SmallVector<SDValue, 4> Ops;
1074 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1075 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1076 // Add each leaf value from the operand to the Constants list
1077 // to form a flattened list of all the values.
1078 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1079 Ops.push_back(SDValue(Val, i));
1082 if (isa<ArrayType>(CDS->getType()))
1083 return DAG.getMergeValues(Ops, getCurSDLoc());
1084 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1088 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1089 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1090 "Unknown struct or array constant!");
1092 SmallVector<EVT, 4> ValueVTs;
1093 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1094 unsigned NumElts = ValueVTs.size();
1096 return SDValue(); // empty struct
1097 SmallVector<SDValue, 4> Constants(NumElts);
1098 for (unsigned i = 0; i != NumElts; ++i) {
1099 EVT EltVT = ValueVTs[i];
1100 if (isa<UndefValue>(C))
1101 Constants[i] = DAG.getUNDEF(EltVT);
1102 else if (EltVT.isFloatingPoint())
1103 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1105 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1108 return DAG.getMergeValues(Constants, getCurSDLoc());
1111 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1112 return DAG.getBlockAddress(BA, VT);
1114 VectorType *VecTy = cast<VectorType>(V->getType());
1115 unsigned NumElements = VecTy->getNumElements();
1117 // Now that we know the number and type of the elements, get that number of
1118 // elements into the Ops array based on what kind of constant it is.
1119 SmallVector<SDValue, 16> Ops;
1120 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1121 for (unsigned i = 0; i != NumElements; ++i)
1122 Ops.push_back(getValue(CV->getOperand(i)));
1124 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1126 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1129 if (EltVT.isFloatingPoint())
1130 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1132 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1133 Ops.assign(NumElements, Op);
1136 // Create a BUILD_VECTOR node.
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1140 // If this is a static alloca, generate it as the frameindex instead of
1142 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1143 DenseMap<const AllocaInst*, int>::iterator SI =
1144 FuncInfo.StaticAllocaMap.find(AI);
1145 if (SI != FuncInfo.StaticAllocaMap.end())
1146 return DAG.getFrameIndex(SI->second,
1147 TLI.getPointerTy(DAG.getDataLayout()));
1150 // If this is an instruction which fast-isel has deferred, select it now.
1151 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1152 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1153 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1155 SDValue Chain = DAG.getEntryNode();
1156 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1159 llvm_unreachable("Can't get register for value!");
1162 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1163 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1164 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1165 bool IsSEH = isAsynchronousEHPersonality(Pers);
1166 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1167 // In MSVC C++, catchblocks are funclets and need prologues.
1169 CatchPadMBB->setIsEHFuncletEntry();
1171 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1173 // Update machine-CFG edge.
1174 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1176 // CatchPads in SEH are not funclets, they are merely markers which indicate
1177 // where to insert register restoration code.
1179 DAG.setRoot(DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1180 getControlRoot(), DAG.getBasicBlock(NormalDestMBB),
1181 DAG.getBasicBlock(FuncInfo.MF->begin())));
1185 // If this is not a fall-through branch or optimizations are switched off,
1187 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1188 TM.getOptLevel() == CodeGenOpt::None)
1189 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1191 DAG.getBasicBlock(NormalDestMBB)));
1194 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1195 // Update machine-CFG edge.
1196 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1197 FuncInfo.MBB->addSuccessor(TargetMBB);
1199 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1200 bool IsSEH = isAsynchronousEHPersonality(Pers);
1202 // If this is not a fall-through branch or optimizations are switched off,
1204 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1205 TM.getOptLevel() == CodeGenOpt::None)
1206 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1207 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1211 // Figure out the funclet membership for the catchret's successor.
1212 // This will be used by the FuncletLayout pass to determine how to order the
1214 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1215 WinEHFuncInfo &EHInfo =
1216 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1217 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1218 assert(SuccessorColor && "No parent funclet for catchret!");
1219 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1220 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1222 // Create the terminator node.
1223 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1224 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1225 DAG.getBasicBlock(SuccessorColorMBB));
1229 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1230 llvm_unreachable("should never codegen catchendpads");
1233 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1234 // Don't emit any special code for the cleanuppad instruction. It just marks
1235 // the start of a funclet.
1236 FuncInfo.MBB->setIsEHFuncletEntry();
1237 FuncInfo.MBB->setIsCleanupFuncletEntry();
1240 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1241 /// many places it could ultimately go. In the IR, we have a single unwind
1242 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1243 /// This function skips over imaginary basic blocks that hold catchpad,
1244 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1245 /// basic block destinations.
1247 findUnwindDestinations(FunctionLoweringInfo &FuncInfo,
1248 const BasicBlock *EHPadBB,
1249 SmallVectorImpl<MachineBasicBlock *> &UnwindDests) {
1250 EHPersonality Personality =
1251 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1252 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1253 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1255 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1256 if (isa<LandingPadInst>(Pad)) {
1257 // Stop on landingpads. They are not funclets.
1258 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1260 } else if (isa<CleanupPadInst>(Pad)) {
1261 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1263 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1264 UnwindDests.back()->setIsEHFuncletEntry();
1266 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1267 // Add the catchpad handler to the possible destinations.
1268 UnwindDests.push_back(FuncInfo.MBBMap[EHPadBB]);
1269 // In MSVC C++, catchblocks are funclets and need prologues.
1270 if (IsMSVCCXX || IsCoreCLR)
1271 UnwindDests.back()->setIsEHFuncletEntry();
1272 EHPadBB = CPI->getUnwindDest();
1273 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad)) {
1274 EHPadBB = CEPI->getUnwindDest();
1275 } else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad)) {
1276 EHPadBB = CEPI->getUnwindDest();
1281 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1282 // Update successor info.
1283 // FIXME: The weights for catchpads will be wrong.
1284 SmallVector<MachineBasicBlock *, 1> UnwindDests;
1285 findUnwindDestinations(FuncInfo, I.getUnwindDest(), UnwindDests);
1286 for (MachineBasicBlock *UnwindDest : UnwindDests) {
1287 UnwindDest->setIsEHPad();
1288 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest);
1291 // Create the terminator node.
1293 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1297 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1298 report_fatal_error("visitCleanupEndPad not yet implemented!");
1301 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1302 report_fatal_error("visitTerminatePad not yet implemented!");
1305 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1307 auto &DL = DAG.getDataLayout();
1308 SDValue Chain = getControlRoot();
1309 SmallVector<ISD::OutputArg, 8> Outs;
1310 SmallVector<SDValue, 8> OutVals;
1312 if (!FuncInfo.CanLowerReturn) {
1313 unsigned DemoteReg = FuncInfo.DemoteRegister;
1314 const Function *F = I.getParent()->getParent();
1316 // Emit a store of the return value through the virtual register.
1317 // Leave Outs empty so that LowerReturn won't try to load return
1318 // registers the usual way.
1319 SmallVector<EVT, 1> PtrValueVTs;
1320 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1323 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1324 SDValue RetOp = getValue(I.getOperand(0));
1326 SmallVector<EVT, 4> ValueVTs;
1327 SmallVector<uint64_t, 4> Offsets;
1328 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1329 unsigned NumValues = ValueVTs.size();
1331 SmallVector<SDValue, 4> Chains(NumValues);
1332 for (unsigned i = 0; i != NumValues; ++i) {
1333 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1334 RetPtr.getValueType(), RetPtr,
1335 DAG.getIntPtrConstant(Offsets[i],
1338 DAG.getStore(Chain, getCurSDLoc(),
1339 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1340 // FIXME: better loc info would be nice.
1341 Add, MachinePointerInfo(), false, false, 0);
1344 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1345 MVT::Other, Chains);
1346 } else if (I.getNumOperands() != 0) {
1347 SmallVector<EVT, 4> ValueVTs;
1348 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1349 unsigned NumValues = ValueVTs.size();
1351 SDValue RetOp = getValue(I.getOperand(0));
1353 const Function *F = I.getParent()->getParent();
1355 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1356 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1358 ExtendKind = ISD::SIGN_EXTEND;
1359 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1361 ExtendKind = ISD::ZERO_EXTEND;
1363 LLVMContext &Context = F->getContext();
1364 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1367 for (unsigned j = 0; j != NumValues; ++j) {
1368 EVT VT = ValueVTs[j];
1370 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1371 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1373 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1374 MVT PartVT = TLI.getRegisterType(Context, VT);
1375 SmallVector<SDValue, 4> Parts(NumParts);
1376 getCopyToParts(DAG, getCurSDLoc(),
1377 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1378 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1380 // 'inreg' on function refers to return value
1381 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1385 // Propagate extension type if any
1386 if (ExtendKind == ISD::SIGN_EXTEND)
1388 else if (ExtendKind == ISD::ZERO_EXTEND)
1391 for (unsigned i = 0; i < NumParts; ++i) {
1392 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1393 VT, /*isfixed=*/true, 0, 0));
1394 OutVals.push_back(Parts[i]);
1400 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1401 CallingConv::ID CallConv =
1402 DAG.getMachineFunction().getFunction()->getCallingConv();
1403 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1404 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1406 // Verify that the target's LowerReturn behaved as expected.
1407 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1408 "LowerReturn didn't return a valid chain!");
1410 // Update the DAG with the new chain value resulting from return lowering.
1414 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1415 /// created for it, emit nodes to copy the value into the virtual
1417 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1419 if (V->getType()->isEmptyTy())
1422 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1423 if (VMI != FuncInfo.ValueMap.end()) {
1424 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1425 CopyValueToVirtualRegister(V, VMI->second);
1429 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1430 /// the current basic block, add it to ValueMap now so that we'll get a
1432 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1433 // No need to export constants.
1434 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1436 // Already exported?
1437 if (FuncInfo.isExportedInst(V)) return;
1439 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1440 CopyValueToVirtualRegister(V, Reg);
1443 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1444 const BasicBlock *FromBB) {
1445 // The operands of the setcc have to be in this block. We don't know
1446 // how to export them from some other block.
1447 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1448 // Can export from current BB.
1449 if (VI->getParent() == FromBB)
1452 // Is already exported, noop.
1453 return FuncInfo.isExportedInst(V);
1456 // If this is an argument, we can export it if the BB is the entry block or
1457 // if it is already exported.
1458 if (isa<Argument>(V)) {
1459 if (FromBB == &FromBB->getParent()->getEntryBlock())
1462 // Otherwise, can only export this if it is already exported.
1463 return FuncInfo.isExportedInst(V);
1466 // Otherwise, constants can always be exported.
1470 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1471 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1472 const MachineBasicBlock *Dst) const {
1473 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1476 const BasicBlock *SrcBB = Src->getBasicBlock();
1477 const BasicBlock *DstBB = Dst->getBasicBlock();
1478 return BPI->getEdgeWeight(SrcBB, DstBB);
1481 void SelectionDAGBuilder::
1482 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1483 uint32_t Weight /* = 0 */) {
1485 Weight = getEdgeWeight(Src, Dst);
1486 Src->addSuccessor(Dst, Weight);
1490 static bool InBlock(const Value *V, const BasicBlock *BB) {
1491 if (const Instruction *I = dyn_cast<Instruction>(V))
1492 return I->getParent() == BB;
1496 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1497 /// This function emits a branch and is used at the leaves of an OR or an
1498 /// AND operator tree.
1501 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1502 MachineBasicBlock *TBB,
1503 MachineBasicBlock *FBB,
1504 MachineBasicBlock *CurBB,
1505 MachineBasicBlock *SwitchBB,
1508 const BasicBlock *BB = CurBB->getBasicBlock();
1510 // If the leaf of the tree is a comparison, merge the condition into
1512 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1513 // The operands of the cmp have to be in this block. We don't know
1514 // how to export them from some other block. If this is the first block
1515 // of the sequence, no exporting is needed.
1516 if (CurBB == SwitchBB ||
1517 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1518 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1519 ISD::CondCode Condition;
1520 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1521 Condition = getICmpCondCode(IC->getPredicate());
1523 const FCmpInst *FC = cast<FCmpInst>(Cond);
1524 Condition = getFCmpCondCode(FC->getPredicate());
1525 if (TM.Options.NoNaNsFPMath)
1526 Condition = getFCmpCodeWithoutNaN(Condition);
1529 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1530 TBB, FBB, CurBB, TWeight, FWeight);
1531 SwitchCases.push_back(CB);
1536 // Create a CaseBlock record representing this branch.
1537 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1538 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1539 SwitchCases.push_back(CB);
1542 /// Scale down both weights to fit into uint32_t.
1543 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1544 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1545 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1546 NewTrue = NewTrue / Scale;
1547 NewFalse = NewFalse / Scale;
1550 /// FindMergedConditions - If Cond is an expression like
1551 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1552 MachineBasicBlock *TBB,
1553 MachineBasicBlock *FBB,
1554 MachineBasicBlock *CurBB,
1555 MachineBasicBlock *SwitchBB,
1556 Instruction::BinaryOps Opc,
1559 // If this node is not part of the or/and tree, emit it as a branch.
1560 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1561 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1562 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1563 BOp->getParent() != CurBB->getBasicBlock() ||
1564 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1565 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1566 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1571 // Create TmpBB after CurBB.
1572 MachineFunction::iterator BBI = CurBB;
1573 MachineFunction &MF = DAG.getMachineFunction();
1574 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1575 CurBB->getParent()->insert(++BBI, TmpBB);
1577 if (Opc == Instruction::Or) {
1578 // Codegen X | Y as:
1587 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1588 // The requirement is that
1589 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1590 // = TrueProb for original BB.
1591 // Assuming the original weights are A and B, one choice is to set BB1's
1592 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1594 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1595 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1596 // TmpBB, but the math is more complicated.
1598 uint64_t NewTrueWeight = TWeight;
1599 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1600 ScaleWeights(NewTrueWeight, NewFalseWeight);
1601 // Emit the LHS condition.
1602 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1603 NewTrueWeight, NewFalseWeight);
1605 NewTrueWeight = TWeight;
1606 NewFalseWeight = 2 * (uint64_t)FWeight;
1607 ScaleWeights(NewTrueWeight, NewFalseWeight);
1608 // Emit the RHS condition into TmpBB.
1609 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1610 NewTrueWeight, NewFalseWeight);
1612 assert(Opc == Instruction::And && "Unknown merge op!");
1613 // Codegen X & Y as:
1621 // This requires creation of TmpBB after CurBB.
1623 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1624 // The requirement is that
1625 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1626 // = FalseProb for original BB.
1627 // Assuming the original weights are A and B, one choice is to set BB1's
1628 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1630 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1632 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1633 uint64_t NewFalseWeight = FWeight;
1634 ScaleWeights(NewTrueWeight, NewFalseWeight);
1635 // Emit the LHS condition.
1636 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1637 NewTrueWeight, NewFalseWeight);
1639 NewTrueWeight = 2 * (uint64_t)TWeight;
1640 NewFalseWeight = FWeight;
1641 ScaleWeights(NewTrueWeight, NewFalseWeight);
1642 // Emit the RHS condition into TmpBB.
1643 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1644 NewTrueWeight, NewFalseWeight);
1648 /// If the set of cases should be emitted as a series of branches, return true.
1649 /// If we should emit this as a bunch of and/or'd together conditions, return
1652 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1653 if (Cases.size() != 2) return true;
1655 // If this is two comparisons of the same values or'd or and'd together, they
1656 // will get folded into a single comparison, so don't emit two blocks.
1657 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1658 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1659 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1660 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1664 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1665 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1666 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1667 Cases[0].CC == Cases[1].CC &&
1668 isa<Constant>(Cases[0].CmpRHS) &&
1669 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1670 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1672 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1679 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1680 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1682 // Update machine-CFG edges.
1683 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1685 if (I.isUnconditional()) {
1686 // Update machine-CFG edges.
1687 BrMBB->addSuccessor(Succ0MBB);
1689 // If this is not a fall-through branch or optimizations are switched off,
1691 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1692 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1693 MVT::Other, getControlRoot(),
1694 DAG.getBasicBlock(Succ0MBB)));
1699 // If this condition is one of the special cases we handle, do special stuff
1701 const Value *CondVal = I.getCondition();
1702 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1704 // If this is a series of conditions that are or'd or and'd together, emit
1705 // this as a sequence of branches instead of setcc's with and/or operations.
1706 // As long as jumps are not expensive, this should improve performance.
1707 // For example, instead of something like:
1720 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1721 Instruction::BinaryOps Opcode = BOp->getOpcode();
1722 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1723 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1724 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1725 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1726 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1727 getEdgeWeight(BrMBB, Succ1MBB));
1728 // If the compares in later blocks need to use values not currently
1729 // exported from this block, export them now. This block should always
1730 // be the first entry.
1731 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1733 // Allow some cases to be rejected.
1734 if (ShouldEmitAsBranches(SwitchCases)) {
1735 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1736 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1737 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1740 // Emit the branch for this block.
1741 visitSwitchCase(SwitchCases[0], BrMBB);
1742 SwitchCases.erase(SwitchCases.begin());
1746 // Okay, we decided not to do this, remove any inserted MBB's and clear
1748 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1749 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1751 SwitchCases.clear();
1755 // Create a CaseBlock record representing this branch.
1756 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1757 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1759 // Use visitSwitchCase to actually insert the fast branch sequence for this
1761 visitSwitchCase(CB, BrMBB);
1764 /// visitSwitchCase - Emits the necessary code to represent a single node in
1765 /// the binary search tree resulting from lowering a switch instruction.
1766 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1767 MachineBasicBlock *SwitchBB) {
1769 SDValue CondLHS = getValue(CB.CmpLHS);
1770 SDLoc dl = getCurSDLoc();
1772 // Build the setcc now.
1774 // Fold "(X == true)" to X and "(X == false)" to !X to
1775 // handle common cases produced by branch lowering.
1776 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1777 CB.CC == ISD::SETEQ)
1779 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1780 CB.CC == ISD::SETEQ) {
1781 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1782 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1784 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1786 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1788 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1789 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1791 SDValue CmpOp = getValue(CB.CmpMHS);
1792 EVT VT = CmpOp.getValueType();
1794 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1795 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1798 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1799 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1800 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1801 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1805 // Update successor info
1806 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1807 // TrueBB and FalseBB are always different unless the incoming IR is
1808 // degenerate. This only happens when running llc on weird IR.
1809 if (CB.TrueBB != CB.FalseBB)
1810 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1812 // If the lhs block is the next block, invert the condition so that we can
1813 // fall through to the lhs instead of the rhs block.
1814 if (CB.TrueBB == NextBlock(SwitchBB)) {
1815 std::swap(CB.TrueBB, CB.FalseBB);
1816 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1817 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1820 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1821 MVT::Other, getControlRoot(), Cond,
1822 DAG.getBasicBlock(CB.TrueBB));
1824 // Insert the false branch. Do this even if it's a fall through branch,
1825 // this makes it easier to do DAG optimizations which require inverting
1826 // the branch condition.
1827 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1828 DAG.getBasicBlock(CB.FalseBB));
1830 DAG.setRoot(BrCond);
1833 /// visitJumpTable - Emit JumpTable node in the current MBB
1834 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1835 // Emit the code for the jump table
1836 assert(JT.Reg != -1U && "Should lower JT Header first!");
1837 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1838 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1840 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1841 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1842 MVT::Other, Index.getValue(1),
1844 DAG.setRoot(BrJumpTable);
1847 /// visitJumpTableHeader - This function emits necessary code to produce index
1848 /// in the JumpTable from switch case.
1849 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1850 JumpTableHeader &JTH,
1851 MachineBasicBlock *SwitchBB) {
1852 SDLoc dl = getCurSDLoc();
1854 // Subtract the lowest switch case value from the value being switched on and
1855 // conditional branch to default mbb if the result is greater than the
1856 // difference between smallest and largest cases.
1857 SDValue SwitchOp = getValue(JTH.SValue);
1858 EVT VT = SwitchOp.getValueType();
1859 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1860 DAG.getConstant(JTH.First, dl, VT));
1862 // The SDNode we just created, which holds the value being switched on minus
1863 // the smallest case value, needs to be copied to a virtual register so it
1864 // can be used as an index into the jump table in a subsequent basic block.
1865 // This value may be smaller or larger than the target's pointer type, and
1866 // therefore require extension or truncating.
1867 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1868 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1870 unsigned JumpTableReg =
1871 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1872 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1873 JumpTableReg, SwitchOp);
1874 JT.Reg = JumpTableReg;
1876 // Emit the range check for the jump table, and branch to the default block
1877 // for the switch statement if the value being switched on exceeds the largest
1878 // case in the switch.
1879 SDValue CMP = DAG.getSetCC(
1880 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1881 Sub.getValueType()),
1882 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1884 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1885 MVT::Other, CopyTo, CMP,
1886 DAG.getBasicBlock(JT.Default));
1888 // Avoid emitting unnecessary branches to the next block.
1889 if (JT.MBB != NextBlock(SwitchBB))
1890 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1891 DAG.getBasicBlock(JT.MBB));
1893 DAG.setRoot(BrCond);
1896 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1897 /// tail spliced into a stack protector check success bb.
1899 /// For a high level explanation of how this fits into the stack protector
1900 /// generation see the comment on the declaration of class
1901 /// StackProtectorDescriptor.
1902 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1903 MachineBasicBlock *ParentBB) {
1905 // First create the loads to the guard/stack slot for the comparison.
1906 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1907 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1909 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1910 int FI = MFI->getStackProtectorIndex();
1912 const Value *IRGuard = SPD.getGuard();
1913 SDValue GuardPtr = getValue(IRGuard);
1914 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1916 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1919 SDLoc dl = getCurSDLoc();
1921 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1922 // guard value from the virtual register holding the value. Otherwise, emit a
1923 // volatile load to retrieve the stack guard value.
1924 unsigned GuardReg = SPD.getGuardReg();
1926 if (GuardReg && TLI.useLoadStackGuardNode())
1927 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1930 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1931 GuardPtr, MachinePointerInfo(IRGuard, 0),
1932 true, false, false, Align);
1934 SDValue StackSlot = DAG.getLoad(
1935 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1936 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1937 false, false, Align);
1939 // Perform the comparison via a subtract/getsetcc.
1940 EVT VT = Guard.getValueType();
1941 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1943 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1945 Sub.getValueType()),
1946 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1948 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1949 // branch to failure MBB.
1950 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1951 MVT::Other, StackSlot.getOperand(0),
1952 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1953 // Otherwise branch to success MBB.
1954 SDValue Br = DAG.getNode(ISD::BR, dl,
1956 DAG.getBasicBlock(SPD.getSuccessMBB()));
1961 /// Codegen the failure basic block for a stack protector check.
1963 /// A failure stack protector machine basic block consists simply of a call to
1964 /// __stack_chk_fail().
1966 /// For a high level explanation of how this fits into the stack protector
1967 /// generation see the comment on the declaration of class
1968 /// StackProtectorDescriptor.
1970 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1971 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1973 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1974 nullptr, 0, false, getCurSDLoc(), false, false).second;
1978 /// visitBitTestHeader - This function emits necessary code to produce value
1979 /// suitable for "bit tests"
1980 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1981 MachineBasicBlock *SwitchBB) {
1982 SDLoc dl = getCurSDLoc();
1984 // Subtract the minimum value
1985 SDValue SwitchOp = getValue(B.SValue);
1986 EVT VT = SwitchOp.getValueType();
1987 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1988 DAG.getConstant(B.First, dl, VT));
1991 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1992 SDValue RangeCmp = DAG.getSetCC(
1993 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1994 Sub.getValueType()),
1995 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
1997 // Determine the type of the test operands.
1998 bool UsePtrType = false;
1999 if (!TLI.isTypeLegal(VT))
2002 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2003 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2004 // Switch table case range are encoded into series of masks.
2005 // Just use pointer type, it's guaranteed to fit.
2011 VT = TLI.getPointerTy(DAG.getDataLayout());
2012 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2015 B.RegVT = VT.getSimpleVT();
2016 B.Reg = FuncInfo.CreateReg(B.RegVT);
2017 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2019 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2021 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2022 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2024 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2025 MVT::Other, CopyTo, RangeCmp,
2026 DAG.getBasicBlock(B.Default));
2028 // Avoid emitting unnecessary branches to the next block.
2029 if (MBB != NextBlock(SwitchBB))
2030 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2031 DAG.getBasicBlock(MBB));
2033 DAG.setRoot(BrRange);
2036 /// visitBitTestCase - this function produces one "bit test"
2037 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2038 MachineBasicBlock* NextMBB,
2039 uint32_t BranchWeightToNext,
2042 MachineBasicBlock *SwitchBB) {
2043 SDLoc dl = getCurSDLoc();
2045 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2047 unsigned PopCount = countPopulation(B.Mask);
2048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2049 if (PopCount == 1) {
2050 // Testing for a single bit; just compare the shift count with what it
2051 // would need to be to shift a 1 bit in that position.
2053 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2054 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2056 } else if (PopCount == BB.Range) {
2057 // There is only one zero bit in the range, test for it directly.
2059 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2060 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2063 // Make desired shift
2064 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2065 DAG.getConstant(1, dl, VT), ShiftOp);
2067 // Emit bit tests and jumps
2068 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2069 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2071 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2072 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2075 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2076 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2077 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2078 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2080 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2081 MVT::Other, getControlRoot(),
2082 Cmp, DAG.getBasicBlock(B.TargetBB));
2084 // Avoid emitting unnecessary branches to the next block.
2085 if (NextMBB != NextBlock(SwitchBB))
2086 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2087 DAG.getBasicBlock(NextMBB));
2092 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2093 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2095 // Retrieve successors. Look through artificial IR level blocks like catchpads
2096 // and catchendpads for successors.
2097 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2098 const BasicBlock *EHPadBB = I.getSuccessor(1);
2100 const Value *Callee(I.getCalledValue());
2101 const Function *Fn = dyn_cast<Function>(Callee);
2102 if (isa<InlineAsm>(Callee))
2104 else if (Fn && Fn->isIntrinsic()) {
2105 switch (Fn->getIntrinsicID()) {
2107 llvm_unreachable("Cannot invoke this intrinsic");
2108 case Intrinsic::donothing:
2109 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2111 case Intrinsic::experimental_patchpoint_void:
2112 case Intrinsic::experimental_patchpoint_i64:
2113 visitPatchpoint(&I, EHPadBB);
2115 case Intrinsic::experimental_gc_statepoint:
2116 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2120 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2122 // If the value of the invoke is used outside of its defining block, make it
2123 // available as a virtual register.
2124 // We already took care of the exported value for the statepoint instruction
2125 // during call to the LowerStatepoint.
2126 if (!isStatepoint(I)) {
2127 CopyToExportRegsIfNeeded(&I);
2130 SmallVector<MachineBasicBlock *, 1> UnwindDests;
2131 findUnwindDestinations(FuncInfo, EHPadBB, UnwindDests);
2133 // Update successor info.
2134 // FIXME: The weights for catchpads will be wrong.
2135 addSuccessorWithWeight(InvokeMBB, Return);
2136 for (MachineBasicBlock *UnwindDest : UnwindDests) {
2137 UnwindDest->setIsEHPad();
2138 addSuccessorWithWeight(InvokeMBB, UnwindDest);
2141 // Drop into normal successor.
2142 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2143 MVT::Other, getControlRoot(),
2144 DAG.getBasicBlock(Return)));
2147 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2148 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2151 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2152 assert(FuncInfo.MBB->isEHPad() &&
2153 "Call to landingpad not in landing pad!");
2155 MachineBasicBlock *MBB = FuncInfo.MBB;
2156 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2157 AddLandingPadInfo(LP, MMI, MBB);
2159 // If there aren't registers to copy the values into (e.g., during SjLj
2160 // exceptions), then don't bother to create these DAG nodes.
2161 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2162 if (TLI.getExceptionPointerRegister() == 0 &&
2163 TLI.getExceptionSelectorRegister() == 0)
2166 SmallVector<EVT, 2> ValueVTs;
2167 SDLoc dl = getCurSDLoc();
2168 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2169 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2171 // Get the two live-in registers as SDValues. The physregs have already been
2172 // copied into virtual registers.
2174 if (FuncInfo.ExceptionPointerVirtReg) {
2175 Ops[0] = DAG.getZExtOrTrunc(
2176 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2177 FuncInfo.ExceptionPointerVirtReg,
2178 TLI.getPointerTy(DAG.getDataLayout())),
2181 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2183 Ops[1] = DAG.getZExtOrTrunc(
2184 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2185 FuncInfo.ExceptionSelectorVirtReg,
2186 TLI.getPointerTy(DAG.getDataLayout())),
2190 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2191 DAG.getVTList(ValueVTs), Ops);
2195 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2197 for (const CaseCluster &CC : Clusters)
2198 assert(CC.Low == CC.High && "Input clusters must be single-case");
2201 std::sort(Clusters.begin(), Clusters.end(),
2202 [](const CaseCluster &a, const CaseCluster &b) {
2203 return a.Low->getValue().slt(b.Low->getValue());
2206 // Merge adjacent clusters with the same destination.
2207 const unsigned N = Clusters.size();
2208 unsigned DstIndex = 0;
2209 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2210 CaseCluster &CC = Clusters[SrcIndex];
2211 const ConstantInt *CaseVal = CC.Low;
2212 MachineBasicBlock *Succ = CC.MBB;
2214 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2215 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2216 // If this case has the same successor and is a neighbour, merge it into
2217 // the previous cluster.
2218 Clusters[DstIndex - 1].High = CaseVal;
2219 Clusters[DstIndex - 1].Weight += CC.Weight;
2220 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2222 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2223 sizeof(Clusters[SrcIndex]));
2226 Clusters.resize(DstIndex);
2229 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2230 MachineBasicBlock *Last) {
2232 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2233 if (JTCases[i].first.HeaderBB == First)
2234 JTCases[i].first.HeaderBB = Last;
2236 // Update BitTestCases.
2237 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2238 if (BitTestCases[i].Parent == First)
2239 BitTestCases[i].Parent = Last;
2242 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2243 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2245 // Update machine-CFG edges with unique successors.
2246 SmallSet<BasicBlock*, 32> Done;
2247 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2248 BasicBlock *BB = I.getSuccessor(i);
2249 bool Inserted = Done.insert(BB).second;
2253 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2254 addSuccessorWithWeight(IndirectBrMBB, Succ);
2257 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2258 MVT::Other, getControlRoot(),
2259 getValue(I.getAddress())));
2262 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2263 if (DAG.getTarget().Options.TrapUnreachable)
2265 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2268 void SelectionDAGBuilder::visitFSub(const User &I) {
2269 // -0.0 - X --> fneg
2270 Type *Ty = I.getType();
2271 if (isa<Constant>(I.getOperand(0)) &&
2272 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2273 SDValue Op2 = getValue(I.getOperand(1));
2274 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2275 Op2.getValueType(), Op2));
2279 visitBinary(I, ISD::FSUB);
2282 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2283 SDValue Op1 = getValue(I.getOperand(0));
2284 SDValue Op2 = getValue(I.getOperand(1));
2291 if (const OverflowingBinaryOperator *OFBinOp =
2292 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2293 nuw = OFBinOp->hasNoUnsignedWrap();
2294 nsw = OFBinOp->hasNoSignedWrap();
2296 if (const PossiblyExactOperator *ExactOp =
2297 dyn_cast<const PossiblyExactOperator>(&I))
2298 exact = ExactOp->isExact();
2299 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2300 FMF = FPOp->getFastMathFlags();
2303 Flags.setExact(exact);
2304 Flags.setNoSignedWrap(nsw);
2305 Flags.setNoUnsignedWrap(nuw);
2306 if (EnableFMFInDAG) {
2307 Flags.setAllowReciprocal(FMF.allowReciprocal());
2308 Flags.setNoInfs(FMF.noInfs());
2309 Flags.setNoNaNs(FMF.noNaNs());
2310 Flags.setNoSignedZeros(FMF.noSignedZeros());
2311 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2313 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2315 setValue(&I, BinNodeValue);
2318 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2319 SDValue Op1 = getValue(I.getOperand(0));
2320 SDValue Op2 = getValue(I.getOperand(1));
2322 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2323 Op2.getValueType(), DAG.getDataLayout());
2325 // Coerce the shift amount to the right type if we can.
2326 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2327 unsigned ShiftSize = ShiftTy.getSizeInBits();
2328 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2329 SDLoc DL = getCurSDLoc();
2331 // If the operand is smaller than the shift count type, promote it.
2332 if (ShiftSize > Op2Size)
2333 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2335 // If the operand is larger than the shift count type but the shift
2336 // count type has enough bits to represent any shift value, truncate
2337 // it now. This is a common case and it exposes the truncate to
2338 // optimization early.
2339 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2340 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2341 // Otherwise we'll need to temporarily settle for some other convenient
2342 // type. Type legalization will make adjustments once the shiftee is split.
2344 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2351 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2353 if (const OverflowingBinaryOperator *OFBinOp =
2354 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2355 nuw = OFBinOp->hasNoUnsignedWrap();
2356 nsw = OFBinOp->hasNoSignedWrap();
2358 if (const PossiblyExactOperator *ExactOp =
2359 dyn_cast<const PossiblyExactOperator>(&I))
2360 exact = ExactOp->isExact();
2363 Flags.setExact(exact);
2364 Flags.setNoSignedWrap(nsw);
2365 Flags.setNoUnsignedWrap(nuw);
2366 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2371 void SelectionDAGBuilder::visitSDiv(const User &I) {
2372 SDValue Op1 = getValue(I.getOperand(0));
2373 SDValue Op2 = getValue(I.getOperand(1));
2376 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2377 cast<PossiblyExactOperator>(&I)->isExact());
2378 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2382 void SelectionDAGBuilder::visitICmp(const User &I) {
2383 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2384 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2385 predicate = IC->getPredicate();
2386 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2387 predicate = ICmpInst::Predicate(IC->getPredicate());
2388 SDValue Op1 = getValue(I.getOperand(0));
2389 SDValue Op2 = getValue(I.getOperand(1));
2390 ISD::CondCode Opcode = getICmpCondCode(predicate);
2392 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2394 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2397 void SelectionDAGBuilder::visitFCmp(const User &I) {
2398 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2399 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2400 predicate = FC->getPredicate();
2401 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2402 predicate = FCmpInst::Predicate(FC->getPredicate());
2403 SDValue Op1 = getValue(I.getOperand(0));
2404 SDValue Op2 = getValue(I.getOperand(1));
2405 ISD::CondCode Condition = getFCmpCondCode(predicate);
2407 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2408 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2409 // further optimization, but currently FMF is only applicable to binary nodes.
2410 if (TM.Options.NoNaNsFPMath)
2411 Condition = getFCmpCodeWithoutNaN(Condition);
2412 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2414 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2417 void SelectionDAGBuilder::visitSelect(const User &I) {
2418 SmallVector<EVT, 4> ValueVTs;
2419 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2421 unsigned NumValues = ValueVTs.size();
2422 if (NumValues == 0) return;
2424 SmallVector<SDValue, 4> Values(NumValues);
2425 SDValue Cond = getValue(I.getOperand(0));
2426 SDValue LHSVal = getValue(I.getOperand(1));
2427 SDValue RHSVal = getValue(I.getOperand(2));
2428 auto BaseOps = {Cond};
2429 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2430 ISD::VSELECT : ISD::SELECT;
2432 // Min/max matching is only viable if all output VTs are the same.
2433 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2434 EVT VT = ValueVTs[0];
2435 LLVMContext &Ctx = *DAG.getContext();
2436 auto &TLI = DAG.getTargetLoweringInfo();
2437 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2438 VT = TLI.getTypeToTransformTo(Ctx, VT);
2441 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2442 ISD::NodeType Opc = ISD::DELETED_NODE;
2443 switch (SPR.Flavor) {
2444 case SPF_UMAX: Opc = ISD::UMAX; break;
2445 case SPF_UMIN: Opc = ISD::UMIN; break;
2446 case SPF_SMAX: Opc = ISD::SMAX; break;
2447 case SPF_SMIN: Opc = ISD::SMIN; break;
2449 switch (SPR.NaNBehavior) {
2450 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2451 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2452 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2453 case SPNB_RETURNS_ANY:
2454 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2460 switch (SPR.NaNBehavior) {
2461 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2462 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2463 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2464 case SPNB_RETURNS_ANY:
2465 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2473 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2474 // If the underlying comparison instruction is used by any other instruction,
2475 // the consumed instructions won't be destroyed, so it is not profitable
2476 // to convert to a min/max.
2477 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2479 LHSVal = getValue(LHS);
2480 RHSVal = getValue(RHS);
2485 for (unsigned i = 0; i != NumValues; ++i) {
2486 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2487 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2488 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2489 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2490 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2494 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2495 DAG.getVTList(ValueVTs), Values));
2498 void SelectionDAGBuilder::visitTrunc(const User &I) {
2499 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2500 SDValue N = getValue(I.getOperand(0));
2501 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2503 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2506 void SelectionDAGBuilder::visitZExt(const User &I) {
2507 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2508 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2509 SDValue N = getValue(I.getOperand(0));
2510 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2512 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2515 void SelectionDAGBuilder::visitSExt(const User &I) {
2516 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2517 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2518 SDValue N = getValue(I.getOperand(0));
2519 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2521 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2524 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2525 // FPTrunc is never a no-op cast, no need to check
2526 SDValue N = getValue(I.getOperand(0));
2527 SDLoc dl = getCurSDLoc();
2528 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2529 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2530 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2531 DAG.getTargetConstant(
2532 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2535 void SelectionDAGBuilder::visitFPExt(const User &I) {
2536 // FPExt is never a no-op cast, no need to check
2537 SDValue N = getValue(I.getOperand(0));
2538 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2540 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2543 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2544 // FPToUI is never a no-op cast, no need to check
2545 SDValue N = getValue(I.getOperand(0));
2546 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2548 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2551 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2552 // FPToSI is never a no-op cast, no need to check
2553 SDValue N = getValue(I.getOperand(0));
2554 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2556 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2559 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2560 // UIToFP is never a no-op cast, no need to check
2561 SDValue N = getValue(I.getOperand(0));
2562 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2564 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2567 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2568 // SIToFP is never a no-op cast, no need to check
2569 SDValue N = getValue(I.getOperand(0));
2570 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2572 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2575 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2576 // What to do depends on the size of the integer and the size of the pointer.
2577 // We can either truncate, zero extend, or no-op, accordingly.
2578 SDValue N = getValue(I.getOperand(0));
2579 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2581 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2584 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2585 // What to do depends on the size of the integer and the size of the pointer.
2586 // We can either truncate, zero extend, or no-op, accordingly.
2587 SDValue N = getValue(I.getOperand(0));
2588 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2590 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2593 void SelectionDAGBuilder::visitBitCast(const User &I) {
2594 SDValue N = getValue(I.getOperand(0));
2595 SDLoc dl = getCurSDLoc();
2596 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2599 // BitCast assures us that source and destination are the same size so this is
2600 // either a BITCAST or a no-op.
2601 if (DestVT != N.getValueType())
2602 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2603 DestVT, N)); // convert types.
2604 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2605 // might fold any kind of constant expression to an integer constant and that
2606 // is not what we are looking for. Only regcognize a bitcast of a genuine
2607 // constant integer as an opaque constant.
2608 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2609 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2612 setValue(&I, N); // noop cast.
2615 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2616 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2617 const Value *SV = I.getOperand(0);
2618 SDValue N = getValue(SV);
2619 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2621 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2622 unsigned DestAS = I.getType()->getPointerAddressSpace();
2624 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2625 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2630 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2631 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2632 SDValue InVec = getValue(I.getOperand(0));
2633 SDValue InVal = getValue(I.getOperand(1));
2634 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2635 TLI.getVectorIdxTy(DAG.getDataLayout()));
2636 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2637 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2638 InVec, InVal, InIdx));
2641 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2642 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2643 SDValue InVec = getValue(I.getOperand(0));
2644 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2645 TLI.getVectorIdxTy(DAG.getDataLayout()));
2646 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2647 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2651 // Utility for visitShuffleVector - Return true if every element in Mask,
2652 // beginning from position Pos and ending in Pos+Size, falls within the
2653 // specified sequential range [L, L+Pos). or is undef.
2654 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2655 unsigned Pos, unsigned Size, int Low) {
2656 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2657 if (Mask[i] >= 0 && Mask[i] != Low)
2662 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2663 SDValue Src1 = getValue(I.getOperand(0));
2664 SDValue Src2 = getValue(I.getOperand(1));
2666 SmallVector<int, 8> Mask;
2667 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2668 unsigned MaskNumElts = Mask.size();
2670 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2671 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2672 EVT SrcVT = Src1.getValueType();
2673 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2675 if (SrcNumElts == MaskNumElts) {
2676 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2681 // Normalize the shuffle vector since mask and vector length don't match.
2682 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2683 // Mask is longer than the source vectors and is a multiple of the source
2684 // vectors. We can use concatenate vector to make the mask and vectors
2686 if (SrcNumElts*2 == MaskNumElts) {
2687 // First check for Src1 in low and Src2 in high
2688 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2689 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2690 // The shuffle is concatenating two vectors together.
2691 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2695 // Then check for Src2 in low and Src1 in high
2696 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2697 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2698 // The shuffle is concatenating two vectors together.
2699 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2705 // Pad both vectors with undefs to make them the same length as the mask.
2706 unsigned NumConcat = MaskNumElts / SrcNumElts;
2707 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2708 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2709 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2711 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2712 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2716 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2717 getCurSDLoc(), VT, MOps1);
2718 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2719 getCurSDLoc(), VT, MOps2);
2721 // Readjust mask for new input vector length.
2722 SmallVector<int, 8> MappedOps;
2723 for (unsigned i = 0; i != MaskNumElts; ++i) {
2725 if (Idx >= (int)SrcNumElts)
2726 Idx -= SrcNumElts - MaskNumElts;
2727 MappedOps.push_back(Idx);
2730 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2735 if (SrcNumElts > MaskNumElts) {
2736 // Analyze the access pattern of the vector to see if we can extract
2737 // two subvectors and do the shuffle. The analysis is done by calculating
2738 // the range of elements the mask access on both vectors.
2739 int MinRange[2] = { static_cast<int>(SrcNumElts),
2740 static_cast<int>(SrcNumElts)};
2741 int MaxRange[2] = {-1, -1};
2743 for (unsigned i = 0; i != MaskNumElts; ++i) {
2749 if (Idx >= (int)SrcNumElts) {
2753 if (Idx > MaxRange[Input])
2754 MaxRange[Input] = Idx;
2755 if (Idx < MinRange[Input])
2756 MinRange[Input] = Idx;
2759 // Check if the access is smaller than the vector size and can we find
2760 // a reasonable extract index.
2761 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2763 int StartIdx[2]; // StartIdx to extract from
2764 for (unsigned Input = 0; Input < 2; ++Input) {
2765 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2766 RangeUse[Input] = 0; // Unused
2767 StartIdx[Input] = 0;
2771 // Find a good start index that is a multiple of the mask length. Then
2772 // see if the rest of the elements are in range.
2773 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2774 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2775 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2776 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2779 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2780 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2783 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2784 // Extract appropriate subvector and generate a vector shuffle
2785 for (unsigned Input = 0; Input < 2; ++Input) {
2786 SDValue &Src = Input == 0 ? Src1 : Src2;
2787 if (RangeUse[Input] == 0)
2788 Src = DAG.getUNDEF(VT);
2790 SDLoc dl = getCurSDLoc();
2792 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2793 DAG.getConstant(StartIdx[Input], dl,
2794 TLI.getVectorIdxTy(DAG.getDataLayout())));
2798 // Calculate new mask.
2799 SmallVector<int, 8> MappedOps;
2800 for (unsigned i = 0; i != MaskNumElts; ++i) {
2803 if (Idx < (int)SrcNumElts)
2806 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2808 MappedOps.push_back(Idx);
2811 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2817 // We can't use either concat vectors or extract subvectors so fall back to
2818 // replacing the shuffle with extract and build vector.
2819 // to insert and build vector.
2820 EVT EltVT = VT.getVectorElementType();
2821 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2822 SDLoc dl = getCurSDLoc();
2823 SmallVector<SDValue,8> Ops;
2824 for (unsigned i = 0; i != MaskNumElts; ++i) {
2829 Res = DAG.getUNDEF(EltVT);
2831 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2832 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2834 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2835 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2841 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2844 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2845 const Value *Op0 = I.getOperand(0);
2846 const Value *Op1 = I.getOperand(1);
2847 Type *AggTy = I.getType();
2848 Type *ValTy = Op1->getType();
2849 bool IntoUndef = isa<UndefValue>(Op0);
2850 bool FromUndef = isa<UndefValue>(Op1);
2852 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2854 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2855 SmallVector<EVT, 4> AggValueVTs;
2856 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2857 SmallVector<EVT, 4> ValValueVTs;
2858 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2860 unsigned NumAggValues = AggValueVTs.size();
2861 unsigned NumValValues = ValValueVTs.size();
2862 SmallVector<SDValue, 4> Values(NumAggValues);
2864 // Ignore an insertvalue that produces an empty object
2865 if (!NumAggValues) {
2866 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2870 SDValue Agg = getValue(Op0);
2872 // Copy the beginning value(s) from the original aggregate.
2873 for (; i != LinearIndex; ++i)
2874 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2875 SDValue(Agg.getNode(), Agg.getResNo() + i);
2876 // Copy values from the inserted value(s).
2878 SDValue Val = getValue(Op1);
2879 for (; i != LinearIndex + NumValValues; ++i)
2880 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2881 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2883 // Copy remaining value(s) from the original aggregate.
2884 for (; i != NumAggValues; ++i)
2885 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2886 SDValue(Agg.getNode(), Agg.getResNo() + i);
2888 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2889 DAG.getVTList(AggValueVTs), Values));
2892 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2893 const Value *Op0 = I.getOperand(0);
2894 Type *AggTy = Op0->getType();
2895 Type *ValTy = I.getType();
2896 bool OutOfUndef = isa<UndefValue>(Op0);
2898 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2901 SmallVector<EVT, 4> ValValueVTs;
2902 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2904 unsigned NumValValues = ValValueVTs.size();
2906 // Ignore a extractvalue that produces an empty object
2907 if (!NumValValues) {
2908 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2912 SmallVector<SDValue, 4> Values(NumValValues);
2914 SDValue Agg = getValue(Op0);
2915 // Copy out the selected value(s).
2916 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2917 Values[i - LinearIndex] =
2919 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2920 SDValue(Agg.getNode(), Agg.getResNo() + i);
2922 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2923 DAG.getVTList(ValValueVTs), Values));
2926 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2927 Value *Op0 = I.getOperand(0);
2928 // Note that the pointer operand may be a vector of pointers. Take the scalar
2929 // element which holds a pointer.
2930 Type *Ty = Op0->getType()->getScalarType();
2931 unsigned AS = Ty->getPointerAddressSpace();
2932 SDValue N = getValue(Op0);
2933 SDLoc dl = getCurSDLoc();
2935 // Normalize Vector GEP - all scalar operands should be converted to the
2937 unsigned VectorWidth = I.getType()->isVectorTy() ?
2938 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2940 if (VectorWidth && !N.getValueType().isVector()) {
2941 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2942 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2943 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2945 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2947 const Value *Idx = *OI;
2948 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2949 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2952 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2953 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2954 DAG.getConstant(Offset, dl, N.getValueType()));
2957 Ty = StTy->getElementType(Field);
2959 Ty = cast<SequentialType>(Ty)->getElementType();
2961 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2962 unsigned PtrSize = PtrTy.getSizeInBits();
2963 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2965 // If this is a scalar constant or a splat vector of constants,
2966 // handle it quickly.
2967 const auto *CI = dyn_cast<ConstantInt>(Idx);
2968 if (!CI && isa<ConstantDataVector>(Idx) &&
2969 cast<ConstantDataVector>(Idx)->getSplatValue())
2970 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2975 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2976 SDValue OffsVal = VectorWidth ?
2977 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2978 DAG.getConstant(Offs, dl, PtrTy);
2979 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
2983 // N = N + Idx * ElementSize;
2984 SDValue IdxN = getValue(Idx);
2986 if (!IdxN.getValueType().isVector() && VectorWidth) {
2987 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
2988 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
2989 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2991 // If the index is smaller or larger than intptr_t, truncate or extend
2993 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
2995 // If this is a multiply by a power of two, turn it into a shl
2996 // immediately. This is a very common case.
2997 if (ElementSize != 1) {
2998 if (ElementSize.isPowerOf2()) {
2999 unsigned Amt = ElementSize.logBase2();
3000 IdxN = DAG.getNode(ISD::SHL, dl,
3001 N.getValueType(), IdxN,
3002 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3004 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3005 IdxN = DAG.getNode(ISD::MUL, dl,
3006 N.getValueType(), IdxN, Scale);
3010 N = DAG.getNode(ISD::ADD, dl,
3011 N.getValueType(), N, IdxN);
3018 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3019 // If this is a fixed sized alloca in the entry block of the function,
3020 // allocate it statically on the stack.
3021 if (FuncInfo.StaticAllocaMap.count(&I))
3022 return; // getValue will auto-populate this.
3024 SDLoc dl = getCurSDLoc();
3025 Type *Ty = I.getAllocatedType();
3026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3027 auto &DL = DAG.getDataLayout();
3028 uint64_t TySize = DL.getTypeAllocSize(Ty);
3030 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3032 SDValue AllocSize = getValue(I.getArraySize());
3034 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3035 if (AllocSize.getValueType() != IntPtr)
3036 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3038 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3040 DAG.getConstant(TySize, dl, IntPtr));
3042 // Handle alignment. If the requested alignment is less than or equal to
3043 // the stack alignment, ignore it. If the size is greater than or equal to
3044 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3045 unsigned StackAlign =
3046 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3047 if (Align <= StackAlign)
3050 // Round the size of the allocation up to the stack alignment size
3051 // by add SA-1 to the size.
3052 AllocSize = DAG.getNode(ISD::ADD, dl,
3053 AllocSize.getValueType(), AllocSize,
3054 DAG.getIntPtrConstant(StackAlign - 1, dl));
3056 // Mask out the low bits for alignment purposes.
3057 AllocSize = DAG.getNode(ISD::AND, dl,
3058 AllocSize.getValueType(), AllocSize,
3059 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3062 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3063 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3064 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3066 DAG.setRoot(DSA.getValue(1));
3068 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3071 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3073 return visitAtomicLoad(I);
3075 const Value *SV = I.getOperand(0);
3076 SDValue Ptr = getValue(SV);
3078 Type *Ty = I.getType();
3080 bool isVolatile = I.isVolatile();
3081 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3083 // The IR notion of invariant_load only guarantees that all *non-faulting*
3084 // invariant loads result in the same value. The MI notion of invariant load
3085 // guarantees that the load can be legally moved to any location within its
3086 // containing function. The MI notion of invariant_load is stronger than the
3087 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3088 // with a guarantee that the location being loaded from is dereferenceable
3089 // throughout the function's lifetime.
3091 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3092 isDereferenceablePointer(SV, DAG.getDataLayout());
3093 unsigned Alignment = I.getAlignment();
3096 I.getAAMetadata(AAInfo);
3097 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3099 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3100 SmallVector<EVT, 4> ValueVTs;
3101 SmallVector<uint64_t, 4> Offsets;
3102 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3103 unsigned NumValues = ValueVTs.size();
3108 bool ConstantMemory = false;
3109 if (isVolatile || NumValues > MaxParallelChains)
3110 // Serialize volatile loads with other side effects.
3112 else if (AA->pointsToConstantMemory(MemoryLocation(
3113 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3114 // Do not serialize (non-volatile) loads of constant memory with anything.
3115 Root = DAG.getEntryNode();
3116 ConstantMemory = true;
3118 // Do not serialize non-volatile loads against each other.
3119 Root = DAG.getRoot();
3122 SDLoc dl = getCurSDLoc();
3125 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3127 SmallVector<SDValue, 4> Values(NumValues);
3128 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3129 EVT PtrVT = Ptr.getValueType();
3130 unsigned ChainI = 0;
3131 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3132 // Serializing loads here may result in excessive register pressure, and
3133 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3134 // could recover a bit by hoisting nodes upward in the chain by recognizing
3135 // they are side-effect free or do not alias. The optimizer should really
3136 // avoid this case by converting large object/array copies to llvm.memcpy
3137 // (MaxParallelChains should always remain as failsafe).
3138 if (ChainI == MaxParallelChains) {
3139 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3140 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3141 makeArrayRef(Chains.data(), ChainI));
3145 SDValue A = DAG.getNode(ISD::ADD, dl,
3147 DAG.getConstant(Offsets[i], dl, PtrVT));
3148 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3149 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3150 isNonTemporal, isInvariant, Alignment, AAInfo,
3154 Chains[ChainI] = L.getValue(1);
3157 if (!ConstantMemory) {
3158 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3159 makeArrayRef(Chains.data(), ChainI));
3163 PendingLoads.push_back(Chain);
3166 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3167 DAG.getVTList(ValueVTs), Values));
3170 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3172 return visitAtomicStore(I);
3174 const Value *SrcV = I.getOperand(0);
3175 const Value *PtrV = I.getOperand(1);
3177 SmallVector<EVT, 4> ValueVTs;
3178 SmallVector<uint64_t, 4> Offsets;
3179 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3180 SrcV->getType(), ValueVTs, &Offsets);
3181 unsigned NumValues = ValueVTs.size();
3185 // Get the lowered operands. Note that we do this after
3186 // checking if NumResults is zero, because with zero results
3187 // the operands won't have values in the map.
3188 SDValue Src = getValue(SrcV);
3189 SDValue Ptr = getValue(PtrV);
3191 SDValue Root = getRoot();
3192 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3193 EVT PtrVT = Ptr.getValueType();
3194 bool isVolatile = I.isVolatile();
3195 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3196 unsigned Alignment = I.getAlignment();
3197 SDLoc dl = getCurSDLoc();
3200 I.getAAMetadata(AAInfo);
3202 unsigned ChainI = 0;
3203 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3204 // See visitLoad comments.
3205 if (ChainI == MaxParallelChains) {
3206 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3207 makeArrayRef(Chains.data(), ChainI));
3211 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3212 DAG.getConstant(Offsets[i], dl, PtrVT));
3213 SDValue St = DAG.getStore(Root, dl,
3214 SDValue(Src.getNode(), Src.getResNo() + i),
3215 Add, MachinePointerInfo(PtrV, Offsets[i]),
3216 isVolatile, isNonTemporal, Alignment, AAInfo);
3217 Chains[ChainI] = St;
3220 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3221 makeArrayRef(Chains.data(), ChainI));
3222 DAG.setRoot(StoreNode);
3225 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3226 SDLoc sdl = getCurSDLoc();
3228 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3229 Value *PtrOperand = I.getArgOperand(1);
3230 SDValue Ptr = getValue(PtrOperand);
3231 SDValue Src0 = getValue(I.getArgOperand(0));
3232 SDValue Mask = getValue(I.getArgOperand(3));
3233 EVT VT = Src0.getValueType();
3234 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3236 Alignment = DAG.getEVTAlignment(VT);
3239 I.getAAMetadata(AAInfo);
3241 MachineMemOperand *MMO =
3242 DAG.getMachineFunction().
3243 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3244 MachineMemOperand::MOStore, VT.getStoreSize(),
3246 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3248 DAG.setRoot(StoreNode);
3249 setValue(&I, StoreNode);
3252 // Get a uniform base for the Gather/Scatter intrinsic.
3253 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3254 // We try to represent it as a base pointer + vector of indices.
3255 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3256 // The first operand of the GEP may be a single pointer or a vector of pointers
3258 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3260 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3261 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3263 // When the first GEP operand is a single pointer - it is the uniform base we
3264 // are looking for. If first operand of the GEP is a splat vector - we
3265 // extract the spalt value and use it as a uniform base.
3266 // In all other cases the function returns 'false'.
3268 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3269 SelectionDAGBuilder* SDB) {
3271 SelectionDAG& DAG = SDB->DAG;
3272 LLVMContext &Context = *DAG.getContext();
3274 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3275 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3276 if (!GEP || GEP->getNumOperands() > 2)
3279 Value *GEPPtr = GEP->getPointerOperand();
3280 if (!GEPPtr->getType()->isVectorTy())
3282 else if (!(Ptr = getSplatValue(GEPPtr)))
3285 Value *IndexVal = GEP->getOperand(1);
3287 // The operands of the GEP may be defined in another basic block.
3288 // In this case we'll not find nodes for the operands.
3289 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3292 Base = SDB->getValue(Ptr);
3293 Index = SDB->getValue(IndexVal);
3295 // Suppress sign extension.
3296 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3297 if (SDB->findValue(Sext->getOperand(0))) {
3298 IndexVal = Sext->getOperand(0);
3299 Index = SDB->getValue(IndexVal);
3302 if (!Index.getValueType().isVector()) {
3303 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3304 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3305 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3306 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3311 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3312 SDLoc sdl = getCurSDLoc();
3314 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3315 Value *Ptr = I.getArgOperand(1);
3316 SDValue Src0 = getValue(I.getArgOperand(0));
3317 SDValue Mask = getValue(I.getArgOperand(3));
3318 EVT VT = Src0.getValueType();
3319 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3321 Alignment = DAG.getEVTAlignment(VT);
3322 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3325 I.getAAMetadata(AAInfo);
3329 Value *BasePtr = Ptr;
3330 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3332 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3333 MachineMemOperand *MMO = DAG.getMachineFunction().
3334 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3335 MachineMemOperand::MOStore, VT.getStoreSize(),
3338 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3339 Index = getValue(Ptr);
3341 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3342 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3344 DAG.setRoot(Scatter);
3345 setValue(&I, Scatter);
3348 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3349 SDLoc sdl = getCurSDLoc();
3351 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3352 Value *PtrOperand = I.getArgOperand(0);
3353 SDValue Ptr = getValue(PtrOperand);
3354 SDValue Src0 = getValue(I.getArgOperand(3));
3355 SDValue Mask = getValue(I.getArgOperand(2));
3357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3358 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3359 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3361 Alignment = DAG.getEVTAlignment(VT);
3364 I.getAAMetadata(AAInfo);
3365 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3367 SDValue InChain = DAG.getRoot();
3368 if (AA->pointsToConstantMemory(MemoryLocation(
3369 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3371 // Do not serialize (non-volatile) loads of constant memory with anything.
3372 InChain = DAG.getEntryNode();
3375 MachineMemOperand *MMO =
3376 DAG.getMachineFunction().
3377 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3378 MachineMemOperand::MOLoad, VT.getStoreSize(),
3379 Alignment, AAInfo, Ranges);
3381 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3383 SDValue OutChain = Load.getValue(1);
3384 DAG.setRoot(OutChain);
3388 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3389 SDLoc sdl = getCurSDLoc();
3391 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3392 Value *Ptr = I.getArgOperand(0);
3393 SDValue Src0 = getValue(I.getArgOperand(3));
3394 SDValue Mask = getValue(I.getArgOperand(2));
3396 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3397 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3398 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3400 Alignment = DAG.getEVTAlignment(VT);
3403 I.getAAMetadata(AAInfo);
3404 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3406 SDValue Root = DAG.getRoot();
3409 Value *BasePtr = Ptr;
3410 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3411 bool ConstantMemory = false;
3413 AA->pointsToConstantMemory(MemoryLocation(
3414 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3416 // Do not serialize (non-volatile) loads of constant memory with anything.
3417 Root = DAG.getEntryNode();
3418 ConstantMemory = true;
3421 MachineMemOperand *MMO =
3422 DAG.getMachineFunction().
3423 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3424 MachineMemOperand::MOLoad, VT.getStoreSize(),
3425 Alignment, AAInfo, Ranges);
3428 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3429 Index = getValue(Ptr);
3431 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3432 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3435 SDValue OutChain = Gather.getValue(1);
3436 if (!ConstantMemory)
3437 PendingLoads.push_back(OutChain);
3438 setValue(&I, Gather);
3441 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3442 SDLoc dl = getCurSDLoc();
3443 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3444 AtomicOrdering FailureOrder = I.getFailureOrdering();
3445 SynchronizationScope Scope = I.getSynchScope();
3447 SDValue InChain = getRoot();
3449 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3450 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3451 SDValue L = DAG.getAtomicCmpSwap(
3452 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3453 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3454 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3455 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3457 SDValue OutChain = L.getValue(2);
3460 DAG.setRoot(OutChain);
3463 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3464 SDLoc dl = getCurSDLoc();
3466 switch (I.getOperation()) {
3467 default: llvm_unreachable("Unknown atomicrmw operation");
3468 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3469 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3470 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3471 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3472 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3473 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3474 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3475 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3476 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3477 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3478 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3480 AtomicOrdering Order = I.getOrdering();
3481 SynchronizationScope Scope = I.getSynchScope();
3483 SDValue InChain = getRoot();
3486 DAG.getAtomic(NT, dl,
3487 getValue(I.getValOperand()).getSimpleValueType(),
3489 getValue(I.getPointerOperand()),
3490 getValue(I.getValOperand()),
3491 I.getPointerOperand(),
3492 /* Alignment=*/ 0, Order, Scope);
3494 SDValue OutChain = L.getValue(1);
3497 DAG.setRoot(OutChain);
3500 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3501 SDLoc dl = getCurSDLoc();
3502 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3505 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3506 TLI.getPointerTy(DAG.getDataLayout()));
3507 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3508 TLI.getPointerTy(DAG.getDataLayout()));
3509 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3512 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3513 SDLoc dl = getCurSDLoc();
3514 AtomicOrdering Order = I.getOrdering();
3515 SynchronizationScope Scope = I.getSynchScope();
3517 SDValue InChain = getRoot();
3519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3520 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3522 if (I.getAlignment() < VT.getSizeInBits() / 8)
3523 report_fatal_error("Cannot generate unaligned atomic load");
3525 MachineMemOperand *MMO =
3526 DAG.getMachineFunction().
3527 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3528 MachineMemOperand::MOVolatile |
3529 MachineMemOperand::MOLoad,
3531 I.getAlignment() ? I.getAlignment() :
3532 DAG.getEVTAlignment(VT));
3534 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3536 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3537 getValue(I.getPointerOperand()), MMO,
3540 SDValue OutChain = L.getValue(1);
3543 DAG.setRoot(OutChain);
3546 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3547 SDLoc dl = getCurSDLoc();
3549 AtomicOrdering Order = I.getOrdering();
3550 SynchronizationScope Scope = I.getSynchScope();
3552 SDValue InChain = getRoot();
3554 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3556 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3558 if (I.getAlignment() < VT.getSizeInBits() / 8)
3559 report_fatal_error("Cannot generate unaligned atomic store");
3562 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3564 getValue(I.getPointerOperand()),
3565 getValue(I.getValueOperand()),
3566 I.getPointerOperand(), I.getAlignment(),
3569 DAG.setRoot(OutChain);
3572 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3574 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3575 unsigned Intrinsic) {
3576 bool HasChain = !I.doesNotAccessMemory();
3577 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3579 // Build the operand list.
3580 SmallVector<SDValue, 8> Ops;
3581 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3583 // We don't need to serialize loads against other loads.
3584 Ops.push_back(DAG.getRoot());
3586 Ops.push_back(getRoot());
3590 // Info is set by getTgtMemInstrinsic
3591 TargetLowering::IntrinsicInfo Info;
3592 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3593 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3595 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3596 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3597 Info.opc == ISD::INTRINSIC_W_CHAIN)
3598 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3599 TLI.getPointerTy(DAG.getDataLayout())));
3601 // Add all operands of the call to the operand list.
3602 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3603 SDValue Op = getValue(I.getArgOperand(i));
3607 SmallVector<EVT, 4> ValueVTs;
3608 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3611 ValueVTs.push_back(MVT::Other);
3613 SDVTList VTs = DAG.getVTList(ValueVTs);
3617 if (IsTgtIntrinsic) {
3618 // This is target intrinsic that touches memory
3619 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3620 VTs, Ops, Info.memVT,
3621 MachinePointerInfo(Info.ptrVal, Info.offset),
3622 Info.align, Info.vol,
3623 Info.readMem, Info.writeMem, Info.size);
3624 } else if (!HasChain) {
3625 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3626 } else if (!I.getType()->isVoidTy()) {
3627 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3629 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3633 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3635 PendingLoads.push_back(Chain);
3640 if (!I.getType()->isVoidTy()) {
3641 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3642 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3643 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3646 setValue(&I, Result);
3650 /// GetSignificand - Get the significand and build it into a floating-point
3651 /// number with exponent of 1:
3653 /// Op = (Op & 0x007fffff) | 0x3f800000;
3655 /// where Op is the hexadecimal representation of floating point value.
3657 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3658 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3659 DAG.getConstant(0x007fffff, dl, MVT::i32));
3660 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3661 DAG.getConstant(0x3f800000, dl, MVT::i32));
3662 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3665 /// GetExponent - Get the exponent:
3667 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3669 /// where Op is the hexadecimal representation of floating point value.
3671 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3673 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3674 DAG.getConstant(0x7f800000, dl, MVT::i32));
3675 SDValue t1 = DAG.getNode(
3676 ISD::SRL, dl, MVT::i32, t0,
3677 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3678 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3679 DAG.getConstant(127, dl, MVT::i32));
3680 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3683 /// getF32Constant - Get 32-bit floating point constant.
3685 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3686 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3690 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3691 SelectionDAG &DAG) {
3692 // TODO: What fast-math-flags should be set on the floating-point nodes?
3694 // IntegerPartOfX = ((int32_t)(t0);
3695 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3697 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3698 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3699 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3701 // IntegerPartOfX <<= 23;
3702 IntegerPartOfX = DAG.getNode(
3703 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3704 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3705 DAG.getDataLayout())));
3707 SDValue TwoToFractionalPartOfX;
3708 if (LimitFloatPrecision <= 6) {
3709 // For floating-point precision of 6:
3711 // TwoToFractionalPartOfX =
3713 // (0.735607626f + 0.252464424f * x) * x;
3715 // error 0.0144103317, which is 6 bits
3716 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3717 getF32Constant(DAG, 0x3e814304, dl));
3718 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3719 getF32Constant(DAG, 0x3f3c50c8, dl));
3720 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3721 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3722 getF32Constant(DAG, 0x3f7f5e7e, dl));
3723 } else if (LimitFloatPrecision <= 12) {
3724 // For floating-point precision of 12:
3726 // TwoToFractionalPartOfX =
3729 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3731 // error 0.000107046256, which is 13 to 14 bits
3732 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3733 getF32Constant(DAG, 0x3da235e3, dl));
3734 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3735 getF32Constant(DAG, 0x3e65b8f3, dl));
3736 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3737 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3738 getF32Constant(DAG, 0x3f324b07, dl));
3739 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3740 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3741 getF32Constant(DAG, 0x3f7ff8fd, dl));
3742 } else { // LimitFloatPrecision <= 18
3743 // For floating-point precision of 18:
3745 // TwoToFractionalPartOfX =
3749 // (0.554906021e-1f +
3750 // (0.961591928e-2f +
3751 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3752 // error 2.47208000*10^(-7), which is better than 18 bits
3753 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3754 getF32Constant(DAG, 0x3924b03e, dl));
3755 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3756 getF32Constant(DAG, 0x3ab24b87, dl));
3757 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3758 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3759 getF32Constant(DAG, 0x3c1d8c17, dl));
3760 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3761 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3762 getF32Constant(DAG, 0x3d634a1d, dl));
3763 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3764 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3765 getF32Constant(DAG, 0x3e75fe14, dl));
3766 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3767 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3768 getF32Constant(DAG, 0x3f317234, dl));
3769 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3770 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3771 getF32Constant(DAG, 0x3f800000, dl));
3774 // Add the exponent into the result in integer domain.
3775 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3776 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3777 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3780 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3781 /// limited-precision mode.
3782 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3783 const TargetLowering &TLI) {
3784 if (Op.getValueType() == MVT::f32 &&
3785 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3787 // Put the exponent in the right bit position for later addition to the
3790 // #define LOG2OFe 1.4426950f
3791 // t0 = Op * LOG2OFe
3793 // TODO: What fast-math-flags should be set here?
3794 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3795 getF32Constant(DAG, 0x3fb8aa3b, dl));
3796 return getLimitedPrecisionExp2(t0, dl, DAG);
3799 // No special expansion.
3800 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3803 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3804 /// limited-precision mode.
3805 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3806 const TargetLowering &TLI) {
3808 // TODO: What fast-math-flags should be set on the floating-point nodes?
3810 if (Op.getValueType() == MVT::f32 &&
3811 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3812 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3814 // Scale the exponent by log(2) [0.69314718f].
3815 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3816 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3817 getF32Constant(DAG, 0x3f317218, dl));
3819 // Get the significand and build it into a floating-point number with
3821 SDValue X = GetSignificand(DAG, Op1, dl);
3823 SDValue LogOfMantissa;
3824 if (LimitFloatPrecision <= 6) {
3825 // For floating-point precision of 6:
3829 // (1.4034025f - 0.23903021f * x) * x;
3831 // error 0.0034276066, which is better than 8 bits
3832 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3833 getF32Constant(DAG, 0xbe74c456, dl));
3834 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3835 getF32Constant(DAG, 0x3fb3a2b1, dl));
3836 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3837 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3838 getF32Constant(DAG, 0x3f949a29, dl));
3839 } else if (LimitFloatPrecision <= 12) {
3840 // For floating-point precision of 12:
3846 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3848 // error 0.000061011436, which is 14 bits
3849 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3850 getF32Constant(DAG, 0xbd67b6d6, dl));
3851 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3852 getF32Constant(DAG, 0x3ee4f4b8, dl));
3853 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3854 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3855 getF32Constant(DAG, 0x3fbc278b, dl));
3856 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3857 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3858 getF32Constant(DAG, 0x40348e95, dl));
3859 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3860 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3861 getF32Constant(DAG, 0x3fdef31a, dl));
3862 } else { // LimitFloatPrecision <= 18
3863 // For floating-point precision of 18:
3871 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3873 // error 0.0000023660568, which is better than 18 bits
3874 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3875 getF32Constant(DAG, 0xbc91e5ac, dl));
3876 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3877 getF32Constant(DAG, 0x3e4350aa, dl));
3878 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3879 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3880 getF32Constant(DAG, 0x3f60d3e3, dl));
3881 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3882 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3883 getF32Constant(DAG, 0x4011cdf0, dl));
3884 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3885 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3886 getF32Constant(DAG, 0x406cfd1c, dl));
3887 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3888 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3889 getF32Constant(DAG, 0x408797cb, dl));
3890 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3891 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3892 getF32Constant(DAG, 0x4006dcab, dl));
3895 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3898 // No special expansion.
3899 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3902 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3903 /// limited-precision mode.
3904 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3905 const TargetLowering &TLI) {
3907 // TODO: What fast-math-flags should be set on the floating-point nodes?
3909 if (Op.getValueType() == MVT::f32 &&
3910 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3911 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3913 // Get the exponent.
3914 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3916 // Get the significand and build it into a floating-point number with
3918 SDValue X = GetSignificand(DAG, Op1, dl);
3920 // Different possible minimax approximations of significand in
3921 // floating-point for various degrees of accuracy over [1,2].
3922 SDValue Log2ofMantissa;
3923 if (LimitFloatPrecision <= 6) {
3924 // For floating-point precision of 6:
3926 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3928 // error 0.0049451742, which is more than 7 bits
3929 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3930 getF32Constant(DAG, 0xbeb08fe0, dl));
3931 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3932 getF32Constant(DAG, 0x40019463, dl));
3933 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3934 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3935 getF32Constant(DAG, 0x3fd6633d, dl));
3936 } else if (LimitFloatPrecision <= 12) {
3937 // For floating-point precision of 12:
3943 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3945 // error 0.0000876136000, which is better than 13 bits
3946 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3947 getF32Constant(DAG, 0xbda7262e, dl));
3948 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3949 getF32Constant(DAG, 0x3f25280b, dl));
3950 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3951 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3952 getF32Constant(DAG, 0x4007b923, dl));
3953 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3954 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3955 getF32Constant(DAG, 0x40823e2f, dl));
3956 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3957 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3958 getF32Constant(DAG, 0x4020d29c, dl));
3959 } else { // LimitFloatPrecision <= 18
3960 // For floating-point precision of 18:
3969 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3971 // error 0.0000018516, which is better than 18 bits
3972 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3973 getF32Constant(DAG, 0xbcd2769e, dl));
3974 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3975 getF32Constant(DAG, 0x3e8ce0b9, dl));
3976 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3977 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3978 getF32Constant(DAG, 0x3fa22ae7, dl));
3979 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3980 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3981 getF32Constant(DAG, 0x40525723, dl));
3982 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3983 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3984 getF32Constant(DAG, 0x40aaf200, dl));
3985 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3986 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3987 getF32Constant(DAG, 0x40c39dad, dl));
3988 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3989 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3990 getF32Constant(DAG, 0x4042902c, dl));
3993 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
3996 // No special expansion.
3997 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4000 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4001 /// limited-precision mode.
4002 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4003 const TargetLowering &TLI) {
4005 // TODO: What fast-math-flags should be set on the floating-point nodes?
4007 if (Op.getValueType() == MVT::f32 &&
4008 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4009 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4011 // Scale the exponent by log10(2) [0.30102999f].
4012 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4013 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4014 getF32Constant(DAG, 0x3e9a209a, dl));
4016 // Get the significand and build it into a floating-point number with
4018 SDValue X = GetSignificand(DAG, Op1, dl);
4020 SDValue Log10ofMantissa;
4021 if (LimitFloatPrecision <= 6) {
4022 // For floating-point precision of 6:
4024 // Log10ofMantissa =
4026 // (0.60948995f - 0.10380950f * x) * x;
4028 // error 0.0014886165, which is 6 bits
4029 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4030 getF32Constant(DAG, 0xbdd49a13, dl));
4031 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4032 getF32Constant(DAG, 0x3f1c0789, dl));
4033 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4034 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4035 getF32Constant(DAG, 0x3f011300, dl));
4036 } else if (LimitFloatPrecision <= 12) {
4037 // For floating-point precision of 12:
4039 // Log10ofMantissa =
4042 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4044 // error 0.00019228036, which is better than 12 bits
4045 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4046 getF32Constant(DAG, 0x3d431f31, dl));
4047 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4048 getF32Constant(DAG, 0x3ea21fb2, dl));
4049 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4050 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4051 getF32Constant(DAG, 0x3f6ae232, dl));
4052 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4053 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4054 getF32Constant(DAG, 0x3f25f7c3, dl));
4055 } else { // LimitFloatPrecision <= 18
4056 // For floating-point precision of 18:
4058 // Log10ofMantissa =
4063 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4065 // error 0.0000037995730, which is better than 18 bits
4066 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4067 getF32Constant(DAG, 0x3c5d51ce, dl));
4068 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4069 getF32Constant(DAG, 0x3e00685a, dl));
4070 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4071 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4072 getF32Constant(DAG, 0x3efb6798, dl));
4073 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4074 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4075 getF32Constant(DAG, 0x3f88d192, dl));
4076 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4077 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4078 getF32Constant(DAG, 0x3fc4316c, dl));
4079 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4080 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4081 getF32Constant(DAG, 0x3f57ce70, dl));
4084 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4087 // No special expansion.
4088 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4091 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4092 /// limited-precision mode.
4093 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4094 const TargetLowering &TLI) {
4095 if (Op.getValueType() == MVT::f32 &&
4096 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4097 return getLimitedPrecisionExp2(Op, dl, DAG);
4099 // No special expansion.
4100 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4103 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4104 /// limited-precision mode with x == 10.0f.
4105 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4106 SelectionDAG &DAG, const TargetLowering &TLI) {
4107 bool IsExp10 = false;
4108 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4109 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4110 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4112 IsExp10 = LHSC->isExactlyValue(Ten);
4116 // TODO: What fast-math-flags should be set on the FMUL node?
4118 // Put the exponent in the right bit position for later addition to the
4121 // #define LOG2OF10 3.3219281f
4122 // t0 = Op * LOG2OF10;
4123 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4124 getF32Constant(DAG, 0x40549a78, dl));
4125 return getLimitedPrecisionExp2(t0, dl, DAG);
4128 // No special expansion.
4129 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4133 /// ExpandPowI - Expand a llvm.powi intrinsic.
4134 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4135 SelectionDAG &DAG) {
4136 // If RHS is a constant, we can expand this out to a multiplication tree,
4137 // otherwise we end up lowering to a call to __powidf2 (for example). When
4138 // optimizing for size, we only want to do this if the expansion would produce
4139 // a small number of multiplies, otherwise we do the full expansion.
4140 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4141 // Get the exponent as a positive value.
4142 unsigned Val = RHSC->getSExtValue();
4143 if ((int)Val < 0) Val = -Val;
4145 // powi(x, 0) -> 1.0
4147 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4149 const Function *F = DAG.getMachineFunction().getFunction();
4150 if (!F->optForSize() ||
4151 // If optimizing for size, don't insert too many multiplies.
4152 // This inserts up to 5 multiplies.
4153 countPopulation(Val) + Log2_32(Val) < 7) {
4154 // We use the simple binary decomposition method to generate the multiply
4155 // sequence. There are more optimal ways to do this (for example,
4156 // powi(x,15) generates one more multiply than it should), but this has
4157 // the benefit of being both really simple and much better than a libcall.
4158 SDValue Res; // Logically starts equal to 1.0
4159 SDValue CurSquare = LHS;
4160 // TODO: Intrinsics should have fast-math-flags that propagate to these
4165 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4167 Res = CurSquare; // 1.0*CurSquare.
4170 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4171 CurSquare, CurSquare);
4175 // If the original was negative, invert the result, producing 1/(x*x*x).
4176 if (RHSC->getSExtValue() < 0)
4177 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4178 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4183 // Otherwise, expand to a libcall.
4184 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4187 // getTruncatedArgReg - Find underlying register used for an truncated
4189 static unsigned getTruncatedArgReg(const SDValue &N) {
4190 if (N.getOpcode() != ISD::TRUNCATE)
4193 const SDValue &Ext = N.getOperand(0);
4194 if (Ext.getOpcode() == ISD::AssertZext ||
4195 Ext.getOpcode() == ISD::AssertSext) {
4196 const SDValue &CFR = Ext.getOperand(0);
4197 if (CFR.getOpcode() == ISD::CopyFromReg)
4198 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4199 if (CFR.getOpcode() == ISD::TRUNCATE)
4200 return getTruncatedArgReg(CFR);
4205 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4206 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4207 /// At the end of instruction selection, they will be inserted to the entry BB.
4208 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4209 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4210 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4211 const Argument *Arg = dyn_cast<Argument>(V);
4215 MachineFunction &MF = DAG.getMachineFunction();
4216 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4218 // Ignore inlined function arguments here.
4220 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4221 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4224 Optional<MachineOperand> Op;
4225 // Some arguments' frame index is recorded during argument lowering.
4226 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4227 Op = MachineOperand::CreateFI(FI);
4229 if (!Op && N.getNode()) {
4231 if (N.getOpcode() == ISD::CopyFromReg)
4232 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4234 Reg = getTruncatedArgReg(N);
4235 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4236 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4237 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4242 Op = MachineOperand::CreateReg(Reg, false);
4246 // Check if ValueMap has reg number.
4247 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4248 if (VMI != FuncInfo.ValueMap.end())
4249 Op = MachineOperand::CreateReg(VMI->second, false);
4252 if (!Op && N.getNode())
4253 // Check if frame index is available.
4254 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4255 if (FrameIndexSDNode *FINode =
4256 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4257 Op = MachineOperand::CreateFI(FINode->getIndex());
4262 assert(Variable->isValidLocationForIntrinsic(DL) &&
4263 "Expected inlined-at fields to agree");
4265 FuncInfo.ArgDbgValues.push_back(
4266 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4267 Op->getReg(), Offset, Variable, Expr));
4269 FuncInfo.ArgDbgValues.push_back(
4270 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4273 .addMetadata(Variable)
4274 .addMetadata(Expr));
4279 // VisualStudio defines setjmp as _setjmp
4280 #if defined(_MSC_VER) && defined(setjmp) && \
4281 !defined(setjmp_undefined_for_msvc)
4282 # pragma push_macro("setjmp")
4284 # define setjmp_undefined_for_msvc
4287 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4288 /// we want to emit this as a call to a named external function, return the name
4289 /// otherwise lower it and return null.
4291 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4292 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4293 SDLoc sdl = getCurSDLoc();
4294 DebugLoc dl = getCurDebugLoc();
4297 switch (Intrinsic) {
4299 // By default, turn this into a target intrinsic node.
4300 visitTargetIntrinsic(I, Intrinsic);
4302 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4303 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4304 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4305 case Intrinsic::returnaddress:
4306 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4307 TLI.getPointerTy(DAG.getDataLayout()),
4308 getValue(I.getArgOperand(0))));
4310 case Intrinsic::frameaddress:
4311 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4312 TLI.getPointerTy(DAG.getDataLayout()),
4313 getValue(I.getArgOperand(0))));
4315 case Intrinsic::read_register: {
4316 Value *Reg = I.getArgOperand(0);
4317 SDValue Chain = getRoot();
4319 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4320 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4321 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4322 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4324 DAG.setRoot(Res.getValue(1));
4327 case Intrinsic::write_register: {
4328 Value *Reg = I.getArgOperand(0);
4329 Value *RegValue = I.getArgOperand(1);
4330 SDValue Chain = getRoot();
4332 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4333 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4334 RegName, getValue(RegValue)));
4337 case Intrinsic::setjmp:
4338 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4339 case Intrinsic::longjmp:
4340 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4341 case Intrinsic::memcpy: {
4342 // FIXME: this definition of "user defined address space" is x86-specific
4343 // Assert for address < 256 since we support only user defined address
4345 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4347 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4349 "Unknown address space");
4350 SDValue Op1 = getValue(I.getArgOperand(0));
4351 SDValue Op2 = getValue(I.getArgOperand(1));
4352 SDValue Op3 = getValue(I.getArgOperand(2));
4353 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4355 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4356 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4357 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4358 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4360 MachinePointerInfo(I.getArgOperand(0)),
4361 MachinePointerInfo(I.getArgOperand(1)));
4362 updateDAGForMaybeTailCall(MC);
4365 case Intrinsic::memset: {
4366 // FIXME: this definition of "user defined address space" is x86-specific
4367 // Assert for address < 256 since we support only user defined address
4369 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4371 "Unknown address space");
4372 SDValue Op1 = getValue(I.getArgOperand(0));
4373 SDValue Op2 = getValue(I.getArgOperand(1));
4374 SDValue Op3 = getValue(I.getArgOperand(2));
4375 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4377 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4378 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4379 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4380 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4381 isTC, MachinePointerInfo(I.getArgOperand(0)));
4382 updateDAGForMaybeTailCall(MS);
4385 case Intrinsic::memmove: {
4386 // FIXME: this definition of "user defined address space" is x86-specific
4387 // Assert for address < 256 since we support only user defined address
4389 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4391 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4393 "Unknown address space");
4394 SDValue Op1 = getValue(I.getArgOperand(0));
4395 SDValue Op2 = getValue(I.getArgOperand(1));
4396 SDValue Op3 = getValue(I.getArgOperand(2));
4397 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4399 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4400 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4401 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4402 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4403 isTC, MachinePointerInfo(I.getArgOperand(0)),
4404 MachinePointerInfo(I.getArgOperand(1)));
4405 updateDAGForMaybeTailCall(MM);
4408 case Intrinsic::dbg_declare: {
4409 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4410 DILocalVariable *Variable = DI.getVariable();
4411 DIExpression *Expression = DI.getExpression();
4412 const Value *Address = DI.getAddress();
4413 assert(Variable && "Missing variable");
4415 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4419 // Check if address has undef value.
4420 if (isa<UndefValue>(Address) ||
4421 (Address->use_empty() && !isa<Argument>(Address))) {
4422 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4426 SDValue &N = NodeMap[Address];
4427 if (!N.getNode() && isa<Argument>(Address))
4428 // Check unused arguments map.
4429 N = UnusedArgNodeMap[Address];
4432 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4433 Address = BCI->getOperand(0);
4434 // Parameters are handled specially.
4435 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4437 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4439 if (isParameter && !AI) {
4440 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4442 // Byval parameter. We have a frame index at this point.
4443 SDV = DAG.getFrameIndexDbgValue(
4444 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4446 // Address is an argument, so try to emit its dbg value using
4447 // virtual register info from the FuncInfo.ValueMap.
4448 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4453 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4454 true, 0, dl, SDNodeOrder);
4456 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4458 // If Address is an argument then try to emit its dbg value using
4459 // virtual register info from the FuncInfo.ValueMap.
4460 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4462 // If variable is pinned by a alloca in dominating bb then
4463 // use StaticAllocaMap.
4464 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4465 if (AI->getParent() != DI.getParent()) {
4466 DenseMap<const AllocaInst*, int>::iterator SI =
4467 FuncInfo.StaticAllocaMap.find(AI);
4468 if (SI != FuncInfo.StaticAllocaMap.end()) {
4469 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4470 0, dl, SDNodeOrder);
4471 DAG.AddDbgValue(SDV, nullptr, false);
4476 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4481 case Intrinsic::dbg_value: {
4482 const DbgValueInst &DI = cast<DbgValueInst>(I);
4483 assert(DI.getVariable() && "Missing variable");
4485 DILocalVariable *Variable = DI.getVariable();
4486 DIExpression *Expression = DI.getExpression();
4487 uint64_t Offset = DI.getOffset();
4488 const Value *V = DI.getValue();
4493 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4494 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4496 DAG.AddDbgValue(SDV, nullptr, false);
4498 // Do not use getValue() in here; we don't want to generate code at
4499 // this point if it hasn't been done yet.
4500 SDValue N = NodeMap[V];
4501 if (!N.getNode() && isa<Argument>(V))
4502 // Check unused arguments map.
4503 N = UnusedArgNodeMap[V];
4505 // A dbg.value for an alloca is always indirect.
4506 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4507 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4509 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4510 IsIndirect, Offset, dl, SDNodeOrder);
4511 DAG.AddDbgValue(SDV, N.getNode(), false);
4513 } else if (!V->use_empty() ) {
4514 // Do not call getValue(V) yet, as we don't want to generate code.
4515 // Remember it for later.
4516 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4517 DanglingDebugInfoMap[V] = DDI;
4519 // We may expand this to cover more cases. One case where we have no
4520 // data available is an unreferenced parameter.
4521 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4525 // Build a debug info table entry.
4526 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4527 V = BCI->getOperand(0);
4528 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4529 // Don't handle byval struct arguments or VLAs, for example.
4531 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4532 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4535 DenseMap<const AllocaInst*, int>::iterator SI =
4536 FuncInfo.StaticAllocaMap.find(AI);
4537 if (SI == FuncInfo.StaticAllocaMap.end())
4538 return nullptr; // VLAs.
4542 case Intrinsic::eh_typeid_for: {
4543 // Find the type id for the given typeinfo.
4544 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4545 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4546 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4551 case Intrinsic::eh_return_i32:
4552 case Intrinsic::eh_return_i64:
4553 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4554 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4557 getValue(I.getArgOperand(0)),
4558 getValue(I.getArgOperand(1))));
4560 case Intrinsic::eh_unwind_init:
4561 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4563 case Intrinsic::eh_dwarf_cfa: {
4564 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4565 TLI.getPointerTy(DAG.getDataLayout()));
4566 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4567 CfaArg.getValueType(),
4568 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4569 CfaArg.getValueType()),
4571 SDValue FA = DAG.getNode(
4572 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4573 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4574 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4578 case Intrinsic::eh_sjlj_callsite: {
4579 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4580 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4581 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4582 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4584 MMI.setCurrentCallSite(CI->getZExtValue());
4587 case Intrinsic::eh_sjlj_functioncontext: {
4588 // Get and store the index of the function context.
4589 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4591 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4592 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4593 MFI->setFunctionContextIndex(FI);
4596 case Intrinsic::eh_sjlj_setjmp: {
4599 Ops[1] = getValue(I.getArgOperand(0));
4600 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4601 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4602 setValue(&I, Op.getValue(0));
4603 DAG.setRoot(Op.getValue(1));
4606 case Intrinsic::eh_sjlj_longjmp: {
4607 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4608 getRoot(), getValue(I.getArgOperand(0))));
4611 case Intrinsic::eh_sjlj_setup_dispatch: {
4612 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4617 case Intrinsic::masked_gather:
4618 visitMaskedGather(I);
4620 case Intrinsic::masked_load:
4623 case Intrinsic::masked_scatter:
4624 visitMaskedScatter(I);
4626 case Intrinsic::masked_store:
4627 visitMaskedStore(I);
4629 case Intrinsic::x86_mmx_pslli_w:
4630 case Intrinsic::x86_mmx_pslli_d:
4631 case Intrinsic::x86_mmx_pslli_q:
4632 case Intrinsic::x86_mmx_psrli_w:
4633 case Intrinsic::x86_mmx_psrli_d:
4634 case Intrinsic::x86_mmx_psrli_q:
4635 case Intrinsic::x86_mmx_psrai_w:
4636 case Intrinsic::x86_mmx_psrai_d: {
4637 SDValue ShAmt = getValue(I.getArgOperand(1));
4638 if (isa<ConstantSDNode>(ShAmt)) {
4639 visitTargetIntrinsic(I, Intrinsic);
4642 unsigned NewIntrinsic = 0;
4643 EVT ShAmtVT = MVT::v2i32;
4644 switch (Intrinsic) {
4645 case Intrinsic::x86_mmx_pslli_w:
4646 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4648 case Intrinsic::x86_mmx_pslli_d:
4649 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4651 case Intrinsic::x86_mmx_pslli_q:
4652 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4654 case Intrinsic::x86_mmx_psrli_w:
4655 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4657 case Intrinsic::x86_mmx_psrli_d:
4658 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4660 case Intrinsic::x86_mmx_psrli_q:
4661 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4663 case Intrinsic::x86_mmx_psrai_w:
4664 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4666 case Intrinsic::x86_mmx_psrai_d:
4667 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4669 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4672 // The vector shift intrinsics with scalars uses 32b shift amounts but
4673 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4675 // We must do this early because v2i32 is not a legal type.
4678 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4679 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4680 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4681 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4682 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4683 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4684 getValue(I.getArgOperand(0)), ShAmt);
4688 case Intrinsic::convertff:
4689 case Intrinsic::convertfsi:
4690 case Intrinsic::convertfui:
4691 case Intrinsic::convertsif:
4692 case Intrinsic::convertuif:
4693 case Intrinsic::convertss:
4694 case Intrinsic::convertsu:
4695 case Intrinsic::convertus:
4696 case Intrinsic::convertuu: {
4697 ISD::CvtCode Code = ISD::CVT_INVALID;
4698 switch (Intrinsic) {
4699 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4700 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4701 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4702 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4703 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4704 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4705 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4706 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4707 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4708 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4710 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4711 const Value *Op1 = I.getArgOperand(0);
4712 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4713 DAG.getValueType(DestVT),
4714 DAG.getValueType(getValue(Op1).getValueType()),
4715 getValue(I.getArgOperand(1)),
4716 getValue(I.getArgOperand(2)),
4721 case Intrinsic::powi:
4722 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4723 getValue(I.getArgOperand(1)), DAG));
4725 case Intrinsic::log:
4726 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4728 case Intrinsic::log2:
4729 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4731 case Intrinsic::log10:
4732 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4734 case Intrinsic::exp:
4735 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4737 case Intrinsic::exp2:
4738 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4740 case Intrinsic::pow:
4741 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4742 getValue(I.getArgOperand(1)), DAG, TLI));
4744 case Intrinsic::sqrt:
4745 case Intrinsic::fabs:
4746 case Intrinsic::sin:
4747 case Intrinsic::cos:
4748 case Intrinsic::floor:
4749 case Intrinsic::ceil:
4750 case Intrinsic::trunc:
4751 case Intrinsic::rint:
4752 case Intrinsic::nearbyint:
4753 case Intrinsic::round: {
4755 switch (Intrinsic) {
4756 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4757 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4758 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4759 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4760 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4761 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4762 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4763 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4764 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4765 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4766 case Intrinsic::round: Opcode = ISD::FROUND; break;
4769 setValue(&I, DAG.getNode(Opcode, sdl,
4770 getValue(I.getArgOperand(0)).getValueType(),
4771 getValue(I.getArgOperand(0))));
4774 case Intrinsic::minnum:
4775 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4776 getValue(I.getArgOperand(0)).getValueType(),
4777 getValue(I.getArgOperand(0)),
4778 getValue(I.getArgOperand(1))));
4780 case Intrinsic::maxnum:
4781 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4782 getValue(I.getArgOperand(0)).getValueType(),
4783 getValue(I.getArgOperand(0)),
4784 getValue(I.getArgOperand(1))));
4786 case Intrinsic::copysign:
4787 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4788 getValue(I.getArgOperand(0)).getValueType(),
4789 getValue(I.getArgOperand(0)),
4790 getValue(I.getArgOperand(1))));
4792 case Intrinsic::fma:
4793 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4794 getValue(I.getArgOperand(0)).getValueType(),
4795 getValue(I.getArgOperand(0)),
4796 getValue(I.getArgOperand(1)),
4797 getValue(I.getArgOperand(2))));
4799 case Intrinsic::fmuladd: {
4800 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4801 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4802 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4803 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4804 getValue(I.getArgOperand(0)).getValueType(),
4805 getValue(I.getArgOperand(0)),
4806 getValue(I.getArgOperand(1)),
4807 getValue(I.getArgOperand(2))));
4809 // TODO: Intrinsic calls should have fast-math-flags.
4810 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4811 getValue(I.getArgOperand(0)).getValueType(),
4812 getValue(I.getArgOperand(0)),
4813 getValue(I.getArgOperand(1)));
4814 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4815 getValue(I.getArgOperand(0)).getValueType(),
4817 getValue(I.getArgOperand(2)));
4822 case Intrinsic::convert_to_fp16:
4823 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4824 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4825 getValue(I.getArgOperand(0)),
4826 DAG.getTargetConstant(0, sdl,
4829 case Intrinsic::convert_from_fp16:
4830 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4831 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4832 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4833 getValue(I.getArgOperand(0)))));
4835 case Intrinsic::pcmarker: {
4836 SDValue Tmp = getValue(I.getArgOperand(0));
4837 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4840 case Intrinsic::readcyclecounter: {
4841 SDValue Op = getRoot();
4842 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4843 DAG.getVTList(MVT::i64, MVT::Other), Op);
4845 DAG.setRoot(Res.getValue(1));
4848 case Intrinsic::bswap:
4849 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4850 getValue(I.getArgOperand(0)).getValueType(),
4851 getValue(I.getArgOperand(0))));
4853 case Intrinsic::uabsdiff:
4854 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4855 getValue(I.getArgOperand(0)).getValueType(),
4856 getValue(I.getArgOperand(0)),
4857 getValue(I.getArgOperand(1))));
4859 case Intrinsic::sabsdiff:
4860 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4861 getValue(I.getArgOperand(0)).getValueType(),
4862 getValue(I.getArgOperand(0)),
4863 getValue(I.getArgOperand(1))));
4865 case Intrinsic::cttz: {
4866 SDValue Arg = getValue(I.getArgOperand(0));
4867 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4868 EVT Ty = Arg.getValueType();
4869 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4873 case Intrinsic::ctlz: {
4874 SDValue Arg = getValue(I.getArgOperand(0));
4875 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4876 EVT Ty = Arg.getValueType();
4877 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4881 case Intrinsic::ctpop: {
4882 SDValue Arg = getValue(I.getArgOperand(0));
4883 EVT Ty = Arg.getValueType();
4884 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4887 case Intrinsic::stacksave: {
4888 SDValue Op = getRoot();
4890 ISD::STACKSAVE, sdl,
4891 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4893 DAG.setRoot(Res.getValue(1));
4896 case Intrinsic::stackrestore: {
4897 Res = getValue(I.getArgOperand(0));
4898 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4901 case Intrinsic::stackprotector: {
4902 // Emit code into the DAG to store the stack guard onto the stack.
4903 MachineFunction &MF = DAG.getMachineFunction();
4904 MachineFrameInfo *MFI = MF.getFrameInfo();
4905 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4906 SDValue Src, Chain = getRoot();
4907 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4908 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4910 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4911 // global variable __stack_chk_guard.
4913 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4914 if (BC->getOpcode() == Instruction::BitCast)
4915 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4917 if (GV && TLI.useLoadStackGuardNode()) {
4918 // Emit a LOAD_STACK_GUARD node.
4919 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4921 MachinePointerInfo MPInfo(GV);
4922 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4923 unsigned Flags = MachineMemOperand::MOLoad |
4924 MachineMemOperand::MOInvariant;
4925 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4926 PtrTy.getSizeInBits() / 8,
4927 DAG.getEVTAlignment(PtrTy));
4928 Node->setMemRefs(MemRefs, MemRefs + 1);
4930 // Copy the guard value to a virtual register so that it can be
4931 // retrieved in the epilogue.
4932 Src = SDValue(Node, 0);
4933 const TargetRegisterClass *RC =
4934 TLI.getRegClassFor(Src.getSimpleValueType());
4935 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4937 SPDescriptor.setGuardReg(Reg);
4938 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4940 Src = getValue(I.getArgOperand(0)); // The guard's value.
4943 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4945 int FI = FuncInfo.StaticAllocaMap[Slot];
4946 MFI->setStackProtectorIndex(FI);
4948 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4950 // Store the stack protector onto the stack.
4951 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4952 DAG.getMachineFunction(), FI),
4958 case Intrinsic::objectsize: {
4959 // If we don't know by now, we're never going to know.
4960 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4962 assert(CI && "Non-constant type in __builtin_object_size?");
4964 SDValue Arg = getValue(I.getCalledValue());
4965 EVT Ty = Arg.getValueType();
4968 Res = DAG.getConstant(-1ULL, sdl, Ty);
4970 Res = DAG.getConstant(0, sdl, Ty);
4975 case Intrinsic::annotation:
4976 case Intrinsic::ptr_annotation:
4977 // Drop the intrinsic, but forward the value
4978 setValue(&I, getValue(I.getOperand(0)));
4980 case Intrinsic::assume:
4981 case Intrinsic::var_annotation:
4982 // Discard annotate attributes and assumptions
4985 case Intrinsic::init_trampoline: {
4986 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4990 Ops[1] = getValue(I.getArgOperand(0));
4991 Ops[2] = getValue(I.getArgOperand(1));
4992 Ops[3] = getValue(I.getArgOperand(2));
4993 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4994 Ops[5] = DAG.getSrcValue(F);
4996 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5001 case Intrinsic::adjust_trampoline: {
5002 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5003 TLI.getPointerTy(DAG.getDataLayout()),
5004 getValue(I.getArgOperand(0))));
5007 case Intrinsic::gcroot:
5009 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5010 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5012 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5013 GFI->addStackRoot(FI->getIndex(), TypeMap);
5016 case Intrinsic::gcread:
5017 case Intrinsic::gcwrite:
5018 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5019 case Intrinsic::flt_rounds:
5020 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5023 case Intrinsic::expect: {
5024 // Just replace __builtin_expect(exp, c) with EXP.
5025 setValue(&I, getValue(I.getArgOperand(0)));
5029 case Intrinsic::debugtrap:
5030 case Intrinsic::trap: {
5031 StringRef TrapFuncName =
5033 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5034 .getValueAsString();
5035 if (TrapFuncName.empty()) {
5036 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5037 ISD::TRAP : ISD::DEBUGTRAP;
5038 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5041 TargetLowering::ArgListTy Args;
5043 TargetLowering::CallLoweringInfo CLI(DAG);
5044 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5045 CallingConv::C, I.getType(),
5046 DAG.getExternalSymbol(TrapFuncName.data(),
5047 TLI.getPointerTy(DAG.getDataLayout())),
5048 std::move(Args), 0);
5050 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5051 DAG.setRoot(Result.second);
5055 case Intrinsic::uadd_with_overflow:
5056 case Intrinsic::sadd_with_overflow:
5057 case Intrinsic::usub_with_overflow:
5058 case Intrinsic::ssub_with_overflow:
5059 case Intrinsic::umul_with_overflow:
5060 case Intrinsic::smul_with_overflow: {
5062 switch (Intrinsic) {
5063 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5064 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5065 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5066 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5067 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5068 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5069 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5071 SDValue Op1 = getValue(I.getArgOperand(0));
5072 SDValue Op2 = getValue(I.getArgOperand(1));
5074 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5075 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5078 case Intrinsic::prefetch: {
5080 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5082 Ops[1] = getValue(I.getArgOperand(0));
5083 Ops[2] = getValue(I.getArgOperand(1));
5084 Ops[3] = getValue(I.getArgOperand(2));
5085 Ops[4] = getValue(I.getArgOperand(3));
5086 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5087 DAG.getVTList(MVT::Other), Ops,
5088 EVT::getIntegerVT(*Context, 8),
5089 MachinePointerInfo(I.getArgOperand(0)),
5091 false, /* volatile */
5093 rw==1)); /* write */
5096 case Intrinsic::lifetime_start:
5097 case Intrinsic::lifetime_end: {
5098 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5099 // Stack coloring is not enabled in O0, discard region information.
5100 if (TM.getOptLevel() == CodeGenOpt::None)
5103 SmallVector<Value *, 4> Allocas;
5104 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5106 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5107 E = Allocas.end(); Object != E; ++Object) {
5108 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5110 // Could not find an Alloca.
5111 if (!LifetimeObject)
5114 // First check that the Alloca is static, otherwise it won't have a
5115 // valid frame index.
5116 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5117 if (SI == FuncInfo.StaticAllocaMap.end())
5120 int FI = SI->second;
5125 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5126 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5128 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5133 case Intrinsic::invariant_start:
5134 // Discard region information.
5135 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5137 case Intrinsic::invariant_end:
5138 // Discard region information.
5140 case Intrinsic::stackprotectorcheck: {
5141 // Do not actually emit anything for this basic block. Instead we initialize
5142 // the stack protector descriptor and export the guard variable so we can
5143 // access it in FinishBasicBlock.
5144 const BasicBlock *BB = I.getParent();
5145 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5146 ExportFromCurrentBlock(SPDescriptor.getGuard());
5148 // Flush our exports since we are going to process a terminator.
5149 (void)getControlRoot();
5152 case Intrinsic::clear_cache:
5153 return TLI.getClearCacheBuiltinName();
5154 case Intrinsic::eh_actions:
5155 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5157 case Intrinsic::donothing:
5160 case Intrinsic::experimental_stackmap: {
5164 case Intrinsic::experimental_patchpoint_void:
5165 case Intrinsic::experimental_patchpoint_i64: {
5166 visitPatchpoint(&I);
5169 case Intrinsic::experimental_gc_statepoint: {
5173 case Intrinsic::experimental_gc_result_int:
5174 case Intrinsic::experimental_gc_result_float:
5175 case Intrinsic::experimental_gc_result_ptr:
5176 case Intrinsic::experimental_gc_result: {
5180 case Intrinsic::experimental_gc_relocate: {
5184 case Intrinsic::instrprof_increment:
5185 llvm_unreachable("instrprof failed to lower an increment");
5187 case Intrinsic::localescape: {
5188 MachineFunction &MF = DAG.getMachineFunction();
5189 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5191 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5192 // is the same on all targets.
5193 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5194 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5195 if (isa<ConstantPointerNull>(Arg))
5196 continue; // Skip null pointers. They represent a hole in index space.
5197 AllocaInst *Slot = cast<AllocaInst>(Arg);
5198 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5199 "can only escape static allocas");
5200 int FI = FuncInfo.StaticAllocaMap[Slot];
5201 MCSymbol *FrameAllocSym =
5202 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5203 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5204 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5205 TII->get(TargetOpcode::LOCAL_ESCAPE))
5206 .addSym(FrameAllocSym)
5213 case Intrinsic::localrecover: {
5214 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5215 MachineFunction &MF = DAG.getMachineFunction();
5216 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5218 // Get the symbol that defines the frame offset.
5219 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5220 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5221 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5222 MCSymbol *FrameAllocSym =
5223 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5224 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5226 // Create a MCSymbol for the label to avoid any target lowering
5227 // that would make this PC relative.
5228 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5230 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5232 // Add the offset to the FP.
5233 Value *FP = I.getArgOperand(1);
5234 SDValue FPVal = getValue(FP);
5235 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5240 case Intrinsic::eh_begincatch:
5241 case Intrinsic::eh_endcatch:
5242 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5243 case Intrinsic::eh_exceptioncode: {
5244 unsigned Reg = TLI.getExceptionPointerRegister();
5245 assert(Reg && "cannot get exception code on this platform");
5246 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5247 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5248 assert(FuncInfo.MBB->isEHPad() && "eh.exceptioncode in non-lpad");
5249 unsigned VReg = FuncInfo.MBB->addLiveIn(Reg, PtrRC);
5251 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5252 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5259 std::pair<SDValue, SDValue>
5260 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5261 const BasicBlock *EHPadBB) {
5262 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5263 MCSymbol *BeginLabel = nullptr;
5266 // Insert a label before the invoke call to mark the try range. This can be
5267 // used to detect deletion of the invoke via the MachineModuleInfo.
5268 BeginLabel = MMI.getContext().createTempSymbol();
5270 // For SjLj, keep track of which landing pads go with which invokes
5271 // so as to maintain the ordering of pads in the LSDA.
5272 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5273 if (CallSiteIndex) {
5274 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5275 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5277 // Now that the call site is handled, stop tracking it.
5278 MMI.setCurrentCallSite(0);
5281 // Both PendingLoads and PendingExports must be flushed here;
5282 // this call might not return.
5284 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5286 CLI.setChain(getRoot());
5288 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5289 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5291 assert((CLI.IsTailCall || Result.second.getNode()) &&
5292 "Non-null chain expected with non-tail call!");
5293 assert((Result.second.getNode() || !Result.first.getNode()) &&
5294 "Null value expected with tail call!");
5296 if (!Result.second.getNode()) {
5297 // As a special case, a null chain means that a tail call has been emitted
5298 // and the DAG root is already updated.
5301 // Since there's no actual continuation from this block, nothing can be
5302 // relying on us setting vregs for them.
5303 PendingExports.clear();
5305 DAG.setRoot(Result.second);
5309 // Insert a label at the end of the invoke call to mark the try range. This
5310 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5311 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5312 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5314 // Inform MachineModuleInfo of range.
5315 if (MMI.hasEHFunclets()) {
5316 WinEHFuncInfo &EHInfo =
5317 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5318 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5320 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5327 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5329 const BasicBlock *EHPadBB) {
5330 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5331 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5332 Type *RetTy = FTy->getReturnType();
5334 TargetLowering::ArgListTy Args;
5335 TargetLowering::ArgListEntry Entry;
5336 Args.reserve(CS.arg_size());
5338 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5340 const Value *V = *i;
5343 if (V->getType()->isEmptyTy())
5346 SDValue ArgNode = getValue(V);
5347 Entry.Node = ArgNode; Entry.Ty = V->getType();
5349 // Skip the first return-type Attribute to get to params.
5350 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5351 Args.push_back(Entry);
5353 // If we have an explicit sret argument that is an Instruction, (i.e., it
5354 // might point to function-local memory), we can't meaningfully tail-call.
5355 if (Entry.isSRet && isa<Instruction>(V))
5359 // Check if target-independent constraints permit a tail call here.
5360 // Target-dependent constraints are checked within TLI->LowerCallTo.
5361 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5364 TargetLowering::CallLoweringInfo CLI(DAG);
5365 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5366 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5367 .setTailCall(isTailCall);
5368 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5370 if (Result.first.getNode())
5371 setValue(CS.getInstruction(), Result.first);
5374 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5375 /// value is equal or not-equal to zero.
5376 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5377 for (const User *U : V->users()) {
5378 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5379 if (IC->isEquality())
5380 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5381 if (C->isNullValue())
5383 // Unknown instruction.
5389 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5391 SelectionDAGBuilder &Builder) {
5393 // Check to see if this load can be trivially constant folded, e.g. if the
5394 // input is from a string literal.
5395 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5396 // Cast pointer to the type we really want to load.
5397 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5398 PointerType::getUnqual(LoadTy));
5400 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5401 const_cast<Constant *>(LoadInput), *Builder.DL))
5402 return Builder.getValue(LoadCst);
5405 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5406 // still constant memory, the input chain can be the entry node.
5408 bool ConstantMemory = false;
5410 // Do not serialize (non-volatile) loads of constant memory with anything.
5411 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5412 Root = Builder.DAG.getEntryNode();
5413 ConstantMemory = true;
5415 // Do not serialize non-volatile loads against each other.
5416 Root = Builder.DAG.getRoot();
5419 SDValue Ptr = Builder.getValue(PtrVal);
5420 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5421 Ptr, MachinePointerInfo(PtrVal),
5423 false /*nontemporal*/,
5424 false /*isinvariant*/, 1 /* align=1 */);
5426 if (!ConstantMemory)
5427 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5431 /// processIntegerCallValue - Record the value for an instruction that
5432 /// produces an integer result, converting the type where necessary.
5433 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5436 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5439 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5441 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5442 setValue(&I, Value);
5445 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5446 /// If so, return true and lower it, otherwise return false and it will be
5447 /// lowered like a normal call.
5448 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5449 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5450 if (I.getNumArgOperands() != 3)
5453 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5454 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5455 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5456 !I.getType()->isIntegerTy())
5459 const Value *Size = I.getArgOperand(2);
5460 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5461 if (CSize && CSize->getZExtValue() == 0) {
5462 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5464 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5468 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5469 std::pair<SDValue, SDValue> Res =
5470 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5471 getValue(LHS), getValue(RHS), getValue(Size),
5472 MachinePointerInfo(LHS),
5473 MachinePointerInfo(RHS));
5474 if (Res.first.getNode()) {
5475 processIntegerCallValue(I, Res.first, true);
5476 PendingLoads.push_back(Res.second);
5480 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5481 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5482 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5483 bool ActuallyDoIt = true;
5486 switch (CSize->getZExtValue()) {
5488 LoadVT = MVT::Other;
5490 ActuallyDoIt = false;
5494 LoadTy = Type::getInt16Ty(CSize->getContext());
5498 LoadTy = Type::getInt32Ty(CSize->getContext());
5502 LoadTy = Type::getInt64Ty(CSize->getContext());
5506 LoadVT = MVT::v4i32;
5507 LoadTy = Type::getInt32Ty(CSize->getContext());
5508 LoadTy = VectorType::get(LoadTy, 4);
5513 // This turns into unaligned loads. We only do this if the target natively
5514 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5515 // we'll only produce a small number of byte loads.
5517 // Require that we can find a legal MVT, and only do this if the target
5518 // supports unaligned loads of that type. Expanding into byte loads would
5520 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5521 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5522 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5523 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5524 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5525 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5526 // TODO: Check alignment of src and dest ptrs.
5527 if (!TLI.isTypeLegal(LoadVT) ||
5528 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5529 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5530 ActuallyDoIt = false;
5534 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5535 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5537 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5539 processIntegerCallValue(I, Res, false);
5548 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5549 /// form. If so, return true and lower it, otherwise return false and it
5550 /// will be lowered like a normal call.
5551 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5552 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5553 if (I.getNumArgOperands() != 3)
5556 const Value *Src = I.getArgOperand(0);
5557 const Value *Char = I.getArgOperand(1);
5558 const Value *Length = I.getArgOperand(2);
5559 if (!Src->getType()->isPointerTy() ||
5560 !Char->getType()->isIntegerTy() ||
5561 !Length->getType()->isIntegerTy() ||
5562 !I.getType()->isPointerTy())
5565 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5566 std::pair<SDValue, SDValue> Res =
5567 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5568 getValue(Src), getValue(Char), getValue(Length),
5569 MachinePointerInfo(Src));
5570 if (Res.first.getNode()) {
5571 setValue(&I, Res.first);
5572 PendingLoads.push_back(Res.second);
5579 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5580 /// optimized form. If so, return true and lower it, otherwise return false
5581 /// and it will be lowered like a normal call.
5582 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5583 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5584 if (I.getNumArgOperands() != 2)
5587 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5588 if (!Arg0->getType()->isPointerTy() ||
5589 !Arg1->getType()->isPointerTy() ||
5590 !I.getType()->isPointerTy())
5593 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5594 std::pair<SDValue, SDValue> Res =
5595 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5596 getValue(Arg0), getValue(Arg1),
5597 MachinePointerInfo(Arg0),
5598 MachinePointerInfo(Arg1), isStpcpy);
5599 if (Res.first.getNode()) {
5600 setValue(&I, Res.first);
5601 DAG.setRoot(Res.second);
5608 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5609 /// If so, return true and lower it, otherwise return false and it will be
5610 /// lowered like a normal call.
5611 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5612 // Verify that the prototype makes sense. int strcmp(void*,void*)
5613 if (I.getNumArgOperands() != 2)
5616 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5617 if (!Arg0->getType()->isPointerTy() ||
5618 !Arg1->getType()->isPointerTy() ||
5619 !I.getType()->isIntegerTy())
5622 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5623 std::pair<SDValue, SDValue> Res =
5624 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5625 getValue(Arg0), getValue(Arg1),
5626 MachinePointerInfo(Arg0),
5627 MachinePointerInfo(Arg1));
5628 if (Res.first.getNode()) {
5629 processIntegerCallValue(I, Res.first, true);
5630 PendingLoads.push_back(Res.second);
5637 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5638 /// form. If so, return true and lower it, otherwise return false and it
5639 /// will be lowered like a normal call.
5640 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5641 // Verify that the prototype makes sense. size_t strlen(char *)
5642 if (I.getNumArgOperands() != 1)
5645 const Value *Arg0 = I.getArgOperand(0);
5646 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5649 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5650 std::pair<SDValue, SDValue> Res =
5651 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5652 getValue(Arg0), MachinePointerInfo(Arg0));
5653 if (Res.first.getNode()) {
5654 processIntegerCallValue(I, Res.first, false);
5655 PendingLoads.push_back(Res.second);
5662 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5663 /// form. If so, return true and lower it, otherwise return false and it
5664 /// will be lowered like a normal call.
5665 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5666 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5667 if (I.getNumArgOperands() != 2)
5670 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5671 if (!Arg0->getType()->isPointerTy() ||
5672 !Arg1->getType()->isIntegerTy() ||
5673 !I.getType()->isIntegerTy())
5676 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5677 std::pair<SDValue, SDValue> Res =
5678 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5679 getValue(Arg0), getValue(Arg1),
5680 MachinePointerInfo(Arg0));
5681 if (Res.first.getNode()) {
5682 processIntegerCallValue(I, Res.first, false);
5683 PendingLoads.push_back(Res.second);
5690 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5691 /// operation (as expected), translate it to an SDNode with the specified opcode
5692 /// and return true.
5693 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5695 // Sanity check that it really is a unary floating-point call.
5696 if (I.getNumArgOperands() != 1 ||
5697 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5698 I.getType() != I.getArgOperand(0)->getType() ||
5699 !I.onlyReadsMemory())
5702 SDValue Tmp = getValue(I.getArgOperand(0));
5703 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5707 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5708 /// operation (as expected), translate it to an SDNode with the specified opcode
5709 /// and return true.
5710 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5712 // Sanity check that it really is a binary floating-point call.
5713 if (I.getNumArgOperands() != 2 ||
5714 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5715 I.getType() != I.getArgOperand(0)->getType() ||
5716 I.getType() != I.getArgOperand(1)->getType() ||
5717 !I.onlyReadsMemory())
5720 SDValue Tmp0 = getValue(I.getArgOperand(0));
5721 SDValue Tmp1 = getValue(I.getArgOperand(1));
5722 EVT VT = Tmp0.getValueType();
5723 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5727 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5728 // Handle inline assembly differently.
5729 if (isa<InlineAsm>(I.getCalledValue())) {
5734 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5735 ComputeUsesVAFloatArgument(I, &MMI);
5737 const char *RenameFn = nullptr;
5738 if (Function *F = I.getCalledFunction()) {
5739 if (F->isDeclaration()) {
5740 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5741 if (unsigned IID = II->getIntrinsicID(F)) {
5742 RenameFn = visitIntrinsicCall(I, IID);
5747 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5748 RenameFn = visitIntrinsicCall(I, IID);
5754 // Check for well-known libc/libm calls. If the function is internal, it
5755 // can't be a library call.
5757 if (!F->hasLocalLinkage() && F->hasName() &&
5758 LibInfo->getLibFunc(F->getName(), Func) &&
5759 LibInfo->hasOptimizedCodeGen(Func)) {
5762 case LibFunc::copysign:
5763 case LibFunc::copysignf:
5764 case LibFunc::copysignl:
5765 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5766 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5767 I.getType() == I.getArgOperand(0)->getType() &&
5768 I.getType() == I.getArgOperand(1)->getType() &&
5769 I.onlyReadsMemory()) {
5770 SDValue LHS = getValue(I.getArgOperand(0));
5771 SDValue RHS = getValue(I.getArgOperand(1));
5772 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5773 LHS.getValueType(), LHS, RHS));
5778 case LibFunc::fabsf:
5779 case LibFunc::fabsl:
5780 if (visitUnaryFloatCall(I, ISD::FABS))
5784 case LibFunc::fminf:
5785 case LibFunc::fminl:
5786 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5790 case LibFunc::fmaxf:
5791 case LibFunc::fmaxl:
5792 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5798 if (visitUnaryFloatCall(I, ISD::FSIN))
5804 if (visitUnaryFloatCall(I, ISD::FCOS))
5808 case LibFunc::sqrtf:
5809 case LibFunc::sqrtl:
5810 case LibFunc::sqrt_finite:
5811 case LibFunc::sqrtf_finite:
5812 case LibFunc::sqrtl_finite:
5813 if (visitUnaryFloatCall(I, ISD::FSQRT))
5816 case LibFunc::floor:
5817 case LibFunc::floorf:
5818 case LibFunc::floorl:
5819 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5822 case LibFunc::nearbyint:
5823 case LibFunc::nearbyintf:
5824 case LibFunc::nearbyintl:
5825 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5829 case LibFunc::ceilf:
5830 case LibFunc::ceill:
5831 if (visitUnaryFloatCall(I, ISD::FCEIL))
5835 case LibFunc::rintf:
5836 case LibFunc::rintl:
5837 if (visitUnaryFloatCall(I, ISD::FRINT))
5840 case LibFunc::round:
5841 case LibFunc::roundf:
5842 case LibFunc::roundl:
5843 if (visitUnaryFloatCall(I, ISD::FROUND))
5846 case LibFunc::trunc:
5847 case LibFunc::truncf:
5848 case LibFunc::truncl:
5849 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5853 case LibFunc::log2f:
5854 case LibFunc::log2l:
5855 if (visitUnaryFloatCall(I, ISD::FLOG2))
5859 case LibFunc::exp2f:
5860 case LibFunc::exp2l:
5861 if (visitUnaryFloatCall(I, ISD::FEXP2))
5864 case LibFunc::memcmp:
5865 if (visitMemCmpCall(I))
5868 case LibFunc::memchr:
5869 if (visitMemChrCall(I))
5872 case LibFunc::strcpy:
5873 if (visitStrCpyCall(I, false))
5876 case LibFunc::stpcpy:
5877 if (visitStrCpyCall(I, true))
5880 case LibFunc::strcmp:
5881 if (visitStrCmpCall(I))
5884 case LibFunc::strlen:
5885 if (visitStrLenCall(I))
5888 case LibFunc::strnlen:
5889 if (visitStrNLenCall(I))
5898 Callee = getValue(I.getCalledValue());
5900 Callee = DAG.getExternalSymbol(
5902 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5904 // Check if we can potentially perform a tail call. More detailed checking is
5905 // be done within LowerCallTo, after more information about the call is known.
5906 LowerCallTo(&I, Callee, I.isTailCall());
5911 /// AsmOperandInfo - This contains information for each constraint that we are
5913 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5915 /// CallOperand - If this is the result output operand or a clobber
5916 /// this is null, otherwise it is the incoming operand to the CallInst.
5917 /// This gets modified as the asm is processed.
5918 SDValue CallOperand;
5920 /// AssignedRegs - If this is a register or register class operand, this
5921 /// contains the set of register corresponding to the operand.
5922 RegsForValue AssignedRegs;
5924 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5925 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5928 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5929 /// corresponds to. If there is no Value* for this operand, it returns
5931 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5932 const DataLayout &DL) const {
5933 if (!CallOperandVal) return MVT::Other;
5935 if (isa<BasicBlock>(CallOperandVal))
5936 return TLI.getPointerTy(DL);
5938 llvm::Type *OpTy = CallOperandVal->getType();
5940 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5941 // If this is an indirect operand, the operand is a pointer to the
5944 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5946 report_fatal_error("Indirect operand for inline asm not a pointer!");
5947 OpTy = PtrTy->getElementType();
5950 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5951 if (StructType *STy = dyn_cast<StructType>(OpTy))
5952 if (STy->getNumElements() == 1)
5953 OpTy = STy->getElementType(0);
5955 // If OpTy is not a single value, it may be a struct/union that we
5956 // can tile with integers.
5957 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5958 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5967 OpTy = IntegerType::get(Context, BitSize);
5972 return TLI.getValueType(DL, OpTy, true);
5976 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5978 } // end anonymous namespace
5980 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5981 /// specified operand. We prefer to assign virtual registers, to allow the
5982 /// register allocator to handle the assignment process. However, if the asm
5983 /// uses features that we can't model on machineinstrs, we have SDISel do the
5984 /// allocation. This produces generally horrible, but correct, code.
5986 /// OpInfo describes the operand.
5988 static void GetRegistersForValue(SelectionDAG &DAG,
5989 const TargetLowering &TLI,
5991 SDISelAsmOperandInfo &OpInfo) {
5992 LLVMContext &Context = *DAG.getContext();
5994 MachineFunction &MF = DAG.getMachineFunction();
5995 SmallVector<unsigned, 4> Regs;
5997 // If this is a constraint for a single physreg, or a constraint for a
5998 // register class, find it.
5999 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6000 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6001 OpInfo.ConstraintCode,
6002 OpInfo.ConstraintVT);
6004 unsigned NumRegs = 1;
6005 if (OpInfo.ConstraintVT != MVT::Other) {
6006 // If this is a FP input in an integer register (or visa versa) insert a bit
6007 // cast of the input value. More generally, handle any case where the input
6008 // value disagrees with the register class we plan to stick this in.
6009 if (OpInfo.Type == InlineAsm::isInput &&
6010 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6011 // Try to convert to the first EVT that the reg class contains. If the
6012 // types are identical size, use a bitcast to convert (e.g. two differing
6014 MVT RegVT = *PhysReg.second->vt_begin();
6015 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6016 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6017 RegVT, OpInfo.CallOperand);
6018 OpInfo.ConstraintVT = RegVT;
6019 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6020 // If the input is a FP value and we want it in FP registers, do a
6021 // bitcast to the corresponding integer type. This turns an f64 value
6022 // into i64, which can be passed with two i32 values on a 32-bit
6024 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6025 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6026 RegVT, OpInfo.CallOperand);
6027 OpInfo.ConstraintVT = RegVT;
6031 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6035 EVT ValueVT = OpInfo.ConstraintVT;
6037 // If this is a constraint for a specific physical register, like {r17},
6039 if (unsigned AssignedReg = PhysReg.first) {
6040 const TargetRegisterClass *RC = PhysReg.second;
6041 if (OpInfo.ConstraintVT == MVT::Other)
6042 ValueVT = *RC->vt_begin();
6044 // Get the actual register value type. This is important, because the user
6045 // may have asked for (e.g.) the AX register in i32 type. We need to
6046 // remember that AX is actually i16 to get the right extension.
6047 RegVT = *RC->vt_begin();
6049 // This is a explicit reference to a physical register.
6050 Regs.push_back(AssignedReg);
6052 // If this is an expanded reference, add the rest of the regs to Regs.
6054 TargetRegisterClass::iterator I = RC->begin();
6055 for (; *I != AssignedReg; ++I)
6056 assert(I != RC->end() && "Didn't find reg!");
6058 // Already added the first reg.
6060 for (; NumRegs; --NumRegs, ++I) {
6061 assert(I != RC->end() && "Ran out of registers to allocate!");
6066 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6070 // Otherwise, if this was a reference to an LLVM register class, create vregs
6071 // for this reference.
6072 if (const TargetRegisterClass *RC = PhysReg.second) {
6073 RegVT = *RC->vt_begin();
6074 if (OpInfo.ConstraintVT == MVT::Other)
6077 // Create the appropriate number of virtual registers.
6078 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6079 for (; NumRegs; --NumRegs)
6080 Regs.push_back(RegInfo.createVirtualRegister(RC));
6082 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6086 // Otherwise, we couldn't allocate enough registers for this.
6089 /// visitInlineAsm - Handle a call to an InlineAsm object.
6091 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6092 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6094 /// ConstraintOperands - Information about all of the constraints.
6095 SDISelAsmOperandInfoVector ConstraintOperands;
6097 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6098 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6099 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6101 bool hasMemory = false;
6103 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6104 unsigned ResNo = 0; // ResNo - The result number of the next output.
6105 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6106 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6107 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6109 MVT OpVT = MVT::Other;
6111 // Compute the value type for each operand.
6112 switch (OpInfo.Type) {
6113 case InlineAsm::isOutput:
6114 // Indirect outputs just consume an argument.
6115 if (OpInfo.isIndirect) {
6116 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6120 // The return value of the call is this value. As such, there is no
6121 // corresponding argument.
6122 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6123 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6124 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6125 STy->getElementType(ResNo));
6127 assert(ResNo == 0 && "Asm only has one result!");
6128 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6132 case InlineAsm::isInput:
6133 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6135 case InlineAsm::isClobber:
6140 // If this is an input or an indirect output, process the call argument.
6141 // BasicBlocks are labels, currently appearing only in asm's.
6142 if (OpInfo.CallOperandVal) {
6143 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6144 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6146 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6149 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6150 DAG.getDataLayout()).getSimpleVT();
6153 OpInfo.ConstraintVT = OpVT;
6155 // Indirect operand accesses access memory.
6156 if (OpInfo.isIndirect)
6159 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6160 TargetLowering::ConstraintType
6161 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6162 if (CType == TargetLowering::C_Memory) {
6170 SDValue Chain, Flag;
6172 // We won't need to flush pending loads if this asm doesn't touch
6173 // memory and is nonvolatile.
6174 if (hasMemory || IA->hasSideEffects())
6177 Chain = DAG.getRoot();
6179 // Second pass over the constraints: compute which constraint option to use
6180 // and assign registers to constraints that want a specific physreg.
6181 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6182 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6184 // If this is an output operand with a matching input operand, look up the
6185 // matching input. If their types mismatch, e.g. one is an integer, the
6186 // other is floating point, or their sizes are different, flag it as an
6188 if (OpInfo.hasMatchingInput()) {
6189 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6191 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6192 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6193 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6194 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6195 OpInfo.ConstraintVT);
6196 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6197 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6198 Input.ConstraintVT);
6199 if ((OpInfo.ConstraintVT.isInteger() !=
6200 Input.ConstraintVT.isInteger()) ||
6201 (MatchRC.second != InputRC.second)) {
6202 report_fatal_error("Unsupported asm: input constraint"
6203 " with a matching output constraint of"
6204 " incompatible type!");
6206 Input.ConstraintVT = OpInfo.ConstraintVT;
6210 // Compute the constraint code and ConstraintType to use.
6211 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6213 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6214 OpInfo.Type == InlineAsm::isClobber)
6217 // If this is a memory input, and if the operand is not indirect, do what we
6218 // need to to provide an address for the memory input.
6219 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6220 !OpInfo.isIndirect) {
6221 assert((OpInfo.isMultipleAlternative ||
6222 (OpInfo.Type == InlineAsm::isInput)) &&
6223 "Can only indirectify direct input operands!");
6225 // Memory operands really want the address of the value. If we don't have
6226 // an indirect input, put it in the constpool if we can, otherwise spill
6227 // it to a stack slot.
6228 // TODO: This isn't quite right. We need to handle these according to
6229 // the addressing mode that the constraint wants. Also, this may take
6230 // an additional register for the computation and we don't want that
6233 // If the operand is a float, integer, or vector constant, spill to a
6234 // constant pool entry to get its address.
6235 const Value *OpVal = OpInfo.CallOperandVal;
6236 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6237 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6238 OpInfo.CallOperand = DAG.getConstantPool(
6239 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6241 // Otherwise, create a stack slot and emit a store to it before the
6243 Type *Ty = OpVal->getType();
6244 auto &DL = DAG.getDataLayout();
6245 uint64_t TySize = DL.getTypeAllocSize(Ty);
6246 unsigned Align = DL.getPrefTypeAlignment(Ty);
6247 MachineFunction &MF = DAG.getMachineFunction();
6248 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6250 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6251 Chain = DAG.getStore(
6252 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6253 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6255 OpInfo.CallOperand = StackSlot;
6258 // There is no longer a Value* corresponding to this operand.
6259 OpInfo.CallOperandVal = nullptr;
6261 // It is now an indirect operand.
6262 OpInfo.isIndirect = true;
6265 // If this constraint is for a specific register, allocate it before
6267 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6268 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6271 // Second pass - Loop over all of the operands, assigning virtual or physregs
6272 // to register class operands.
6273 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6274 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6276 // C_Register operands have already been allocated, Other/Memory don't need
6278 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6279 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6282 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6283 std::vector<SDValue> AsmNodeOperands;
6284 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6285 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6286 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6288 // If we have a !srcloc metadata node associated with it, we want to attach
6289 // this to the ultimately generated inline asm machineinstr. To do this, we
6290 // pass in the third operand as this (potentially null) inline asm MDNode.
6291 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6292 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6294 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6295 // bits as operand 3.
6296 unsigned ExtraInfo = 0;
6297 if (IA->hasSideEffects())
6298 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6299 if (IA->isAlignStack())
6300 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6301 // Set the asm dialect.
6302 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6304 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6305 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6306 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6308 // Compute the constraint code and ConstraintType to use.
6309 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6311 // Ideally, we would only check against memory constraints. However, the
6312 // meaning of an other constraint can be target-specific and we can't easily
6313 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6314 // for other constriants as well.
6315 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6316 OpInfo.ConstraintType == TargetLowering::C_Other) {
6317 if (OpInfo.Type == InlineAsm::isInput)
6318 ExtraInfo |= InlineAsm::Extra_MayLoad;
6319 else if (OpInfo.Type == InlineAsm::isOutput)
6320 ExtraInfo |= InlineAsm::Extra_MayStore;
6321 else if (OpInfo.Type == InlineAsm::isClobber)
6322 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6326 AsmNodeOperands.push_back(DAG.getTargetConstant(
6327 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6329 // Loop over all of the inputs, copying the operand values into the
6330 // appropriate registers and processing the output regs.
6331 RegsForValue RetValRegs;
6333 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6334 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6336 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6337 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6339 switch (OpInfo.Type) {
6340 case InlineAsm::isOutput: {
6341 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6342 OpInfo.ConstraintType != TargetLowering::C_Register) {
6343 // Memory output, or 'other' output (e.g. 'X' constraint).
6344 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6346 unsigned ConstraintID =
6347 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6348 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6349 "Failed to convert memory constraint code to constraint id.");
6351 // Add information to the INLINEASM node to know about this output.
6352 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6353 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6354 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6356 AsmNodeOperands.push_back(OpInfo.CallOperand);
6360 // Otherwise, this is a register or register class output.
6362 // Copy the output from the appropriate register. Find a register that
6364 if (OpInfo.AssignedRegs.Regs.empty()) {
6365 LLVMContext &Ctx = *DAG.getContext();
6366 Ctx.emitError(CS.getInstruction(),
6367 "couldn't allocate output register for constraint '" +
6368 Twine(OpInfo.ConstraintCode) + "'");
6372 // If this is an indirect operand, store through the pointer after the
6374 if (OpInfo.isIndirect) {
6375 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6376 OpInfo.CallOperandVal));
6378 // This is the result value of the call.
6379 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6380 // Concatenate this output onto the outputs list.
6381 RetValRegs.append(OpInfo.AssignedRegs);
6384 // Add information to the INLINEASM node to know that this register is
6387 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6388 ? InlineAsm::Kind_RegDefEarlyClobber
6389 : InlineAsm::Kind_RegDef,
6390 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6393 case InlineAsm::isInput: {
6394 SDValue InOperandVal = OpInfo.CallOperand;
6396 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6397 // If this is required to match an output register we have already set,
6398 // just use its register.
6399 unsigned OperandNo = OpInfo.getMatchedOperand();
6401 // Scan until we find the definition we already emitted of this operand.
6402 // When we find it, create a RegsForValue operand.
6403 unsigned CurOp = InlineAsm::Op_FirstOperand;
6404 for (; OperandNo; --OperandNo) {
6405 // Advance to the next operand.
6407 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6408 assert((InlineAsm::isRegDefKind(OpFlag) ||
6409 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6410 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6411 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6415 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6416 if (InlineAsm::isRegDefKind(OpFlag) ||
6417 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6418 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6419 if (OpInfo.isIndirect) {
6420 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6421 LLVMContext &Ctx = *DAG.getContext();
6422 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6423 " don't know how to handle tied "
6424 "indirect register inputs");
6428 RegsForValue MatchedRegs;
6429 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6430 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6431 MatchedRegs.RegVTs.push_back(RegVT);
6432 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6433 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6435 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6436 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6438 LLVMContext &Ctx = *DAG.getContext();
6439 Ctx.emitError(CS.getInstruction(),
6440 "inline asm error: This value"
6441 " type register class is not natively supported!");
6445 SDLoc dl = getCurSDLoc();
6446 // Use the produced MatchedRegs object to
6447 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6448 Chain, &Flag, CS.getInstruction());
6449 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6450 true, OpInfo.getMatchedOperand(), dl,
6451 DAG, AsmNodeOperands);
6455 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6456 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6457 "Unexpected number of operands");
6458 // Add information to the INLINEASM node to know about this input.
6459 // See InlineAsm.h isUseOperandTiedToDef.
6460 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6461 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6462 OpInfo.getMatchedOperand());
6463 AsmNodeOperands.push_back(DAG.getTargetConstant(
6464 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6465 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6469 // Treat indirect 'X' constraint as memory.
6470 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6472 OpInfo.ConstraintType = TargetLowering::C_Memory;
6474 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6475 std::vector<SDValue> Ops;
6476 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6479 LLVMContext &Ctx = *DAG.getContext();
6480 Ctx.emitError(CS.getInstruction(),
6481 "invalid operand for inline asm constraint '" +
6482 Twine(OpInfo.ConstraintCode) + "'");
6486 // Add information to the INLINEASM node to know about this input.
6487 unsigned ResOpType =
6488 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6489 AsmNodeOperands.push_back(DAG.getTargetConstant(
6490 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6491 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6495 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6496 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6497 assert(InOperandVal.getValueType() ==
6498 TLI.getPointerTy(DAG.getDataLayout()) &&
6499 "Memory operands expect pointer values");
6501 unsigned ConstraintID =
6502 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6503 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6504 "Failed to convert memory constraint code to constraint id.");
6506 // Add information to the INLINEASM node to know about this input.
6507 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6508 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6509 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6512 AsmNodeOperands.push_back(InOperandVal);
6516 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6517 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6518 "Unknown constraint type!");
6520 // TODO: Support this.
6521 if (OpInfo.isIndirect) {
6522 LLVMContext &Ctx = *DAG.getContext();
6523 Ctx.emitError(CS.getInstruction(),
6524 "Don't know how to handle indirect register inputs yet "
6525 "for constraint '" +
6526 Twine(OpInfo.ConstraintCode) + "'");
6530 // Copy the input into the appropriate registers.
6531 if (OpInfo.AssignedRegs.Regs.empty()) {
6532 LLVMContext &Ctx = *DAG.getContext();
6533 Ctx.emitError(CS.getInstruction(),
6534 "couldn't allocate input reg for constraint '" +
6535 Twine(OpInfo.ConstraintCode) + "'");
6539 SDLoc dl = getCurSDLoc();
6541 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6542 Chain, &Flag, CS.getInstruction());
6544 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6545 dl, DAG, AsmNodeOperands);
6548 case InlineAsm::isClobber: {
6549 // Add the clobbered value to the operand list, so that the register
6550 // allocator is aware that the physreg got clobbered.
6551 if (!OpInfo.AssignedRegs.Regs.empty())
6552 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6553 false, 0, getCurSDLoc(), DAG,
6560 // Finish up input operands. Set the input chain and add the flag last.
6561 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6562 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6564 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6565 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6566 Flag = Chain.getValue(1);
6568 // If this asm returns a register value, copy the result from that register
6569 // and set it as the value of the call.
6570 if (!RetValRegs.Regs.empty()) {
6571 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6572 Chain, &Flag, CS.getInstruction());
6574 // FIXME: Why don't we do this for inline asms with MRVs?
6575 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6576 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6578 // If any of the results of the inline asm is a vector, it may have the
6579 // wrong width/num elts. This can happen for register classes that can
6580 // contain multiple different value types. The preg or vreg allocated may
6581 // not have the same VT as was expected. Convert it to the right type
6582 // with bit_convert.
6583 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6584 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6587 } else if (ResultType != Val.getValueType() &&
6588 ResultType.isInteger() && Val.getValueType().isInteger()) {
6589 // If a result value was tied to an input value, the computed result may
6590 // have a wider width than the expected result. Extract the relevant
6592 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6595 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6598 setValue(CS.getInstruction(), Val);
6599 // Don't need to use this as a chain in this case.
6600 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6604 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6606 // Process indirect outputs, first output all of the flagged copies out of
6608 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6609 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6610 const Value *Ptr = IndirectStoresToEmit[i].second;
6611 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6613 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6616 // Emit the non-flagged stores from the physregs.
6617 SmallVector<SDValue, 8> OutChains;
6618 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6619 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6620 StoresToEmit[i].first,
6621 getValue(StoresToEmit[i].second),
6622 MachinePointerInfo(StoresToEmit[i].second),
6624 OutChains.push_back(Val);
6627 if (!OutChains.empty())
6628 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6633 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6634 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6635 MVT::Other, getRoot(),
6636 getValue(I.getArgOperand(0)),
6637 DAG.getSrcValue(I.getArgOperand(0))));
6640 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6642 const DataLayout &DL = DAG.getDataLayout();
6643 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6644 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6645 DAG.getSrcValue(I.getOperand(0)),
6646 DL.getABITypeAlignment(I.getType()));
6648 DAG.setRoot(V.getValue(1));
6651 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6652 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6653 MVT::Other, getRoot(),
6654 getValue(I.getArgOperand(0)),
6655 DAG.getSrcValue(I.getArgOperand(0))));
6658 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6659 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6660 MVT::Other, getRoot(),
6661 getValue(I.getArgOperand(0)),
6662 getValue(I.getArgOperand(1)),
6663 DAG.getSrcValue(I.getArgOperand(0)),
6664 DAG.getSrcValue(I.getArgOperand(1))));
6667 /// \brief Lower an argument list according to the target calling convention.
6669 /// \return A tuple of <return-value, token-chain>
6671 /// This is a helper for lowering intrinsics that follow a target calling
6672 /// convention or require stack pointer adjustment. Only a subset of the
6673 /// intrinsic's operands need to participate in the calling convention.
6674 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6675 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6676 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6677 TargetLowering::ArgListTy Args;
6678 Args.reserve(NumArgs);
6680 // Populate the argument list.
6681 // Attributes for args start at offset 1, after the return attribute.
6682 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6683 ArgI != ArgE; ++ArgI) {
6684 const Value *V = CS->getOperand(ArgI);
6686 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6688 TargetLowering::ArgListEntry Entry;
6689 Entry.Node = getValue(V);
6690 Entry.Ty = V->getType();
6691 Entry.setAttributes(&CS, AttrI);
6692 Args.push_back(Entry);
6695 TargetLowering::CallLoweringInfo CLI(DAG);
6696 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6697 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6698 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6700 return lowerInvokable(CLI, EHPadBB);
6703 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6704 /// or patchpoint target node's operand list.
6706 /// Constants are converted to TargetConstants purely as an optimization to
6707 /// avoid constant materialization and register allocation.
6709 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6710 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6711 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6712 /// address materialization and register allocation, but may also be required
6713 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6714 /// alloca in the entry block, then the runtime may assume that the alloca's
6715 /// StackMap location can be read immediately after compilation and that the
6716 /// location is valid at any point during execution (this is similar to the
6717 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6718 /// only available in a register, then the runtime would need to trap when
6719 /// execution reaches the StackMap in order to read the alloca's location.
6720 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6721 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6722 SelectionDAGBuilder &Builder) {
6723 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6724 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6725 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6727 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6729 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6730 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6731 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6732 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6733 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6735 Ops.push_back(OpVal);
6739 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6740 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6741 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6742 // [live variables...])
6744 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6746 SDValue Chain, InFlag, Callee, NullPtr;
6747 SmallVector<SDValue, 32> Ops;
6749 SDLoc DL = getCurSDLoc();
6750 Callee = getValue(CI.getCalledValue());
6751 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6753 // The stackmap intrinsic only records the live variables (the arguemnts
6754 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6755 // intrinsic, this won't be lowered to a function call. This means we don't
6756 // have to worry about calling conventions and target specific lowering code.
6757 // Instead we perform the call lowering right here.
6759 // chain, flag = CALLSEQ_START(chain, 0)
6760 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6761 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6763 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6764 InFlag = Chain.getValue(1);
6766 // Add the <id> and <numBytes> constants.
6767 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6768 Ops.push_back(DAG.getTargetConstant(
6769 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6770 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6771 Ops.push_back(DAG.getTargetConstant(
6772 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6775 // Push live variables for the stack map.
6776 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6778 // We are not pushing any register mask info here on the operands list,
6779 // because the stackmap doesn't clobber anything.
6781 // Push the chain and the glue flag.
6782 Ops.push_back(Chain);
6783 Ops.push_back(InFlag);
6785 // Create the STACKMAP node.
6786 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6787 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6788 Chain = SDValue(SM, 0);
6789 InFlag = Chain.getValue(1);
6791 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6793 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6795 // Set the root to the target-lowered call chain.
6798 // Inform the Frame Information that we have a stackmap in this function.
6799 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6802 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6803 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6804 const BasicBlock *EHPadBB) {
6805 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6810 // [live variables...])
6812 CallingConv::ID CC = CS.getCallingConv();
6813 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6814 bool HasDef = !CS->getType()->isVoidTy();
6815 SDLoc dl = getCurSDLoc();
6816 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6818 // Handle immediate and symbolic callees.
6819 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6820 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6822 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6823 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6824 SDLoc(SymbolicCallee),
6825 SymbolicCallee->getValueType(0));
6827 // Get the real number of arguments participating in the call <numArgs>
6828 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6829 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6831 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6832 // Intrinsics include all meta-operands up to but not including CC.
6833 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6834 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6835 "Not enough arguments provided to the patchpoint intrinsic");
6837 // For AnyRegCC the arguments are lowered later on manually.
6838 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6840 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6841 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6842 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6844 SDNode *CallEnd = Result.second.getNode();
6845 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6846 CallEnd = CallEnd->getOperand(0).getNode();
6848 /// Get a call instruction from the call sequence chain.
6849 /// Tail calls are not allowed.
6850 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6851 "Expected a callseq node.");
6852 SDNode *Call = CallEnd->getOperand(0).getNode();
6853 bool HasGlue = Call->getGluedNode();
6855 // Replace the target specific call node with the patchable intrinsic.
6856 SmallVector<SDValue, 8> Ops;
6858 // Add the <id> and <numBytes> constants.
6859 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6860 Ops.push_back(DAG.getTargetConstant(
6861 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6862 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6863 Ops.push_back(DAG.getTargetConstant(
6864 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6868 Ops.push_back(Callee);
6870 // Adjust <numArgs> to account for any arguments that have been passed on the
6872 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6873 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6874 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6875 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6877 // Add the calling convention
6878 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6880 // Add the arguments we omitted previously. The register allocator should
6881 // place these in any free register.
6883 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6884 Ops.push_back(getValue(CS.getArgument(i)));
6886 // Push the arguments from the call instruction up to the register mask.
6887 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6888 Ops.append(Call->op_begin() + 2, e);
6890 // Push live variables for the stack map.
6891 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6893 // Push the register mask info.
6895 Ops.push_back(*(Call->op_end()-2));
6897 Ops.push_back(*(Call->op_end()-1));
6899 // Push the chain (this is originally the first operand of the call, but
6900 // becomes now the last or second to last operand).
6901 Ops.push_back(*(Call->op_begin()));
6903 // Push the glue flag (last operand).
6905 Ops.push_back(*(Call->op_end()-1));
6908 if (IsAnyRegCC && HasDef) {
6909 // Create the return types based on the intrinsic definition
6910 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6911 SmallVector<EVT, 3> ValueVTs;
6912 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6913 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6915 // There is always a chain and a glue type at the end
6916 ValueVTs.push_back(MVT::Other);
6917 ValueVTs.push_back(MVT::Glue);
6918 NodeTys = DAG.getVTList(ValueVTs);
6920 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6922 // Replace the target specific call node with a PATCHPOINT node.
6923 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6926 // Update the NodeMap.
6929 setValue(CS.getInstruction(), SDValue(MN, 0));
6931 setValue(CS.getInstruction(), Result.first);
6934 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6935 // call sequence. Furthermore the location of the chain and glue can change
6936 // when the AnyReg calling convention is used and the intrinsic returns a
6938 if (IsAnyRegCC && HasDef) {
6939 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6940 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6941 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6943 DAG.ReplaceAllUsesWith(Call, MN);
6944 DAG.DeleteNode(Call);
6946 // Inform the Frame Information that we have a patchpoint in this function.
6947 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6950 /// Returns an AttributeSet representing the attributes applied to the return
6951 /// value of the given call.
6952 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6953 SmallVector<Attribute::AttrKind, 2> Attrs;
6955 Attrs.push_back(Attribute::SExt);
6957 Attrs.push_back(Attribute::ZExt);
6959 Attrs.push_back(Attribute::InReg);
6961 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6965 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6966 /// implementation, which just calls LowerCall.
6967 /// FIXME: When all targets are
6968 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6969 std::pair<SDValue, SDValue>
6970 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6971 // Handle the incoming return values from the call.
6973 Type *OrigRetTy = CLI.RetTy;
6974 SmallVector<EVT, 4> RetTys;
6975 SmallVector<uint64_t, 4> Offsets;
6976 auto &DL = CLI.DAG.getDataLayout();
6977 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6979 SmallVector<ISD::OutputArg, 4> Outs;
6980 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6982 bool CanLowerReturn =
6983 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6984 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6986 SDValue DemoteStackSlot;
6987 int DemoteStackIdx = -100;
6988 if (!CanLowerReturn) {
6989 // FIXME: equivalent assert?
6990 // assert(!CS.hasInAllocaArgument() &&
6991 // "sret demotion is incompatible with inalloca");
6992 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
6993 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
6994 MachineFunction &MF = CLI.DAG.getMachineFunction();
6995 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6996 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
6998 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7000 Entry.Node = DemoteStackSlot;
7001 Entry.Ty = StackSlotPtrType;
7002 Entry.isSExt = false;
7003 Entry.isZExt = false;
7004 Entry.isInReg = false;
7005 Entry.isSRet = true;
7006 Entry.isNest = false;
7007 Entry.isByVal = false;
7008 Entry.isReturned = false;
7009 Entry.Alignment = Align;
7010 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7011 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7013 // sret demotion isn't compatible with tail-calls, since the sret argument
7014 // points into the callers stack frame.
7015 CLI.IsTailCall = false;
7017 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7019 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7020 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7021 for (unsigned i = 0; i != NumRegs; ++i) {
7022 ISD::InputArg MyFlags;
7023 MyFlags.VT = RegisterVT;
7025 MyFlags.Used = CLI.IsReturnValueUsed;
7027 MyFlags.Flags.setSExt();
7029 MyFlags.Flags.setZExt();
7031 MyFlags.Flags.setInReg();
7032 CLI.Ins.push_back(MyFlags);
7037 // Handle all of the outgoing arguments.
7039 CLI.OutVals.clear();
7040 ArgListTy &Args = CLI.getArgs();
7041 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7042 SmallVector<EVT, 4> ValueVTs;
7043 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7044 Type *FinalType = Args[i].Ty;
7045 if (Args[i].isByVal)
7046 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7047 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7048 FinalType, CLI.CallConv, CLI.IsVarArg);
7049 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7051 EVT VT = ValueVTs[Value];
7052 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7053 SDValue Op = SDValue(Args[i].Node.getNode(),
7054 Args[i].Node.getResNo() + Value);
7055 ISD::ArgFlagsTy Flags;
7056 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7062 if (Args[i].isInReg)
7066 if (Args[i].isByVal)
7068 if (Args[i].isInAlloca) {
7069 Flags.setInAlloca();
7070 // Set the byval flag for CCAssignFn callbacks that don't know about
7071 // inalloca. This way we can know how many bytes we should've allocated
7072 // and how many bytes a callee cleanup function will pop. If we port
7073 // inalloca to more targets, we'll have to add custom inalloca handling
7074 // in the various CC lowering callbacks.
7077 if (Args[i].isByVal || Args[i].isInAlloca) {
7078 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7079 Type *ElementTy = Ty->getElementType();
7080 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7081 // For ByVal, alignment should come from FE. BE will guess if this
7082 // info is not there but there are cases it cannot get right.
7083 unsigned FrameAlign;
7084 if (Args[i].Alignment)
7085 FrameAlign = Args[i].Alignment;
7087 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7088 Flags.setByValAlign(FrameAlign);
7093 Flags.setInConsecutiveRegs();
7094 Flags.setOrigAlign(OriginalAlignment);
7096 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7097 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7098 SmallVector<SDValue, 4> Parts(NumParts);
7099 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7102 ExtendKind = ISD::SIGN_EXTEND;
7103 else if (Args[i].isZExt)
7104 ExtendKind = ISD::ZERO_EXTEND;
7106 // Conservatively only handle 'returned' on non-vectors for now
7107 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7108 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7109 "unexpected use of 'returned'");
7110 // Before passing 'returned' to the target lowering code, ensure that
7111 // either the register MVT and the actual EVT are the same size or that
7112 // the return value and argument are extended in the same way; in these
7113 // cases it's safe to pass the argument register value unchanged as the
7114 // return register value (although it's at the target's option whether
7116 // TODO: allow code generation to take advantage of partially preserved
7117 // registers rather than clobbering the entire register when the
7118 // parameter extension method is not compatible with the return
7120 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7121 (ExtendKind != ISD::ANY_EXTEND &&
7122 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7123 Flags.setReturned();
7126 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7127 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7129 for (unsigned j = 0; j != NumParts; ++j) {
7130 // if it isn't first piece, alignment must be 1
7131 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7132 i < CLI.NumFixedArgs,
7133 i, j*Parts[j].getValueType().getStoreSize());
7134 if (NumParts > 1 && j == 0)
7135 MyFlags.Flags.setSplit();
7137 MyFlags.Flags.setOrigAlign(1);
7139 CLI.Outs.push_back(MyFlags);
7140 CLI.OutVals.push_back(Parts[j]);
7143 if (NeedsRegBlock && Value == NumValues - 1)
7144 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7148 SmallVector<SDValue, 4> InVals;
7149 CLI.Chain = LowerCall(CLI, InVals);
7151 // Verify that the target's LowerCall behaved as expected.
7152 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7153 "LowerCall didn't return a valid chain!");
7154 assert((!CLI.IsTailCall || InVals.empty()) &&
7155 "LowerCall emitted a return value for a tail call!");
7156 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7157 "LowerCall didn't emit the correct number of values!");
7159 // For a tail call, the return value is merely live-out and there aren't
7160 // any nodes in the DAG representing it. Return a special value to
7161 // indicate that a tail call has been emitted and no more Instructions
7162 // should be processed in the current block.
7163 if (CLI.IsTailCall) {
7164 CLI.DAG.setRoot(CLI.Chain);
7165 return std::make_pair(SDValue(), SDValue());
7168 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7169 assert(InVals[i].getNode() &&
7170 "LowerCall emitted a null value!");
7171 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7172 "LowerCall emitted a value with the wrong type!");
7175 SmallVector<SDValue, 4> ReturnValues;
7176 if (!CanLowerReturn) {
7177 // The instruction result is the result of loading from the
7178 // hidden sret parameter.
7179 SmallVector<EVT, 1> PVTs;
7180 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7182 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7183 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7184 EVT PtrVT = PVTs[0];
7186 unsigned NumValues = RetTys.size();
7187 ReturnValues.resize(NumValues);
7188 SmallVector<SDValue, 4> Chains(NumValues);
7190 for (unsigned i = 0; i < NumValues; ++i) {
7191 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7192 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7194 SDValue L = CLI.DAG.getLoad(
7195 RetTys[i], CLI.DL, CLI.Chain, Add,
7196 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7197 DemoteStackIdx, Offsets[i]),
7198 false, false, false, 1);
7199 ReturnValues[i] = L;
7200 Chains[i] = L.getValue(1);
7203 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7205 // Collect the legal value parts into potentially illegal values
7206 // that correspond to the original function's return values.
7207 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7209 AssertOp = ISD::AssertSext;
7210 else if (CLI.RetZExt)
7211 AssertOp = ISD::AssertZext;
7212 unsigned CurReg = 0;
7213 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7215 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7216 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7218 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7219 NumRegs, RegisterVT, VT, nullptr,
7224 // For a function returning void, there is no return value. We can't create
7225 // such a node, so we just return a null return value in that case. In
7226 // that case, nothing will actually look at the value.
7227 if (ReturnValues.empty())
7228 return std::make_pair(SDValue(), CLI.Chain);
7231 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7232 CLI.DAG.getVTList(RetTys), ReturnValues);
7233 return std::make_pair(Res, CLI.Chain);
7236 void TargetLowering::LowerOperationWrapper(SDNode *N,
7237 SmallVectorImpl<SDValue> &Results,
7238 SelectionDAG &DAG) const {
7239 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7241 Results.push_back(Res);
7244 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7245 llvm_unreachable("LowerOperation not implemented for this target!");
7249 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7250 SDValue Op = getNonRegisterValue(V);
7251 assert((Op.getOpcode() != ISD::CopyFromReg ||
7252 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7253 "Copy from a reg to the same reg!");
7254 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7257 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7259 SDValue Chain = DAG.getEntryNode();
7261 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7262 FuncInfo.PreferredExtendType.end())
7264 : FuncInfo.PreferredExtendType[V];
7265 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7266 PendingExports.push_back(Chain);
7269 #include "llvm/CodeGen/SelectionDAGISel.h"
7271 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7272 /// entry block, return true. This includes arguments used by switches, since
7273 /// the switch may expand into multiple basic blocks.
7274 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7275 // With FastISel active, we may be splitting blocks, so force creation
7276 // of virtual registers for all non-dead arguments.
7278 return A->use_empty();
7280 const BasicBlock *Entry = A->getParent()->begin();
7281 for (const User *U : A->users())
7282 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7283 return false; // Use not in entry block.
7288 void SelectionDAGISel::LowerArguments(const Function &F) {
7289 SelectionDAG &DAG = SDB->DAG;
7290 SDLoc dl = SDB->getCurSDLoc();
7291 const DataLayout &DL = DAG.getDataLayout();
7292 SmallVector<ISD::InputArg, 16> Ins;
7294 if (!FuncInfo->CanLowerReturn) {
7295 // Put in an sret pointer parameter before all the other parameters.
7296 SmallVector<EVT, 1> ValueVTs;
7297 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7298 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7300 // NOTE: Assuming that a pointer will never break down to more than one VT
7302 ISD::ArgFlagsTy Flags;
7304 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7305 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7306 ISD::InputArg::NoArgIndex, 0);
7307 Ins.push_back(RetArg);
7310 // Set up the incoming argument description vector.
7312 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7313 I != E; ++I, ++Idx) {
7314 SmallVector<EVT, 4> ValueVTs;
7315 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7316 bool isArgValueUsed = !I->use_empty();
7317 unsigned PartBase = 0;
7318 Type *FinalType = I->getType();
7319 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7320 FinalType = cast<PointerType>(FinalType)->getElementType();
7321 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7322 FinalType, F.getCallingConv(), F.isVarArg());
7323 for (unsigned Value = 0, NumValues = ValueVTs.size();
7324 Value != NumValues; ++Value) {
7325 EVT VT = ValueVTs[Value];
7326 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7327 ISD::ArgFlagsTy Flags;
7328 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7330 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7332 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7334 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7336 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7338 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7340 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7341 Flags.setInAlloca();
7342 // Set the byval flag for CCAssignFn callbacks that don't know about
7343 // inalloca. This way we can know how many bytes we should've allocated
7344 // and how many bytes a callee cleanup function will pop. If we port
7345 // inalloca to more targets, we'll have to add custom inalloca handling
7346 // in the various CC lowering callbacks.
7349 if (Flags.isByVal() || Flags.isInAlloca()) {
7350 PointerType *Ty = cast<PointerType>(I->getType());
7351 Type *ElementTy = Ty->getElementType();
7352 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7353 // For ByVal, alignment should be passed from FE. BE will guess if
7354 // this info is not there but there are cases it cannot get right.
7355 unsigned FrameAlign;
7356 if (F.getParamAlignment(Idx))
7357 FrameAlign = F.getParamAlignment(Idx);
7359 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7360 Flags.setByValAlign(FrameAlign);
7362 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7365 Flags.setInConsecutiveRegs();
7366 Flags.setOrigAlign(OriginalAlignment);
7368 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7369 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7370 for (unsigned i = 0; i != NumRegs; ++i) {
7371 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7372 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7373 if (NumRegs > 1 && i == 0)
7374 MyFlags.Flags.setSplit();
7375 // if it isn't first piece, alignment must be 1
7377 MyFlags.Flags.setOrigAlign(1);
7378 Ins.push_back(MyFlags);
7380 if (NeedsRegBlock && Value == NumValues - 1)
7381 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7382 PartBase += VT.getStoreSize();
7386 // Call the target to set up the argument values.
7387 SmallVector<SDValue, 8> InVals;
7388 SDValue NewRoot = TLI->LowerFormalArguments(
7389 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7391 // Verify that the target's LowerFormalArguments behaved as expected.
7392 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7393 "LowerFormalArguments didn't return a valid chain!");
7394 assert(InVals.size() == Ins.size() &&
7395 "LowerFormalArguments didn't emit the correct number of values!");
7397 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7398 assert(InVals[i].getNode() &&
7399 "LowerFormalArguments emitted a null value!");
7400 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7401 "LowerFormalArguments emitted a value with the wrong type!");
7405 // Update the DAG with the new chain value resulting from argument lowering.
7406 DAG.setRoot(NewRoot);
7408 // Set up the argument values.
7411 if (!FuncInfo->CanLowerReturn) {
7412 // Create a virtual register for the sret pointer, and put in a copy
7413 // from the sret argument into it.
7414 SmallVector<EVT, 1> ValueVTs;
7415 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7416 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7417 MVT VT = ValueVTs[0].getSimpleVT();
7418 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7419 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7420 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7421 RegVT, VT, nullptr, AssertOp);
7423 MachineFunction& MF = SDB->DAG.getMachineFunction();
7424 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7425 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7426 FuncInfo->DemoteRegister = SRetReg;
7428 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7429 DAG.setRoot(NewRoot);
7431 // i indexes lowered arguments. Bump it past the hidden sret argument.
7432 // Idx indexes LLVM arguments. Don't touch it.
7436 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7438 SmallVector<SDValue, 4> ArgValues;
7439 SmallVector<EVT, 4> ValueVTs;
7440 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7441 unsigned NumValues = ValueVTs.size();
7443 // If this argument is unused then remember its value. It is used to generate
7444 // debugging information.
7445 if (I->use_empty() && NumValues) {
7446 SDB->setUnusedArgValue(I, InVals[i]);
7448 // Also remember any frame index for use in FastISel.
7449 if (FrameIndexSDNode *FI =
7450 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7451 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7454 for (unsigned Val = 0; Val != NumValues; ++Val) {
7455 EVT VT = ValueVTs[Val];
7456 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7457 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7459 if (!I->use_empty()) {
7460 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7461 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7462 AssertOp = ISD::AssertSext;
7463 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7464 AssertOp = ISD::AssertZext;
7466 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7467 NumParts, PartVT, VT,
7468 nullptr, AssertOp));
7474 // We don't need to do anything else for unused arguments.
7475 if (ArgValues.empty())
7478 // Note down frame index.
7479 if (FrameIndexSDNode *FI =
7480 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7481 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7483 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7484 SDB->getCurSDLoc());
7486 SDB->setValue(I, Res);
7487 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7488 if (LoadSDNode *LNode =
7489 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7490 if (FrameIndexSDNode *FI =
7491 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7492 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7495 // If this argument is live outside of the entry block, insert a copy from
7496 // wherever we got it to the vreg that other BB's will reference it as.
7497 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7498 // If we can, though, try to skip creating an unnecessary vreg.
7499 // FIXME: This isn't very clean... it would be nice to make this more
7500 // general. It's also subtly incompatible with the hacks FastISel
7502 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7503 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7504 FuncInfo->ValueMap[I] = Reg;
7508 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7509 FuncInfo->InitializeRegForValue(I);
7510 SDB->CopyToExportRegsIfNeeded(I);
7514 assert(i == InVals.size() && "Argument register count mismatch!");
7516 // Finally, if the target has anything special to do, allow it to do so.
7517 EmitFunctionEntryCode();
7520 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7521 /// ensure constants are generated when needed. Remember the virtual registers
7522 /// that need to be added to the Machine PHI nodes as input. We cannot just
7523 /// directly add them, because expansion might result in multiple MBB's for one
7524 /// BB. As such, the start of the BB might correspond to a different MBB than
7528 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7529 const TerminatorInst *TI = LLVMBB->getTerminator();
7531 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7533 // Check PHI nodes in successors that expect a value to be available from this
7535 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7536 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7537 if (!isa<PHINode>(SuccBB->begin())) continue;
7538 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7540 // If this terminator has multiple identical successors (common for
7541 // switches), only handle each succ once.
7542 if (!SuccsHandled.insert(SuccMBB).second)
7545 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7547 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7548 // nodes and Machine PHI nodes, but the incoming operands have not been
7550 for (BasicBlock::const_iterator I = SuccBB->begin();
7551 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7552 // Ignore dead phi's.
7553 if (PN->use_empty()) continue;
7556 if (PN->getType()->isEmptyTy())
7560 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7562 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7563 unsigned &RegOut = ConstantsOut[C];
7565 RegOut = FuncInfo.CreateRegs(C->getType());
7566 CopyValueToVirtualRegister(C, RegOut);
7570 DenseMap<const Value *, unsigned>::iterator I =
7571 FuncInfo.ValueMap.find(PHIOp);
7572 if (I != FuncInfo.ValueMap.end())
7575 assert(isa<AllocaInst>(PHIOp) &&
7576 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7577 "Didn't codegen value into a register!??");
7578 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7579 CopyValueToVirtualRegister(PHIOp, Reg);
7583 // Remember that this register needs to added to the machine PHI node as
7584 // the input for this MBB.
7585 SmallVector<EVT, 4> ValueVTs;
7586 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7587 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7588 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7589 EVT VT = ValueVTs[vti];
7590 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7591 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7592 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7593 Reg += NumRegisters;
7598 ConstantsOut.clear();
7601 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7604 SelectionDAGBuilder::StackProtectorDescriptor::
7605 AddSuccessorMBB(const BasicBlock *BB,
7606 MachineBasicBlock *ParentMBB,
7608 MachineBasicBlock *SuccMBB) {
7609 // If SuccBB has not been created yet, create it.
7611 MachineFunction *MF = ParentMBB->getParent();
7612 MachineFunction::iterator BBI = ParentMBB;
7613 SuccMBB = MF->CreateMachineBasicBlock(BB);
7614 MF->insert(++BBI, SuccMBB);
7616 // Add it as a successor of ParentMBB.
7617 ParentMBB->addSuccessor(
7618 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7622 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7623 MachineFunction::iterator I = MBB;
7624 if (++I == FuncInfo.MF->end())
7629 /// During lowering new call nodes can be created (such as memset, etc.).
7630 /// Those will become new roots of the current DAG, but complications arise
7631 /// when they are tail calls. In such cases, the call lowering will update
7632 /// the root, but the builder still needs to know that a tail call has been
7633 /// lowered in order to avoid generating an additional return.
7634 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7635 // If the node is null, we do have a tail call.
7636 if (MaybeTC.getNode() != nullptr)
7637 DAG.setRoot(MaybeTC);
7642 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7643 unsigned *TotalCases, unsigned First,
7645 assert(Last >= First);
7646 assert(TotalCases[Last] >= TotalCases[First]);
7648 APInt LowCase = Clusters[First].Low->getValue();
7649 APInt HighCase = Clusters[Last].High->getValue();
7650 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7652 // FIXME: A range of consecutive cases has 100% density, but only requires one
7653 // comparison to lower. We should discriminate against such consecutive ranges
7656 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7657 uint64_t Range = Diff + 1;
7660 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7662 assert(NumCases < UINT64_MAX / 100);
7663 assert(Range >= NumCases);
7665 return NumCases * 100 >= Range * MinJumpTableDensity;
7668 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7669 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7670 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7673 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7674 unsigned First, unsigned Last,
7675 const SwitchInst *SI,
7676 MachineBasicBlock *DefaultMBB,
7677 CaseCluster &JTCluster) {
7678 assert(First <= Last);
7680 uint32_t Weight = 0;
7681 unsigned NumCmps = 0;
7682 std::vector<MachineBasicBlock*> Table;
7683 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7684 for (unsigned I = First; I <= Last; ++I) {
7685 assert(Clusters[I].Kind == CC_Range);
7686 Weight += Clusters[I].Weight;
7687 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7688 APInt Low = Clusters[I].Low->getValue();
7689 APInt High = Clusters[I].High->getValue();
7690 NumCmps += (Low == High) ? 1 : 2;
7692 // Fill the gap between this and the previous cluster.
7693 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7694 assert(PreviousHigh.slt(Low));
7695 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7696 for (uint64_t J = 0; J < Gap; J++)
7697 Table.push_back(DefaultMBB);
7699 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7700 for (uint64_t J = 0; J < ClusterSize; ++J)
7701 Table.push_back(Clusters[I].MBB);
7702 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7705 unsigned NumDests = JTWeights.size();
7706 if (isSuitableForBitTests(NumDests, NumCmps,
7707 Clusters[First].Low->getValue(),
7708 Clusters[Last].High->getValue())) {
7709 // Clusters[First..Last] should be lowered as bit tests instead.
7713 // Create the MBB that will load from and jump through the table.
7714 // Note: We create it here, but it's not inserted into the function yet.
7715 MachineFunction *CurMF = FuncInfo.MF;
7716 MachineBasicBlock *JumpTableMBB =
7717 CurMF->CreateMachineBasicBlock(SI->getParent());
7719 // Add successors. Note: use table order for determinism.
7720 SmallPtrSet<MachineBasicBlock *, 8> Done;
7721 for (MachineBasicBlock *Succ : Table) {
7722 if (Done.count(Succ))
7724 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7728 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7729 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7730 ->createJumpTableIndex(Table);
7732 // Set up the jump table info.
7733 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7734 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7735 Clusters[Last].High->getValue(), SI->getCondition(),
7737 JTCases.emplace_back(std::move(JTH), std::move(JT));
7739 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7740 JTCases.size() - 1, Weight);
7744 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7745 const SwitchInst *SI,
7746 MachineBasicBlock *DefaultMBB) {
7748 // Clusters must be non-empty, sorted, and only contain Range clusters.
7749 assert(!Clusters.empty());
7750 for (CaseCluster &C : Clusters)
7751 assert(C.Kind == CC_Range);
7752 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7753 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7756 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7757 if (!areJTsAllowed(TLI))
7760 const int64_t N = Clusters.size();
7761 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7763 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7764 SmallVector<unsigned, 8> TotalCases(N);
7766 for (unsigned i = 0; i < N; ++i) {
7767 APInt Hi = Clusters[i].High->getValue();
7768 APInt Lo = Clusters[i].Low->getValue();
7769 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7771 TotalCases[i] += TotalCases[i - 1];
7774 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7775 // Cheap case: the whole range might be suitable for jump table.
7776 CaseCluster JTCluster;
7777 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7778 Clusters[0] = JTCluster;
7784 // The algorithm below is not suitable for -O0.
7785 if (TM.getOptLevel() == CodeGenOpt::None)
7788 // Split Clusters into minimum number of dense partitions. The algorithm uses
7789 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7790 // for the Case Statement'" (1994), but builds the MinPartitions array in
7791 // reverse order to make it easier to reconstruct the partitions in ascending
7792 // order. In the choice between two optimal partitionings, it picks the one
7793 // which yields more jump tables.
7795 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7796 SmallVector<unsigned, 8> MinPartitions(N);
7797 // LastElement[i] is the last element of the partition starting at i.
7798 SmallVector<unsigned, 8> LastElement(N);
7799 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7800 SmallVector<unsigned, 8> NumTables(N);
7802 // Base case: There is only one way to partition Clusters[N-1].
7803 MinPartitions[N - 1] = 1;
7804 LastElement[N - 1] = N - 1;
7805 assert(MinJumpTableSize > 1);
7806 NumTables[N - 1] = 0;
7808 // Note: loop indexes are signed to avoid underflow.
7809 for (int64_t i = N - 2; i >= 0; i--) {
7810 // Find optimal partitioning of Clusters[i..N-1].
7811 // Baseline: Put Clusters[i] into a partition on its own.
7812 MinPartitions[i] = MinPartitions[i + 1] + 1;
7814 NumTables[i] = NumTables[i + 1];
7816 // Search for a solution that results in fewer partitions.
7817 for (int64_t j = N - 1; j > i; j--) {
7818 // Try building a partition from Clusters[i..j].
7819 if (isDense(Clusters, &TotalCases[0], i, j)) {
7820 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7821 bool IsTable = j - i + 1 >= MinJumpTableSize;
7822 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7824 // If this j leads to fewer partitions, or same number of partitions
7825 // with more lookup tables, it is a better partitioning.
7826 if (NumPartitions < MinPartitions[i] ||
7827 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7828 MinPartitions[i] = NumPartitions;
7830 NumTables[i] = Tables;
7836 // Iterate over the partitions, replacing some with jump tables in-place.
7837 unsigned DstIndex = 0;
7838 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7839 Last = LastElement[First];
7840 assert(Last >= First);
7841 assert(DstIndex <= First);
7842 unsigned NumClusters = Last - First + 1;
7844 CaseCluster JTCluster;
7845 if (NumClusters >= MinJumpTableSize &&
7846 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7847 Clusters[DstIndex++] = JTCluster;
7849 for (unsigned I = First; I <= Last; ++I)
7850 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7853 Clusters.resize(DstIndex);
7856 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7857 // FIXME: Using the pointer type doesn't seem ideal.
7858 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7859 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7863 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7866 const APInt &High) {
7867 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7868 // range of cases both require only one branch to lower. Just looking at the
7869 // number of clusters and destinations should be enough to decide whether to
7872 // To lower a range with bit tests, the range must fit the bitwidth of a
7874 if (!rangeFitsInWord(Low, High))
7877 // Decide whether it's profitable to lower this range with bit tests. Each
7878 // destination requires a bit test and branch, and there is an overall range
7879 // check branch. For a small number of clusters, separate comparisons might be
7880 // cheaper, and for many destinations, splitting the range might be better.
7881 return (NumDests == 1 && NumCmps >= 3) ||
7882 (NumDests == 2 && NumCmps >= 5) ||
7883 (NumDests == 3 && NumCmps >= 6);
7886 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7887 unsigned First, unsigned Last,
7888 const SwitchInst *SI,
7889 CaseCluster &BTCluster) {
7890 assert(First <= Last);
7894 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7895 unsigned NumCmps = 0;
7896 for (int64_t I = First; I <= Last; ++I) {
7897 assert(Clusters[I].Kind == CC_Range);
7898 Dests.set(Clusters[I].MBB->getNumber());
7899 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7901 unsigned NumDests = Dests.count();
7903 APInt Low = Clusters[First].Low->getValue();
7904 APInt High = Clusters[Last].High->getValue();
7905 assert(Low.slt(High));
7907 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7913 const int BitWidth = DAG.getTargetLoweringInfo()
7914 .getPointerTy(DAG.getDataLayout())
7916 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7918 // Check if the clusters cover a contiguous range such that no value in the
7919 // range will jump to the default statement.
7920 bool ContiguousRange = true;
7921 for (int64_t I = First + 1; I <= Last; ++I) {
7922 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7923 ContiguousRange = false;
7928 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7929 // Optimize the case where all the case values fit in a word without having
7930 // to subtract minValue. In this case, we can optimize away the subtraction.
7931 LowBound = APInt::getNullValue(Low.getBitWidth());
7933 ContiguousRange = false;
7936 CmpRange = High - Low;
7940 uint32_t TotalWeight = 0;
7941 for (unsigned i = First; i <= Last; ++i) {
7942 // Find the CaseBits for this destination.
7944 for (j = 0; j < CBV.size(); ++j)
7945 if (CBV[j].BB == Clusters[i].MBB)
7947 if (j == CBV.size())
7948 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7949 CaseBits *CB = &CBV[j];
7951 // Update Mask, Bits and ExtraWeight.
7952 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7953 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7954 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7955 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7956 CB->Bits += Hi - Lo + 1;
7957 CB->ExtraWeight += Clusters[i].Weight;
7958 TotalWeight += Clusters[i].Weight;
7959 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7963 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7964 // Sort by weight first, number of bits second.
7965 if (a.ExtraWeight != b.ExtraWeight)
7966 return a.ExtraWeight > b.ExtraWeight;
7967 return a.Bits > b.Bits;
7970 for (auto &CB : CBV) {
7971 MachineBasicBlock *BitTestBB =
7972 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7973 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7975 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7976 SI->getCondition(), -1U, MVT::Other, false,
7977 ContiguousRange, nullptr, nullptr, std::move(BTI),
7980 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7981 BitTestCases.size() - 1, TotalWeight);
7985 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7986 const SwitchInst *SI) {
7987 // Partition Clusters into as few subsets as possible, where each subset has a
7988 // range that fits in a machine word and has <= 3 unique destinations.
7991 // Clusters must be sorted and contain Range or JumpTable clusters.
7992 assert(!Clusters.empty());
7993 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
7994 for (const CaseCluster &C : Clusters)
7995 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
7996 for (unsigned i = 1; i < Clusters.size(); ++i)
7997 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8000 // The algorithm below is not suitable for -O0.
8001 if (TM.getOptLevel() == CodeGenOpt::None)
8004 // If target does not have legal shift left, do not emit bit tests at all.
8005 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8006 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8007 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8010 int BitWidth = PTy.getSizeInBits();
8011 const int64_t N = Clusters.size();
8013 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8014 SmallVector<unsigned, 8> MinPartitions(N);
8015 // LastElement[i] is the last element of the partition starting at i.
8016 SmallVector<unsigned, 8> LastElement(N);
8018 // FIXME: This might not be the best algorithm for finding bit test clusters.
8020 // Base case: There is only one way to partition Clusters[N-1].
8021 MinPartitions[N - 1] = 1;
8022 LastElement[N - 1] = N - 1;
8024 // Note: loop indexes are signed to avoid underflow.
8025 for (int64_t i = N - 2; i >= 0; --i) {
8026 // Find optimal partitioning of Clusters[i..N-1].
8027 // Baseline: Put Clusters[i] into a partition on its own.
8028 MinPartitions[i] = MinPartitions[i + 1] + 1;
8031 // Search for a solution that results in fewer partitions.
8032 // Note: the search is limited by BitWidth, reducing time complexity.
8033 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8034 // Try building a partition from Clusters[i..j].
8037 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8038 Clusters[j].High->getValue()))
8041 // Check nbr of destinations and cluster types.
8042 // FIXME: This works, but doesn't seem very efficient.
8043 bool RangesOnly = true;
8044 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8045 for (int64_t k = i; k <= j; k++) {
8046 if (Clusters[k].Kind != CC_Range) {
8050 Dests.set(Clusters[k].MBB->getNumber());
8052 if (!RangesOnly || Dests.count() > 3)
8055 // Check if it's a better partition.
8056 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8057 if (NumPartitions < MinPartitions[i]) {
8058 // Found a better partition.
8059 MinPartitions[i] = NumPartitions;
8065 // Iterate over the partitions, replacing with bit-test clusters in-place.
8066 unsigned DstIndex = 0;
8067 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8068 Last = LastElement[First];
8069 assert(First <= Last);
8070 assert(DstIndex <= First);
8072 CaseCluster BitTestCluster;
8073 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8074 Clusters[DstIndex++] = BitTestCluster;
8076 size_t NumClusters = Last - First + 1;
8077 std::memmove(&Clusters[DstIndex], &Clusters[First],
8078 sizeof(Clusters[0]) * NumClusters);
8079 DstIndex += NumClusters;
8082 Clusters.resize(DstIndex);
8085 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8086 MachineBasicBlock *SwitchMBB,
8087 MachineBasicBlock *DefaultMBB) {
8088 MachineFunction *CurMF = FuncInfo.MF;
8089 MachineBasicBlock *NextMBB = nullptr;
8090 MachineFunction::iterator BBI = W.MBB;
8091 if (++BBI != FuncInfo.MF->end())
8094 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8096 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8098 if (Size == 2 && W.MBB == SwitchMBB) {
8099 // If any two of the cases has the same destination, and if one value
8100 // is the same as the other, but has one bit unset that the other has set,
8101 // use bit manipulation to do two compares at once. For example:
8102 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8103 // TODO: This could be extended to merge any 2 cases in switches with 3
8105 // TODO: Handle cases where W.CaseBB != SwitchBB.
8106 CaseCluster &Small = *W.FirstCluster;
8107 CaseCluster &Big = *W.LastCluster;
8109 if (Small.Low == Small.High && Big.Low == Big.High &&
8110 Small.MBB == Big.MBB) {
8111 const APInt &SmallValue = Small.Low->getValue();
8112 const APInt &BigValue = Big.Low->getValue();
8114 // Check that there is only one bit different.
8115 APInt CommonBit = BigValue ^ SmallValue;
8116 if (CommonBit.isPowerOf2()) {
8117 SDValue CondLHS = getValue(Cond);
8118 EVT VT = CondLHS.getValueType();
8119 SDLoc DL = getCurSDLoc();
8121 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8122 DAG.getConstant(CommonBit, DL, VT));
8123 SDValue Cond = DAG.getSetCC(
8124 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8127 // Update successor info.
8128 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8129 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8130 addSuccessorWithWeight(
8131 SwitchMBB, DefaultMBB,
8132 // The default destination is the first successor in IR.
8133 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8136 // Insert the true branch.
8138 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8139 DAG.getBasicBlock(Small.MBB));
8140 // Insert the false branch.
8141 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8142 DAG.getBasicBlock(DefaultMBB));
8144 DAG.setRoot(BrCond);
8150 if (TM.getOptLevel() != CodeGenOpt::None) {
8151 // Order cases by weight so the most likely case will be checked first.
8152 std::sort(W.FirstCluster, W.LastCluster + 1,
8153 [](const CaseCluster &a, const CaseCluster &b) {
8154 return a.Weight > b.Weight;
8157 // Rearrange the case blocks so that the last one falls through if possible
8158 // without without changing the order of weights.
8159 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8161 if (I->Weight > W.LastCluster->Weight)
8163 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8164 std::swap(*I, *W.LastCluster);
8170 // Compute total weight.
8171 uint32_t DefaultWeight = W.DefaultWeight;
8172 uint32_t UnhandledWeights = DefaultWeight;
8173 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8174 UnhandledWeights += I->Weight;
8175 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8178 MachineBasicBlock *CurMBB = W.MBB;
8179 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8180 MachineBasicBlock *Fallthrough;
8181 if (I == W.LastCluster) {
8182 // For the last cluster, fall through to the default destination.
8183 Fallthrough = DefaultMBB;
8185 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8186 CurMF->insert(BBI, Fallthrough);
8187 // Put Cond in a virtual register to make it available from the new blocks.
8188 ExportFromCurrentBlock(Cond);
8190 UnhandledWeights -= I->Weight;
8193 case CC_JumpTable: {
8194 // FIXME: Optimize away range check based on pivot comparisons.
8195 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8196 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8198 // The jump block hasn't been inserted yet; insert it here.
8199 MachineBasicBlock *JumpMBB = JT->MBB;
8200 CurMF->insert(BBI, JumpMBB);
8202 uint32_t JumpWeight = I->Weight;
8203 uint32_t FallthroughWeight = UnhandledWeights;
8205 // If the default statement is a target of the jump table, we evenly
8206 // distribute the default weight to successors of CurMBB. Also update
8207 // the weight on the edge from JumpMBB to Fallthrough.
8208 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8209 SE = JumpMBB->succ_end();
8211 if (*SI == DefaultMBB) {
8212 JumpWeight += DefaultWeight / 2;
8213 FallthroughWeight -= DefaultWeight / 2;
8214 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8219 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8220 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8222 // The jump table header will be inserted in our current block, do the
8223 // range check, and fall through to our fallthrough block.
8224 JTH->HeaderBB = CurMBB;
8225 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8227 // If we're in the right place, emit the jump table header right now.
8228 if (CurMBB == SwitchMBB) {
8229 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8230 JTH->Emitted = true;
8235 // FIXME: Optimize away range check based on pivot comparisons.
8236 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8238 // The bit test blocks haven't been inserted yet; insert them here.
8239 for (BitTestCase &BTC : BTB->Cases)
8240 CurMF->insert(BBI, BTC.ThisBB);
8242 // Fill in fields of the BitTestBlock.
8243 BTB->Parent = CurMBB;
8244 BTB->Default = Fallthrough;
8246 BTB->DefaultWeight = UnhandledWeights;
8247 // If the cases in bit test don't form a contiguous range, we evenly
8248 // distribute the weight on the edge to Fallthrough to two successors
8250 if (!BTB->ContiguousRange) {
8251 BTB->Weight += DefaultWeight / 2;
8252 BTB->DefaultWeight -= DefaultWeight / 2;
8255 // If we're in the right place, emit the bit test header right now.
8256 if (CurMBB == SwitchMBB) {
8257 visitBitTestHeader(*BTB, SwitchMBB);
8258 BTB->Emitted = true;
8263 const Value *RHS, *LHS, *MHS;
8265 if (I->Low == I->High) {
8266 // Check Cond == I->Low.
8272 // Check I->Low <= Cond <= I->High.
8279 // The false weight is the sum of all unhandled cases.
8280 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8283 if (CurMBB == SwitchMBB)
8284 visitSwitchCase(CB, SwitchMBB);
8286 SwitchCases.push_back(CB);
8291 CurMBB = Fallthrough;
8295 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8296 CaseClusterIt First,
8297 CaseClusterIt Last) {
8298 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8299 if (X.Weight != CC.Weight)
8300 return X.Weight > CC.Weight;
8302 // Ties are broken by comparing the case value.
8303 return X.Low->getValue().slt(CC.Low->getValue());
8307 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8308 const SwitchWorkListItem &W,
8310 MachineBasicBlock *SwitchMBB) {
8311 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8312 "Clusters not sorted?");
8314 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8316 // Balance the tree based on branch weights to create a near-optimal (in terms
8317 // of search time given key frequency) binary search tree. See e.g. Kurt
8318 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8319 CaseClusterIt LastLeft = W.FirstCluster;
8320 CaseClusterIt FirstRight = W.LastCluster;
8321 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8322 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8324 // Move LastLeft and FirstRight towards each other from opposite directions to
8325 // find a partitioning of the clusters which balances the weight on both
8326 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8327 // taken to ensure 0-weight nodes are distributed evenly.
8329 while (LastLeft + 1 < FirstRight) {
8330 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8331 LeftWeight += (++LastLeft)->Weight;
8333 RightWeight += (--FirstRight)->Weight;
8338 // Our binary search tree differs from a typical BST in that ours can have up
8339 // to three values in each leaf. The pivot selection above doesn't take that
8340 // into account, which means the tree might require more nodes and be less
8341 // efficient. We compensate for this here.
8343 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8344 unsigned NumRight = W.LastCluster - FirstRight + 1;
8346 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8347 // If one side has less than 3 clusters, and the other has more than 3,
8348 // consider taking a cluster from the other side.
8350 if (NumLeft < NumRight) {
8351 // Consider moving the first cluster on the right to the left side.
8352 CaseCluster &CC = *FirstRight;
8353 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8354 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8355 if (LeftSideRank <= RightSideRank) {
8356 // Moving the cluster to the left does not demote it.
8362 assert(NumRight < NumLeft);
8363 // Consider moving the last element on the left to the right side.
8364 CaseCluster &CC = *LastLeft;
8365 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8366 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8367 if (RightSideRank <= LeftSideRank) {
8368 // Moving the cluster to the right does not demot it.
8378 assert(LastLeft + 1 == FirstRight);
8379 assert(LastLeft >= W.FirstCluster);
8380 assert(FirstRight <= W.LastCluster);
8382 // Use the first element on the right as pivot since we will make less-than
8383 // comparisons against it.
8384 CaseClusterIt PivotCluster = FirstRight;
8385 assert(PivotCluster > W.FirstCluster);
8386 assert(PivotCluster <= W.LastCluster);
8388 CaseClusterIt FirstLeft = W.FirstCluster;
8389 CaseClusterIt LastRight = W.LastCluster;
8391 const ConstantInt *Pivot = PivotCluster->Low;
8393 // New blocks will be inserted immediately after the current one.
8394 MachineFunction::iterator BBI = W.MBB;
8397 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8398 // we can branch to its destination directly if it's squeezed exactly in
8399 // between the known lower bound and Pivot - 1.
8400 MachineBasicBlock *LeftMBB;
8401 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8402 FirstLeft->Low == W.GE &&
8403 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8404 LeftMBB = FirstLeft->MBB;
8406 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8407 FuncInfo.MF->insert(BBI, LeftMBB);
8409 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8410 // Put Cond in a virtual register to make it available from the new blocks.
8411 ExportFromCurrentBlock(Cond);
8414 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8415 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8416 // directly if RHS.High equals the current upper bound.
8417 MachineBasicBlock *RightMBB;
8418 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8419 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8420 RightMBB = FirstRight->MBB;
8422 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8423 FuncInfo.MF->insert(BBI, RightMBB);
8425 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8426 // Put Cond in a virtual register to make it available from the new blocks.
8427 ExportFromCurrentBlock(Cond);
8430 // Create the CaseBlock record that will be used to lower the branch.
8431 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8432 LeftWeight, RightWeight);
8434 if (W.MBB == SwitchMBB)
8435 visitSwitchCase(CB, SwitchMBB);
8437 SwitchCases.push_back(CB);
8440 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8441 // Extract cases from the switch.
8442 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8443 CaseClusterVector Clusters;
8444 Clusters.reserve(SI.getNumCases());
8445 for (auto I : SI.cases()) {
8446 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8447 const ConstantInt *CaseVal = I.getCaseValue();
8449 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8450 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8453 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8455 // Cluster adjacent cases with the same destination. We do this at all
8456 // optimization levels because it's cheap to do and will make codegen faster
8457 // if there are many clusters.
8458 sortAndRangeify(Clusters);
8460 if (TM.getOptLevel() != CodeGenOpt::None) {
8461 // Replace an unreachable default with the most popular destination.
8462 // FIXME: Exploit unreachable default more aggressively.
8463 bool UnreachableDefault =
8464 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8465 if (UnreachableDefault && !Clusters.empty()) {
8466 DenseMap<const BasicBlock *, unsigned> Popularity;
8467 unsigned MaxPop = 0;
8468 const BasicBlock *MaxBB = nullptr;
8469 for (auto I : SI.cases()) {
8470 const BasicBlock *BB = I.getCaseSuccessor();
8471 if (++Popularity[BB] > MaxPop) {
8472 MaxPop = Popularity[BB];
8477 assert(MaxPop > 0 && MaxBB);
8478 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8480 // Remove cases that were pointing to the destination that is now the
8482 CaseClusterVector New;
8483 New.reserve(Clusters.size());
8484 for (CaseCluster &CC : Clusters) {
8485 if (CC.MBB != DefaultMBB)
8488 Clusters = std::move(New);
8492 // If there is only the default destination, jump there directly.
8493 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8494 if (Clusters.empty()) {
8495 SwitchMBB->addSuccessor(DefaultMBB);
8496 if (DefaultMBB != NextBlock(SwitchMBB)) {
8497 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8498 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8503 findJumpTables(Clusters, &SI, DefaultMBB);
8504 findBitTestClusters(Clusters, &SI);
8507 dbgs() << "Case clusters: ";
8508 for (const CaseCluster &C : Clusters) {
8509 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8510 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8512 C.Low->getValue().print(dbgs(), true);
8513 if (C.Low != C.High) {
8515 C.High->getValue().print(dbgs(), true);
8522 assert(!Clusters.empty());
8523 SwitchWorkList WorkList;
8524 CaseClusterIt First = Clusters.begin();
8525 CaseClusterIt Last = Clusters.end() - 1;
8526 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8527 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8529 while (!WorkList.empty()) {
8530 SwitchWorkListItem W = WorkList.back();
8531 WorkList.pop_back();
8532 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8534 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8535 // For optimized builds, lower large range as a balanced binary tree.
8536 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8540 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);