1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
61 #include "llvm/Target/TargetSubtargetInfo.h"
65 #define DEBUG_TYPE "isel"
67 /// LimitFloatPrecision - Generate low-precision inline sequences for
68 /// some float libcalls (6, 8 or 12 bits).
69 static unsigned LimitFloatPrecision;
71 static cl::opt<unsigned, true>
72 LimitFPPrecision("limit-float-precision",
73 cl::desc("Generate low-precision inline sequences "
74 "for some float libcalls"),
75 cl::location(LimitFloatPrecision),
78 // Limit the width of DAG chains. This is important in general to prevent
79 // prevent DAG-based analysis from blowing up. For example, alias analysis and
80 // load clustering may not complete in reasonable time. It is difficult to
81 // recognize and avoid this situation within each individual analysis, and
82 // future analyses are likely to have the same behavior. Limiting DAG width is
83 // the safe approach, and will be especially important with global DAGs.
85 // MaxParallelChains default is arbitrarily high to avoid affecting
86 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
87 // sequence over this should have been converted to llvm.memcpy by the
88 // frontend. It easy to induce this behavior with .ll code such as:
89 // %buffer = alloca [4096 x i8]
90 // %data = load [4096 x i8]* %argPtr
91 // store [4096 x i8] %data, [4096 x i8]* %buffer
92 static const unsigned MaxParallelChains = 64;
94 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
95 const SDValue *Parts, unsigned NumParts,
96 MVT PartVT, EVT ValueVT, const Value *V);
98 /// getCopyFromParts - Create a value that contains the specified legal parts
99 /// combined into the value they represent. If the parts combine to a type
100 /// larger then ValueVT then AssertOp can be used to specify whether the extra
101 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
102 /// (ISD::AssertSext).
103 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts,
105 unsigned NumParts, MVT PartVT, EVT ValueVT,
107 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
108 if (ValueVT.isVector())
109 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
112 assert(NumParts > 0 && "No parts to assemble!");
113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
114 SDValue Val = Parts[0];
117 // Assemble the value from multiple parts.
118 if (ValueVT.isInteger()) {
119 unsigned PartBits = PartVT.getSizeInBits();
120 unsigned ValueBits = ValueVT.getSizeInBits();
122 // Assemble the power of 2 part.
123 unsigned RoundParts = NumParts & (NumParts - 1) ?
124 1 << Log2_32(NumParts) : NumParts;
125 unsigned RoundBits = PartBits * RoundParts;
126 EVT RoundVT = RoundBits == ValueBits ?
127 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
130 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
132 if (RoundParts > 2) {
133 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
135 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
136 RoundParts / 2, PartVT, HalfVT, V);
138 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
139 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
142 if (TLI.isBigEndian())
145 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
147 if (RoundParts < NumParts) {
148 // Assemble the trailing non-power-of-2 part.
149 unsigned OddParts = NumParts - RoundParts;
150 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
151 Hi = getCopyFromParts(DAG, DL,
152 Parts + RoundParts, OddParts, PartVT, OddVT, V);
154 // Combine the round and odd parts.
156 if (TLI.isBigEndian())
158 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
159 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
160 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
161 DAG.getConstant(Lo.getValueType().getSizeInBits(),
162 TLI.getPointerTy()));
163 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
164 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
166 } else if (PartVT.isFloatingPoint()) {
167 // FP split into multiple FP parts (for ppcf128)
168 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
171 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
172 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
173 if (TLI.hasBigEndianPartOrdering(ValueVT))
175 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
177 // FP split into integer parts (soft fp)
178 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
179 !PartVT.isVector() && "Unexpected split");
180 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
181 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
185 // There is now one part, held in Val. Correct it to match ValueVT.
186 EVT PartEVT = Val.getValueType();
188 if (PartEVT == ValueVT)
191 if (PartEVT.isInteger() && ValueVT.isInteger()) {
192 if (ValueVT.bitsLT(PartEVT)) {
193 // For a truncate, see if we have any information to
194 // indicate whether the truncated bits will always be
195 // zero or sign-extension.
196 if (AssertOp != ISD::DELETED_NODE)
197 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
198 DAG.getValueType(ValueVT));
199 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
201 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
204 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
205 // FP_ROUND's are always exact here.
206 if (ValueVT.bitsLT(Val.getValueType()))
207 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
208 DAG.getTargetConstant(1, TLI.getPointerTy()));
210 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
213 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
214 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
216 llvm_unreachable("Unknown mismatch!");
219 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
220 const Twine &ErrMsg) {
221 const Instruction *I = dyn_cast_or_null<Instruction>(V);
223 return Ctx.emitError(ErrMsg);
225 const char *AsmError = ", possible invalid constraint for vector type";
226 if (const CallInst *CI = dyn_cast<CallInst>(I))
227 if (isa<InlineAsm>(CI->getCalledValue()))
228 return Ctx.emitError(I, ErrMsg + AsmError);
230 return Ctx.emitError(I, ErrMsg);
233 /// getCopyFromPartsVector - Create a value that contains the specified legal
234 /// parts combined into the value they represent. If the parts combine to a
235 /// type larger then ValueVT then AssertOp can be used to specify whether the
236 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
237 /// ValueVT (ISD::AssertSext).
238 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
239 const SDValue *Parts, unsigned NumParts,
240 MVT PartVT, EVT ValueVT, const Value *V) {
241 assert(ValueVT.isVector() && "Not a vector value");
242 assert(NumParts > 0 && "No parts to assemble!");
243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
244 SDValue Val = Parts[0];
246 // Handle a multi-element vector.
250 unsigned NumIntermediates;
252 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
253 NumIntermediates, RegisterVT);
254 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
255 NumParts = NumRegs; // Silence a compiler warning.
256 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
257 assert(RegisterVT == Parts[0].getSimpleValueType() &&
258 "Part type doesn't match part!");
260 // Assemble the parts into intermediate operands.
261 SmallVector<SDValue, 8> Ops(NumIntermediates);
262 if (NumIntermediates == NumParts) {
263 // If the register was not expanded, truncate or copy the value,
265 for (unsigned i = 0; i != NumParts; ++i)
266 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
267 PartVT, IntermediateVT, V);
268 } else if (NumParts > 0) {
269 // If the intermediate type was expanded, build the intermediate
270 // operands from the parts.
271 assert(NumParts % NumIntermediates == 0 &&
272 "Must expand into a divisible number of parts!");
273 unsigned Factor = NumParts / NumIntermediates;
274 for (unsigned i = 0; i != NumIntermediates; ++i)
275 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
276 PartVT, IntermediateVT, V);
279 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
280 // intermediate operands.
281 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
286 // There is now one part, held in Val. Correct it to match ValueVT.
287 EVT PartEVT = Val.getValueType();
289 if (PartEVT == ValueVT)
292 if (PartEVT.isVector()) {
293 // If the element type of the source/dest vectors are the same, but the
294 // parts vector has more elements than the value vector, then we have a
295 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
297 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
298 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
299 "Cannot narrow, it would be a lossy transformation");
300 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
301 DAG.getConstant(0, TLI.getVectorIdxTy()));
304 // Vector/Vector bitcast.
305 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
306 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
308 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
309 "Cannot handle this kind of promotion");
310 // Promoted vector extract
311 bool Smaller = ValueVT.bitsLE(PartEVT);
312 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
317 // Trivial bitcast if the types are the same size and the destination
318 // vector type is legal.
319 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
320 TLI.isTypeLegal(ValueVT))
321 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
323 // Handle cases such as i8 -> <1 x i1>
324 if (ValueVT.getVectorNumElements() != 1) {
325 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
326 "non-trivial scalar-to-vector conversion");
327 return DAG.getUNDEF(ValueVT);
330 if (ValueVT.getVectorNumElements() == 1 &&
331 ValueVT.getVectorElementType() != PartEVT) {
332 bool Smaller = ValueVT.bitsLE(PartEVT);
333 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
334 DL, ValueVT.getScalarType(), Val);
337 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
340 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
341 SDValue Val, SDValue *Parts, unsigned NumParts,
342 MVT PartVT, const Value *V);
344 /// getCopyToParts - Create a series of nodes that contain the specified value
345 /// split into legal parts. If the parts contain more bits than Val, then, for
346 /// integers, ExtendKind can be used to specify how to generate the extra bits.
347 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
348 SDValue Val, SDValue *Parts, unsigned NumParts,
349 MVT PartVT, const Value *V,
350 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
351 EVT ValueVT = Val.getValueType();
353 // Handle the vector case separately.
354 if (ValueVT.isVector())
355 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
357 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
358 unsigned PartBits = PartVT.getSizeInBits();
359 unsigned OrigNumParts = NumParts;
360 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
365 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
366 EVT PartEVT = PartVT;
367 if (PartEVT == ValueVT) {
368 assert(NumParts == 1 && "No-op copy with multiple parts!");
373 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
374 // If the parts cover more bits than the value has, promote the value.
375 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
376 assert(NumParts == 1 && "Do not know what to promote to!");
377 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
379 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
380 ValueVT.isInteger() &&
381 "Unknown mismatch!");
382 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
383 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
384 if (PartVT == MVT::x86mmx)
385 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
387 } else if (PartBits == ValueVT.getSizeInBits()) {
388 // Different types of the same size.
389 assert(NumParts == 1 && PartEVT != ValueVT);
390 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
392 // If the parts cover less bits than value has, truncate the value.
393 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
394 ValueVT.isInteger() &&
395 "Unknown mismatch!");
396 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
397 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
398 if (PartVT == MVT::x86mmx)
399 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
402 // The value may have changed - recompute ValueVT.
403 ValueVT = Val.getValueType();
404 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
405 "Failed to tile the value with PartVT!");
408 if (PartEVT != ValueVT)
409 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
410 "scalar-to-vector conversion failed");
416 // Expand the value into multiple parts.
417 if (NumParts & (NumParts - 1)) {
418 // The number of parts is not a power of 2. Split off and copy the tail.
419 assert(PartVT.isInteger() && ValueVT.isInteger() &&
420 "Do not know what to expand to!");
421 unsigned RoundParts = 1 << Log2_32(NumParts);
422 unsigned RoundBits = RoundParts * PartBits;
423 unsigned OddParts = NumParts - RoundParts;
424 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
425 DAG.getIntPtrConstant(RoundBits));
426 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
428 if (TLI.isBigEndian())
429 // The odd parts were reversed by getCopyToParts - unreverse them.
430 std::reverse(Parts + RoundParts, Parts + NumParts);
432 NumParts = RoundParts;
433 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
434 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
437 // The number of parts is a power of 2. Repeatedly bisect the value using
439 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
440 EVT::getIntegerVT(*DAG.getContext(),
441 ValueVT.getSizeInBits()),
444 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
445 for (unsigned i = 0; i < NumParts; i += StepSize) {
446 unsigned ThisBits = StepSize * PartBits / 2;
447 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
448 SDValue &Part0 = Parts[i];
449 SDValue &Part1 = Parts[i+StepSize/2];
451 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
452 ThisVT, Part0, DAG.getIntPtrConstant(1));
453 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
454 ThisVT, Part0, DAG.getIntPtrConstant(0));
456 if (ThisBits == PartBits && ThisVT != PartVT) {
457 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
458 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
463 if (TLI.isBigEndian())
464 std::reverse(Parts, Parts + OrigNumParts);
468 /// getCopyToPartsVector - Create a series of nodes that contain the specified
469 /// value split into legal parts.
470 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
471 SDValue Val, SDValue *Parts, unsigned NumParts,
472 MVT PartVT, const Value *V) {
473 EVT ValueVT = Val.getValueType();
474 assert(ValueVT.isVector() && "Not a vector");
475 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
478 EVT PartEVT = PartVT;
479 if (PartEVT == ValueVT) {
481 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
482 // Bitconvert vector->vector case.
483 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
484 } else if (PartVT.isVector() &&
485 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
486 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
487 EVT ElementVT = PartVT.getVectorElementType();
488 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
490 SmallVector<SDValue, 16> Ops;
491 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
492 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
493 ElementVT, Val, DAG.getConstant(i,
494 TLI.getVectorIdxTy())));
496 for (unsigned i = ValueVT.getVectorNumElements(),
497 e = PartVT.getVectorNumElements(); i != e; ++i)
498 Ops.push_back(DAG.getUNDEF(ElementVT));
500 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
502 // FIXME: Use CONCAT for 2x -> 4x.
504 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
505 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType().bitsGE(
508 ValueVT.getVectorElementType()) &&
509 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
511 // Promoted vector extract
512 bool Smaller = PartEVT.bitsLE(ValueVT);
513 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
516 // Vector -> scalar conversion.
517 assert(ValueVT.getVectorNumElements() == 1 &&
518 "Only trivial vector-to-scalar conversions should get here!");
519 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
520 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
522 bool Smaller = ValueVT.bitsLE(PartVT);
523 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
531 // Handle a multi-element vector.
534 unsigned NumIntermediates;
535 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
537 NumIntermediates, RegisterVT);
538 unsigned NumElements = ValueVT.getVectorNumElements();
540 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
541 NumParts = NumRegs; // Silence a compiler warning.
542 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
544 // Split the vector into intermediate operands.
545 SmallVector<SDValue, 8> Ops(NumIntermediates);
546 for (unsigned i = 0; i != NumIntermediates; ++i) {
547 if (IntermediateVT.isVector())
548 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
550 DAG.getConstant(i * (NumElements / NumIntermediates),
551 TLI.getVectorIdxTy()));
553 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
555 DAG.getConstant(i, TLI.getVectorIdxTy()));
558 // Split the intermediate operands into legal parts.
559 if (NumParts == NumIntermediates) {
560 // If the register was not expanded, promote or copy the value,
562 for (unsigned i = 0; i != NumParts; ++i)
563 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
564 } else if (NumParts > 0) {
565 // If the intermediate type was expanded, split each the value into
567 assert(NumParts % NumIntermediates == 0 &&
568 "Must expand into a divisible number of parts!");
569 unsigned Factor = NumParts / NumIntermediates;
570 for (unsigned i = 0; i != NumIntermediates; ++i)
571 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
576 /// RegsForValue - This struct represents the registers (physical or virtual)
577 /// that a particular set of values is assigned, and the type information
578 /// about the value. The most common situation is to represent one value at a
579 /// time, but struct or array values are handled element-wise as multiple
580 /// values. The splitting of aggregates is performed recursively, so that we
581 /// never have aggregate-typed registers. The values at this point do not
582 /// necessarily have legal types, so each value may require one or more
583 /// registers of some legal type.
585 struct RegsForValue {
586 /// ValueVTs - The value types of the values, which may not be legal, and
587 /// may need be promoted or synthesized from one or more registers.
589 SmallVector<EVT, 4> ValueVTs;
591 /// RegVTs - The value types of the registers. This is the same size as
592 /// ValueVTs and it records, for each value, what the type of the assigned
593 /// register or registers are. (Individual values are never synthesized
594 /// from more than one type of register.)
596 /// With virtual registers, the contents of RegVTs is redundant with TLI's
597 /// getRegisterType member function, however when with physical registers
598 /// it is necessary to have a separate record of the types.
600 SmallVector<MVT, 4> RegVTs;
602 /// Regs - This list holds the registers assigned to the values.
603 /// Each legal or promoted value requires one register, and each
604 /// expanded value requires multiple registers.
606 SmallVector<unsigned, 4> Regs;
610 RegsForValue(const SmallVector<unsigned, 4> ®s,
611 MVT regvt, EVT valuevt)
612 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
614 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
615 unsigned Reg, Type *Ty) {
616 ComputeValueVTs(tli, Ty, ValueVTs);
618 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
619 EVT ValueVT = ValueVTs[Value];
620 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
621 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
622 for (unsigned i = 0; i != NumRegs; ++i)
623 Regs.push_back(Reg + i);
624 RegVTs.push_back(RegisterVT);
629 /// append - Add the specified values to this one.
630 void append(const RegsForValue &RHS) {
631 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
632 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
633 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
636 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
637 /// this value and returns the result as a ValueVTs value. This uses
638 /// Chain/Flag as the input and updates them for the output Chain/Flag.
639 /// If the Flag pointer is NULL, no flag is used.
640 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
642 SDValue &Chain, SDValue *Flag,
643 const Value *V = nullptr) const;
645 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
646 /// specified value into the registers specified by this object. This uses
647 /// Chain/Flag as the input and updates them for the output Chain/Flag.
648 /// If the Flag pointer is NULL, no flag is used.
650 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
651 SDValue *Flag, const Value *V,
652 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
654 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
655 /// operand list. This adds the code marker, matching input operand index
656 /// (if applicable), and includes the number of values added into it.
657 void AddInlineAsmOperands(unsigned Kind,
658 bool HasMatching, unsigned MatchingIdx,
660 std::vector<SDValue> &Ops) const;
664 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
665 /// this value and returns the result as a ValueVT value. This uses
666 /// Chain/Flag as the input and updates them for the output Chain/Flag.
667 /// If the Flag pointer is NULL, no flag is used.
668 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
669 FunctionLoweringInfo &FuncInfo,
671 SDValue &Chain, SDValue *Flag,
672 const Value *V) const {
673 // A Value with type {} or [0 x %t] needs no registers.
674 if (ValueVTs.empty())
677 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
679 // Assemble the legal parts into the final values.
680 SmallVector<SDValue, 4> Values(ValueVTs.size());
681 SmallVector<SDValue, 8> Parts;
682 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
683 // Copy the legal parts from the registers.
684 EVT ValueVT = ValueVTs[Value];
685 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
686 MVT RegisterVT = RegVTs[Value];
688 Parts.resize(NumRegs);
689 for (unsigned i = 0; i != NumRegs; ++i) {
692 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
694 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
695 *Flag = P.getValue(2);
698 Chain = P.getValue(1);
701 // If the source register was virtual and if we know something about it,
702 // add an assert node.
703 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
704 !RegisterVT.isInteger() || RegisterVT.isVector())
707 const FunctionLoweringInfo::LiveOutInfo *LOI =
708 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
712 unsigned RegSize = RegisterVT.getSizeInBits();
713 unsigned NumSignBits = LOI->NumSignBits;
714 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
716 if (NumZeroBits == RegSize) {
717 // The current value is a zero.
718 // Explicitly express that as it would be easier for
719 // optimizations to kick in.
720 Parts[i] = DAG.getConstant(0, RegisterVT);
724 // FIXME: We capture more information than the dag can represent. For
725 // now, just use the tightest assertzext/assertsext possible.
727 EVT FromVT(MVT::Other);
728 if (NumSignBits == RegSize)
729 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
730 else if (NumZeroBits >= RegSize-1)
731 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
732 else if (NumSignBits > RegSize-8)
733 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
734 else if (NumZeroBits >= RegSize-8)
735 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
736 else if (NumSignBits > RegSize-16)
737 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
738 else if (NumZeroBits >= RegSize-16)
739 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
740 else if (NumSignBits > RegSize-32)
741 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
742 else if (NumZeroBits >= RegSize-32)
743 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
747 // Add an assertion node.
748 assert(FromVT != MVT::Other);
749 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
750 RegisterVT, P, DAG.getValueType(FromVT));
753 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
754 NumRegs, RegisterVT, ValueVT, V);
759 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
762 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
763 /// specified value into the registers specified by this object. This uses
764 /// Chain/Flag as the input and updates them for the output Chain/Flag.
765 /// If the Flag pointer is NULL, no flag is used.
766 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
767 SDValue &Chain, SDValue *Flag, const Value *V,
768 ISD::NodeType PreferredExtendType) const {
769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
770 ISD::NodeType ExtendKind = PreferredExtendType;
772 // Get the list of the values's legal parts.
773 unsigned NumRegs = Regs.size();
774 SmallVector<SDValue, 8> Parts(NumRegs);
775 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
776 EVT ValueVT = ValueVTs[Value];
777 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
778 MVT RegisterVT = RegVTs[Value];
780 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
781 ExtendKind = ISD::ZERO_EXTEND;
783 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
784 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
788 // Copy the parts into the registers.
789 SmallVector<SDValue, 8> Chains(NumRegs);
790 for (unsigned i = 0; i != NumRegs; ++i) {
793 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
795 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
796 *Flag = Part.getValue(1);
799 Chains[i] = Part.getValue(0);
802 if (NumRegs == 1 || Flag)
803 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
804 // flagged to it. That is the CopyToReg nodes and the user are considered
805 // a single scheduling unit. If we create a TokenFactor and return it as
806 // chain, then the TokenFactor is both a predecessor (operand) of the
807 // user as well as a successor (the TF operands are flagged to the user).
808 // c1, f1 = CopyToReg
809 // c2, f2 = CopyToReg
810 // c3 = TokenFactor c1, c2
813 Chain = Chains[NumRegs-1];
815 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
818 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
819 /// operand list. This adds the code marker and includes the number of
820 /// values added into it.
821 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
822 unsigned MatchingIdx,
824 std::vector<SDValue> &Ops) const {
825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
827 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
829 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
830 else if (!Regs.empty() &&
831 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
832 // Put the register class of the virtual registers in the flag word. That
833 // way, later passes can recompute register class constraints for inline
834 // assembly as well as normal instructions.
835 // Don't do this for tied operands that can use the regclass information
837 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
838 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
839 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
842 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
845 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
846 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
847 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
848 MVT RegisterVT = RegVTs[Value];
849 for (unsigned i = 0; i != NumRegs; ++i) {
850 assert(Reg < Regs.size() && "Mismatch in # registers expected");
851 unsigned TheReg = Regs[Reg++];
852 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
854 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
855 // If we clobbered the stack pointer, MFI should know about it.
856 assert(DAG.getMachineFunction().getFrameInfo()->
857 hasInlineAsmWithSPAdjust());
863 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
864 const TargetLibraryInfo *li) {
868 DL = DAG.getSubtarget().getDataLayout();
869 Context = DAG.getContext();
870 LPadToCallSiteMap.clear();
873 /// clear - Clear out the current SelectionDAG and the associated
874 /// state and prepare this SelectionDAGBuilder object to be used
875 /// for a new block. This doesn't clear out information about
876 /// additional blocks that are needed to complete switch lowering
877 /// or PHI node updating; that information is cleared out as it is
879 void SelectionDAGBuilder::clear() {
881 UnusedArgNodeMap.clear();
882 PendingLoads.clear();
883 PendingExports.clear();
886 SDNodeOrder = LowestSDNodeOrder;
889 /// clearDanglingDebugInfo - Clear the dangling debug information
890 /// map. This function is separated from the clear so that debug
891 /// information that is dangling in a basic block can be properly
892 /// resolved in a different basic block. This allows the
893 /// SelectionDAG to resolve dangling debug information attached
895 void SelectionDAGBuilder::clearDanglingDebugInfo() {
896 DanglingDebugInfoMap.clear();
899 /// getRoot - Return the current virtual root of the Selection DAG,
900 /// flushing any PendingLoad items. This must be done before emitting
901 /// a store or any other node that may need to be ordered after any
902 /// prior load instructions.
904 SDValue SelectionDAGBuilder::getRoot() {
905 if (PendingLoads.empty())
906 return DAG.getRoot();
908 if (PendingLoads.size() == 1) {
909 SDValue Root = PendingLoads[0];
911 PendingLoads.clear();
915 // Otherwise, we have to make a token factor node.
916 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
918 PendingLoads.clear();
923 /// getControlRoot - Similar to getRoot, but instead of flushing all the
924 /// PendingLoad items, flush all the PendingExports items. It is necessary
925 /// to do this before emitting a terminator instruction.
927 SDValue SelectionDAGBuilder::getControlRoot() {
928 SDValue Root = DAG.getRoot();
930 if (PendingExports.empty())
933 // Turn all of the CopyToReg chains into one factored node.
934 if (Root.getOpcode() != ISD::EntryToken) {
935 unsigned i = 0, e = PendingExports.size();
936 for (; i != e; ++i) {
937 assert(PendingExports[i].getNode()->getNumOperands() > 1);
938 if (PendingExports[i].getNode()->getOperand(0) == Root)
939 break; // Don't add the root if we already indirectly depend on it.
943 PendingExports.push_back(Root);
946 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
948 PendingExports.clear();
953 void SelectionDAGBuilder::visit(const Instruction &I) {
954 // Set up outgoing PHI node register values before emitting the terminator.
955 if (isa<TerminatorInst>(&I))
956 HandlePHINodesInSuccessorBlocks(I.getParent());
962 visit(I.getOpcode(), I);
964 if (!isa<TerminatorInst>(&I) && !HasTailCall)
965 CopyToExportRegsIfNeeded(&I);
970 void SelectionDAGBuilder::visitPHI(const PHINode &) {
971 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
974 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
975 // Note: this doesn't use InstVisitor, because it has to work with
976 // ConstantExpr's in addition to instructions.
978 default: llvm_unreachable("Unknown instruction type encountered!");
979 // Build the switch statement using the Instruction.def file.
980 #define HANDLE_INST(NUM, OPCODE, CLASS) \
981 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
982 #include "llvm/IR/Instruction.def"
986 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
987 // generate the debug data structures now that we've seen its definition.
988 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
990 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
992 const DbgValueInst *DI = DDI.getDI();
993 DebugLoc dl = DDI.getdl();
994 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
995 MDNode *Variable = DI->getVariable();
996 MDNode *Expr = DI->getExpression();
997 uint64_t Offset = DI->getOffset();
998 // A dbg.value for an alloca is always indirect.
999 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1001 if (Val.getNode()) {
1002 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, Offset, IsIndirect,
1004 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1005 IsIndirect, Offset, dl, DbgSDNodeOrder);
1006 DAG.AddDbgValue(SDV, Val.getNode(), false);
1009 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1010 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1014 /// getValue - Return an SDValue for the given Value.
1015 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1016 // If we already have an SDValue for this value, use it. It's important
1017 // to do this first, so that we don't create a CopyFromReg if we already
1018 // have a regular SDValue.
1019 SDValue &N = NodeMap[V];
1020 if (N.getNode()) return N;
1022 // If there's a virtual register allocated and initialized for this
1024 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1025 if (It != FuncInfo.ValueMap.end()) {
1026 unsigned InReg = It->second;
1027 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1029 SDValue Chain = DAG.getEntryNode();
1030 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1031 resolveDanglingDebugInfo(V, N);
1035 // Otherwise create a new SDValue and remember it.
1036 SDValue Val = getValueImpl(V);
1038 resolveDanglingDebugInfo(V, Val);
1042 /// getNonRegisterValue - Return an SDValue for the given Value, but
1043 /// don't look in FuncInfo.ValueMap for a virtual register.
1044 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1045 // If we already have an SDValue for this value, use it.
1046 SDValue &N = NodeMap[V];
1047 if (N.getNode()) return N;
1049 // Otherwise create a new SDValue and remember it.
1050 SDValue Val = getValueImpl(V);
1052 resolveDanglingDebugInfo(V, Val);
1056 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1057 /// Create an SDValue for the given value.
1058 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1061 if (const Constant *C = dyn_cast<Constant>(V)) {
1062 EVT VT = TLI.getValueType(V->getType(), true);
1064 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1065 return DAG.getConstant(*CI, VT);
1067 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1068 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1070 if (isa<ConstantPointerNull>(C)) {
1071 unsigned AS = V->getType()->getPointerAddressSpace();
1072 return DAG.getConstant(0, TLI.getPointerTy(AS));
1075 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1076 return DAG.getConstantFP(*CFP, VT);
1078 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1079 return DAG.getUNDEF(VT);
1081 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1082 visit(CE->getOpcode(), *CE);
1083 SDValue N1 = NodeMap[V];
1084 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1088 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1089 SmallVector<SDValue, 4> Constants;
1090 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1092 SDNode *Val = getValue(*OI).getNode();
1093 // If the operand is an empty aggregate, there are no values.
1095 // Add each leaf value from the operand to the Constants list
1096 // to form a flattened list of all the values.
1097 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1098 Constants.push_back(SDValue(Val, i));
1101 return DAG.getMergeValues(Constants, getCurSDLoc());
1104 if (const ConstantDataSequential *CDS =
1105 dyn_cast<ConstantDataSequential>(C)) {
1106 SmallVector<SDValue, 4> Ops;
1107 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1108 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1109 // Add each leaf value from the operand to the Constants list
1110 // to form a flattened list of all the values.
1111 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1112 Ops.push_back(SDValue(Val, i));
1115 if (isa<ArrayType>(CDS->getType()))
1116 return DAG.getMergeValues(Ops, getCurSDLoc());
1117 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1121 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1122 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1123 "Unknown struct or array constant!");
1125 SmallVector<EVT, 4> ValueVTs;
1126 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1127 unsigned NumElts = ValueVTs.size();
1129 return SDValue(); // empty struct
1130 SmallVector<SDValue, 4> Constants(NumElts);
1131 for (unsigned i = 0; i != NumElts; ++i) {
1132 EVT EltVT = ValueVTs[i];
1133 if (isa<UndefValue>(C))
1134 Constants[i] = DAG.getUNDEF(EltVT);
1135 else if (EltVT.isFloatingPoint())
1136 Constants[i] = DAG.getConstantFP(0, EltVT);
1138 Constants[i] = DAG.getConstant(0, EltVT);
1141 return DAG.getMergeValues(Constants, getCurSDLoc());
1144 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1145 return DAG.getBlockAddress(BA, VT);
1147 VectorType *VecTy = cast<VectorType>(V->getType());
1148 unsigned NumElements = VecTy->getNumElements();
1150 // Now that we know the number and type of the elements, get that number of
1151 // elements into the Ops array based on what kind of constant it is.
1152 SmallVector<SDValue, 16> Ops;
1153 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1154 for (unsigned i = 0; i != NumElements; ++i)
1155 Ops.push_back(getValue(CV->getOperand(i)));
1157 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1158 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1161 if (EltVT.isFloatingPoint())
1162 Op = DAG.getConstantFP(0, EltVT);
1164 Op = DAG.getConstant(0, EltVT);
1165 Ops.assign(NumElements, Op);
1168 // Create a BUILD_VECTOR node.
1169 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1172 // If this is a static alloca, generate it as the frameindex instead of
1174 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1175 DenseMap<const AllocaInst*, int>::iterator SI =
1176 FuncInfo.StaticAllocaMap.find(AI);
1177 if (SI != FuncInfo.StaticAllocaMap.end())
1178 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1181 // If this is an instruction which fast-isel has deferred, select it now.
1182 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1183 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1184 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1185 SDValue Chain = DAG.getEntryNode();
1186 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1189 llvm_unreachable("Can't get register for value!");
1192 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1193 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1194 SDValue Chain = getControlRoot();
1195 SmallVector<ISD::OutputArg, 8> Outs;
1196 SmallVector<SDValue, 8> OutVals;
1198 if (!FuncInfo.CanLowerReturn) {
1199 unsigned DemoteReg = FuncInfo.DemoteRegister;
1200 const Function *F = I.getParent()->getParent();
1202 // Emit a store of the return value through the virtual register.
1203 // Leave Outs empty so that LowerReturn won't try to load return
1204 // registers the usual way.
1205 SmallVector<EVT, 1> PtrValueVTs;
1206 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1209 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1210 SDValue RetOp = getValue(I.getOperand(0));
1212 SmallVector<EVT, 4> ValueVTs;
1213 SmallVector<uint64_t, 4> Offsets;
1214 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1215 unsigned NumValues = ValueVTs.size();
1217 SmallVector<SDValue, 4> Chains(NumValues);
1218 for (unsigned i = 0; i != NumValues; ++i) {
1219 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1220 RetPtr.getValueType(), RetPtr,
1221 DAG.getIntPtrConstant(Offsets[i]));
1223 DAG.getStore(Chain, getCurSDLoc(),
1224 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1225 // FIXME: better loc info would be nice.
1226 Add, MachinePointerInfo(), false, false, 0);
1229 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1230 MVT::Other, Chains);
1231 } else if (I.getNumOperands() != 0) {
1232 SmallVector<EVT, 4> ValueVTs;
1233 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1234 unsigned NumValues = ValueVTs.size();
1236 SDValue RetOp = getValue(I.getOperand(0));
1237 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1238 EVT VT = ValueVTs[j];
1240 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1242 const Function *F = I.getParent()->getParent();
1243 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1245 ExtendKind = ISD::SIGN_EXTEND;
1246 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1248 ExtendKind = ISD::ZERO_EXTEND;
1250 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1251 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1253 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1254 MVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1255 SmallVector<SDValue, 4> Parts(NumParts);
1256 getCopyToParts(DAG, getCurSDLoc(),
1257 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1258 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1260 // 'inreg' on function refers to return value
1261 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1262 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1266 // Propagate extension type if any
1267 if (ExtendKind == ISD::SIGN_EXTEND)
1269 else if (ExtendKind == ISD::ZERO_EXTEND)
1272 for (unsigned i = 0; i < NumParts; ++i) {
1273 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1274 VT, /*isfixed=*/true, 0, 0));
1275 OutVals.push_back(Parts[i]);
1281 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1282 CallingConv::ID CallConv =
1283 DAG.getMachineFunction().getFunction()->getCallingConv();
1284 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1285 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1287 // Verify that the target's LowerReturn behaved as expected.
1288 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1289 "LowerReturn didn't return a valid chain!");
1291 // Update the DAG with the new chain value resulting from return lowering.
1295 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1296 /// created for it, emit nodes to copy the value into the virtual
1298 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1300 if (V->getType()->isEmptyTy())
1303 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1304 if (VMI != FuncInfo.ValueMap.end()) {
1305 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1306 CopyValueToVirtualRegister(V, VMI->second);
1310 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1311 /// the current basic block, add it to ValueMap now so that we'll get a
1313 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1314 // No need to export constants.
1315 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1317 // Already exported?
1318 if (FuncInfo.isExportedInst(V)) return;
1320 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1321 CopyValueToVirtualRegister(V, Reg);
1324 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1325 const BasicBlock *FromBB) {
1326 // The operands of the setcc have to be in this block. We don't know
1327 // how to export them from some other block.
1328 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1329 // Can export from current BB.
1330 if (VI->getParent() == FromBB)
1333 // Is already exported, noop.
1334 return FuncInfo.isExportedInst(V);
1337 // If this is an argument, we can export it if the BB is the entry block or
1338 // if it is already exported.
1339 if (isa<Argument>(V)) {
1340 if (FromBB == &FromBB->getParent()->getEntryBlock())
1343 // Otherwise, can only export this if it is already exported.
1344 return FuncInfo.isExportedInst(V);
1347 // Otherwise, constants can always be exported.
1351 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1352 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1353 const MachineBasicBlock *Dst) const {
1354 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1357 const BasicBlock *SrcBB = Src->getBasicBlock();
1358 const BasicBlock *DstBB = Dst->getBasicBlock();
1359 return BPI->getEdgeWeight(SrcBB, DstBB);
1362 void SelectionDAGBuilder::
1363 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1364 uint32_t Weight /* = 0 */) {
1366 Weight = getEdgeWeight(Src, Dst);
1367 Src->addSuccessor(Dst, Weight);
1371 static bool InBlock(const Value *V, const BasicBlock *BB) {
1372 if (const Instruction *I = dyn_cast<Instruction>(V))
1373 return I->getParent() == BB;
1377 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1378 /// This function emits a branch and is used at the leaves of an OR or an
1379 /// AND operator tree.
1382 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1383 MachineBasicBlock *TBB,
1384 MachineBasicBlock *FBB,
1385 MachineBasicBlock *CurBB,
1386 MachineBasicBlock *SwitchBB,
1389 const BasicBlock *BB = CurBB->getBasicBlock();
1391 // If the leaf of the tree is a comparison, merge the condition into
1393 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1394 // The operands of the cmp have to be in this block. We don't know
1395 // how to export them from some other block. If this is the first block
1396 // of the sequence, no exporting is needed.
1397 if (CurBB == SwitchBB ||
1398 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1399 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1400 ISD::CondCode Condition;
1401 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1402 Condition = getICmpCondCode(IC->getPredicate());
1403 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1404 Condition = getFCmpCondCode(FC->getPredicate());
1405 if (TM.Options.NoNaNsFPMath)
1406 Condition = getFCmpCodeWithoutNaN(Condition);
1408 Condition = ISD::SETEQ; // silence warning.
1409 llvm_unreachable("Unknown compare instruction");
1412 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1413 TBB, FBB, CurBB, TWeight, FWeight);
1414 SwitchCases.push_back(CB);
1419 // Create a CaseBlock record representing this branch.
1420 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1421 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1422 SwitchCases.push_back(CB);
1425 /// Scale down both weights to fit into uint32_t.
1426 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1427 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1428 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1429 NewTrue = NewTrue / Scale;
1430 NewFalse = NewFalse / Scale;
1433 /// FindMergedConditions - If Cond is an expression like
1434 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1435 MachineBasicBlock *TBB,
1436 MachineBasicBlock *FBB,
1437 MachineBasicBlock *CurBB,
1438 MachineBasicBlock *SwitchBB,
1439 unsigned Opc, uint32_t TWeight,
1441 // If this node is not part of the or/and tree, emit it as a branch.
1442 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1443 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1444 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1445 BOp->getParent() != CurBB->getBasicBlock() ||
1446 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1447 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1448 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1453 // Create TmpBB after CurBB.
1454 MachineFunction::iterator BBI = CurBB;
1455 MachineFunction &MF = DAG.getMachineFunction();
1456 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1457 CurBB->getParent()->insert(++BBI, TmpBB);
1459 if (Opc == Instruction::Or) {
1460 // Codegen X | Y as:
1469 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1470 // The requirement is that
1471 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1472 // = TrueProb for orignal BB.
1473 // Assuming the orignal weights are A and B, one choice is to set BB1's
1474 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1476 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1477 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1478 // TmpBB, but the math is more complicated.
1480 uint64_t NewTrueWeight = TWeight;
1481 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1482 ScaleWeights(NewTrueWeight, NewFalseWeight);
1483 // Emit the LHS condition.
1484 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1485 NewTrueWeight, NewFalseWeight);
1487 NewTrueWeight = TWeight;
1488 NewFalseWeight = 2 * (uint64_t)FWeight;
1489 ScaleWeights(NewTrueWeight, NewFalseWeight);
1490 // Emit the RHS condition into TmpBB.
1491 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1492 NewTrueWeight, NewFalseWeight);
1494 assert(Opc == Instruction::And && "Unknown merge op!");
1495 // Codegen X & Y as:
1503 // This requires creation of TmpBB after CurBB.
1505 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1506 // The requirement is that
1507 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1508 // = FalseProb for orignal BB.
1509 // Assuming the orignal weights are A and B, one choice is to set BB1's
1510 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1512 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1514 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1515 uint64_t NewFalseWeight = FWeight;
1516 ScaleWeights(NewTrueWeight, NewFalseWeight);
1517 // Emit the LHS condition.
1518 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1519 NewTrueWeight, NewFalseWeight);
1521 NewTrueWeight = 2 * (uint64_t)TWeight;
1522 NewFalseWeight = FWeight;
1523 ScaleWeights(NewTrueWeight, NewFalseWeight);
1524 // Emit the RHS condition into TmpBB.
1525 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1526 NewTrueWeight, NewFalseWeight);
1530 /// If the set of cases should be emitted as a series of branches, return true.
1531 /// If we should emit this as a bunch of and/or'd together conditions, return
1534 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1535 if (Cases.size() != 2) return true;
1537 // If this is two comparisons of the same values or'd or and'd together, they
1538 // will get folded into a single comparison, so don't emit two blocks.
1539 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1540 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1541 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1542 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1546 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1547 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1548 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1549 Cases[0].CC == Cases[1].CC &&
1550 isa<Constant>(Cases[0].CmpRHS) &&
1551 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1552 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1554 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1561 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1562 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1564 // Update machine-CFG edges.
1565 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1567 // Figure out which block is immediately after the current one.
1568 MachineBasicBlock *NextBlock = nullptr;
1569 MachineFunction::iterator BBI = BrMBB;
1570 if (++BBI != FuncInfo.MF->end())
1573 if (I.isUnconditional()) {
1574 // Update machine-CFG edges.
1575 BrMBB->addSuccessor(Succ0MBB);
1577 // If this is not a fall-through branch or optimizations are switched off,
1579 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1580 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1581 MVT::Other, getControlRoot(),
1582 DAG.getBasicBlock(Succ0MBB)));
1587 // If this condition is one of the special cases we handle, do special stuff
1589 const Value *CondVal = I.getCondition();
1590 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1592 // If this is a series of conditions that are or'd or and'd together, emit
1593 // this as a sequence of branches instead of setcc's with and/or operations.
1594 // As long as jumps are not expensive, this should improve performance.
1595 // For example, instead of something like:
1608 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1609 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1610 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1611 BOp->getOpcode() == Instruction::Or)) {
1612 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1613 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1614 getEdgeWeight(BrMBB, Succ1MBB));
1615 // If the compares in later blocks need to use values not currently
1616 // exported from this block, export them now. This block should always
1617 // be the first entry.
1618 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1620 // Allow some cases to be rejected.
1621 if (ShouldEmitAsBranches(SwitchCases)) {
1622 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1623 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1624 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1627 // Emit the branch for this block.
1628 visitSwitchCase(SwitchCases[0], BrMBB);
1629 SwitchCases.erase(SwitchCases.begin());
1633 // Okay, we decided not to do this, remove any inserted MBB's and clear
1635 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1636 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1638 SwitchCases.clear();
1642 // Create a CaseBlock record representing this branch.
1643 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1644 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1646 // Use visitSwitchCase to actually insert the fast branch sequence for this
1648 visitSwitchCase(CB, BrMBB);
1651 /// visitSwitchCase - Emits the necessary code to represent a single node in
1652 /// the binary search tree resulting from lowering a switch instruction.
1653 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1654 MachineBasicBlock *SwitchBB) {
1656 SDValue CondLHS = getValue(CB.CmpLHS);
1657 SDLoc dl = getCurSDLoc();
1659 // Build the setcc now.
1661 // Fold "(X == true)" to X and "(X == false)" to !X to
1662 // handle common cases produced by branch lowering.
1663 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1664 CB.CC == ISD::SETEQ)
1666 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1667 CB.CC == ISD::SETEQ) {
1668 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1669 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1671 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1673 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1675 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1676 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1678 SDValue CmpOp = getValue(CB.CmpMHS);
1679 EVT VT = CmpOp.getValueType();
1681 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1682 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1685 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1686 VT, CmpOp, DAG.getConstant(Low, VT));
1687 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1688 DAG.getConstant(High-Low, VT), ISD::SETULE);
1692 // Update successor info
1693 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1694 // TrueBB and FalseBB are always different unless the incoming IR is
1695 // degenerate. This only happens when running llc on weird IR.
1696 if (CB.TrueBB != CB.FalseBB)
1697 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1699 // Set NextBlock to be the MBB immediately after the current one, if any.
1700 // This is used to avoid emitting unnecessary branches to the next block.
1701 MachineBasicBlock *NextBlock = nullptr;
1702 MachineFunction::iterator BBI = SwitchBB;
1703 if (++BBI != FuncInfo.MF->end())
1706 // If the lhs block is the next block, invert the condition so that we can
1707 // fall through to the lhs instead of the rhs block.
1708 if (CB.TrueBB == NextBlock) {
1709 std::swap(CB.TrueBB, CB.FalseBB);
1710 SDValue True = DAG.getConstant(1, Cond.getValueType());
1711 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1714 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1715 MVT::Other, getControlRoot(), Cond,
1716 DAG.getBasicBlock(CB.TrueBB));
1718 // Insert the false branch. Do this even if it's a fall through branch,
1719 // this makes it easier to do DAG optimizations which require inverting
1720 // the branch condition.
1721 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1722 DAG.getBasicBlock(CB.FalseBB));
1724 DAG.setRoot(BrCond);
1727 /// visitJumpTable - Emit JumpTable node in the current MBB
1728 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1729 // Emit the code for the jump table
1730 assert(JT.Reg != -1U && "Should lower JT Header first!");
1731 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1732 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1734 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1735 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1736 MVT::Other, Index.getValue(1),
1738 DAG.setRoot(BrJumpTable);
1741 /// visitJumpTableHeader - This function emits necessary code to produce index
1742 /// in the JumpTable from switch case.
1743 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1744 JumpTableHeader &JTH,
1745 MachineBasicBlock *SwitchBB) {
1746 // Subtract the lowest switch case value from the value being switched on and
1747 // conditional branch to default mbb if the result is greater than the
1748 // difference between smallest and largest cases.
1749 SDValue SwitchOp = getValue(JTH.SValue);
1750 EVT VT = SwitchOp.getValueType();
1751 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1752 DAG.getConstant(JTH.First, VT));
1754 // The SDNode we just created, which holds the value being switched on minus
1755 // the smallest case value, needs to be copied to a virtual register so it
1756 // can be used as an index into the jump table in a subsequent basic block.
1757 // This value may be smaller or larger than the target's pointer type, and
1758 // therefore require extension or truncating.
1759 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1760 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1762 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1763 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1764 JumpTableReg, SwitchOp);
1765 JT.Reg = JumpTableReg;
1767 // Emit the range check for the jump table, and branch to the default block
1768 // for the switch statement if the value being switched on exceeds the largest
1769 // case in the switch.
1771 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1772 Sub.getValueType()),
1773 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1775 // Set NextBlock to be the MBB immediately after the current one, if any.
1776 // This is used to avoid emitting unnecessary branches to the next block.
1777 MachineBasicBlock *NextBlock = nullptr;
1778 MachineFunction::iterator BBI = SwitchBB;
1780 if (++BBI != FuncInfo.MF->end())
1783 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1784 MVT::Other, CopyTo, CMP,
1785 DAG.getBasicBlock(JT.Default));
1787 if (JT.MBB != NextBlock)
1788 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1789 DAG.getBasicBlock(JT.MBB));
1791 DAG.setRoot(BrCond);
1794 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1795 /// tail spliced into a stack protector check success bb.
1797 /// For a high level explanation of how this fits into the stack protector
1798 /// generation see the comment on the declaration of class
1799 /// StackProtectorDescriptor.
1800 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1801 MachineBasicBlock *ParentBB) {
1803 // First create the loads to the guard/stack slot for the comparison.
1804 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1805 EVT PtrTy = TLI.getPointerTy();
1807 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1808 int FI = MFI->getStackProtectorIndex();
1810 const Value *IRGuard = SPD.getGuard();
1811 SDValue GuardPtr = getValue(IRGuard);
1812 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1815 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1819 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1820 // guard value from the virtual register holding the value. Otherwise, emit a
1821 // volatile load to retrieve the stack guard value.
1822 unsigned GuardReg = SPD.getGuardReg();
1824 if (GuardReg && TLI.useLoadStackGuardNode())
1825 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1828 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1829 GuardPtr, MachinePointerInfo(IRGuard, 0),
1830 true, false, false, Align);
1832 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1834 MachinePointerInfo::getFixedStack(FI),
1835 true, false, false, Align);
1837 // Perform the comparison via a subtract/getsetcc.
1838 EVT VT = Guard.getValueType();
1839 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1842 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1843 Sub.getValueType()),
1844 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1846 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1847 // branch to failure MBB.
1848 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1849 MVT::Other, StackSlot.getOperand(0),
1850 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1851 // Otherwise branch to success MBB.
1852 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1854 DAG.getBasicBlock(SPD.getSuccessMBB()));
1859 /// Codegen the failure basic block for a stack protector check.
1861 /// A failure stack protector machine basic block consists simply of a call to
1862 /// __stack_chk_fail().
1864 /// For a high level explanation of how this fits into the stack protector
1865 /// generation see the comment on the declaration of class
1866 /// StackProtectorDescriptor.
1868 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1869 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1871 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1872 nullptr, 0, false, getCurSDLoc(), false, false).second;
1876 /// visitBitTestHeader - This function emits necessary code to produce value
1877 /// suitable for "bit tests"
1878 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1879 MachineBasicBlock *SwitchBB) {
1880 // Subtract the minimum value
1881 SDValue SwitchOp = getValue(B.SValue);
1882 EVT VT = SwitchOp.getValueType();
1883 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1884 DAG.getConstant(B.First, VT));
1887 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1889 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1890 Sub.getValueType()),
1891 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1893 // Determine the type of the test operands.
1894 bool UsePtrType = false;
1895 if (!TLI.isTypeLegal(VT))
1898 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1899 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1900 // Switch table case range are encoded into series of masks.
1901 // Just use pointer type, it's guaranteed to fit.
1907 VT = TLI.getPointerTy();
1908 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1911 B.RegVT = VT.getSimpleVT();
1912 B.Reg = FuncInfo.CreateReg(B.RegVT);
1913 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1916 // Set NextBlock to be the MBB immediately after the current one, if any.
1917 // This is used to avoid emitting unnecessary branches to the next block.
1918 MachineBasicBlock *NextBlock = nullptr;
1919 MachineFunction::iterator BBI = SwitchBB;
1920 if (++BBI != FuncInfo.MF->end())
1923 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1925 addSuccessorWithWeight(SwitchBB, B.Default);
1926 addSuccessorWithWeight(SwitchBB, MBB);
1928 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1929 MVT::Other, CopyTo, RangeCmp,
1930 DAG.getBasicBlock(B.Default));
1932 if (MBB != NextBlock)
1933 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1934 DAG.getBasicBlock(MBB));
1936 DAG.setRoot(BrRange);
1939 /// visitBitTestCase - this function produces one "bit test"
1940 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1941 MachineBasicBlock* NextMBB,
1942 uint32_t BranchWeightToNext,
1945 MachineBasicBlock *SwitchBB) {
1947 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1950 unsigned PopCount = CountPopulation_64(B.Mask);
1951 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1952 if (PopCount == 1) {
1953 // Testing for a single bit; just compare the shift count with what it
1954 // would need to be to shift a 1 bit in that position.
1956 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1957 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1958 } else if (PopCount == BB.Range) {
1959 // There is only one zero bit in the range, test for it directly.
1961 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1962 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), ISD::SETNE);
1964 // Make desired shift
1965 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1966 DAG.getConstant(1, VT), ShiftOp);
1968 // Emit bit tests and jumps
1969 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1970 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1971 Cmp = DAG.getSetCC(getCurSDLoc(),
1972 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1973 DAG.getConstant(0, VT), ISD::SETNE);
1976 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1977 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1978 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1979 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1981 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1982 MVT::Other, getControlRoot(),
1983 Cmp, DAG.getBasicBlock(B.TargetBB));
1985 // Set NextBlock to be the MBB immediately after the current one, if any.
1986 // This is used to avoid emitting unnecessary branches to the next block.
1987 MachineBasicBlock *NextBlock = nullptr;
1988 MachineFunction::iterator BBI = SwitchBB;
1989 if (++BBI != FuncInfo.MF->end())
1992 if (NextMBB != NextBlock)
1993 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1994 DAG.getBasicBlock(NextMBB));
1999 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2000 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2002 // Retrieve successors.
2003 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2004 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2006 const Value *Callee(I.getCalledValue());
2007 const Function *Fn = dyn_cast<Function>(Callee);
2008 if (isa<InlineAsm>(Callee))
2010 else if (Fn && Fn->isIntrinsic()) {
2011 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2012 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2014 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2016 // If the value of the invoke is used outside of its defining block, make it
2017 // available as a virtual register.
2018 CopyToExportRegsIfNeeded(&I);
2020 // Update successor info
2021 addSuccessorWithWeight(InvokeMBB, Return);
2022 addSuccessorWithWeight(InvokeMBB, LandingPad);
2024 // Drop into normal successor.
2025 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2026 MVT::Other, getControlRoot(),
2027 DAG.getBasicBlock(Return)));
2030 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2031 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2034 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2035 assert(FuncInfo.MBB->isLandingPad() &&
2036 "Call to landingpad not in landing pad!");
2038 MachineBasicBlock *MBB = FuncInfo.MBB;
2039 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2040 AddLandingPadInfo(LP, MMI, MBB);
2042 // If there aren't registers to copy the values into (e.g., during SjLj
2043 // exceptions), then don't bother to create these DAG nodes.
2044 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2045 if (TLI.getExceptionPointerRegister() == 0 &&
2046 TLI.getExceptionSelectorRegister() == 0)
2049 SmallVector<EVT, 2> ValueVTs;
2050 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2051 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2053 // Get the two live-in registers as SDValues. The physregs have already been
2054 // copied into virtual registers.
2056 Ops[0] = DAG.getZExtOrTrunc(
2057 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2058 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2059 getCurSDLoc(), ValueVTs[0]);
2060 Ops[1] = DAG.getZExtOrTrunc(
2061 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2062 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2063 getCurSDLoc(), ValueVTs[1]);
2066 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2067 DAG.getVTList(ValueVTs), Ops);
2071 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2072 /// small case ranges).
2073 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2074 CaseRecVector& WorkList,
2076 MachineBasicBlock *Default,
2077 MachineBasicBlock *SwitchBB) {
2078 // Size is the number of Cases represented by this range.
2079 size_t Size = CR.Range.second - CR.Range.first;
2083 // Get the MachineFunction which holds the current MBB. This is used when
2084 // inserting any additional MBBs necessary to represent the switch.
2085 MachineFunction *CurMF = FuncInfo.MF;
2087 // Figure out which block is immediately after the current one.
2088 MachineBasicBlock *NextBlock = nullptr;
2089 MachineFunction::iterator BBI = CR.CaseBB;
2091 if (++BBI != FuncInfo.MF->end())
2094 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2095 // If any two of the cases has the same destination, and if one value
2096 // is the same as the other, but has one bit unset that the other has set,
2097 // use bit manipulation to do two compares at once. For example:
2098 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2099 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2100 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2101 if (Size == 2 && CR.CaseBB == SwitchBB) {
2102 Case &Small = *CR.Range.first;
2103 Case &Big = *(CR.Range.second-1);
2105 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2106 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2107 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2109 // Check that there is only one bit different.
2110 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2111 (SmallValue | BigValue) == BigValue) {
2112 // Isolate the common bit.
2113 APInt CommonBit = BigValue & ~SmallValue;
2114 assert((SmallValue | CommonBit) == BigValue &&
2115 CommonBit.countPopulation() == 1 && "Not a common bit?");
2117 SDValue CondLHS = getValue(SV);
2118 EVT VT = CondLHS.getValueType();
2119 SDLoc DL = getCurSDLoc();
2121 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2122 DAG.getConstant(CommonBit, VT));
2123 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2124 Or, DAG.getConstant(BigValue, VT),
2127 // Update successor info.
2128 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2129 addSuccessorWithWeight(SwitchBB, Small.BB,
2130 Small.ExtraWeight + Big.ExtraWeight);
2131 addSuccessorWithWeight(SwitchBB, Default,
2132 // The default destination is the first successor in IR.
2133 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2135 // Insert the true branch.
2136 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2137 getControlRoot(), Cond,
2138 DAG.getBasicBlock(Small.BB));
2140 // Insert the false branch.
2141 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2142 DAG.getBasicBlock(Default));
2144 DAG.setRoot(BrCond);
2150 // Order cases by weight so the most likely case will be checked first.
2151 uint32_t UnhandledWeights = 0;
2153 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2154 uint32_t IWeight = I->ExtraWeight;
2155 UnhandledWeights += IWeight;
2156 for (CaseItr J = CR.Range.first; J < I; ++J) {
2157 uint32_t JWeight = J->ExtraWeight;
2158 if (IWeight > JWeight)
2163 // Rearrange the case blocks so that the last one falls through if possible.
2164 Case &BackCase = *(CR.Range.second-1);
2166 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2167 // The last case block won't fall through into 'NextBlock' if we emit the
2168 // branches in this order. See if rearranging a case value would help.
2169 // We start at the bottom as it's the case with the least weight.
2170 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2171 if (I->BB == NextBlock) {
2172 std::swap(*I, BackCase);
2177 // Create a CaseBlock record representing a conditional branch to
2178 // the Case's target mbb if the value being switched on SV is equal
2180 MachineBasicBlock *CurBlock = CR.CaseBB;
2181 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2182 MachineBasicBlock *FallThrough;
2184 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2185 CurMF->insert(BBI, FallThrough);
2187 // Put SV in a virtual register to make it available from the new blocks.
2188 ExportFromCurrentBlock(SV);
2190 // If the last case doesn't match, go to the default block.
2191 FallThrough = Default;
2194 const Value *RHS, *LHS, *MHS;
2196 if (I->High == I->Low) {
2197 // This is just small small case range :) containing exactly 1 case
2199 LHS = SV; RHS = I->High; MHS = nullptr;
2202 LHS = I->Low; MHS = SV; RHS = I->High;
2205 // The false weight should be sum of all un-handled cases.
2206 UnhandledWeights -= I->ExtraWeight;
2207 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2209 /* trueweight */ I->ExtraWeight,
2210 /* falseweight */ UnhandledWeights);
2212 // If emitting the first comparison, just call visitSwitchCase to emit the
2213 // code into the current block. Otherwise, push the CaseBlock onto the
2214 // vector to be later processed by SDISel, and insert the node's MBB
2215 // before the next MBB.
2216 if (CurBlock == SwitchBB)
2217 visitSwitchCase(CB, SwitchBB);
2219 SwitchCases.push_back(CB);
2221 CurBlock = FallThrough;
2227 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2228 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2229 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2232 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2233 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2234 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2235 return (LastExt - FirstExt + 1ULL);
2238 /// handleJTSwitchCase - Emit jumptable for current switch case range
2239 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2240 CaseRecVector &WorkList,
2242 MachineBasicBlock *Default,
2243 MachineBasicBlock *SwitchBB) {
2244 Case& FrontCase = *CR.Range.first;
2245 Case& BackCase = *(CR.Range.second-1);
2247 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2248 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2250 APInt TSize(First.getBitWidth(), 0);
2251 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2255 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2258 APInt Range = ComputeRange(First, Last);
2259 // The density is TSize / Range. Require at least 40%.
2260 // It should not be possible for IntTSize to saturate for sane code, but make
2261 // sure we handle Range saturation correctly.
2262 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2263 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2264 if (IntTSize * 10 < IntRange * 4)
2267 DEBUG(dbgs() << "Lowering jump table\n"
2268 << "First entry: " << First << ". Last entry: " << Last << '\n'
2269 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2271 // Get the MachineFunction which holds the current MBB. This is used when
2272 // inserting any additional MBBs necessary to represent the switch.
2273 MachineFunction *CurMF = FuncInfo.MF;
2275 // Figure out which block is immediately after the current one.
2276 MachineFunction::iterator BBI = CR.CaseBB;
2279 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2281 // Create a new basic block to hold the code for loading the address
2282 // of the jump table, and jumping to it. Update successor information;
2283 // we will either branch to the default case for the switch, or the jump
2285 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2286 CurMF->insert(BBI, JumpTableBB);
2288 addSuccessorWithWeight(CR.CaseBB, Default);
2289 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2291 // Build a vector of destination BBs, corresponding to each target
2292 // of the jump table. If the value of the jump table slot corresponds to
2293 // a case statement, push the case's BB onto the vector, otherwise, push
2295 std::vector<MachineBasicBlock*> DestBBs;
2297 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2298 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2299 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2301 if (Low.sle(TEI) && TEI.sle(High)) {
2302 DestBBs.push_back(I->BB);
2306 DestBBs.push_back(Default);
2310 // Calculate weight for each unique destination in CR.
2311 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2313 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2314 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2315 DestWeights.find(I->BB);
2316 if (Itr != DestWeights.end())
2317 Itr->second += I->ExtraWeight;
2319 DestWeights[I->BB] = I->ExtraWeight;
2322 // Update successor info. Add one edge to each unique successor.
2323 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2324 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2325 E = DestBBs.end(); I != E; ++I) {
2326 if (!SuccsHandled[(*I)->getNumber()]) {
2327 SuccsHandled[(*I)->getNumber()] = true;
2328 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2329 DestWeights.find(*I);
2330 addSuccessorWithWeight(JumpTableBB, *I,
2331 Itr != DestWeights.end() ? Itr->second : 0);
2335 // Create a jump table index for this jump table.
2336 unsigned JTEncoding = TLI.getJumpTableEncoding();
2337 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2338 ->createJumpTableIndex(DestBBs);
2340 // Set the jump table information so that we can codegen it as a second
2341 // MachineBasicBlock
2342 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2343 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2344 if (CR.CaseBB == SwitchBB)
2345 visitJumpTableHeader(JT, JTH, SwitchBB);
2347 JTCases.push_back(JumpTableBlock(JTH, JT));
2351 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2353 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2354 CaseRecVector& WorkList,
2356 MachineBasicBlock* SwitchBB) {
2357 // Get the MachineFunction which holds the current MBB. This is used when
2358 // inserting any additional MBBs necessary to represent the switch.
2359 MachineFunction *CurMF = FuncInfo.MF;
2361 // Figure out which block is immediately after the current one.
2362 MachineFunction::iterator BBI = CR.CaseBB;
2365 Case& FrontCase = *CR.Range.first;
2366 Case& BackCase = *(CR.Range.second-1);
2367 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2369 // Size is the number of Cases represented by this range.
2370 unsigned Size = CR.Range.second - CR.Range.first;
2372 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2373 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2375 CaseItr Pivot = CR.Range.first + Size/2;
2377 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2378 // (heuristically) allow us to emit JumpTable's later.
2379 APInt TSize(First.getBitWidth(), 0);
2380 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2384 APInt LSize = FrontCase.size();
2385 APInt RSize = TSize-LSize;
2386 DEBUG(dbgs() << "Selecting best pivot: \n"
2387 << "First: " << First << ", Last: " << Last <<'\n'
2388 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2389 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2391 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2392 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2393 APInt Range = ComputeRange(LEnd, RBegin);
2394 assert((Range - 2ULL).isNonNegative() &&
2395 "Invalid case distance");
2396 // Use volatile double here to avoid excess precision issues on some hosts,
2397 // e.g. that use 80-bit X87 registers.
2398 volatile double LDensity =
2399 (double)LSize.roundToDouble() /
2400 (LEnd - First + 1ULL).roundToDouble();
2401 volatile double RDensity =
2402 (double)RSize.roundToDouble() /
2403 (Last - RBegin + 1ULL).roundToDouble();
2404 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2405 // Should always split in some non-trivial place
2406 DEBUG(dbgs() <<"=>Step\n"
2407 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2408 << "LDensity: " << LDensity
2409 << ", RDensity: " << RDensity << '\n'
2410 << "Metric: " << Metric << '\n');
2411 if (FMetric < Metric) {
2414 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2421 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2422 if (areJTsAllowed(TLI)) {
2423 // If our case is dense we *really* should handle it earlier!
2424 assert((FMetric > 0) && "Should handle dense range earlier!");
2426 Pivot = CR.Range.first + Size/2;
2429 CaseRange LHSR(CR.Range.first, Pivot);
2430 CaseRange RHSR(Pivot, CR.Range.second);
2431 const Constant *C = Pivot->Low;
2432 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2434 // We know that we branch to the LHS if the Value being switched on is
2435 // less than the Pivot value, C. We use this to optimize our binary
2436 // tree a bit, by recognizing that if SV is greater than or equal to the
2437 // LHS's Case Value, and that Case Value is exactly one less than the
2438 // Pivot's Value, then we can branch directly to the LHS's Target,
2439 // rather than creating a leaf node for it.
2440 if ((LHSR.second - LHSR.first) == 1 &&
2441 LHSR.first->High == CR.GE &&
2442 cast<ConstantInt>(C)->getValue() ==
2443 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2444 TrueBB = LHSR.first->BB;
2446 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2447 CurMF->insert(BBI, TrueBB);
2448 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2450 // Put SV in a virtual register to make it available from the new blocks.
2451 ExportFromCurrentBlock(SV);
2454 // Similar to the optimization above, if the Value being switched on is
2455 // known to be less than the Constant CR.LT, and the current Case Value
2456 // is CR.LT - 1, then we can branch directly to the target block for
2457 // the current Case Value, rather than emitting a RHS leaf node for it.
2458 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2459 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2460 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2461 FalseBB = RHSR.first->BB;
2463 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2464 CurMF->insert(BBI, FalseBB);
2465 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2467 // Put SV in a virtual register to make it available from the new blocks.
2468 ExportFromCurrentBlock(SV);
2471 // Create a CaseBlock record representing a conditional branch to
2472 // the LHS node if the value being switched on SV is less than C.
2473 // Otherwise, branch to LHS.
2474 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2476 if (CR.CaseBB == SwitchBB)
2477 visitSwitchCase(CB, SwitchBB);
2479 SwitchCases.push_back(CB);
2484 /// handleBitTestsSwitchCase - if current case range has few destination and
2485 /// range span less, than machine word bitwidth, encode case range into series
2486 /// of masks and emit bit tests with these masks.
2487 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2488 CaseRecVector& WorkList,
2490 MachineBasicBlock* Default,
2491 MachineBasicBlock* SwitchBB) {
2492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2493 EVT PTy = TLI.getPointerTy();
2494 unsigned IntPtrBits = PTy.getSizeInBits();
2496 Case& FrontCase = *CR.Range.first;
2497 Case& BackCase = *(CR.Range.second-1);
2499 // Get the MachineFunction which holds the current MBB. This is used when
2500 // inserting any additional MBBs necessary to represent the switch.
2501 MachineFunction *CurMF = FuncInfo.MF;
2503 // If target does not have legal shift left, do not emit bit tests at all.
2504 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2508 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2510 // Single case counts one, case range - two.
2511 numCmps += (I->Low == I->High ? 1 : 2);
2514 // Count unique destinations
2515 SmallSet<MachineBasicBlock*, 4> Dests;
2516 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2517 Dests.insert(I->BB);
2518 if (Dests.size() > 3)
2519 // Don't bother the code below, if there are too much unique destinations
2522 DEBUG(dbgs() << "Total number of unique destinations: "
2523 << Dests.size() << '\n'
2524 << "Total number of comparisons: " << numCmps << '\n');
2526 // Compute span of values.
2527 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2528 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2529 APInt cmpRange = maxValue - minValue;
2531 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2532 << "Low bound: " << minValue << '\n'
2533 << "High bound: " << maxValue << '\n');
2535 if (cmpRange.uge(IntPtrBits) ||
2536 (!(Dests.size() == 1 && numCmps >= 3) &&
2537 !(Dests.size() == 2 && numCmps >= 5) &&
2538 !(Dests.size() >= 3 && numCmps >= 6)))
2541 DEBUG(dbgs() << "Emitting bit tests\n");
2542 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2544 // Optimize the case where all the case values fit in a
2545 // word without having to subtract minValue. In this case,
2546 // we can optimize away the subtraction.
2547 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2548 cmpRange = maxValue;
2550 lowBound = minValue;
2553 CaseBitsVector CasesBits;
2554 unsigned i, count = 0;
2556 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2557 MachineBasicBlock* Dest = I->BB;
2558 for (i = 0; i < count; ++i)
2559 if (Dest == CasesBits[i].BB)
2563 assert((count < 3) && "Too much destinations to test!");
2564 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2568 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2569 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2571 uint64_t lo = (lowValue - lowBound).getZExtValue();
2572 uint64_t hi = (highValue - lowBound).getZExtValue();
2573 CasesBits[i].ExtraWeight += I->ExtraWeight;
2575 for (uint64_t j = lo; j <= hi; j++) {
2576 CasesBits[i].Mask |= 1ULL << j;
2577 CasesBits[i].Bits++;
2581 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2585 // Figure out which block is immediately after the current one.
2586 MachineFunction::iterator BBI = CR.CaseBB;
2589 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2591 DEBUG(dbgs() << "Cases:\n");
2592 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2593 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2594 << ", Bits: " << CasesBits[i].Bits
2595 << ", BB: " << CasesBits[i].BB << '\n');
2597 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2598 CurMF->insert(BBI, CaseBB);
2599 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2601 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2603 // Put SV in a virtual register to make it available from the new blocks.
2604 ExportFromCurrentBlock(SV);
2607 BitTestBlock BTB(lowBound, cmpRange, SV,
2608 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2609 CR.CaseBB, Default, std::move(BTC));
2611 if (CR.CaseBB == SwitchBB)
2612 visitBitTestHeader(BTB, SwitchBB);
2614 BitTestCases.push_back(std::move(BTB));
2619 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2620 void SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2621 const SwitchInst& SI) {
2622 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2623 // Start with "simple" cases
2624 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2626 const BasicBlock *SuccBB = i.getCaseSuccessor();
2627 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2629 uint32_t ExtraWeight =
2630 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2632 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2633 SMBB, ExtraWeight));
2635 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2637 // Merge case into clusters
2638 if (Cases.size() >= 2)
2639 // Must recompute end() each iteration because it may be
2640 // invalidated by erase if we hold on to it
2641 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2642 J != Cases.end(); ) {
2643 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2644 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2645 MachineBasicBlock* nextBB = J->BB;
2646 MachineBasicBlock* currentBB = I->BB;
2648 // If the two neighboring cases go to the same destination, merge them
2649 // into a single case.
2650 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2652 I->ExtraWeight += J->ExtraWeight;
2661 for (auto &I : Cases)
2662 // A range counts double, since it requires two compares.
2663 numCmps += I.Low != I.High ? 2 : 1;
2665 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2666 << ". Total compares: " << numCmps << '\n';
2670 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2671 MachineBasicBlock *Last) {
2673 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2674 if (JTCases[i].first.HeaderBB == First)
2675 JTCases[i].first.HeaderBB = Last;
2677 // Update BitTestCases.
2678 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2679 if (BitTestCases[i].Parent == First)
2680 BitTestCases[i].Parent = Last;
2683 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2684 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2686 // Figure out which block is immediately after the current one.
2687 MachineBasicBlock *NextBlock = nullptr;
2688 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2690 // If there is only the default destination, branch to it if it is not the
2691 // next basic block. Otherwise, just fall through.
2692 if (!SI.getNumCases()) {
2693 // Update machine-CFG edges.
2695 // If this is not a fall-through branch, emit the branch.
2696 SwitchMBB->addSuccessor(Default);
2697 if (Default != NextBlock)
2698 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2699 MVT::Other, getControlRoot(),
2700 DAG.getBasicBlock(Default)));
2705 // If there are any non-default case statements, create a vector of Cases
2706 // representing each one, and sort the vector so that we can efficiently
2707 // create a binary search tree from them.
2709 Clusterify(Cases, SI);
2711 // Get the Value to be switched on and default basic blocks, which will be
2712 // inserted into CaseBlock records, representing basic blocks in the binary
2714 const Value *SV = SI.getCondition();
2716 // Push the initial CaseRec onto the worklist
2717 CaseRecVector WorkList;
2718 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2719 CaseRange(Cases.begin(),Cases.end())));
2721 while (!WorkList.empty()) {
2722 // Grab a record representing a case range to process off the worklist
2723 CaseRec CR = WorkList.back();
2724 WorkList.pop_back();
2726 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2729 // If the range has few cases (two or less) emit a series of specific
2731 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2734 // If the switch has more than N blocks, and is at least 40% dense, and the
2735 // target supports indirect branches, then emit a jump table rather than
2736 // lowering the switch to a binary tree of conditional branches.
2737 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2738 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2741 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2742 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2743 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2747 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2748 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2750 // Update machine-CFG edges with unique successors.
2751 SmallSet<BasicBlock*, 32> Done;
2752 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2753 BasicBlock *BB = I.getSuccessor(i);
2754 bool Inserted = Done.insert(BB);
2758 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2759 addSuccessorWithWeight(IndirectBrMBB, Succ);
2762 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2763 MVT::Other, getControlRoot(),
2764 getValue(I.getAddress())));
2767 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2768 if (DAG.getTarget().Options.TrapUnreachable)
2769 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2772 void SelectionDAGBuilder::visitFSub(const User &I) {
2773 // -0.0 - X --> fneg
2774 Type *Ty = I.getType();
2775 if (isa<Constant>(I.getOperand(0)) &&
2776 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2777 SDValue Op2 = getValue(I.getOperand(1));
2778 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2779 Op2.getValueType(), Op2));
2783 visitBinary(I, ISD::FSUB);
2786 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2787 SDValue Op1 = getValue(I.getOperand(0));
2788 SDValue Op2 = getValue(I.getOperand(1));
2793 if (const OverflowingBinaryOperator *OFBinOp =
2794 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2795 nuw = OFBinOp->hasNoUnsignedWrap();
2796 nsw = OFBinOp->hasNoSignedWrap();
2798 if (const PossiblyExactOperator *ExactOp =
2799 dyn_cast<const PossiblyExactOperator>(&I))
2800 exact = ExactOp->isExact();
2802 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2803 Op1, Op2, nuw, nsw, exact);
2804 setValue(&I, BinNodeValue);
2807 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2808 SDValue Op1 = getValue(I.getOperand(0));
2809 SDValue Op2 = getValue(I.getOperand(1));
2812 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2814 // Coerce the shift amount to the right type if we can.
2815 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2816 unsigned ShiftSize = ShiftTy.getSizeInBits();
2817 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2818 SDLoc DL = getCurSDLoc();
2820 // If the operand is smaller than the shift count type, promote it.
2821 if (ShiftSize > Op2Size)
2822 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2824 // If the operand is larger than the shift count type but the shift
2825 // count type has enough bits to represent any shift value, truncate
2826 // it now. This is a common case and it exposes the truncate to
2827 // optimization early.
2828 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2829 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2830 // Otherwise we'll need to temporarily settle for some other convenient
2831 // type. Type legalization will make adjustments once the shiftee is split.
2833 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2840 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2842 if (const OverflowingBinaryOperator *OFBinOp =
2843 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2844 nuw = OFBinOp->hasNoUnsignedWrap();
2845 nsw = OFBinOp->hasNoSignedWrap();
2847 if (const PossiblyExactOperator *ExactOp =
2848 dyn_cast<const PossiblyExactOperator>(&I))
2849 exact = ExactOp->isExact();
2852 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2857 void SelectionDAGBuilder::visitSDiv(const User &I) {
2858 SDValue Op1 = getValue(I.getOperand(0));
2859 SDValue Op2 = getValue(I.getOperand(1));
2861 // Turn exact SDivs into multiplications.
2862 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2864 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2865 !isa<ConstantSDNode>(Op1) &&
2866 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2867 setValue(&I, DAG.getTargetLoweringInfo()
2868 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2870 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2874 void SelectionDAGBuilder::visitICmp(const User &I) {
2875 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2876 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2877 predicate = IC->getPredicate();
2878 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2879 predicate = ICmpInst::Predicate(IC->getPredicate());
2880 SDValue Op1 = getValue(I.getOperand(0));
2881 SDValue Op2 = getValue(I.getOperand(1));
2882 ISD::CondCode Opcode = getICmpCondCode(predicate);
2884 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2885 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2888 void SelectionDAGBuilder::visitFCmp(const User &I) {
2889 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2890 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2891 predicate = FC->getPredicate();
2892 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2893 predicate = FCmpInst::Predicate(FC->getPredicate());
2894 SDValue Op1 = getValue(I.getOperand(0));
2895 SDValue Op2 = getValue(I.getOperand(1));
2896 ISD::CondCode Condition = getFCmpCondCode(predicate);
2897 if (TM.Options.NoNaNsFPMath)
2898 Condition = getFCmpCodeWithoutNaN(Condition);
2899 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2900 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2903 void SelectionDAGBuilder::visitSelect(const User &I) {
2904 SmallVector<EVT, 4> ValueVTs;
2905 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2906 unsigned NumValues = ValueVTs.size();
2907 if (NumValues == 0) return;
2909 SmallVector<SDValue, 4> Values(NumValues);
2910 SDValue Cond = getValue(I.getOperand(0));
2911 SDValue TrueVal = getValue(I.getOperand(1));
2912 SDValue FalseVal = getValue(I.getOperand(2));
2913 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2914 ISD::VSELECT : ISD::SELECT;
2916 for (unsigned i = 0; i != NumValues; ++i)
2917 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2918 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2920 SDValue(TrueVal.getNode(),
2921 TrueVal.getResNo() + i),
2922 SDValue(FalseVal.getNode(),
2923 FalseVal.getResNo() + i));
2925 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2926 DAG.getVTList(ValueVTs), Values));
2929 void SelectionDAGBuilder::visitTrunc(const User &I) {
2930 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2931 SDValue N = getValue(I.getOperand(0));
2932 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2933 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2936 void SelectionDAGBuilder::visitZExt(const User &I) {
2937 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2938 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2939 SDValue N = getValue(I.getOperand(0));
2940 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2941 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2944 void SelectionDAGBuilder::visitSExt(const User &I) {
2945 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2946 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2947 SDValue N = getValue(I.getOperand(0));
2948 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2949 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2952 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2953 // FPTrunc is never a no-op cast, no need to check
2954 SDValue N = getValue(I.getOperand(0));
2955 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2956 EVT DestVT = TLI.getValueType(I.getType());
2957 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
2958 DAG.getTargetConstant(0, TLI.getPointerTy())));
2961 void SelectionDAGBuilder::visitFPExt(const User &I) {
2962 // FPExt is never a no-op cast, no need to check
2963 SDValue N = getValue(I.getOperand(0));
2964 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2965 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2968 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2969 // FPToUI is never a no-op cast, no need to check
2970 SDValue N = getValue(I.getOperand(0));
2971 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2972 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2975 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2976 // FPToSI is never a no-op cast, no need to check
2977 SDValue N = getValue(I.getOperand(0));
2978 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2979 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2982 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2983 // UIToFP is never a no-op cast, no need to check
2984 SDValue N = getValue(I.getOperand(0));
2985 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2986 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2989 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2990 // SIToFP is never a no-op cast, no need to check
2991 SDValue N = getValue(I.getOperand(0));
2992 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2993 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2996 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2997 // What to do depends on the size of the integer and the size of the pointer.
2998 // We can either truncate, zero extend, or no-op, accordingly.
2999 SDValue N = getValue(I.getOperand(0));
3000 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3001 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3004 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3005 // What to do depends on the size of the integer and the size of the pointer.
3006 // We can either truncate, zero extend, or no-op, accordingly.
3007 SDValue N = getValue(I.getOperand(0));
3008 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3009 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3012 void SelectionDAGBuilder::visitBitCast(const User &I) {
3013 SDValue N = getValue(I.getOperand(0));
3014 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3016 // BitCast assures us that source and destination are the same size so this is
3017 // either a BITCAST or a no-op.
3018 if (DestVT != N.getValueType())
3019 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3020 DestVT, N)); // convert types.
3021 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3022 // might fold any kind of constant expression to an integer constant and that
3023 // is not what we are looking for. Only regcognize a bitcast of a genuine
3024 // constant integer as an opaque constant.
3025 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3026 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3029 setValue(&I, N); // noop cast.
3032 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3033 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3034 const Value *SV = I.getOperand(0);
3035 SDValue N = getValue(SV);
3036 EVT DestVT = TLI.getValueType(I.getType());
3038 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3039 unsigned DestAS = I.getType()->getPointerAddressSpace();
3041 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3042 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3047 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3048 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3049 SDValue InVec = getValue(I.getOperand(0));
3050 SDValue InVal = getValue(I.getOperand(1));
3051 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3052 getCurSDLoc(), TLI.getVectorIdxTy());
3053 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3054 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3057 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3058 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3059 SDValue InVec = getValue(I.getOperand(0));
3060 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3061 getCurSDLoc(), TLI.getVectorIdxTy());
3062 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3063 TLI.getValueType(I.getType()), InVec, InIdx));
3066 // Utility for visitShuffleVector - Return true if every element in Mask,
3067 // beginning from position Pos and ending in Pos+Size, falls within the
3068 // specified sequential range [L, L+Pos). or is undef.
3069 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3070 unsigned Pos, unsigned Size, int Low) {
3071 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3072 if (Mask[i] >= 0 && Mask[i] != Low)
3077 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3078 SDValue Src1 = getValue(I.getOperand(0));
3079 SDValue Src2 = getValue(I.getOperand(1));
3081 SmallVector<int, 8> Mask;
3082 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3083 unsigned MaskNumElts = Mask.size();
3085 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3086 EVT VT = TLI.getValueType(I.getType());
3087 EVT SrcVT = Src1.getValueType();
3088 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3090 if (SrcNumElts == MaskNumElts) {
3091 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3096 // Normalize the shuffle vector since mask and vector length don't match.
3097 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3098 // Mask is longer than the source vectors and is a multiple of the source
3099 // vectors. We can use concatenate vector to make the mask and vectors
3101 if (SrcNumElts*2 == MaskNumElts) {
3102 // First check for Src1 in low and Src2 in high
3103 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3104 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3105 // The shuffle is concatenating two vectors together.
3106 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3110 // Then check for Src2 in low and Src1 in high
3111 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3112 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3113 // The shuffle is concatenating two vectors together.
3114 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3120 // Pad both vectors with undefs to make them the same length as the mask.
3121 unsigned NumConcat = MaskNumElts / SrcNumElts;
3122 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3123 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3124 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3126 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3127 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3131 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3132 getCurSDLoc(), VT, MOps1);
3133 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3134 getCurSDLoc(), VT, MOps2);
3136 // Readjust mask for new input vector length.
3137 SmallVector<int, 8> MappedOps;
3138 for (unsigned i = 0; i != MaskNumElts; ++i) {
3140 if (Idx >= (int)SrcNumElts)
3141 Idx -= SrcNumElts - MaskNumElts;
3142 MappedOps.push_back(Idx);
3145 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3150 if (SrcNumElts > MaskNumElts) {
3151 // Analyze the access pattern of the vector to see if we can extract
3152 // two subvectors and do the shuffle. The analysis is done by calculating
3153 // the range of elements the mask access on both vectors.
3154 int MinRange[2] = { static_cast<int>(SrcNumElts),
3155 static_cast<int>(SrcNumElts)};
3156 int MaxRange[2] = {-1, -1};
3158 for (unsigned i = 0; i != MaskNumElts; ++i) {
3164 if (Idx >= (int)SrcNumElts) {
3168 if (Idx > MaxRange[Input])
3169 MaxRange[Input] = Idx;
3170 if (Idx < MinRange[Input])
3171 MinRange[Input] = Idx;
3174 // Check if the access is smaller than the vector size and can we find
3175 // a reasonable extract index.
3176 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3178 int StartIdx[2]; // StartIdx to extract from
3179 for (unsigned Input = 0; Input < 2; ++Input) {
3180 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3181 RangeUse[Input] = 0; // Unused
3182 StartIdx[Input] = 0;
3186 // Find a good start index that is a multiple of the mask length. Then
3187 // see if the rest of the elements are in range.
3188 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3189 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3190 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3191 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3194 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3195 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3198 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3199 // Extract appropriate subvector and generate a vector shuffle
3200 for (unsigned Input = 0; Input < 2; ++Input) {
3201 SDValue &Src = Input == 0 ? Src1 : Src2;
3202 if (RangeUse[Input] == 0)
3203 Src = DAG.getUNDEF(VT);
3206 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3207 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3210 // Calculate new mask.
3211 SmallVector<int, 8> MappedOps;
3212 for (unsigned i = 0; i != MaskNumElts; ++i) {
3215 if (Idx < (int)SrcNumElts)
3218 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3220 MappedOps.push_back(Idx);
3223 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3229 // We can't use either concat vectors or extract subvectors so fall back to
3230 // replacing the shuffle with extract and build vector.
3231 // to insert and build vector.
3232 EVT EltVT = VT.getVectorElementType();
3233 EVT IdxVT = TLI.getVectorIdxTy();
3234 SmallVector<SDValue,8> Ops;
3235 for (unsigned i = 0; i != MaskNumElts; ++i) {
3240 Res = DAG.getUNDEF(EltVT);
3242 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3243 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3245 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3246 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3252 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3255 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3256 const Value *Op0 = I.getOperand(0);
3257 const Value *Op1 = I.getOperand(1);
3258 Type *AggTy = I.getType();
3259 Type *ValTy = Op1->getType();
3260 bool IntoUndef = isa<UndefValue>(Op0);
3261 bool FromUndef = isa<UndefValue>(Op1);
3263 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3265 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3266 SmallVector<EVT, 4> AggValueVTs;
3267 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3268 SmallVector<EVT, 4> ValValueVTs;
3269 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3271 unsigned NumAggValues = AggValueVTs.size();
3272 unsigned NumValValues = ValValueVTs.size();
3273 SmallVector<SDValue, 4> Values(NumAggValues);
3275 // Ignore an insertvalue that produces an empty object
3276 if (!NumAggValues) {
3277 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3281 SDValue Agg = getValue(Op0);
3283 // Copy the beginning value(s) from the original aggregate.
3284 for (; i != LinearIndex; ++i)
3285 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3286 SDValue(Agg.getNode(), Agg.getResNo() + i);
3287 // Copy values from the inserted value(s).
3289 SDValue Val = getValue(Op1);
3290 for (; i != LinearIndex + NumValValues; ++i)
3291 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3292 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3294 // Copy remaining value(s) from the original aggregate.
3295 for (; i != NumAggValues; ++i)
3296 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3297 SDValue(Agg.getNode(), Agg.getResNo() + i);
3299 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3300 DAG.getVTList(AggValueVTs), Values));
3303 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3304 const Value *Op0 = I.getOperand(0);
3305 Type *AggTy = Op0->getType();
3306 Type *ValTy = I.getType();
3307 bool OutOfUndef = isa<UndefValue>(Op0);
3309 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3311 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3312 SmallVector<EVT, 4> ValValueVTs;
3313 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3315 unsigned NumValValues = ValValueVTs.size();
3317 // Ignore a extractvalue that produces an empty object
3318 if (!NumValValues) {
3319 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3323 SmallVector<SDValue, 4> Values(NumValValues);
3325 SDValue Agg = getValue(Op0);
3326 // Copy out the selected value(s).
3327 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3328 Values[i - LinearIndex] =
3330 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3331 SDValue(Agg.getNode(), Agg.getResNo() + i);
3333 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3334 DAG.getVTList(ValValueVTs), Values));
3337 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3338 Value *Op0 = I.getOperand(0);
3339 // Note that the pointer operand may be a vector of pointers. Take the scalar
3340 // element which holds a pointer.
3341 Type *Ty = Op0->getType()->getScalarType();
3342 unsigned AS = Ty->getPointerAddressSpace();
3343 SDValue N = getValue(Op0);
3345 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3347 const Value *Idx = *OI;
3348 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3349 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3352 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3353 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3354 DAG.getConstant(Offset, N.getValueType()));
3357 Ty = StTy->getElementType(Field);
3359 Ty = cast<SequentialType>(Ty)->getElementType();
3361 // If this is a constant subscript, handle it quickly.
3362 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3363 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3364 if (CI->isZero()) continue;
3366 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3368 EVT PTy = TLI.getPointerTy(AS);
3369 unsigned PtrBits = PTy.getSizeInBits();
3371 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3372 DAG.getConstant(Offs, MVT::i64));
3374 OffsVal = DAG.getConstant(Offs, PTy);
3376 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3381 // N = N + Idx * ElementSize;
3383 APInt(TLI.getPointerSizeInBits(AS), DL->getTypeAllocSize(Ty));
3384 SDValue IdxN = getValue(Idx);
3386 // If the index is smaller or larger than intptr_t, truncate or extend
3388 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3390 // If this is a multiply by a power of two, turn it into a shl
3391 // immediately. This is a very common case.
3392 if (ElementSize != 1) {
3393 if (ElementSize.isPowerOf2()) {
3394 unsigned Amt = ElementSize.logBase2();
3395 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3396 N.getValueType(), IdxN,
3397 DAG.getConstant(Amt, IdxN.getValueType()));
3399 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3400 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3401 N.getValueType(), IdxN, Scale);
3405 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3406 N.getValueType(), N, IdxN);
3413 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3414 // If this is a fixed sized alloca in the entry block of the function,
3415 // allocate it statically on the stack.
3416 if (FuncInfo.StaticAllocaMap.count(&I))
3417 return; // getValue will auto-populate this.
3419 Type *Ty = I.getAllocatedType();
3420 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3421 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3423 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3426 SDValue AllocSize = getValue(I.getArraySize());
3428 EVT IntPtr = TLI.getPointerTy();
3429 if (AllocSize.getValueType() != IntPtr)
3430 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3432 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3434 DAG.getConstant(TySize, IntPtr));
3436 // Handle alignment. If the requested alignment is less than or equal to
3437 // the stack alignment, ignore it. If the size is greater than or equal to
3438 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3439 unsigned StackAlign =
3440 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3441 if (Align <= StackAlign)
3444 // Round the size of the allocation up to the stack alignment size
3445 // by add SA-1 to the size.
3446 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3447 AllocSize.getValueType(), AllocSize,
3448 DAG.getIntPtrConstant(StackAlign-1));
3450 // Mask out the low bits for alignment purposes.
3451 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3452 AllocSize.getValueType(), AllocSize,
3453 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3455 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3456 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3457 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3459 DAG.setRoot(DSA.getValue(1));
3461 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3464 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3466 return visitAtomicLoad(I);
3468 const Value *SV = I.getOperand(0);
3469 SDValue Ptr = getValue(SV);
3471 Type *Ty = I.getType();
3473 bool isVolatile = I.isVolatile();
3474 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3475 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3476 unsigned Alignment = I.getAlignment();
3479 I.getAAMetadata(AAInfo);
3480 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3482 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3483 SmallVector<EVT, 4> ValueVTs;
3484 SmallVector<uint64_t, 4> Offsets;
3485 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3486 unsigned NumValues = ValueVTs.size();
3491 bool ConstantMemory = false;
3492 if (isVolatile || NumValues > MaxParallelChains)
3493 // Serialize volatile loads with other side effects.
3495 else if (AA->pointsToConstantMemory(
3496 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3497 // Do not serialize (non-volatile) loads of constant memory with anything.
3498 Root = DAG.getEntryNode();
3499 ConstantMemory = true;
3501 // Do not serialize non-volatile loads against each other.
3502 Root = DAG.getRoot();
3506 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3508 SmallVector<SDValue, 4> Values(NumValues);
3509 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3511 EVT PtrVT = Ptr.getValueType();
3512 unsigned ChainI = 0;
3513 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3514 // Serializing loads here may result in excessive register pressure, and
3515 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3516 // could recover a bit by hoisting nodes upward in the chain by recognizing
3517 // they are side-effect free or do not alias. The optimizer should really
3518 // avoid this case by converting large object/array copies to llvm.memcpy
3519 // (MaxParallelChains should always remain as failsafe).
3520 if (ChainI == MaxParallelChains) {
3521 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3522 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3523 makeArrayRef(Chains.data(), ChainI));
3527 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3529 DAG.getConstant(Offsets[i], PtrVT));
3530 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3531 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3532 isNonTemporal, isInvariant, Alignment, AAInfo,
3536 Chains[ChainI] = L.getValue(1);
3539 if (!ConstantMemory) {
3540 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3541 makeArrayRef(Chains.data(), ChainI));
3545 PendingLoads.push_back(Chain);
3548 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3549 DAG.getVTList(ValueVTs), Values));
3552 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3554 return visitAtomicStore(I);
3556 const Value *SrcV = I.getOperand(0);
3557 const Value *PtrV = I.getOperand(1);
3559 SmallVector<EVT, 4> ValueVTs;
3560 SmallVector<uint64_t, 4> Offsets;
3561 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3562 ValueVTs, &Offsets);
3563 unsigned NumValues = ValueVTs.size();
3567 // Get the lowered operands. Note that we do this after
3568 // checking if NumResults is zero, because with zero results
3569 // the operands won't have values in the map.
3570 SDValue Src = getValue(SrcV);
3571 SDValue Ptr = getValue(PtrV);
3573 SDValue Root = getRoot();
3574 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3576 EVT PtrVT = Ptr.getValueType();
3577 bool isVolatile = I.isVolatile();
3578 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3579 unsigned Alignment = I.getAlignment();
3582 I.getAAMetadata(AAInfo);
3584 unsigned ChainI = 0;
3585 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3586 // See visitLoad comments.
3587 if (ChainI == MaxParallelChains) {
3588 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3589 makeArrayRef(Chains.data(), ChainI));
3593 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3594 DAG.getConstant(Offsets[i], PtrVT));
3595 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3596 SDValue(Src.getNode(), Src.getResNo() + i),
3597 Add, MachinePointerInfo(PtrV, Offsets[i]),
3598 isVolatile, isNonTemporal, Alignment, AAInfo);
3599 Chains[ChainI] = St;
3602 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3603 makeArrayRef(Chains.data(), ChainI));
3604 DAG.setRoot(StoreNode);
3607 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3608 SynchronizationScope Scope,
3609 bool Before, SDLoc dl,
3611 const TargetLowering &TLI) {
3612 // Fence, if necessary
3614 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3616 else if (Order == Acquire || Order == Monotonic || Order == Unordered)
3619 if (Order == AcquireRelease)
3621 else if (Order == Release || Order == Monotonic || Order == Unordered)
3626 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3627 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3628 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops);
3631 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3632 SDLoc dl = getCurSDLoc();
3633 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3634 AtomicOrdering FailureOrder = I.getFailureOrdering();
3635 SynchronizationScope Scope = I.getSynchScope();
3637 SDValue InChain = getRoot();
3639 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3640 if (TLI.getInsertFencesForAtomic())
3642 InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl, DAG, TLI);
3644 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3645 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3646 SDValue L = DAG.getAtomicCmpSwap(
3647 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3648 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3649 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3651 TLI.getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3652 TLI.getInsertFencesForAtomic() ? Monotonic : FailureOrder, Scope);
3654 SDValue OutChain = L.getValue(2);
3656 if (TLI.getInsertFencesForAtomic())
3657 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3661 DAG.setRoot(OutChain);
3664 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3665 SDLoc dl = getCurSDLoc();
3667 switch (I.getOperation()) {
3668 default: llvm_unreachable("Unknown atomicrmw operation");
3669 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3670 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3671 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3672 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3673 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3674 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3675 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3676 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3677 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3678 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3679 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3681 AtomicOrdering Order = I.getOrdering();
3682 SynchronizationScope Scope = I.getSynchScope();
3684 SDValue InChain = getRoot();
3686 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3687 if (TLI.getInsertFencesForAtomic())
3688 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, DAG, TLI);
3690 SDValue L = DAG.getAtomic(
3691 NT, dl, getValue(I.getValOperand()).getSimpleValueType(), InChain,
3692 getValue(I.getPointerOperand()), getValue(I.getValOperand()),
3693 I.getPointerOperand(), 0 /* Alignment */,
3694 TLI.getInsertFencesForAtomic() ? Monotonic : Order, Scope);
3696 SDValue OutChain = L.getValue(1);
3698 if (TLI.getInsertFencesForAtomic())
3700 InsertFenceForAtomic(OutChain, Order, Scope, false, dl, DAG, TLI);
3703 DAG.setRoot(OutChain);
3706 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3707 SDLoc dl = getCurSDLoc();
3708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3711 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3712 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3713 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3716 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3717 SDLoc dl = getCurSDLoc();
3718 AtomicOrdering Order = I.getOrdering();
3719 SynchronizationScope Scope = I.getSynchScope();
3721 SDValue InChain = getRoot();
3723 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3724 EVT VT = TLI.getValueType(I.getType());
3726 if (I.getAlignment() < VT.getSizeInBits() / 8)
3727 report_fatal_error("Cannot generate unaligned atomic load");
3729 MachineMemOperand *MMO =
3730 DAG.getMachineFunction().
3731 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3732 MachineMemOperand::MOVolatile |
3733 MachineMemOperand::MOLoad,
3735 I.getAlignment() ? I.getAlignment() :
3736 DAG.getEVTAlignment(VT));
3738 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3739 SDValue L = DAG.getAtomic(
3740 ISD::ATOMIC_LOAD, dl, VT, VT, InChain, getValue(I.getPointerOperand()),
3741 MMO, TLI.getInsertFencesForAtomic() ? Monotonic : Order, Scope);
3743 SDValue OutChain = L.getValue(1);
3745 if (TLI.getInsertFencesForAtomic())
3746 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3750 DAG.setRoot(OutChain);
3753 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3754 SDLoc dl = getCurSDLoc();
3756 AtomicOrdering Order = I.getOrdering();
3757 SynchronizationScope Scope = I.getSynchScope();
3759 SDValue InChain = getRoot();
3761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3762 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3764 if (I.getAlignment() < VT.getSizeInBits() / 8)
3765 report_fatal_error("Cannot generate unaligned atomic store");
3767 if (TLI.getInsertFencesForAtomic())
3768 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, DAG, TLI);
3770 SDValue OutChain = DAG.getAtomic(
3771 ISD::ATOMIC_STORE, dl, VT, InChain, getValue(I.getPointerOperand()),
3772 getValue(I.getValueOperand()), I.getPointerOperand(), I.getAlignment(),
3773 TLI.getInsertFencesForAtomic() ? Monotonic : Order, Scope);
3775 if (TLI.getInsertFencesForAtomic())
3777 InsertFenceForAtomic(OutChain, Order, Scope, false, dl, DAG, TLI);
3779 DAG.setRoot(OutChain);
3782 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3784 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3785 unsigned Intrinsic) {
3786 bool HasChain = !I.doesNotAccessMemory();
3787 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3789 // Build the operand list.
3790 SmallVector<SDValue, 8> Ops;
3791 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3793 // We don't need to serialize loads against other loads.
3794 Ops.push_back(DAG.getRoot());
3796 Ops.push_back(getRoot());
3800 // Info is set by getTgtMemInstrinsic
3801 TargetLowering::IntrinsicInfo Info;
3802 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3803 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3805 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3806 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3807 Info.opc == ISD::INTRINSIC_W_CHAIN)
3808 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3810 // Add all operands of the call to the operand list.
3811 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3812 SDValue Op = getValue(I.getArgOperand(i));
3816 SmallVector<EVT, 4> ValueVTs;
3817 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3820 ValueVTs.push_back(MVT::Other);
3822 SDVTList VTs = DAG.getVTList(ValueVTs);
3826 if (IsTgtIntrinsic) {
3827 // This is target intrinsic that touches memory
3828 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3829 VTs, Ops, Info.memVT,
3830 MachinePointerInfo(Info.ptrVal, Info.offset),
3831 Info.align, Info.vol,
3832 Info.readMem, Info.writeMem, Info.size);
3833 } else if (!HasChain) {
3834 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3835 } else if (!I.getType()->isVoidTy()) {
3836 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3838 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3842 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3844 PendingLoads.push_back(Chain);
3849 if (!I.getType()->isVoidTy()) {
3850 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3851 EVT VT = TLI.getValueType(PTy);
3852 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3855 setValue(&I, Result);
3859 /// GetSignificand - Get the significand and build it into a floating-point
3860 /// number with exponent of 1:
3862 /// Op = (Op & 0x007fffff) | 0x3f800000;
3864 /// where Op is the hexadecimal representation of floating point value.
3866 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3867 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3868 DAG.getConstant(0x007fffff, MVT::i32));
3869 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3870 DAG.getConstant(0x3f800000, MVT::i32));
3871 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3874 /// GetExponent - Get the exponent:
3876 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3878 /// where Op is the hexadecimal representation of floating point value.
3880 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3882 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3883 DAG.getConstant(0x7f800000, MVT::i32));
3884 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3885 DAG.getConstant(23, TLI.getPointerTy()));
3886 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3887 DAG.getConstant(127, MVT::i32));
3888 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3891 /// getF32Constant - Get 32-bit floating point constant.
3893 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3894 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3898 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3899 /// limited-precision mode.
3900 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3901 const TargetLowering &TLI) {
3902 if (Op.getValueType() == MVT::f32 &&
3903 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3905 // Put the exponent in the right bit position for later addition to the
3908 // #define LOG2OFe 1.4426950f
3909 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3910 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3911 getF32Constant(DAG, 0x3fb8aa3b));
3912 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3914 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3915 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3916 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3918 // IntegerPartOfX <<= 23;
3919 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3920 DAG.getConstant(23, TLI.getPointerTy()));
3922 SDValue TwoToFracPartOfX;
3923 if (LimitFloatPrecision <= 6) {
3924 // For floating-point precision of 6:
3926 // TwoToFractionalPartOfX =
3928 // (0.735607626f + 0.252464424f * x) * x;
3930 // error 0.0144103317, which is 6 bits
3931 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3932 getF32Constant(DAG, 0x3e814304));
3933 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3934 getF32Constant(DAG, 0x3f3c50c8));
3935 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3936 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3937 getF32Constant(DAG, 0x3f7f5e7e));
3938 } else if (LimitFloatPrecision <= 12) {
3939 // For floating-point precision of 12:
3941 // TwoToFractionalPartOfX =
3944 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3946 // 0.000107046256 error, which is 13 to 14 bits
3947 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3948 getF32Constant(DAG, 0x3da235e3));
3949 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3950 getF32Constant(DAG, 0x3e65b8f3));
3951 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3952 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3953 getF32Constant(DAG, 0x3f324b07));
3954 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3955 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3956 getF32Constant(DAG, 0x3f7ff8fd));
3957 } else { // LimitFloatPrecision <= 18
3958 // For floating-point precision of 18:
3960 // TwoToFractionalPartOfX =
3964 // (0.554906021e-1f +
3965 // (0.961591928e-2f +
3966 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3968 // error 2.47208000*10^(-7), which is better than 18 bits
3969 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3970 getF32Constant(DAG, 0x3924b03e));
3971 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3972 getF32Constant(DAG, 0x3ab24b87));
3973 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3974 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3975 getF32Constant(DAG, 0x3c1d8c17));
3976 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3977 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3978 getF32Constant(DAG, 0x3d634a1d));
3979 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3980 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3981 getF32Constant(DAG, 0x3e75fe14));
3982 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3983 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3984 getF32Constant(DAG, 0x3f317234));
3985 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3986 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3987 getF32Constant(DAG, 0x3f800000));
3990 // Add the exponent into the result in integer domain.
3991 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3992 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3993 DAG.getNode(ISD::ADD, dl, MVT::i32,
3994 t13, IntegerPartOfX));
3997 // No special expansion.
3998 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4001 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4002 /// limited-precision mode.
4003 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4004 const TargetLowering &TLI) {
4005 if (Op.getValueType() == MVT::f32 &&
4006 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4007 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4009 // Scale the exponent by log(2) [0.69314718f].
4010 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4011 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4012 getF32Constant(DAG, 0x3f317218));
4014 // Get the significand and build it into a floating-point number with
4016 SDValue X = GetSignificand(DAG, Op1, dl);
4018 SDValue LogOfMantissa;
4019 if (LimitFloatPrecision <= 6) {
4020 // For floating-point precision of 6:
4024 // (1.4034025f - 0.23903021f * x) * x;
4026 // error 0.0034276066, which is better than 8 bits
4027 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4028 getF32Constant(DAG, 0xbe74c456));
4029 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4030 getF32Constant(DAG, 0x3fb3a2b1));
4031 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4032 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4033 getF32Constant(DAG, 0x3f949a29));
4034 } else if (LimitFloatPrecision <= 12) {
4035 // For floating-point precision of 12:
4041 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4043 // error 0.000061011436, which is 14 bits
4044 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4045 getF32Constant(DAG, 0xbd67b6d6));
4046 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4047 getF32Constant(DAG, 0x3ee4f4b8));
4048 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4049 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4050 getF32Constant(DAG, 0x3fbc278b));
4051 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4052 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4053 getF32Constant(DAG, 0x40348e95));
4054 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4055 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4056 getF32Constant(DAG, 0x3fdef31a));
4057 } else { // LimitFloatPrecision <= 18
4058 // For floating-point precision of 18:
4066 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4068 // error 0.0000023660568, which is better than 18 bits
4069 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4070 getF32Constant(DAG, 0xbc91e5ac));
4071 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4072 getF32Constant(DAG, 0x3e4350aa));
4073 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4074 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4075 getF32Constant(DAG, 0x3f60d3e3));
4076 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4077 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4078 getF32Constant(DAG, 0x4011cdf0));
4079 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4080 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4081 getF32Constant(DAG, 0x406cfd1c));
4082 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4083 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4084 getF32Constant(DAG, 0x408797cb));
4085 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4086 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4087 getF32Constant(DAG, 0x4006dcab));
4090 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4093 // No special expansion.
4094 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4097 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4098 /// limited-precision mode.
4099 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4100 const TargetLowering &TLI) {
4101 if (Op.getValueType() == MVT::f32 &&
4102 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4103 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4105 // Get the exponent.
4106 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4108 // Get the significand and build it into a floating-point number with
4110 SDValue X = GetSignificand(DAG, Op1, dl);
4112 // Different possible minimax approximations of significand in
4113 // floating-point for various degrees of accuracy over [1,2].
4114 SDValue Log2ofMantissa;
4115 if (LimitFloatPrecision <= 6) {
4116 // For floating-point precision of 6:
4118 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4120 // error 0.0049451742, which is more than 7 bits
4121 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4122 getF32Constant(DAG, 0xbeb08fe0));
4123 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4124 getF32Constant(DAG, 0x40019463));
4125 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4126 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4127 getF32Constant(DAG, 0x3fd6633d));
4128 } else if (LimitFloatPrecision <= 12) {
4129 // For floating-point precision of 12:
4135 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4137 // error 0.0000876136000, which is better than 13 bits
4138 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4139 getF32Constant(DAG, 0xbda7262e));
4140 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4141 getF32Constant(DAG, 0x3f25280b));
4142 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4143 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4144 getF32Constant(DAG, 0x4007b923));
4145 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4146 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4147 getF32Constant(DAG, 0x40823e2f));
4148 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4149 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4150 getF32Constant(DAG, 0x4020d29c));
4151 } else { // LimitFloatPrecision <= 18
4152 // For floating-point precision of 18:
4161 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4163 // error 0.0000018516, which is better than 18 bits
4164 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4165 getF32Constant(DAG, 0xbcd2769e));
4166 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4167 getF32Constant(DAG, 0x3e8ce0b9));
4168 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4169 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4170 getF32Constant(DAG, 0x3fa22ae7));
4171 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4172 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4173 getF32Constant(DAG, 0x40525723));
4174 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4175 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4176 getF32Constant(DAG, 0x40aaf200));
4177 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4178 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4179 getF32Constant(DAG, 0x40c39dad));
4180 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4181 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4182 getF32Constant(DAG, 0x4042902c));
4185 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4188 // No special expansion.
4189 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4192 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4193 /// limited-precision mode.
4194 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4195 const TargetLowering &TLI) {
4196 if (Op.getValueType() == MVT::f32 &&
4197 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4198 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4200 // Scale the exponent by log10(2) [0.30102999f].
4201 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4202 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4203 getF32Constant(DAG, 0x3e9a209a));
4205 // Get the significand and build it into a floating-point number with
4207 SDValue X = GetSignificand(DAG, Op1, dl);
4209 SDValue Log10ofMantissa;
4210 if (LimitFloatPrecision <= 6) {
4211 // For floating-point precision of 6:
4213 // Log10ofMantissa =
4215 // (0.60948995f - 0.10380950f * x) * x;
4217 // error 0.0014886165, which is 6 bits
4218 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4219 getF32Constant(DAG, 0xbdd49a13));
4220 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4221 getF32Constant(DAG, 0x3f1c0789));
4222 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4223 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4224 getF32Constant(DAG, 0x3f011300));
4225 } else if (LimitFloatPrecision <= 12) {
4226 // For floating-point precision of 12:
4228 // Log10ofMantissa =
4231 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4233 // error 0.00019228036, which is better than 12 bits
4234 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4235 getF32Constant(DAG, 0x3d431f31));
4236 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4237 getF32Constant(DAG, 0x3ea21fb2));
4238 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4239 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4240 getF32Constant(DAG, 0x3f6ae232));
4241 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4242 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4243 getF32Constant(DAG, 0x3f25f7c3));
4244 } else { // LimitFloatPrecision <= 18
4245 // For floating-point precision of 18:
4247 // Log10ofMantissa =
4252 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4254 // error 0.0000037995730, which is better than 18 bits
4255 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4256 getF32Constant(DAG, 0x3c5d51ce));
4257 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4258 getF32Constant(DAG, 0x3e00685a));
4259 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4260 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4261 getF32Constant(DAG, 0x3efb6798));
4262 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4263 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4264 getF32Constant(DAG, 0x3f88d192));
4265 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4266 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4267 getF32Constant(DAG, 0x3fc4316c));
4268 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4269 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4270 getF32Constant(DAG, 0x3f57ce70));
4273 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4276 // No special expansion.
4277 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4280 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4281 /// limited-precision mode.
4282 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4283 const TargetLowering &TLI) {
4284 if (Op.getValueType() == MVT::f32 &&
4285 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4286 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4288 // FractionalPartOfX = x - (float)IntegerPartOfX;
4289 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4290 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4292 // IntegerPartOfX <<= 23;
4293 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4294 DAG.getConstant(23, TLI.getPointerTy()));
4296 SDValue TwoToFractionalPartOfX;
4297 if (LimitFloatPrecision <= 6) {
4298 // For floating-point precision of 6:
4300 // TwoToFractionalPartOfX =
4302 // (0.735607626f + 0.252464424f * x) * x;
4304 // error 0.0144103317, which is 6 bits
4305 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4306 getF32Constant(DAG, 0x3e814304));
4307 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4308 getF32Constant(DAG, 0x3f3c50c8));
4309 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4310 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4311 getF32Constant(DAG, 0x3f7f5e7e));
4312 } else if (LimitFloatPrecision <= 12) {
4313 // For floating-point precision of 12:
4315 // TwoToFractionalPartOfX =
4318 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4320 // error 0.000107046256, which is 13 to 14 bits
4321 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4322 getF32Constant(DAG, 0x3da235e3));
4323 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4324 getF32Constant(DAG, 0x3e65b8f3));
4325 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4326 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4327 getF32Constant(DAG, 0x3f324b07));
4328 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4329 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4330 getF32Constant(DAG, 0x3f7ff8fd));
4331 } else { // LimitFloatPrecision <= 18
4332 // For floating-point precision of 18:
4334 // TwoToFractionalPartOfX =
4338 // (0.554906021e-1f +
4339 // (0.961591928e-2f +
4340 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4341 // error 2.47208000*10^(-7), which is better than 18 bits
4342 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4343 getF32Constant(DAG, 0x3924b03e));
4344 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4345 getF32Constant(DAG, 0x3ab24b87));
4346 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4347 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4348 getF32Constant(DAG, 0x3c1d8c17));
4349 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4350 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4351 getF32Constant(DAG, 0x3d634a1d));
4352 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4353 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4354 getF32Constant(DAG, 0x3e75fe14));
4355 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4356 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4357 getF32Constant(DAG, 0x3f317234));
4358 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4359 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4360 getF32Constant(DAG, 0x3f800000));
4363 // Add the exponent into the result in integer domain.
4364 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4365 TwoToFractionalPartOfX);
4366 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4367 DAG.getNode(ISD::ADD, dl, MVT::i32,
4368 t13, IntegerPartOfX));
4371 // No special expansion.
4372 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4375 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4376 /// limited-precision mode with x == 10.0f.
4377 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4378 SelectionDAG &DAG, const TargetLowering &TLI) {
4379 bool IsExp10 = false;
4380 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4381 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4382 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4384 IsExp10 = LHSC->isExactlyValue(Ten);
4389 // Put the exponent in the right bit position for later addition to the
4392 // #define LOG2OF10 3.3219281f
4393 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4394 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4395 getF32Constant(DAG, 0x40549a78));
4396 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4398 // FractionalPartOfX = x - (float)IntegerPartOfX;
4399 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4400 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4402 // IntegerPartOfX <<= 23;
4403 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4404 DAG.getConstant(23, TLI.getPointerTy()));
4406 SDValue TwoToFractionalPartOfX;
4407 if (LimitFloatPrecision <= 6) {
4408 // For floating-point precision of 6:
4410 // twoToFractionalPartOfX =
4412 // (0.735607626f + 0.252464424f * x) * x;
4414 // error 0.0144103317, which is 6 bits
4415 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4416 getF32Constant(DAG, 0x3e814304));
4417 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4418 getF32Constant(DAG, 0x3f3c50c8));
4419 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4420 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4421 getF32Constant(DAG, 0x3f7f5e7e));
4422 } else if (LimitFloatPrecision <= 12) {
4423 // For floating-point precision of 12:
4425 // TwoToFractionalPartOfX =
4428 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4430 // error 0.000107046256, which is 13 to 14 bits
4431 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4432 getF32Constant(DAG, 0x3da235e3));
4433 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4434 getF32Constant(DAG, 0x3e65b8f3));
4435 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4436 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4437 getF32Constant(DAG, 0x3f324b07));
4438 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4439 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4440 getF32Constant(DAG, 0x3f7ff8fd));
4441 } else { // LimitFloatPrecision <= 18
4442 // For floating-point precision of 18:
4444 // TwoToFractionalPartOfX =
4448 // (0.554906021e-1f +
4449 // (0.961591928e-2f +
4450 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4451 // error 2.47208000*10^(-7), which is better than 18 bits
4452 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4453 getF32Constant(DAG, 0x3924b03e));
4454 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4455 getF32Constant(DAG, 0x3ab24b87));
4456 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4457 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4458 getF32Constant(DAG, 0x3c1d8c17));
4459 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4460 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4461 getF32Constant(DAG, 0x3d634a1d));
4462 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4463 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4464 getF32Constant(DAG, 0x3e75fe14));
4465 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4466 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4467 getF32Constant(DAG, 0x3f317234));
4468 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4469 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4470 getF32Constant(DAG, 0x3f800000));
4473 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4474 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4475 DAG.getNode(ISD::ADD, dl, MVT::i32,
4476 t13, IntegerPartOfX));
4479 // No special expansion.
4480 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4484 /// ExpandPowI - Expand a llvm.powi intrinsic.
4485 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4486 SelectionDAG &DAG) {
4487 // If RHS is a constant, we can expand this out to a multiplication tree,
4488 // otherwise we end up lowering to a call to __powidf2 (for example). When
4489 // optimizing for size, we only want to do this if the expansion would produce
4490 // a small number of multiplies, otherwise we do the full expansion.
4491 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4492 // Get the exponent as a positive value.
4493 unsigned Val = RHSC->getSExtValue();
4494 if ((int)Val < 0) Val = -Val;
4496 // powi(x, 0) -> 1.0
4498 return DAG.getConstantFP(1.0, LHS.getValueType());
4500 const Function *F = DAG.getMachineFunction().getFunction();
4501 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4502 Attribute::OptimizeForSize) ||
4503 // If optimizing for size, don't insert too many multiplies. This
4504 // inserts up to 5 multiplies.
4505 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4506 // We use the simple binary decomposition method to generate the multiply
4507 // sequence. There are more optimal ways to do this (for example,
4508 // powi(x,15) generates one more multiply than it should), but this has
4509 // the benefit of being both really simple and much better than a libcall.
4510 SDValue Res; // Logically starts equal to 1.0
4511 SDValue CurSquare = LHS;
4515 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4517 Res = CurSquare; // 1.0*CurSquare.
4520 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4521 CurSquare, CurSquare);
4525 // If the original was negative, invert the result, producing 1/(x*x*x).
4526 if (RHSC->getSExtValue() < 0)
4527 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4528 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4533 // Otherwise, expand to a libcall.
4534 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4537 // getTruncatedArgReg - Find underlying register used for an truncated
4539 static unsigned getTruncatedArgReg(const SDValue &N) {
4540 if (N.getOpcode() != ISD::TRUNCATE)
4543 const SDValue &Ext = N.getOperand(0);
4544 if (Ext.getOpcode() == ISD::AssertZext ||
4545 Ext.getOpcode() == ISD::AssertSext) {
4546 const SDValue &CFR = Ext.getOperand(0);
4547 if (CFR.getOpcode() == ISD::CopyFromReg)
4548 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4549 if (CFR.getOpcode() == ISD::TRUNCATE)
4550 return getTruncatedArgReg(CFR);
4555 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4556 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4557 /// At the end of instruction selection, they will be inserted to the entry BB.
4558 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V,
4560 MDNode *Expr, int64_t Offset,
4563 const Argument *Arg = dyn_cast<Argument>(V);
4567 MachineFunction &MF = DAG.getMachineFunction();
4568 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4570 // Ignore inlined function arguments here.
4571 DIVariable DV(Variable);
4572 if (DV.isInlinedFnArgument(MF.getFunction()))
4575 Optional<MachineOperand> Op;
4576 // Some arguments' frame index is recorded during argument lowering.
4577 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4578 Op = MachineOperand::CreateFI(FI);
4580 if (!Op && N.getNode()) {
4582 if (N.getOpcode() == ISD::CopyFromReg)
4583 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4585 Reg = getTruncatedArgReg(N);
4586 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4587 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4588 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4593 Op = MachineOperand::CreateReg(Reg, false);
4597 // Check if ValueMap has reg number.
4598 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4599 if (VMI != FuncInfo.ValueMap.end())
4600 Op = MachineOperand::CreateReg(VMI->second, false);
4603 if (!Op && N.getNode())
4604 // Check if frame index is available.
4605 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4606 if (FrameIndexSDNode *FINode =
4607 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4608 Op = MachineOperand::CreateFI(FINode->getIndex());
4614 FuncInfo.ArgDbgValues.push_back(
4615 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE),
4616 IsIndirect, Op->getReg(), Offset, Variable, Expr));
4618 FuncInfo.ArgDbgValues.push_back(
4619 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4622 .addMetadata(Variable)
4623 .addMetadata(Expr));
4628 // VisualStudio defines setjmp as _setjmp
4629 #if defined(_MSC_VER) && defined(setjmp) && \
4630 !defined(setjmp_undefined_for_msvc)
4631 # pragma push_macro("setjmp")
4633 # define setjmp_undefined_for_msvc
4636 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4637 /// we want to emit this as a call to a named external function, return the name
4638 /// otherwise lower it and return null.
4640 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4642 SDLoc sdl = getCurSDLoc();
4643 DebugLoc dl = getCurDebugLoc();
4646 switch (Intrinsic) {
4648 // By default, turn this into a target intrinsic node.
4649 visitTargetIntrinsic(I, Intrinsic);
4651 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4652 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4653 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4654 case Intrinsic::returnaddress:
4655 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4656 getValue(I.getArgOperand(0))));
4658 case Intrinsic::frameaddress:
4659 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4660 getValue(I.getArgOperand(0))));
4662 case Intrinsic::read_register: {
4663 Value *Reg = I.getArgOperand(0);
4664 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4665 EVT VT = TLI.getValueType(I.getType());
4666 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4669 case Intrinsic::write_register: {
4670 Value *Reg = I.getArgOperand(0);
4671 Value *RegValue = I.getArgOperand(1);
4672 SDValue Chain = getValue(RegValue).getOperand(0);
4673 SDValue RegName = DAG.getMDNode(cast<MDNode>(Reg));
4674 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4675 RegName, getValue(RegValue)));
4678 case Intrinsic::setjmp:
4679 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4680 case Intrinsic::longjmp:
4681 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4682 case Intrinsic::memcpy: {
4683 // Assert for address < 256 since we support only user defined address
4685 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4687 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4689 "Unknown address space");
4690 SDValue Op1 = getValue(I.getArgOperand(0));
4691 SDValue Op2 = getValue(I.getArgOperand(1));
4692 SDValue Op3 = getValue(I.getArgOperand(2));
4693 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4695 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4696 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4697 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4698 MachinePointerInfo(I.getArgOperand(0)),
4699 MachinePointerInfo(I.getArgOperand(1))));
4702 case Intrinsic::memset: {
4703 // Assert for address < 256 since we support only user defined address
4705 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4707 "Unknown address space");
4708 SDValue Op1 = getValue(I.getArgOperand(0));
4709 SDValue Op2 = getValue(I.getArgOperand(1));
4710 SDValue Op3 = getValue(I.getArgOperand(2));
4711 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4713 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4714 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4715 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4716 MachinePointerInfo(I.getArgOperand(0))));
4719 case Intrinsic::memmove: {
4720 // Assert for address < 256 since we support only user defined address
4722 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4724 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4726 "Unknown address space");
4727 SDValue Op1 = getValue(I.getArgOperand(0));
4728 SDValue Op2 = getValue(I.getArgOperand(1));
4729 SDValue Op3 = getValue(I.getArgOperand(2));
4730 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4732 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4733 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4734 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4735 MachinePointerInfo(I.getArgOperand(0)),
4736 MachinePointerInfo(I.getArgOperand(1))));
4739 case Intrinsic::dbg_declare: {
4740 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4741 MDNode *Variable = DI.getVariable();
4742 MDNode *Expression = DI.getExpression();
4743 const Value *Address = DI.getAddress();
4744 DIVariable DIVar(Variable);
4745 assert((!DIVar || DIVar.isVariable()) &&
4746 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4747 if (!Address || !DIVar) {
4748 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4752 // Check if address has undef value.
4753 if (isa<UndefValue>(Address) ||
4754 (Address->use_empty() && !isa<Argument>(Address))) {
4755 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4759 SDValue &N = NodeMap[Address];
4760 if (!N.getNode() && isa<Argument>(Address))
4761 // Check unused arguments map.
4762 N = UnusedArgNodeMap[Address];
4765 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4766 Address = BCI->getOperand(0);
4767 // Parameters are handled specially.
4769 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4770 isa<Argument>(Address));
4772 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4774 if (isParameter && !AI) {
4775 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4777 // Byval parameter. We have a frame index at this point.
4778 SDV = DAG.getFrameIndexDbgValue(
4779 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4781 // Address is an argument, so try to emit its dbg value using
4782 // virtual register info from the FuncInfo.ValueMap.
4783 EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false, N);
4787 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4788 true, 0, dl, SDNodeOrder);
4790 // Can't do anything with other non-AI cases yet.
4791 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4792 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4793 DEBUG(Address->dump());
4796 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4798 // If Address is an argument then try to emit its dbg value using
4799 // virtual register info from the FuncInfo.ValueMap.
4800 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, 0, false,
4802 // If variable is pinned by a alloca in dominating bb then
4803 // use StaticAllocaMap.
4804 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4805 if (AI->getParent() != DI.getParent()) {
4806 DenseMap<const AllocaInst*, int>::iterator SI =
4807 FuncInfo.StaticAllocaMap.find(AI);
4808 if (SI != FuncInfo.StaticAllocaMap.end()) {
4809 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4810 0, dl, SDNodeOrder);
4811 DAG.AddDbgValue(SDV, nullptr, false);
4816 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4821 case Intrinsic::dbg_value: {
4822 const DbgValueInst &DI = cast<DbgValueInst>(I);
4823 DIVariable DIVar(DI.getVariable());
4824 assert((!DIVar || DIVar.isVariable()) &&
4825 "Variable in DbgValueInst should be either null or a DIVariable.");
4829 MDNode *Variable = DI.getVariable();
4830 MDNode *Expression = DI.getExpression();
4831 uint64_t Offset = DI.getOffset();
4832 const Value *V = DI.getValue();
4837 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4838 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4840 DAG.AddDbgValue(SDV, nullptr, false);
4842 // Do not use getValue() in here; we don't want to generate code at
4843 // this point if it hasn't been done yet.
4844 SDValue N = NodeMap[V];
4845 if (!N.getNode() && isa<Argument>(V))
4846 // Check unused arguments map.
4847 N = UnusedArgNodeMap[V];
4849 // A dbg.value for an alloca is always indirect.
4850 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4851 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, Offset,
4853 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4854 IsIndirect, Offset, dl, SDNodeOrder);
4855 DAG.AddDbgValue(SDV, N.getNode(), false);
4857 } else if (!V->use_empty() ) {
4858 // Do not call getValue(V) yet, as we don't want to generate code.
4859 // Remember it for later.
4860 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4861 DanglingDebugInfoMap[V] = DDI;
4863 // We may expand this to cover more cases. One case where we have no
4864 // data available is an unreferenced parameter.
4865 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4869 // Build a debug info table entry.
4870 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4871 V = BCI->getOperand(0);
4872 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4873 // Don't handle byval struct arguments or VLAs, for example.
4875 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4876 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4879 DenseMap<const AllocaInst*, int>::iterator SI =
4880 FuncInfo.StaticAllocaMap.find(AI);
4881 if (SI == FuncInfo.StaticAllocaMap.end())
4882 return nullptr; // VLAs.
4886 case Intrinsic::eh_typeid_for: {
4887 // Find the type id for the given typeinfo.
4888 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4889 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4890 Res = DAG.getConstant(TypeID, MVT::i32);
4895 case Intrinsic::eh_return_i32:
4896 case Intrinsic::eh_return_i64:
4897 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4898 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4901 getValue(I.getArgOperand(0)),
4902 getValue(I.getArgOperand(1))));
4904 case Intrinsic::eh_unwind_init:
4905 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4907 case Intrinsic::eh_dwarf_cfa: {
4908 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4909 TLI.getPointerTy());
4910 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4911 CfaArg.getValueType(),
4912 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4913 CfaArg.getValueType()),
4915 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4916 DAG.getConstant(0, TLI.getPointerTy()));
4917 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4921 case Intrinsic::eh_sjlj_callsite: {
4922 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4923 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4924 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4925 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4927 MMI.setCurrentCallSite(CI->getZExtValue());
4930 case Intrinsic::eh_sjlj_functioncontext: {
4931 // Get and store the index of the function context.
4932 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4934 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4935 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4936 MFI->setFunctionContextIndex(FI);
4939 case Intrinsic::eh_sjlj_setjmp: {
4942 Ops[1] = getValue(I.getArgOperand(0));
4943 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4944 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4945 setValue(&I, Op.getValue(0));
4946 DAG.setRoot(Op.getValue(1));
4949 case Intrinsic::eh_sjlj_longjmp: {
4950 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4951 getRoot(), getValue(I.getArgOperand(0))));
4955 case Intrinsic::x86_mmx_pslli_w:
4956 case Intrinsic::x86_mmx_pslli_d:
4957 case Intrinsic::x86_mmx_pslli_q:
4958 case Intrinsic::x86_mmx_psrli_w:
4959 case Intrinsic::x86_mmx_psrli_d:
4960 case Intrinsic::x86_mmx_psrli_q:
4961 case Intrinsic::x86_mmx_psrai_w:
4962 case Intrinsic::x86_mmx_psrai_d: {
4963 SDValue ShAmt = getValue(I.getArgOperand(1));
4964 if (isa<ConstantSDNode>(ShAmt)) {
4965 visitTargetIntrinsic(I, Intrinsic);
4968 unsigned NewIntrinsic = 0;
4969 EVT ShAmtVT = MVT::v2i32;
4970 switch (Intrinsic) {
4971 case Intrinsic::x86_mmx_pslli_w:
4972 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4974 case Intrinsic::x86_mmx_pslli_d:
4975 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4977 case Intrinsic::x86_mmx_pslli_q:
4978 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4980 case Intrinsic::x86_mmx_psrli_w:
4981 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4983 case Intrinsic::x86_mmx_psrli_d:
4984 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4986 case Intrinsic::x86_mmx_psrli_q:
4987 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4989 case Intrinsic::x86_mmx_psrai_w:
4990 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4992 case Intrinsic::x86_mmx_psrai_d:
4993 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4995 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4998 // The vector shift intrinsics with scalars uses 32b shift amounts but
4999 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
5001 // We must do this early because v2i32 is not a legal type.
5004 ShOps[1] = DAG.getConstant(0, MVT::i32);
5005 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
5006 EVT DestVT = TLI.getValueType(I.getType());
5007 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
5008 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
5009 DAG.getConstant(NewIntrinsic, MVT::i32),
5010 getValue(I.getArgOperand(0)), ShAmt);
5014 case Intrinsic::x86_avx_vinsertf128_pd_256:
5015 case Intrinsic::x86_avx_vinsertf128_ps_256:
5016 case Intrinsic::x86_avx_vinsertf128_si_256:
5017 case Intrinsic::x86_avx2_vinserti128: {
5018 EVT DestVT = TLI.getValueType(I.getType());
5019 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
5020 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
5021 ElVT.getVectorNumElements();
5023 DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
5024 getValue(I.getArgOperand(0)), getValue(I.getArgOperand(1)),
5025 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5029 case Intrinsic::x86_avx_vextractf128_pd_256:
5030 case Intrinsic::x86_avx_vextractf128_ps_256:
5031 case Intrinsic::x86_avx_vextractf128_si_256:
5032 case Intrinsic::x86_avx2_vextracti128: {
5033 EVT DestVT = TLI.getValueType(I.getType());
5034 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5035 DestVT.getVectorNumElements();
5036 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5037 getValue(I.getArgOperand(0)),
5038 DAG.getConstant(Idx, TLI.getVectorIdxTy()));
5042 case Intrinsic::convertff:
5043 case Intrinsic::convertfsi:
5044 case Intrinsic::convertfui:
5045 case Intrinsic::convertsif:
5046 case Intrinsic::convertuif:
5047 case Intrinsic::convertss:
5048 case Intrinsic::convertsu:
5049 case Intrinsic::convertus:
5050 case Intrinsic::convertuu: {
5051 ISD::CvtCode Code = ISD::CVT_INVALID;
5052 switch (Intrinsic) {
5053 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5054 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5055 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5056 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5057 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5058 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5059 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5060 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5061 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5062 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5064 EVT DestVT = TLI.getValueType(I.getType());
5065 const Value *Op1 = I.getArgOperand(0);
5066 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5067 DAG.getValueType(DestVT),
5068 DAG.getValueType(getValue(Op1).getValueType()),
5069 getValue(I.getArgOperand(1)),
5070 getValue(I.getArgOperand(2)),
5075 case Intrinsic::powi:
5076 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5077 getValue(I.getArgOperand(1)), DAG));
5079 case Intrinsic::log:
5080 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5082 case Intrinsic::log2:
5083 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5085 case Intrinsic::log10:
5086 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5088 case Intrinsic::exp:
5089 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5091 case Intrinsic::exp2:
5092 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
5094 case Intrinsic::pow:
5095 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5096 getValue(I.getArgOperand(1)), DAG, TLI));
5098 case Intrinsic::sqrt:
5099 case Intrinsic::fabs:
5100 case Intrinsic::sin:
5101 case Intrinsic::cos:
5102 case Intrinsic::floor:
5103 case Intrinsic::ceil:
5104 case Intrinsic::trunc:
5105 case Intrinsic::rint:
5106 case Intrinsic::nearbyint:
5107 case Intrinsic::round: {
5109 switch (Intrinsic) {
5110 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5111 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5112 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5113 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5114 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5115 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5116 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5117 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5118 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5119 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5120 case Intrinsic::round: Opcode = ISD::FROUND; break;
5123 setValue(&I, DAG.getNode(Opcode, sdl,
5124 getValue(I.getArgOperand(0)).getValueType(),
5125 getValue(I.getArgOperand(0))));
5128 case Intrinsic::copysign:
5129 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5130 getValue(I.getArgOperand(0)).getValueType(),
5131 getValue(I.getArgOperand(0)),
5132 getValue(I.getArgOperand(1))));
5134 case Intrinsic::fma:
5135 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5136 getValue(I.getArgOperand(0)).getValueType(),
5137 getValue(I.getArgOperand(0)),
5138 getValue(I.getArgOperand(1)),
5139 getValue(I.getArgOperand(2))));
5141 case Intrinsic::fmuladd: {
5142 EVT VT = TLI.getValueType(I.getType());
5143 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5144 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5145 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5146 getValue(I.getArgOperand(0)).getValueType(),
5147 getValue(I.getArgOperand(0)),
5148 getValue(I.getArgOperand(1)),
5149 getValue(I.getArgOperand(2))));
5151 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5152 getValue(I.getArgOperand(0)).getValueType(),
5153 getValue(I.getArgOperand(0)),
5154 getValue(I.getArgOperand(1)));
5155 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5156 getValue(I.getArgOperand(0)).getValueType(),
5158 getValue(I.getArgOperand(2)));
5163 case Intrinsic::convert_to_fp16:
5164 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5165 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5166 getValue(I.getArgOperand(0)),
5167 DAG.getTargetConstant(0, MVT::i32))));
5169 case Intrinsic::convert_from_fp16:
5171 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5172 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5173 getValue(I.getArgOperand(0)))));
5175 case Intrinsic::pcmarker: {
5176 SDValue Tmp = getValue(I.getArgOperand(0));
5177 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5180 case Intrinsic::readcyclecounter: {
5181 SDValue Op = getRoot();
5182 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5183 DAG.getVTList(MVT::i64, MVT::Other), Op);
5185 DAG.setRoot(Res.getValue(1));
5188 case Intrinsic::bswap:
5189 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5190 getValue(I.getArgOperand(0)).getValueType(),
5191 getValue(I.getArgOperand(0))));
5193 case Intrinsic::cttz: {
5194 SDValue Arg = getValue(I.getArgOperand(0));
5195 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5196 EVT Ty = Arg.getValueType();
5197 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5201 case Intrinsic::ctlz: {
5202 SDValue Arg = getValue(I.getArgOperand(0));
5203 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5204 EVT Ty = Arg.getValueType();
5205 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5209 case Intrinsic::ctpop: {
5210 SDValue Arg = getValue(I.getArgOperand(0));
5211 EVT Ty = Arg.getValueType();
5212 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5215 case Intrinsic::stacksave: {
5216 SDValue Op = getRoot();
5217 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5218 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5220 DAG.setRoot(Res.getValue(1));
5223 case Intrinsic::stackrestore: {
5224 Res = getValue(I.getArgOperand(0));
5225 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5228 case Intrinsic::stackprotector: {
5229 // Emit code into the DAG to store the stack guard onto the stack.
5230 MachineFunction &MF = DAG.getMachineFunction();
5231 MachineFrameInfo *MFI = MF.getFrameInfo();
5232 EVT PtrTy = TLI.getPointerTy();
5233 SDValue Src, Chain = getRoot();
5234 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5235 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5237 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5238 // global variable __stack_chk_guard.
5240 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5241 if (BC->getOpcode() == Instruction::BitCast)
5242 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5244 if (GV && TLI.useLoadStackGuardNode()) {
5245 // Emit a LOAD_STACK_GUARD node.
5246 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5248 MachinePointerInfo MPInfo(GV);
5249 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5250 unsigned Flags = MachineMemOperand::MOLoad |
5251 MachineMemOperand::MOInvariant;
5252 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5253 PtrTy.getSizeInBits() / 8,
5254 DAG.getEVTAlignment(PtrTy));
5255 Node->setMemRefs(MemRefs, MemRefs + 1);
5257 // Copy the guard value to a virtual register so that it can be
5258 // retrieved in the epilogue.
5259 Src = SDValue(Node, 0);
5260 const TargetRegisterClass *RC =
5261 TLI.getRegClassFor(Src.getSimpleValueType());
5262 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5264 SPDescriptor.setGuardReg(Reg);
5265 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5267 Src = getValue(I.getArgOperand(0)); // The guard's value.
5270 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5272 int FI = FuncInfo.StaticAllocaMap[Slot];
5273 MFI->setStackProtectorIndex(FI);
5275 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5277 // Store the stack protector onto the stack.
5278 Res = DAG.getStore(Chain, sdl, Src, FIN,
5279 MachinePointerInfo::getFixedStack(FI),
5285 case Intrinsic::objectsize: {
5286 // If we don't know by now, we're never going to know.
5287 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5289 assert(CI && "Non-constant type in __builtin_object_size?");
5291 SDValue Arg = getValue(I.getCalledValue());
5292 EVT Ty = Arg.getValueType();
5295 Res = DAG.getConstant(-1ULL, Ty);
5297 Res = DAG.getConstant(0, Ty);
5302 case Intrinsic::annotation:
5303 case Intrinsic::ptr_annotation:
5304 // Drop the intrinsic, but forward the value
5305 setValue(&I, getValue(I.getOperand(0)));
5307 case Intrinsic::assume:
5308 case Intrinsic::var_annotation:
5309 // Discard annotate attributes and assumptions
5312 case Intrinsic::init_trampoline: {
5313 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5317 Ops[1] = getValue(I.getArgOperand(0));
5318 Ops[2] = getValue(I.getArgOperand(1));
5319 Ops[3] = getValue(I.getArgOperand(2));
5320 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5321 Ops[5] = DAG.getSrcValue(F);
5323 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5328 case Intrinsic::adjust_trampoline: {
5329 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5331 getValue(I.getArgOperand(0))));
5334 case Intrinsic::gcroot:
5336 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5337 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5339 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5340 GFI->addStackRoot(FI->getIndex(), TypeMap);
5343 case Intrinsic::gcread:
5344 case Intrinsic::gcwrite:
5345 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5346 case Intrinsic::flt_rounds:
5347 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5350 case Intrinsic::expect: {
5351 // Just replace __builtin_expect(exp, c) with EXP.
5352 setValue(&I, getValue(I.getArgOperand(0)));
5356 case Intrinsic::debugtrap:
5357 case Intrinsic::trap: {
5358 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5359 if (TrapFuncName.empty()) {
5360 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5361 ISD::TRAP : ISD::DEBUGTRAP;
5362 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5365 TargetLowering::ArgListTy Args;
5367 TargetLowering::CallLoweringInfo CLI(DAG);
5368 CLI.setDebugLoc(sdl).setChain(getRoot())
5369 .setCallee(CallingConv::C, I.getType(),
5370 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5371 std::move(Args), 0);
5373 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5374 DAG.setRoot(Result.second);
5378 case Intrinsic::uadd_with_overflow:
5379 case Intrinsic::sadd_with_overflow:
5380 case Intrinsic::usub_with_overflow:
5381 case Intrinsic::ssub_with_overflow:
5382 case Intrinsic::umul_with_overflow:
5383 case Intrinsic::smul_with_overflow: {
5385 switch (Intrinsic) {
5386 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5387 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5388 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5389 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5390 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5391 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5392 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5394 SDValue Op1 = getValue(I.getArgOperand(0));
5395 SDValue Op2 = getValue(I.getArgOperand(1));
5397 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5398 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5401 case Intrinsic::prefetch: {
5403 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5405 Ops[1] = getValue(I.getArgOperand(0));
5406 Ops[2] = getValue(I.getArgOperand(1));
5407 Ops[3] = getValue(I.getArgOperand(2));
5408 Ops[4] = getValue(I.getArgOperand(3));
5409 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5410 DAG.getVTList(MVT::Other), Ops,
5411 EVT::getIntegerVT(*Context, 8),
5412 MachinePointerInfo(I.getArgOperand(0)),
5414 false, /* volatile */
5416 rw==1)); /* write */
5419 case Intrinsic::lifetime_start:
5420 case Intrinsic::lifetime_end: {
5421 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5422 // Stack coloring is not enabled in O0, discard region information.
5423 if (TM.getOptLevel() == CodeGenOpt::None)
5426 SmallVector<Value *, 4> Allocas;
5427 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5429 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5430 E = Allocas.end(); Object != E; ++Object) {
5431 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5433 // Could not find an Alloca.
5434 if (!LifetimeObject)
5437 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5441 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5442 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5444 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5449 case Intrinsic::invariant_start:
5450 // Discard region information.
5451 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5453 case Intrinsic::invariant_end:
5454 // Discard region information.
5456 case Intrinsic::stackprotectorcheck: {
5457 // Do not actually emit anything for this basic block. Instead we initialize
5458 // the stack protector descriptor and export the guard variable so we can
5459 // access it in FinishBasicBlock.
5460 const BasicBlock *BB = I.getParent();
5461 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5462 ExportFromCurrentBlock(SPDescriptor.getGuard());
5464 // Flush our exports since we are going to process a terminator.
5465 (void)getControlRoot();
5468 case Intrinsic::clear_cache:
5469 return TLI.getClearCacheBuiltinName();
5470 case Intrinsic::donothing:
5473 case Intrinsic::experimental_stackmap: {
5477 case Intrinsic::experimental_patchpoint_void:
5478 case Intrinsic::experimental_patchpoint_i64: {
5485 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5487 MachineBasicBlock *LandingPad) {
5488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5489 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5490 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5491 Type *RetTy = FTy->getReturnType();
5492 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5493 MCSymbol *BeginLabel = nullptr;
5495 TargetLowering::ArgListTy Args;
5496 TargetLowering::ArgListEntry Entry;
5497 Args.reserve(CS.arg_size());
5499 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5501 const Value *V = *i;
5504 if (V->getType()->isEmptyTy())
5507 SDValue ArgNode = getValue(V);
5508 Entry.Node = ArgNode; Entry.Ty = V->getType();
5510 // Skip the first return-type Attribute to get to params.
5511 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5512 Args.push_back(Entry);
5516 // Insert a label before the invoke call to mark the try range. This can be
5517 // used to detect deletion of the invoke via the MachineModuleInfo.
5518 BeginLabel = MMI.getContext().CreateTempSymbol();
5520 // For SjLj, keep track of which landing pads go with which invokes
5521 // so as to maintain the ordering of pads in the LSDA.
5522 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5523 if (CallSiteIndex) {
5524 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5525 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5527 // Now that the call site is handled, stop tracking it.
5528 MMI.setCurrentCallSite(0);
5531 // Both PendingLoads and PendingExports must be flushed here;
5532 // this call might not return.
5534 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5537 // Check if target-independent constraints permit a tail call here.
5538 // Target-dependent constraints are checked within TLI.LowerCallTo.
5539 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5542 TargetLowering::CallLoweringInfo CLI(DAG);
5543 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5544 .setCallee(RetTy, FTy, Callee, std::move(Args), CS).setTailCall(isTailCall);
5546 std::pair<SDValue,SDValue> Result = TLI.LowerCallTo(CLI);
5547 assert((isTailCall || Result.second.getNode()) &&
5548 "Non-null chain expected with non-tail call!");
5549 assert((Result.second.getNode() || !Result.first.getNode()) &&
5550 "Null value expected with tail call!");
5551 if (Result.first.getNode())
5552 setValue(CS.getInstruction(), Result.first);
5554 if (!Result.second.getNode()) {
5555 // As a special case, a null chain means that a tail call has been emitted
5556 // and the DAG root is already updated.
5559 // Since there's no actual continuation from this block, nothing can be
5560 // relying on us setting vregs for them.
5561 PendingExports.clear();
5563 DAG.setRoot(Result.second);
5567 // Insert a label at the end of the invoke call to mark the try range. This
5568 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5569 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5570 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5572 // Inform MachineModuleInfo of range.
5573 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5577 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5578 /// value is equal or not-equal to zero.
5579 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5580 for (const User *U : V->users()) {
5581 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5582 if (IC->isEquality())
5583 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5584 if (C->isNullValue())
5586 // Unknown instruction.
5592 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5594 SelectionDAGBuilder &Builder) {
5596 // Check to see if this load can be trivially constant folded, e.g. if the
5597 // input is from a string literal.
5598 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5599 // Cast pointer to the type we really want to load.
5600 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5601 PointerType::getUnqual(LoadTy));
5603 if (const Constant *LoadCst =
5604 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5606 return Builder.getValue(LoadCst);
5609 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5610 // still constant memory, the input chain can be the entry node.
5612 bool ConstantMemory = false;
5614 // Do not serialize (non-volatile) loads of constant memory with anything.
5615 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5616 Root = Builder.DAG.getEntryNode();
5617 ConstantMemory = true;
5619 // Do not serialize non-volatile loads against each other.
5620 Root = Builder.DAG.getRoot();
5623 SDValue Ptr = Builder.getValue(PtrVal);
5624 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5625 Ptr, MachinePointerInfo(PtrVal),
5627 false /*nontemporal*/,
5628 false /*isinvariant*/, 1 /* align=1 */);
5630 if (!ConstantMemory)
5631 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5635 /// processIntegerCallValue - Record the value for an instruction that
5636 /// produces an integer result, converting the type where necessary.
5637 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5640 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5642 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5644 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5645 setValue(&I, Value);
5648 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5649 /// If so, return true and lower it, otherwise return false and it will be
5650 /// lowered like a normal call.
5651 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5652 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5653 if (I.getNumArgOperands() != 3)
5656 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5657 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5658 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5659 !I.getType()->isIntegerTy())
5662 const Value *Size = I.getArgOperand(2);
5663 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5664 if (CSize && CSize->getZExtValue() == 0) {
5665 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5666 setValue(&I, DAG.getConstant(0, CallVT));
5670 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5671 std::pair<SDValue, SDValue> Res =
5672 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5673 getValue(LHS), getValue(RHS), getValue(Size),
5674 MachinePointerInfo(LHS),
5675 MachinePointerInfo(RHS));
5676 if (Res.first.getNode()) {
5677 processIntegerCallValue(I, Res.first, true);
5678 PendingLoads.push_back(Res.second);
5682 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5683 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5684 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5685 bool ActuallyDoIt = true;
5688 switch (CSize->getZExtValue()) {
5690 LoadVT = MVT::Other;
5692 ActuallyDoIt = false;
5696 LoadTy = Type::getInt16Ty(CSize->getContext());
5700 LoadTy = Type::getInt32Ty(CSize->getContext());
5704 LoadTy = Type::getInt64Ty(CSize->getContext());
5708 LoadVT = MVT::v4i32;
5709 LoadTy = Type::getInt32Ty(CSize->getContext());
5710 LoadTy = VectorType::get(LoadTy, 4);
5715 // This turns into unaligned loads. We only do this if the target natively
5716 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5717 // we'll only produce a small number of byte loads.
5719 // Require that we can find a legal MVT, and only do this if the target
5720 // supports unaligned loads of that type. Expanding into byte loads would
5722 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5723 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5724 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5725 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5726 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5727 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5728 // TODO: Check alignment of src and dest ptrs.
5729 if (!TLI.isTypeLegal(LoadVT) ||
5730 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5731 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5732 ActuallyDoIt = false;
5736 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5737 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5739 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5741 processIntegerCallValue(I, Res, false);
5750 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5751 /// form. If so, return true and lower it, otherwise return false and it
5752 /// will be lowered like a normal call.
5753 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5754 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5755 if (I.getNumArgOperands() != 3)
5758 const Value *Src = I.getArgOperand(0);
5759 const Value *Char = I.getArgOperand(1);
5760 const Value *Length = I.getArgOperand(2);
5761 if (!Src->getType()->isPointerTy() ||
5762 !Char->getType()->isIntegerTy() ||
5763 !Length->getType()->isIntegerTy() ||
5764 !I.getType()->isPointerTy())
5767 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5768 std::pair<SDValue, SDValue> Res =
5769 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5770 getValue(Src), getValue(Char), getValue(Length),
5771 MachinePointerInfo(Src));
5772 if (Res.first.getNode()) {
5773 setValue(&I, Res.first);
5774 PendingLoads.push_back(Res.second);
5781 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5782 /// optimized form. If so, return true and lower it, otherwise return false
5783 /// and it will be lowered like a normal call.
5784 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5785 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5786 if (I.getNumArgOperands() != 2)
5789 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5790 if (!Arg0->getType()->isPointerTy() ||
5791 !Arg1->getType()->isPointerTy() ||
5792 !I.getType()->isPointerTy())
5795 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5796 std::pair<SDValue, SDValue> Res =
5797 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5798 getValue(Arg0), getValue(Arg1),
5799 MachinePointerInfo(Arg0),
5800 MachinePointerInfo(Arg1), isStpcpy);
5801 if (Res.first.getNode()) {
5802 setValue(&I, Res.first);
5803 DAG.setRoot(Res.second);
5810 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5811 /// If so, return true and lower it, otherwise return false and it will be
5812 /// lowered like a normal call.
5813 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5814 // Verify that the prototype makes sense. int strcmp(void*,void*)
5815 if (I.getNumArgOperands() != 2)
5818 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5819 if (!Arg0->getType()->isPointerTy() ||
5820 !Arg1->getType()->isPointerTy() ||
5821 !I.getType()->isIntegerTy())
5824 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5825 std::pair<SDValue, SDValue> Res =
5826 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5827 getValue(Arg0), getValue(Arg1),
5828 MachinePointerInfo(Arg0),
5829 MachinePointerInfo(Arg1));
5830 if (Res.first.getNode()) {
5831 processIntegerCallValue(I, Res.first, true);
5832 PendingLoads.push_back(Res.second);
5839 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5840 /// form. If so, return true and lower it, otherwise return false and it
5841 /// will be lowered like a normal call.
5842 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5843 // Verify that the prototype makes sense. size_t strlen(char *)
5844 if (I.getNumArgOperands() != 1)
5847 const Value *Arg0 = I.getArgOperand(0);
5848 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5851 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5852 std::pair<SDValue, SDValue> Res =
5853 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5854 getValue(Arg0), MachinePointerInfo(Arg0));
5855 if (Res.first.getNode()) {
5856 processIntegerCallValue(I, Res.first, false);
5857 PendingLoads.push_back(Res.second);
5864 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5865 /// form. If so, return true and lower it, otherwise return false and it
5866 /// will be lowered like a normal call.
5867 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5868 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5869 if (I.getNumArgOperands() != 2)
5872 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5873 if (!Arg0->getType()->isPointerTy() ||
5874 !Arg1->getType()->isIntegerTy() ||
5875 !I.getType()->isIntegerTy())
5878 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5879 std::pair<SDValue, SDValue> Res =
5880 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5881 getValue(Arg0), getValue(Arg1),
5882 MachinePointerInfo(Arg0));
5883 if (Res.first.getNode()) {
5884 processIntegerCallValue(I, Res.first, false);
5885 PendingLoads.push_back(Res.second);
5892 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5893 /// operation (as expected), translate it to an SDNode with the specified opcode
5894 /// and return true.
5895 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5897 // Sanity check that it really is a unary floating-point call.
5898 if (I.getNumArgOperands() != 1 ||
5899 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5900 I.getType() != I.getArgOperand(0)->getType() ||
5901 !I.onlyReadsMemory())
5904 SDValue Tmp = getValue(I.getArgOperand(0));
5905 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5909 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5910 // Handle inline assembly differently.
5911 if (isa<InlineAsm>(I.getCalledValue())) {
5916 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5917 ComputeUsesVAFloatArgument(I, &MMI);
5919 const char *RenameFn = nullptr;
5920 if (Function *F = I.getCalledFunction()) {
5921 if (F->isDeclaration()) {
5922 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5923 if (unsigned IID = II->getIntrinsicID(F)) {
5924 RenameFn = visitIntrinsicCall(I, IID);
5929 if (unsigned IID = F->getIntrinsicID()) {
5930 RenameFn = visitIntrinsicCall(I, IID);
5936 // Check for well-known libc/libm calls. If the function is internal, it
5937 // can't be a library call.
5939 if (!F->hasLocalLinkage() && F->hasName() &&
5940 LibInfo->getLibFunc(F->getName(), Func) &&
5941 LibInfo->hasOptimizedCodeGen(Func)) {
5944 case LibFunc::copysign:
5945 case LibFunc::copysignf:
5946 case LibFunc::copysignl:
5947 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5948 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5949 I.getType() == I.getArgOperand(0)->getType() &&
5950 I.getType() == I.getArgOperand(1)->getType() &&
5951 I.onlyReadsMemory()) {
5952 SDValue LHS = getValue(I.getArgOperand(0));
5953 SDValue RHS = getValue(I.getArgOperand(1));
5954 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5955 LHS.getValueType(), LHS, RHS));
5960 case LibFunc::fabsf:
5961 case LibFunc::fabsl:
5962 if (visitUnaryFloatCall(I, ISD::FABS))
5968 if (visitUnaryFloatCall(I, ISD::FSIN))
5974 if (visitUnaryFloatCall(I, ISD::FCOS))
5978 case LibFunc::sqrtf:
5979 case LibFunc::sqrtl:
5980 case LibFunc::sqrt_finite:
5981 case LibFunc::sqrtf_finite:
5982 case LibFunc::sqrtl_finite:
5983 if (visitUnaryFloatCall(I, ISD::FSQRT))
5986 case LibFunc::floor:
5987 case LibFunc::floorf:
5988 case LibFunc::floorl:
5989 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5992 case LibFunc::nearbyint:
5993 case LibFunc::nearbyintf:
5994 case LibFunc::nearbyintl:
5995 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5999 case LibFunc::ceilf:
6000 case LibFunc::ceill:
6001 if (visitUnaryFloatCall(I, ISD::FCEIL))
6005 case LibFunc::rintf:
6006 case LibFunc::rintl:
6007 if (visitUnaryFloatCall(I, ISD::FRINT))
6010 case LibFunc::round:
6011 case LibFunc::roundf:
6012 case LibFunc::roundl:
6013 if (visitUnaryFloatCall(I, ISD::FROUND))
6016 case LibFunc::trunc:
6017 case LibFunc::truncf:
6018 case LibFunc::truncl:
6019 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6023 case LibFunc::log2f:
6024 case LibFunc::log2l:
6025 if (visitUnaryFloatCall(I, ISD::FLOG2))
6029 case LibFunc::exp2f:
6030 case LibFunc::exp2l:
6031 if (visitUnaryFloatCall(I, ISD::FEXP2))
6034 case LibFunc::memcmp:
6035 if (visitMemCmpCall(I))
6038 case LibFunc::memchr:
6039 if (visitMemChrCall(I))
6042 case LibFunc::strcpy:
6043 if (visitStrCpyCall(I, false))
6046 case LibFunc::stpcpy:
6047 if (visitStrCpyCall(I, true))
6050 case LibFunc::strcmp:
6051 if (visitStrCmpCall(I))
6054 case LibFunc::strlen:
6055 if (visitStrLenCall(I))
6058 case LibFunc::strnlen:
6059 if (visitStrNLenCall(I))
6068 Callee = getValue(I.getCalledValue());
6070 Callee = DAG.getExternalSymbol(RenameFn,
6071 DAG.getTargetLoweringInfo().getPointerTy());
6073 // Check if we can potentially perform a tail call. More detailed checking is
6074 // be done within LowerCallTo, after more information about the call is known.
6075 LowerCallTo(&I, Callee, I.isTailCall());
6080 /// AsmOperandInfo - This contains information for each constraint that we are
6082 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6084 /// CallOperand - If this is the result output operand or a clobber
6085 /// this is null, otherwise it is the incoming operand to the CallInst.
6086 /// This gets modified as the asm is processed.
6087 SDValue CallOperand;
6089 /// AssignedRegs - If this is a register or register class operand, this
6090 /// contains the set of register corresponding to the operand.
6091 RegsForValue AssignedRegs;
6093 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6094 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6097 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6098 /// corresponds to. If there is no Value* for this operand, it returns
6100 EVT getCallOperandValEVT(LLVMContext &Context,
6101 const TargetLowering &TLI,
6102 const DataLayout *DL) const {
6103 if (!CallOperandVal) return MVT::Other;
6105 if (isa<BasicBlock>(CallOperandVal))
6106 return TLI.getPointerTy();
6108 llvm::Type *OpTy = CallOperandVal->getType();
6110 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6111 // If this is an indirect operand, the operand is a pointer to the
6114 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6116 report_fatal_error("Indirect operand for inline asm not a pointer!");
6117 OpTy = PtrTy->getElementType();
6120 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6121 if (StructType *STy = dyn_cast<StructType>(OpTy))
6122 if (STy->getNumElements() == 1)
6123 OpTy = STy->getElementType(0);
6125 // If OpTy is not a single value, it may be a struct/union that we
6126 // can tile with integers.
6127 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6128 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6137 OpTy = IntegerType::get(Context, BitSize);
6142 return TLI.getValueType(OpTy, true);
6146 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6148 } // end anonymous namespace
6150 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6151 /// specified operand. We prefer to assign virtual registers, to allow the
6152 /// register allocator to handle the assignment process. However, if the asm
6153 /// uses features that we can't model on machineinstrs, we have SDISel do the
6154 /// allocation. This produces generally horrible, but correct, code.
6156 /// OpInfo describes the operand.
6158 static void GetRegistersForValue(SelectionDAG &DAG,
6159 const TargetLowering &TLI,
6161 SDISelAsmOperandInfo &OpInfo) {
6162 LLVMContext &Context = *DAG.getContext();
6164 MachineFunction &MF = DAG.getMachineFunction();
6165 SmallVector<unsigned, 4> Regs;
6167 // If this is a constraint for a single physreg, or a constraint for a
6168 // register class, find it.
6169 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6170 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6171 OpInfo.ConstraintVT);
6173 unsigned NumRegs = 1;
6174 if (OpInfo.ConstraintVT != MVT::Other) {
6175 // If this is a FP input in an integer register (or visa versa) insert a bit
6176 // cast of the input value. More generally, handle any case where the input
6177 // value disagrees with the register class we plan to stick this in.
6178 if (OpInfo.Type == InlineAsm::isInput &&
6179 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6180 // Try to convert to the first EVT that the reg class contains. If the
6181 // types are identical size, use a bitcast to convert (e.g. two differing
6183 MVT RegVT = *PhysReg.second->vt_begin();
6184 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6185 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6186 RegVT, OpInfo.CallOperand);
6187 OpInfo.ConstraintVT = RegVT;
6188 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6189 // If the input is a FP value and we want it in FP registers, do a
6190 // bitcast to the corresponding integer type. This turns an f64 value
6191 // into i64, which can be passed with two i32 values on a 32-bit
6193 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6194 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6195 RegVT, OpInfo.CallOperand);
6196 OpInfo.ConstraintVT = RegVT;
6200 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6204 EVT ValueVT = OpInfo.ConstraintVT;
6206 // If this is a constraint for a specific physical register, like {r17},
6208 if (unsigned AssignedReg = PhysReg.first) {
6209 const TargetRegisterClass *RC = PhysReg.second;
6210 if (OpInfo.ConstraintVT == MVT::Other)
6211 ValueVT = *RC->vt_begin();
6213 // Get the actual register value type. This is important, because the user
6214 // may have asked for (e.g.) the AX register in i32 type. We need to
6215 // remember that AX is actually i16 to get the right extension.
6216 RegVT = *RC->vt_begin();
6218 // This is a explicit reference to a physical register.
6219 Regs.push_back(AssignedReg);
6221 // If this is an expanded reference, add the rest of the regs to Regs.
6223 TargetRegisterClass::iterator I = RC->begin();
6224 for (; *I != AssignedReg; ++I)
6225 assert(I != RC->end() && "Didn't find reg!");
6227 // Already added the first reg.
6229 for (; NumRegs; --NumRegs, ++I) {
6230 assert(I != RC->end() && "Ran out of registers to allocate!");
6235 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6239 // Otherwise, if this was a reference to an LLVM register class, create vregs
6240 // for this reference.
6241 if (const TargetRegisterClass *RC = PhysReg.second) {
6242 RegVT = *RC->vt_begin();
6243 if (OpInfo.ConstraintVT == MVT::Other)
6246 // Create the appropriate number of virtual registers.
6247 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6248 for (; NumRegs; --NumRegs)
6249 Regs.push_back(RegInfo.createVirtualRegister(RC));
6251 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6255 // Otherwise, we couldn't allocate enough registers for this.
6258 /// visitInlineAsm - Handle a call to an InlineAsm object.
6260 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6261 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6263 /// ConstraintOperands - Information about all of the constraints.
6264 SDISelAsmOperandInfoVector ConstraintOperands;
6266 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6267 TargetLowering::AsmOperandInfoVector
6268 TargetConstraints = TLI.ParseConstraints(CS);
6270 bool hasMemory = false;
6272 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6273 unsigned ResNo = 0; // ResNo - The result number of the next output.
6274 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6275 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6276 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6278 MVT OpVT = MVT::Other;
6280 // Compute the value type for each operand.
6281 switch (OpInfo.Type) {
6282 case InlineAsm::isOutput:
6283 // Indirect outputs just consume an argument.
6284 if (OpInfo.isIndirect) {
6285 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6289 // The return value of the call is this value. As such, there is no
6290 // corresponding argument.
6291 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6292 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6293 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6295 assert(ResNo == 0 && "Asm only has one result!");
6296 OpVT = TLI.getSimpleValueType(CS.getType());
6300 case InlineAsm::isInput:
6301 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6303 case InlineAsm::isClobber:
6308 // If this is an input or an indirect output, process the call argument.
6309 // BasicBlocks are labels, currently appearing only in asm's.
6310 if (OpInfo.CallOperandVal) {
6311 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6312 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6314 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6318 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6321 OpInfo.ConstraintVT = OpVT;
6323 // Indirect operand accesses access memory.
6324 if (OpInfo.isIndirect)
6327 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6328 TargetLowering::ConstraintType
6329 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6330 if (CType == TargetLowering::C_Memory) {
6338 SDValue Chain, Flag;
6340 // We won't need to flush pending loads if this asm doesn't touch
6341 // memory and is nonvolatile.
6342 if (hasMemory || IA->hasSideEffects())
6345 Chain = DAG.getRoot();
6347 // Second pass over the constraints: compute which constraint option to use
6348 // and assign registers to constraints that want a specific physreg.
6349 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6350 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6352 // If this is an output operand with a matching input operand, look up the
6353 // matching input. If their types mismatch, e.g. one is an integer, the
6354 // other is floating point, or their sizes are different, flag it as an
6356 if (OpInfo.hasMatchingInput()) {
6357 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6359 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6360 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6361 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6362 OpInfo.ConstraintVT);
6363 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6364 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
6365 Input.ConstraintVT);
6366 if ((OpInfo.ConstraintVT.isInteger() !=
6367 Input.ConstraintVT.isInteger()) ||
6368 (MatchRC.second != InputRC.second)) {
6369 report_fatal_error("Unsupported asm: input constraint"
6370 " with a matching output constraint of"
6371 " incompatible type!");
6373 Input.ConstraintVT = OpInfo.ConstraintVT;
6377 // Compute the constraint code and ConstraintType to use.
6378 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6380 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6381 OpInfo.Type == InlineAsm::isClobber)
6384 // If this is a memory input, and if the operand is not indirect, do what we
6385 // need to to provide an address for the memory input.
6386 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6387 !OpInfo.isIndirect) {
6388 assert((OpInfo.isMultipleAlternative ||
6389 (OpInfo.Type == InlineAsm::isInput)) &&
6390 "Can only indirectify direct input operands!");
6392 // Memory operands really want the address of the value. If we don't have
6393 // an indirect input, put it in the constpool if we can, otherwise spill
6394 // it to a stack slot.
6395 // TODO: This isn't quite right. We need to handle these according to
6396 // the addressing mode that the constraint wants. Also, this may take
6397 // an additional register for the computation and we don't want that
6400 // If the operand is a float, integer, or vector constant, spill to a
6401 // constant pool entry to get its address.
6402 const Value *OpVal = OpInfo.CallOperandVal;
6403 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6404 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6405 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6406 TLI.getPointerTy());
6408 // Otherwise, create a stack slot and emit a store to it before the
6410 Type *Ty = OpVal->getType();
6411 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6412 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6413 MachineFunction &MF = DAG.getMachineFunction();
6414 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6415 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6416 Chain = DAG.getStore(Chain, getCurSDLoc(),
6417 OpInfo.CallOperand, StackSlot,
6418 MachinePointerInfo::getFixedStack(SSFI),
6420 OpInfo.CallOperand = StackSlot;
6423 // There is no longer a Value* corresponding to this operand.
6424 OpInfo.CallOperandVal = nullptr;
6426 // It is now an indirect operand.
6427 OpInfo.isIndirect = true;
6430 // If this constraint is for a specific register, allocate it before
6432 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6433 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6436 // Second pass - Loop over all of the operands, assigning virtual or physregs
6437 // to register class operands.
6438 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6439 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6441 // C_Register operands have already been allocated, Other/Memory don't need
6443 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6444 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6447 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6448 std::vector<SDValue> AsmNodeOperands;
6449 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6450 AsmNodeOperands.push_back(
6451 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6452 TLI.getPointerTy()));
6454 // If we have a !srcloc metadata node associated with it, we want to attach
6455 // this to the ultimately generated inline asm machineinstr. To do this, we
6456 // pass in the third operand as this (potentially null) inline asm MDNode.
6457 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6458 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6460 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6461 // bits as operand 3.
6462 unsigned ExtraInfo = 0;
6463 if (IA->hasSideEffects())
6464 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6465 if (IA->isAlignStack())
6466 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6467 // Set the asm dialect.
6468 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6470 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6471 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6472 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6474 // Compute the constraint code and ConstraintType to use.
6475 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6477 // Ideally, we would only check against memory constraints. However, the
6478 // meaning of an other constraint can be target-specific and we can't easily
6479 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6480 // for other constriants as well.
6481 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6482 OpInfo.ConstraintType == TargetLowering::C_Other) {
6483 if (OpInfo.Type == InlineAsm::isInput)
6484 ExtraInfo |= InlineAsm::Extra_MayLoad;
6485 else if (OpInfo.Type == InlineAsm::isOutput)
6486 ExtraInfo |= InlineAsm::Extra_MayStore;
6487 else if (OpInfo.Type == InlineAsm::isClobber)
6488 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6492 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6493 TLI.getPointerTy()));
6495 // Loop over all of the inputs, copying the operand values into the
6496 // appropriate registers and processing the output regs.
6497 RegsForValue RetValRegs;
6499 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6500 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6502 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6503 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6505 switch (OpInfo.Type) {
6506 case InlineAsm::isOutput: {
6507 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6508 OpInfo.ConstraintType != TargetLowering::C_Register) {
6509 // Memory output, or 'other' output (e.g. 'X' constraint).
6510 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6512 // Add information to the INLINEASM node to know about this output.
6513 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6514 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6515 TLI.getPointerTy()));
6516 AsmNodeOperands.push_back(OpInfo.CallOperand);
6520 // Otherwise, this is a register or register class output.
6522 // Copy the output from the appropriate register. Find a register that
6524 if (OpInfo.AssignedRegs.Regs.empty()) {
6525 LLVMContext &Ctx = *DAG.getContext();
6526 Ctx.emitError(CS.getInstruction(),
6527 "couldn't allocate output register for constraint '" +
6528 Twine(OpInfo.ConstraintCode) + "'");
6532 // If this is an indirect operand, store through the pointer after the
6534 if (OpInfo.isIndirect) {
6535 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6536 OpInfo.CallOperandVal));
6538 // This is the result value of the call.
6539 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6540 // Concatenate this output onto the outputs list.
6541 RetValRegs.append(OpInfo.AssignedRegs);
6544 // Add information to the INLINEASM node to know that this register is
6547 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6548 ? InlineAsm::Kind_RegDefEarlyClobber
6549 : InlineAsm::Kind_RegDef,
6550 false, 0, DAG, AsmNodeOperands);
6553 case InlineAsm::isInput: {
6554 SDValue InOperandVal = OpInfo.CallOperand;
6556 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6557 // If this is required to match an output register we have already set,
6558 // just use its register.
6559 unsigned OperandNo = OpInfo.getMatchedOperand();
6561 // Scan until we find the definition we already emitted of this operand.
6562 // When we find it, create a RegsForValue operand.
6563 unsigned CurOp = InlineAsm::Op_FirstOperand;
6564 for (; OperandNo; --OperandNo) {
6565 // Advance to the next operand.
6567 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6568 assert((InlineAsm::isRegDefKind(OpFlag) ||
6569 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6570 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6571 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6575 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6576 if (InlineAsm::isRegDefKind(OpFlag) ||
6577 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6578 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6579 if (OpInfo.isIndirect) {
6580 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6581 LLVMContext &Ctx = *DAG.getContext();
6582 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6583 " don't know how to handle tied "
6584 "indirect register inputs");
6588 RegsForValue MatchedRegs;
6589 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6590 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6591 MatchedRegs.RegVTs.push_back(RegVT);
6592 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6593 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6595 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6596 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6598 LLVMContext &Ctx = *DAG.getContext();
6599 Ctx.emitError(CS.getInstruction(),
6600 "inline asm error: This value"
6601 " type register class is not natively supported!");
6605 // Use the produced MatchedRegs object to
6606 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6607 Chain, &Flag, CS.getInstruction());
6608 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6609 true, OpInfo.getMatchedOperand(),
6610 DAG, AsmNodeOperands);
6614 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6615 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6616 "Unexpected number of operands");
6617 // Add information to the INLINEASM node to know about this input.
6618 // See InlineAsm.h isUseOperandTiedToDef.
6619 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6620 OpInfo.getMatchedOperand());
6621 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6622 TLI.getPointerTy()));
6623 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6627 // Treat indirect 'X' constraint as memory.
6628 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6630 OpInfo.ConstraintType = TargetLowering::C_Memory;
6632 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6633 std::vector<SDValue> Ops;
6634 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6637 LLVMContext &Ctx = *DAG.getContext();
6638 Ctx.emitError(CS.getInstruction(),
6639 "invalid operand for inline asm constraint '" +
6640 Twine(OpInfo.ConstraintCode) + "'");
6644 // Add information to the INLINEASM node to know about this input.
6645 unsigned ResOpType =
6646 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6647 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6648 TLI.getPointerTy()));
6649 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6653 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6654 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6655 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6656 "Memory operands expect pointer values");
6658 // Add information to the INLINEASM node to know about this input.
6659 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6660 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6661 TLI.getPointerTy()));
6662 AsmNodeOperands.push_back(InOperandVal);
6666 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6667 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6668 "Unknown constraint type!");
6670 // TODO: Support this.
6671 if (OpInfo.isIndirect) {
6672 LLVMContext &Ctx = *DAG.getContext();
6673 Ctx.emitError(CS.getInstruction(),
6674 "Don't know how to handle indirect register inputs yet "
6675 "for constraint '" +
6676 Twine(OpInfo.ConstraintCode) + "'");
6680 // Copy the input into the appropriate registers.
6681 if (OpInfo.AssignedRegs.Regs.empty()) {
6682 LLVMContext &Ctx = *DAG.getContext();
6683 Ctx.emitError(CS.getInstruction(),
6684 "couldn't allocate input reg for constraint '" +
6685 Twine(OpInfo.ConstraintCode) + "'");
6689 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6690 Chain, &Flag, CS.getInstruction());
6692 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6693 DAG, AsmNodeOperands);
6696 case InlineAsm::isClobber: {
6697 // Add the clobbered value to the operand list, so that the register
6698 // allocator is aware that the physreg got clobbered.
6699 if (!OpInfo.AssignedRegs.Regs.empty())
6700 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6708 // Finish up input operands. Set the input chain and add the flag last.
6709 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6710 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6712 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6713 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6714 Flag = Chain.getValue(1);
6716 // If this asm returns a register value, copy the result from that register
6717 // and set it as the value of the call.
6718 if (!RetValRegs.Regs.empty()) {
6719 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6720 Chain, &Flag, CS.getInstruction());
6722 // FIXME: Why don't we do this for inline asms with MRVs?
6723 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6724 EVT ResultType = TLI.getValueType(CS.getType());
6726 // If any of the results of the inline asm is a vector, it may have the
6727 // wrong width/num elts. This can happen for register classes that can
6728 // contain multiple different value types. The preg or vreg allocated may
6729 // not have the same VT as was expected. Convert it to the right type
6730 // with bit_convert.
6731 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6732 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6735 } else if (ResultType != Val.getValueType() &&
6736 ResultType.isInteger() && Val.getValueType().isInteger()) {
6737 // If a result value was tied to an input value, the computed result may
6738 // have a wider width than the expected result. Extract the relevant
6740 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6743 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6746 setValue(CS.getInstruction(), Val);
6747 // Don't need to use this as a chain in this case.
6748 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6752 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6754 // Process indirect outputs, first output all of the flagged copies out of
6756 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6757 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6758 const Value *Ptr = IndirectStoresToEmit[i].second;
6759 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6761 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6764 // Emit the non-flagged stores from the physregs.
6765 SmallVector<SDValue, 8> OutChains;
6766 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6767 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6768 StoresToEmit[i].first,
6769 getValue(StoresToEmit[i].second),
6770 MachinePointerInfo(StoresToEmit[i].second),
6772 OutChains.push_back(Val);
6775 if (!OutChains.empty())
6776 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6781 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6782 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6783 MVT::Other, getRoot(),
6784 getValue(I.getArgOperand(0)),
6785 DAG.getSrcValue(I.getArgOperand(0))));
6788 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6789 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6790 const DataLayout &DL = *TLI.getDataLayout();
6791 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6792 getRoot(), getValue(I.getOperand(0)),
6793 DAG.getSrcValue(I.getOperand(0)),
6794 DL.getABITypeAlignment(I.getType()));
6796 DAG.setRoot(V.getValue(1));
6799 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6800 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6801 MVT::Other, getRoot(),
6802 getValue(I.getArgOperand(0)),
6803 DAG.getSrcValue(I.getArgOperand(0))));
6806 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6807 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6808 MVT::Other, getRoot(),
6809 getValue(I.getArgOperand(0)),
6810 getValue(I.getArgOperand(1)),
6811 DAG.getSrcValue(I.getArgOperand(0)),
6812 DAG.getSrcValue(I.getArgOperand(1))));
6815 /// \brief Lower an argument list according to the target calling convention.
6817 /// \return A tuple of <return-value, token-chain>
6819 /// This is a helper for lowering intrinsics that follow a target calling
6820 /// convention or require stack pointer adjustment. Only a subset of the
6821 /// intrinsic's operands need to participate in the calling convention.
6822 std::pair<SDValue, SDValue>
6823 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6824 unsigned NumArgs, SDValue Callee,
6826 TargetLowering::ArgListTy Args;
6827 Args.reserve(NumArgs);
6829 // Populate the argument list.
6830 // Attributes for args start at offset 1, after the return attribute.
6831 ImmutableCallSite CS(&CI);
6832 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6833 ArgI != ArgE; ++ArgI) {
6834 const Value *V = CI.getOperand(ArgI);
6836 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6838 TargetLowering::ArgListEntry Entry;
6839 Entry.Node = getValue(V);
6840 Entry.Ty = V->getType();
6841 Entry.setAttributes(&CS, AttrI);
6842 Args.push_back(Entry);
6845 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6846 TargetLowering::CallLoweringInfo CLI(DAG);
6847 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6848 .setCallee(CI.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6849 .setDiscardResult(!CI.use_empty());
6851 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6852 return TLI.LowerCallTo(CLI);
6855 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6856 /// or patchpoint target node's operand list.
6858 /// Constants are converted to TargetConstants purely as an optimization to
6859 /// avoid constant materialization and register allocation.
6861 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6862 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6863 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6864 /// address materialization and register allocation, but may also be required
6865 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6866 /// alloca in the entry block, then the runtime may assume that the alloca's
6867 /// StackMap location can be read immediately after compilation and that the
6868 /// location is valid at any point during execution (this is similar to the
6869 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6870 /// only available in a register, then the runtime would need to trap when
6871 /// execution reaches the StackMap in order to read the alloca's location.
6872 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6873 SmallVectorImpl<SDValue> &Ops,
6874 SelectionDAGBuilder &Builder) {
6875 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6876 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6877 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6879 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6881 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6882 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6883 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6885 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6887 Ops.push_back(OpVal);
6891 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6892 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6893 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6894 // [live variables...])
6896 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6898 SDValue Chain, InFlag, Callee, NullPtr;
6899 SmallVector<SDValue, 32> Ops;
6901 SDLoc DL = getCurSDLoc();
6902 Callee = getValue(CI.getCalledValue());
6903 NullPtr = DAG.getIntPtrConstant(0, true);
6905 // The stackmap intrinsic only records the live variables (the arguemnts
6906 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6907 // intrinsic, this won't be lowered to a function call. This means we don't
6908 // have to worry about calling conventions and target specific lowering code.
6909 // Instead we perform the call lowering right here.
6911 // chain, flag = CALLSEQ_START(chain, 0)
6912 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6913 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6915 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6916 InFlag = Chain.getValue(1);
6918 // Add the <id> and <numBytes> constants.
6919 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6920 Ops.push_back(DAG.getTargetConstant(
6921 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6922 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6923 Ops.push_back(DAG.getTargetConstant(
6924 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6926 // Push live variables for the stack map.
6927 addStackMapLiveVars(CI, 2, Ops, *this);
6929 // We are not pushing any register mask info here on the operands list,
6930 // because the stackmap doesn't clobber anything.
6932 // Push the chain and the glue flag.
6933 Ops.push_back(Chain);
6934 Ops.push_back(InFlag);
6936 // Create the STACKMAP node.
6937 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6938 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6939 Chain = SDValue(SM, 0);
6940 InFlag = Chain.getValue(1);
6942 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6944 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6946 // Set the root to the target-lowered call chain.
6949 // Inform the Frame Information that we have a stackmap in this function.
6950 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6953 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6954 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6955 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6960 // [live variables...])
6962 CallingConv::ID CC = CI.getCallingConv();
6963 bool isAnyRegCC = CC == CallingConv::AnyReg;
6964 bool hasDef = !CI.getType()->isVoidTy();
6965 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6967 // Get the real number of arguments participating in the call <numArgs>
6968 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6969 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6971 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6972 // Intrinsics include all meta-operands up to but not including CC.
6973 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6974 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6975 "Not enough arguments provided to the patchpoint intrinsic");
6977 // For AnyRegCC the arguments are lowered later on manually.
6978 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6979 std::pair<SDValue, SDValue> Result =
6980 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6982 // Set the root to the target-lowered call chain.
6983 SDValue Chain = Result.second;
6986 SDNode *CallEnd = Chain.getNode();
6987 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6988 CallEnd = CallEnd->getOperand(0).getNode();
6990 /// Get a call instruction from the call sequence chain.
6991 /// Tail calls are not allowed.
6992 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6993 "Expected a callseq node.");
6994 SDNode *Call = CallEnd->getOperand(0).getNode();
6995 bool hasGlue = Call->getGluedNode();
6997 // Replace the target specific call node with the patchable intrinsic.
6998 SmallVector<SDValue, 8> Ops;
7000 // Add the <id> and <numBytes> constants.
7001 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7002 Ops.push_back(DAG.getTargetConstant(
7003 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7004 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7005 Ops.push_back(DAG.getTargetConstant(
7006 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7008 // Assume that the Callee is a constant address.
7009 // FIXME: handle function symbols in the future.
7011 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7012 /*isTarget=*/true));
7014 // Adjust <numArgs> to account for any arguments that have been passed on the
7016 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7017 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7018 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7019 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7021 // Add the calling convention
7022 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7024 // Add the arguments we omitted previously. The register allocator should
7025 // place these in any free register.
7027 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7028 Ops.push_back(getValue(CI.getArgOperand(i)));
7030 // Push the arguments from the call instruction up to the register mask.
7031 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7032 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7035 // Push live variables for the stack map.
7036 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7038 // Push the register mask info.
7040 Ops.push_back(*(Call->op_end()-2));
7042 Ops.push_back(*(Call->op_end()-1));
7044 // Push the chain (this is originally the first operand of the call, but
7045 // becomes now the last or second to last operand).
7046 Ops.push_back(*(Call->op_begin()));
7048 // Push the glue flag (last operand).
7050 Ops.push_back(*(Call->op_end()-1));
7053 if (isAnyRegCC && hasDef) {
7054 // Create the return types based on the intrinsic definition
7055 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7056 SmallVector<EVT, 3> ValueVTs;
7057 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7058 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7060 // There is always a chain and a glue type at the end
7061 ValueVTs.push_back(MVT::Other);
7062 ValueVTs.push_back(MVT::Glue);
7063 NodeTys = DAG.getVTList(ValueVTs);
7065 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7067 // Replace the target specific call node with a PATCHPOINT node.
7068 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7069 getCurSDLoc(), NodeTys, Ops);
7071 // Update the NodeMap.
7074 setValue(&CI, SDValue(MN, 0));
7076 setValue(&CI, Result.first);
7079 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7080 // call sequence. Furthermore the location of the chain and glue can change
7081 // when the AnyReg calling convention is used and the intrinsic returns a
7083 if (isAnyRegCC && hasDef) {
7084 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7085 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7086 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7088 DAG.ReplaceAllUsesWith(Call, MN);
7089 DAG.DeleteNode(Call);
7091 // Inform the Frame Information that we have a patchpoint in this function.
7092 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7095 /// Returns an AttributeSet representing the attributes applied to the return
7096 /// value of the given call.
7097 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7098 SmallVector<Attribute::AttrKind, 2> Attrs;
7100 Attrs.push_back(Attribute::SExt);
7102 Attrs.push_back(Attribute::ZExt);
7104 Attrs.push_back(Attribute::InReg);
7106 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7110 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7111 /// implementation, which just calls LowerCall.
7112 /// FIXME: When all targets are
7113 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7114 std::pair<SDValue, SDValue>
7115 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7116 // Handle the incoming return values from the call.
7118 Type *OrigRetTy = CLI.RetTy;
7119 SmallVector<EVT, 4> RetTys;
7120 SmallVector<uint64_t, 4> Offsets;
7121 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7123 SmallVector<ISD::OutputArg, 4> Outs;
7124 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7126 bool CanLowerReturn =
7127 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7128 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7130 SDValue DemoteStackSlot;
7131 int DemoteStackIdx = -100;
7132 if (!CanLowerReturn) {
7133 // FIXME: equivalent assert?
7134 // assert(!CS.hasInAllocaArgument() &&
7135 // "sret demotion is incompatible with inalloca");
7136 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7137 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7138 MachineFunction &MF = CLI.DAG.getMachineFunction();
7139 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7140 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7142 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7144 Entry.Node = DemoteStackSlot;
7145 Entry.Ty = StackSlotPtrType;
7146 Entry.isSExt = false;
7147 Entry.isZExt = false;
7148 Entry.isInReg = false;
7149 Entry.isSRet = true;
7150 Entry.isNest = false;
7151 Entry.isByVal = false;
7152 Entry.isReturned = false;
7153 Entry.Alignment = Align;
7154 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7155 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7157 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7159 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7160 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7161 for (unsigned i = 0; i != NumRegs; ++i) {
7162 ISD::InputArg MyFlags;
7163 MyFlags.VT = RegisterVT;
7165 MyFlags.Used = CLI.IsReturnValueUsed;
7167 MyFlags.Flags.setSExt();
7169 MyFlags.Flags.setZExt();
7171 MyFlags.Flags.setInReg();
7172 CLI.Ins.push_back(MyFlags);
7177 // Handle all of the outgoing arguments.
7179 CLI.OutVals.clear();
7180 ArgListTy &Args = CLI.getArgs();
7181 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7182 SmallVector<EVT, 4> ValueVTs;
7183 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7184 Type *FinalType = Args[i].Ty;
7185 if (Args[i].isByVal)
7186 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7187 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7188 FinalType, CLI.CallConv, CLI.IsVarArg);
7189 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7191 EVT VT = ValueVTs[Value];
7192 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7193 SDValue Op = SDValue(Args[i].Node.getNode(),
7194 Args[i].Node.getResNo() + Value);
7195 ISD::ArgFlagsTy Flags;
7196 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7202 if (Args[i].isInReg)
7206 if (Args[i].isByVal)
7208 if (Args[i].isInAlloca) {
7209 Flags.setInAlloca();
7210 // Set the byval flag for CCAssignFn callbacks that don't know about
7211 // inalloca. This way we can know how many bytes we should've allocated
7212 // and how many bytes a callee cleanup function will pop. If we port
7213 // inalloca to more targets, we'll have to add custom inalloca handling
7214 // in the various CC lowering callbacks.
7217 if (Args[i].isByVal || Args[i].isInAlloca) {
7218 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7219 Type *ElementTy = Ty->getElementType();
7220 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7221 // For ByVal, alignment should come from FE. BE will guess if this
7222 // info is not there but there are cases it cannot get right.
7223 unsigned FrameAlign;
7224 if (Args[i].Alignment)
7225 FrameAlign = Args[i].Alignment;
7227 FrameAlign = getByValTypeAlignment(ElementTy);
7228 Flags.setByValAlign(FrameAlign);
7232 if (NeedsRegBlock) {
7233 Flags.setInConsecutiveRegs();
7234 if (Value == NumValues - 1)
7235 Flags.setInConsecutiveRegsLast();
7237 Flags.setOrigAlign(OriginalAlignment);
7239 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7240 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7241 SmallVector<SDValue, 4> Parts(NumParts);
7242 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7245 ExtendKind = ISD::SIGN_EXTEND;
7246 else if (Args[i].isZExt)
7247 ExtendKind = ISD::ZERO_EXTEND;
7249 // Conservatively only handle 'returned' on non-vectors for now
7250 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7251 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7252 "unexpected use of 'returned'");
7253 // Before passing 'returned' to the target lowering code, ensure that
7254 // either the register MVT and the actual EVT are the same size or that
7255 // the return value and argument are extended in the same way; in these
7256 // cases it's safe to pass the argument register value unchanged as the
7257 // return register value (although it's at the target's option whether
7259 // TODO: allow code generation to take advantage of partially preserved
7260 // registers rather than clobbering the entire register when the
7261 // parameter extension method is not compatible with the return
7263 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7264 (ExtendKind != ISD::ANY_EXTEND &&
7265 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7266 Flags.setReturned();
7269 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7270 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7272 for (unsigned j = 0; j != NumParts; ++j) {
7273 // if it isn't first piece, alignment must be 1
7274 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7275 i < CLI.NumFixedArgs,
7276 i, j*Parts[j].getValueType().getStoreSize());
7277 if (NumParts > 1 && j == 0)
7278 MyFlags.Flags.setSplit();
7280 MyFlags.Flags.setOrigAlign(1);
7282 CLI.Outs.push_back(MyFlags);
7283 CLI.OutVals.push_back(Parts[j]);
7288 SmallVector<SDValue, 4> InVals;
7289 CLI.Chain = LowerCall(CLI, InVals);
7291 // Verify that the target's LowerCall behaved as expected.
7292 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7293 "LowerCall didn't return a valid chain!");
7294 assert((!CLI.IsTailCall || InVals.empty()) &&
7295 "LowerCall emitted a return value for a tail call!");
7296 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7297 "LowerCall didn't emit the correct number of values!");
7299 // For a tail call, the return value is merely live-out and there aren't
7300 // any nodes in the DAG representing it. Return a special value to
7301 // indicate that a tail call has been emitted and no more Instructions
7302 // should be processed in the current block.
7303 if (CLI.IsTailCall) {
7304 CLI.DAG.setRoot(CLI.Chain);
7305 return std::make_pair(SDValue(), SDValue());
7308 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7309 assert(InVals[i].getNode() &&
7310 "LowerCall emitted a null value!");
7311 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7312 "LowerCall emitted a value with the wrong type!");
7315 SmallVector<SDValue, 4> ReturnValues;
7316 if (!CanLowerReturn) {
7317 // The instruction result is the result of loading from the
7318 // hidden sret parameter.
7319 SmallVector<EVT, 1> PVTs;
7320 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7322 ComputeValueVTs(*this, PtrRetTy, PVTs);
7323 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7324 EVT PtrVT = PVTs[0];
7326 unsigned NumValues = RetTys.size();
7327 ReturnValues.resize(NumValues);
7328 SmallVector<SDValue, 4> Chains(NumValues);
7330 for (unsigned i = 0; i < NumValues; ++i) {
7331 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7332 CLI.DAG.getConstant(Offsets[i], PtrVT));
7333 SDValue L = CLI.DAG.getLoad(
7334 RetTys[i], CLI.DL, CLI.Chain, Add,
7335 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7337 ReturnValues[i] = L;
7338 Chains[i] = L.getValue(1);
7341 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7343 // Collect the legal value parts into potentially illegal values
7344 // that correspond to the original function's return values.
7345 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7347 AssertOp = ISD::AssertSext;
7348 else if (CLI.RetZExt)
7349 AssertOp = ISD::AssertZext;
7350 unsigned CurReg = 0;
7351 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7353 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7354 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7356 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7357 NumRegs, RegisterVT, VT, nullptr,
7362 // For a function returning void, there is no return value. We can't create
7363 // such a node, so we just return a null return value in that case. In
7364 // that case, nothing will actually look at the value.
7365 if (ReturnValues.empty())
7366 return std::make_pair(SDValue(), CLI.Chain);
7369 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7370 CLI.DAG.getVTList(RetTys), ReturnValues);
7371 return std::make_pair(Res, CLI.Chain);
7374 void TargetLowering::LowerOperationWrapper(SDNode *N,
7375 SmallVectorImpl<SDValue> &Results,
7376 SelectionDAG &DAG) const {
7377 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7379 Results.push_back(Res);
7382 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7383 llvm_unreachable("LowerOperation not implemented for this target!");
7387 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7388 SDValue Op = getNonRegisterValue(V);
7389 assert((Op.getOpcode() != ISD::CopyFromReg ||
7390 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7391 "Copy from a reg to the same reg!");
7392 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7394 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7395 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7396 SDValue Chain = DAG.getEntryNode();
7398 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7399 FuncInfo.PreferredExtendType.end())
7401 : FuncInfo.PreferredExtendType[V];
7402 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7403 PendingExports.push_back(Chain);
7406 #include "llvm/CodeGen/SelectionDAGISel.h"
7408 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7409 /// entry block, return true. This includes arguments used by switches, since
7410 /// the switch may expand into multiple basic blocks.
7411 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7412 // With FastISel active, we may be splitting blocks, so force creation
7413 // of virtual registers for all non-dead arguments.
7415 return A->use_empty();
7417 const BasicBlock *Entry = A->getParent()->begin();
7418 for (const User *U : A->users())
7419 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7420 return false; // Use not in entry block.
7425 void SelectionDAGISel::LowerArguments(const Function &F) {
7426 SelectionDAG &DAG = SDB->DAG;
7427 SDLoc dl = SDB->getCurSDLoc();
7428 const DataLayout *DL = TLI->getDataLayout();
7429 SmallVector<ISD::InputArg, 16> Ins;
7431 if (!FuncInfo->CanLowerReturn) {
7432 // Put in an sret pointer parameter before all the other parameters.
7433 SmallVector<EVT, 1> ValueVTs;
7434 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7436 // NOTE: Assuming that a pointer will never break down to more than one VT
7438 ISD::ArgFlagsTy Flags;
7440 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7441 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7442 Ins.push_back(RetArg);
7445 // Set up the incoming argument description vector.
7447 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7448 I != E; ++I, ++Idx) {
7449 SmallVector<EVT, 4> ValueVTs;
7450 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7451 bool isArgValueUsed = !I->use_empty();
7452 unsigned PartBase = 0;
7453 Type *FinalType = I->getType();
7454 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7455 FinalType = cast<PointerType>(FinalType)->getElementType();
7456 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7457 FinalType, F.getCallingConv(), F.isVarArg());
7458 for (unsigned Value = 0, NumValues = ValueVTs.size();
7459 Value != NumValues; ++Value) {
7460 EVT VT = ValueVTs[Value];
7461 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7462 ISD::ArgFlagsTy Flags;
7463 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7465 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7467 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7469 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7471 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7473 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7475 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7476 Flags.setInAlloca();
7477 // Set the byval flag for CCAssignFn callbacks that don't know about
7478 // inalloca. This way we can know how many bytes we should've allocated
7479 // and how many bytes a callee cleanup function will pop. If we port
7480 // inalloca to more targets, we'll have to add custom inalloca handling
7481 // in the various CC lowering callbacks.
7484 if (Flags.isByVal() || Flags.isInAlloca()) {
7485 PointerType *Ty = cast<PointerType>(I->getType());
7486 Type *ElementTy = Ty->getElementType();
7487 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7488 // For ByVal, alignment should be passed from FE. BE will guess if
7489 // this info is not there but there are cases it cannot get right.
7490 unsigned FrameAlign;
7491 if (F.getParamAlignment(Idx))
7492 FrameAlign = F.getParamAlignment(Idx);
7494 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7495 Flags.setByValAlign(FrameAlign);
7497 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7499 if (NeedsRegBlock) {
7500 Flags.setInConsecutiveRegs();
7501 if (Value == NumValues - 1)
7502 Flags.setInConsecutiveRegsLast();
7504 Flags.setOrigAlign(OriginalAlignment);
7506 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7507 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7508 for (unsigned i = 0; i != NumRegs; ++i) {
7509 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7510 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7511 if (NumRegs > 1 && i == 0)
7512 MyFlags.Flags.setSplit();
7513 // if it isn't first piece, alignment must be 1
7515 MyFlags.Flags.setOrigAlign(1);
7516 Ins.push_back(MyFlags);
7518 PartBase += VT.getStoreSize();
7522 // Call the target to set up the argument values.
7523 SmallVector<SDValue, 8> InVals;
7524 SDValue NewRoot = TLI->LowerFormalArguments(
7525 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7527 // Verify that the target's LowerFormalArguments behaved as expected.
7528 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7529 "LowerFormalArguments didn't return a valid chain!");
7530 assert(InVals.size() == Ins.size() &&
7531 "LowerFormalArguments didn't emit the correct number of values!");
7533 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7534 assert(InVals[i].getNode() &&
7535 "LowerFormalArguments emitted a null value!");
7536 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7537 "LowerFormalArguments emitted a value with the wrong type!");
7541 // Update the DAG with the new chain value resulting from argument lowering.
7542 DAG.setRoot(NewRoot);
7544 // Set up the argument values.
7547 if (!FuncInfo->CanLowerReturn) {
7548 // Create a virtual register for the sret pointer, and put in a copy
7549 // from the sret argument into it.
7550 SmallVector<EVT, 1> ValueVTs;
7551 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7552 MVT VT = ValueVTs[0].getSimpleVT();
7553 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7554 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7555 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7556 RegVT, VT, nullptr, AssertOp);
7558 MachineFunction& MF = SDB->DAG.getMachineFunction();
7559 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7560 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7561 FuncInfo->DemoteRegister = SRetReg;
7563 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7564 DAG.setRoot(NewRoot);
7566 // i indexes lowered arguments. Bump it past the hidden sret argument.
7567 // Idx indexes LLVM arguments. Don't touch it.
7571 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7573 SmallVector<SDValue, 4> ArgValues;
7574 SmallVector<EVT, 4> ValueVTs;
7575 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7576 unsigned NumValues = ValueVTs.size();
7578 // If this argument is unused then remember its value. It is used to generate
7579 // debugging information.
7580 if (I->use_empty() && NumValues) {
7581 SDB->setUnusedArgValue(I, InVals[i]);
7583 // Also remember any frame index for use in FastISel.
7584 if (FrameIndexSDNode *FI =
7585 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7586 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7589 for (unsigned Val = 0; Val != NumValues; ++Val) {
7590 EVT VT = ValueVTs[Val];
7591 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7592 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7594 if (!I->use_empty()) {
7595 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7596 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7597 AssertOp = ISD::AssertSext;
7598 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7599 AssertOp = ISD::AssertZext;
7601 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7602 NumParts, PartVT, VT,
7603 nullptr, AssertOp));
7609 // We don't need to do anything else for unused arguments.
7610 if (ArgValues.empty())
7613 // Note down frame index.
7614 if (FrameIndexSDNode *FI =
7615 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7616 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7618 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7619 SDB->getCurSDLoc());
7621 SDB->setValue(I, Res);
7622 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7623 if (LoadSDNode *LNode =
7624 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7625 if (FrameIndexSDNode *FI =
7626 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7627 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7630 // If this argument is live outside of the entry block, insert a copy from
7631 // wherever we got it to the vreg that other BB's will reference it as.
7632 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7633 // If we can, though, try to skip creating an unnecessary vreg.
7634 // FIXME: This isn't very clean... it would be nice to make this more
7635 // general. It's also subtly incompatible with the hacks FastISel
7637 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7638 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7639 FuncInfo->ValueMap[I] = Reg;
7643 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7644 FuncInfo->InitializeRegForValue(I);
7645 SDB->CopyToExportRegsIfNeeded(I);
7649 assert(i == InVals.size() && "Argument register count mismatch!");
7651 // Finally, if the target has anything special to do, allow it to do so.
7652 // FIXME: this should insert code into the DAG!
7653 EmitFunctionEntryCode();
7656 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7657 /// ensure constants are generated when needed. Remember the virtual registers
7658 /// that need to be added to the Machine PHI nodes as input. We cannot just
7659 /// directly add them, because expansion might result in multiple MBB's for one
7660 /// BB. As such, the start of the BB might correspond to a different MBB than
7664 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7665 const TerminatorInst *TI = LLVMBB->getTerminator();
7667 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7669 // Check successor nodes' PHI nodes that expect a constant to be available
7671 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7672 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7673 if (!isa<PHINode>(SuccBB->begin())) continue;
7674 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7676 // If this terminator has multiple identical successors (common for
7677 // switches), only handle each succ once.
7678 if (!SuccsHandled.insert(SuccMBB)) continue;
7680 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7682 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7683 // nodes and Machine PHI nodes, but the incoming operands have not been
7685 for (BasicBlock::const_iterator I = SuccBB->begin();
7686 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7687 // Ignore dead phi's.
7688 if (PN->use_empty()) continue;
7691 if (PN->getType()->isEmptyTy())
7695 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7697 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7698 unsigned &RegOut = ConstantsOut[C];
7700 RegOut = FuncInfo.CreateRegs(C->getType());
7701 CopyValueToVirtualRegister(C, RegOut);
7705 DenseMap<const Value *, unsigned>::iterator I =
7706 FuncInfo.ValueMap.find(PHIOp);
7707 if (I != FuncInfo.ValueMap.end())
7710 assert(isa<AllocaInst>(PHIOp) &&
7711 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7712 "Didn't codegen value into a register!??");
7713 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7714 CopyValueToVirtualRegister(PHIOp, Reg);
7718 // Remember that this register needs to added to the machine PHI node as
7719 // the input for this MBB.
7720 SmallVector<EVT, 4> ValueVTs;
7721 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7722 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7723 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7724 EVT VT = ValueVTs[vti];
7725 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7726 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7727 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7728 Reg += NumRegisters;
7733 ConstantsOut.clear();
7736 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7739 SelectionDAGBuilder::StackProtectorDescriptor::
7740 AddSuccessorMBB(const BasicBlock *BB,
7741 MachineBasicBlock *ParentMBB,
7742 MachineBasicBlock *SuccMBB) {
7743 // If SuccBB has not been created yet, create it.
7745 MachineFunction *MF = ParentMBB->getParent();
7746 MachineFunction::iterator BBI = ParentMBB;
7747 SuccMBB = MF->CreateMachineBasicBlock(BB);
7748 MF->insert(++BBI, SuccMBB);
7750 // Add it as a successor of ParentMBB.
7751 ParentMBB->addSuccessor(SuccMBB);