1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/PseudoSourceValue.h"
45 #include "llvm/CodeGen/SelectionDAG.h"
46 #include "llvm/Analysis/DebugInfo.h"
47 #include "llvm/Target/TargetData.h"
48 #include "llvm/Target/TargetFrameLowering.h"
49 #include "llvm/Target/TargetInstrInfo.h"
50 #include "llvm/Target/TargetIntrinsicInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/Compiler.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static cl::opt<unsigned>
88 MaxParallelChains("dag-chain-limit", cl::desc("Max parallel isel dag chains"),
89 cl::init(64), cl::Hidden);
91 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
92 const SDValue *Parts, unsigned NumParts,
93 EVT PartVT, EVT ValueVT);
95 /// getCopyFromParts - Create a value that contains the specified legal parts
96 /// combined into the value they represent. If the parts combine to a type
97 /// larger then ValueVT then AssertOp can be used to specify whether the extra
98 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
99 /// (ISD::AssertSext).
100 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
101 const SDValue *Parts,
102 unsigned NumParts, EVT PartVT, EVT ValueVT,
103 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
104 if (ValueVT.isVector())
105 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
107 assert(NumParts > 0 && "No parts to assemble!");
108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
109 SDValue Val = Parts[0];
112 // Assemble the value from multiple parts.
113 if (ValueVT.isInteger()) {
114 unsigned PartBits = PartVT.getSizeInBits();
115 unsigned ValueBits = ValueVT.getSizeInBits();
117 // Assemble the power of 2 part.
118 unsigned RoundParts = NumParts & (NumParts - 1) ?
119 1 << Log2_32(NumParts) : NumParts;
120 unsigned RoundBits = PartBits * RoundParts;
121 EVT RoundVT = RoundBits == ValueBits ?
122 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
125 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
127 if (RoundParts > 2) {
128 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
130 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
131 RoundParts / 2, PartVT, HalfVT);
133 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
134 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
137 if (TLI.isBigEndian())
140 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
142 if (RoundParts < NumParts) {
143 // Assemble the trailing non-power-of-2 part.
144 unsigned OddParts = NumParts - RoundParts;
145 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
146 Hi = getCopyFromParts(DAG, DL,
147 Parts + RoundParts, OddParts, PartVT, OddVT);
149 // Combine the round and odd parts.
151 if (TLI.isBigEndian())
153 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
154 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
155 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
156 DAG.getConstant(Lo.getValueType().getSizeInBits(),
157 TLI.getPointerTy()));
158 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
159 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
161 } else if (PartVT.isFloatingPoint()) {
162 // FP split into multiple FP parts (for ppcf128)
163 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
166 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
167 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
168 if (TLI.isBigEndian())
170 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
172 // FP split into integer parts (soft fp)
173 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
174 !PartVT.isVector() && "Unexpected split");
175 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
176 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
180 // There is now one part, held in Val. Correct it to match ValueVT.
181 PartVT = Val.getValueType();
183 if (PartVT == ValueVT)
186 if (PartVT.isInteger() && ValueVT.isInteger()) {
187 if (ValueVT.bitsLT(PartVT)) {
188 // For a truncate, see if we have any information to
189 // indicate whether the truncated bits will always be
190 // zero or sign-extension.
191 if (AssertOp != ISD::DELETED_NODE)
192 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
193 DAG.getValueType(ValueVT));
194 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
196 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
199 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
200 // FP_ROUND's are always exact here.
201 if (ValueVT.bitsLT(Val.getValueType()))
202 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
203 DAG.getIntPtrConstant(1));
205 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
208 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
209 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
211 llvm_unreachable("Unknown mismatch!");
215 /// getCopyFromParts - Create a value that contains the specified legal parts
216 /// combined into the value they represent. If the parts combine to a type
217 /// larger then ValueVT then AssertOp can be used to specify whether the extra
218 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
219 /// (ISD::AssertSext).
220 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
221 const SDValue *Parts, unsigned NumParts,
222 EVT PartVT, EVT ValueVT) {
223 assert(ValueVT.isVector() && "Not a vector value");
224 assert(NumParts > 0 && "No parts to assemble!");
225 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
226 SDValue Val = Parts[0];
228 // Handle a multi-element vector.
230 EVT IntermediateVT, RegisterVT;
231 unsigned NumIntermediates;
233 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
234 NumIntermediates, RegisterVT);
235 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
236 NumParts = NumRegs; // Silence a compiler warning.
237 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
238 assert(RegisterVT == Parts[0].getValueType() &&
239 "Part type doesn't match part!");
241 // Assemble the parts into intermediate operands.
242 SmallVector<SDValue, 8> Ops(NumIntermediates);
243 if (NumIntermediates == NumParts) {
244 // If the register was not expanded, truncate or copy the value,
246 for (unsigned i = 0; i != NumParts; ++i)
247 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
248 PartVT, IntermediateVT);
249 } else if (NumParts > 0) {
250 // If the intermediate type was expanded, build the intermediate
251 // operands from the parts.
252 assert(NumParts % NumIntermediates == 0 &&
253 "Must expand into a divisible number of parts!");
254 unsigned Factor = NumParts / NumIntermediates;
255 for (unsigned i = 0; i != NumIntermediates; ++i)
256 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
257 PartVT, IntermediateVT);
260 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
261 // intermediate operands.
262 Val = DAG.getNode(IntermediateVT.isVector() ?
263 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
264 ValueVT, &Ops[0], NumIntermediates);
267 // There is now one part, held in Val. Correct it to match ValueVT.
268 PartVT = Val.getValueType();
270 if (PartVT == ValueVT)
273 if (PartVT.isVector()) {
274 // If the element type of the source/dest vectors are the same, but the
275 // parts vector has more elements than the value vector, then we have a
276 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
278 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
279 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
280 "Cannot narrow, it would be a lossy transformation");
281 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
282 DAG.getIntPtrConstant(0));
285 // Vector/Vector bitcast.
286 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
289 assert(ValueVT.getVectorElementType() == PartVT &&
290 ValueVT.getVectorNumElements() == 1 &&
291 "Only trivial scalar-to-vector conversions should get here!");
292 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
298 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
299 SDValue Val, SDValue *Parts, unsigned NumParts,
302 /// getCopyToParts - Create a series of nodes that contain the specified value
303 /// split into legal parts. If the parts contain more bits than Val, then, for
304 /// integers, ExtendKind can be used to specify how to generate the extra bits.
305 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
306 SDValue Val, SDValue *Parts, unsigned NumParts,
308 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
309 EVT ValueVT = Val.getValueType();
311 // Handle the vector case separately.
312 if (ValueVT.isVector())
313 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
315 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
316 unsigned PartBits = PartVT.getSizeInBits();
317 unsigned OrigNumParts = NumParts;
318 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
323 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
324 if (PartVT == ValueVT) {
325 assert(NumParts == 1 && "No-op copy with multiple parts!");
330 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
331 // If the parts cover more bits than the value has, promote the value.
332 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
333 assert(NumParts == 1 && "Do not know what to promote to!");
334 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
336 assert(PartVT.isInteger() && ValueVT.isInteger() &&
337 "Unknown mismatch!");
338 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
339 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
341 } else if (PartBits == ValueVT.getSizeInBits()) {
342 // Different types of the same size.
343 assert(NumParts == 1 && PartVT != ValueVT);
344 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
345 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
346 // If the parts cover less bits than value has, truncate the value.
347 assert(PartVT.isInteger() && ValueVT.isInteger() &&
348 "Unknown mismatch!");
349 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
350 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
353 // The value may have changed - recompute ValueVT.
354 ValueVT = Val.getValueType();
355 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
356 "Failed to tile the value with PartVT!");
359 assert(PartVT == ValueVT && "Type conversion failed!");
364 // Expand the value into multiple parts.
365 if (NumParts & (NumParts - 1)) {
366 // The number of parts is not a power of 2. Split off and copy the tail.
367 assert(PartVT.isInteger() && ValueVT.isInteger() &&
368 "Do not know what to expand to!");
369 unsigned RoundParts = 1 << Log2_32(NumParts);
370 unsigned RoundBits = RoundParts * PartBits;
371 unsigned OddParts = NumParts - RoundParts;
372 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
373 DAG.getIntPtrConstant(RoundBits));
374 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
376 if (TLI.isBigEndian())
377 // The odd parts were reversed by getCopyToParts - unreverse them.
378 std::reverse(Parts + RoundParts, Parts + NumParts);
380 NumParts = RoundParts;
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
385 // The number of parts is a power of 2. Repeatedly bisect the value using
387 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
388 EVT::getIntegerVT(*DAG.getContext(),
389 ValueVT.getSizeInBits()),
392 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
393 for (unsigned i = 0; i < NumParts; i += StepSize) {
394 unsigned ThisBits = StepSize * PartBits / 2;
395 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
396 SDValue &Part0 = Parts[i];
397 SDValue &Part1 = Parts[i+StepSize/2];
399 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
400 ThisVT, Part0, DAG.getIntPtrConstant(1));
401 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
402 ThisVT, Part0, DAG.getIntPtrConstant(0));
404 if (ThisBits == PartBits && ThisVT != PartVT) {
405 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
406 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
411 if (TLI.isBigEndian())
412 std::reverse(Parts, Parts + OrigNumParts);
416 /// getCopyToPartsVector - Create a series of nodes that contain the specified
417 /// value split into legal parts.
418 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
419 SDValue Val, SDValue *Parts, unsigned NumParts,
421 EVT ValueVT = Val.getValueType();
422 assert(ValueVT.isVector() && "Not a vector");
423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
426 if (PartVT == ValueVT) {
428 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
429 // Bitconvert vector->vector case.
430 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
431 } else if (PartVT.isVector() &&
432 PartVT.getVectorElementType() == ValueVT.getVectorElementType()&&
433 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
434 EVT ElementVT = PartVT.getVectorElementType();
435 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
437 SmallVector<SDValue, 16> Ops;
438 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
439 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
440 ElementVT, Val, DAG.getIntPtrConstant(i)));
442 for (unsigned i = ValueVT.getVectorNumElements(),
443 e = PartVT.getVectorNumElements(); i != e; ++i)
444 Ops.push_back(DAG.getUNDEF(ElementVT));
446 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
448 // FIXME: Use CONCAT for 2x -> 4x.
450 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
451 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
453 // Vector -> scalar conversion.
454 assert(ValueVT.getVectorElementType() == PartVT &&
455 ValueVT.getVectorNumElements() == 1 &&
456 "Only trivial vector-to-scalar conversions should get here!");
457 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
458 PartVT, Val, DAG.getIntPtrConstant(0));
465 // Handle a multi-element vector.
466 EVT IntermediateVT, RegisterVT;
467 unsigned NumIntermediates;
468 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
470 NumIntermediates, RegisterVT);
471 unsigned NumElements = ValueVT.getVectorNumElements();
473 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
474 NumParts = NumRegs; // Silence a compiler warning.
475 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
477 // Split the vector into intermediate operands.
478 SmallVector<SDValue, 8> Ops(NumIntermediates);
479 for (unsigned i = 0; i != NumIntermediates; ++i) {
480 if (IntermediateVT.isVector())
481 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
483 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
485 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
486 IntermediateVT, Val, DAG.getIntPtrConstant(i));
489 // Split the intermediate operands into legal parts.
490 if (NumParts == NumIntermediates) {
491 // If the register was not expanded, promote or copy the value,
493 for (unsigned i = 0; i != NumParts; ++i)
494 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
495 } else if (NumParts > 0) {
496 // If the intermediate type was expanded, split each the value into
498 assert(NumParts % NumIntermediates == 0 &&
499 "Must expand into a divisible number of parts!");
500 unsigned Factor = NumParts / NumIntermediates;
501 for (unsigned i = 0; i != NumIntermediates; ++i)
502 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
510 /// RegsForValue - This struct represents the registers (physical or virtual)
511 /// that a particular set of values is assigned, and the type information
512 /// about the value. The most common situation is to represent one value at a
513 /// time, but struct or array values are handled element-wise as multiple
514 /// values. The splitting of aggregates is performed recursively, so that we
515 /// never have aggregate-typed registers. The values at this point do not
516 /// necessarily have legal types, so each value may require one or more
517 /// registers of some legal type.
519 struct RegsForValue {
520 /// ValueVTs - The value types of the values, which may not be legal, and
521 /// may need be promoted or synthesized from one or more registers.
523 SmallVector<EVT, 4> ValueVTs;
525 /// RegVTs - The value types of the registers. This is the same size as
526 /// ValueVTs and it records, for each value, what the type of the assigned
527 /// register or registers are. (Individual values are never synthesized
528 /// from more than one type of register.)
530 /// With virtual registers, the contents of RegVTs is redundant with TLI's
531 /// getRegisterType member function, however when with physical registers
532 /// it is necessary to have a separate record of the types.
534 SmallVector<EVT, 4> RegVTs;
536 /// Regs - This list holds the registers assigned to the values.
537 /// Each legal or promoted value requires one register, and each
538 /// expanded value requires multiple registers.
540 SmallVector<unsigned, 4> Regs;
544 RegsForValue(const SmallVector<unsigned, 4> ®s,
545 EVT regvt, EVT valuevt)
546 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
548 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
549 unsigned Reg, const Type *Ty) {
550 ComputeValueVTs(tli, Ty, ValueVTs);
552 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
553 EVT ValueVT = ValueVTs[Value];
554 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
555 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
556 for (unsigned i = 0; i != NumRegs; ++i)
557 Regs.push_back(Reg + i);
558 RegVTs.push_back(RegisterVT);
563 /// areValueTypesLegal - Return true if types of all the values are legal.
564 bool areValueTypesLegal(const TargetLowering &TLI) {
565 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
566 EVT RegisterVT = RegVTs[Value];
567 if (!TLI.isTypeLegal(RegisterVT))
573 /// append - Add the specified values to this one.
574 void append(const RegsForValue &RHS) {
575 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
576 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
577 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
580 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
581 /// this value and returns the result as a ValueVTs value. This uses
582 /// Chain/Flag as the input and updates them for the output Chain/Flag.
583 /// If the Flag pointer is NULL, no flag is used.
584 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
586 SDValue &Chain, SDValue *Flag) const;
588 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
589 /// specified value into the registers specified by this object. This uses
590 /// Chain/Flag as the input and updates them for the output Chain/Flag.
591 /// If the Flag pointer is NULL, no flag is used.
592 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
593 SDValue &Chain, SDValue *Flag) const;
595 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
596 /// operand list. This adds the code marker, matching input operand index
597 /// (if applicable), and includes the number of values added into it.
598 void AddInlineAsmOperands(unsigned Kind,
599 bool HasMatching, unsigned MatchingIdx,
601 std::vector<SDValue> &Ops) const;
605 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
606 /// this value and returns the result as a ValueVT value. This uses
607 /// Chain/Flag as the input and updates them for the output Chain/Flag.
608 /// If the Flag pointer is NULL, no flag is used.
609 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
610 FunctionLoweringInfo &FuncInfo,
612 SDValue &Chain, SDValue *Flag) const {
613 // A Value with type {} or [0 x %t] needs no registers.
614 if (ValueVTs.empty())
617 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
619 // Assemble the legal parts into the final values.
620 SmallVector<SDValue, 4> Values(ValueVTs.size());
621 SmallVector<SDValue, 8> Parts;
622 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
623 // Copy the legal parts from the registers.
624 EVT ValueVT = ValueVTs[Value];
625 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
626 EVT RegisterVT = RegVTs[Value];
628 Parts.resize(NumRegs);
629 for (unsigned i = 0; i != NumRegs; ++i) {
632 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
634 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
635 *Flag = P.getValue(2);
638 Chain = P.getValue(1);
641 // If the source register was virtual and if we know something about it,
642 // add an assert node.
643 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
644 !RegisterVT.isInteger() || RegisterVT.isVector())
647 const FunctionLoweringInfo::LiveOutInfo *LOI =
648 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
652 unsigned RegSize = RegisterVT.getSizeInBits();
653 unsigned NumSignBits = LOI->NumSignBits;
654 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
656 // FIXME: We capture more information than the dag can represent. For
657 // now, just use the tightest assertzext/assertsext possible.
659 EVT FromVT(MVT::Other);
660 if (NumSignBits == RegSize)
661 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
662 else if (NumZeroBits >= RegSize-1)
663 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
664 else if (NumSignBits > RegSize-8)
665 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
666 else if (NumZeroBits >= RegSize-8)
667 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
668 else if (NumSignBits > RegSize-16)
669 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
670 else if (NumZeroBits >= RegSize-16)
671 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
672 else if (NumSignBits > RegSize-32)
673 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
674 else if (NumZeroBits >= RegSize-32)
675 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
679 // Add an assertion node.
680 assert(FromVT != MVT::Other);
681 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
682 RegisterVT, P, DAG.getValueType(FromVT));
685 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
686 NumRegs, RegisterVT, ValueVT);
691 return DAG.getNode(ISD::MERGE_VALUES, dl,
692 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
693 &Values[0], ValueVTs.size());
696 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
697 /// specified value into the registers specified by this object. This uses
698 /// Chain/Flag as the input and updates them for the output Chain/Flag.
699 /// If the Flag pointer is NULL, no flag is used.
700 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
701 SDValue &Chain, SDValue *Flag) const {
702 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
704 // Get the list of the values's legal parts.
705 unsigned NumRegs = Regs.size();
706 SmallVector<SDValue, 8> Parts(NumRegs);
707 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
708 EVT ValueVT = ValueVTs[Value];
709 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
710 EVT RegisterVT = RegVTs[Value];
712 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
713 &Parts[Part], NumParts, RegisterVT);
717 // Copy the parts into the registers.
718 SmallVector<SDValue, 8> Chains(NumRegs);
719 for (unsigned i = 0; i != NumRegs; ++i) {
722 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
724 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
725 *Flag = Part.getValue(1);
728 Chains[i] = Part.getValue(0);
731 if (NumRegs == 1 || Flag)
732 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
733 // flagged to it. That is the CopyToReg nodes and the user are considered
734 // a single scheduling unit. If we create a TokenFactor and return it as
735 // chain, then the TokenFactor is both a predecessor (operand) of the
736 // user as well as a successor (the TF operands are flagged to the user).
737 // c1, f1 = CopyToReg
738 // c2, f2 = CopyToReg
739 // c3 = TokenFactor c1, c2
742 Chain = Chains[NumRegs-1];
744 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
747 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
748 /// operand list. This adds the code marker and includes the number of
749 /// values added into it.
750 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
751 unsigned MatchingIdx,
753 std::vector<SDValue> &Ops) const {
754 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
756 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
758 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
759 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
762 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
763 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
764 EVT RegisterVT = RegVTs[Value];
765 for (unsigned i = 0; i != NumRegs; ++i) {
766 assert(Reg < Regs.size() && "Mismatch in # registers expected");
767 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
772 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) {
775 TD = DAG.getTarget().getTargetData();
778 /// clear - Clear out the current SelectionDAG and the associated
779 /// state and prepare this SelectionDAGBuilder object to be used
780 /// for a new block. This doesn't clear out information about
781 /// additional blocks that are needed to complete switch lowering
782 /// or PHI node updating; that information is cleared out as it is
784 void SelectionDAGBuilder::clear() {
786 UnusedArgNodeMap.clear();
787 PendingLoads.clear();
788 PendingExports.clear();
789 DanglingDebugInfoMap.clear();
790 CurDebugLoc = DebugLoc();
794 /// getRoot - Return the current virtual root of the Selection DAG,
795 /// flushing any PendingLoad items. This must be done before emitting
796 /// a store or any other node that may need to be ordered after any
797 /// prior load instructions.
799 SDValue SelectionDAGBuilder::getRoot() {
800 if (PendingLoads.empty())
801 return DAG.getRoot();
803 if (PendingLoads.size() == 1) {
804 SDValue Root = PendingLoads[0];
806 PendingLoads.clear();
810 // Otherwise, we have to make a token factor node.
811 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
812 &PendingLoads[0], PendingLoads.size());
813 PendingLoads.clear();
818 /// getControlRoot - Similar to getRoot, but instead of flushing all the
819 /// PendingLoad items, flush all the PendingExports items. It is necessary
820 /// to do this before emitting a terminator instruction.
822 SDValue SelectionDAGBuilder::getControlRoot() {
823 SDValue Root = DAG.getRoot();
825 if (PendingExports.empty())
828 // Turn all of the CopyToReg chains into one factored node.
829 if (Root.getOpcode() != ISD::EntryToken) {
830 unsigned i = 0, e = PendingExports.size();
831 for (; i != e; ++i) {
832 assert(PendingExports[i].getNode()->getNumOperands() > 1);
833 if (PendingExports[i].getNode()->getOperand(0) == Root)
834 break; // Don't add the root if we already indirectly depend on it.
838 PendingExports.push_back(Root);
841 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
843 PendingExports.size());
844 PendingExports.clear();
849 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
850 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
851 DAG.AssignOrdering(Node, SDNodeOrder);
853 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
854 AssignOrderingToNode(Node->getOperand(I).getNode());
857 void SelectionDAGBuilder::visit(const Instruction &I) {
858 // Set up outgoing PHI node register values before emitting the terminator.
859 if (isa<TerminatorInst>(&I))
860 HandlePHINodesInSuccessorBlocks(I.getParent());
862 CurDebugLoc = I.getDebugLoc();
864 visit(I.getOpcode(), I);
866 if (!isa<TerminatorInst>(&I) && !HasTailCall)
867 CopyToExportRegsIfNeeded(&I);
869 CurDebugLoc = DebugLoc();
872 void SelectionDAGBuilder::visitPHI(const PHINode &) {
873 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
876 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
877 // Note: this doesn't use InstVisitor, because it has to work with
878 // ConstantExpr's in addition to instructions.
880 default: llvm_unreachable("Unknown instruction type encountered!");
881 // Build the switch statement using the Instruction.def file.
882 #define HANDLE_INST(NUM, OPCODE, CLASS) \
883 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
884 #include "llvm/Instruction.def"
887 // Assign the ordering to the freshly created DAG nodes.
888 if (NodeMap.count(&I)) {
890 AssignOrderingToNode(getValue(&I).getNode());
894 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
895 // generate the debug data structures now that we've seen its definition.
896 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
898 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
900 const DbgValueInst *DI = DDI.getDI();
901 DebugLoc dl = DDI.getdl();
902 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
903 MDNode *Variable = DI->getVariable();
904 uint64_t Offset = DI->getOffset();
907 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
908 SDV = DAG.getDbgValue(Variable, Val.getNode(),
909 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
910 DAG.AddDbgValue(SDV, Val.getNode(), false);
913 DEBUG(dbgs() << "Dropping debug info for " << DI);
914 DanglingDebugInfoMap[V] = DanglingDebugInfo();
918 // getValue - Return an SDValue for the given Value.
919 SDValue SelectionDAGBuilder::getValue(const Value *V) {
920 // If we already have an SDValue for this value, use it. It's important
921 // to do this first, so that we don't create a CopyFromReg if we already
922 // have a regular SDValue.
923 SDValue &N = NodeMap[V];
924 if (N.getNode()) return N;
926 // If there's a virtual register allocated and initialized for this
928 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
929 if (It != FuncInfo.ValueMap.end()) {
930 unsigned InReg = It->second;
931 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
932 SDValue Chain = DAG.getEntryNode();
933 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain,NULL);
934 resolveDanglingDebugInfo(V, N);
938 // Otherwise create a new SDValue and remember it.
939 SDValue Val = getValueImpl(V);
941 resolveDanglingDebugInfo(V, Val);
945 /// getNonRegisterValue - Return an SDValue for the given Value, but
946 /// don't look in FuncInfo.ValueMap for a virtual register.
947 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
948 // If we already have an SDValue for this value, use it.
949 SDValue &N = NodeMap[V];
950 if (N.getNode()) return N;
952 // Otherwise create a new SDValue and remember it.
953 SDValue Val = getValueImpl(V);
955 resolveDanglingDebugInfo(V, Val);
959 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
960 /// Create an SDValue for the given value.
961 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
962 if (const Constant *C = dyn_cast<Constant>(V)) {
963 EVT VT = TLI.getValueType(V->getType(), true);
965 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
966 return DAG.getConstant(*CI, VT);
968 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
969 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
971 if (isa<ConstantPointerNull>(C))
972 return DAG.getConstant(0, TLI.getPointerTy());
974 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
975 return DAG.getConstantFP(*CFP, VT);
977 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
978 return DAG.getUNDEF(VT);
980 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
981 visit(CE->getOpcode(), *CE);
982 SDValue N1 = NodeMap[V];
983 assert(N1.getNode() && "visit didn't populate the NodeMap!");
987 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
988 SmallVector<SDValue, 4> Constants;
989 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
991 SDNode *Val = getValue(*OI).getNode();
992 // If the operand is an empty aggregate, there are no values.
994 // Add each leaf value from the operand to the Constants list
995 // to form a flattened list of all the values.
996 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
997 Constants.push_back(SDValue(Val, i));
1000 return DAG.getMergeValues(&Constants[0], Constants.size(),
1004 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1005 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1006 "Unknown struct or array constant!");
1008 SmallVector<EVT, 4> ValueVTs;
1009 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1010 unsigned NumElts = ValueVTs.size();
1012 return SDValue(); // empty struct
1013 SmallVector<SDValue, 4> Constants(NumElts);
1014 for (unsigned i = 0; i != NumElts; ++i) {
1015 EVT EltVT = ValueVTs[i];
1016 if (isa<UndefValue>(C))
1017 Constants[i] = DAG.getUNDEF(EltVT);
1018 else if (EltVT.isFloatingPoint())
1019 Constants[i] = DAG.getConstantFP(0, EltVT);
1021 Constants[i] = DAG.getConstant(0, EltVT);
1024 return DAG.getMergeValues(&Constants[0], NumElts,
1028 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1029 return DAG.getBlockAddress(BA, VT);
1031 const VectorType *VecTy = cast<VectorType>(V->getType());
1032 unsigned NumElements = VecTy->getNumElements();
1034 // Now that we know the number and type of the elements, get that number of
1035 // elements into the Ops array based on what kind of constant it is.
1036 SmallVector<SDValue, 16> Ops;
1037 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) {
1038 for (unsigned i = 0; i != NumElements; ++i)
1039 Ops.push_back(getValue(CP->getOperand(i)));
1041 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1042 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1045 if (EltVT.isFloatingPoint())
1046 Op = DAG.getConstantFP(0, EltVT);
1048 Op = DAG.getConstant(0, EltVT);
1049 Ops.assign(NumElements, Op);
1052 // Create a BUILD_VECTOR node.
1053 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1054 VT, &Ops[0], Ops.size());
1057 // If this is a static alloca, generate it as the frameindex instead of
1059 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1060 DenseMap<const AllocaInst*, int>::iterator SI =
1061 FuncInfo.StaticAllocaMap.find(AI);
1062 if (SI != FuncInfo.StaticAllocaMap.end())
1063 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1066 // If this is an instruction which fast-isel has deferred, select it now.
1067 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1068 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1069 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1070 SDValue Chain = DAG.getEntryNode();
1071 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1074 llvm_unreachable("Can't get register for value!");
1078 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1079 SDValue Chain = getControlRoot();
1080 SmallVector<ISD::OutputArg, 8> Outs;
1081 SmallVector<SDValue, 8> OutVals;
1083 if (!FuncInfo.CanLowerReturn) {
1084 unsigned DemoteReg = FuncInfo.DemoteRegister;
1085 const Function *F = I.getParent()->getParent();
1087 // Emit a store of the return value through the virtual register.
1088 // Leave Outs empty so that LowerReturn won't try to load return
1089 // registers the usual way.
1090 SmallVector<EVT, 1> PtrValueVTs;
1091 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1094 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1095 SDValue RetOp = getValue(I.getOperand(0));
1097 SmallVector<EVT, 4> ValueVTs;
1098 SmallVector<uint64_t, 4> Offsets;
1099 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1100 unsigned NumValues = ValueVTs.size();
1102 SmallVector<SDValue, 4> Chains(NumValues);
1103 for (unsigned i = 0; i != NumValues; ++i) {
1104 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1105 RetPtr.getValueType(), RetPtr,
1106 DAG.getIntPtrConstant(Offsets[i]));
1108 DAG.getStore(Chain, getCurDebugLoc(),
1109 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1110 // FIXME: better loc info would be nice.
1111 Add, MachinePointerInfo(), false, false, 0);
1114 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1115 MVT::Other, &Chains[0], NumValues);
1116 } else if (I.getNumOperands() != 0) {
1117 SmallVector<EVT, 4> ValueVTs;
1118 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1119 unsigned NumValues = ValueVTs.size();
1121 SDValue RetOp = getValue(I.getOperand(0));
1122 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1123 EVT VT = ValueVTs[j];
1125 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1127 const Function *F = I.getParent()->getParent();
1128 if (F->paramHasAttr(0, Attribute::SExt))
1129 ExtendKind = ISD::SIGN_EXTEND;
1130 else if (F->paramHasAttr(0, Attribute::ZExt))
1131 ExtendKind = ISD::ZERO_EXTEND;
1133 // FIXME: C calling convention requires the return type to be promoted
1134 // to at least 32-bit. But this is not necessary for non-C calling
1135 // conventions. The frontend should mark functions whose return values
1136 // require promoting with signext or zeroext attributes.
1137 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1138 EVT MinVT = TLI.getRegisterType(*DAG.getContext(), MVT::i32);
1139 if (VT.bitsLT(MinVT))
1143 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1144 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1145 SmallVector<SDValue, 4> Parts(NumParts);
1146 getCopyToParts(DAG, getCurDebugLoc(),
1147 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1148 &Parts[0], NumParts, PartVT, ExtendKind);
1150 // 'inreg' on function refers to return value
1151 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1152 if (F->paramHasAttr(0, Attribute::InReg))
1155 // Propagate extension type if any
1156 if (F->paramHasAttr(0, Attribute::SExt))
1158 else if (F->paramHasAttr(0, Attribute::ZExt))
1161 for (unsigned i = 0; i < NumParts; ++i) {
1162 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1164 OutVals.push_back(Parts[i]);
1170 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1171 CallingConv::ID CallConv =
1172 DAG.getMachineFunction().getFunction()->getCallingConv();
1173 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1174 Outs, OutVals, getCurDebugLoc(), DAG);
1176 // Verify that the target's LowerReturn behaved as expected.
1177 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1178 "LowerReturn didn't return a valid chain!");
1180 // Update the DAG with the new chain value resulting from return lowering.
1184 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1185 /// created for it, emit nodes to copy the value into the virtual
1187 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1188 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1189 if (VMI != FuncInfo.ValueMap.end()) {
1190 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1191 CopyValueToVirtualRegister(V, VMI->second);
1195 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1196 /// the current basic block, add it to ValueMap now so that we'll get a
1198 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1199 // No need to export constants.
1200 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1202 // Already exported?
1203 if (FuncInfo.isExportedInst(V)) return;
1205 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1206 CopyValueToVirtualRegister(V, Reg);
1209 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1210 const BasicBlock *FromBB) {
1211 // The operands of the setcc have to be in this block. We don't know
1212 // how to export them from some other block.
1213 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1214 // Can export from current BB.
1215 if (VI->getParent() == FromBB)
1218 // Is already exported, noop.
1219 return FuncInfo.isExportedInst(V);
1222 // If this is an argument, we can export it if the BB is the entry block or
1223 // if it is already exported.
1224 if (isa<Argument>(V)) {
1225 if (FromBB == &FromBB->getParent()->getEntryBlock())
1228 // Otherwise, can only export this if it is already exported.
1229 return FuncInfo.isExportedInst(V);
1232 // Otherwise, constants can always be exported.
1236 static bool InBlock(const Value *V, const BasicBlock *BB) {
1237 if (const Instruction *I = dyn_cast<Instruction>(V))
1238 return I->getParent() == BB;
1242 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1243 /// This function emits a branch and is used at the leaves of an OR or an
1244 /// AND operator tree.
1247 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1248 MachineBasicBlock *TBB,
1249 MachineBasicBlock *FBB,
1250 MachineBasicBlock *CurBB,
1251 MachineBasicBlock *SwitchBB) {
1252 const BasicBlock *BB = CurBB->getBasicBlock();
1254 // If the leaf of the tree is a comparison, merge the condition into
1256 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1257 // The operands of the cmp have to be in this block. We don't know
1258 // how to export them from some other block. If this is the first block
1259 // of the sequence, no exporting is needed.
1260 if (CurBB == SwitchBB ||
1261 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1262 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1263 ISD::CondCode Condition;
1264 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1265 Condition = getICmpCondCode(IC->getPredicate());
1266 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1267 Condition = getFCmpCondCode(FC->getPredicate());
1269 Condition = ISD::SETEQ; // silence warning.
1270 llvm_unreachable("Unknown compare instruction");
1273 CaseBlock CB(Condition, BOp->getOperand(0),
1274 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1275 SwitchCases.push_back(CB);
1280 // Create a CaseBlock record representing this branch.
1281 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1282 NULL, TBB, FBB, CurBB);
1283 SwitchCases.push_back(CB);
1286 /// FindMergedConditions - If Cond is an expression like
1287 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1288 MachineBasicBlock *TBB,
1289 MachineBasicBlock *FBB,
1290 MachineBasicBlock *CurBB,
1291 MachineBasicBlock *SwitchBB,
1293 // If this node is not part of the or/and tree, emit it as a branch.
1294 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1295 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1296 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1297 BOp->getParent() != CurBB->getBasicBlock() ||
1298 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1299 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1300 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1304 // Create TmpBB after CurBB.
1305 MachineFunction::iterator BBI = CurBB;
1306 MachineFunction &MF = DAG.getMachineFunction();
1307 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1308 CurBB->getParent()->insert(++BBI, TmpBB);
1310 if (Opc == Instruction::Or) {
1311 // Codegen X | Y as:
1319 // Emit the LHS condition.
1320 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1322 // Emit the RHS condition into TmpBB.
1323 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1325 assert(Opc == Instruction::And && "Unknown merge op!");
1326 // Codegen X & Y as:
1333 // This requires creation of TmpBB after CurBB.
1335 // Emit the LHS condition.
1336 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1338 // Emit the RHS condition into TmpBB.
1339 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1343 /// If the set of cases should be emitted as a series of branches, return true.
1344 /// If we should emit this as a bunch of and/or'd together conditions, return
1347 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1348 if (Cases.size() != 2) return true;
1350 // If this is two comparisons of the same values or'd or and'd together, they
1351 // will get folded into a single comparison, so don't emit two blocks.
1352 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1353 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1354 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1355 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1359 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1360 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1361 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1362 Cases[0].CC == Cases[1].CC &&
1363 isa<Constant>(Cases[0].CmpRHS) &&
1364 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1365 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1367 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1374 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1375 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1377 // Update machine-CFG edges.
1378 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1380 // Figure out which block is immediately after the current one.
1381 MachineBasicBlock *NextBlock = 0;
1382 MachineFunction::iterator BBI = BrMBB;
1383 if (++BBI != FuncInfo.MF->end())
1386 if (I.isUnconditional()) {
1387 // Update machine-CFG edges.
1388 BrMBB->addSuccessor(Succ0MBB);
1390 // If this is not a fall-through branch, emit the branch.
1391 if (Succ0MBB != NextBlock)
1392 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1393 MVT::Other, getControlRoot(),
1394 DAG.getBasicBlock(Succ0MBB)));
1399 // If this condition is one of the special cases we handle, do special stuff
1401 const Value *CondVal = I.getCondition();
1402 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1404 // If this is a series of conditions that are or'd or and'd together, emit
1405 // this as a sequence of branches instead of setcc's with and/or operations.
1406 // As long as jumps are not expensive, this should improve performance.
1407 // For example, instead of something like:
1420 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1421 if (!TLI.isJumpExpensive() &&
1423 (BOp->getOpcode() == Instruction::And ||
1424 BOp->getOpcode() == Instruction::Or)) {
1425 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1427 // If the compares in later blocks need to use values not currently
1428 // exported from this block, export them now. This block should always
1429 // be the first entry.
1430 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1432 // Allow some cases to be rejected.
1433 if (ShouldEmitAsBranches(SwitchCases)) {
1434 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1435 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1436 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1439 // Emit the branch for this block.
1440 visitSwitchCase(SwitchCases[0], BrMBB);
1441 SwitchCases.erase(SwitchCases.begin());
1445 // Okay, we decided not to do this, remove any inserted MBB's and clear
1447 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1448 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1450 SwitchCases.clear();
1454 // Create a CaseBlock record representing this branch.
1455 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1456 NULL, Succ0MBB, Succ1MBB, BrMBB);
1458 // Use visitSwitchCase to actually insert the fast branch sequence for this
1460 visitSwitchCase(CB, BrMBB);
1463 /// visitSwitchCase - Emits the necessary code to represent a single node in
1464 /// the binary search tree resulting from lowering a switch instruction.
1465 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1466 MachineBasicBlock *SwitchBB) {
1468 SDValue CondLHS = getValue(CB.CmpLHS);
1469 DebugLoc dl = getCurDebugLoc();
1471 // Build the setcc now.
1472 if (CB.CmpMHS == NULL) {
1473 // Fold "(X == true)" to X and "(X == false)" to !X to
1474 // handle common cases produced by branch lowering.
1475 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1476 CB.CC == ISD::SETEQ)
1478 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1479 CB.CC == ISD::SETEQ) {
1480 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1481 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1483 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1485 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1487 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1488 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1490 SDValue CmpOp = getValue(CB.CmpMHS);
1491 EVT VT = CmpOp.getValueType();
1493 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1494 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1497 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1498 VT, CmpOp, DAG.getConstant(Low, VT));
1499 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1500 DAG.getConstant(High-Low, VT), ISD::SETULE);
1504 // Update successor info
1505 SwitchBB->addSuccessor(CB.TrueBB);
1506 SwitchBB->addSuccessor(CB.FalseBB);
1508 // Set NextBlock to be the MBB immediately after the current one, if any.
1509 // This is used to avoid emitting unnecessary branches to the next block.
1510 MachineBasicBlock *NextBlock = 0;
1511 MachineFunction::iterator BBI = SwitchBB;
1512 if (++BBI != FuncInfo.MF->end())
1515 // If the lhs block is the next block, invert the condition so that we can
1516 // fall through to the lhs instead of the rhs block.
1517 if (CB.TrueBB == NextBlock) {
1518 std::swap(CB.TrueBB, CB.FalseBB);
1519 SDValue True = DAG.getConstant(1, Cond.getValueType());
1520 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1523 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1524 MVT::Other, getControlRoot(), Cond,
1525 DAG.getBasicBlock(CB.TrueBB));
1527 // Insert the false branch. Do this even if it's a fall through branch,
1528 // this makes it easier to do DAG optimizations which require inverting
1529 // the branch condition.
1530 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1531 DAG.getBasicBlock(CB.FalseBB));
1533 DAG.setRoot(BrCond);
1536 /// visitJumpTable - Emit JumpTable node in the current MBB
1537 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1538 // Emit the code for the jump table
1539 assert(JT.Reg != -1U && "Should lower JT Header first!");
1540 EVT PTy = TLI.getPointerTy();
1541 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1543 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1544 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1545 MVT::Other, Index.getValue(1),
1547 DAG.setRoot(BrJumpTable);
1550 /// visitJumpTableHeader - This function emits necessary code to produce index
1551 /// in the JumpTable from switch case.
1552 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1553 JumpTableHeader &JTH,
1554 MachineBasicBlock *SwitchBB) {
1555 // Subtract the lowest switch case value from the value being switched on and
1556 // conditional branch to default mbb if the result is greater than the
1557 // difference between smallest and largest cases.
1558 SDValue SwitchOp = getValue(JTH.SValue);
1559 EVT VT = SwitchOp.getValueType();
1560 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1561 DAG.getConstant(JTH.First, VT));
1563 // The SDNode we just created, which holds the value being switched on minus
1564 // the smallest case value, needs to be copied to a virtual register so it
1565 // can be used as an index into the jump table in a subsequent basic block.
1566 // This value may be smaller or larger than the target's pointer type, and
1567 // therefore require extension or truncating.
1568 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1570 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1571 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1572 JumpTableReg, SwitchOp);
1573 JT.Reg = JumpTableReg;
1575 // Emit the range check for the jump table, and branch to the default block
1576 // for the switch statement if the value being switched on exceeds the largest
1577 // case in the switch.
1578 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1579 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1580 DAG.getConstant(JTH.Last-JTH.First,VT),
1583 // Set NextBlock to be the MBB immediately after the current one, if any.
1584 // This is used to avoid emitting unnecessary branches to the next block.
1585 MachineBasicBlock *NextBlock = 0;
1586 MachineFunction::iterator BBI = SwitchBB;
1588 if (++BBI != FuncInfo.MF->end())
1591 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1592 MVT::Other, CopyTo, CMP,
1593 DAG.getBasicBlock(JT.Default));
1595 if (JT.MBB != NextBlock)
1596 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1597 DAG.getBasicBlock(JT.MBB));
1599 DAG.setRoot(BrCond);
1602 /// visitBitTestHeader - This function emits necessary code to produce value
1603 /// suitable for "bit tests"
1604 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1605 MachineBasicBlock *SwitchBB) {
1606 // Subtract the minimum value
1607 SDValue SwitchOp = getValue(B.SValue);
1608 EVT VT = SwitchOp.getValueType();
1609 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1610 DAG.getConstant(B.First, VT));
1613 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1614 TLI.getSetCCResultType(Sub.getValueType()),
1615 Sub, DAG.getConstant(B.Range, VT),
1618 // Determine the type of the test operands.
1619 bool UsePtrType = false;
1620 if (!TLI.isTypeLegal(VT))
1623 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1624 if ((uint64_t)((int64_t)B.Cases[i].Mask >> VT.getSizeInBits()) + 1 >= 2) {
1625 // Switch table case range are encoded into series of masks.
1626 // Just use pointer type, it's guaranteed to fit.
1632 VT = TLI.getPointerTy();
1633 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1637 B.Reg = FuncInfo.CreateReg(VT);
1638 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1641 // Set NextBlock to be the MBB immediately after the current one, if any.
1642 // This is used to avoid emitting unnecessary branches to the next block.
1643 MachineBasicBlock *NextBlock = 0;
1644 MachineFunction::iterator BBI = SwitchBB;
1645 if (++BBI != FuncInfo.MF->end())
1648 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1650 SwitchBB->addSuccessor(B.Default);
1651 SwitchBB->addSuccessor(MBB);
1653 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1654 MVT::Other, CopyTo, RangeCmp,
1655 DAG.getBasicBlock(B.Default));
1657 if (MBB != NextBlock)
1658 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1659 DAG.getBasicBlock(MBB));
1661 DAG.setRoot(BrRange);
1664 /// visitBitTestCase - this function produces one "bit test"
1665 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1666 MachineBasicBlock* NextMBB,
1669 MachineBasicBlock *SwitchBB) {
1671 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1674 if (CountPopulation_64(B.Mask) == 1) {
1675 // Testing for a single bit; just compare the shift count with what it
1676 // would need to be to shift a 1 bit in that position.
1677 Cmp = DAG.getSetCC(getCurDebugLoc(),
1678 TLI.getSetCCResultType(VT),
1680 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1683 // Make desired shift
1684 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1685 DAG.getConstant(1, VT), ShiftOp);
1687 // Emit bit tests and jumps
1688 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1689 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1690 Cmp = DAG.getSetCC(getCurDebugLoc(),
1691 TLI.getSetCCResultType(VT),
1692 AndOp, DAG.getConstant(0, VT),
1696 SwitchBB->addSuccessor(B.TargetBB);
1697 SwitchBB->addSuccessor(NextMBB);
1699 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1700 MVT::Other, getControlRoot(),
1701 Cmp, DAG.getBasicBlock(B.TargetBB));
1703 // Set NextBlock to be the MBB immediately after the current one, if any.
1704 // This is used to avoid emitting unnecessary branches to the next block.
1705 MachineBasicBlock *NextBlock = 0;
1706 MachineFunction::iterator BBI = SwitchBB;
1707 if (++BBI != FuncInfo.MF->end())
1710 if (NextMBB != NextBlock)
1711 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1712 DAG.getBasicBlock(NextMBB));
1717 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1718 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1720 // Retrieve successors.
1721 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1722 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1724 const Value *Callee(I.getCalledValue());
1725 if (isa<InlineAsm>(Callee))
1728 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1730 // If the value of the invoke is used outside of its defining block, make it
1731 // available as a virtual register.
1732 CopyToExportRegsIfNeeded(&I);
1734 // Update successor info
1735 InvokeMBB->addSuccessor(Return);
1736 InvokeMBB->addSuccessor(LandingPad);
1738 // Drop into normal successor.
1739 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1740 MVT::Other, getControlRoot(),
1741 DAG.getBasicBlock(Return)));
1744 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1747 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1748 /// small case ranges).
1749 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1750 CaseRecVector& WorkList,
1752 MachineBasicBlock *Default,
1753 MachineBasicBlock *SwitchBB) {
1754 Case& BackCase = *(CR.Range.second-1);
1756 // Size is the number of Cases represented by this range.
1757 size_t Size = CR.Range.second - CR.Range.first;
1761 // Get the MachineFunction which holds the current MBB. This is used when
1762 // inserting any additional MBBs necessary to represent the switch.
1763 MachineFunction *CurMF = FuncInfo.MF;
1765 // Figure out which block is immediately after the current one.
1766 MachineBasicBlock *NextBlock = 0;
1767 MachineFunction::iterator BBI = CR.CaseBB;
1769 if (++BBI != FuncInfo.MF->end())
1772 // If any two of the cases has the same destination, and if one value
1773 // is the same as the other, but has one bit unset that the other has set,
1774 // use bit manipulation to do two compares at once. For example:
1775 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1776 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1777 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1778 if (Size == 2 && CR.CaseBB == SwitchBB) {
1779 Case &Small = *CR.Range.first;
1780 Case &Big = *(CR.Range.second-1);
1782 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1783 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1784 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1786 // Check that there is only one bit different.
1787 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1788 (SmallValue | BigValue) == BigValue) {
1789 // Isolate the common bit.
1790 APInt CommonBit = BigValue & ~SmallValue;
1791 assert((SmallValue | CommonBit) == BigValue &&
1792 CommonBit.countPopulation() == 1 && "Not a common bit?");
1794 SDValue CondLHS = getValue(SV);
1795 EVT VT = CondLHS.getValueType();
1796 DebugLoc DL = getCurDebugLoc();
1798 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1799 DAG.getConstant(CommonBit, VT));
1800 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1801 Or, DAG.getConstant(BigValue, VT),
1804 // Update successor info.
1805 SwitchBB->addSuccessor(Small.BB);
1806 SwitchBB->addSuccessor(Default);
1808 // Insert the true branch.
1809 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1810 getControlRoot(), Cond,
1811 DAG.getBasicBlock(Small.BB));
1813 // Insert the false branch.
1814 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1815 DAG.getBasicBlock(Default));
1817 DAG.setRoot(BrCond);
1823 // Rearrange the case blocks so that the last one falls through if possible.
1824 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1825 // The last case block won't fall through into 'NextBlock' if we emit the
1826 // branches in this order. See if rearranging a case value would help.
1827 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1828 if (I->BB == NextBlock) {
1829 std::swap(*I, BackCase);
1835 // Create a CaseBlock record representing a conditional branch to
1836 // the Case's target mbb if the value being switched on SV is equal
1838 MachineBasicBlock *CurBlock = CR.CaseBB;
1839 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1840 MachineBasicBlock *FallThrough;
1842 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1843 CurMF->insert(BBI, FallThrough);
1845 // Put SV in a virtual register to make it available from the new blocks.
1846 ExportFromCurrentBlock(SV);
1848 // If the last case doesn't match, go to the default block.
1849 FallThrough = Default;
1852 const Value *RHS, *LHS, *MHS;
1854 if (I->High == I->Low) {
1855 // This is just small small case range :) containing exactly 1 case
1857 LHS = SV; RHS = I->High; MHS = NULL;
1860 LHS = I->Low; MHS = SV; RHS = I->High;
1862 CaseBlock CB(CC, LHS, RHS, MHS, I->BB, FallThrough, CurBlock);
1864 // If emitting the first comparison, just call visitSwitchCase to emit the
1865 // code into the current block. Otherwise, push the CaseBlock onto the
1866 // vector to be later processed by SDISel, and insert the node's MBB
1867 // before the next MBB.
1868 if (CurBlock == SwitchBB)
1869 visitSwitchCase(CB, SwitchBB);
1871 SwitchCases.push_back(CB);
1873 CurBlock = FallThrough;
1879 static inline bool areJTsAllowed(const TargetLowering &TLI) {
1880 return !DisableJumpTables &&
1881 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
1882 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
1885 static APInt ComputeRange(const APInt &First, const APInt &Last) {
1886 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
1887 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
1888 return (LastExt - FirstExt + 1ULL);
1891 /// handleJTSwitchCase - Emit jumptable for current switch case range
1892 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec& CR,
1893 CaseRecVector& WorkList,
1895 MachineBasicBlock* Default,
1896 MachineBasicBlock *SwitchBB) {
1897 Case& FrontCase = *CR.Range.first;
1898 Case& BackCase = *(CR.Range.second-1);
1900 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
1901 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
1903 APInt TSize(First.getBitWidth(), 0);
1904 for (CaseItr I = CR.Range.first, E = CR.Range.second;
1908 if (!areJTsAllowed(TLI) || TSize.ult(4))
1911 APInt Range = ComputeRange(First, Last);
1912 double Density = TSize.roundToDouble() / Range.roundToDouble();
1916 DEBUG(dbgs() << "Lowering jump table\n"
1917 << "First entry: " << First << ". Last entry: " << Last << '\n'
1918 << "Range: " << Range
1919 << ". Size: " << TSize << ". Density: " << Density << "\n\n");
1921 // Get the MachineFunction which holds the current MBB. This is used when
1922 // inserting any additional MBBs necessary to represent the switch.
1923 MachineFunction *CurMF = FuncInfo.MF;
1925 // Figure out which block is immediately after the current one.
1926 MachineFunction::iterator BBI = CR.CaseBB;
1929 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
1931 // Create a new basic block to hold the code for loading the address
1932 // of the jump table, and jumping to it. Update successor information;
1933 // we will either branch to the default case for the switch, or the jump
1935 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
1936 CurMF->insert(BBI, JumpTableBB);
1937 CR.CaseBB->addSuccessor(Default);
1938 CR.CaseBB->addSuccessor(JumpTableBB);
1940 // Build a vector of destination BBs, corresponding to each target
1941 // of the jump table. If the value of the jump table slot corresponds to
1942 // a case statement, push the case's BB onto the vector, otherwise, push
1944 std::vector<MachineBasicBlock*> DestBBs;
1946 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
1947 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
1948 const APInt &High = cast<ConstantInt>(I->High)->getValue();
1950 if (Low.sle(TEI) && TEI.sle(High)) {
1951 DestBBs.push_back(I->BB);
1955 DestBBs.push_back(Default);
1959 // Update successor info. Add one edge to each unique successor.
1960 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
1961 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
1962 E = DestBBs.end(); I != E; ++I) {
1963 if (!SuccsHandled[(*I)->getNumber()]) {
1964 SuccsHandled[(*I)->getNumber()] = true;
1965 JumpTableBB->addSuccessor(*I);
1969 // Create a jump table index for this jump table.
1970 unsigned JTEncoding = TLI.getJumpTableEncoding();
1971 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
1972 ->createJumpTableIndex(DestBBs);
1974 // Set the jump table information so that we can codegen it as a second
1975 // MachineBasicBlock
1976 JumpTable JT(-1U, JTI, JumpTableBB, Default);
1977 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
1978 if (CR.CaseBB == SwitchBB)
1979 visitJumpTableHeader(JT, JTH, SwitchBB);
1981 JTCases.push_back(JumpTableBlock(JTH, JT));
1986 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
1988 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
1989 CaseRecVector& WorkList,
1991 MachineBasicBlock *Default,
1992 MachineBasicBlock *SwitchBB) {
1993 // Get the MachineFunction which holds the current MBB. This is used when
1994 // inserting any additional MBBs necessary to represent the switch.
1995 MachineFunction *CurMF = FuncInfo.MF;
1997 // Figure out which block is immediately after the current one.
1998 MachineFunction::iterator BBI = CR.CaseBB;
2001 Case& FrontCase = *CR.Range.first;
2002 Case& BackCase = *(CR.Range.second-1);
2003 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2005 // Size is the number of Cases represented by this range.
2006 unsigned Size = CR.Range.second - CR.Range.first;
2008 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2009 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2011 CaseItr Pivot = CR.Range.first + Size/2;
2013 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2014 // (heuristically) allow us to emit JumpTable's later.
2015 APInt TSize(First.getBitWidth(), 0);
2016 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2020 APInt LSize = FrontCase.size();
2021 APInt RSize = TSize-LSize;
2022 DEBUG(dbgs() << "Selecting best pivot: \n"
2023 << "First: " << First << ", Last: " << Last <<'\n'
2024 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2025 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2027 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2028 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2029 APInt Range = ComputeRange(LEnd, RBegin);
2030 assert((Range - 2ULL).isNonNegative() &&
2031 "Invalid case distance");
2032 double LDensity = (double)LSize.roundToDouble() /
2033 (LEnd - First + 1ULL).roundToDouble();
2034 double RDensity = (double)RSize.roundToDouble() /
2035 (Last - RBegin + 1ULL).roundToDouble();
2036 double Metric = Range.logBase2()*(LDensity+RDensity);
2037 // Should always split in some non-trivial place
2038 DEBUG(dbgs() <<"=>Step\n"
2039 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2040 << "LDensity: " << LDensity
2041 << ", RDensity: " << RDensity << '\n'
2042 << "Metric: " << Metric << '\n');
2043 if (FMetric < Metric) {
2046 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2052 if (areJTsAllowed(TLI)) {
2053 // If our case is dense we *really* should handle it earlier!
2054 assert((FMetric > 0) && "Should handle dense range earlier!");
2056 Pivot = CR.Range.first + Size/2;
2059 CaseRange LHSR(CR.Range.first, Pivot);
2060 CaseRange RHSR(Pivot, CR.Range.second);
2061 Constant *C = Pivot->Low;
2062 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2064 // We know that we branch to the LHS if the Value being switched on is
2065 // less than the Pivot value, C. We use this to optimize our binary
2066 // tree a bit, by recognizing that if SV is greater than or equal to the
2067 // LHS's Case Value, and that Case Value is exactly one less than the
2068 // Pivot's Value, then we can branch directly to the LHS's Target,
2069 // rather than creating a leaf node for it.
2070 if ((LHSR.second - LHSR.first) == 1 &&
2071 LHSR.first->High == CR.GE &&
2072 cast<ConstantInt>(C)->getValue() ==
2073 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2074 TrueBB = LHSR.first->BB;
2076 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2077 CurMF->insert(BBI, TrueBB);
2078 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2080 // Put SV in a virtual register to make it available from the new blocks.
2081 ExportFromCurrentBlock(SV);
2084 // Similar to the optimization above, if the Value being switched on is
2085 // known to be less than the Constant CR.LT, and the current Case Value
2086 // is CR.LT - 1, then we can branch directly to the target block for
2087 // the current Case Value, rather than emitting a RHS leaf node for it.
2088 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2089 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2090 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2091 FalseBB = RHSR.first->BB;
2093 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2094 CurMF->insert(BBI, FalseBB);
2095 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2097 // Put SV in a virtual register to make it available from the new blocks.
2098 ExportFromCurrentBlock(SV);
2101 // Create a CaseBlock record representing a conditional branch to
2102 // the LHS node if the value being switched on SV is less than C.
2103 // Otherwise, branch to LHS.
2104 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2106 if (CR.CaseBB == SwitchBB)
2107 visitSwitchCase(CB, SwitchBB);
2109 SwitchCases.push_back(CB);
2114 /// handleBitTestsSwitchCase - if current case range has few destination and
2115 /// range span less, than machine word bitwidth, encode case range into series
2116 /// of masks and emit bit tests with these masks.
2117 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2118 CaseRecVector& WorkList,
2120 MachineBasicBlock* Default,
2121 MachineBasicBlock *SwitchBB){
2122 EVT PTy = TLI.getPointerTy();
2123 unsigned IntPtrBits = PTy.getSizeInBits();
2125 Case& FrontCase = *CR.Range.first;
2126 Case& BackCase = *(CR.Range.second-1);
2128 // Get the MachineFunction which holds the current MBB. This is used when
2129 // inserting any additional MBBs necessary to represent the switch.
2130 MachineFunction *CurMF = FuncInfo.MF;
2132 // If target does not have legal shift left, do not emit bit tests at all.
2133 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2137 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2139 // Single case counts one, case range - two.
2140 numCmps += (I->Low == I->High ? 1 : 2);
2143 // Count unique destinations
2144 SmallSet<MachineBasicBlock*, 4> Dests;
2145 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2146 Dests.insert(I->BB);
2147 if (Dests.size() > 3)
2148 // Don't bother the code below, if there are too much unique destinations
2151 DEBUG(dbgs() << "Total number of unique destinations: "
2152 << Dests.size() << '\n'
2153 << "Total number of comparisons: " << numCmps << '\n');
2155 // Compute span of values.
2156 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2157 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2158 APInt cmpRange = maxValue - minValue;
2160 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2161 << "Low bound: " << minValue << '\n'
2162 << "High bound: " << maxValue << '\n');
2164 if (cmpRange.uge(IntPtrBits) ||
2165 (!(Dests.size() == 1 && numCmps >= 3) &&
2166 !(Dests.size() == 2 && numCmps >= 5) &&
2167 !(Dests.size() >= 3 && numCmps >= 6)))
2170 DEBUG(dbgs() << "Emitting bit tests\n");
2171 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2173 // Optimize the case where all the case values fit in a
2174 // word without having to subtract minValue. In this case,
2175 // we can optimize away the subtraction.
2176 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2177 cmpRange = maxValue;
2179 lowBound = minValue;
2182 CaseBitsVector CasesBits;
2183 unsigned i, count = 0;
2185 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2186 MachineBasicBlock* Dest = I->BB;
2187 for (i = 0; i < count; ++i)
2188 if (Dest == CasesBits[i].BB)
2192 assert((count < 3) && "Too much destinations to test!");
2193 CasesBits.push_back(CaseBits(0, Dest, 0));
2197 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2198 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2200 uint64_t lo = (lowValue - lowBound).getZExtValue();
2201 uint64_t hi = (highValue - lowBound).getZExtValue();
2203 for (uint64_t j = lo; j <= hi; j++) {
2204 CasesBits[i].Mask |= 1ULL << j;
2205 CasesBits[i].Bits++;
2209 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2213 // Figure out which block is immediately after the current one.
2214 MachineFunction::iterator BBI = CR.CaseBB;
2217 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2219 DEBUG(dbgs() << "Cases:\n");
2220 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2221 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2222 << ", Bits: " << CasesBits[i].Bits
2223 << ", BB: " << CasesBits[i].BB << '\n');
2225 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2226 CurMF->insert(BBI, CaseBB);
2227 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2231 // Put SV in a virtual register to make it available from the new blocks.
2232 ExportFromCurrentBlock(SV);
2235 BitTestBlock BTB(lowBound, cmpRange, SV,
2236 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2237 CR.CaseBB, Default, BTC);
2239 if (CR.CaseBB == SwitchBB)
2240 visitBitTestHeader(BTB, SwitchBB);
2242 BitTestCases.push_back(BTB);
2247 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2248 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2249 const SwitchInst& SI) {
2252 // Start with "simple" cases
2253 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) {
2254 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SI.getSuccessor(i)];
2255 Cases.push_back(Case(SI.getSuccessorValue(i),
2256 SI.getSuccessorValue(i),
2259 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2261 // Merge case into clusters
2262 if (Cases.size() >= 2)
2263 // Must recompute end() each iteration because it may be
2264 // invalidated by erase if we hold on to it
2265 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2266 J != Cases.end(); ) {
2267 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2268 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2269 MachineBasicBlock* nextBB = J->BB;
2270 MachineBasicBlock* currentBB = I->BB;
2272 // If the two neighboring cases go to the same destination, merge them
2273 // into a single case.
2274 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2282 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2283 if (I->Low != I->High)
2284 // A range counts double, since it requires two compares.
2291 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2292 MachineBasicBlock *Last) {
2294 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2295 if (JTCases[i].first.HeaderBB == First)
2296 JTCases[i].first.HeaderBB = Last;
2298 // Update BitTestCases.
2299 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2300 if (BitTestCases[i].Parent == First)
2301 BitTestCases[i].Parent = Last;
2304 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2305 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2307 // Figure out which block is immediately after the current one.
2308 MachineBasicBlock *NextBlock = 0;
2309 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2311 // If there is only the default destination, branch to it if it is not the
2312 // next basic block. Otherwise, just fall through.
2313 if (SI.getNumOperands() == 2) {
2314 // Update machine-CFG edges.
2316 // If this is not a fall-through branch, emit the branch.
2317 SwitchMBB->addSuccessor(Default);
2318 if (Default != NextBlock)
2319 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2320 MVT::Other, getControlRoot(),
2321 DAG.getBasicBlock(Default)));
2326 // If there are any non-default case statements, create a vector of Cases
2327 // representing each one, and sort the vector so that we can efficiently
2328 // create a binary search tree from them.
2330 size_t numCmps = Clusterify(Cases, SI);
2331 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2332 << ". Total compares: " << numCmps << '\n');
2335 // Get the Value to be switched on and default basic blocks, which will be
2336 // inserted into CaseBlock records, representing basic blocks in the binary
2338 const Value *SV = SI.getOperand(0);
2340 // Push the initial CaseRec onto the worklist
2341 CaseRecVector WorkList;
2342 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2343 CaseRange(Cases.begin(),Cases.end())));
2345 while (!WorkList.empty()) {
2346 // Grab a record representing a case range to process off the worklist
2347 CaseRec CR = WorkList.back();
2348 WorkList.pop_back();
2350 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2353 // If the range has few cases (two or less) emit a series of specific
2355 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2358 // If the switch has more than 5 blocks, and at least 40% dense, and the
2359 // target supports indirect branches, then emit a jump table rather than
2360 // lowering the switch to a binary tree of conditional branches.
2361 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2364 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2365 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2366 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2370 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2371 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2373 // Update machine-CFG edges with unique successors.
2374 SmallVector<BasicBlock*, 32> succs;
2375 succs.reserve(I.getNumSuccessors());
2376 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2377 succs.push_back(I.getSuccessor(i));
2378 array_pod_sort(succs.begin(), succs.end());
2379 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2380 for (unsigned i = 0, e = succs.size(); i != e; ++i)
2381 IndirectBrMBB->addSuccessor(FuncInfo.MBBMap[succs[i]]);
2383 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2384 MVT::Other, getControlRoot(),
2385 getValue(I.getAddress())));
2388 void SelectionDAGBuilder::visitFSub(const User &I) {
2389 // -0.0 - X --> fneg
2390 const Type *Ty = I.getType();
2391 if (isa<Constant>(I.getOperand(0)) &&
2392 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2393 SDValue Op2 = getValue(I.getOperand(1));
2394 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2395 Op2.getValueType(), Op2));
2399 visitBinary(I, ISD::FSUB);
2402 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2403 SDValue Op1 = getValue(I.getOperand(0));
2404 SDValue Op2 = getValue(I.getOperand(1));
2405 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2406 Op1.getValueType(), Op1, Op2));
2409 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2410 SDValue Op1 = getValue(I.getOperand(0));
2411 SDValue Op2 = getValue(I.getOperand(1));
2413 MVT ShiftTy = TLI.getShiftAmountTy();
2415 // Coerce the shift amount to the right type if we can.
2416 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2417 unsigned ShiftSize = ShiftTy.getSizeInBits();
2418 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2419 DebugLoc DL = getCurDebugLoc();
2421 // If the operand is smaller than the shift count type, promote it.
2422 if (ShiftSize > Op2Size)
2423 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2425 // If the operand is larger than the shift count type but the shift
2426 // count type has enough bits to represent any shift value, truncate
2427 // it now. This is a common case and it exposes the truncate to
2428 // optimization early.
2429 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2430 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2431 // Otherwise we'll need to temporarily settle for some other convenient
2432 // type. Type legalization will make adjustments once the shiftee is split.
2434 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2437 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2438 Op1.getValueType(), Op1, Op2));
2441 void SelectionDAGBuilder::visitICmp(const User &I) {
2442 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2443 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2444 predicate = IC->getPredicate();
2445 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2446 predicate = ICmpInst::Predicate(IC->getPredicate());
2447 SDValue Op1 = getValue(I.getOperand(0));
2448 SDValue Op2 = getValue(I.getOperand(1));
2449 ISD::CondCode Opcode = getICmpCondCode(predicate);
2451 EVT DestVT = TLI.getValueType(I.getType());
2452 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2455 void SelectionDAGBuilder::visitFCmp(const User &I) {
2456 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2457 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2458 predicate = FC->getPredicate();
2459 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2460 predicate = FCmpInst::Predicate(FC->getPredicate());
2461 SDValue Op1 = getValue(I.getOperand(0));
2462 SDValue Op2 = getValue(I.getOperand(1));
2463 ISD::CondCode Condition = getFCmpCondCode(predicate);
2464 EVT DestVT = TLI.getValueType(I.getType());
2465 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2468 void SelectionDAGBuilder::visitSelect(const User &I) {
2469 SmallVector<EVT, 4> ValueVTs;
2470 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2471 unsigned NumValues = ValueVTs.size();
2472 if (NumValues == 0) return;
2474 SmallVector<SDValue, 4> Values(NumValues);
2475 SDValue Cond = getValue(I.getOperand(0));
2476 SDValue TrueVal = getValue(I.getOperand(1));
2477 SDValue FalseVal = getValue(I.getOperand(2));
2479 for (unsigned i = 0; i != NumValues; ++i)
2480 Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(),
2481 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2483 SDValue(TrueVal.getNode(),
2484 TrueVal.getResNo() + i),
2485 SDValue(FalseVal.getNode(),
2486 FalseVal.getResNo() + i));
2488 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2489 DAG.getVTList(&ValueVTs[0], NumValues),
2490 &Values[0], NumValues));
2493 void SelectionDAGBuilder::visitTrunc(const User &I) {
2494 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2495 SDValue N = getValue(I.getOperand(0));
2496 EVT DestVT = TLI.getValueType(I.getType());
2497 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2500 void SelectionDAGBuilder::visitZExt(const User &I) {
2501 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2502 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2503 SDValue N = getValue(I.getOperand(0));
2504 EVT DestVT = TLI.getValueType(I.getType());
2505 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2508 void SelectionDAGBuilder::visitSExt(const User &I) {
2509 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2510 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2511 SDValue N = getValue(I.getOperand(0));
2512 EVT DestVT = TLI.getValueType(I.getType());
2513 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2516 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2517 // FPTrunc is never a no-op cast, no need to check
2518 SDValue N = getValue(I.getOperand(0));
2519 EVT DestVT = TLI.getValueType(I.getType());
2520 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2521 DestVT, N, DAG.getIntPtrConstant(0)));
2524 void SelectionDAGBuilder::visitFPExt(const User &I){
2525 // FPTrunc is never a no-op cast, no need to check
2526 SDValue N = getValue(I.getOperand(0));
2527 EVT DestVT = TLI.getValueType(I.getType());
2528 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2531 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2532 // FPToUI is never a no-op cast, no need to check
2533 SDValue N = getValue(I.getOperand(0));
2534 EVT DestVT = TLI.getValueType(I.getType());
2535 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2538 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2539 // FPToSI is never a no-op cast, no need to check
2540 SDValue N = getValue(I.getOperand(0));
2541 EVT DestVT = TLI.getValueType(I.getType());
2542 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2545 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2546 // UIToFP is never a no-op cast, no need to check
2547 SDValue N = getValue(I.getOperand(0));
2548 EVT DestVT = TLI.getValueType(I.getType());
2549 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2552 void SelectionDAGBuilder::visitSIToFP(const User &I){
2553 // SIToFP is never a no-op cast, no need to check
2554 SDValue N = getValue(I.getOperand(0));
2555 EVT DestVT = TLI.getValueType(I.getType());
2556 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2559 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2560 // What to do depends on the size of the integer and the size of the pointer.
2561 // We can either truncate, zero extend, or no-op, accordingly.
2562 SDValue N = getValue(I.getOperand(0));
2563 EVT DestVT = TLI.getValueType(I.getType());
2564 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2567 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2568 // What to do depends on the size of the integer and the size of the pointer.
2569 // We can either truncate, zero extend, or no-op, accordingly.
2570 SDValue N = getValue(I.getOperand(0));
2571 EVT DestVT = TLI.getValueType(I.getType());
2572 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2575 void SelectionDAGBuilder::visitBitCast(const User &I) {
2576 SDValue N = getValue(I.getOperand(0));
2577 EVT DestVT = TLI.getValueType(I.getType());
2579 // BitCast assures us that source and destination are the same size so this is
2580 // either a BITCAST or a no-op.
2581 if (DestVT != N.getValueType())
2582 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2583 DestVT, N)); // convert types.
2585 setValue(&I, N); // noop cast.
2588 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2589 SDValue InVec = getValue(I.getOperand(0));
2590 SDValue InVal = getValue(I.getOperand(1));
2591 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2593 getValue(I.getOperand(2)));
2594 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2595 TLI.getValueType(I.getType()),
2596 InVec, InVal, InIdx));
2599 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2600 SDValue InVec = getValue(I.getOperand(0));
2601 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2603 getValue(I.getOperand(1)));
2604 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2605 TLI.getValueType(I.getType()), InVec, InIdx));
2608 // Utility for visitShuffleVector - Returns true if the mask is mask starting
2609 // from SIndx and increasing to the element length (undefs are allowed).
2610 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) {
2611 unsigned MaskNumElts = Mask.size();
2612 for (unsigned i = 0; i != MaskNumElts; ++i)
2613 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx)))
2618 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2619 SmallVector<int, 8> Mask;
2620 SDValue Src1 = getValue(I.getOperand(0));
2621 SDValue Src2 = getValue(I.getOperand(1));
2623 // Convert the ConstantVector mask operand into an array of ints, with -1
2624 // representing undef values.
2625 SmallVector<Constant*, 8> MaskElts;
2626 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts);
2627 unsigned MaskNumElts = MaskElts.size();
2628 for (unsigned i = 0; i != MaskNumElts; ++i) {
2629 if (isa<UndefValue>(MaskElts[i]))
2632 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
2635 EVT VT = TLI.getValueType(I.getType());
2636 EVT SrcVT = Src1.getValueType();
2637 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2639 if (SrcNumElts == MaskNumElts) {
2640 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2645 // Normalize the shuffle vector since mask and vector length don't match.
2646 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2647 // Mask is longer than the source vectors and is a multiple of the source
2648 // vectors. We can use concatenate vector to make the mask and vectors
2650 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) {
2651 // The shuffle is concatenating two vectors together.
2652 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2657 // Pad both vectors with undefs to make them the same length as the mask.
2658 unsigned NumConcat = MaskNumElts / SrcNumElts;
2659 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2660 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2661 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2663 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2664 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2668 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2669 getCurDebugLoc(), VT,
2670 &MOps1[0], NumConcat);
2671 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2672 getCurDebugLoc(), VT,
2673 &MOps2[0], NumConcat);
2675 // Readjust mask for new input vector length.
2676 SmallVector<int, 8> MappedOps;
2677 for (unsigned i = 0; i != MaskNumElts; ++i) {
2679 if (Idx < (int)SrcNumElts)
2680 MappedOps.push_back(Idx);
2682 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2685 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2690 if (SrcNumElts > MaskNumElts) {
2691 // Analyze the access pattern of the vector to see if we can extract
2692 // two subvectors and do the shuffle. The analysis is done by calculating
2693 // the range of elements the mask access on both vectors.
2694 int MinRange[2] = { SrcNumElts+1, SrcNumElts+1};
2695 int MaxRange[2] = {-1, -1};
2697 for (unsigned i = 0; i != MaskNumElts; ++i) {
2703 if (Idx >= (int)SrcNumElts) {
2707 if (Idx > MaxRange[Input])
2708 MaxRange[Input] = Idx;
2709 if (Idx < MinRange[Input])
2710 MinRange[Input] = Idx;
2713 // Check if the access is smaller than the vector size and can we find
2714 // a reasonable extract index.
2715 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2717 int StartIdx[2]; // StartIdx to extract from
2718 for (int Input=0; Input < 2; ++Input) {
2719 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2720 RangeUse[Input] = 0; // Unused
2721 StartIdx[Input] = 0;
2722 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2723 // Fits within range but we should see if we can find a good
2724 // start index that is a multiple of the mask length.
2725 if (MaxRange[Input] < (int)MaskNumElts) {
2726 RangeUse[Input] = 1; // Extract from beginning of the vector
2727 StartIdx[Input] = 0;
2729 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2730 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2731 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2732 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2737 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2738 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2741 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2742 // Extract appropriate subvector and generate a vector shuffle
2743 for (int Input=0; Input < 2; ++Input) {
2744 SDValue &Src = Input == 0 ? Src1 : Src2;
2745 if (RangeUse[Input] == 0)
2746 Src = DAG.getUNDEF(VT);
2748 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2749 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2752 // Calculate new mask.
2753 SmallVector<int, 8> MappedOps;
2754 for (unsigned i = 0; i != MaskNumElts; ++i) {
2757 MappedOps.push_back(Idx);
2758 else if (Idx < (int)SrcNumElts)
2759 MappedOps.push_back(Idx - StartIdx[0]);
2761 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2764 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2770 // We can't use either concat vectors or extract subvectors so fall back to
2771 // replacing the shuffle with extract and build vector.
2772 // to insert and build vector.
2773 EVT EltVT = VT.getVectorElementType();
2774 EVT PtrVT = TLI.getPointerTy();
2775 SmallVector<SDValue,8> Ops;
2776 for (unsigned i = 0; i != MaskNumElts; ++i) {
2778 Ops.push_back(DAG.getUNDEF(EltVT));
2783 if (Idx < (int)SrcNumElts)
2784 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2785 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2787 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2789 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2795 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2796 VT, &Ops[0], Ops.size()));
2799 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2800 const Value *Op0 = I.getOperand(0);
2801 const Value *Op1 = I.getOperand(1);
2802 const Type *AggTy = I.getType();
2803 const Type *ValTy = Op1->getType();
2804 bool IntoUndef = isa<UndefValue>(Op0);
2805 bool FromUndef = isa<UndefValue>(Op1);
2807 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2809 SmallVector<EVT, 4> AggValueVTs;
2810 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2811 SmallVector<EVT, 4> ValValueVTs;
2812 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2814 unsigned NumAggValues = AggValueVTs.size();
2815 unsigned NumValValues = ValValueVTs.size();
2816 SmallVector<SDValue, 4> Values(NumAggValues);
2818 SDValue Agg = getValue(Op0);
2819 SDValue Val = getValue(Op1);
2821 // Copy the beginning value(s) from the original aggregate.
2822 for (; i != LinearIndex; ++i)
2823 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2824 SDValue(Agg.getNode(), Agg.getResNo() + i);
2825 // Copy values from the inserted value(s).
2826 for (; i != LinearIndex + NumValValues; ++i)
2827 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2828 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2829 // Copy remaining value(s) from the original aggregate.
2830 for (; i != NumAggValues; ++i)
2831 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2832 SDValue(Agg.getNode(), Agg.getResNo() + i);
2834 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2835 DAG.getVTList(&AggValueVTs[0], NumAggValues),
2836 &Values[0], NumAggValues));
2839 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2840 const Value *Op0 = I.getOperand(0);
2841 const Type *AggTy = Op0->getType();
2842 const Type *ValTy = I.getType();
2843 bool OutOfUndef = isa<UndefValue>(Op0);
2845 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.idx_begin(), I.idx_end());
2847 SmallVector<EVT, 4> ValValueVTs;
2848 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2850 unsigned NumValValues = ValValueVTs.size();
2851 SmallVector<SDValue, 4> Values(NumValValues);
2853 SDValue Agg = getValue(Op0);
2854 // Copy out the selected value(s).
2855 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2856 Values[i - LinearIndex] =
2858 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2859 SDValue(Agg.getNode(), Agg.getResNo() + i);
2861 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2862 DAG.getVTList(&ValValueVTs[0], NumValValues),
2863 &Values[0], NumValValues));
2866 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2867 SDValue N = getValue(I.getOperand(0));
2868 const Type *Ty = I.getOperand(0)->getType();
2870 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2872 const Value *Idx = *OI;
2873 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
2874 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
2877 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
2878 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2879 DAG.getIntPtrConstant(Offset));
2882 Ty = StTy->getElementType(Field);
2884 Ty = cast<SequentialType>(Ty)->getElementType();
2886 // If this is a constant subscript, handle it quickly.
2887 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
2888 if (CI->isZero()) continue;
2890 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
2892 EVT PTy = TLI.getPointerTy();
2893 unsigned PtrBits = PTy.getSizeInBits();
2895 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
2897 DAG.getConstant(Offs, MVT::i64));
2899 OffsVal = DAG.getIntPtrConstant(Offs);
2901 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
2906 // N = N + Idx * ElementSize;
2907 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
2908 TD->getTypeAllocSize(Ty));
2909 SDValue IdxN = getValue(Idx);
2911 // If the index is smaller or larger than intptr_t, truncate or extend
2913 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
2915 // If this is a multiply by a power of two, turn it into a shl
2916 // immediately. This is a very common case.
2917 if (ElementSize != 1) {
2918 if (ElementSize.isPowerOf2()) {
2919 unsigned Amt = ElementSize.logBase2();
2920 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
2921 N.getValueType(), IdxN,
2922 DAG.getConstant(Amt, TLI.getPointerTy()));
2924 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
2925 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
2926 N.getValueType(), IdxN, Scale);
2930 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2931 N.getValueType(), N, IdxN);
2938 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
2939 // If this is a fixed sized alloca in the entry block of the function,
2940 // allocate it statically on the stack.
2941 if (FuncInfo.StaticAllocaMap.count(&I))
2942 return; // getValue will auto-populate this.
2944 const Type *Ty = I.getAllocatedType();
2945 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
2947 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
2950 SDValue AllocSize = getValue(I.getArraySize());
2952 EVT IntPtr = TLI.getPointerTy();
2953 if (AllocSize.getValueType() != IntPtr)
2954 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
2956 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
2958 DAG.getConstant(TySize, IntPtr));
2960 // Handle alignment. If the requested alignment is less than or equal to
2961 // the stack alignment, ignore it. If the size is greater than or equal to
2962 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
2963 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
2964 if (Align <= StackAlign)
2967 // Round the size of the allocation up to the stack alignment size
2968 // by add SA-1 to the size.
2969 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
2970 AllocSize.getValueType(), AllocSize,
2971 DAG.getIntPtrConstant(StackAlign-1));
2973 // Mask out the low bits for alignment purposes.
2974 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
2975 AllocSize.getValueType(), AllocSize,
2976 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
2978 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
2979 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
2980 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
2983 DAG.setRoot(DSA.getValue(1));
2985 // Inform the Frame Information that we have just allocated a variable-sized
2987 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
2990 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
2991 const Value *SV = I.getOperand(0);
2992 SDValue Ptr = getValue(SV);
2994 const Type *Ty = I.getType();
2996 bool isVolatile = I.isVolatile();
2997 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
2998 unsigned Alignment = I.getAlignment();
2999 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3001 SmallVector<EVT, 4> ValueVTs;
3002 SmallVector<uint64_t, 4> Offsets;
3003 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3004 unsigned NumValues = ValueVTs.size();
3009 bool ConstantMemory = false;
3010 if (I.isVolatile() || NumValues > MaxParallelChains)
3011 // Serialize volatile loads with other side effects.
3013 else if (AA->pointsToConstantMemory(
3014 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3015 // Do not serialize (non-volatile) loads of constant memory with anything.
3016 Root = DAG.getEntryNode();
3017 ConstantMemory = true;
3019 // Do not serialize non-volatile loads against each other.
3020 Root = DAG.getRoot();
3023 SmallVector<SDValue, 4> Values(NumValues);
3024 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3026 EVT PtrVT = Ptr.getValueType();
3027 unsigned ChainI = 0;
3028 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3029 // Serializing loads here may result in excessive register pressure, and
3030 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3031 // could recover a bit by hoisting nodes upward in the chain by recognizing
3032 // they are side-effect free or do not alias. The optimizer should really
3033 // avoid this case by converting large object/array copies to llvm.memcpy
3034 // (MaxParallelChains should always remain as failsafe).
3035 if (ChainI == MaxParallelChains) {
3036 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3037 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3038 MVT::Other, &Chains[0], ChainI);
3042 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3044 DAG.getConstant(Offsets[i], PtrVT));
3045 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3046 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3047 isNonTemporal, Alignment, TBAAInfo);
3050 Chains[ChainI] = L.getValue(1);
3053 if (!ConstantMemory) {
3054 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3055 MVT::Other, &Chains[0], ChainI);
3059 PendingLoads.push_back(Chain);
3062 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3063 DAG.getVTList(&ValueVTs[0], NumValues),
3064 &Values[0], NumValues));
3067 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3068 const Value *SrcV = I.getOperand(0);
3069 const Value *PtrV = I.getOperand(1);
3071 SmallVector<EVT, 4> ValueVTs;
3072 SmallVector<uint64_t, 4> Offsets;
3073 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3074 unsigned NumValues = ValueVTs.size();
3078 // Get the lowered operands. Note that we do this after
3079 // checking if NumResults is zero, because with zero results
3080 // the operands won't have values in the map.
3081 SDValue Src = getValue(SrcV);
3082 SDValue Ptr = getValue(PtrV);
3084 SDValue Root = getRoot();
3085 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3087 EVT PtrVT = Ptr.getValueType();
3088 bool isVolatile = I.isVolatile();
3089 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3090 unsigned Alignment = I.getAlignment();
3091 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3093 unsigned ChainI = 0;
3094 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3095 // See visitLoad comments.
3096 if (ChainI == MaxParallelChains) {
3097 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3098 MVT::Other, &Chains[0], ChainI);
3102 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3103 DAG.getConstant(Offsets[i], PtrVT));
3104 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3105 SDValue(Src.getNode(), Src.getResNo() + i),
3106 Add, MachinePointerInfo(PtrV, Offsets[i]),
3107 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3108 Chains[ChainI] = St;
3111 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3112 MVT::Other, &Chains[0], ChainI);
3114 AssignOrderingToNode(StoreNode.getNode());
3115 DAG.setRoot(StoreNode);
3118 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3120 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3121 unsigned Intrinsic) {
3122 bool HasChain = !I.doesNotAccessMemory();
3123 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3125 // Build the operand list.
3126 SmallVector<SDValue, 8> Ops;
3127 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3129 // We don't need to serialize loads against other loads.
3130 Ops.push_back(DAG.getRoot());
3132 Ops.push_back(getRoot());
3136 // Info is set by getTgtMemInstrinsic
3137 TargetLowering::IntrinsicInfo Info;
3138 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3140 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3141 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3142 Info.opc == ISD::INTRINSIC_W_CHAIN)
3143 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy()));
3145 // Add all operands of the call to the operand list.
3146 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3147 SDValue Op = getValue(I.getArgOperand(i));
3148 assert(TLI.isTypeLegal(Op.getValueType()) &&
3149 "Intrinsic uses a non-legal type?");
3153 SmallVector<EVT, 4> ValueVTs;
3154 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3156 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
3157 assert(TLI.isTypeLegal(ValueVTs[Val]) &&
3158 "Intrinsic uses a non-legal type?");
3163 ValueVTs.push_back(MVT::Other);
3165 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3169 if (IsTgtIntrinsic) {
3170 // This is target intrinsic that touches memory
3171 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3172 VTs, &Ops[0], Ops.size(),
3174 MachinePointerInfo(Info.ptrVal, Info.offset),
3175 Info.align, Info.vol,
3176 Info.readMem, Info.writeMem);
3177 } else if (!HasChain) {
3178 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3179 VTs, &Ops[0], Ops.size());
3180 } else if (!I.getType()->isVoidTy()) {
3181 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3182 VTs, &Ops[0], Ops.size());
3184 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3185 VTs, &Ops[0], Ops.size());
3189 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3191 PendingLoads.push_back(Chain);
3196 if (!I.getType()->isVoidTy()) {
3197 if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3198 EVT VT = TLI.getValueType(PTy);
3199 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3202 setValue(&I, Result);
3206 /// GetSignificand - Get the significand and build it into a floating-point
3207 /// number with exponent of 1:
3209 /// Op = (Op & 0x007fffff) | 0x3f800000;
3211 /// where Op is the hexidecimal representation of floating point value.
3213 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3214 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3215 DAG.getConstant(0x007fffff, MVT::i32));
3216 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3217 DAG.getConstant(0x3f800000, MVT::i32));
3218 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3221 /// GetExponent - Get the exponent:
3223 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3225 /// where Op is the hexidecimal representation of floating point value.
3227 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3229 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3230 DAG.getConstant(0x7f800000, MVT::i32));
3231 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3232 DAG.getConstant(23, TLI.getPointerTy()));
3233 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3234 DAG.getConstant(127, MVT::i32));
3235 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3238 /// getF32Constant - Get 32-bit floating point constant.
3240 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3241 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3244 /// Inlined utility function to implement binary input atomic intrinsics for
3245 /// visitIntrinsicCall: I is a call instruction
3246 /// Op is the associated NodeType for I
3248 SelectionDAGBuilder::implVisitBinaryAtomic(const CallInst& I,
3250 SDValue Root = getRoot();
3252 DAG.getAtomic(Op, getCurDebugLoc(),
3253 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
3255 getValue(I.getArgOperand(0)),
3256 getValue(I.getArgOperand(1)),
3257 I.getArgOperand(0));
3259 DAG.setRoot(L.getValue(1));
3263 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3265 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3266 SDValue Op1 = getValue(I.getArgOperand(0));
3267 SDValue Op2 = getValue(I.getArgOperand(1));
3269 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3270 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3274 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3275 /// limited-precision mode.
3277 SelectionDAGBuilder::visitExp(const CallInst &I) {
3279 DebugLoc dl = getCurDebugLoc();
3281 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3282 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3283 SDValue Op = getValue(I.getArgOperand(0));
3285 // Put the exponent in the right bit position for later addition to the
3288 // #define LOG2OFe 1.4426950f
3289 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3290 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3291 getF32Constant(DAG, 0x3fb8aa3b));
3292 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3294 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3295 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3296 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3298 // IntegerPartOfX <<= 23;
3299 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3300 DAG.getConstant(23, TLI.getPointerTy()));
3302 if (LimitFloatPrecision <= 6) {
3303 // For floating-point precision of 6:
3305 // TwoToFractionalPartOfX =
3307 // (0.735607626f + 0.252464424f * x) * x;
3309 // error 0.0144103317, which is 6 bits
3310 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3311 getF32Constant(DAG, 0x3e814304));
3312 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3313 getF32Constant(DAG, 0x3f3c50c8));
3314 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3315 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3316 getF32Constant(DAG, 0x3f7f5e7e));
3317 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3319 // Add the exponent into the result in integer domain.
3320 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3321 TwoToFracPartOfX, IntegerPartOfX);
3323 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3324 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3325 // For floating-point precision of 12:
3327 // TwoToFractionalPartOfX =
3330 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3332 // 0.000107046256 error, which is 13 to 14 bits
3333 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3334 getF32Constant(DAG, 0x3da235e3));
3335 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3336 getF32Constant(DAG, 0x3e65b8f3));
3337 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3338 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3339 getF32Constant(DAG, 0x3f324b07));
3340 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3341 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3342 getF32Constant(DAG, 0x3f7ff8fd));
3343 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3345 // Add the exponent into the result in integer domain.
3346 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3347 TwoToFracPartOfX, IntegerPartOfX);
3349 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3350 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3351 // For floating-point precision of 18:
3353 // TwoToFractionalPartOfX =
3357 // (0.554906021e-1f +
3358 // (0.961591928e-2f +
3359 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3361 // error 2.47208000*10^(-7), which is better than 18 bits
3362 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3363 getF32Constant(DAG, 0x3924b03e));
3364 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3365 getF32Constant(DAG, 0x3ab24b87));
3366 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3367 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3368 getF32Constant(DAG, 0x3c1d8c17));
3369 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3370 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3371 getF32Constant(DAG, 0x3d634a1d));
3372 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3373 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3374 getF32Constant(DAG, 0x3e75fe14));
3375 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3376 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3377 getF32Constant(DAG, 0x3f317234));
3378 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3379 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3380 getF32Constant(DAG, 0x3f800000));
3381 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3384 // Add the exponent into the result in integer domain.
3385 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3386 TwoToFracPartOfX, IntegerPartOfX);
3388 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3391 // No special expansion.
3392 result = DAG.getNode(ISD::FEXP, dl,
3393 getValue(I.getArgOperand(0)).getValueType(),
3394 getValue(I.getArgOperand(0)));
3397 setValue(&I, result);
3400 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3401 /// limited-precision mode.
3403 SelectionDAGBuilder::visitLog(const CallInst &I) {
3405 DebugLoc dl = getCurDebugLoc();
3407 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3408 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3409 SDValue Op = getValue(I.getArgOperand(0));
3410 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3412 // Scale the exponent by log(2) [0.69314718f].
3413 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3414 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3415 getF32Constant(DAG, 0x3f317218));
3417 // Get the significand and build it into a floating-point number with
3419 SDValue X = GetSignificand(DAG, Op1, dl);
3421 if (LimitFloatPrecision <= 6) {
3422 // For floating-point precision of 6:
3426 // (1.4034025f - 0.23903021f * x) * x;
3428 // error 0.0034276066, which is better than 8 bits
3429 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3430 getF32Constant(DAG, 0xbe74c456));
3431 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3432 getF32Constant(DAG, 0x3fb3a2b1));
3433 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3434 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3435 getF32Constant(DAG, 0x3f949a29));
3437 result = DAG.getNode(ISD::FADD, dl,
3438 MVT::f32, LogOfExponent, LogOfMantissa);
3439 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3440 // For floating-point precision of 12:
3446 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3448 // error 0.000061011436, which is 14 bits
3449 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3450 getF32Constant(DAG, 0xbd67b6d6));
3451 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3452 getF32Constant(DAG, 0x3ee4f4b8));
3453 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3454 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3455 getF32Constant(DAG, 0x3fbc278b));
3456 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3457 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3458 getF32Constant(DAG, 0x40348e95));
3459 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3460 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3461 getF32Constant(DAG, 0x3fdef31a));
3463 result = DAG.getNode(ISD::FADD, dl,
3464 MVT::f32, LogOfExponent, LogOfMantissa);
3465 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3466 // For floating-point precision of 18:
3474 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3476 // error 0.0000023660568, which is better than 18 bits
3477 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3478 getF32Constant(DAG, 0xbc91e5ac));
3479 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3480 getF32Constant(DAG, 0x3e4350aa));
3481 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3482 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3483 getF32Constant(DAG, 0x3f60d3e3));
3484 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3485 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3486 getF32Constant(DAG, 0x4011cdf0));
3487 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3488 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3489 getF32Constant(DAG, 0x406cfd1c));
3490 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3491 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3492 getF32Constant(DAG, 0x408797cb));
3493 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3494 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3495 getF32Constant(DAG, 0x4006dcab));
3497 result = DAG.getNode(ISD::FADD, dl,
3498 MVT::f32, LogOfExponent, LogOfMantissa);
3501 // No special expansion.
3502 result = DAG.getNode(ISD::FLOG, dl,
3503 getValue(I.getArgOperand(0)).getValueType(),
3504 getValue(I.getArgOperand(0)));
3507 setValue(&I, result);
3510 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3511 /// limited-precision mode.
3513 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3515 DebugLoc dl = getCurDebugLoc();
3517 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3518 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3519 SDValue Op = getValue(I.getArgOperand(0));
3520 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3522 // Get the exponent.
3523 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3525 // Get the significand and build it into a floating-point number with
3527 SDValue X = GetSignificand(DAG, Op1, dl);
3529 // Different possible minimax approximations of significand in
3530 // floating-point for various degrees of accuracy over [1,2].
3531 if (LimitFloatPrecision <= 6) {
3532 // For floating-point precision of 6:
3534 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3536 // error 0.0049451742, which is more than 7 bits
3537 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3538 getF32Constant(DAG, 0xbeb08fe0));
3539 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3540 getF32Constant(DAG, 0x40019463));
3541 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3542 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3543 getF32Constant(DAG, 0x3fd6633d));
3545 result = DAG.getNode(ISD::FADD, dl,
3546 MVT::f32, LogOfExponent, Log2ofMantissa);
3547 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3548 // For floating-point precision of 12:
3554 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3556 // error 0.0000876136000, which is better than 13 bits
3557 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3558 getF32Constant(DAG, 0xbda7262e));
3559 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3560 getF32Constant(DAG, 0x3f25280b));
3561 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3562 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3563 getF32Constant(DAG, 0x4007b923));
3564 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3565 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3566 getF32Constant(DAG, 0x40823e2f));
3567 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3568 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3569 getF32Constant(DAG, 0x4020d29c));
3571 result = DAG.getNode(ISD::FADD, dl,
3572 MVT::f32, LogOfExponent, Log2ofMantissa);
3573 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3574 // For floating-point precision of 18:
3583 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3585 // error 0.0000018516, which is better than 18 bits
3586 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3587 getF32Constant(DAG, 0xbcd2769e));
3588 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3589 getF32Constant(DAG, 0x3e8ce0b9));
3590 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3591 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3592 getF32Constant(DAG, 0x3fa22ae7));
3593 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3594 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3595 getF32Constant(DAG, 0x40525723));
3596 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3597 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3598 getF32Constant(DAG, 0x40aaf200));
3599 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3600 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3601 getF32Constant(DAG, 0x40c39dad));
3602 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3603 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3604 getF32Constant(DAG, 0x4042902c));
3606 result = DAG.getNode(ISD::FADD, dl,
3607 MVT::f32, LogOfExponent, Log2ofMantissa);
3610 // No special expansion.
3611 result = DAG.getNode(ISD::FLOG2, dl,
3612 getValue(I.getArgOperand(0)).getValueType(),
3613 getValue(I.getArgOperand(0)));
3616 setValue(&I, result);
3619 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3620 /// limited-precision mode.
3622 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3624 DebugLoc dl = getCurDebugLoc();
3626 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3627 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3628 SDValue Op = getValue(I.getArgOperand(0));
3629 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3631 // Scale the exponent by log10(2) [0.30102999f].
3632 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3633 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3634 getF32Constant(DAG, 0x3e9a209a));
3636 // Get the significand and build it into a floating-point number with
3638 SDValue X = GetSignificand(DAG, Op1, dl);
3640 if (LimitFloatPrecision <= 6) {
3641 // For floating-point precision of 6:
3643 // Log10ofMantissa =
3645 // (0.60948995f - 0.10380950f * x) * x;
3647 // error 0.0014886165, which is 6 bits
3648 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3649 getF32Constant(DAG, 0xbdd49a13));
3650 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3651 getF32Constant(DAG, 0x3f1c0789));
3652 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3653 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3654 getF32Constant(DAG, 0x3f011300));
3656 result = DAG.getNode(ISD::FADD, dl,
3657 MVT::f32, LogOfExponent, Log10ofMantissa);
3658 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3659 // For floating-point precision of 12:
3661 // Log10ofMantissa =
3664 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
3666 // error 0.00019228036, which is better than 12 bits
3667 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3668 getF32Constant(DAG, 0x3d431f31));
3669 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3670 getF32Constant(DAG, 0x3ea21fb2));
3671 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3672 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3673 getF32Constant(DAG, 0x3f6ae232));
3674 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3675 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3676 getF32Constant(DAG, 0x3f25f7c3));
3678 result = DAG.getNode(ISD::FADD, dl,
3679 MVT::f32, LogOfExponent, Log10ofMantissa);
3680 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3681 // For floating-point precision of 18:
3683 // Log10ofMantissa =
3688 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
3690 // error 0.0000037995730, which is better than 18 bits
3691 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3692 getF32Constant(DAG, 0x3c5d51ce));
3693 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
3694 getF32Constant(DAG, 0x3e00685a));
3695 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3696 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3697 getF32Constant(DAG, 0x3efb6798));
3698 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3699 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
3700 getF32Constant(DAG, 0x3f88d192));
3701 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3702 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3703 getF32Constant(DAG, 0x3fc4316c));
3704 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3705 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
3706 getF32Constant(DAG, 0x3f57ce70));
3708 result = DAG.getNode(ISD::FADD, dl,
3709 MVT::f32, LogOfExponent, Log10ofMantissa);
3712 // No special expansion.
3713 result = DAG.getNode(ISD::FLOG10, dl,
3714 getValue(I.getArgOperand(0)).getValueType(),
3715 getValue(I.getArgOperand(0)));
3718 setValue(&I, result);
3721 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
3722 /// limited-precision mode.
3724 SelectionDAGBuilder::visitExp2(const CallInst &I) {
3726 DebugLoc dl = getCurDebugLoc();
3728 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3729 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3730 SDValue Op = getValue(I.getArgOperand(0));
3732 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
3734 // FractionalPartOfX = x - (float)IntegerPartOfX;
3735 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3736 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
3738 // IntegerPartOfX <<= 23;
3739 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3740 DAG.getConstant(23, TLI.getPointerTy()));
3742 if (LimitFloatPrecision <= 6) {
3743 // For floating-point precision of 6:
3745 // TwoToFractionalPartOfX =
3747 // (0.735607626f + 0.252464424f * x) * x;
3749 // error 0.0144103317, which is 6 bits
3750 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3751 getF32Constant(DAG, 0x3e814304));
3752 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3753 getF32Constant(DAG, 0x3f3c50c8));
3754 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3755 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3756 getF32Constant(DAG, 0x3f7f5e7e));
3757 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3758 SDValue TwoToFractionalPartOfX =
3759 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3761 result = DAG.getNode(ISD::BITCAST, dl,
3762 MVT::f32, TwoToFractionalPartOfX);
3763 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3764 // For floating-point precision of 12:
3766 // TwoToFractionalPartOfX =
3769 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3771 // error 0.000107046256, which is 13 to 14 bits
3772 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3773 getF32Constant(DAG, 0x3da235e3));
3774 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3775 getF32Constant(DAG, 0x3e65b8f3));
3776 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3777 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3778 getF32Constant(DAG, 0x3f324b07));
3779 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3780 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3781 getF32Constant(DAG, 0x3f7ff8fd));
3782 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3783 SDValue TwoToFractionalPartOfX =
3784 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3786 result = DAG.getNode(ISD::BITCAST, dl,
3787 MVT::f32, TwoToFractionalPartOfX);
3788 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3789 // For floating-point precision of 18:
3791 // TwoToFractionalPartOfX =
3795 // (0.554906021e-1f +
3796 // (0.961591928e-2f +
3797 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3798 // error 2.47208000*10^(-7), which is better than 18 bits
3799 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3800 getF32Constant(DAG, 0x3924b03e));
3801 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3802 getF32Constant(DAG, 0x3ab24b87));
3803 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3804 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3805 getF32Constant(DAG, 0x3c1d8c17));
3806 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3807 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3808 getF32Constant(DAG, 0x3d634a1d));
3809 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3810 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3811 getF32Constant(DAG, 0x3e75fe14));
3812 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3813 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3814 getF32Constant(DAG, 0x3f317234));
3815 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3816 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3817 getF32Constant(DAG, 0x3f800000));
3818 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3819 SDValue TwoToFractionalPartOfX =
3820 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3822 result = DAG.getNode(ISD::BITCAST, dl,
3823 MVT::f32, TwoToFractionalPartOfX);
3826 // No special expansion.
3827 result = DAG.getNode(ISD::FEXP2, dl,
3828 getValue(I.getArgOperand(0)).getValueType(),
3829 getValue(I.getArgOperand(0)));
3832 setValue(&I, result);
3835 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
3836 /// limited-precision mode with x == 10.0f.
3838 SelectionDAGBuilder::visitPow(const CallInst &I) {
3840 const Value *Val = I.getArgOperand(0);
3841 DebugLoc dl = getCurDebugLoc();
3842 bool IsExp10 = false;
3844 if (getValue(Val).getValueType() == MVT::f32 &&
3845 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
3846 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3847 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
3848 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
3850 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
3855 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3856 SDValue Op = getValue(I.getArgOperand(1));
3858 // Put the exponent in the right bit position for later addition to the
3861 // #define LOG2OF10 3.3219281f
3862 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
3863 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3864 getF32Constant(DAG, 0x40549a78));
3865 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3867 // FractionalPartOfX = x - (float)IntegerPartOfX;
3868 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3869 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3871 // IntegerPartOfX <<= 23;
3872 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3873 DAG.getConstant(23, TLI.getPointerTy()));
3875 if (LimitFloatPrecision <= 6) {
3876 // For floating-point precision of 6:
3878 // twoToFractionalPartOfX =
3880 // (0.735607626f + 0.252464424f * x) * x;
3882 // error 0.0144103317, which is 6 bits
3883 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3884 getF32Constant(DAG, 0x3e814304));
3885 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3886 getF32Constant(DAG, 0x3f3c50c8));
3887 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3888 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3889 getF32Constant(DAG, 0x3f7f5e7e));
3890 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
3891 SDValue TwoToFractionalPartOfX =
3892 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
3894 result = DAG.getNode(ISD::BITCAST, dl,
3895 MVT::f32, TwoToFractionalPartOfX);
3896 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3897 // For floating-point precision of 12:
3899 // TwoToFractionalPartOfX =
3902 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3904 // error 0.000107046256, which is 13 to 14 bits
3905 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3906 getF32Constant(DAG, 0x3da235e3));
3907 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3908 getF32Constant(DAG, 0x3e65b8f3));
3909 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3910 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3911 getF32Constant(DAG, 0x3f324b07));
3912 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3913 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3914 getF32Constant(DAG, 0x3f7ff8fd));
3915 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
3916 SDValue TwoToFractionalPartOfX =
3917 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
3919 result = DAG.getNode(ISD::BITCAST, dl,
3920 MVT::f32, TwoToFractionalPartOfX);
3921 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3922 // For floating-point precision of 18:
3924 // TwoToFractionalPartOfX =
3928 // (0.554906021e-1f +
3929 // (0.961591928e-2f +
3930 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3931 // error 2.47208000*10^(-7), which is better than 18 bits
3932 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3933 getF32Constant(DAG, 0x3924b03e));
3934 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3935 getF32Constant(DAG, 0x3ab24b87));
3936 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3937 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3938 getF32Constant(DAG, 0x3c1d8c17));
3939 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3940 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3941 getF32Constant(DAG, 0x3d634a1d));
3942 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3943 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3944 getF32Constant(DAG, 0x3e75fe14));
3945 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3946 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3947 getF32Constant(DAG, 0x3f317234));
3948 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3949 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3950 getF32Constant(DAG, 0x3f800000));
3951 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
3952 SDValue TwoToFractionalPartOfX =
3953 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
3955 result = DAG.getNode(ISD::BITCAST, dl,
3956 MVT::f32, TwoToFractionalPartOfX);
3959 // No special expansion.
3960 result = DAG.getNode(ISD::FPOW, dl,
3961 getValue(I.getArgOperand(0)).getValueType(),
3962 getValue(I.getArgOperand(0)),
3963 getValue(I.getArgOperand(1)));
3966 setValue(&I, result);
3970 /// ExpandPowI - Expand a llvm.powi intrinsic.
3971 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
3972 SelectionDAG &DAG) {
3973 // If RHS is a constant, we can expand this out to a multiplication tree,
3974 // otherwise we end up lowering to a call to __powidf2 (for example). When
3975 // optimizing for size, we only want to do this if the expansion would produce
3976 // a small number of multiplies, otherwise we do the full expansion.
3977 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3978 // Get the exponent as a positive value.
3979 unsigned Val = RHSC->getSExtValue();
3980 if ((int)Val < 0) Val = -Val;
3982 // powi(x, 0) -> 1.0
3984 return DAG.getConstantFP(1.0, LHS.getValueType());
3986 const Function *F = DAG.getMachineFunction().getFunction();
3987 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
3988 // If optimizing for size, don't insert too many multiplies. This
3989 // inserts up to 5 multiplies.
3990 CountPopulation_32(Val)+Log2_32(Val) < 7) {
3991 // We use the simple binary decomposition method to generate the multiply
3992 // sequence. There are more optimal ways to do this (for example,
3993 // powi(x,15) generates one more multiply than it should), but this has
3994 // the benefit of being both really simple and much better than a libcall.
3995 SDValue Res; // Logically starts equal to 1.0
3996 SDValue CurSquare = LHS;
4000 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4002 Res = CurSquare; // 1.0*CurSquare.
4005 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4006 CurSquare, CurSquare);
4010 // If the original was negative, invert the result, producing 1/(x*x*x).
4011 if (RHSC->getSExtValue() < 0)
4012 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4013 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4018 // Otherwise, expand to a libcall.
4019 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4022 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4023 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4024 /// At the end of instruction selection, they will be inserted to the entry BB.
4026 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4029 const Argument *Arg = dyn_cast<Argument>(V);
4033 MachineFunction &MF = DAG.getMachineFunction();
4034 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4035 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4037 // Ignore inlined function arguments here.
4038 DIVariable DV(Variable);
4039 if (DV.isInlinedFnArgument(MF.getFunction()))
4042 MachineBasicBlock *MBB = FuncInfo.MBB;
4043 if (MBB != &MF.front())
4047 if (Arg->hasByValAttr()) {
4048 // Byval arguments' frame index is recorded during argument lowering.
4049 // Use this info directly.
4050 Reg = TRI->getFrameRegister(MF);
4051 Offset = FuncInfo.getByValArgumentFrameIndex(Arg);
4052 // If byval argument ofset is not recorded then ignore this.
4057 if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) {
4058 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4059 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4060 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4061 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4068 // Check if ValueMap has reg number.
4069 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4070 if (VMI != FuncInfo.ValueMap.end())
4074 if (!Reg && N.getNode()) {
4075 // Check if frame index is available.
4076 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4077 if (FrameIndexSDNode *FINode =
4078 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4079 Reg = TRI->getFrameRegister(MF);
4080 Offset = FINode->getIndex();
4087 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4088 TII->get(TargetOpcode::DBG_VALUE))
4089 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4090 FuncInfo.ArgDbgValues.push_back(&*MIB);
4094 // VisualStudio defines setjmp as _setjmp
4095 #if defined(_MSC_VER) && defined(setjmp) && \
4096 !defined(setjmp_undefined_for_msvc)
4097 # pragma push_macro("setjmp")
4099 # define setjmp_undefined_for_msvc
4102 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4103 /// we want to emit this as a call to a named external function, return the name
4104 /// otherwise lower it and return null.
4106 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4107 DebugLoc dl = getCurDebugLoc();
4110 switch (Intrinsic) {
4112 // By default, turn this into a target intrinsic node.
4113 visitTargetIntrinsic(I, Intrinsic);
4115 case Intrinsic::vastart: visitVAStart(I); return 0;
4116 case Intrinsic::vaend: visitVAEnd(I); return 0;
4117 case Intrinsic::vacopy: visitVACopy(I); return 0;
4118 case Intrinsic::returnaddress:
4119 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4120 getValue(I.getArgOperand(0))));
4122 case Intrinsic::frameaddress:
4123 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4124 getValue(I.getArgOperand(0))));
4126 case Intrinsic::setjmp:
4127 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4128 case Intrinsic::longjmp:
4129 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4130 case Intrinsic::memcpy: {
4131 // Assert for address < 256 since we support only user defined address
4133 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4135 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4137 "Unknown address space");
4138 SDValue Op1 = getValue(I.getArgOperand(0));
4139 SDValue Op2 = getValue(I.getArgOperand(1));
4140 SDValue Op3 = getValue(I.getArgOperand(2));
4141 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4142 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4143 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4144 MachinePointerInfo(I.getArgOperand(0)),
4145 MachinePointerInfo(I.getArgOperand(1))));
4148 case Intrinsic::memset: {
4149 // Assert for address < 256 since we support only user defined address
4151 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4153 "Unknown address space");
4154 SDValue Op1 = getValue(I.getArgOperand(0));
4155 SDValue Op2 = getValue(I.getArgOperand(1));
4156 SDValue Op3 = getValue(I.getArgOperand(2));
4157 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4158 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4159 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4160 MachinePointerInfo(I.getArgOperand(0))));
4163 case Intrinsic::memmove: {
4164 // Assert for address < 256 since we support only user defined address
4166 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4168 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4170 "Unknown address space");
4171 SDValue Op1 = getValue(I.getArgOperand(0));
4172 SDValue Op2 = getValue(I.getArgOperand(1));
4173 SDValue Op3 = getValue(I.getArgOperand(2));
4174 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4175 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4176 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4177 MachinePointerInfo(I.getArgOperand(0)),
4178 MachinePointerInfo(I.getArgOperand(1))));
4181 case Intrinsic::dbg_declare: {
4182 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4183 MDNode *Variable = DI.getVariable();
4184 const Value *Address = DI.getAddress();
4185 if (!Address || !DIVariable(DI.getVariable()).Verify())
4188 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4189 // but do not always have a corresponding SDNode built. The SDNodeOrder
4190 // absolute, but not relative, values are different depending on whether
4191 // debug info exists.
4194 // Check if address has undef value.
4195 if (isa<UndefValue>(Address) ||
4196 (Address->use_empty() && !isa<Argument>(Address))) {
4197 DEBUG(dbgs() << "Dropping debug info for " << DI);
4201 SDValue &N = NodeMap[Address];
4202 if (!N.getNode() && isa<Argument>(Address))
4203 // Check unused arguments map.
4204 N = UnusedArgNodeMap[Address];
4207 // Parameters are handled specially.
4209 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4210 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4211 Address = BCI->getOperand(0);
4212 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4214 if (isParameter && !AI) {
4215 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4217 // Byval parameter. We have a frame index at this point.
4218 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4219 0, dl, SDNodeOrder);
4221 // Can't do anything with other non-AI cases yet. This might be a
4222 // parameter of a callee function that got inlined, for example.
4223 DEBUG(dbgs() << "Dropping debug info for " << DI);
4227 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4228 0, dl, SDNodeOrder);
4230 // Can't do anything with other non-AI cases yet.
4231 DEBUG(dbgs() << "Dropping debug info for " << DI);
4234 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4236 // If Address is an argument then try to emit its dbg value using
4237 // virtual register info from the FuncInfo.ValueMap.
4238 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4239 // If variable is pinned by a alloca in dominating bb then
4240 // use StaticAllocaMap.
4241 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4242 if (AI->getParent() != DI.getParent()) {
4243 DenseMap<const AllocaInst*, int>::iterator SI =
4244 FuncInfo.StaticAllocaMap.find(AI);
4245 if (SI != FuncInfo.StaticAllocaMap.end()) {
4246 SDV = DAG.getDbgValue(Variable, SI->second,
4247 0, dl, SDNodeOrder);
4248 DAG.AddDbgValue(SDV, 0, false);
4253 DEBUG(dbgs() << "Dropping debug info for " << DI);
4258 case Intrinsic::dbg_value: {
4259 const DbgValueInst &DI = cast<DbgValueInst>(I);
4260 if (!DIVariable(DI.getVariable()).Verify())
4263 MDNode *Variable = DI.getVariable();
4264 uint64_t Offset = DI.getOffset();
4265 const Value *V = DI.getValue();
4269 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4270 // but do not always have a corresponding SDNode built. The SDNodeOrder
4271 // absolute, but not relative, values are different depending on whether
4272 // debug info exists.
4275 if (isa<ConstantInt>(V) || isa<ConstantFP>(V)) {
4276 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4277 DAG.AddDbgValue(SDV, 0, false);
4279 // Do not use getValue() in here; we don't want to generate code at
4280 // this point if it hasn't been done yet.
4281 SDValue N = NodeMap[V];
4282 if (!N.getNode() && isa<Argument>(V))
4283 // Check unused arguments map.
4284 N = UnusedArgNodeMap[V];
4286 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4287 SDV = DAG.getDbgValue(Variable, N.getNode(),
4288 N.getResNo(), Offset, dl, SDNodeOrder);
4289 DAG.AddDbgValue(SDV, N.getNode(), false);
4291 } else if (!V->use_empty() ) {
4292 // Do not call getValue(V) yet, as we don't want to generate code.
4293 // Remember it for later.
4294 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4295 DanglingDebugInfoMap[V] = DDI;
4297 // We may expand this to cover more cases. One case where we have no
4298 // data available is an unreferenced parameter.
4299 DEBUG(dbgs() << "Dropping debug info for " << DI);
4303 // Build a debug info table entry.
4304 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4305 V = BCI->getOperand(0);
4306 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4307 // Don't handle byval struct arguments or VLAs, for example.
4310 DenseMap<const AllocaInst*, int>::iterator SI =
4311 FuncInfo.StaticAllocaMap.find(AI);
4312 if (SI == FuncInfo.StaticAllocaMap.end())
4314 int FI = SI->second;
4316 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4317 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4318 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4321 case Intrinsic::eh_exception: {
4322 // Insert the EXCEPTIONADDR instruction.
4323 assert(FuncInfo.MBB->isLandingPad() &&
4324 "Call to eh.exception not in landing pad!");
4325 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4327 Ops[0] = DAG.getRoot();
4328 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
4330 DAG.setRoot(Op.getValue(1));
4334 case Intrinsic::eh_selector: {
4335 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4336 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4337 if (CallMBB->isLandingPad())
4338 AddCatchInfo(I, &MMI, CallMBB);
4341 FuncInfo.CatchInfoLost.insert(&I);
4343 // FIXME: Mark exception selector register as live in. Hack for PR1508.
4344 unsigned Reg = TLI.getExceptionSelectorRegister();
4345 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4348 // Insert the EHSELECTION instruction.
4349 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
4351 Ops[0] = getValue(I.getArgOperand(0));
4353 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2);
4354 DAG.setRoot(Op.getValue(1));
4355 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32));
4359 case Intrinsic::eh_typeid_for: {
4360 // Find the type id for the given typeinfo.
4361 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4362 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4363 Res = DAG.getConstant(TypeID, MVT::i32);
4368 case Intrinsic::eh_return_i32:
4369 case Intrinsic::eh_return_i64:
4370 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4371 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4374 getValue(I.getArgOperand(0)),
4375 getValue(I.getArgOperand(1))));
4377 case Intrinsic::eh_unwind_init:
4378 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4380 case Intrinsic::eh_dwarf_cfa: {
4381 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4382 TLI.getPointerTy());
4383 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4385 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4386 TLI.getPointerTy()),
4388 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4390 DAG.getConstant(0, TLI.getPointerTy()));
4391 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4395 case Intrinsic::eh_sjlj_callsite: {
4396 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4397 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4398 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4399 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4401 MMI.setCurrentCallSite(CI->getZExtValue());
4404 case Intrinsic::eh_sjlj_setjmp: {
4405 setValue(&I, DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, MVT::i32, getRoot(),
4406 getValue(I.getArgOperand(0))));
4409 case Intrinsic::eh_sjlj_longjmp: {
4410 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4411 getRoot(), getValue(I.getArgOperand(0))));
4414 case Intrinsic::eh_sjlj_dispatch_setup: {
4415 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
4416 getRoot(), getValue(I.getArgOperand(0))));
4420 case Intrinsic::x86_mmx_pslli_w:
4421 case Intrinsic::x86_mmx_pslli_d:
4422 case Intrinsic::x86_mmx_pslli_q:
4423 case Intrinsic::x86_mmx_psrli_w:
4424 case Intrinsic::x86_mmx_psrli_d:
4425 case Intrinsic::x86_mmx_psrli_q:
4426 case Intrinsic::x86_mmx_psrai_w:
4427 case Intrinsic::x86_mmx_psrai_d: {
4428 SDValue ShAmt = getValue(I.getArgOperand(1));
4429 if (isa<ConstantSDNode>(ShAmt)) {
4430 visitTargetIntrinsic(I, Intrinsic);
4433 unsigned NewIntrinsic = 0;
4434 EVT ShAmtVT = MVT::v2i32;
4435 switch (Intrinsic) {
4436 case Intrinsic::x86_mmx_pslli_w:
4437 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4439 case Intrinsic::x86_mmx_pslli_d:
4440 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4442 case Intrinsic::x86_mmx_pslli_q:
4443 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4445 case Intrinsic::x86_mmx_psrli_w:
4446 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4448 case Intrinsic::x86_mmx_psrli_d:
4449 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4451 case Intrinsic::x86_mmx_psrli_q:
4452 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4454 case Intrinsic::x86_mmx_psrai_w:
4455 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4457 case Intrinsic::x86_mmx_psrai_d:
4458 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4460 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4463 // The vector shift intrinsics with scalars uses 32b shift amounts but
4464 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4466 // We must do this early because v2i32 is not a legal type.
4467 DebugLoc dl = getCurDebugLoc();
4470 ShOps[1] = DAG.getConstant(0, MVT::i32);
4471 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4472 EVT DestVT = TLI.getValueType(I.getType());
4473 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4474 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4475 DAG.getConstant(NewIntrinsic, MVT::i32),
4476 getValue(I.getArgOperand(0)), ShAmt);
4480 case Intrinsic::convertff:
4481 case Intrinsic::convertfsi:
4482 case Intrinsic::convertfui:
4483 case Intrinsic::convertsif:
4484 case Intrinsic::convertuif:
4485 case Intrinsic::convertss:
4486 case Intrinsic::convertsu:
4487 case Intrinsic::convertus:
4488 case Intrinsic::convertuu: {
4489 ISD::CvtCode Code = ISD::CVT_INVALID;
4490 switch (Intrinsic) {
4491 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4492 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4493 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4494 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4495 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4496 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4497 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4498 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4499 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4501 EVT DestVT = TLI.getValueType(I.getType());
4502 const Value *Op1 = I.getArgOperand(0);
4503 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4504 DAG.getValueType(DestVT),
4505 DAG.getValueType(getValue(Op1).getValueType()),
4506 getValue(I.getArgOperand(1)),
4507 getValue(I.getArgOperand(2)),
4512 case Intrinsic::sqrt:
4513 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4514 getValue(I.getArgOperand(0)).getValueType(),
4515 getValue(I.getArgOperand(0))));
4517 case Intrinsic::powi:
4518 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4519 getValue(I.getArgOperand(1)), DAG));
4521 case Intrinsic::sin:
4522 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4523 getValue(I.getArgOperand(0)).getValueType(),
4524 getValue(I.getArgOperand(0))));
4526 case Intrinsic::cos:
4527 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4528 getValue(I.getArgOperand(0)).getValueType(),
4529 getValue(I.getArgOperand(0))));
4531 case Intrinsic::log:
4534 case Intrinsic::log2:
4537 case Intrinsic::log10:
4540 case Intrinsic::exp:
4543 case Intrinsic::exp2:
4546 case Intrinsic::pow:
4549 case Intrinsic::convert_to_fp16:
4550 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4551 MVT::i16, getValue(I.getArgOperand(0))));
4553 case Intrinsic::convert_from_fp16:
4554 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4555 MVT::f32, getValue(I.getArgOperand(0))));
4557 case Intrinsic::pcmarker: {
4558 SDValue Tmp = getValue(I.getArgOperand(0));
4559 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4562 case Intrinsic::readcyclecounter: {
4563 SDValue Op = getRoot();
4564 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4565 DAG.getVTList(MVT::i64, MVT::Other),
4568 DAG.setRoot(Res.getValue(1));
4571 case Intrinsic::bswap:
4572 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4573 getValue(I.getArgOperand(0)).getValueType(),
4574 getValue(I.getArgOperand(0))));
4576 case Intrinsic::cttz: {
4577 SDValue Arg = getValue(I.getArgOperand(0));
4578 EVT Ty = Arg.getValueType();
4579 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg));
4582 case Intrinsic::ctlz: {
4583 SDValue Arg = getValue(I.getArgOperand(0));
4584 EVT Ty = Arg.getValueType();
4585 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg));
4588 case Intrinsic::ctpop: {
4589 SDValue Arg = getValue(I.getArgOperand(0));
4590 EVT Ty = Arg.getValueType();
4591 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4594 case Intrinsic::stacksave: {
4595 SDValue Op = getRoot();
4596 Res = DAG.getNode(ISD::STACKSAVE, dl,
4597 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4599 DAG.setRoot(Res.getValue(1));
4602 case Intrinsic::stackrestore: {
4603 Res = getValue(I.getArgOperand(0));
4604 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4607 case Intrinsic::stackprotector: {
4608 // Emit code into the DAG to store the stack guard onto the stack.
4609 MachineFunction &MF = DAG.getMachineFunction();
4610 MachineFrameInfo *MFI = MF.getFrameInfo();
4611 EVT PtrTy = TLI.getPointerTy();
4613 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4614 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4616 int FI = FuncInfo.StaticAllocaMap[Slot];
4617 MFI->setStackProtectorIndex(FI);
4619 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4621 // Store the stack protector onto the stack.
4622 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4623 MachinePointerInfo::getFixedStack(FI),
4629 case Intrinsic::objectsize: {
4630 // If we don't know by now, we're never going to know.
4631 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4633 assert(CI && "Non-constant type in __builtin_object_size?");
4635 SDValue Arg = getValue(I.getCalledValue());
4636 EVT Ty = Arg.getValueType();
4639 Res = DAG.getConstant(-1ULL, Ty);
4641 Res = DAG.getConstant(0, Ty);
4646 case Intrinsic::var_annotation:
4647 // Discard annotate attributes
4650 case Intrinsic::init_trampoline: {
4651 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
4655 Ops[1] = getValue(I.getArgOperand(0));
4656 Ops[2] = getValue(I.getArgOperand(1));
4657 Ops[3] = getValue(I.getArgOperand(2));
4658 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
4659 Ops[5] = DAG.getSrcValue(F);
4661 Res = DAG.getNode(ISD::TRAMPOLINE, dl,
4662 DAG.getVTList(TLI.getPointerTy(), MVT::Other),
4666 DAG.setRoot(Res.getValue(1));
4669 case Intrinsic::gcroot:
4671 const Value *Alloca = I.getArgOperand(0);
4672 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
4674 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
4675 GFI->addStackRoot(FI->getIndex(), TypeMap);
4678 case Intrinsic::gcread:
4679 case Intrinsic::gcwrite:
4680 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
4682 case Intrinsic::flt_rounds:
4683 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
4685 case Intrinsic::trap:
4686 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
4688 case Intrinsic::uadd_with_overflow:
4689 return implVisitAluOverflow(I, ISD::UADDO);
4690 case Intrinsic::sadd_with_overflow:
4691 return implVisitAluOverflow(I, ISD::SADDO);
4692 case Intrinsic::usub_with_overflow:
4693 return implVisitAluOverflow(I, ISD::USUBO);
4694 case Intrinsic::ssub_with_overflow:
4695 return implVisitAluOverflow(I, ISD::SSUBO);
4696 case Intrinsic::umul_with_overflow:
4697 return implVisitAluOverflow(I, ISD::UMULO);
4698 case Intrinsic::smul_with_overflow:
4699 return implVisitAluOverflow(I, ISD::SMULO);
4701 case Intrinsic::prefetch: {
4703 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
4705 Ops[1] = getValue(I.getArgOperand(0));
4706 Ops[2] = getValue(I.getArgOperand(1));
4707 Ops[3] = getValue(I.getArgOperand(2));
4708 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
4709 DAG.getVTList(MVT::Other),
4711 EVT::getIntegerVT(*Context, 8),
4712 MachinePointerInfo(I.getArgOperand(0)),
4714 false, /* volatile */
4716 rw==1)); /* write */
4719 case Intrinsic::memory_barrier: {
4722 for (int x = 1; x < 6; ++x)
4723 Ops[x] = getValue(I.getArgOperand(x - 1));
4725 DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
4728 case Intrinsic::atomic_cmp_swap: {
4729 SDValue Root = getRoot();
4731 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, getCurDebugLoc(),
4732 getValue(I.getArgOperand(1)).getValueType().getSimpleVT(),
4734 getValue(I.getArgOperand(0)),
4735 getValue(I.getArgOperand(1)),
4736 getValue(I.getArgOperand(2)),
4737 MachinePointerInfo(I.getArgOperand(0)));
4739 DAG.setRoot(L.getValue(1));
4742 case Intrinsic::atomic_load_add:
4743 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_ADD);
4744 case Intrinsic::atomic_load_sub:
4745 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_SUB);
4746 case Intrinsic::atomic_load_or:
4747 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_OR);
4748 case Intrinsic::atomic_load_xor:
4749 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_XOR);
4750 case Intrinsic::atomic_load_and:
4751 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_AND);
4752 case Intrinsic::atomic_load_nand:
4753 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_NAND);
4754 case Intrinsic::atomic_load_max:
4755 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MAX);
4756 case Intrinsic::atomic_load_min:
4757 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_MIN);
4758 case Intrinsic::atomic_load_umin:
4759 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMIN);
4760 case Intrinsic::atomic_load_umax:
4761 return implVisitBinaryAtomic(I, ISD::ATOMIC_LOAD_UMAX);
4762 case Intrinsic::atomic_swap:
4763 return implVisitBinaryAtomic(I, ISD::ATOMIC_SWAP);
4765 case Intrinsic::invariant_start:
4766 case Intrinsic::lifetime_start:
4767 // Discard region information.
4768 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
4770 case Intrinsic::invariant_end:
4771 case Intrinsic::lifetime_end:
4772 // Discard region information.
4777 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
4779 MachineBasicBlock *LandingPad) {
4780 const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
4781 const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
4782 const Type *RetTy = FTy->getReturnType();
4783 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4784 MCSymbol *BeginLabel = 0;
4786 TargetLowering::ArgListTy Args;
4787 TargetLowering::ArgListEntry Entry;
4788 Args.reserve(CS.arg_size());
4790 // Check whether the function can return without sret-demotion.
4791 SmallVector<ISD::OutputArg, 4> Outs;
4792 SmallVector<uint64_t, 4> Offsets;
4793 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4794 Outs, TLI, &Offsets);
4796 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4797 FTy->isVarArg(), Outs, FTy->getContext());
4799 SDValue DemoteStackSlot;
4800 int DemoteStackIdx = -100;
4802 if (!CanLowerReturn) {
4803 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
4804 FTy->getReturnType());
4805 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
4806 FTy->getReturnType());
4807 MachineFunction &MF = DAG.getMachineFunction();
4808 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
4809 const Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
4811 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
4812 Entry.Node = DemoteStackSlot;
4813 Entry.Ty = StackSlotPtrType;
4814 Entry.isSExt = false;
4815 Entry.isZExt = false;
4816 Entry.isInReg = false;
4817 Entry.isSRet = true;
4818 Entry.isNest = false;
4819 Entry.isByVal = false;
4820 Entry.Alignment = Align;
4821 Args.push_back(Entry);
4822 RetTy = Type::getVoidTy(FTy->getContext());
4825 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
4827 SDValue ArgNode = getValue(*i);
4828 Entry.Node = ArgNode; Entry.Ty = (*i)->getType();
4830 unsigned attrInd = i - CS.arg_begin() + 1;
4831 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
4832 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
4833 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
4834 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
4835 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
4836 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
4837 Entry.Alignment = CS.getParamAlignment(attrInd);
4838 Args.push_back(Entry);
4842 // Insert a label before the invoke call to mark the try range. This can be
4843 // used to detect deletion of the invoke via the MachineModuleInfo.
4844 BeginLabel = MMI.getContext().CreateTempSymbol();
4846 // For SjLj, keep track of which landing pads go with which invokes
4847 // so as to maintain the ordering of pads in the LSDA.
4848 unsigned CallSiteIndex = MMI.getCurrentCallSite();
4849 if (CallSiteIndex) {
4850 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
4851 // Now that the call site is handled, stop tracking it.
4852 MMI.setCurrentCallSite(0);
4855 // Both PendingLoads and PendingExports must be flushed here;
4856 // this call might not return.
4858 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
4861 // Check if target-independent constraints permit a tail call here.
4862 // Target-dependent constraints are checked within TLI.LowerCallTo.
4864 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
4867 // If there's a possibility that fast-isel has already selected some amount
4868 // of the current basic block, don't emit a tail call.
4869 if (isTailCall && EnableFastISel)
4872 std::pair<SDValue,SDValue> Result =
4873 TLI.LowerCallTo(getRoot(), RetTy,
4874 CS.paramHasAttr(0, Attribute::SExt),
4875 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
4876 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
4877 CS.getCallingConv(),
4879 !CS.getInstruction()->use_empty(),
4880 Callee, Args, DAG, getCurDebugLoc());
4881 assert((isTailCall || Result.second.getNode()) &&
4882 "Non-null chain expected with non-tail call!");
4883 assert((Result.second.getNode() || !Result.first.getNode()) &&
4884 "Null value expected with tail call!");
4885 if (Result.first.getNode()) {
4886 setValue(CS.getInstruction(), Result.first);
4887 } else if (!CanLowerReturn && Result.second.getNode()) {
4888 // The instruction result is the result of loading from the
4889 // hidden sret parameter.
4890 SmallVector<EVT, 1> PVTs;
4891 const Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
4893 ComputeValueVTs(TLI, PtrRetTy, PVTs);
4894 assert(PVTs.size() == 1 && "Pointers should fit in one register");
4895 EVT PtrVT = PVTs[0];
4896 unsigned NumValues = Outs.size();
4897 SmallVector<SDValue, 4> Values(NumValues);
4898 SmallVector<SDValue, 4> Chains(NumValues);
4900 for (unsigned i = 0; i < NumValues; ++i) {
4901 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
4903 DAG.getConstant(Offsets[i], PtrVT));
4904 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4906 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
4909 Chains[i] = L.getValue(1);
4912 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
4913 MVT::Other, &Chains[0], NumValues);
4914 PendingLoads.push_back(Chain);
4916 // Collect the legal value parts into potentially illegal values
4917 // that correspond to the original function's return values.
4918 SmallVector<EVT, 4> RetTys;
4919 RetTy = FTy->getReturnType();
4920 ComputeValueVTs(TLI, RetTy, RetTys);
4921 ISD::NodeType AssertOp = ISD::DELETED_NODE;
4922 SmallVector<SDValue, 4> ReturnValues;
4923 unsigned CurReg = 0;
4924 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
4926 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
4927 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
4929 SDValue ReturnValue =
4930 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
4931 RegisterVT, VT, AssertOp);
4932 ReturnValues.push_back(ReturnValue);
4936 setValue(CS.getInstruction(),
4937 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
4938 DAG.getVTList(&RetTys[0], RetTys.size()),
4939 &ReturnValues[0], ReturnValues.size()));
4943 // As a special case, a null chain means that a tail call has been emitted and
4944 // the DAG root is already updated.
4945 if (Result.second.getNode())
4946 DAG.setRoot(Result.second);
4951 // Insert a label at the end of the invoke call to mark the try range. This
4952 // can be used to detect deletion of the invoke via the MachineModuleInfo.
4953 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
4954 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
4956 // Inform MachineModuleInfo of range.
4957 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
4961 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
4962 /// value is equal or not-equal to zero.
4963 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
4964 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
4966 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
4967 if (IC->isEquality())
4968 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
4969 if (C->isNullValue())
4971 // Unknown instruction.
4977 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
4979 SelectionDAGBuilder &Builder) {
4981 // Check to see if this load can be trivially constant folded, e.g. if the
4982 // input is from a string literal.
4983 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
4984 // Cast pointer to the type we really want to load.
4985 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
4986 PointerType::getUnqual(LoadTy));
4988 if (const Constant *LoadCst =
4989 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
4991 return Builder.getValue(LoadCst);
4994 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
4995 // still constant memory, the input chain can be the entry node.
4997 bool ConstantMemory = false;
4999 // Do not serialize (non-volatile) loads of constant memory with anything.
5000 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5001 Root = Builder.DAG.getEntryNode();
5002 ConstantMemory = true;
5004 // Do not serialize non-volatile loads against each other.
5005 Root = Builder.DAG.getRoot();
5008 SDValue Ptr = Builder.getValue(PtrVal);
5009 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5010 Ptr, MachinePointerInfo(PtrVal),
5012 false /*nontemporal*/, 1 /* align=1 */);
5014 if (!ConstantMemory)
5015 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5020 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5021 /// If so, return true and lower it, otherwise return false and it will be
5022 /// lowered like a normal call.
5023 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5024 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5025 if (I.getNumArgOperands() != 3)
5028 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5029 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5030 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5031 !I.getType()->isIntegerTy())
5034 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5036 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5037 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5038 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5039 bool ActuallyDoIt = true;
5042 switch (Size->getZExtValue()) {
5044 LoadVT = MVT::Other;
5046 ActuallyDoIt = false;
5050 LoadTy = Type::getInt16Ty(Size->getContext());
5054 LoadTy = Type::getInt32Ty(Size->getContext());
5058 LoadTy = Type::getInt64Ty(Size->getContext());
5062 LoadVT = MVT::v4i32;
5063 LoadTy = Type::getInt32Ty(Size->getContext());
5064 LoadTy = VectorType::get(LoadTy, 4);
5069 // This turns into unaligned loads. We only do this if the target natively
5070 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5071 // we'll only produce a small number of byte loads.
5073 // Require that we can find a legal MVT, and only do this if the target
5074 // supports unaligned loads of that type. Expanding into byte loads would
5076 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5077 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5078 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5079 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5080 ActuallyDoIt = false;
5084 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5085 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5087 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5089 EVT CallVT = TLI.getValueType(I.getType(), true);
5090 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5100 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5101 // Handle inline assembly differently.
5102 if (isa<InlineAsm>(I.getCalledValue())) {
5107 // See if any floating point values are being passed to this function. This is
5108 // used to emit an undefined reference to fltused on Windows.
5109 const FunctionType *FT =
5110 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5111 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5112 if (FT->isVarArg() &&
5113 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5114 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5115 const Type* T = I.getArgOperand(i)->getType();
5116 for (po_iterator<const Type*> i = po_begin(T), e = po_end(T);
5118 if (!i->isFloatingPointTy()) continue;
5119 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5125 const char *RenameFn = 0;
5126 if (Function *F = I.getCalledFunction()) {
5127 if (F->isDeclaration()) {
5128 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5129 if (unsigned IID = II->getIntrinsicID(F)) {
5130 RenameFn = visitIntrinsicCall(I, IID);
5135 if (unsigned IID = F->getIntrinsicID()) {
5136 RenameFn = visitIntrinsicCall(I, IID);
5142 // Check for well-known libc/libm calls. If the function is internal, it
5143 // can't be a library call.
5144 if (!F->hasLocalLinkage() && F->hasName()) {
5145 StringRef Name = F->getName();
5146 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") {
5147 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5148 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5149 I.getType() == I.getArgOperand(0)->getType() &&
5150 I.getType() == I.getArgOperand(1)->getType()) {
5151 SDValue LHS = getValue(I.getArgOperand(0));
5152 SDValue RHS = getValue(I.getArgOperand(1));
5153 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5154 LHS.getValueType(), LHS, RHS));
5157 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") {
5158 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5159 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5160 I.getType() == I.getArgOperand(0)->getType()) {
5161 SDValue Tmp = getValue(I.getArgOperand(0));
5162 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5163 Tmp.getValueType(), Tmp));
5166 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") {
5167 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5168 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5169 I.getType() == I.getArgOperand(0)->getType() &&
5170 I.onlyReadsMemory()) {
5171 SDValue Tmp = getValue(I.getArgOperand(0));
5172 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5173 Tmp.getValueType(), Tmp));
5176 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") {
5177 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5178 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5179 I.getType() == I.getArgOperand(0)->getType() &&
5180 I.onlyReadsMemory()) {
5181 SDValue Tmp = getValue(I.getArgOperand(0));
5182 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5183 Tmp.getValueType(), Tmp));
5186 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") {
5187 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5188 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5189 I.getType() == I.getArgOperand(0)->getType() &&
5190 I.onlyReadsMemory()) {
5191 SDValue Tmp = getValue(I.getArgOperand(0));
5192 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5193 Tmp.getValueType(), Tmp));
5196 } else if (Name == "memcmp") {
5197 if (visitMemCmpCall(I))
5205 Callee = getValue(I.getCalledValue());
5207 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5209 // Check if we can potentially perform a tail call. More detailed checking is
5210 // be done within LowerCallTo, after more information about the call is known.
5211 LowerCallTo(&I, Callee, I.isTailCall());
5216 /// AsmOperandInfo - This contains information for each constraint that we are
5218 class LLVM_LIBRARY_VISIBILITY SDISelAsmOperandInfo :
5219 public TargetLowering::AsmOperandInfo {
5221 /// CallOperand - If this is the result output operand or a clobber
5222 /// this is null, otherwise it is the incoming operand to the CallInst.
5223 /// This gets modified as the asm is processed.
5224 SDValue CallOperand;
5226 /// AssignedRegs - If this is a register or register class operand, this
5227 /// contains the set of register corresponding to the operand.
5228 RegsForValue AssignedRegs;
5230 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5231 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5234 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5235 /// busy in OutputRegs/InputRegs.
5236 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5237 std::set<unsigned> &OutputRegs,
5238 std::set<unsigned> &InputRegs,
5239 const TargetRegisterInfo &TRI) const {
5241 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5242 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5245 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5246 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5250 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5251 /// corresponds to. If there is no Value* for this operand, it returns
5253 EVT getCallOperandValEVT(LLVMContext &Context,
5254 const TargetLowering &TLI,
5255 const TargetData *TD) const {
5256 if (CallOperandVal == 0) return MVT::Other;
5258 if (isa<BasicBlock>(CallOperandVal))
5259 return TLI.getPointerTy();
5261 const llvm::Type *OpTy = CallOperandVal->getType();
5263 // If this is an indirect operand, the operand is a pointer to the
5266 const llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5268 report_fatal_error("Indirect operand for inline asm not a pointer!");
5269 OpTy = PtrTy->getElementType();
5272 // If OpTy is not a single value, it may be a struct/union that we
5273 // can tile with integers.
5274 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5275 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5284 OpTy = IntegerType::get(Context, BitSize);
5289 return TLI.getValueType(OpTy, true);
5293 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5295 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5296 const TargetRegisterInfo &TRI) {
5297 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5299 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5300 for (; *Aliases; ++Aliases)
5301 Regs.insert(*Aliases);
5305 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5307 } // end llvm namespace.
5309 /// isAllocatableRegister - If the specified register is safe to allocate,
5310 /// i.e. it isn't a stack pointer or some other special register, return the
5311 /// register class for the register. Otherwise, return null.
5312 static const TargetRegisterClass *
5313 isAllocatableRegister(unsigned Reg, MachineFunction &MF,
5314 const TargetLowering &TLI,
5315 const TargetRegisterInfo *TRI) {
5316 EVT FoundVT = MVT::Other;
5317 const TargetRegisterClass *FoundRC = 0;
5318 for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
5319 E = TRI->regclass_end(); RCI != E; ++RCI) {
5320 EVT ThisVT = MVT::Other;
5322 const TargetRegisterClass *RC = *RCI;
5323 // If none of the value types for this register class are valid, we
5324 // can't use it. For example, 64-bit reg classes on 32-bit targets.
5325 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
5327 if (TLI.isTypeLegal(*I)) {
5328 // If we have already found this register in a different register class,
5329 // choose the one with the largest VT specified. For example, on
5330 // PowerPC, we favor f64 register classes over f32.
5331 if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
5338 if (ThisVT == MVT::Other) continue;
5340 // NOTE: This isn't ideal. In particular, this might allocate the
5341 // frame pointer in functions that need it (due to them not being taken
5342 // out of allocation, because a variable sized allocation hasn't been seen
5343 // yet). This is a slight code pessimization, but should still work.
5344 for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
5345 E = RC->allocation_order_end(MF); I != E; ++I)
5347 // We found a matching register class. Keep looking at others in case
5348 // we find one with larger registers that this physreg is also in.
5357 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5358 /// specified operand. We prefer to assign virtual registers, to allow the
5359 /// register allocator to handle the assignment process. However, if the asm
5360 /// uses features that we can't model on machineinstrs, we have SDISel do the
5361 /// allocation. This produces generally horrible, but correct, code.
5363 /// OpInfo describes the operand.
5364 /// Input and OutputRegs are the set of already allocated physical registers.
5366 void SelectionDAGBuilder::
5367 GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
5368 std::set<unsigned> &OutputRegs,
5369 std::set<unsigned> &InputRegs) {
5370 LLVMContext &Context = FuncInfo.Fn->getContext();
5372 // Compute whether this value requires an input register, an output register,
5374 bool isOutReg = false;
5375 bool isInReg = false;
5376 switch (OpInfo.Type) {
5377 case InlineAsm::isOutput:
5380 // If there is an input constraint that matches this, we need to reserve
5381 // the input register so no other inputs allocate to it.
5382 isInReg = OpInfo.hasMatchingInput();
5384 case InlineAsm::isInput:
5388 case InlineAsm::isClobber:
5395 MachineFunction &MF = DAG.getMachineFunction();
5396 SmallVector<unsigned, 4> Regs;
5398 // If this is a constraint for a single physreg, or a constraint for a
5399 // register class, find it.
5400 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5401 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5402 OpInfo.ConstraintVT);
5404 unsigned NumRegs = 1;
5405 if (OpInfo.ConstraintVT != MVT::Other) {
5406 // If this is a FP input in an integer register (or visa versa) insert a bit
5407 // cast of the input value. More generally, handle any case where the input
5408 // value disagrees with the register class we plan to stick this in.
5409 if (OpInfo.Type == InlineAsm::isInput &&
5410 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5411 // Try to convert to the first EVT that the reg class contains. If the
5412 // types are identical size, use a bitcast to convert (e.g. two differing
5414 EVT RegVT = *PhysReg.second->vt_begin();
5415 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5416 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5417 RegVT, OpInfo.CallOperand);
5418 OpInfo.ConstraintVT = RegVT;
5419 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5420 // If the input is a FP value and we want it in FP registers, do a
5421 // bitcast to the corresponding integer type. This turns an f64 value
5422 // into i64, which can be passed with two i32 values on a 32-bit
5424 RegVT = EVT::getIntegerVT(Context,
5425 OpInfo.ConstraintVT.getSizeInBits());
5426 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5427 RegVT, OpInfo.CallOperand);
5428 OpInfo.ConstraintVT = RegVT;
5432 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5436 EVT ValueVT = OpInfo.ConstraintVT;
5438 // If this is a constraint for a specific physical register, like {r17},
5440 if (unsigned AssignedReg = PhysReg.first) {
5441 const TargetRegisterClass *RC = PhysReg.second;
5442 if (OpInfo.ConstraintVT == MVT::Other)
5443 ValueVT = *RC->vt_begin();
5445 // Get the actual register value type. This is important, because the user
5446 // may have asked for (e.g.) the AX register in i32 type. We need to
5447 // remember that AX is actually i16 to get the right extension.
5448 RegVT = *RC->vt_begin();
5450 // This is a explicit reference to a physical register.
5451 Regs.push_back(AssignedReg);
5453 // If this is an expanded reference, add the rest of the regs to Regs.
5455 TargetRegisterClass::iterator I = RC->begin();
5456 for (; *I != AssignedReg; ++I)
5457 assert(I != RC->end() && "Didn't find reg!");
5459 // Already added the first reg.
5461 for (; NumRegs; --NumRegs, ++I) {
5462 assert(I != RC->end() && "Ran out of registers to allocate!");
5467 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5468 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5469 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5473 // Otherwise, if this was a reference to an LLVM register class, create vregs
5474 // for this reference.
5475 if (const TargetRegisterClass *RC = PhysReg.second) {
5476 RegVT = *RC->vt_begin();
5477 if (OpInfo.ConstraintVT == MVT::Other)
5480 // Create the appropriate number of virtual registers.
5481 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5482 for (; NumRegs; --NumRegs)
5483 Regs.push_back(RegInfo.createVirtualRegister(RC));
5485 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5489 // This is a reference to a register class that doesn't directly correspond
5490 // to an LLVM register class. Allocate NumRegs consecutive, available,
5491 // registers from the class.
5492 std::vector<unsigned> RegClassRegs
5493 = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode,
5494 OpInfo.ConstraintVT);
5496 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5497 unsigned NumAllocated = 0;
5498 for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) {
5499 unsigned Reg = RegClassRegs[i];
5500 // See if this register is available.
5501 if ((isOutReg && OutputRegs.count(Reg)) || // Already used.
5502 (isInReg && InputRegs.count(Reg))) { // Already used.
5503 // Make sure we find consecutive registers.
5508 // Check to see if this register is allocatable (i.e. don't give out the
5510 const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI);
5511 if (!RC) { // Couldn't allocate this register.
5512 // Reset NumAllocated to make sure we return consecutive registers.
5517 // Okay, this register is good, we can use it.
5520 // If we allocated enough consecutive registers, succeed.
5521 if (NumAllocated == NumRegs) {
5522 unsigned RegStart = (i-NumAllocated)+1;
5523 unsigned RegEnd = i+1;
5524 // Mark all of the allocated registers used.
5525 for (unsigned i = RegStart; i != RegEnd; ++i)
5526 Regs.push_back(RegClassRegs[i]);
5528 OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(),
5529 OpInfo.ConstraintVT);
5530 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5535 // Otherwise, we couldn't allocate enough registers for this.
5538 /// visitInlineAsm - Handle a call to an InlineAsm object.
5540 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5541 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5543 /// ConstraintOperands - Information about all of the constraints.
5544 SDISelAsmOperandInfoVector ConstraintOperands;
5546 std::set<unsigned> OutputRegs, InputRegs;
5548 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(CS);
5549 bool hasMemory = false;
5551 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5552 unsigned ResNo = 0; // ResNo - The result number of the next output.
5553 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5554 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5555 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5557 EVT OpVT = MVT::Other;
5559 // Compute the value type for each operand.
5560 switch (OpInfo.Type) {
5561 case InlineAsm::isOutput:
5562 // Indirect outputs just consume an argument.
5563 if (OpInfo.isIndirect) {
5564 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5568 // The return value of the call is this value. As such, there is no
5569 // corresponding argument.
5570 assert(!CS.getType()->isVoidTy() &&
5572 if (const StructType *STy = dyn_cast<StructType>(CS.getType())) {
5573 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5575 assert(ResNo == 0 && "Asm only has one result!");
5576 OpVT = TLI.getValueType(CS.getType());
5580 case InlineAsm::isInput:
5581 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5583 case InlineAsm::isClobber:
5588 // If this is an input or an indirect output, process the call argument.
5589 // BasicBlocks are labels, currently appearing only in asm's.
5590 if (OpInfo.CallOperandVal) {
5591 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5592 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5594 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5597 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5600 OpInfo.ConstraintVT = OpVT;
5602 // Indirect operand accesses access memory.
5603 if (OpInfo.isIndirect)
5606 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5607 TargetLowering::ConstraintType CType = TLI.getConstraintType(OpInfo.Codes[j]);
5608 if (CType == TargetLowering::C_Memory) {
5616 SDValue Chain, Flag;
5618 // We won't need to flush pending loads if this asm doesn't touch
5619 // memory and is nonvolatile.
5620 if (hasMemory || IA->hasSideEffects())
5623 Chain = DAG.getRoot();
5625 // Second pass over the constraints: compute which constraint option to use
5626 // and assign registers to constraints that want a specific physreg.
5627 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5628 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5630 // If this is an output operand with a matching input operand, look up the
5631 // matching input. If their types mismatch, e.g. one is an integer, the
5632 // other is floating point, or their sizes are different, flag it as an
5634 if (OpInfo.hasMatchingInput()) {
5635 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5637 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5638 if ((OpInfo.ConstraintVT.isInteger() !=
5639 Input.ConstraintVT.isInteger()) ||
5640 (OpInfo.ConstraintVT.getSizeInBits() !=
5641 Input.ConstraintVT.getSizeInBits())) {
5642 report_fatal_error("Unsupported asm: input constraint"
5643 " with a matching output constraint of"
5644 " incompatible type!");
5646 Input.ConstraintVT = OpInfo.ConstraintVT;
5650 // Compute the constraint code and ConstraintType to use.
5651 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5653 // If this is a memory input, and if the operand is not indirect, do what we
5654 // need to to provide an address for the memory input.
5655 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5656 !OpInfo.isIndirect) {
5657 assert((OpInfo.isMultipleAlternative || (OpInfo.Type == InlineAsm::isInput)) &&
5658 "Can only indirectify direct input operands!");
5660 // Memory operands really want the address of the value. If we don't have
5661 // an indirect input, put it in the constpool if we can, otherwise spill
5662 // it to a stack slot.
5664 // If the operand is a float, integer, or vector constant, spill to a
5665 // constant pool entry to get its address.
5666 const Value *OpVal = OpInfo.CallOperandVal;
5667 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5668 isa<ConstantVector>(OpVal)) {
5669 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5670 TLI.getPointerTy());
5672 // Otherwise, create a stack slot and emit a store to it before the
5674 const Type *Ty = OpVal->getType();
5675 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5676 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5677 MachineFunction &MF = DAG.getMachineFunction();
5678 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5679 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5680 Chain = DAG.getStore(Chain, getCurDebugLoc(),
5681 OpInfo.CallOperand, StackSlot,
5682 MachinePointerInfo::getFixedStack(SSFI),
5684 OpInfo.CallOperand = StackSlot;
5687 // There is no longer a Value* corresponding to this operand.
5688 OpInfo.CallOperandVal = 0;
5690 // It is now an indirect operand.
5691 OpInfo.isIndirect = true;
5694 // If this constraint is for a specific register, allocate it before
5696 if (OpInfo.ConstraintType == TargetLowering::C_Register)
5697 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5700 // Second pass - Loop over all of the operands, assigning virtual or physregs
5701 // to register class operands.
5702 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5703 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5705 // C_Register operands have already been allocated, Other/Memory don't need
5707 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
5708 GetRegistersForValue(OpInfo, OutputRegs, InputRegs);
5711 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
5712 std::vector<SDValue> AsmNodeOperands;
5713 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
5714 AsmNodeOperands.push_back(
5715 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
5716 TLI.getPointerTy()));
5718 // If we have a !srcloc metadata node associated with it, we want to attach
5719 // this to the ultimately generated inline asm machineinstr. To do this, we
5720 // pass in the third operand as this (potentially null) inline asm MDNode.
5721 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
5722 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
5724 // Remember the HasSideEffect and AlignStack bits as operand 3.
5725 unsigned ExtraInfo = 0;
5726 if (IA->hasSideEffects())
5727 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
5728 if (IA->isAlignStack())
5729 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
5730 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
5731 TLI.getPointerTy()));
5733 // Loop over all of the inputs, copying the operand values into the
5734 // appropriate registers and processing the output regs.
5735 RegsForValue RetValRegs;
5737 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
5738 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
5740 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5741 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5743 switch (OpInfo.Type) {
5744 case InlineAsm::isOutput: {
5745 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
5746 OpInfo.ConstraintType != TargetLowering::C_Register) {
5747 // Memory output, or 'other' output (e.g. 'X' constraint).
5748 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
5750 // Add information to the INLINEASM node to know about this output.
5751 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5752 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
5753 TLI.getPointerTy()));
5754 AsmNodeOperands.push_back(OpInfo.CallOperand);
5758 // Otherwise, this is a register or register class output.
5760 // Copy the output from the appropriate register. Find a register that
5762 if (OpInfo.AssignedRegs.Regs.empty())
5763 report_fatal_error("Couldn't allocate output reg for constraint '" +
5764 Twine(OpInfo.ConstraintCode) + "'!");
5766 // If this is an indirect operand, store through the pointer after the
5768 if (OpInfo.isIndirect) {
5769 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
5770 OpInfo.CallOperandVal));
5772 // This is the result value of the call.
5773 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5774 // Concatenate this output onto the outputs list.
5775 RetValRegs.append(OpInfo.AssignedRegs);
5778 // Add information to the INLINEASM node to know that this register is
5780 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
5781 InlineAsm::Kind_RegDefEarlyClobber :
5782 InlineAsm::Kind_RegDef,
5789 case InlineAsm::isInput: {
5790 SDValue InOperandVal = OpInfo.CallOperand;
5792 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
5793 // If this is required to match an output register we have already set,
5794 // just use its register.
5795 unsigned OperandNo = OpInfo.getMatchedOperand();
5797 // Scan until we find the definition we already emitted of this operand.
5798 // When we find it, create a RegsForValue operand.
5799 unsigned CurOp = InlineAsm::Op_FirstOperand;
5800 for (; OperandNo; --OperandNo) {
5801 // Advance to the next operand.
5803 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5804 assert((InlineAsm::isRegDefKind(OpFlag) ||
5805 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
5806 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
5807 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
5811 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
5812 if (InlineAsm::isRegDefKind(OpFlag) ||
5813 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
5814 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
5815 if (OpInfo.isIndirect) {
5816 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
5817 LLVMContext &Ctx = *DAG.getContext();
5818 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
5819 " don't know how to handle tied "
5820 "indirect register inputs");
5823 RegsForValue MatchedRegs;
5824 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
5825 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
5826 MatchedRegs.RegVTs.push_back(RegVT);
5827 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
5828 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
5830 MatchedRegs.Regs.push_back
5831 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
5833 // Use the produced MatchedRegs object to
5834 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5836 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
5837 true, OpInfo.getMatchedOperand(),
5838 DAG, AsmNodeOperands);
5842 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
5843 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
5844 "Unexpected number of operands");
5845 // Add information to the INLINEASM node to know about this input.
5846 // See InlineAsm.h isUseOperandTiedToDef.
5847 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
5848 OpInfo.getMatchedOperand());
5849 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
5850 TLI.getPointerTy()));
5851 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
5855 // Treat indirect 'X' constraint as memory.
5856 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
5858 OpInfo.ConstraintType = TargetLowering::C_Memory;
5860 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
5861 std::vector<SDValue> Ops;
5862 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
5865 report_fatal_error("Invalid operand for inline asm constraint '" +
5866 Twine(OpInfo.ConstraintCode) + "'!");
5868 // Add information to the INLINEASM node to know about this input.
5869 unsigned ResOpType =
5870 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
5871 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5872 TLI.getPointerTy()));
5873 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
5877 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
5878 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
5879 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
5880 "Memory operands expect pointer values");
5882 // Add information to the INLINEASM node to know about this input.
5883 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
5884 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
5885 TLI.getPointerTy()));
5886 AsmNodeOperands.push_back(InOperandVal);
5890 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
5891 OpInfo.ConstraintType == TargetLowering::C_Register) &&
5892 "Unknown constraint type!");
5893 assert(!OpInfo.isIndirect &&
5894 "Don't know how to handle indirect register inputs yet!");
5896 // Copy the input into the appropriate registers.
5897 if (OpInfo.AssignedRegs.Regs.empty() ||
5898 !OpInfo.AssignedRegs.areValueTypesLegal(TLI))
5899 report_fatal_error("Couldn't allocate input reg for constraint '" +
5900 Twine(OpInfo.ConstraintCode) + "'!");
5902 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
5905 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
5906 DAG, AsmNodeOperands);
5909 case InlineAsm::isClobber: {
5910 // Add the clobbered value to the operand list, so that the register
5911 // allocator is aware that the physreg got clobbered.
5912 if (!OpInfo.AssignedRegs.Regs.empty())
5913 OpInfo.AssignedRegs.AddInlineAsmOperands(
5914 InlineAsm::Kind_RegDefEarlyClobber,
5922 // Finish up input operands. Set the input chain and add the flag last.
5923 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
5924 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
5926 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
5927 DAG.getVTList(MVT::Other, MVT::Glue),
5928 &AsmNodeOperands[0], AsmNodeOperands.size());
5929 Flag = Chain.getValue(1);
5931 // If this asm returns a register value, copy the result from that register
5932 // and set it as the value of the call.
5933 if (!RetValRegs.Regs.empty()) {
5934 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5937 // FIXME: Why don't we do this for inline asms with MRVs?
5938 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
5939 EVT ResultType = TLI.getValueType(CS.getType());
5941 // If any of the results of the inline asm is a vector, it may have the
5942 // wrong width/num elts. This can happen for register classes that can
5943 // contain multiple different value types. The preg or vreg allocated may
5944 // not have the same VT as was expected. Convert it to the right type
5945 // with bit_convert.
5946 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
5947 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
5950 } else if (ResultType != Val.getValueType() &&
5951 ResultType.isInteger() && Val.getValueType().isInteger()) {
5952 // If a result value was tied to an input value, the computed result may
5953 // have a wider width than the expected result. Extract the relevant
5955 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
5958 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
5961 setValue(CS.getInstruction(), Val);
5962 // Don't need to use this as a chain in this case.
5963 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
5967 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
5969 // Process indirect outputs, first output all of the flagged copies out of
5971 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
5972 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
5973 const Value *Ptr = IndirectStoresToEmit[i].second;
5974 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
5976 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
5979 // Emit the non-flagged stores from the physregs.
5980 SmallVector<SDValue, 8> OutChains;
5981 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
5982 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
5983 StoresToEmit[i].first,
5984 getValue(StoresToEmit[i].second),
5985 MachinePointerInfo(StoresToEmit[i].second),
5987 OutChains.push_back(Val);
5990 if (!OutChains.empty())
5991 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
5992 &OutChains[0], OutChains.size());
5997 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
5998 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
5999 MVT::Other, getRoot(),
6000 getValue(I.getArgOperand(0)),
6001 DAG.getSrcValue(I.getArgOperand(0))));
6004 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6005 const TargetData &TD = *TLI.getTargetData();
6006 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6007 getRoot(), getValue(I.getOperand(0)),
6008 DAG.getSrcValue(I.getOperand(0)),
6009 TD.getABITypeAlignment(I.getType()));
6011 DAG.setRoot(V.getValue(1));
6014 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6015 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6016 MVT::Other, getRoot(),
6017 getValue(I.getArgOperand(0)),
6018 DAG.getSrcValue(I.getArgOperand(0))));
6021 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6022 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6023 MVT::Other, getRoot(),
6024 getValue(I.getArgOperand(0)),
6025 getValue(I.getArgOperand(1)),
6026 DAG.getSrcValue(I.getArgOperand(0)),
6027 DAG.getSrcValue(I.getArgOperand(1))));
6030 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6031 /// implementation, which just calls LowerCall.
6032 /// FIXME: When all targets are
6033 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6034 std::pair<SDValue, SDValue>
6035 TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
6036 bool RetSExt, bool RetZExt, bool isVarArg,
6037 bool isInreg, unsigned NumFixedArgs,
6038 CallingConv::ID CallConv, bool isTailCall,
6039 bool isReturnValueUsed,
6041 ArgListTy &Args, SelectionDAG &DAG,
6042 DebugLoc dl) const {
6043 // Handle all of the outgoing arguments.
6044 SmallVector<ISD::OutputArg, 32> Outs;
6045 SmallVector<SDValue, 32> OutVals;
6046 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6047 SmallVector<EVT, 4> ValueVTs;
6048 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6049 for (unsigned Value = 0, NumValues = ValueVTs.size();
6050 Value != NumValues; ++Value) {
6051 EVT VT = ValueVTs[Value];
6052 const Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6053 SDValue Op = SDValue(Args[i].Node.getNode(),
6054 Args[i].Node.getResNo() + Value);
6055 ISD::ArgFlagsTy Flags;
6056 unsigned OriginalAlignment =
6057 getTargetData()->getABITypeAlignment(ArgTy);
6063 if (Args[i].isInReg)
6067 if (Args[i].isByVal) {
6069 const PointerType *Ty = cast<PointerType>(Args[i].Ty);
6070 const Type *ElementTy = Ty->getElementType();
6071 unsigned FrameAlign = getByValTypeAlignment(ElementTy);
6072 unsigned FrameSize = getTargetData()->getTypeAllocSize(ElementTy);
6073 // For ByVal, alignment should come from FE. BE will guess if this
6074 // info is not there but there are cases it cannot get right.
6075 if (Args[i].Alignment)
6076 FrameAlign = Args[i].Alignment;
6077 Flags.setByValAlign(FrameAlign);
6078 Flags.setByValSize(FrameSize);
6082 Flags.setOrigAlign(OriginalAlignment);
6084 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6085 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6086 SmallVector<SDValue, 4> Parts(NumParts);
6087 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6090 ExtendKind = ISD::SIGN_EXTEND;
6091 else if (Args[i].isZExt)
6092 ExtendKind = ISD::ZERO_EXTEND;
6094 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6095 PartVT, ExtendKind);
6097 for (unsigned j = 0; j != NumParts; ++j) {
6098 // if it isn't first piece, alignment must be 1
6099 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6101 if (NumParts > 1 && j == 0)
6102 MyFlags.Flags.setSplit();
6104 MyFlags.Flags.setOrigAlign(1);
6106 Outs.push_back(MyFlags);
6107 OutVals.push_back(Parts[j]);
6112 // Handle the incoming return values from the call.
6113 SmallVector<ISD::InputArg, 32> Ins;
6114 SmallVector<EVT, 4> RetTys;
6115 ComputeValueVTs(*this, RetTy, RetTys);
6116 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6118 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6119 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6120 for (unsigned i = 0; i != NumRegs; ++i) {
6121 ISD::InputArg MyFlags;
6122 MyFlags.VT = RegisterVT.getSimpleVT();
6123 MyFlags.Used = isReturnValueUsed;
6125 MyFlags.Flags.setSExt();
6127 MyFlags.Flags.setZExt();
6129 MyFlags.Flags.setInReg();
6130 Ins.push_back(MyFlags);
6134 SmallVector<SDValue, 4> InVals;
6135 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6136 Outs, OutVals, Ins, dl, DAG, InVals);
6138 // Verify that the target's LowerCall behaved as expected.
6139 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6140 "LowerCall didn't return a valid chain!");
6141 assert((!isTailCall || InVals.empty()) &&
6142 "LowerCall emitted a return value for a tail call!");
6143 assert((isTailCall || InVals.size() == Ins.size()) &&
6144 "LowerCall didn't emit the correct number of values!");
6146 // For a tail call, the return value is merely live-out and there aren't
6147 // any nodes in the DAG representing it. Return a special value to
6148 // indicate that a tail call has been emitted and no more Instructions
6149 // should be processed in the current block.
6152 return std::make_pair(SDValue(), SDValue());
6155 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6156 assert(InVals[i].getNode() &&
6157 "LowerCall emitted a null value!");
6158 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6159 "LowerCall emitted a value with the wrong type!");
6162 // Collect the legal value parts into potentially illegal values
6163 // that correspond to the original function's return values.
6164 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6166 AssertOp = ISD::AssertSext;
6168 AssertOp = ISD::AssertZext;
6169 SmallVector<SDValue, 4> ReturnValues;
6170 unsigned CurReg = 0;
6171 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6173 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6174 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6176 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6177 NumRegs, RegisterVT, VT,
6182 // For a function returning void, there is no return value. We can't create
6183 // such a node, so we just return a null return value in that case. In
6184 // that case, nothing will actualy look at the value.
6185 if (ReturnValues.empty())
6186 return std::make_pair(SDValue(), Chain);
6188 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6189 DAG.getVTList(&RetTys[0], RetTys.size()),
6190 &ReturnValues[0], ReturnValues.size());
6191 return std::make_pair(Res, Chain);
6194 void TargetLowering::LowerOperationWrapper(SDNode *N,
6195 SmallVectorImpl<SDValue> &Results,
6196 SelectionDAG &DAG) const {
6197 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6199 Results.push_back(Res);
6202 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6203 llvm_unreachable("LowerOperation not implemented for this target!");
6208 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6209 SDValue Op = getNonRegisterValue(V);
6210 assert((Op.getOpcode() != ISD::CopyFromReg ||
6211 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6212 "Copy from a reg to the same reg!");
6213 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6215 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6216 SDValue Chain = DAG.getEntryNode();
6217 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6218 PendingExports.push_back(Chain);
6221 #include "llvm/CodeGen/SelectionDAGISel.h"
6223 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6224 // If this is the entry block, emit arguments.
6225 const Function &F = *LLVMBB->getParent();
6226 SelectionDAG &DAG = SDB->DAG;
6227 DebugLoc dl = SDB->getCurDebugLoc();
6228 const TargetData *TD = TLI.getTargetData();
6229 SmallVector<ISD::InputArg, 16> Ins;
6231 // Check whether the function can return without sret-demotion.
6232 SmallVector<ISD::OutputArg, 4> Outs;
6233 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6236 if (!FuncInfo->CanLowerReturn) {
6237 // Put in an sret pointer parameter before all the other parameters.
6238 SmallVector<EVT, 1> ValueVTs;
6239 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6241 // NOTE: Assuming that a pointer will never break down to more than one VT
6243 ISD::ArgFlagsTy Flags;
6245 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6246 ISD::InputArg RetArg(Flags, RegisterVT, true);
6247 Ins.push_back(RetArg);
6250 // Set up the incoming argument description vector.
6252 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6253 I != E; ++I, ++Idx) {
6254 SmallVector<EVT, 4> ValueVTs;
6255 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6256 bool isArgValueUsed = !I->use_empty();
6257 for (unsigned Value = 0, NumValues = ValueVTs.size();
6258 Value != NumValues; ++Value) {
6259 EVT VT = ValueVTs[Value];
6260 const Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6261 ISD::ArgFlagsTy Flags;
6262 unsigned OriginalAlignment =
6263 TD->getABITypeAlignment(ArgTy);
6265 if (F.paramHasAttr(Idx, Attribute::ZExt))
6267 if (F.paramHasAttr(Idx, Attribute::SExt))
6269 if (F.paramHasAttr(Idx, Attribute::InReg))
6271 if (F.paramHasAttr(Idx, Attribute::StructRet))
6273 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6275 const PointerType *Ty = cast<PointerType>(I->getType());
6276 const Type *ElementTy = Ty->getElementType();
6277 unsigned FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6278 unsigned FrameSize = TD->getTypeAllocSize(ElementTy);
6279 // For ByVal, alignment should be passed from FE. BE will guess if
6280 // this info is not there but there are cases it cannot get right.
6281 if (F.getParamAlignment(Idx))
6282 FrameAlign = F.getParamAlignment(Idx);
6283 Flags.setByValAlign(FrameAlign);
6284 Flags.setByValSize(FrameSize);
6286 if (F.paramHasAttr(Idx, Attribute::Nest))
6288 Flags.setOrigAlign(OriginalAlignment);
6290 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6291 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6292 for (unsigned i = 0; i != NumRegs; ++i) {
6293 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6294 if (NumRegs > 1 && i == 0)
6295 MyFlags.Flags.setSplit();
6296 // if it isn't first piece, alignment must be 1
6298 MyFlags.Flags.setOrigAlign(1);
6299 Ins.push_back(MyFlags);
6304 // Call the target to set up the argument values.
6305 SmallVector<SDValue, 8> InVals;
6306 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6310 // Verify that the target's LowerFormalArguments behaved as expected.
6311 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6312 "LowerFormalArguments didn't return a valid chain!");
6313 assert(InVals.size() == Ins.size() &&
6314 "LowerFormalArguments didn't emit the correct number of values!");
6316 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6317 assert(InVals[i].getNode() &&
6318 "LowerFormalArguments emitted a null value!");
6319 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6320 "LowerFormalArguments emitted a value with the wrong type!");
6324 // Update the DAG with the new chain value resulting from argument lowering.
6325 DAG.setRoot(NewRoot);
6327 // Set up the argument values.
6330 if (!FuncInfo->CanLowerReturn) {
6331 // Create a virtual register for the sret pointer, and put in a copy
6332 // from the sret argument into it.
6333 SmallVector<EVT, 1> ValueVTs;
6334 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6335 EVT VT = ValueVTs[0];
6336 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6337 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6338 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6339 RegVT, VT, AssertOp);
6341 MachineFunction& MF = SDB->DAG.getMachineFunction();
6342 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6343 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6344 FuncInfo->DemoteRegister = SRetReg;
6345 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6347 DAG.setRoot(NewRoot);
6349 // i indexes lowered arguments. Bump it past the hidden sret argument.
6350 // Idx indexes LLVM arguments. Don't touch it.
6354 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6356 SmallVector<SDValue, 4> ArgValues;
6357 SmallVector<EVT, 4> ValueVTs;
6358 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6359 unsigned NumValues = ValueVTs.size();
6361 // If this argument is unused then remember its value. It is used to generate
6362 // debugging information.
6363 if (I->use_empty() && NumValues)
6364 SDB->setUnusedArgValue(I, InVals[i]);
6366 for (unsigned Value = 0; Value != NumValues; ++Value) {
6367 EVT VT = ValueVTs[Value];
6368 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6369 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6371 if (!I->use_empty()) {
6372 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6373 if (F.paramHasAttr(Idx, Attribute::SExt))
6374 AssertOp = ISD::AssertSext;
6375 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6376 AssertOp = ISD::AssertZext;
6378 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6379 NumParts, PartVT, VT,
6386 // Note down frame index for byval arguments.
6387 if (I->hasByValAttr() && !ArgValues.empty())
6388 if (FrameIndexSDNode *FI =
6389 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6390 FuncInfo->setByValArgumentFrameIndex(I, FI->getIndex());
6392 if (!I->use_empty()) {
6394 if (!ArgValues.empty())
6395 Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6396 SDB->getCurDebugLoc());
6397 SDB->setValue(I, Res);
6399 // If this argument is live outside of the entry block, insert a copy from
6400 // whereever we got it to the vreg that other BB's will reference it as.
6401 SDB->CopyToExportRegsIfNeeded(I);
6405 assert(i == InVals.size() && "Argument register count mismatch!");
6407 // Finally, if the target has anything special to do, allow it to do so.
6408 // FIXME: this should insert code into the DAG!
6409 EmitFunctionEntryCode();
6412 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6413 /// ensure constants are generated when needed. Remember the virtual registers
6414 /// that need to be added to the Machine PHI nodes as input. We cannot just
6415 /// directly add them, because expansion might result in multiple MBB's for one
6416 /// BB. As such, the start of the BB might correspond to a different MBB than
6420 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6421 const TerminatorInst *TI = LLVMBB->getTerminator();
6423 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6425 // Check successor nodes' PHI nodes that expect a constant to be available
6427 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6428 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6429 if (!isa<PHINode>(SuccBB->begin())) continue;
6430 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6432 // If this terminator has multiple identical successors (common for
6433 // switches), only handle each succ once.
6434 if (!SuccsHandled.insert(SuccMBB)) continue;
6436 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6438 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6439 // nodes and Machine PHI nodes, but the incoming operands have not been
6441 for (BasicBlock::const_iterator I = SuccBB->begin();
6442 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6443 // Ignore dead phi's.
6444 if (PN->use_empty()) continue;
6447 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6449 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6450 unsigned &RegOut = ConstantsOut[C];
6452 RegOut = FuncInfo.CreateRegs(C->getType());
6453 CopyValueToVirtualRegister(C, RegOut);
6457 DenseMap<const Value *, unsigned>::iterator I =
6458 FuncInfo.ValueMap.find(PHIOp);
6459 if (I != FuncInfo.ValueMap.end())
6462 assert(isa<AllocaInst>(PHIOp) &&
6463 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6464 "Didn't codegen value into a register!??");
6465 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6466 CopyValueToVirtualRegister(PHIOp, Reg);
6470 // Remember that this register needs to added to the machine PHI node as
6471 // the input for this MBB.
6472 SmallVector<EVT, 4> ValueVTs;
6473 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6474 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6475 EVT VT = ValueVTs[vti];
6476 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6477 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6478 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6479 Reg += NumRegisters;
6483 ConstantsOut.clear();