1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/Analysis.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
69 #define DEBUG_TYPE "isel"
71 /// LimitFloatPrecision - Generate low-precision inline sequences for
72 /// some float libcalls (6, 8 or 12 bits).
73 static unsigned LimitFloatPrecision;
75 static cl::opt<unsigned, true>
76 LimitFPPrecision("limit-float-precision",
77 cl::desc("Generate low-precision inline sequences "
78 "for some float libcalls"),
79 cl::location(LimitFloatPrecision),
82 // Limit the width of DAG chains. This is important in general to prevent
83 // prevent DAG-based analysis from blowing up. For example, alias analysis and
84 // load clustering may not complete in reasonable time. It is difficult to
85 // recognize and avoid this situation within each individual analysis, and
86 // future analyses are likely to have the same behavior. Limiting DAG width is
87 // the safe approach, and will be especially important with global DAGs.
89 // MaxParallelChains default is arbitrarily high to avoid affecting
90 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
91 // sequence over this should have been converted to llvm.memcpy by the
92 // frontend. It easy to induce this behavior with .ll code such as:
93 // %buffer = alloca [4096 x i8]
94 // %data = load [4096 x i8]* %argPtr
95 // store [4096 x i8] %data, [4096 x i8]* %buffer
96 static const unsigned MaxParallelChains = 64;
98 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
99 const SDValue *Parts, unsigned NumParts,
100 MVT PartVT, EVT ValueVT, const Value *V);
102 /// getCopyFromParts - Create a value that contains the specified legal parts
103 /// combined into the value they represent. If the parts combine to a type
104 /// larger then ValueVT then AssertOp can be used to specify whether the extra
105 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
106 /// (ISD::AssertSext).
107 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
108 const SDValue *Parts,
109 unsigned NumParts, MVT PartVT, EVT ValueVT,
111 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
112 if (ValueVT.isVector())
113 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
116 assert(NumParts > 0 && "No parts to assemble!");
117 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
118 SDValue Val = Parts[0];
121 // Assemble the value from multiple parts.
122 if (ValueVT.isInteger()) {
123 unsigned PartBits = PartVT.getSizeInBits();
124 unsigned ValueBits = ValueVT.getSizeInBits();
126 // Assemble the power of 2 part.
127 unsigned RoundParts = NumParts & (NumParts - 1) ?
128 1 << Log2_32(NumParts) : NumParts;
129 unsigned RoundBits = PartBits * RoundParts;
130 EVT RoundVT = RoundBits == ValueBits ?
131 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
134 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
136 if (RoundParts > 2) {
137 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
139 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
140 RoundParts / 2, PartVT, HalfVT, V);
142 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
143 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
146 if (TLI.isBigEndian())
149 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
151 if (RoundParts < NumParts) {
152 // Assemble the trailing non-power-of-2 part.
153 unsigned OddParts = NumParts - RoundParts;
154 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
155 Hi = getCopyFromParts(DAG, DL,
156 Parts + RoundParts, OddParts, PartVT, OddVT, V);
158 // Combine the round and odd parts.
160 if (TLI.isBigEndian())
162 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
163 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
164 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
165 DAG.getConstant(Lo.getValueType().getSizeInBits(),
166 TLI.getPointerTy()));
167 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
168 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
170 } else if (PartVT.isFloatingPoint()) {
171 // FP split into multiple FP parts (for ppcf128)
172 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
175 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
176 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
177 if (TLI.hasBigEndianPartOrdering(ValueVT))
179 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
181 // FP split into integer parts (soft fp)
182 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
183 !PartVT.isVector() && "Unexpected split");
184 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
185 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
189 // There is now one part, held in Val. Correct it to match ValueVT.
190 EVT PartEVT = Val.getValueType();
192 if (PartEVT == ValueVT)
195 if (PartEVT.isInteger() && ValueVT.isInteger()) {
196 if (ValueVT.bitsLT(PartEVT)) {
197 // For a truncate, see if we have any information to
198 // indicate whether the truncated bits will always be
199 // zero or sign-extension.
200 if (AssertOp != ISD::DELETED_NODE)
201 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
202 DAG.getValueType(ValueVT));
203 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
205 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
208 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
209 // FP_ROUND's are always exact here.
210 if (ValueVT.bitsLT(Val.getValueType()))
211 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
212 DAG.getTargetConstant(1, TLI.getPointerTy()));
214 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
217 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
218 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
220 llvm_unreachable("Unknown mismatch!");
223 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
224 const Twine &ErrMsg) {
225 const Instruction *I = dyn_cast_or_null<Instruction>(V);
227 return Ctx.emitError(ErrMsg);
229 const char *AsmError = ", possible invalid constraint for vector type";
230 if (const CallInst *CI = dyn_cast<CallInst>(I))
231 if (isa<InlineAsm>(CI->getCalledValue()))
232 return Ctx.emitError(I, ErrMsg + AsmError);
234 return Ctx.emitError(I, ErrMsg);
237 /// getCopyFromPartsVector - Create a value that contains the specified legal
238 /// parts combined into the value they represent. If the parts combine to a
239 /// type larger then ValueVT then AssertOp can be used to specify whether the
240 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
241 /// ValueVT (ISD::AssertSext).
242 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
243 const SDValue *Parts, unsigned NumParts,
244 MVT PartVT, EVT ValueVT, const Value *V) {
245 assert(ValueVT.isVector() && "Not a vector value");
246 assert(NumParts > 0 && "No parts to assemble!");
247 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
248 SDValue Val = Parts[0];
250 // Handle a multi-element vector.
254 unsigned NumIntermediates;
256 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
257 NumIntermediates, RegisterVT);
258 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
259 NumParts = NumRegs; // Silence a compiler warning.
260 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
261 assert(RegisterVT == Parts[0].getSimpleValueType() &&
262 "Part type doesn't match part!");
264 // Assemble the parts into intermediate operands.
265 SmallVector<SDValue, 8> Ops(NumIntermediates);
266 if (NumIntermediates == NumParts) {
267 // If the register was not expanded, truncate or copy the value,
269 for (unsigned i = 0; i != NumParts; ++i)
270 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
271 PartVT, IntermediateVT, V);
272 } else if (NumParts > 0) {
273 // If the intermediate type was expanded, build the intermediate
274 // operands from the parts.
275 assert(NumParts % NumIntermediates == 0 &&
276 "Must expand into a divisible number of parts!");
277 unsigned Factor = NumParts / NumIntermediates;
278 for (unsigned i = 0; i != NumIntermediates; ++i)
279 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
280 PartVT, IntermediateVT, V);
283 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
284 // intermediate operands.
285 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
290 // There is now one part, held in Val. Correct it to match ValueVT.
291 EVT PartEVT = Val.getValueType();
293 if (PartEVT == ValueVT)
296 if (PartEVT.isVector()) {
297 // If the element type of the source/dest vectors are the same, but the
298 // parts vector has more elements than the value vector, then we have a
299 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
301 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
302 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
303 "Cannot narrow, it would be a lossy transformation");
304 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
305 DAG.getConstant(0, TLI.getVectorIdxTy()));
308 // Vector/Vector bitcast.
309 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
310 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
312 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
313 "Cannot handle this kind of promotion");
314 // Promoted vector extract
315 bool Smaller = ValueVT.bitsLE(PartEVT);
316 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
321 // Trivial bitcast if the types are the same size and the destination
322 // vector type is legal.
323 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
324 TLI.isTypeLegal(ValueVT))
325 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
327 // Handle cases such as i8 -> <1 x i1>
328 if (ValueVT.getVectorNumElements() != 1) {
329 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
330 "non-trivial scalar-to-vector conversion");
331 return DAG.getUNDEF(ValueVT);
334 if (ValueVT.getVectorNumElements() == 1 &&
335 ValueVT.getVectorElementType() != PartEVT) {
336 bool Smaller = ValueVT.bitsLE(PartEVT);
337 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
338 DL, ValueVT.getScalarType(), Val);
341 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
344 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
345 SDValue Val, SDValue *Parts, unsigned NumParts,
346 MVT PartVT, const Value *V);
348 /// getCopyToParts - Create a series of nodes that contain the specified value
349 /// split into legal parts. If the parts contain more bits than Val, then, for
350 /// integers, ExtendKind can be used to specify how to generate the extra bits.
351 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
352 SDValue Val, SDValue *Parts, unsigned NumParts,
353 MVT PartVT, const Value *V,
354 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
355 EVT ValueVT = Val.getValueType();
357 // Handle the vector case separately.
358 if (ValueVT.isVector())
359 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
361 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
362 unsigned PartBits = PartVT.getSizeInBits();
363 unsigned OrigNumParts = NumParts;
364 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
369 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
370 EVT PartEVT = PartVT;
371 if (PartEVT == ValueVT) {
372 assert(NumParts == 1 && "No-op copy with multiple parts!");
377 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
378 // If the parts cover more bits than the value has, promote the value.
379 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
380 assert(NumParts == 1 && "Do not know what to promote to!");
381 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
383 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
384 ValueVT.isInteger() &&
385 "Unknown mismatch!");
386 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
387 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
388 if (PartVT == MVT::x86mmx)
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
391 } else if (PartBits == ValueVT.getSizeInBits()) {
392 // Different types of the same size.
393 assert(NumParts == 1 && PartEVT != ValueVT);
394 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
395 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
396 // If the parts cover less bits than value has, truncate the value.
397 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
398 ValueVT.isInteger() &&
399 "Unknown mismatch!");
400 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
401 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
402 if (PartVT == MVT::x86mmx)
403 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
406 // The value may have changed - recompute ValueVT.
407 ValueVT = Val.getValueType();
408 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
409 "Failed to tile the value with PartVT!");
412 if (PartEVT != ValueVT)
413 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
414 "scalar-to-vector conversion failed");
420 // Expand the value into multiple parts.
421 if (NumParts & (NumParts - 1)) {
422 // The number of parts is not a power of 2. Split off and copy the tail.
423 assert(PartVT.isInteger() && ValueVT.isInteger() &&
424 "Do not know what to expand to!");
425 unsigned RoundParts = 1 << Log2_32(NumParts);
426 unsigned RoundBits = RoundParts * PartBits;
427 unsigned OddParts = NumParts - RoundParts;
428 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
429 DAG.getIntPtrConstant(RoundBits));
430 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
432 if (TLI.isBigEndian())
433 // The odd parts were reversed by getCopyToParts - unreverse them.
434 std::reverse(Parts + RoundParts, Parts + NumParts);
436 NumParts = RoundParts;
437 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
438 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
441 // The number of parts is a power of 2. Repeatedly bisect the value using
443 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
444 EVT::getIntegerVT(*DAG.getContext(),
445 ValueVT.getSizeInBits()),
448 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
449 for (unsigned i = 0; i < NumParts; i += StepSize) {
450 unsigned ThisBits = StepSize * PartBits / 2;
451 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
452 SDValue &Part0 = Parts[i];
453 SDValue &Part1 = Parts[i+StepSize/2];
455 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
456 ThisVT, Part0, DAG.getIntPtrConstant(1));
457 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
458 ThisVT, Part0, DAG.getIntPtrConstant(0));
460 if (ThisBits == PartBits && ThisVT != PartVT) {
461 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
462 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
467 if (TLI.isBigEndian())
468 std::reverse(Parts, Parts + OrigNumParts);
472 /// getCopyToPartsVector - Create a series of nodes that contain the specified
473 /// value split into legal parts.
474 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
475 SDValue Val, SDValue *Parts, unsigned NumParts,
476 MVT PartVT, const Value *V) {
477 EVT ValueVT = Val.getValueType();
478 assert(ValueVT.isVector() && "Not a vector");
479 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
482 EVT PartEVT = PartVT;
483 if (PartEVT == ValueVT) {
485 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
486 // Bitconvert vector->vector case.
487 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
488 } else if (PartVT.isVector() &&
489 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
490 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
491 EVT ElementVT = PartVT.getVectorElementType();
492 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
494 SmallVector<SDValue, 16> Ops;
495 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
496 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
497 ElementVT, Val, DAG.getConstant(i,
498 TLI.getVectorIdxTy())));
500 for (unsigned i = ValueVT.getVectorNumElements(),
501 e = PartVT.getVectorNumElements(); i != e; ++i)
502 Ops.push_back(DAG.getUNDEF(ElementVT));
504 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
506 // FIXME: Use CONCAT for 2x -> 4x.
508 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
509 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
510 } else if (PartVT.isVector() &&
511 PartEVT.getVectorElementType().bitsGE(
512 ValueVT.getVectorElementType()) &&
513 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
515 // Promoted vector extract
516 bool Smaller = PartEVT.bitsLE(ValueVT);
517 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
520 // Vector -> scalar conversion.
521 assert(ValueVT.getVectorNumElements() == 1 &&
522 "Only trivial vector-to-scalar conversions should get here!");
523 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
526 bool Smaller = ValueVT.bitsLE(PartVT);
527 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
535 // Handle a multi-element vector.
538 unsigned NumIntermediates;
539 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
541 NumIntermediates, RegisterVT);
542 unsigned NumElements = ValueVT.getVectorNumElements();
544 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
545 NumParts = NumRegs; // Silence a compiler warning.
546 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
548 // Split the vector into intermediate operands.
549 SmallVector<SDValue, 8> Ops(NumIntermediates);
550 for (unsigned i = 0; i != NumIntermediates; ++i) {
551 if (IntermediateVT.isVector())
552 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
554 DAG.getConstant(i * (NumElements / NumIntermediates),
555 TLI.getVectorIdxTy()));
557 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
559 DAG.getConstant(i, TLI.getVectorIdxTy()));
562 // Split the intermediate operands into legal parts.
563 if (NumParts == NumIntermediates) {
564 // If the register was not expanded, promote or copy the value,
566 for (unsigned i = 0; i != NumParts; ++i)
567 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
568 } else if (NumParts > 0) {
569 // If the intermediate type was expanded, split each the value into
571 assert(NumIntermediates != 0 && "division by zero");
572 assert(NumParts % NumIntermediates == 0 &&
573 "Must expand into a divisible number of parts!");
574 unsigned Factor = NumParts / NumIntermediates;
575 for (unsigned i = 0; i != NumIntermediates; ++i)
576 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
581 /// RegsForValue - This struct represents the registers (physical or virtual)
582 /// that a particular set of values is assigned, and the type information
583 /// about the value. The most common situation is to represent one value at a
584 /// time, but struct or array values are handled element-wise as multiple
585 /// values. The splitting of aggregates is performed recursively, so that we
586 /// never have aggregate-typed registers. The values at this point do not
587 /// necessarily have legal types, so each value may require one or more
588 /// registers of some legal type.
590 struct RegsForValue {
591 /// ValueVTs - The value types of the values, which may not be legal, and
592 /// may need be promoted or synthesized from one or more registers.
594 SmallVector<EVT, 4> ValueVTs;
596 /// RegVTs - The value types of the registers. This is the same size as
597 /// ValueVTs and it records, for each value, what the type of the assigned
598 /// register or registers are. (Individual values are never synthesized
599 /// from more than one type of register.)
601 /// With virtual registers, the contents of RegVTs is redundant with TLI's
602 /// getRegisterType member function, however when with physical registers
603 /// it is necessary to have a separate record of the types.
605 SmallVector<MVT, 4> RegVTs;
607 /// Regs - This list holds the registers assigned to the values.
608 /// Each legal or promoted value requires one register, and each
609 /// expanded value requires multiple registers.
611 SmallVector<unsigned, 4> Regs;
615 RegsForValue(const SmallVector<unsigned, 4> ®s,
616 MVT regvt, EVT valuevt)
617 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
619 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
620 unsigned Reg, Type *Ty) {
621 ComputeValueVTs(tli, Ty, ValueVTs);
623 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
624 EVT ValueVT = ValueVTs[Value];
625 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
626 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
627 for (unsigned i = 0; i != NumRegs; ++i)
628 Regs.push_back(Reg + i);
629 RegVTs.push_back(RegisterVT);
634 /// append - Add the specified values to this one.
635 void append(const RegsForValue &RHS) {
636 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
637 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
638 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
641 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
642 /// this value and returns the result as a ValueVTs value. This uses
643 /// Chain/Flag as the input and updates them for the output Chain/Flag.
644 /// If the Flag pointer is NULL, no flag is used.
645 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
647 SDValue &Chain, SDValue *Flag,
648 const Value *V = nullptr) const;
650 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
651 /// specified value into the registers specified by this object. This uses
652 /// Chain/Flag as the input and updates them for the output Chain/Flag.
653 /// If the Flag pointer is NULL, no flag is used.
655 getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl, SDValue &Chain,
656 SDValue *Flag, const Value *V,
657 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
659 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
660 /// operand list. This adds the code marker, matching input operand index
661 /// (if applicable), and includes the number of values added into it.
662 void AddInlineAsmOperands(unsigned Kind,
663 bool HasMatching, unsigned MatchingIdx,
665 std::vector<SDValue> &Ops) const;
669 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
670 /// this value and returns the result as a ValueVT value. This uses
671 /// Chain/Flag as the input and updates them for the output Chain/Flag.
672 /// If the Flag pointer is NULL, no flag is used.
673 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
674 FunctionLoweringInfo &FuncInfo,
676 SDValue &Chain, SDValue *Flag,
677 const Value *V) const {
678 // A Value with type {} or [0 x %t] needs no registers.
679 if (ValueVTs.empty())
682 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
684 // Assemble the legal parts into the final values.
685 SmallVector<SDValue, 4> Values(ValueVTs.size());
686 SmallVector<SDValue, 8> Parts;
687 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
688 // Copy the legal parts from the registers.
689 EVT ValueVT = ValueVTs[Value];
690 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
691 MVT RegisterVT = RegVTs[Value];
693 Parts.resize(NumRegs);
694 for (unsigned i = 0; i != NumRegs; ++i) {
697 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
699 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
700 *Flag = P.getValue(2);
703 Chain = P.getValue(1);
706 // If the source register was virtual and if we know something about it,
707 // add an assert node.
708 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
709 !RegisterVT.isInteger() || RegisterVT.isVector())
712 const FunctionLoweringInfo::LiveOutInfo *LOI =
713 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
717 unsigned RegSize = RegisterVT.getSizeInBits();
718 unsigned NumSignBits = LOI->NumSignBits;
719 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
721 if (NumZeroBits == RegSize) {
722 // The current value is a zero.
723 // Explicitly express that as it would be easier for
724 // optimizations to kick in.
725 Parts[i] = DAG.getConstant(0, RegisterVT);
729 // FIXME: We capture more information than the dag can represent. For
730 // now, just use the tightest assertzext/assertsext possible.
732 EVT FromVT(MVT::Other);
733 if (NumSignBits == RegSize)
734 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
735 else if (NumZeroBits >= RegSize-1)
736 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
737 else if (NumSignBits > RegSize-8)
738 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
739 else if (NumZeroBits >= RegSize-8)
740 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
741 else if (NumSignBits > RegSize-16)
742 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
743 else if (NumZeroBits >= RegSize-16)
744 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
745 else if (NumSignBits > RegSize-32)
746 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
747 else if (NumZeroBits >= RegSize-32)
748 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
752 // Add an assertion node.
753 assert(FromVT != MVT::Other);
754 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
755 RegisterVT, P, DAG.getValueType(FromVT));
758 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
759 NumRegs, RegisterVT, ValueVT, V);
764 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
767 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
768 /// specified value into the registers specified by this object. This uses
769 /// Chain/Flag as the input and updates them for the output Chain/Flag.
770 /// If the Flag pointer is NULL, no flag is used.
771 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
772 SDValue &Chain, SDValue *Flag, const Value *V,
773 ISD::NodeType PreferredExtendType) const {
774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
775 ISD::NodeType ExtendKind = PreferredExtendType;
777 // Get the list of the values's legal parts.
778 unsigned NumRegs = Regs.size();
779 SmallVector<SDValue, 8> Parts(NumRegs);
780 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
781 EVT ValueVT = ValueVTs[Value];
782 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
783 MVT RegisterVT = RegVTs[Value];
785 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
786 ExtendKind = ISD::ZERO_EXTEND;
788 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
789 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
793 // Copy the parts into the registers.
794 SmallVector<SDValue, 8> Chains(NumRegs);
795 for (unsigned i = 0; i != NumRegs; ++i) {
798 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
800 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
801 *Flag = Part.getValue(1);
804 Chains[i] = Part.getValue(0);
807 if (NumRegs == 1 || Flag)
808 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
809 // flagged to it. That is the CopyToReg nodes and the user are considered
810 // a single scheduling unit. If we create a TokenFactor and return it as
811 // chain, then the TokenFactor is both a predecessor (operand) of the
812 // user as well as a successor (the TF operands are flagged to the user).
813 // c1, f1 = CopyToReg
814 // c2, f2 = CopyToReg
815 // c3 = TokenFactor c1, c2
818 Chain = Chains[NumRegs-1];
820 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
823 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
824 /// operand list. This adds the code marker and includes the number of
825 /// values added into it.
826 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
827 unsigned MatchingIdx,
829 std::vector<SDValue> &Ops) const {
830 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
832 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
834 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
835 else if (!Regs.empty() &&
836 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
837 // Put the register class of the virtual registers in the flag word. That
838 // way, later passes can recompute register class constraints for inline
839 // assembly as well as normal instructions.
840 // Don't do this for tied operands that can use the regclass information
842 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
843 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
844 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
847 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
850 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
851 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
852 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
853 MVT RegisterVT = RegVTs[Value];
854 for (unsigned i = 0; i != NumRegs; ++i) {
855 assert(Reg < Regs.size() && "Mismatch in # registers expected");
856 unsigned TheReg = Regs[Reg++];
857 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
859 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
860 // If we clobbered the stack pointer, MFI should know about it.
861 assert(DAG.getMachineFunction().getFrameInfo()->
862 hasInlineAsmWithSPAdjust());
868 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
869 const TargetLibraryInfo *li) {
873 DL = DAG.getTarget().getDataLayout();
874 Context = DAG.getContext();
875 LPadToCallSiteMap.clear();
878 /// clear - Clear out the current SelectionDAG and the associated
879 /// state and prepare this SelectionDAGBuilder object to be used
880 /// for a new block. This doesn't clear out information about
881 /// additional blocks that are needed to complete switch lowering
882 /// or PHI node updating; that information is cleared out as it is
884 void SelectionDAGBuilder::clear() {
886 UnusedArgNodeMap.clear();
887 PendingLoads.clear();
888 PendingExports.clear();
891 SDNodeOrder = LowestSDNodeOrder;
892 StatepointLowering.clear();
895 /// clearDanglingDebugInfo - Clear the dangling debug information
896 /// map. This function is separated from the clear so that debug
897 /// information that is dangling in a basic block can be properly
898 /// resolved in a different basic block. This allows the
899 /// SelectionDAG to resolve dangling debug information attached
901 void SelectionDAGBuilder::clearDanglingDebugInfo() {
902 DanglingDebugInfoMap.clear();
905 /// getRoot - Return the current virtual root of the Selection DAG,
906 /// flushing any PendingLoad items. This must be done before emitting
907 /// a store or any other node that may need to be ordered after any
908 /// prior load instructions.
910 SDValue SelectionDAGBuilder::getRoot() {
911 if (PendingLoads.empty())
912 return DAG.getRoot();
914 if (PendingLoads.size() == 1) {
915 SDValue Root = PendingLoads[0];
917 PendingLoads.clear();
921 // Otherwise, we have to make a token factor node.
922 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
924 PendingLoads.clear();
929 /// getControlRoot - Similar to getRoot, but instead of flushing all the
930 /// PendingLoad items, flush all the PendingExports items. It is necessary
931 /// to do this before emitting a terminator instruction.
933 SDValue SelectionDAGBuilder::getControlRoot() {
934 SDValue Root = DAG.getRoot();
936 if (PendingExports.empty())
939 // Turn all of the CopyToReg chains into one factored node.
940 if (Root.getOpcode() != ISD::EntryToken) {
941 unsigned i = 0, e = PendingExports.size();
942 for (; i != e; ++i) {
943 assert(PendingExports[i].getNode()->getNumOperands() > 1);
944 if (PendingExports[i].getNode()->getOperand(0) == Root)
945 break; // Don't add the root if we already indirectly depend on it.
949 PendingExports.push_back(Root);
952 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
954 PendingExports.clear();
959 void SelectionDAGBuilder::visit(const Instruction &I) {
960 // Set up outgoing PHI node register values before emitting the terminator.
961 if (isa<TerminatorInst>(&I))
962 HandlePHINodesInSuccessorBlocks(I.getParent());
968 visit(I.getOpcode(), I);
970 if (!isa<TerminatorInst>(&I) && !HasTailCall)
971 CopyToExportRegsIfNeeded(&I);
976 void SelectionDAGBuilder::visitPHI(const PHINode &) {
977 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
980 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
981 // Note: this doesn't use InstVisitor, because it has to work with
982 // ConstantExpr's in addition to instructions.
984 default: llvm_unreachable("Unknown instruction type encountered!");
985 // Build the switch statement using the Instruction.def file.
986 #define HANDLE_INST(NUM, OPCODE, CLASS) \
987 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
988 #include "llvm/IR/Instruction.def"
992 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
993 // generate the debug data structures now that we've seen its definition.
994 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
996 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
998 const DbgValueInst *DI = DDI.getDI();
999 DebugLoc dl = DDI.getdl();
1000 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1001 MDLocalVariable *Variable = DI->getVariable();
1002 MDExpression *Expr = DI->getExpression();
1003 assert(Variable->isValidLocationForIntrinsic(dl) &&
1004 "Expected inlined-at fields to agree");
1005 uint64_t Offset = DI->getOffset();
1006 // A dbg.value for an alloca is always indirect.
1007 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
1009 if (Val.getNode()) {
1010 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
1012 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
1013 IsIndirect, Offset, dl, DbgSDNodeOrder);
1014 DAG.AddDbgValue(SDV, Val.getNode(), false);
1017 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1018 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1022 /// getCopyFromRegs - If there was virtual register allocated for the value V
1023 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
1024 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
1025 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1028 if (It != FuncInfo.ValueMap.end()) {
1029 unsigned InReg = It->second;
1030 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(), InReg,
1032 SDValue Chain = DAG.getEntryNode();
1033 res = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1034 resolveDanglingDebugInfo(V, res);
1040 /// getValue - Return an SDValue for the given Value.
1041 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1042 // If we already have an SDValue for this value, use it. It's important
1043 // to do this first, so that we don't create a CopyFromReg if we already
1044 // have a regular SDValue.
1045 SDValue &N = NodeMap[V];
1046 if (N.getNode()) return N;
1048 // If there's a virtual register allocated and initialized for this
1050 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
1051 if (copyFromReg.getNode()) {
1055 // Otherwise create a new SDValue and remember it.
1056 SDValue Val = getValueImpl(V);
1058 resolveDanglingDebugInfo(V, Val);
1062 /// getNonRegisterValue - Return an SDValue for the given Value, but
1063 /// don't look in FuncInfo.ValueMap for a virtual register.
1064 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1065 // If we already have an SDValue for this value, use it.
1066 SDValue &N = NodeMap[V];
1067 if (N.getNode()) return N;
1069 // Otherwise create a new SDValue and remember it.
1070 SDValue Val = getValueImpl(V);
1072 resolveDanglingDebugInfo(V, Val);
1076 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1077 /// Create an SDValue for the given value.
1078 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1081 if (const Constant *C = dyn_cast<Constant>(V)) {
1082 EVT VT = TLI.getValueType(V->getType(), true);
1084 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1085 return DAG.getConstant(*CI, VT);
1087 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1088 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1090 if (isa<ConstantPointerNull>(C)) {
1091 unsigned AS = V->getType()->getPointerAddressSpace();
1092 return DAG.getConstant(0, TLI.getPointerTy(AS));
1095 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1096 return DAG.getConstantFP(*CFP, VT);
1098 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1099 return DAG.getUNDEF(VT);
1101 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1102 visit(CE->getOpcode(), *CE);
1103 SDValue N1 = NodeMap[V];
1104 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1108 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1109 SmallVector<SDValue, 4> Constants;
1110 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1112 SDNode *Val = getValue(*OI).getNode();
1113 // If the operand is an empty aggregate, there are no values.
1115 // Add each leaf value from the operand to the Constants list
1116 // to form a flattened list of all the values.
1117 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1118 Constants.push_back(SDValue(Val, i));
1121 return DAG.getMergeValues(Constants, getCurSDLoc());
1124 if (const ConstantDataSequential *CDS =
1125 dyn_cast<ConstantDataSequential>(C)) {
1126 SmallVector<SDValue, 4> Ops;
1127 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1128 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1129 // Add each leaf value from the operand to the Constants list
1130 // to form a flattened list of all the values.
1131 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1132 Ops.push_back(SDValue(Val, i));
1135 if (isa<ArrayType>(CDS->getType()))
1136 return DAG.getMergeValues(Ops, getCurSDLoc());
1137 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1141 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1142 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1143 "Unknown struct or array constant!");
1145 SmallVector<EVT, 4> ValueVTs;
1146 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1147 unsigned NumElts = ValueVTs.size();
1149 return SDValue(); // empty struct
1150 SmallVector<SDValue, 4> Constants(NumElts);
1151 for (unsigned i = 0; i != NumElts; ++i) {
1152 EVT EltVT = ValueVTs[i];
1153 if (isa<UndefValue>(C))
1154 Constants[i] = DAG.getUNDEF(EltVT);
1155 else if (EltVT.isFloatingPoint())
1156 Constants[i] = DAG.getConstantFP(0, EltVT);
1158 Constants[i] = DAG.getConstant(0, EltVT);
1161 return DAG.getMergeValues(Constants, getCurSDLoc());
1164 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1165 return DAG.getBlockAddress(BA, VT);
1167 VectorType *VecTy = cast<VectorType>(V->getType());
1168 unsigned NumElements = VecTy->getNumElements();
1170 // Now that we know the number and type of the elements, get that number of
1171 // elements into the Ops array based on what kind of constant it is.
1172 SmallVector<SDValue, 16> Ops;
1173 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1174 for (unsigned i = 0; i != NumElements; ++i)
1175 Ops.push_back(getValue(CV->getOperand(i)));
1177 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1178 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1181 if (EltVT.isFloatingPoint())
1182 Op = DAG.getConstantFP(0, EltVT);
1184 Op = DAG.getConstant(0, EltVT);
1185 Ops.assign(NumElements, Op);
1188 // Create a BUILD_VECTOR node.
1189 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1192 // If this is a static alloca, generate it as the frameindex instead of
1194 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1195 DenseMap<const AllocaInst*, int>::iterator SI =
1196 FuncInfo.StaticAllocaMap.find(AI);
1197 if (SI != FuncInfo.StaticAllocaMap.end())
1198 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1201 // If this is an instruction which fast-isel has deferred, select it now.
1202 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1203 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1204 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1205 SDValue Chain = DAG.getEntryNode();
1206 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1209 llvm_unreachable("Can't get register for value!");
1212 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1213 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1214 SDValue Chain = getControlRoot();
1215 SmallVector<ISD::OutputArg, 8> Outs;
1216 SmallVector<SDValue, 8> OutVals;
1218 if (!FuncInfo.CanLowerReturn) {
1219 unsigned DemoteReg = FuncInfo.DemoteRegister;
1220 const Function *F = I.getParent()->getParent();
1222 // Emit a store of the return value through the virtual register.
1223 // Leave Outs empty so that LowerReturn won't try to load return
1224 // registers the usual way.
1225 SmallVector<EVT, 1> PtrValueVTs;
1226 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1229 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1230 SDValue RetOp = getValue(I.getOperand(0));
1232 SmallVector<EVT, 4> ValueVTs;
1233 SmallVector<uint64_t, 4> Offsets;
1234 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1235 unsigned NumValues = ValueVTs.size();
1237 SmallVector<SDValue, 4> Chains(NumValues);
1238 for (unsigned i = 0; i != NumValues; ++i) {
1239 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1240 RetPtr.getValueType(), RetPtr,
1241 DAG.getIntPtrConstant(Offsets[i]));
1243 DAG.getStore(Chain, getCurSDLoc(),
1244 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1245 // FIXME: better loc info would be nice.
1246 Add, MachinePointerInfo(), false, false, 0);
1249 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1250 MVT::Other, Chains);
1251 } else if (I.getNumOperands() != 0) {
1252 SmallVector<EVT, 4> ValueVTs;
1253 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1254 unsigned NumValues = ValueVTs.size();
1256 SDValue RetOp = getValue(I.getOperand(0));
1258 const Function *F = I.getParent()->getParent();
1260 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1261 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 ExtendKind = ISD::SIGN_EXTEND;
1264 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1266 ExtendKind = ISD::ZERO_EXTEND;
1268 LLVMContext &Context = F->getContext();
1269 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1272 for (unsigned j = 0; j != NumValues; ++j) {
1273 EVT VT = ValueVTs[j];
1275 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1276 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1278 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1279 MVT PartVT = TLI.getRegisterType(Context, VT);
1280 SmallVector<SDValue, 4> Parts(NumParts);
1281 getCopyToParts(DAG, getCurSDLoc(),
1282 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1283 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1285 // 'inreg' on function refers to return value
1286 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1290 // Propagate extension type if any
1291 if (ExtendKind == ISD::SIGN_EXTEND)
1293 else if (ExtendKind == ISD::ZERO_EXTEND)
1296 for (unsigned i = 0; i < NumParts; ++i) {
1297 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1298 VT, /*isfixed=*/true, 0, 0));
1299 OutVals.push_back(Parts[i]);
1305 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1306 CallingConv::ID CallConv =
1307 DAG.getMachineFunction().getFunction()->getCallingConv();
1308 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1309 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1311 // Verify that the target's LowerReturn behaved as expected.
1312 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1313 "LowerReturn didn't return a valid chain!");
1315 // Update the DAG with the new chain value resulting from return lowering.
1319 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1320 /// created for it, emit nodes to copy the value into the virtual
1322 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1324 if (V->getType()->isEmptyTy())
1327 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1328 if (VMI != FuncInfo.ValueMap.end()) {
1329 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1330 CopyValueToVirtualRegister(V, VMI->second);
1334 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1335 /// the current basic block, add it to ValueMap now so that we'll get a
1337 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1338 // No need to export constants.
1339 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1341 // Already exported?
1342 if (FuncInfo.isExportedInst(V)) return;
1344 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1345 CopyValueToVirtualRegister(V, Reg);
1348 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1349 const BasicBlock *FromBB) {
1350 // The operands of the setcc have to be in this block. We don't know
1351 // how to export them from some other block.
1352 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1353 // Can export from current BB.
1354 if (VI->getParent() == FromBB)
1357 // Is already exported, noop.
1358 return FuncInfo.isExportedInst(V);
1361 // If this is an argument, we can export it if the BB is the entry block or
1362 // if it is already exported.
1363 if (isa<Argument>(V)) {
1364 if (FromBB == &FromBB->getParent()->getEntryBlock())
1367 // Otherwise, can only export this if it is already exported.
1368 return FuncInfo.isExportedInst(V);
1371 // Otherwise, constants can always be exported.
1375 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1376 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1377 const MachineBasicBlock *Dst) const {
1378 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1381 const BasicBlock *SrcBB = Src->getBasicBlock();
1382 const BasicBlock *DstBB = Dst->getBasicBlock();
1383 return BPI->getEdgeWeight(SrcBB, DstBB);
1386 void SelectionDAGBuilder::
1387 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1388 uint32_t Weight /* = 0 */) {
1390 Weight = getEdgeWeight(Src, Dst);
1391 Src->addSuccessor(Dst, Weight);
1395 static bool InBlock(const Value *V, const BasicBlock *BB) {
1396 if (const Instruction *I = dyn_cast<Instruction>(V))
1397 return I->getParent() == BB;
1401 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1402 /// This function emits a branch and is used at the leaves of an OR or an
1403 /// AND operator tree.
1406 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1407 MachineBasicBlock *TBB,
1408 MachineBasicBlock *FBB,
1409 MachineBasicBlock *CurBB,
1410 MachineBasicBlock *SwitchBB,
1413 const BasicBlock *BB = CurBB->getBasicBlock();
1415 // If the leaf of the tree is a comparison, merge the condition into
1417 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1418 // The operands of the cmp have to be in this block. We don't know
1419 // how to export them from some other block. If this is the first block
1420 // of the sequence, no exporting is needed.
1421 if (CurBB == SwitchBB ||
1422 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1423 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1424 ISD::CondCode Condition;
1425 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1426 Condition = getICmpCondCode(IC->getPredicate());
1427 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1428 Condition = getFCmpCondCode(FC->getPredicate());
1429 if (TM.Options.NoNaNsFPMath)
1430 Condition = getFCmpCodeWithoutNaN(Condition);
1432 (void)Condition; // silence warning.
1433 llvm_unreachable("Unknown compare instruction");
1436 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1437 TBB, FBB, CurBB, TWeight, FWeight);
1438 SwitchCases.push_back(CB);
1443 // Create a CaseBlock record representing this branch.
1444 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1445 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1446 SwitchCases.push_back(CB);
1449 /// Scale down both weights to fit into uint32_t.
1450 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1451 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1452 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1453 NewTrue = NewTrue / Scale;
1454 NewFalse = NewFalse / Scale;
1457 /// FindMergedConditions - If Cond is an expression like
1458 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1459 MachineBasicBlock *TBB,
1460 MachineBasicBlock *FBB,
1461 MachineBasicBlock *CurBB,
1462 MachineBasicBlock *SwitchBB,
1463 unsigned Opc, uint32_t TWeight,
1465 // If this node is not part of the or/and tree, emit it as a branch.
1466 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1467 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1468 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1469 BOp->getParent() != CurBB->getBasicBlock() ||
1470 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1471 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1472 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1477 // Create TmpBB after CurBB.
1478 MachineFunction::iterator BBI = CurBB;
1479 MachineFunction &MF = DAG.getMachineFunction();
1480 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1481 CurBB->getParent()->insert(++BBI, TmpBB);
1483 if (Opc == Instruction::Or) {
1484 // Codegen X | Y as:
1493 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1494 // The requirement is that
1495 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1496 // = TrueProb for orignal BB.
1497 // Assuming the orignal weights are A and B, one choice is to set BB1's
1498 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1500 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1501 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1502 // TmpBB, but the math is more complicated.
1504 uint64_t NewTrueWeight = TWeight;
1505 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1506 ScaleWeights(NewTrueWeight, NewFalseWeight);
1507 // Emit the LHS condition.
1508 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1509 NewTrueWeight, NewFalseWeight);
1511 NewTrueWeight = TWeight;
1512 NewFalseWeight = 2 * (uint64_t)FWeight;
1513 ScaleWeights(NewTrueWeight, NewFalseWeight);
1514 // Emit the RHS condition into TmpBB.
1515 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1516 NewTrueWeight, NewFalseWeight);
1518 assert(Opc == Instruction::And && "Unknown merge op!");
1519 // Codegen X & Y as:
1527 // This requires creation of TmpBB after CurBB.
1529 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1530 // The requirement is that
1531 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1532 // = FalseProb for orignal BB.
1533 // Assuming the orignal weights are A and B, one choice is to set BB1's
1534 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1536 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1538 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1539 uint64_t NewFalseWeight = FWeight;
1540 ScaleWeights(NewTrueWeight, NewFalseWeight);
1541 // Emit the LHS condition.
1542 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1543 NewTrueWeight, NewFalseWeight);
1545 NewTrueWeight = 2 * (uint64_t)TWeight;
1546 NewFalseWeight = FWeight;
1547 ScaleWeights(NewTrueWeight, NewFalseWeight);
1548 // Emit the RHS condition into TmpBB.
1549 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1550 NewTrueWeight, NewFalseWeight);
1554 /// If the set of cases should be emitted as a series of branches, return true.
1555 /// If we should emit this as a bunch of and/or'd together conditions, return
1558 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1559 if (Cases.size() != 2) return true;
1561 // If this is two comparisons of the same values or'd or and'd together, they
1562 // will get folded into a single comparison, so don't emit two blocks.
1563 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1564 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1565 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1566 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1570 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1571 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1572 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1573 Cases[0].CC == Cases[1].CC &&
1574 isa<Constant>(Cases[0].CmpRHS) &&
1575 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1576 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1578 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1585 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1586 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1588 // Update machine-CFG edges.
1589 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1591 if (I.isUnconditional()) {
1592 // Update machine-CFG edges.
1593 BrMBB->addSuccessor(Succ0MBB);
1595 // If this is not a fall-through branch or optimizations are switched off,
1597 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1598 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1599 MVT::Other, getControlRoot(),
1600 DAG.getBasicBlock(Succ0MBB)));
1605 // If this condition is one of the special cases we handle, do special stuff
1607 const Value *CondVal = I.getCondition();
1608 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1610 // If this is a series of conditions that are or'd or and'd together, emit
1611 // this as a sequence of branches instead of setcc's with and/or operations.
1612 // As long as jumps are not expensive, this should improve performance.
1613 // For example, instead of something like:
1626 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1627 if (!DAG.getTargetLoweringInfo().isJumpExpensive() &&
1628 BOp->hasOneUse() && (BOp->getOpcode() == Instruction::And ||
1629 BOp->getOpcode() == Instruction::Or)) {
1630 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1631 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1632 getEdgeWeight(BrMBB, Succ1MBB));
1633 // If the compares in later blocks need to use values not currently
1634 // exported from this block, export them now. This block should always
1635 // be the first entry.
1636 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1638 // Allow some cases to be rejected.
1639 if (ShouldEmitAsBranches(SwitchCases)) {
1640 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1641 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1642 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1645 // Emit the branch for this block.
1646 visitSwitchCase(SwitchCases[0], BrMBB);
1647 SwitchCases.erase(SwitchCases.begin());
1651 // Okay, we decided not to do this, remove any inserted MBB's and clear
1653 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1654 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1656 SwitchCases.clear();
1660 // Create a CaseBlock record representing this branch.
1661 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1662 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1664 // Use visitSwitchCase to actually insert the fast branch sequence for this
1666 visitSwitchCase(CB, BrMBB);
1669 /// visitSwitchCase - Emits the necessary code to represent a single node in
1670 /// the binary search tree resulting from lowering a switch instruction.
1671 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1672 MachineBasicBlock *SwitchBB) {
1674 SDValue CondLHS = getValue(CB.CmpLHS);
1675 SDLoc dl = getCurSDLoc();
1677 // Build the setcc now.
1679 // Fold "(X == true)" to X and "(X == false)" to !X to
1680 // handle common cases produced by branch lowering.
1681 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1682 CB.CC == ISD::SETEQ)
1684 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1685 CB.CC == ISD::SETEQ) {
1686 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1687 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1689 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1691 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1693 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1694 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1696 SDValue CmpOp = getValue(CB.CmpMHS);
1697 EVT VT = CmpOp.getValueType();
1699 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1700 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1703 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1704 VT, CmpOp, DAG.getConstant(Low, VT));
1705 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1706 DAG.getConstant(High-Low, VT), ISD::SETULE);
1710 // Update successor info
1711 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1712 // TrueBB and FalseBB are always different unless the incoming IR is
1713 // degenerate. This only happens when running llc on weird IR.
1714 if (CB.TrueBB != CB.FalseBB)
1715 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1717 // If the lhs block is the next block, invert the condition so that we can
1718 // fall through to the lhs instead of the rhs block.
1719 if (CB.TrueBB == NextBlock(SwitchBB)) {
1720 std::swap(CB.TrueBB, CB.FalseBB);
1721 SDValue True = DAG.getConstant(1, Cond.getValueType());
1722 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1725 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1726 MVT::Other, getControlRoot(), Cond,
1727 DAG.getBasicBlock(CB.TrueBB));
1729 // Insert the false branch. Do this even if it's a fall through branch,
1730 // this makes it easier to do DAG optimizations which require inverting
1731 // the branch condition.
1732 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1733 DAG.getBasicBlock(CB.FalseBB));
1735 DAG.setRoot(BrCond);
1738 /// visitJumpTable - Emit JumpTable node in the current MBB
1739 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1740 // Emit the code for the jump table
1741 assert(JT.Reg != -1U && "Should lower JT Header first!");
1742 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy();
1743 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1745 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1746 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1747 MVT::Other, Index.getValue(1),
1749 DAG.setRoot(BrJumpTable);
1752 /// visitJumpTableHeader - This function emits necessary code to produce index
1753 /// in the JumpTable from switch case.
1754 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1755 JumpTableHeader &JTH,
1756 MachineBasicBlock *SwitchBB) {
1757 // Subtract the lowest switch case value from the value being switched on and
1758 // conditional branch to default mbb if the result is greater than the
1759 // difference between smallest and largest cases.
1760 SDValue SwitchOp = getValue(JTH.SValue);
1761 EVT VT = SwitchOp.getValueType();
1762 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1763 DAG.getConstant(JTH.First, VT));
1765 // The SDNode we just created, which holds the value being switched on minus
1766 // the smallest case value, needs to be copied to a virtual register so it
1767 // can be used as an index into the jump table in a subsequent basic block.
1768 // This value may be smaller or larger than the target's pointer type, and
1769 // therefore require extension or truncating.
1770 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1771 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI.getPointerTy());
1773 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1774 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1775 JumpTableReg, SwitchOp);
1776 JT.Reg = JumpTableReg;
1778 // Emit the range check for the jump table, and branch to the default block
1779 // for the switch statement if the value being switched on exceeds the largest
1780 // case in the switch.
1782 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1783 Sub.getValueType()),
1784 Sub, DAG.getConstant(JTH.Last - JTH.First, VT), ISD::SETUGT);
1786 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1787 MVT::Other, CopyTo, CMP,
1788 DAG.getBasicBlock(JT.Default));
1790 // Avoid emitting unnecessary branches to the next block.
1791 if (JT.MBB != NextBlock(SwitchBB))
1792 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1793 DAG.getBasicBlock(JT.MBB));
1795 DAG.setRoot(BrCond);
1798 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1799 /// tail spliced into a stack protector check success bb.
1801 /// For a high level explanation of how this fits into the stack protector
1802 /// generation see the comment on the declaration of class
1803 /// StackProtectorDescriptor.
1804 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1805 MachineBasicBlock *ParentBB) {
1807 // First create the loads to the guard/stack slot for the comparison.
1808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1809 EVT PtrTy = TLI.getPointerTy();
1811 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1812 int FI = MFI->getStackProtectorIndex();
1814 const Value *IRGuard = SPD.getGuard();
1815 SDValue GuardPtr = getValue(IRGuard);
1816 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1819 TLI.getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1823 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1824 // guard value from the virtual register holding the value. Otherwise, emit a
1825 // volatile load to retrieve the stack guard value.
1826 unsigned GuardReg = SPD.getGuardReg();
1828 if (GuardReg && TLI.useLoadStackGuardNode())
1829 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), GuardReg,
1832 Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1833 GuardPtr, MachinePointerInfo(IRGuard, 0),
1834 true, false, false, Align);
1836 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1838 MachinePointerInfo::getFixedStack(FI),
1839 true, false, false, Align);
1841 // Perform the comparison via a subtract/getsetcc.
1842 EVT VT = Guard.getValueType();
1843 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1846 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1847 Sub.getValueType()),
1848 Sub, DAG.getConstant(0, VT), ISD::SETNE);
1850 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1851 // branch to failure MBB.
1852 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1853 MVT::Other, StackSlot.getOperand(0),
1854 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1855 // Otherwise branch to success MBB.
1856 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1858 DAG.getBasicBlock(SPD.getSuccessMBB()));
1863 /// Codegen the failure basic block for a stack protector check.
1865 /// A failure stack protector machine basic block consists simply of a call to
1866 /// __stack_chk_fail().
1868 /// For a high level explanation of how this fits into the stack protector
1869 /// generation see the comment on the declaration of class
1870 /// StackProtectorDescriptor.
1872 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1873 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1875 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1876 nullptr, 0, false, getCurSDLoc(), false, false).second;
1880 /// visitBitTestHeader - This function emits necessary code to produce value
1881 /// suitable for "bit tests"
1882 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1883 MachineBasicBlock *SwitchBB) {
1884 // Subtract the minimum value
1885 SDValue SwitchOp = getValue(B.SValue);
1886 EVT VT = SwitchOp.getValueType();
1887 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1888 DAG.getConstant(B.First, VT));
1891 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1893 DAG.getSetCC(getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(),
1894 Sub.getValueType()),
1895 Sub, DAG.getConstant(B.Range, VT), ISD::SETUGT);
1897 // Determine the type of the test operands.
1898 bool UsePtrType = false;
1899 if (!TLI.isTypeLegal(VT))
1902 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1903 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1904 // Switch table case range are encoded into series of masks.
1905 // Just use pointer type, it's guaranteed to fit.
1911 VT = TLI.getPointerTy();
1912 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1915 B.RegVT = VT.getSimpleVT();
1916 B.Reg = FuncInfo.CreateReg(B.RegVT);
1917 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1920 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1922 addSuccessorWithWeight(SwitchBB, B.Default);
1923 addSuccessorWithWeight(SwitchBB, MBB);
1925 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1926 MVT::Other, CopyTo, RangeCmp,
1927 DAG.getBasicBlock(B.Default));
1929 // Avoid emitting unnecessary branches to the next block.
1930 if (MBB != NextBlock(SwitchBB))
1931 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1932 DAG.getBasicBlock(MBB));
1934 DAG.setRoot(BrRange);
1937 /// visitBitTestCase - this function produces one "bit test"
1938 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1939 MachineBasicBlock* NextMBB,
1940 uint32_t BranchWeightToNext,
1943 MachineBasicBlock *SwitchBB) {
1945 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1948 unsigned PopCount = countPopulation(B.Mask);
1949 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1950 if (PopCount == 1) {
1951 // Testing for a single bit; just compare the shift count with what it
1952 // would need to be to shift a 1 bit in that position.
1954 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1955 DAG.getConstant(countTrailingZeros(B.Mask), VT), ISD::SETEQ);
1956 } else if (PopCount == BB.Range) {
1957 // There is only one zero bit in the range, test for it directly.
1959 getCurSDLoc(), TLI.getSetCCResultType(*DAG.getContext(), VT), ShiftOp,
1960 DAG.getConstant(countTrailingOnes(B.Mask), VT), ISD::SETNE);
1962 // Make desired shift
1963 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1964 DAG.getConstant(1, VT), ShiftOp);
1966 // Emit bit tests and jumps
1967 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1968 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1969 Cmp = DAG.getSetCC(getCurSDLoc(),
1970 TLI.getSetCCResultType(*DAG.getContext(), VT), AndOp,
1971 DAG.getConstant(0, VT), ISD::SETNE);
1974 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1975 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1976 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1977 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1979 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1980 MVT::Other, getControlRoot(),
1981 Cmp, DAG.getBasicBlock(B.TargetBB));
1983 // Avoid emitting unnecessary branches to the next block.
1984 if (NextMBB != NextBlock(SwitchBB))
1985 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1986 DAG.getBasicBlock(NextMBB));
1991 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1992 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1994 // Retrieve successors.
1995 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1996 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1998 const Value *Callee(I.getCalledValue());
1999 const Function *Fn = dyn_cast<Function>(Callee);
2000 if (isa<InlineAsm>(Callee))
2002 else if (Fn && Fn->isIntrinsic()) {
2003 switch (Fn->getIntrinsicID()) {
2005 llvm_unreachable("Cannot invoke this intrinsic");
2006 case Intrinsic::donothing:
2007 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2009 case Intrinsic::experimental_patchpoint_void:
2010 case Intrinsic::experimental_patchpoint_i64:
2011 visitPatchpoint(&I, LandingPad);
2013 case Intrinsic::experimental_gc_statepoint:
2014 LowerStatepoint(ImmutableStatepoint(&I), LandingPad);
2018 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2020 // If the value of the invoke is used outside of its defining block, make it
2021 // available as a virtual register.
2022 // We already took care of the exported value for the statepoint instruction
2023 // during call to the LowerStatepoint.
2024 if (!isStatepoint(I)) {
2025 CopyToExportRegsIfNeeded(&I);
2028 // Update successor info
2029 addSuccessorWithWeight(InvokeMBB, Return);
2030 addSuccessorWithWeight(InvokeMBB, LandingPad);
2032 // Drop into normal successor.
2033 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2034 MVT::Other, getControlRoot(),
2035 DAG.getBasicBlock(Return)));
2038 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2039 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2042 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2043 assert(FuncInfo.MBB->isLandingPad() &&
2044 "Call to landingpad not in landing pad!");
2046 MachineBasicBlock *MBB = FuncInfo.MBB;
2047 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2048 AddLandingPadInfo(LP, MMI, MBB);
2050 // If there aren't registers to copy the values into (e.g., during SjLj
2051 // exceptions), then don't bother to create these DAG nodes.
2052 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2053 if (TLI.getExceptionPointerRegister() == 0 &&
2054 TLI.getExceptionSelectorRegister() == 0)
2057 SmallVector<EVT, 2> ValueVTs;
2058 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
2059 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2061 // Get the two live-in registers as SDValues. The physregs have already been
2062 // copied into virtual registers.
2064 if (FuncInfo.ExceptionPointerVirtReg) {
2065 Ops[0] = DAG.getZExtOrTrunc(
2066 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2067 FuncInfo.ExceptionPointerVirtReg, TLI.getPointerTy()),
2068 getCurSDLoc(), ValueVTs[0]);
2070 Ops[0] = DAG.getConstant(0, TLI.getPointerTy());
2072 Ops[1] = DAG.getZExtOrTrunc(
2073 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2074 FuncInfo.ExceptionSelectorVirtReg, TLI.getPointerTy()),
2075 getCurSDLoc(), ValueVTs[1]);
2078 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2079 DAG.getVTList(ValueVTs), Ops);
2084 SelectionDAGBuilder::visitLandingPadClauseBB(GlobalValue *ClauseGV,
2085 MachineBasicBlock *LPadBB) {
2086 SDValue Chain = getControlRoot();
2088 // Get the typeid that we will dispatch on later.
2089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2090 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy());
2091 unsigned VReg = FuncInfo.MF->getRegInfo().createVirtualRegister(RC);
2092 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(ClauseGV);
2093 SDValue Sel = DAG.getConstant(TypeID, TLI.getPointerTy());
2094 Chain = DAG.getCopyToReg(Chain, getCurSDLoc(), VReg, Sel);
2096 // Branch to the main landing pad block.
2097 MachineBasicBlock *ClauseMBB = FuncInfo.MBB;
2098 ClauseMBB->addSuccessor(LPadBB);
2099 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
2100 DAG.getBasicBlock(LPadBB)));
2104 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2105 /// small case ranges).
2106 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2107 CaseRecVector& WorkList,
2109 MachineBasicBlock *Default,
2110 MachineBasicBlock *SwitchBB) {
2111 // Size is the number of Cases represented by this range.
2112 size_t Size = CR.Range.second - CR.Range.first;
2116 // Get the MachineFunction which holds the current MBB. This is used when
2117 // inserting any additional MBBs necessary to represent the switch.
2118 MachineFunction *CurMF = FuncInfo.MF;
2120 // Figure out which block is immediately after the current one.
2121 MachineBasicBlock *NextMBB = nullptr;
2122 MachineFunction::iterator BBI = CR.CaseBB;
2123 if (++BBI != FuncInfo.MF->end())
2126 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2127 // If any two of the cases has the same destination, and if one value
2128 // is the same as the other, but has one bit unset that the other has set,
2129 // use bit manipulation to do two compares at once. For example:
2130 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2131 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2132 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2133 if (Size == 2 && CR.CaseBB == SwitchBB) {
2134 Case &Small = *CR.Range.first;
2135 Case &Big = *(CR.Range.second-1);
2137 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2138 const APInt& SmallValue = Small.Low->getValue();
2139 const APInt& BigValue = Big.Low->getValue();
2141 // Check that there is only one bit different.
2142 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2143 (SmallValue | BigValue) == BigValue) {
2144 // Isolate the common bit.
2145 APInt CommonBit = BigValue & ~SmallValue;
2146 assert((SmallValue | CommonBit) == BigValue &&
2147 CommonBit.countPopulation() == 1 && "Not a common bit?");
2149 SDValue CondLHS = getValue(SV);
2150 EVT VT = CondLHS.getValueType();
2151 SDLoc DL = getCurSDLoc();
2153 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2154 DAG.getConstant(CommonBit, VT));
2155 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2156 Or, DAG.getConstant(BigValue, VT),
2159 // Update successor info.
2160 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2161 addSuccessorWithWeight(SwitchBB, Small.BB,
2162 Small.ExtraWeight + Big.ExtraWeight);
2163 addSuccessorWithWeight(SwitchBB, Default,
2164 // The default destination is the first successor in IR.
2165 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2167 // Insert the true branch.
2168 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2169 getControlRoot(), Cond,
2170 DAG.getBasicBlock(Small.BB));
2172 // Insert the false branch.
2173 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2174 DAG.getBasicBlock(Default));
2176 DAG.setRoot(BrCond);
2182 // Order cases by weight so the most likely case will be checked first.
2183 uint32_t UnhandledWeights = 0;
2185 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2186 uint32_t IWeight = I->ExtraWeight;
2187 UnhandledWeights += IWeight;
2188 for (CaseItr J = CR.Range.first; J < I; ++J) {
2189 uint32_t JWeight = J->ExtraWeight;
2190 if (IWeight > JWeight)
2195 // Rearrange the case blocks so that the last one falls through if possible.
2196 Case &BackCase = *(CR.Range.second-1);
2197 if (Size > 1 && NextMBB && Default != NextMBB && BackCase.BB != NextMBB) {
2198 // The last case block won't fall through into 'NextMBB' if we emit the
2199 // branches in this order. See if rearranging a case value would help.
2200 // We start at the bottom as it's the case with the least weight.
2201 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2202 if (I->BB == NextMBB) {
2203 std::swap(*I, BackCase);
2208 // Create a CaseBlock record representing a conditional branch to
2209 // the Case's target mbb if the value being switched on SV is equal
2211 MachineBasicBlock *CurBlock = CR.CaseBB;
2212 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2213 MachineBasicBlock *FallThrough;
2215 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2216 CurMF->insert(BBI, FallThrough);
2218 // Put SV in a virtual register to make it available from the new blocks.
2219 ExportFromCurrentBlock(SV);
2221 // If the last case doesn't match, go to the default block.
2222 FallThrough = Default;
2225 const Value *RHS, *LHS, *MHS;
2227 if (I->High == I->Low) {
2228 // This is just small small case range :) containing exactly 1 case
2230 LHS = SV; RHS = I->High; MHS = nullptr;
2233 LHS = I->Low; MHS = SV; RHS = I->High;
2236 // The false weight should be sum of all un-handled cases.
2237 UnhandledWeights -= I->ExtraWeight;
2238 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2240 /* trueweight */ I->ExtraWeight,
2241 /* falseweight */ UnhandledWeights);
2243 // If emitting the first comparison, just call visitSwitchCase to emit the
2244 // code into the current block. Otherwise, push the CaseBlock onto the
2245 // vector to be later processed by SDISel, and insert the node's MBB
2246 // before the next MBB.
2247 if (CurBlock == SwitchBB)
2248 visitSwitchCase(CB, SwitchBB);
2250 SwitchCases.push_back(CB);
2252 CurBlock = FallThrough;
2258 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2259 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2260 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
2263 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2264 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2265 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2266 return (LastExt - FirstExt + 1ULL);
2269 /// handleJTSwitchCase - Emit jumptable for current switch case range
2270 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2271 CaseRecVector &WorkList,
2273 MachineBasicBlock *Default,
2274 MachineBasicBlock *SwitchBB) {
2275 Case& FrontCase = *CR.Range.first;
2276 Case& BackCase = *(CR.Range.second-1);
2278 const APInt &First = FrontCase.Low->getValue();
2279 const APInt &Last = BackCase.High->getValue();
2281 APInt TSize(First.getBitWidth(), 0);
2282 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2285 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2286 if (!areJTsAllowed(TLI) || TSize.ult(TLI.getMinimumJumpTableEntries()))
2289 APInt Range = ComputeRange(First, Last);
2290 // The density is TSize / Range. Require at least 40%.
2291 // It should not be possible for IntTSize to saturate for sane code, but make
2292 // sure we handle Range saturation correctly.
2293 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2294 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2295 if (IntTSize * 10 < IntRange * 4)
2298 DEBUG(dbgs() << "Lowering jump table\n"
2299 << "First entry: " << First << ". Last entry: " << Last << '\n'
2300 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2302 // Get the MachineFunction which holds the current MBB. This is used when
2303 // inserting any additional MBBs necessary to represent the switch.
2304 MachineFunction *CurMF = FuncInfo.MF;
2306 // Figure out which block is immediately after the current one.
2307 MachineFunction::iterator BBI = CR.CaseBB;
2310 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2312 // Create a new basic block to hold the code for loading the address
2313 // of the jump table, and jumping to it. Update successor information;
2314 // we will either branch to the default case for the switch, or the jump
2316 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2317 CurMF->insert(BBI, JumpTableBB);
2319 addSuccessorWithWeight(CR.CaseBB, Default);
2320 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2322 // Build a vector of destination BBs, corresponding to each target
2323 // of the jump table. If the value of the jump table slot corresponds to
2324 // a case statement, push the case's BB onto the vector, otherwise, push
2326 std::vector<MachineBasicBlock*> DestBBs;
2328 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2329 const APInt &Low = I->Low->getValue();
2330 const APInt &High = I->High->getValue();
2332 if (Low.sle(TEI) && TEI.sle(High)) {
2333 DestBBs.push_back(I->BB);
2337 DestBBs.push_back(Default);
2341 // Calculate weight for each unique destination in CR.
2342 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2344 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2345 DestWeights[I->BB] += I->ExtraWeight;
2348 // Update successor info. Add one edge to each unique successor.
2349 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2350 for (MachineBasicBlock *DestBB : DestBBs) {
2351 if (!SuccsHandled[DestBB->getNumber()]) {
2352 SuccsHandled[DestBB->getNumber()] = true;
2353 auto I = DestWeights.find(DestBB);
2354 addSuccessorWithWeight(JumpTableBB, DestBB,
2355 I != DestWeights.end() ? I->second : 0);
2359 // Create a jump table index for this jump table.
2360 unsigned JTEncoding = TLI.getJumpTableEncoding();
2361 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2362 ->createJumpTableIndex(DestBBs);
2364 // Set the jump table information so that we can codegen it as a second
2365 // MachineBasicBlock
2366 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2367 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2368 if (CR.CaseBB == SwitchBB)
2369 visitJumpTableHeader(JT, JTH, SwitchBB);
2371 JTCases.push_back(JumpTableBlock(JTH, JT));
2375 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2377 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2378 CaseRecVector& WorkList,
2380 MachineBasicBlock* SwitchBB) {
2381 Case& FrontCase = *CR.Range.first;
2382 Case& BackCase = *(CR.Range.second-1);
2384 // Size is the number of Cases represented by this range.
2385 unsigned Size = CR.Range.second - CR.Range.first;
2387 const APInt &First = FrontCase.Low->getValue();
2388 const APInt &Last = BackCase.High->getValue();
2390 CaseItr Pivot = CR.Range.first + Size/2;
2392 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2393 // (heuristically) allow us to emit JumpTable's later.
2394 APInt TSize(First.getBitWidth(), 0);
2395 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2399 APInt LSize = FrontCase.size();
2400 APInt RSize = TSize-LSize;
2401 DEBUG(dbgs() << "Selecting best pivot: \n"
2402 << "First: " << First << ", Last: " << Last <<'\n'
2403 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2404 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2405 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2407 const APInt &LEnd = I->High->getValue();
2408 const APInt &RBegin = J->Low->getValue();
2409 APInt Range = ComputeRange(LEnd, RBegin);
2410 assert((Range - 2ULL).isNonNegative() &&
2411 "Invalid case distance");
2412 // Use volatile double here to avoid excess precision issues on some hosts,
2413 // e.g. that use 80-bit X87 registers.
2414 // Only consider the density of sub-ranges that actually have sufficient
2415 // entries to be lowered as a jump table.
2416 volatile double LDensity =
2417 LSize.ult(TLI.getMinimumJumpTableEntries())
2419 : LSize.roundToDouble() / (LEnd - First + 1ULL).roundToDouble();
2420 volatile double RDensity =
2421 RSize.ult(TLI.getMinimumJumpTableEntries())
2423 : RSize.roundToDouble() / (Last - RBegin + 1ULL).roundToDouble();
2424 volatile double Metric = Range.logBase2() * (LDensity + RDensity);
2425 // Should always split in some non-trivial place
2426 DEBUG(dbgs() <<"=>Step\n"
2427 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2428 << "LDensity: " << LDensity
2429 << ", RDensity: " << RDensity << '\n'
2430 << "Metric: " << Metric << '\n');
2431 if (FMetric < Metric) {
2434 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2441 if (FMetric == 0 || !areJTsAllowed(TLI))
2442 Pivot = CR.Range.first + Size/2;
2443 splitSwitchCase(CR, Pivot, WorkList, SV, SwitchBB);
2447 void SelectionDAGBuilder::splitSwitchCase(CaseRec &CR, CaseItr Pivot,
2448 CaseRecVector &WorkList,
2450 MachineBasicBlock *SwitchBB) {
2451 // Get the MachineFunction which holds the current MBB. This is used when
2452 // inserting any additional MBBs necessary to represent the switch.
2453 MachineFunction *CurMF = FuncInfo.MF;
2455 // Figure out which block is immediately after the current one.
2456 MachineFunction::iterator BBI = CR.CaseBB;
2459 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2461 CaseRange LHSR(CR.Range.first, Pivot);
2462 CaseRange RHSR(Pivot, CR.Range.second);
2463 const ConstantInt *C = Pivot->Low;
2464 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2466 // We know that we branch to the LHS if the Value being switched on is
2467 // less than the Pivot value, C. We use this to optimize our binary
2468 // tree a bit, by recognizing that if SV is greater than or equal to the
2469 // LHS's Case Value, and that Case Value is exactly one less than the
2470 // Pivot's Value, then we can branch directly to the LHS's Target,
2471 // rather than creating a leaf node for it.
2472 if ((LHSR.second - LHSR.first) == 1 && LHSR.first->High == CR.GE &&
2473 C->getValue() == (CR.GE->getValue() + 1LL)) {
2474 TrueBB = LHSR.first->BB;
2476 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2477 CurMF->insert(BBI, TrueBB);
2478 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2480 // Put SV in a virtual register to make it available from the new blocks.
2481 ExportFromCurrentBlock(SV);
2484 // Similar to the optimization above, if the Value being switched on is
2485 // known to be less than the Constant CR.LT, and the current Case Value
2486 // is CR.LT - 1, then we can branch directly to the target block for
2487 // the current Case Value, rather than emitting a RHS leaf node for it.
2488 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2489 RHSR.first->Low->getValue() == (CR.LT->getValue() - 1LL)) {
2490 FalseBB = RHSR.first->BB;
2492 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2493 CurMF->insert(BBI, FalseBB);
2494 WorkList.push_back(CaseRec(FalseBB, CR.LT, C, RHSR));
2496 // Put SV in a virtual register to make it available from the new blocks.
2497 ExportFromCurrentBlock(SV);
2500 // Create a CaseBlock record representing a conditional branch to
2501 // the LHS node if the value being switched on SV is less than C.
2502 // Otherwise, branch to LHS.
2503 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2505 if (CR.CaseBB == SwitchBB)
2506 visitSwitchCase(CB, SwitchBB);
2508 SwitchCases.push_back(CB);
2511 /// handleBitTestsSwitchCase - if current case range has few destination and
2512 /// range span less, than machine word bitwidth, encode case range into series
2513 /// of masks and emit bit tests with these masks.
2514 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2515 CaseRecVector& WorkList,
2517 MachineBasicBlock* Default,
2518 MachineBasicBlock* SwitchBB) {
2519 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2520 EVT PTy = TLI.getPointerTy();
2521 unsigned IntPtrBits = PTy.getSizeInBits();
2523 Case& FrontCase = *CR.Range.first;
2524 Case& BackCase = *(CR.Range.second-1);
2526 // Get the MachineFunction which holds the current MBB. This is used when
2527 // inserting any additional MBBs necessary to represent the switch.
2528 MachineFunction *CurMF = FuncInfo.MF;
2530 // If target does not have legal shift left, do not emit bit tests at all.
2531 if (!TLI.isOperationLegal(ISD::SHL, PTy))
2535 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2536 // Single case counts one, case range - two.
2537 numCmps += (I->Low == I->High ? 1 : 2);
2540 // Count unique destinations
2541 SmallSet<MachineBasicBlock*, 4> Dests;
2542 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2543 Dests.insert(I->BB);
2544 if (Dests.size() > 3)
2545 // Don't bother the code below, if there are too much unique destinations
2548 DEBUG(dbgs() << "Total number of unique destinations: "
2549 << Dests.size() << '\n'
2550 << "Total number of comparisons: " << numCmps << '\n');
2552 // Compute span of values.
2553 const APInt& minValue = FrontCase.Low->getValue();
2554 const APInt& maxValue = BackCase.High->getValue();
2555 APInt cmpRange = maxValue - minValue;
2557 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2558 << "Low bound: " << minValue << '\n'
2559 << "High bound: " << maxValue << '\n');
2561 if (cmpRange.uge(IntPtrBits) ||
2562 (!(Dests.size() == 1 && numCmps >= 3) &&
2563 !(Dests.size() == 2 && numCmps >= 5) &&
2564 !(Dests.size() >= 3 && numCmps >= 6)))
2567 DEBUG(dbgs() << "Emitting bit tests\n");
2568 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2570 // Optimize the case where all the case values fit in a
2571 // word without having to subtract minValue. In this case,
2572 // we can optimize away the subtraction.
2573 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2574 cmpRange = maxValue;
2576 lowBound = minValue;
2579 CaseBitsVector CasesBits;
2580 unsigned i, count = 0;
2582 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2583 MachineBasicBlock* Dest = I->BB;
2584 for (i = 0; i < count; ++i)
2585 if (Dest == CasesBits[i].BB)
2589 assert((count < 3) && "Too much destinations to test!");
2590 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2594 const APInt& lowValue = I->Low->getValue();
2595 const APInt& highValue = I->High->getValue();
2597 uint64_t lo = (lowValue - lowBound).getZExtValue();
2598 uint64_t hi = (highValue - lowBound).getZExtValue();
2599 CasesBits[i].ExtraWeight += I->ExtraWeight;
2601 for (uint64_t j = lo; j <= hi; j++) {
2602 CasesBits[i].Mask |= 1ULL << j;
2603 CasesBits[i].Bits++;
2607 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2611 // Figure out which block is immediately after the current one.
2612 MachineFunction::iterator BBI = CR.CaseBB;
2615 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2617 DEBUG(dbgs() << "Cases:\n");
2618 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2619 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2620 << ", Bits: " << CasesBits[i].Bits
2621 << ", BB: " << CasesBits[i].BB << '\n');
2623 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2624 CurMF->insert(BBI, CaseBB);
2625 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2627 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2629 // Put SV in a virtual register to make it available from the new blocks.
2630 ExportFromCurrentBlock(SV);
2633 BitTestBlock BTB(lowBound, cmpRange, SV,
2634 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2635 CR.CaseBB, Default, std::move(BTC));
2637 if (CR.CaseBB == SwitchBB)
2638 visitBitTestHeader(BTB, SwitchBB);
2640 BitTestCases.push_back(std::move(BTB));
2645 void SelectionDAGBuilder::Clusterify(CaseVector &Cases, const SwitchInst *SI) {
2646 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2648 // Extract cases from the switch and sort them.
2649 typedef std::pair<const ConstantInt*, unsigned> CasePair;
2650 std::vector<CasePair> Sorted;
2651 Sorted.reserve(SI->getNumCases());
2652 for (auto I : SI->cases())
2653 Sorted.push_back(std::make_pair(I.getCaseValue(), I.getSuccessorIndex()));
2654 std::sort(Sorted.begin(), Sorted.end(), [](CasePair a, CasePair b) {
2655 return a.first->getValue().slt(b.first->getValue());
2658 // Merge adjacent cases with the same destination, build Cases vector.
2659 assert(Cases.empty() && "Cases should be empty before Clusterify;");
2660 Cases.reserve(SI->getNumCases());
2661 MachineBasicBlock *PreviousSucc = nullptr;
2662 for (CasePair &CP : Sorted) {
2663 const ConstantInt *CaseVal = CP.first;
2664 unsigned SuccIndex = CP.second;
2665 MachineBasicBlock *Succ = FuncInfo.MBBMap[SI->getSuccessor(SuccIndex)];
2666 uint32_t Weight = BPI ? BPI->getEdgeWeight(SI->getParent(), SuccIndex) : 0;
2668 if (PreviousSucc == Succ &&
2669 (CaseVal->getValue() - Cases.back().High->getValue()) == 1) {
2670 // If this case has the same successor and is a neighbour, merge it into
2671 // the previous cluster.
2672 Cases.back().High = CaseVal;
2673 Cases.back().ExtraWeight += Weight;
2675 Cases.push_back(Case(CaseVal, CaseVal, Succ, Weight));
2678 PreviousSucc = Succ;
2683 for (auto &I : Cases)
2684 // A range counts double, since it requires two compares.
2685 numCmps += I.Low != I.High ? 2 : 1;
2687 dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2688 << ". Total compares: " << numCmps << '\n';
2692 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2693 MachineBasicBlock *Last) {
2695 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2696 if (JTCases[i].first.HeaderBB == First)
2697 JTCases[i].first.HeaderBB = Last;
2699 // Update BitTestCases.
2700 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2701 if (BitTestCases[i].Parent == First)
2702 BitTestCases[i].Parent = Last;
2705 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2706 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2708 // Create a vector of Cases, sorted so that we can efficiently create a binary
2709 // search tree from them.
2711 Clusterify(Cases, &SI);
2713 // Get the default destination MBB.
2714 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2716 if (isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg()) &&
2718 // Replace an unreachable default destination with the most popular case
2720 DenseMap<const BasicBlock *, unsigned> Popularity;
2721 unsigned MaxPop = 0;
2722 const BasicBlock *MaxBB = nullptr;
2723 for (auto I : SI.cases()) {
2724 const BasicBlock *BB = I.getCaseSuccessor();
2725 if (++Popularity[BB] > MaxPop) {
2726 MaxPop = Popularity[BB];
2734 Default = FuncInfo.MBBMap[MaxBB];
2736 // Remove cases that were pointing to the destination that is now the default.
2737 Cases.erase(std::remove_if(Cases.begin(), Cases.end(),
2738 [&](const Case &C) { return C.BB == Default; }),
2742 // If there is only the default destination, go there directly.
2743 if (Cases.empty()) {
2744 // Update machine-CFG edges.
2745 SwitchMBB->addSuccessor(Default);
2747 // If this is not a fall-through branch, emit the branch.
2748 if (Default != NextBlock(SwitchMBB)) {
2749 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
2750 getControlRoot(), DAG.getBasicBlock(Default)));
2755 // Get the Value to be switched on.
2756 const Value *SV = SI.getCondition();
2758 // Push the initial CaseRec onto the worklist
2759 CaseRecVector WorkList;
2760 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2761 CaseRange(Cases.begin(),Cases.end())));
2763 while (!WorkList.empty()) {
2764 // Grab a record representing a case range to process off the worklist
2765 CaseRec CR = WorkList.back();
2766 WorkList.pop_back();
2768 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2771 // If the range has few cases (two or less) emit a series of specific
2773 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2776 // If the switch has more than N blocks, and is at least 40% dense, and the
2777 // target supports indirect branches, then emit a jump table rather than
2778 // lowering the switch to a binary tree of conditional branches.
2779 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2780 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2783 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2784 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2785 handleBTSplitSwitchCase(CR, WorkList, SV, SwitchMBB);
2789 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2790 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2792 // Update machine-CFG edges with unique successors.
2793 SmallSet<BasicBlock*, 32> Done;
2794 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2795 BasicBlock *BB = I.getSuccessor(i);
2796 bool Inserted = Done.insert(BB).second;
2800 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2801 addSuccessorWithWeight(IndirectBrMBB, Succ);
2804 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2805 MVT::Other, getControlRoot(),
2806 getValue(I.getAddress())));
2809 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2810 if (DAG.getTarget().Options.TrapUnreachable)
2811 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2814 void SelectionDAGBuilder::visitFSub(const User &I) {
2815 // -0.0 - X --> fneg
2816 Type *Ty = I.getType();
2817 if (isa<Constant>(I.getOperand(0)) &&
2818 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2819 SDValue Op2 = getValue(I.getOperand(1));
2820 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2821 Op2.getValueType(), Op2));
2825 visitBinary(I, ISD::FSUB);
2828 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2829 SDValue Op1 = getValue(I.getOperand(0));
2830 SDValue Op2 = getValue(I.getOperand(1));
2835 if (const OverflowingBinaryOperator *OFBinOp =
2836 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2837 nuw = OFBinOp->hasNoUnsignedWrap();
2838 nsw = OFBinOp->hasNoSignedWrap();
2840 if (const PossiblyExactOperator *ExactOp =
2841 dyn_cast<const PossiblyExactOperator>(&I))
2842 exact = ExactOp->isExact();
2844 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2845 Op1, Op2, nuw, nsw, exact);
2846 setValue(&I, BinNodeValue);
2849 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2850 SDValue Op1 = getValue(I.getOperand(0));
2851 SDValue Op2 = getValue(I.getOperand(1));
2854 DAG.getTargetLoweringInfo().getShiftAmountTy(Op2.getValueType());
2856 // Coerce the shift amount to the right type if we can.
2857 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2858 unsigned ShiftSize = ShiftTy.getSizeInBits();
2859 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2860 SDLoc DL = getCurSDLoc();
2862 // If the operand is smaller than the shift count type, promote it.
2863 if (ShiftSize > Op2Size)
2864 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2866 // If the operand is larger than the shift count type but the shift
2867 // count type has enough bits to represent any shift value, truncate
2868 // it now. This is a common case and it exposes the truncate to
2869 // optimization early.
2870 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2871 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2872 // Otherwise we'll need to temporarily settle for some other convenient
2873 // type. Type legalization will make adjustments once the shiftee is split.
2875 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2882 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2884 if (const OverflowingBinaryOperator *OFBinOp =
2885 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2886 nuw = OFBinOp->hasNoUnsignedWrap();
2887 nsw = OFBinOp->hasNoSignedWrap();
2889 if (const PossiblyExactOperator *ExactOp =
2890 dyn_cast<const PossiblyExactOperator>(&I))
2891 exact = ExactOp->isExact();
2894 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2899 void SelectionDAGBuilder::visitSDiv(const User &I) {
2900 SDValue Op1 = getValue(I.getOperand(0));
2901 SDValue Op2 = getValue(I.getOperand(1));
2903 // Turn exact SDivs into multiplications.
2904 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2906 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2907 !isa<ConstantSDNode>(Op1) &&
2908 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2909 setValue(&I, DAG.getTargetLoweringInfo()
2910 .BuildExactSDIV(Op1, Op2, getCurSDLoc(), DAG));
2912 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2916 void SelectionDAGBuilder::visitICmp(const User &I) {
2917 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2918 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2919 predicate = IC->getPredicate();
2920 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2921 predicate = ICmpInst::Predicate(IC->getPredicate());
2922 SDValue Op1 = getValue(I.getOperand(0));
2923 SDValue Op2 = getValue(I.getOperand(1));
2924 ISD::CondCode Opcode = getICmpCondCode(predicate);
2926 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2927 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2930 void SelectionDAGBuilder::visitFCmp(const User &I) {
2931 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2932 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2933 predicate = FC->getPredicate();
2934 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2935 predicate = FCmpInst::Predicate(FC->getPredicate());
2936 SDValue Op1 = getValue(I.getOperand(0));
2937 SDValue Op2 = getValue(I.getOperand(1));
2938 ISD::CondCode Condition = getFCmpCondCode(predicate);
2939 if (TM.Options.NoNaNsFPMath)
2940 Condition = getFCmpCodeWithoutNaN(Condition);
2941 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2942 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2945 void SelectionDAGBuilder::visitSelect(const User &I) {
2946 SmallVector<EVT, 4> ValueVTs;
2947 ComputeValueVTs(DAG.getTargetLoweringInfo(), I.getType(), ValueVTs);
2948 unsigned NumValues = ValueVTs.size();
2949 if (NumValues == 0) return;
2951 SmallVector<SDValue, 4> Values(NumValues);
2952 SDValue Cond = getValue(I.getOperand(0));
2953 SDValue TrueVal = getValue(I.getOperand(1));
2954 SDValue FalseVal = getValue(I.getOperand(2));
2955 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2956 ISD::VSELECT : ISD::SELECT;
2958 for (unsigned i = 0; i != NumValues; ++i)
2959 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2960 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2962 SDValue(TrueVal.getNode(),
2963 TrueVal.getResNo() + i),
2964 SDValue(FalseVal.getNode(),
2965 FalseVal.getResNo() + i));
2967 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2968 DAG.getVTList(ValueVTs), Values));
2971 void SelectionDAGBuilder::visitTrunc(const User &I) {
2972 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2973 SDValue N = getValue(I.getOperand(0));
2974 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2975 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2978 void SelectionDAGBuilder::visitZExt(const User &I) {
2979 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2980 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2981 SDValue N = getValue(I.getOperand(0));
2982 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2983 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2986 void SelectionDAGBuilder::visitSExt(const User &I) {
2987 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2988 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2989 SDValue N = getValue(I.getOperand(0));
2990 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
2991 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2994 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2995 // FPTrunc is never a no-op cast, no need to check
2996 SDValue N = getValue(I.getOperand(0));
2997 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2998 EVT DestVT = TLI.getValueType(I.getType());
2999 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(), DestVT, N,
3000 DAG.getTargetConstant(0, TLI.getPointerTy())));
3003 void SelectionDAGBuilder::visitFPExt(const User &I) {
3004 // FPExt is never a no-op cast, no need to check
3005 SDValue N = getValue(I.getOperand(0));
3006 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3007 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
3010 void SelectionDAGBuilder::visitFPToUI(const User &I) {
3011 // FPToUI is never a no-op cast, no need to check
3012 SDValue N = getValue(I.getOperand(0));
3013 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3014 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
3017 void SelectionDAGBuilder::visitFPToSI(const User &I) {
3018 // FPToSI is never a no-op cast, no need to check
3019 SDValue N = getValue(I.getOperand(0));
3020 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3021 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
3024 void SelectionDAGBuilder::visitUIToFP(const User &I) {
3025 // UIToFP is never a no-op cast, no need to check
3026 SDValue N = getValue(I.getOperand(0));
3027 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3028 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
3031 void SelectionDAGBuilder::visitSIToFP(const User &I) {
3032 // SIToFP is never a no-op cast, no need to check
3033 SDValue N = getValue(I.getOperand(0));
3034 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3035 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
3038 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
3039 // What to do depends on the size of the integer and the size of the pointer.
3040 // We can either truncate, zero extend, or no-op, accordingly.
3041 SDValue N = getValue(I.getOperand(0));
3042 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3043 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3046 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
3047 // What to do depends on the size of the integer and the size of the pointer.
3048 // We can either truncate, zero extend, or no-op, accordingly.
3049 SDValue N = getValue(I.getOperand(0));
3050 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3051 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
3054 void SelectionDAGBuilder::visitBitCast(const User &I) {
3055 SDValue N = getValue(I.getOperand(0));
3056 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(I.getType());
3058 // BitCast assures us that source and destination are the same size so this is
3059 // either a BITCAST or a no-op.
3060 if (DestVT != N.getValueType())
3061 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
3062 DestVT, N)); // convert types.
3063 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
3064 // might fold any kind of constant expression to an integer constant and that
3065 // is not what we are looking for. Only regcognize a bitcast of a genuine
3066 // constant integer as an opaque constant.
3067 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
3068 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3071 setValue(&I, N); // noop cast.
3074 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3075 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3076 const Value *SV = I.getOperand(0);
3077 SDValue N = getValue(SV);
3078 EVT DestVT = TLI.getValueType(I.getType());
3080 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3081 unsigned DestAS = I.getType()->getPointerAddressSpace();
3083 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3084 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3089 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3090 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3091 SDValue InVec = getValue(I.getOperand(0));
3092 SDValue InVal = getValue(I.getOperand(1));
3093 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3094 getCurSDLoc(), TLI.getVectorIdxTy());
3095 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3096 TLI.getValueType(I.getType()), InVec, InVal, InIdx));
3099 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3100 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3101 SDValue InVec = getValue(I.getOperand(0));
3102 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3103 getCurSDLoc(), TLI.getVectorIdxTy());
3104 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3105 TLI.getValueType(I.getType()), InVec, InIdx));
3108 // Utility for visitShuffleVector - Return true if every element in Mask,
3109 // beginning from position Pos and ending in Pos+Size, falls within the
3110 // specified sequential range [L, L+Pos). or is undef.
3111 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3112 unsigned Pos, unsigned Size, int Low) {
3113 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3114 if (Mask[i] >= 0 && Mask[i] != Low)
3119 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3120 SDValue Src1 = getValue(I.getOperand(0));
3121 SDValue Src2 = getValue(I.getOperand(1));
3123 SmallVector<int, 8> Mask;
3124 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3125 unsigned MaskNumElts = Mask.size();
3127 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3128 EVT VT = TLI.getValueType(I.getType());
3129 EVT SrcVT = Src1.getValueType();
3130 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3132 if (SrcNumElts == MaskNumElts) {
3133 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3138 // Normalize the shuffle vector since mask and vector length don't match.
3139 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3140 // Mask is longer than the source vectors and is a multiple of the source
3141 // vectors. We can use concatenate vector to make the mask and vectors
3143 if (SrcNumElts*2 == MaskNumElts) {
3144 // First check for Src1 in low and Src2 in high
3145 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3146 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3147 // The shuffle is concatenating two vectors together.
3148 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3152 // Then check for Src2 in low and Src1 in high
3153 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3154 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3155 // The shuffle is concatenating two vectors together.
3156 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3162 // Pad both vectors with undefs to make them the same length as the mask.
3163 unsigned NumConcat = MaskNumElts / SrcNumElts;
3164 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3165 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3166 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3168 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3169 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3173 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3174 getCurSDLoc(), VT, MOps1);
3175 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3176 getCurSDLoc(), VT, MOps2);
3178 // Readjust mask for new input vector length.
3179 SmallVector<int, 8> MappedOps;
3180 for (unsigned i = 0; i != MaskNumElts; ++i) {
3182 if (Idx >= (int)SrcNumElts)
3183 Idx -= SrcNumElts - MaskNumElts;
3184 MappedOps.push_back(Idx);
3187 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3192 if (SrcNumElts > MaskNumElts) {
3193 // Analyze the access pattern of the vector to see if we can extract
3194 // two subvectors and do the shuffle. The analysis is done by calculating
3195 // the range of elements the mask access on both vectors.
3196 int MinRange[2] = { static_cast<int>(SrcNumElts),
3197 static_cast<int>(SrcNumElts)};
3198 int MaxRange[2] = {-1, -1};
3200 for (unsigned i = 0; i != MaskNumElts; ++i) {
3206 if (Idx >= (int)SrcNumElts) {
3210 if (Idx > MaxRange[Input])
3211 MaxRange[Input] = Idx;
3212 if (Idx < MinRange[Input])
3213 MinRange[Input] = Idx;
3216 // Check if the access is smaller than the vector size and can we find
3217 // a reasonable extract index.
3218 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3220 int StartIdx[2]; // StartIdx to extract from
3221 for (unsigned Input = 0; Input < 2; ++Input) {
3222 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3223 RangeUse[Input] = 0; // Unused
3224 StartIdx[Input] = 0;
3228 // Find a good start index that is a multiple of the mask length. Then
3229 // see if the rest of the elements are in range.
3230 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3231 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3232 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3233 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3236 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3237 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3240 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3241 // Extract appropriate subvector and generate a vector shuffle
3242 for (unsigned Input = 0; Input < 2; ++Input) {
3243 SDValue &Src = Input == 0 ? Src1 : Src2;
3244 if (RangeUse[Input] == 0)
3245 Src = DAG.getUNDEF(VT);
3248 ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT, Src,
3249 DAG.getConstant(StartIdx[Input], TLI.getVectorIdxTy()));
3252 // Calculate new mask.
3253 SmallVector<int, 8> MappedOps;
3254 for (unsigned i = 0; i != MaskNumElts; ++i) {
3257 if (Idx < (int)SrcNumElts)
3260 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3262 MappedOps.push_back(Idx);
3265 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3271 // We can't use either concat vectors or extract subvectors so fall back to
3272 // replacing the shuffle with extract and build vector.
3273 // to insert and build vector.
3274 EVT EltVT = VT.getVectorElementType();
3275 EVT IdxVT = TLI.getVectorIdxTy();
3276 SmallVector<SDValue,8> Ops;
3277 for (unsigned i = 0; i != MaskNumElts; ++i) {
3282 Res = DAG.getUNDEF(EltVT);
3284 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3285 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3287 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3288 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3294 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops));
3297 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3298 const Value *Op0 = I.getOperand(0);
3299 const Value *Op1 = I.getOperand(1);
3300 Type *AggTy = I.getType();
3301 Type *ValTy = Op1->getType();
3302 bool IntoUndef = isa<UndefValue>(Op0);
3303 bool FromUndef = isa<UndefValue>(Op1);
3305 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3307 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3308 SmallVector<EVT, 4> AggValueVTs;
3309 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3310 SmallVector<EVT, 4> ValValueVTs;
3311 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3313 unsigned NumAggValues = AggValueVTs.size();
3314 unsigned NumValValues = ValValueVTs.size();
3315 SmallVector<SDValue, 4> Values(NumAggValues);
3317 // Ignore an insertvalue that produces an empty object
3318 if (!NumAggValues) {
3319 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3323 SDValue Agg = getValue(Op0);
3325 // Copy the beginning value(s) from the original aggregate.
3326 for (; i != LinearIndex; ++i)
3327 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3328 SDValue(Agg.getNode(), Agg.getResNo() + i);
3329 // Copy values from the inserted value(s).
3331 SDValue Val = getValue(Op1);
3332 for (; i != LinearIndex + NumValValues; ++i)
3333 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3334 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3336 // Copy remaining value(s) from the original aggregate.
3337 for (; i != NumAggValues; ++i)
3338 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3339 SDValue(Agg.getNode(), Agg.getResNo() + i);
3341 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3342 DAG.getVTList(AggValueVTs), Values));
3345 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3346 const Value *Op0 = I.getOperand(0);
3347 Type *AggTy = Op0->getType();
3348 Type *ValTy = I.getType();
3349 bool OutOfUndef = isa<UndefValue>(Op0);
3351 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3354 SmallVector<EVT, 4> ValValueVTs;
3355 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3357 unsigned NumValValues = ValValueVTs.size();
3359 // Ignore a extractvalue that produces an empty object
3360 if (!NumValValues) {
3361 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3365 SmallVector<SDValue, 4> Values(NumValValues);
3367 SDValue Agg = getValue(Op0);
3368 // Copy out the selected value(s).
3369 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3370 Values[i - LinearIndex] =
3372 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3373 SDValue(Agg.getNode(), Agg.getResNo() + i);
3375 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3376 DAG.getVTList(ValValueVTs), Values));
3379 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3380 Value *Op0 = I.getOperand(0);
3381 // Note that the pointer operand may be a vector of pointers. Take the scalar
3382 // element which holds a pointer.
3383 Type *Ty = Op0->getType()->getScalarType();
3384 unsigned AS = Ty->getPointerAddressSpace();
3385 SDValue N = getValue(Op0);
3387 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3389 const Value *Idx = *OI;
3390 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3391 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3394 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3395 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3396 DAG.getConstant(Offset, N.getValueType()));
3399 Ty = StTy->getElementType(Field);
3401 Ty = cast<SequentialType>(Ty)->getElementType();
3402 MVT PtrTy = DAG.getTargetLoweringInfo().getPointerTy(AS);
3403 unsigned PtrSize = PtrTy.getSizeInBits();
3404 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
3406 // If this is a constant subscript, handle it quickly.
3407 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
3410 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3411 SDValue OffsVal = DAG.getConstant(Offs, PtrTy);
3412 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N, OffsVal);
3416 // N = N + Idx * ElementSize;
3417 SDValue IdxN = getValue(Idx);
3419 // If the index is smaller or larger than intptr_t, truncate or extend
3421 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3423 // If this is a multiply by a power of two, turn it into a shl
3424 // immediately. This is a very common case.
3425 if (ElementSize != 1) {
3426 if (ElementSize.isPowerOf2()) {
3427 unsigned Amt = ElementSize.logBase2();
3428 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3429 N.getValueType(), IdxN,
3430 DAG.getConstant(Amt, IdxN.getValueType()));
3432 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3433 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3434 N.getValueType(), IdxN, Scale);
3438 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3439 N.getValueType(), N, IdxN);
3446 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3447 // If this is a fixed sized alloca in the entry block of the function,
3448 // allocate it statically on the stack.
3449 if (FuncInfo.StaticAllocaMap.count(&I))
3450 return; // getValue will auto-populate this.
3452 Type *Ty = I.getAllocatedType();
3453 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3454 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
3456 std::max((unsigned)TLI.getDataLayout()->getPrefTypeAlignment(Ty),
3459 SDValue AllocSize = getValue(I.getArraySize());
3461 EVT IntPtr = TLI.getPointerTy();
3462 if (AllocSize.getValueType() != IntPtr)
3463 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3465 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3467 DAG.getConstant(TySize, IntPtr));
3469 // Handle alignment. If the requested alignment is less than or equal to
3470 // the stack alignment, ignore it. If the size is greater than or equal to
3471 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3472 unsigned StackAlign =
3473 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3474 if (Align <= StackAlign)
3477 // Round the size of the allocation up to the stack alignment size
3478 // by add SA-1 to the size.
3479 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3480 AllocSize.getValueType(), AllocSize,
3481 DAG.getIntPtrConstant(StackAlign-1));
3483 // Mask out the low bits for alignment purposes.
3484 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3485 AllocSize.getValueType(), AllocSize,
3486 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3488 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3489 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3490 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(), VTs, Ops);
3492 DAG.setRoot(DSA.getValue(1));
3494 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3497 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3499 return visitAtomicLoad(I);
3501 const Value *SV = I.getOperand(0);
3502 SDValue Ptr = getValue(SV);
3504 Type *Ty = I.getType();
3506 bool isVolatile = I.isVolatile();
3507 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3508 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr;
3509 unsigned Alignment = I.getAlignment();
3512 I.getAAMetadata(AAInfo);
3513 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3515 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3516 SmallVector<EVT, 4> ValueVTs;
3517 SmallVector<uint64_t, 4> Offsets;
3518 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3519 unsigned NumValues = ValueVTs.size();
3524 bool ConstantMemory = false;
3525 if (isVolatile || NumValues > MaxParallelChains)
3526 // Serialize volatile loads with other side effects.
3528 else if (AA->pointsToConstantMemory(
3529 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), AAInfo))) {
3530 // Do not serialize (non-volatile) loads of constant memory with anything.
3531 Root = DAG.getEntryNode();
3532 ConstantMemory = true;
3534 // Do not serialize non-volatile loads against each other.
3535 Root = DAG.getRoot();
3539 Root = TLI.prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3541 SmallVector<SDValue, 4> Values(NumValues);
3542 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3544 EVT PtrVT = Ptr.getValueType();
3545 unsigned ChainI = 0;
3546 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3547 // Serializing loads here may result in excessive register pressure, and
3548 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3549 // could recover a bit by hoisting nodes upward in the chain by recognizing
3550 // they are side-effect free or do not alias. The optimizer should really
3551 // avoid this case by converting large object/array copies to llvm.memcpy
3552 // (MaxParallelChains should always remain as failsafe).
3553 if (ChainI == MaxParallelChains) {
3554 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3555 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3556 makeArrayRef(Chains.data(), ChainI));
3560 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3562 DAG.getConstant(Offsets[i], PtrVT));
3563 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3564 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3565 isNonTemporal, isInvariant, Alignment, AAInfo,
3569 Chains[ChainI] = L.getValue(1);
3572 if (!ConstantMemory) {
3573 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3574 makeArrayRef(Chains.data(), ChainI));
3578 PendingLoads.push_back(Chain);
3581 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3582 DAG.getVTList(ValueVTs), Values));
3585 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3587 return visitAtomicStore(I);
3589 const Value *SrcV = I.getOperand(0);
3590 const Value *PtrV = I.getOperand(1);
3592 SmallVector<EVT, 4> ValueVTs;
3593 SmallVector<uint64_t, 4> Offsets;
3594 ComputeValueVTs(DAG.getTargetLoweringInfo(), SrcV->getType(),
3595 ValueVTs, &Offsets);
3596 unsigned NumValues = ValueVTs.size();
3600 // Get the lowered operands. Note that we do this after
3601 // checking if NumResults is zero, because with zero results
3602 // the operands won't have values in the map.
3603 SDValue Src = getValue(SrcV);
3604 SDValue Ptr = getValue(PtrV);
3606 SDValue Root = getRoot();
3607 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3609 EVT PtrVT = Ptr.getValueType();
3610 bool isVolatile = I.isVolatile();
3611 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3612 unsigned Alignment = I.getAlignment();
3615 I.getAAMetadata(AAInfo);
3617 unsigned ChainI = 0;
3618 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3619 // See visitLoad comments.
3620 if (ChainI == MaxParallelChains) {
3621 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3622 makeArrayRef(Chains.data(), ChainI));
3626 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3627 DAG.getConstant(Offsets[i], PtrVT));
3628 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3629 SDValue(Src.getNode(), Src.getResNo() + i),
3630 Add, MachinePointerInfo(PtrV, Offsets[i]),
3631 isVolatile, isNonTemporal, Alignment, AAInfo);
3632 Chains[ChainI] = St;
3635 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
3636 makeArrayRef(Chains.data(), ChainI));
3637 DAG.setRoot(StoreNode);
3640 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3641 SDLoc sdl = getCurSDLoc();
3643 // llvm.masked.store.*(Src0, Ptr, alignemt, Mask)
3644 Value *PtrOperand = I.getArgOperand(1);
3645 SDValue Ptr = getValue(PtrOperand);
3646 SDValue Src0 = getValue(I.getArgOperand(0));
3647 SDValue Mask = getValue(I.getArgOperand(3));
3648 EVT VT = Src0.getValueType();
3649 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3651 Alignment = DAG.getEVTAlignment(VT);
3654 I.getAAMetadata(AAInfo);
3656 MachineMemOperand *MMO =
3657 DAG.getMachineFunction().
3658 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3659 MachineMemOperand::MOStore, VT.getStoreSize(),
3661 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3663 DAG.setRoot(StoreNode);
3664 setValue(&I, StoreNode);
3667 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3668 SDLoc sdl = getCurSDLoc();
3670 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3671 Value *PtrOperand = I.getArgOperand(0);
3672 SDValue Ptr = getValue(PtrOperand);
3673 SDValue Src0 = getValue(I.getArgOperand(3));
3674 SDValue Mask = getValue(I.getArgOperand(2));
3676 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3677 EVT VT = TLI.getValueType(I.getType());
3678 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3680 Alignment = DAG.getEVTAlignment(VT);
3683 I.getAAMetadata(AAInfo);
3684 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3686 SDValue InChain = DAG.getRoot();
3687 if (AA->pointsToConstantMemory(
3688 AliasAnalysis::Location(PtrOperand,
3689 AA->getTypeStoreSize(I.getType()),
3691 // Do not serialize (non-volatile) loads of constant memory with anything.
3692 InChain = DAG.getEntryNode();
3695 MachineMemOperand *MMO =
3696 DAG.getMachineFunction().
3697 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3698 MachineMemOperand::MOLoad, VT.getStoreSize(),
3699 Alignment, AAInfo, Ranges);
3701 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3703 SDValue OutChain = Load.getValue(1);
3704 DAG.setRoot(OutChain);
3708 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3709 SDLoc dl = getCurSDLoc();
3710 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3711 AtomicOrdering FailureOrder = I.getFailureOrdering();
3712 SynchronizationScope Scope = I.getSynchScope();
3714 SDValue InChain = getRoot();
3716 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3717 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3718 SDValue L = DAG.getAtomicCmpSwap(
3719 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3720 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3721 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3722 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3724 SDValue OutChain = L.getValue(2);
3727 DAG.setRoot(OutChain);
3730 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3731 SDLoc dl = getCurSDLoc();
3733 switch (I.getOperation()) {
3734 default: llvm_unreachable("Unknown atomicrmw operation");
3735 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3736 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3737 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3738 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3739 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3740 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3741 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3742 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3743 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3744 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3745 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3747 AtomicOrdering Order = I.getOrdering();
3748 SynchronizationScope Scope = I.getSynchScope();
3750 SDValue InChain = getRoot();
3753 DAG.getAtomic(NT, dl,
3754 getValue(I.getValOperand()).getSimpleValueType(),
3756 getValue(I.getPointerOperand()),
3757 getValue(I.getValOperand()),
3758 I.getPointerOperand(),
3759 /* Alignment=*/ 0, Order, Scope);
3761 SDValue OutChain = L.getValue(1);
3764 DAG.setRoot(OutChain);
3767 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3768 SDLoc dl = getCurSDLoc();
3769 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3772 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3773 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3774 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3777 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3778 SDLoc dl = getCurSDLoc();
3779 AtomicOrdering Order = I.getOrdering();
3780 SynchronizationScope Scope = I.getSynchScope();
3782 SDValue InChain = getRoot();
3784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3785 EVT VT = TLI.getValueType(I.getType());
3787 if (I.getAlignment() < VT.getSizeInBits() / 8)
3788 report_fatal_error("Cannot generate unaligned atomic load");
3790 MachineMemOperand *MMO =
3791 DAG.getMachineFunction().
3792 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3793 MachineMemOperand::MOVolatile |
3794 MachineMemOperand::MOLoad,
3796 I.getAlignment() ? I.getAlignment() :
3797 DAG.getEVTAlignment(VT));
3799 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3801 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3802 getValue(I.getPointerOperand()), MMO,
3805 SDValue OutChain = L.getValue(1);
3808 DAG.setRoot(OutChain);
3811 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3812 SDLoc dl = getCurSDLoc();
3814 AtomicOrdering Order = I.getOrdering();
3815 SynchronizationScope Scope = I.getSynchScope();
3817 SDValue InChain = getRoot();
3819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3820 EVT VT = TLI.getValueType(I.getValueOperand()->getType());
3822 if (I.getAlignment() < VT.getSizeInBits() / 8)
3823 report_fatal_error("Cannot generate unaligned atomic store");
3826 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3828 getValue(I.getPointerOperand()),
3829 getValue(I.getValueOperand()),
3830 I.getPointerOperand(), I.getAlignment(),
3833 DAG.setRoot(OutChain);
3836 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3838 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3839 unsigned Intrinsic) {
3840 bool HasChain = !I.doesNotAccessMemory();
3841 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3843 // Build the operand list.
3844 SmallVector<SDValue, 8> Ops;
3845 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3847 // We don't need to serialize loads against other loads.
3848 Ops.push_back(DAG.getRoot());
3850 Ops.push_back(getRoot());
3854 // Info is set by getTgtMemInstrinsic
3855 TargetLowering::IntrinsicInfo Info;
3856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3857 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3859 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3860 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3861 Info.opc == ISD::INTRINSIC_W_CHAIN)
3862 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3864 // Add all operands of the call to the operand list.
3865 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3866 SDValue Op = getValue(I.getArgOperand(i));
3870 SmallVector<EVT, 4> ValueVTs;
3871 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3874 ValueVTs.push_back(MVT::Other);
3876 SDVTList VTs = DAG.getVTList(ValueVTs);
3880 if (IsTgtIntrinsic) {
3881 // This is target intrinsic that touches memory
3882 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3883 VTs, Ops, Info.memVT,
3884 MachinePointerInfo(Info.ptrVal, Info.offset),
3885 Info.align, Info.vol,
3886 Info.readMem, Info.writeMem, Info.size);
3887 } else if (!HasChain) {
3888 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3889 } else if (!I.getType()->isVoidTy()) {
3890 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3892 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3896 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3898 PendingLoads.push_back(Chain);
3903 if (!I.getType()->isVoidTy()) {
3904 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3905 EVT VT = TLI.getValueType(PTy);
3906 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3909 setValue(&I, Result);
3913 /// GetSignificand - Get the significand and build it into a floating-point
3914 /// number with exponent of 1:
3916 /// Op = (Op & 0x007fffff) | 0x3f800000;
3918 /// where Op is the hexadecimal representation of floating point value.
3920 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3921 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3922 DAG.getConstant(0x007fffff, MVT::i32));
3923 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3924 DAG.getConstant(0x3f800000, MVT::i32));
3925 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3928 /// GetExponent - Get the exponent:
3930 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3932 /// where Op is the hexadecimal representation of floating point value.
3934 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3936 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3937 DAG.getConstant(0x7f800000, MVT::i32));
3938 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3939 DAG.getConstant(23, TLI.getPointerTy()));
3940 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3941 DAG.getConstant(127, MVT::i32));
3942 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3945 /// getF32Constant - Get 32-bit floating point constant.
3947 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3948 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3952 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3953 SelectionDAG &DAG) {
3954 // IntegerPartOfX = ((int32_t)(t0);
3955 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3957 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3958 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3959 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3961 // IntegerPartOfX <<= 23;
3962 IntegerPartOfX = DAG.getNode(
3963 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3964 DAG.getConstant(23, DAG.getTargetLoweringInfo().getPointerTy()));
3966 SDValue TwoToFractionalPartOfX;
3967 if (LimitFloatPrecision <= 6) {
3968 // For floating-point precision of 6:
3970 // TwoToFractionalPartOfX =
3972 // (0.735607626f + 0.252464424f * x) * x;
3974 // error 0.0144103317, which is 6 bits
3975 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3976 getF32Constant(DAG, 0x3e814304));
3977 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3978 getF32Constant(DAG, 0x3f3c50c8));
3979 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3980 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3981 getF32Constant(DAG, 0x3f7f5e7e));
3982 } else if (LimitFloatPrecision <= 12) {
3983 // For floating-point precision of 12:
3985 // TwoToFractionalPartOfX =
3988 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3990 // error 0.000107046256, which is 13 to 14 bits
3991 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3992 getF32Constant(DAG, 0x3da235e3));
3993 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3994 getF32Constant(DAG, 0x3e65b8f3));
3995 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3996 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3997 getF32Constant(DAG, 0x3f324b07));
3998 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3999 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4000 getF32Constant(DAG, 0x3f7ff8fd));
4001 } else { // LimitFloatPrecision <= 18
4002 // For floating-point precision of 18:
4004 // TwoToFractionalPartOfX =
4008 // (0.554906021e-1f +
4009 // (0.961591928e-2f +
4010 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4011 // error 2.47208000*10^(-7), which is better than 18 bits
4012 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4013 getF32Constant(DAG, 0x3924b03e));
4014 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4015 getF32Constant(DAG, 0x3ab24b87));
4016 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4017 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4018 getF32Constant(DAG, 0x3c1d8c17));
4019 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4020 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4021 getF32Constant(DAG, 0x3d634a1d));
4022 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4023 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4024 getF32Constant(DAG, 0x3e75fe14));
4025 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4026 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4027 getF32Constant(DAG, 0x3f317234));
4028 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4029 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4030 getF32Constant(DAG, 0x3f800000));
4033 // Add the exponent into the result in integer domain.
4034 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
4035 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4036 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
4039 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
4040 /// limited-precision mode.
4041 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4042 const TargetLowering &TLI) {
4043 if (Op.getValueType() == MVT::f32 &&
4044 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4046 // Put the exponent in the right bit position for later addition to the
4049 // #define LOG2OFe 1.4426950f
4050 // t0 = Op * LOG2OFe
4051 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4052 getF32Constant(DAG, 0x3fb8aa3b));
4053 return getLimitedPrecisionExp2(t0, dl, DAG);
4056 // No special expansion.
4057 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
4060 /// expandLog - Lower a log intrinsic. Handles the special sequences for
4061 /// limited-precision mode.
4062 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4063 const TargetLowering &TLI) {
4064 if (Op.getValueType() == MVT::f32 &&
4065 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4066 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4068 // Scale the exponent by log(2) [0.69314718f].
4069 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4070 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4071 getF32Constant(DAG, 0x3f317218));
4073 // Get the significand and build it into a floating-point number with
4075 SDValue X = GetSignificand(DAG, Op1, dl);
4077 SDValue LogOfMantissa;
4078 if (LimitFloatPrecision <= 6) {
4079 // For floating-point precision of 6:
4083 // (1.4034025f - 0.23903021f * x) * x;
4085 // error 0.0034276066, which is better than 8 bits
4086 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4087 getF32Constant(DAG, 0xbe74c456));
4088 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4089 getF32Constant(DAG, 0x3fb3a2b1));
4090 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4091 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4092 getF32Constant(DAG, 0x3f949a29));
4093 } else if (LimitFloatPrecision <= 12) {
4094 // For floating-point precision of 12:
4100 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4102 // error 0.000061011436, which is 14 bits
4103 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4104 getF32Constant(DAG, 0xbd67b6d6));
4105 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4106 getF32Constant(DAG, 0x3ee4f4b8));
4107 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4108 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4109 getF32Constant(DAG, 0x3fbc278b));
4110 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4111 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4112 getF32Constant(DAG, 0x40348e95));
4113 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4114 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4115 getF32Constant(DAG, 0x3fdef31a));
4116 } else { // LimitFloatPrecision <= 18
4117 // For floating-point precision of 18:
4125 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4127 // error 0.0000023660568, which is better than 18 bits
4128 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4129 getF32Constant(DAG, 0xbc91e5ac));
4130 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4131 getF32Constant(DAG, 0x3e4350aa));
4132 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4133 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4134 getF32Constant(DAG, 0x3f60d3e3));
4135 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4136 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4137 getF32Constant(DAG, 0x4011cdf0));
4138 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4139 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4140 getF32Constant(DAG, 0x406cfd1c));
4141 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4142 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4143 getF32Constant(DAG, 0x408797cb));
4144 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4145 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4146 getF32Constant(DAG, 0x4006dcab));
4149 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4152 // No special expansion.
4153 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4156 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4157 /// limited-precision mode.
4158 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4159 const TargetLowering &TLI) {
4160 if (Op.getValueType() == MVT::f32 &&
4161 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4162 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4164 // Get the exponent.
4165 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4167 // Get the significand and build it into a floating-point number with
4169 SDValue X = GetSignificand(DAG, Op1, dl);
4171 // Different possible minimax approximations of significand in
4172 // floating-point for various degrees of accuracy over [1,2].
4173 SDValue Log2ofMantissa;
4174 if (LimitFloatPrecision <= 6) {
4175 // For floating-point precision of 6:
4177 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4179 // error 0.0049451742, which is more than 7 bits
4180 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4181 getF32Constant(DAG, 0xbeb08fe0));
4182 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4183 getF32Constant(DAG, 0x40019463));
4184 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4185 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4186 getF32Constant(DAG, 0x3fd6633d));
4187 } else if (LimitFloatPrecision <= 12) {
4188 // For floating-point precision of 12:
4194 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4196 // error 0.0000876136000, which is better than 13 bits
4197 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4198 getF32Constant(DAG, 0xbda7262e));
4199 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4200 getF32Constant(DAG, 0x3f25280b));
4201 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4202 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4203 getF32Constant(DAG, 0x4007b923));
4204 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4205 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4206 getF32Constant(DAG, 0x40823e2f));
4207 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4208 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4209 getF32Constant(DAG, 0x4020d29c));
4210 } else { // LimitFloatPrecision <= 18
4211 // For floating-point precision of 18:
4220 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4222 // error 0.0000018516, which is better than 18 bits
4223 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4224 getF32Constant(DAG, 0xbcd2769e));
4225 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4226 getF32Constant(DAG, 0x3e8ce0b9));
4227 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4228 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4229 getF32Constant(DAG, 0x3fa22ae7));
4230 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4231 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4232 getF32Constant(DAG, 0x40525723));
4233 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4234 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4235 getF32Constant(DAG, 0x40aaf200));
4236 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4237 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4238 getF32Constant(DAG, 0x40c39dad));
4239 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4240 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4241 getF32Constant(DAG, 0x4042902c));
4244 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4247 // No special expansion.
4248 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4251 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4252 /// limited-precision mode.
4253 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4254 const TargetLowering &TLI) {
4255 if (Op.getValueType() == MVT::f32 &&
4256 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4257 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4259 // Scale the exponent by log10(2) [0.30102999f].
4260 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4261 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4262 getF32Constant(DAG, 0x3e9a209a));
4264 // Get the significand and build it into a floating-point number with
4266 SDValue X = GetSignificand(DAG, Op1, dl);
4268 SDValue Log10ofMantissa;
4269 if (LimitFloatPrecision <= 6) {
4270 // For floating-point precision of 6:
4272 // Log10ofMantissa =
4274 // (0.60948995f - 0.10380950f * x) * x;
4276 // error 0.0014886165, which is 6 bits
4277 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4278 getF32Constant(DAG, 0xbdd49a13));
4279 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4280 getF32Constant(DAG, 0x3f1c0789));
4281 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4282 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4283 getF32Constant(DAG, 0x3f011300));
4284 } else if (LimitFloatPrecision <= 12) {
4285 // For floating-point precision of 12:
4287 // Log10ofMantissa =
4290 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4292 // error 0.00019228036, which is better than 12 bits
4293 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4294 getF32Constant(DAG, 0x3d431f31));
4295 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4296 getF32Constant(DAG, 0x3ea21fb2));
4297 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4298 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4299 getF32Constant(DAG, 0x3f6ae232));
4300 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4301 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4302 getF32Constant(DAG, 0x3f25f7c3));
4303 } else { // LimitFloatPrecision <= 18
4304 // For floating-point precision of 18:
4306 // Log10ofMantissa =
4311 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4313 // error 0.0000037995730, which is better than 18 bits
4314 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4315 getF32Constant(DAG, 0x3c5d51ce));
4316 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4317 getF32Constant(DAG, 0x3e00685a));
4318 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4319 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4320 getF32Constant(DAG, 0x3efb6798));
4321 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4322 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4323 getF32Constant(DAG, 0x3f88d192));
4324 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4325 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4326 getF32Constant(DAG, 0x3fc4316c));
4327 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4328 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4329 getF32Constant(DAG, 0x3f57ce70));
4332 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4335 // No special expansion.
4336 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4339 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4340 /// limited-precision mode.
4341 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4342 const TargetLowering &TLI) {
4343 if (Op.getValueType() == MVT::f32 &&
4344 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4345 return getLimitedPrecisionExp2(Op, dl, DAG);
4347 // No special expansion.
4348 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4351 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4352 /// limited-precision mode with x == 10.0f.
4353 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4354 SelectionDAG &DAG, const TargetLowering &TLI) {
4355 bool IsExp10 = false;
4356 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4357 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4358 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4360 IsExp10 = LHSC->isExactlyValue(Ten);
4365 // Put the exponent in the right bit position for later addition to the
4368 // #define LOG2OF10 3.3219281f
4369 // t0 = Op * LOG2OF10;
4370 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4371 getF32Constant(DAG, 0x40549a78));
4372 return getLimitedPrecisionExp2(t0, dl, DAG);
4375 // No special expansion.
4376 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4380 /// ExpandPowI - Expand a llvm.powi intrinsic.
4381 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4382 SelectionDAG &DAG) {
4383 // If RHS is a constant, we can expand this out to a multiplication tree,
4384 // otherwise we end up lowering to a call to __powidf2 (for example). When
4385 // optimizing for size, we only want to do this if the expansion would produce
4386 // a small number of multiplies, otherwise we do the full expansion.
4387 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4388 // Get the exponent as a positive value.
4389 unsigned Val = RHSC->getSExtValue();
4390 if ((int)Val < 0) Val = -Val;
4392 // powi(x, 0) -> 1.0
4394 return DAG.getConstantFP(1.0, LHS.getValueType());
4396 const Function *F = DAG.getMachineFunction().getFunction();
4397 if (!F->hasFnAttribute(Attribute::OptimizeForSize) ||
4398 // If optimizing for size, don't insert too many multiplies. This
4399 // inserts up to 5 multiplies.
4400 countPopulation(Val) + Log2_32(Val) < 7) {
4401 // We use the simple binary decomposition method to generate the multiply
4402 // sequence. There are more optimal ways to do this (for example,
4403 // powi(x,15) generates one more multiply than it should), but this has
4404 // the benefit of being both really simple and much better than a libcall.
4405 SDValue Res; // Logically starts equal to 1.0
4406 SDValue CurSquare = LHS;
4410 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4412 Res = CurSquare; // 1.0*CurSquare.
4415 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4416 CurSquare, CurSquare);
4420 // If the original was negative, invert the result, producing 1/(x*x*x).
4421 if (RHSC->getSExtValue() < 0)
4422 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4423 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4428 // Otherwise, expand to a libcall.
4429 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4432 // getTruncatedArgReg - Find underlying register used for an truncated
4434 static unsigned getTruncatedArgReg(const SDValue &N) {
4435 if (N.getOpcode() != ISD::TRUNCATE)
4438 const SDValue &Ext = N.getOperand(0);
4439 if (Ext.getOpcode() == ISD::AssertZext ||
4440 Ext.getOpcode() == ISD::AssertSext) {
4441 const SDValue &CFR = Ext.getOperand(0);
4442 if (CFR.getOpcode() == ISD::CopyFromReg)
4443 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4444 if (CFR.getOpcode() == ISD::TRUNCATE)
4445 return getTruncatedArgReg(CFR);
4450 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4451 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4452 /// At the end of instruction selection, they will be inserted to the entry BB.
4453 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4454 const Value *V, MDLocalVariable *Variable, MDExpression *Expr,
4455 MDLocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4456 const Argument *Arg = dyn_cast<Argument>(V);
4460 MachineFunction &MF = DAG.getMachineFunction();
4461 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4463 // Ignore inlined function arguments here.
4465 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4466 DIVariable DV(Variable);
4467 if (!DV->getScope()->getSubprogram()->describes(MF.getFunction()))
4470 Optional<MachineOperand> Op;
4471 // Some arguments' frame index is recorded during argument lowering.
4472 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4473 Op = MachineOperand::CreateFI(FI);
4475 if (!Op && N.getNode()) {
4477 if (N.getOpcode() == ISD::CopyFromReg)
4478 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4480 Reg = getTruncatedArgReg(N);
4481 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4482 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4483 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4488 Op = MachineOperand::CreateReg(Reg, false);
4492 // Check if ValueMap has reg number.
4493 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4494 if (VMI != FuncInfo.ValueMap.end())
4495 Op = MachineOperand::CreateReg(VMI->second, false);
4498 if (!Op && N.getNode())
4499 // Check if frame index is available.
4500 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4501 if (FrameIndexSDNode *FINode =
4502 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4503 Op = MachineOperand::CreateFI(FINode->getIndex());
4508 assert(Variable->isValidLocationForIntrinsic(DL) &&
4509 "Expected inlined-at fields to agree");
4511 FuncInfo.ArgDbgValues.push_back(
4512 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4513 Op->getReg(), Offset, Variable, Expr));
4515 FuncInfo.ArgDbgValues.push_back(
4516 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4519 .addMetadata(Variable)
4520 .addMetadata(Expr));
4525 // VisualStudio defines setjmp as _setjmp
4526 #if defined(_MSC_VER) && defined(setjmp) && \
4527 !defined(setjmp_undefined_for_msvc)
4528 # pragma push_macro("setjmp")
4530 # define setjmp_undefined_for_msvc
4533 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4534 /// we want to emit this as a call to a named external function, return the name
4535 /// otherwise lower it and return null.
4537 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4538 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4539 SDLoc sdl = getCurSDLoc();
4540 DebugLoc dl = getCurDebugLoc();
4543 switch (Intrinsic) {
4545 // By default, turn this into a target intrinsic node.
4546 visitTargetIntrinsic(I, Intrinsic);
4548 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4549 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4550 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4551 case Intrinsic::returnaddress:
4552 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI.getPointerTy(),
4553 getValue(I.getArgOperand(0))));
4555 case Intrinsic::frameaddress:
4556 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4557 getValue(I.getArgOperand(0))));
4559 case Intrinsic::read_register: {
4560 Value *Reg = I.getArgOperand(0);
4562 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4563 EVT VT = TLI.getValueType(I.getType());
4564 setValue(&I, DAG.getNode(ISD::READ_REGISTER, sdl, VT, RegName));
4567 case Intrinsic::write_register: {
4568 Value *Reg = I.getArgOperand(0);
4569 Value *RegValue = I.getArgOperand(1);
4570 SDValue Chain = getValue(RegValue).getOperand(0);
4572 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4573 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4574 RegName, getValue(RegValue)));
4577 case Intrinsic::setjmp:
4578 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4579 case Intrinsic::longjmp:
4580 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4581 case Intrinsic::memcpy: {
4582 // FIXME: this definition of "user defined address space" is x86-specific
4583 // Assert for address < 256 since we support only user defined address
4585 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4587 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4589 "Unknown address space");
4590 SDValue Op1 = getValue(I.getArgOperand(0));
4591 SDValue Op2 = getValue(I.getArgOperand(1));
4592 SDValue Op3 = getValue(I.getArgOperand(2));
4593 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4595 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4596 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4597 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4598 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4600 MachinePointerInfo(I.getArgOperand(0)),
4601 MachinePointerInfo(I.getArgOperand(1)));
4602 updateDAGForMaybeTailCall(MC);
4605 case Intrinsic::memset: {
4606 // FIXME: this definition of "user defined address space" is x86-specific
4607 // Assert for address < 256 since we support only user defined address
4609 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4611 "Unknown address space");
4612 SDValue Op1 = getValue(I.getArgOperand(0));
4613 SDValue Op2 = getValue(I.getArgOperand(1));
4614 SDValue Op3 = getValue(I.getArgOperand(2));
4615 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4617 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4618 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4619 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4620 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4621 isTC, MachinePointerInfo(I.getArgOperand(0)));
4622 updateDAGForMaybeTailCall(MS);
4625 case Intrinsic::memmove: {
4626 // FIXME: this definition of "user defined address space" is x86-specific
4627 // Assert for address < 256 since we support only user defined address
4629 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4631 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4633 "Unknown address space");
4634 SDValue Op1 = getValue(I.getArgOperand(0));
4635 SDValue Op2 = getValue(I.getArgOperand(1));
4636 SDValue Op3 = getValue(I.getArgOperand(2));
4637 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4639 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4640 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4641 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4642 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4643 isTC, MachinePointerInfo(I.getArgOperand(0)),
4644 MachinePointerInfo(I.getArgOperand(1)));
4645 updateDAGForMaybeTailCall(MM);
4648 case Intrinsic::dbg_declare: {
4649 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4650 MDLocalVariable *Variable = DI.getVariable();
4651 MDExpression *Expression = DI.getExpression();
4652 const Value *Address = DI.getAddress();
4653 DIVariable DIVar = Variable;
4654 if (!Address || !DIVar) {
4655 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4659 // Check if address has undef value.
4660 if (isa<UndefValue>(Address) ||
4661 (Address->use_empty() && !isa<Argument>(Address))) {
4662 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4666 SDValue &N = NodeMap[Address];
4667 if (!N.getNode() && isa<Argument>(Address))
4668 // Check unused arguments map.
4669 N = UnusedArgNodeMap[Address];
4672 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4673 Address = BCI->getOperand(0);
4674 // Parameters are handled specially.
4676 (DIVariable(Variable)->getTag() == dwarf::DW_TAG_arg_variable ||
4677 isa<Argument>(Address));
4679 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4681 if (isParameter && !AI) {
4682 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4684 // Byval parameter. We have a frame index at this point.
4685 SDV = DAG.getFrameIndexDbgValue(
4686 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4688 // Address is an argument, so try to emit its dbg value using
4689 // virtual register info from the FuncInfo.ValueMap.
4690 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4695 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4696 true, 0, dl, SDNodeOrder);
4698 // Can't do anything with other non-AI cases yet.
4699 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4700 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4701 DEBUG(Address->dump());
4704 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4706 // If Address is an argument then try to emit its dbg value using
4707 // virtual register info from the FuncInfo.ValueMap.
4708 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4710 // If variable is pinned by a alloca in dominating bb then
4711 // use StaticAllocaMap.
4712 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4713 if (AI->getParent() != DI.getParent()) {
4714 DenseMap<const AllocaInst*, int>::iterator SI =
4715 FuncInfo.StaticAllocaMap.find(AI);
4716 if (SI != FuncInfo.StaticAllocaMap.end()) {
4717 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4718 0, dl, SDNodeOrder);
4719 DAG.AddDbgValue(SDV, nullptr, false);
4724 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4729 case Intrinsic::dbg_value: {
4730 const DbgValueInst &DI = cast<DbgValueInst>(I);
4731 DIVariable DIVar = DI.getVariable();
4735 MDLocalVariable *Variable = DI.getVariable();
4736 MDExpression *Expression = DI.getExpression();
4737 uint64_t Offset = DI.getOffset();
4738 const Value *V = DI.getValue();
4743 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4744 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4746 DAG.AddDbgValue(SDV, nullptr, false);
4748 // Do not use getValue() in here; we don't want to generate code at
4749 // this point if it hasn't been done yet.
4750 SDValue N = NodeMap[V];
4751 if (!N.getNode() && isa<Argument>(V))
4752 // Check unused arguments map.
4753 N = UnusedArgNodeMap[V];
4755 // A dbg.value for an alloca is always indirect.
4756 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4757 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4759 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4760 IsIndirect, Offset, dl, SDNodeOrder);
4761 DAG.AddDbgValue(SDV, N.getNode(), false);
4763 } else if (!V->use_empty() ) {
4764 // Do not call getValue(V) yet, as we don't want to generate code.
4765 // Remember it for later.
4766 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4767 DanglingDebugInfoMap[V] = DDI;
4769 // We may expand this to cover more cases. One case where we have no
4770 // data available is an unreferenced parameter.
4771 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4775 // Build a debug info table entry.
4776 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4777 V = BCI->getOperand(0);
4778 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4779 // Don't handle byval struct arguments or VLAs, for example.
4781 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4782 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4785 DenseMap<const AllocaInst*, int>::iterator SI =
4786 FuncInfo.StaticAllocaMap.find(AI);
4787 if (SI == FuncInfo.StaticAllocaMap.end())
4788 return nullptr; // VLAs.
4792 case Intrinsic::eh_typeid_for: {
4793 // Find the type id for the given typeinfo.
4794 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4795 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4796 Res = DAG.getConstant(TypeID, MVT::i32);
4801 case Intrinsic::eh_return_i32:
4802 case Intrinsic::eh_return_i64:
4803 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4804 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4807 getValue(I.getArgOperand(0)),
4808 getValue(I.getArgOperand(1))));
4810 case Intrinsic::eh_unwind_init:
4811 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4813 case Intrinsic::eh_dwarf_cfa: {
4814 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4815 TLI.getPointerTy());
4816 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4817 CfaArg.getValueType(),
4818 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4819 CfaArg.getValueType()),
4821 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl, TLI.getPointerTy(),
4822 DAG.getConstant(0, TLI.getPointerTy()));
4823 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4827 case Intrinsic::eh_sjlj_callsite: {
4828 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4829 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4830 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4831 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4833 MMI.setCurrentCallSite(CI->getZExtValue());
4836 case Intrinsic::eh_sjlj_functioncontext: {
4837 // Get and store the index of the function context.
4838 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4840 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4841 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4842 MFI->setFunctionContextIndex(FI);
4845 case Intrinsic::eh_sjlj_setjmp: {
4848 Ops[1] = getValue(I.getArgOperand(0));
4849 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4850 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4851 setValue(&I, Op.getValue(0));
4852 DAG.setRoot(Op.getValue(1));
4855 case Intrinsic::eh_sjlj_longjmp: {
4856 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4857 getRoot(), getValue(I.getArgOperand(0))));
4861 case Intrinsic::masked_load:
4864 case Intrinsic::masked_store:
4865 visitMaskedStore(I);
4867 case Intrinsic::x86_mmx_pslli_w:
4868 case Intrinsic::x86_mmx_pslli_d:
4869 case Intrinsic::x86_mmx_pslli_q:
4870 case Intrinsic::x86_mmx_psrli_w:
4871 case Intrinsic::x86_mmx_psrli_d:
4872 case Intrinsic::x86_mmx_psrli_q:
4873 case Intrinsic::x86_mmx_psrai_w:
4874 case Intrinsic::x86_mmx_psrai_d: {
4875 SDValue ShAmt = getValue(I.getArgOperand(1));
4876 if (isa<ConstantSDNode>(ShAmt)) {
4877 visitTargetIntrinsic(I, Intrinsic);
4880 unsigned NewIntrinsic = 0;
4881 EVT ShAmtVT = MVT::v2i32;
4882 switch (Intrinsic) {
4883 case Intrinsic::x86_mmx_pslli_w:
4884 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4886 case Intrinsic::x86_mmx_pslli_d:
4887 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4889 case Intrinsic::x86_mmx_pslli_q:
4890 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4892 case Intrinsic::x86_mmx_psrli_w:
4893 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4895 case Intrinsic::x86_mmx_psrli_d:
4896 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4898 case Intrinsic::x86_mmx_psrli_q:
4899 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4901 case Intrinsic::x86_mmx_psrai_w:
4902 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4904 case Intrinsic::x86_mmx_psrai_d:
4905 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4907 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4910 // The vector shift intrinsics with scalars uses 32b shift amounts but
4911 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4913 // We must do this early because v2i32 is not a legal type.
4916 ShOps[1] = DAG.getConstant(0, MVT::i32);
4917 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4918 EVT DestVT = TLI.getValueType(I.getType());
4919 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4920 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4921 DAG.getConstant(NewIntrinsic, MVT::i32),
4922 getValue(I.getArgOperand(0)), ShAmt);
4926 case Intrinsic::convertff:
4927 case Intrinsic::convertfsi:
4928 case Intrinsic::convertfui:
4929 case Intrinsic::convertsif:
4930 case Intrinsic::convertuif:
4931 case Intrinsic::convertss:
4932 case Intrinsic::convertsu:
4933 case Intrinsic::convertus:
4934 case Intrinsic::convertuu: {
4935 ISD::CvtCode Code = ISD::CVT_INVALID;
4936 switch (Intrinsic) {
4937 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4938 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4939 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4940 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4941 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4942 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4943 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4944 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4945 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4946 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4948 EVT DestVT = TLI.getValueType(I.getType());
4949 const Value *Op1 = I.getArgOperand(0);
4950 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4951 DAG.getValueType(DestVT),
4952 DAG.getValueType(getValue(Op1).getValueType()),
4953 getValue(I.getArgOperand(1)),
4954 getValue(I.getArgOperand(2)),
4959 case Intrinsic::powi:
4960 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4961 getValue(I.getArgOperand(1)), DAG));
4963 case Intrinsic::log:
4964 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4966 case Intrinsic::log2:
4967 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4969 case Intrinsic::log10:
4970 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4972 case Intrinsic::exp:
4973 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4975 case Intrinsic::exp2:
4976 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4978 case Intrinsic::pow:
4979 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4980 getValue(I.getArgOperand(1)), DAG, TLI));
4982 case Intrinsic::sqrt:
4983 case Intrinsic::fabs:
4984 case Intrinsic::sin:
4985 case Intrinsic::cos:
4986 case Intrinsic::floor:
4987 case Intrinsic::ceil:
4988 case Intrinsic::trunc:
4989 case Intrinsic::rint:
4990 case Intrinsic::nearbyint:
4991 case Intrinsic::round: {
4993 switch (Intrinsic) {
4994 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4995 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4996 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4997 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4998 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4999 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5000 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5001 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5002 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5003 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5004 case Intrinsic::round: Opcode = ISD::FROUND; break;
5007 setValue(&I, DAG.getNode(Opcode, sdl,
5008 getValue(I.getArgOperand(0)).getValueType(),
5009 getValue(I.getArgOperand(0))));
5012 case Intrinsic::minnum:
5013 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
5014 getValue(I.getArgOperand(0)).getValueType(),
5015 getValue(I.getArgOperand(0)),
5016 getValue(I.getArgOperand(1))));
5018 case Intrinsic::maxnum:
5019 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
5020 getValue(I.getArgOperand(0)).getValueType(),
5021 getValue(I.getArgOperand(0)),
5022 getValue(I.getArgOperand(1))));
5024 case Intrinsic::copysign:
5025 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5026 getValue(I.getArgOperand(0)).getValueType(),
5027 getValue(I.getArgOperand(0)),
5028 getValue(I.getArgOperand(1))));
5030 case Intrinsic::fma:
5031 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5032 getValue(I.getArgOperand(0)).getValueType(),
5033 getValue(I.getArgOperand(0)),
5034 getValue(I.getArgOperand(1)),
5035 getValue(I.getArgOperand(2))));
5037 case Intrinsic::fmuladd: {
5038 EVT VT = TLI.getValueType(I.getType());
5039 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5040 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
5041 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5042 getValue(I.getArgOperand(0)).getValueType(),
5043 getValue(I.getArgOperand(0)),
5044 getValue(I.getArgOperand(1)),
5045 getValue(I.getArgOperand(2))));
5047 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5048 getValue(I.getArgOperand(0)).getValueType(),
5049 getValue(I.getArgOperand(0)),
5050 getValue(I.getArgOperand(1)));
5051 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5052 getValue(I.getArgOperand(0)).getValueType(),
5054 getValue(I.getArgOperand(2)));
5059 case Intrinsic::convert_to_fp16:
5060 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
5061 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
5062 getValue(I.getArgOperand(0)),
5063 DAG.getTargetConstant(0, MVT::i32))));
5065 case Intrinsic::convert_from_fp16:
5067 DAG.getNode(ISD::FP_EXTEND, sdl, TLI.getValueType(I.getType()),
5068 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
5069 getValue(I.getArgOperand(0)))));
5071 case Intrinsic::pcmarker: {
5072 SDValue Tmp = getValue(I.getArgOperand(0));
5073 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5076 case Intrinsic::readcyclecounter: {
5077 SDValue Op = getRoot();
5078 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5079 DAG.getVTList(MVT::i64, MVT::Other), Op);
5081 DAG.setRoot(Res.getValue(1));
5084 case Intrinsic::bswap:
5085 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5086 getValue(I.getArgOperand(0)).getValueType(),
5087 getValue(I.getArgOperand(0))));
5089 case Intrinsic::cttz: {
5090 SDValue Arg = getValue(I.getArgOperand(0));
5091 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5092 EVT Ty = Arg.getValueType();
5093 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5097 case Intrinsic::ctlz: {
5098 SDValue Arg = getValue(I.getArgOperand(0));
5099 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5100 EVT Ty = Arg.getValueType();
5101 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5105 case Intrinsic::ctpop: {
5106 SDValue Arg = getValue(I.getArgOperand(0));
5107 EVT Ty = Arg.getValueType();
5108 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5111 case Intrinsic::stacksave: {
5112 SDValue Op = getRoot();
5113 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5114 DAG.getVTList(TLI.getPointerTy(), MVT::Other), Op);
5116 DAG.setRoot(Res.getValue(1));
5119 case Intrinsic::stackrestore: {
5120 Res = getValue(I.getArgOperand(0));
5121 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5124 case Intrinsic::stackprotector: {
5125 // Emit code into the DAG to store the stack guard onto the stack.
5126 MachineFunction &MF = DAG.getMachineFunction();
5127 MachineFrameInfo *MFI = MF.getFrameInfo();
5128 EVT PtrTy = TLI.getPointerTy();
5129 SDValue Src, Chain = getRoot();
5130 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
5131 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
5133 // See if Ptr is a bitcast. If it is, look through it and see if we can get
5134 // global variable __stack_chk_guard.
5136 if (const Operator *BC = dyn_cast<Operator>(Ptr))
5137 if (BC->getOpcode() == Instruction::BitCast)
5138 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
5140 if (GV && TLI.useLoadStackGuardNode()) {
5141 // Emit a LOAD_STACK_GUARD node.
5142 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
5144 MachinePointerInfo MPInfo(GV);
5145 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
5146 unsigned Flags = MachineMemOperand::MOLoad |
5147 MachineMemOperand::MOInvariant;
5148 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
5149 PtrTy.getSizeInBits() / 8,
5150 DAG.getEVTAlignment(PtrTy));
5151 Node->setMemRefs(MemRefs, MemRefs + 1);
5153 // Copy the guard value to a virtual register so that it can be
5154 // retrieved in the epilogue.
5155 Src = SDValue(Node, 0);
5156 const TargetRegisterClass *RC =
5157 TLI.getRegClassFor(Src.getSimpleValueType());
5158 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
5160 SPDescriptor.setGuardReg(Reg);
5161 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
5163 Src = getValue(I.getArgOperand(0)); // The guard's value.
5166 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5168 int FI = FuncInfo.StaticAllocaMap[Slot];
5169 MFI->setStackProtectorIndex(FI);
5171 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5173 // Store the stack protector onto the stack.
5174 Res = DAG.getStore(Chain, sdl, Src, FIN,
5175 MachinePointerInfo::getFixedStack(FI),
5181 case Intrinsic::objectsize: {
5182 // If we don't know by now, we're never going to know.
5183 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5185 assert(CI && "Non-constant type in __builtin_object_size?");
5187 SDValue Arg = getValue(I.getCalledValue());
5188 EVT Ty = Arg.getValueType();
5191 Res = DAG.getConstant(-1ULL, Ty);
5193 Res = DAG.getConstant(0, Ty);
5198 case Intrinsic::annotation:
5199 case Intrinsic::ptr_annotation:
5200 // Drop the intrinsic, but forward the value
5201 setValue(&I, getValue(I.getOperand(0)));
5203 case Intrinsic::assume:
5204 case Intrinsic::var_annotation:
5205 // Discard annotate attributes and assumptions
5208 case Intrinsic::init_trampoline: {
5209 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5213 Ops[1] = getValue(I.getArgOperand(0));
5214 Ops[2] = getValue(I.getArgOperand(1));
5215 Ops[3] = getValue(I.getArgOperand(2));
5216 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5217 Ops[5] = DAG.getSrcValue(F);
5219 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5224 case Intrinsic::adjust_trampoline: {
5225 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5227 getValue(I.getArgOperand(0))));
5230 case Intrinsic::gcroot:
5232 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5233 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5235 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5236 GFI->addStackRoot(FI->getIndex(), TypeMap);
5239 case Intrinsic::gcread:
5240 case Intrinsic::gcwrite:
5241 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5242 case Intrinsic::flt_rounds:
5243 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5246 case Intrinsic::expect: {
5247 // Just replace __builtin_expect(exp, c) with EXP.
5248 setValue(&I, getValue(I.getArgOperand(0)));
5252 case Intrinsic::debugtrap:
5253 case Intrinsic::trap: {
5254 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5255 if (TrapFuncName.empty()) {
5256 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5257 ISD::TRAP : ISD::DEBUGTRAP;
5258 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5261 TargetLowering::ArgListTy Args;
5263 TargetLowering::CallLoweringInfo CLI(DAG);
5264 CLI.setDebugLoc(sdl).setChain(getRoot())
5265 .setCallee(CallingConv::C, I.getType(),
5266 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5267 std::move(Args), 0);
5269 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5270 DAG.setRoot(Result.second);
5274 case Intrinsic::uadd_with_overflow:
5275 case Intrinsic::sadd_with_overflow:
5276 case Intrinsic::usub_with_overflow:
5277 case Intrinsic::ssub_with_overflow:
5278 case Intrinsic::umul_with_overflow:
5279 case Intrinsic::smul_with_overflow: {
5281 switch (Intrinsic) {
5282 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5283 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5284 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5285 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5286 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5287 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5288 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5290 SDValue Op1 = getValue(I.getArgOperand(0));
5291 SDValue Op2 = getValue(I.getArgOperand(1));
5293 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5294 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5297 case Intrinsic::prefetch: {
5299 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5301 Ops[1] = getValue(I.getArgOperand(0));
5302 Ops[2] = getValue(I.getArgOperand(1));
5303 Ops[3] = getValue(I.getArgOperand(2));
5304 Ops[4] = getValue(I.getArgOperand(3));
5305 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5306 DAG.getVTList(MVT::Other), Ops,
5307 EVT::getIntegerVT(*Context, 8),
5308 MachinePointerInfo(I.getArgOperand(0)),
5310 false, /* volatile */
5312 rw==1)); /* write */
5315 case Intrinsic::lifetime_start:
5316 case Intrinsic::lifetime_end: {
5317 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5318 // Stack coloring is not enabled in O0, discard region information.
5319 if (TM.getOptLevel() == CodeGenOpt::None)
5322 SmallVector<Value *, 4> Allocas;
5323 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5325 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5326 E = Allocas.end(); Object != E; ++Object) {
5327 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5329 // Could not find an Alloca.
5330 if (!LifetimeObject)
5333 // First check that the Alloca is static, otherwise it won't have a
5334 // valid frame index.
5335 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5336 if (SI == FuncInfo.StaticAllocaMap.end())
5339 int FI = SI->second;
5343 Ops[1] = DAG.getFrameIndex(FI, TLI.getPointerTy(), true);
5344 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5346 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5351 case Intrinsic::invariant_start:
5352 // Discard region information.
5353 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5355 case Intrinsic::invariant_end:
5356 // Discard region information.
5358 case Intrinsic::stackprotectorcheck: {
5359 // Do not actually emit anything for this basic block. Instead we initialize
5360 // the stack protector descriptor and export the guard variable so we can
5361 // access it in FinishBasicBlock.
5362 const BasicBlock *BB = I.getParent();
5363 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5364 ExportFromCurrentBlock(SPDescriptor.getGuard());
5366 // Flush our exports since we are going to process a terminator.
5367 (void)getControlRoot();
5370 case Intrinsic::clear_cache:
5371 return TLI.getClearCacheBuiltinName();
5372 case Intrinsic::eh_actions:
5373 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5375 case Intrinsic::donothing:
5378 case Intrinsic::experimental_stackmap: {
5382 case Intrinsic::experimental_patchpoint_void:
5383 case Intrinsic::experimental_patchpoint_i64: {
5384 visitPatchpoint(&I);
5387 case Intrinsic::experimental_gc_statepoint: {
5391 case Intrinsic::experimental_gc_result_int:
5392 case Intrinsic::experimental_gc_result_float:
5393 case Intrinsic::experimental_gc_result_ptr:
5394 case Intrinsic::experimental_gc_result: {
5398 case Intrinsic::experimental_gc_relocate: {
5402 case Intrinsic::instrprof_increment:
5403 llvm_unreachable("instrprof failed to lower an increment");
5405 case Intrinsic::frameescape: {
5406 MachineFunction &MF = DAG.getMachineFunction();
5407 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5409 // Directly emit some FRAME_ALLOC machine instrs. Label assignment emission
5410 // is the same on all targets.
5411 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5412 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5413 if (isa<ConstantPointerNull>(Arg))
5414 continue; // Skip null pointers. They represent a hole in index space.
5415 AllocaInst *Slot = cast<AllocaInst>(Arg);
5416 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5417 "can only escape static allocas");
5418 int FI = FuncInfo.StaticAllocaMap[Slot];
5419 MCSymbol *FrameAllocSym =
5420 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5421 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5422 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5423 TII->get(TargetOpcode::FRAME_ALLOC))
5424 .addSym(FrameAllocSym)
5431 case Intrinsic::framerecover: {
5432 // i8* @llvm.framerecover(i8* %fn, i8* %fp, i32 %idx)
5433 MachineFunction &MF = DAG.getMachineFunction();
5434 MVT PtrVT = TLI.getPointerTy(0);
5436 // Get the symbol that defines the frame offset.
5437 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5438 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5439 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5440 MCSymbol *FrameAllocSym =
5441 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5442 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5444 // Create a TargetExternalSymbol for the label to avoid any target lowering
5445 // that would make this PC relative.
5446 StringRef Name = FrameAllocSym->getName();
5447 assert(Name.data()[Name.size()] == '\0' && "not null terminated");
5448 SDValue OffsetSym = DAG.getTargetExternalSymbol(Name.data(), PtrVT);
5450 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, sdl, PtrVT, OffsetSym);
5452 // Add the offset to the FP.
5453 Value *FP = I.getArgOperand(1);
5454 SDValue FPVal = getValue(FP);
5455 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5460 case Intrinsic::eh_begincatch:
5461 case Intrinsic::eh_endcatch:
5462 llvm_unreachable("begin/end catch intrinsics not lowered in codegen");
5466 std::pair<SDValue, SDValue>
5467 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5468 MachineBasicBlock *LandingPad) {
5469 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5470 MCSymbol *BeginLabel = nullptr;
5473 // Insert a label before the invoke call to mark the try range. This can be
5474 // used to detect deletion of the invoke via the MachineModuleInfo.
5475 BeginLabel = MMI.getContext().CreateTempSymbol();
5477 // For SjLj, keep track of which landing pads go with which invokes
5478 // so as to maintain the ordering of pads in the LSDA.
5479 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5480 if (CallSiteIndex) {
5481 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5482 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5484 // Now that the call site is handled, stop tracking it.
5485 MMI.setCurrentCallSite(0);
5488 // Both PendingLoads and PendingExports must be flushed here;
5489 // this call might not return.
5491 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5493 CLI.setChain(getRoot());
5495 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5496 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5498 assert((CLI.IsTailCall || Result.second.getNode()) &&
5499 "Non-null chain expected with non-tail call!");
5500 assert((Result.second.getNode() || !Result.first.getNode()) &&
5501 "Null value expected with tail call!");
5503 if (!Result.second.getNode()) {
5504 // As a special case, a null chain means that a tail call has been emitted
5505 // and the DAG root is already updated.
5508 // Since there's no actual continuation from this block, nothing can be
5509 // relying on us setting vregs for them.
5510 PendingExports.clear();
5512 DAG.setRoot(Result.second);
5516 // Insert a label at the end of the invoke call to mark the try range. This
5517 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5518 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5519 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5521 // Inform MachineModuleInfo of range.
5522 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5528 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5530 MachineBasicBlock *LandingPad) {
5531 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5532 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5533 Type *RetTy = FTy->getReturnType();
5535 TargetLowering::ArgListTy Args;
5536 TargetLowering::ArgListEntry Entry;
5537 Args.reserve(CS.arg_size());
5539 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5541 const Value *V = *i;
5544 if (V->getType()->isEmptyTy())
5547 SDValue ArgNode = getValue(V);
5548 Entry.Node = ArgNode; Entry.Ty = V->getType();
5550 // Skip the first return-type Attribute to get to params.
5551 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5552 Args.push_back(Entry);
5554 // If we have an explicit sret argument that is an Instruction, (i.e., it
5555 // might point to function-local memory), we can't meaningfully tail-call.
5556 if (Entry.isSRet && isa<Instruction>(V))
5560 // Check if target-independent constraints permit a tail call here.
5561 // Target-dependent constraints are checked within TLI->LowerCallTo.
5562 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5565 TargetLowering::CallLoweringInfo CLI(DAG);
5566 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5567 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5568 .setTailCall(isTailCall);
5569 std::pair<SDValue,SDValue> Result = lowerInvokable(CLI, LandingPad);
5571 if (Result.first.getNode())
5572 setValue(CS.getInstruction(), Result.first);
5575 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5576 /// value is equal or not-equal to zero.
5577 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5578 for (const User *U : V->users()) {
5579 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5580 if (IC->isEquality())
5581 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5582 if (C->isNullValue())
5584 // Unknown instruction.
5590 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5592 SelectionDAGBuilder &Builder) {
5594 // Check to see if this load can be trivially constant folded, e.g. if the
5595 // input is from a string literal.
5596 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5597 // Cast pointer to the type we really want to load.
5598 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5599 PointerType::getUnqual(LoadTy));
5601 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5602 const_cast<Constant *>(LoadInput), *Builder.DL))
5603 return Builder.getValue(LoadCst);
5606 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5607 // still constant memory, the input chain can be the entry node.
5609 bool ConstantMemory = false;
5611 // Do not serialize (non-volatile) loads of constant memory with anything.
5612 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5613 Root = Builder.DAG.getEntryNode();
5614 ConstantMemory = true;
5616 // Do not serialize non-volatile loads against each other.
5617 Root = Builder.DAG.getRoot();
5620 SDValue Ptr = Builder.getValue(PtrVal);
5621 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5622 Ptr, MachinePointerInfo(PtrVal),
5624 false /*nontemporal*/,
5625 false /*isinvariant*/, 1 /* align=1 */);
5627 if (!ConstantMemory)
5628 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5632 /// processIntegerCallValue - Record the value for an instruction that
5633 /// produces an integer result, converting the type where necessary.
5634 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5637 EVT VT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5639 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5641 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5642 setValue(&I, Value);
5645 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5646 /// If so, return true and lower it, otherwise return false and it will be
5647 /// lowered like a normal call.
5648 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5649 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5650 if (I.getNumArgOperands() != 3)
5653 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5654 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5655 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5656 !I.getType()->isIntegerTy())
5659 const Value *Size = I.getArgOperand(2);
5660 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5661 if (CSize && CSize->getZExtValue() == 0) {
5662 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(I.getType(), true);
5663 setValue(&I, DAG.getConstant(0, CallVT));
5667 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5668 std::pair<SDValue, SDValue> Res =
5669 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5670 getValue(LHS), getValue(RHS), getValue(Size),
5671 MachinePointerInfo(LHS),
5672 MachinePointerInfo(RHS));
5673 if (Res.first.getNode()) {
5674 processIntegerCallValue(I, Res.first, true);
5675 PendingLoads.push_back(Res.second);
5679 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5680 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5681 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5682 bool ActuallyDoIt = true;
5685 switch (CSize->getZExtValue()) {
5687 LoadVT = MVT::Other;
5689 ActuallyDoIt = false;
5693 LoadTy = Type::getInt16Ty(CSize->getContext());
5697 LoadTy = Type::getInt32Ty(CSize->getContext());
5701 LoadTy = Type::getInt64Ty(CSize->getContext());
5705 LoadVT = MVT::v4i32;
5706 LoadTy = Type::getInt32Ty(CSize->getContext());
5707 LoadTy = VectorType::get(LoadTy, 4);
5712 // This turns into unaligned loads. We only do this if the target natively
5713 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5714 // we'll only produce a small number of byte loads.
5716 // Require that we can find a legal MVT, and only do this if the target
5717 // supports unaligned loads of that type. Expanding into byte loads would
5719 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5720 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5721 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5722 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5723 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5724 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5725 // TODO: Check alignment of src and dest ptrs.
5726 if (!TLI.isTypeLegal(LoadVT) ||
5727 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5728 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5729 ActuallyDoIt = false;
5733 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5734 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5736 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5738 processIntegerCallValue(I, Res, false);
5747 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5748 /// form. If so, return true and lower it, otherwise return false and it
5749 /// will be lowered like a normal call.
5750 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5751 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5752 if (I.getNumArgOperands() != 3)
5755 const Value *Src = I.getArgOperand(0);
5756 const Value *Char = I.getArgOperand(1);
5757 const Value *Length = I.getArgOperand(2);
5758 if (!Src->getType()->isPointerTy() ||
5759 !Char->getType()->isIntegerTy() ||
5760 !Length->getType()->isIntegerTy() ||
5761 !I.getType()->isPointerTy())
5764 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5765 std::pair<SDValue, SDValue> Res =
5766 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5767 getValue(Src), getValue(Char), getValue(Length),
5768 MachinePointerInfo(Src));
5769 if (Res.first.getNode()) {
5770 setValue(&I, Res.first);
5771 PendingLoads.push_back(Res.second);
5778 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5779 /// optimized form. If so, return true and lower it, otherwise return false
5780 /// and it will be lowered like a normal call.
5781 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5782 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5783 if (I.getNumArgOperands() != 2)
5786 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5787 if (!Arg0->getType()->isPointerTy() ||
5788 !Arg1->getType()->isPointerTy() ||
5789 !I.getType()->isPointerTy())
5792 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5793 std::pair<SDValue, SDValue> Res =
5794 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5795 getValue(Arg0), getValue(Arg1),
5796 MachinePointerInfo(Arg0),
5797 MachinePointerInfo(Arg1), isStpcpy);
5798 if (Res.first.getNode()) {
5799 setValue(&I, Res.first);
5800 DAG.setRoot(Res.second);
5807 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5808 /// If so, return true and lower it, otherwise return false and it will be
5809 /// lowered like a normal call.
5810 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5811 // Verify that the prototype makes sense. int strcmp(void*,void*)
5812 if (I.getNumArgOperands() != 2)
5815 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5816 if (!Arg0->getType()->isPointerTy() ||
5817 !Arg1->getType()->isPointerTy() ||
5818 !I.getType()->isIntegerTy())
5821 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5822 std::pair<SDValue, SDValue> Res =
5823 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5824 getValue(Arg0), getValue(Arg1),
5825 MachinePointerInfo(Arg0),
5826 MachinePointerInfo(Arg1));
5827 if (Res.first.getNode()) {
5828 processIntegerCallValue(I, Res.first, true);
5829 PendingLoads.push_back(Res.second);
5836 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5837 /// form. If so, return true and lower it, otherwise return false and it
5838 /// will be lowered like a normal call.
5839 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5840 // Verify that the prototype makes sense. size_t strlen(char *)
5841 if (I.getNumArgOperands() != 1)
5844 const Value *Arg0 = I.getArgOperand(0);
5845 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5848 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5849 std::pair<SDValue, SDValue> Res =
5850 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5851 getValue(Arg0), MachinePointerInfo(Arg0));
5852 if (Res.first.getNode()) {
5853 processIntegerCallValue(I, Res.first, false);
5854 PendingLoads.push_back(Res.second);
5861 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5862 /// form. If so, return true and lower it, otherwise return false and it
5863 /// will be lowered like a normal call.
5864 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5865 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5866 if (I.getNumArgOperands() != 2)
5869 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5870 if (!Arg0->getType()->isPointerTy() ||
5871 !Arg1->getType()->isIntegerTy() ||
5872 !I.getType()->isIntegerTy())
5875 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5876 std::pair<SDValue, SDValue> Res =
5877 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5878 getValue(Arg0), getValue(Arg1),
5879 MachinePointerInfo(Arg0));
5880 if (Res.first.getNode()) {
5881 processIntegerCallValue(I, Res.first, false);
5882 PendingLoads.push_back(Res.second);
5889 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5890 /// operation (as expected), translate it to an SDNode with the specified opcode
5891 /// and return true.
5892 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5894 // Sanity check that it really is a unary floating-point call.
5895 if (I.getNumArgOperands() != 1 ||
5896 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5897 I.getType() != I.getArgOperand(0)->getType() ||
5898 !I.onlyReadsMemory())
5901 SDValue Tmp = getValue(I.getArgOperand(0));
5902 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5906 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5907 /// operation (as expected), translate it to an SDNode with the specified opcode
5908 /// and return true.
5909 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5911 // Sanity check that it really is a binary floating-point call.
5912 if (I.getNumArgOperands() != 2 ||
5913 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5914 I.getType() != I.getArgOperand(0)->getType() ||
5915 I.getType() != I.getArgOperand(1)->getType() ||
5916 !I.onlyReadsMemory())
5919 SDValue Tmp0 = getValue(I.getArgOperand(0));
5920 SDValue Tmp1 = getValue(I.getArgOperand(1));
5921 EVT VT = Tmp0.getValueType();
5922 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5926 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5927 // Handle inline assembly differently.
5928 if (isa<InlineAsm>(I.getCalledValue())) {
5933 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5934 ComputeUsesVAFloatArgument(I, &MMI);
5936 const char *RenameFn = nullptr;
5937 if (Function *F = I.getCalledFunction()) {
5938 if (F->isDeclaration()) {
5939 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5940 if (unsigned IID = II->getIntrinsicID(F)) {
5941 RenameFn = visitIntrinsicCall(I, IID);
5946 if (unsigned IID = F->getIntrinsicID()) {
5947 RenameFn = visitIntrinsicCall(I, IID);
5953 // Check for well-known libc/libm calls. If the function is internal, it
5954 // can't be a library call.
5956 if (!F->hasLocalLinkage() && F->hasName() &&
5957 LibInfo->getLibFunc(F->getName(), Func) &&
5958 LibInfo->hasOptimizedCodeGen(Func)) {
5961 case LibFunc::copysign:
5962 case LibFunc::copysignf:
5963 case LibFunc::copysignl:
5964 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5965 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5966 I.getType() == I.getArgOperand(0)->getType() &&
5967 I.getType() == I.getArgOperand(1)->getType() &&
5968 I.onlyReadsMemory()) {
5969 SDValue LHS = getValue(I.getArgOperand(0));
5970 SDValue RHS = getValue(I.getArgOperand(1));
5971 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5972 LHS.getValueType(), LHS, RHS));
5977 case LibFunc::fabsf:
5978 case LibFunc::fabsl:
5979 if (visitUnaryFloatCall(I, ISD::FABS))
5983 case LibFunc::fminf:
5984 case LibFunc::fminl:
5985 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5989 case LibFunc::fmaxf:
5990 case LibFunc::fmaxl:
5991 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5997 if (visitUnaryFloatCall(I, ISD::FSIN))
6003 if (visitUnaryFloatCall(I, ISD::FCOS))
6007 case LibFunc::sqrtf:
6008 case LibFunc::sqrtl:
6009 case LibFunc::sqrt_finite:
6010 case LibFunc::sqrtf_finite:
6011 case LibFunc::sqrtl_finite:
6012 if (visitUnaryFloatCall(I, ISD::FSQRT))
6015 case LibFunc::floor:
6016 case LibFunc::floorf:
6017 case LibFunc::floorl:
6018 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6021 case LibFunc::nearbyint:
6022 case LibFunc::nearbyintf:
6023 case LibFunc::nearbyintl:
6024 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6028 case LibFunc::ceilf:
6029 case LibFunc::ceill:
6030 if (visitUnaryFloatCall(I, ISD::FCEIL))
6034 case LibFunc::rintf:
6035 case LibFunc::rintl:
6036 if (visitUnaryFloatCall(I, ISD::FRINT))
6039 case LibFunc::round:
6040 case LibFunc::roundf:
6041 case LibFunc::roundl:
6042 if (visitUnaryFloatCall(I, ISD::FROUND))
6045 case LibFunc::trunc:
6046 case LibFunc::truncf:
6047 case LibFunc::truncl:
6048 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6052 case LibFunc::log2f:
6053 case LibFunc::log2l:
6054 if (visitUnaryFloatCall(I, ISD::FLOG2))
6058 case LibFunc::exp2f:
6059 case LibFunc::exp2l:
6060 if (visitUnaryFloatCall(I, ISD::FEXP2))
6063 case LibFunc::memcmp:
6064 if (visitMemCmpCall(I))
6067 case LibFunc::memchr:
6068 if (visitMemChrCall(I))
6071 case LibFunc::strcpy:
6072 if (visitStrCpyCall(I, false))
6075 case LibFunc::stpcpy:
6076 if (visitStrCpyCall(I, true))
6079 case LibFunc::strcmp:
6080 if (visitStrCmpCall(I))
6083 case LibFunc::strlen:
6084 if (visitStrLenCall(I))
6087 case LibFunc::strnlen:
6088 if (visitStrNLenCall(I))
6097 Callee = getValue(I.getCalledValue());
6099 Callee = DAG.getExternalSymbol(RenameFn,
6100 DAG.getTargetLoweringInfo().getPointerTy());
6102 // Check if we can potentially perform a tail call. More detailed checking is
6103 // be done within LowerCallTo, after more information about the call is known.
6104 LowerCallTo(&I, Callee, I.isTailCall());
6109 /// AsmOperandInfo - This contains information for each constraint that we are
6111 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6113 /// CallOperand - If this is the result output operand or a clobber
6114 /// this is null, otherwise it is the incoming operand to the CallInst.
6115 /// This gets modified as the asm is processed.
6116 SDValue CallOperand;
6118 /// AssignedRegs - If this is a register or register class operand, this
6119 /// contains the set of register corresponding to the operand.
6120 RegsForValue AssignedRegs;
6122 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6123 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6126 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6127 /// corresponds to. If there is no Value* for this operand, it returns
6129 EVT getCallOperandValEVT(LLVMContext &Context,
6130 const TargetLowering &TLI,
6131 const DataLayout *DL) const {
6132 if (!CallOperandVal) return MVT::Other;
6134 if (isa<BasicBlock>(CallOperandVal))
6135 return TLI.getPointerTy();
6137 llvm::Type *OpTy = CallOperandVal->getType();
6139 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6140 // If this is an indirect operand, the operand is a pointer to the
6143 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6145 report_fatal_error("Indirect operand for inline asm not a pointer!");
6146 OpTy = PtrTy->getElementType();
6149 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6150 if (StructType *STy = dyn_cast<StructType>(OpTy))
6151 if (STy->getNumElements() == 1)
6152 OpTy = STy->getElementType(0);
6154 // If OpTy is not a single value, it may be a struct/union that we
6155 // can tile with integers.
6156 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6157 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6166 OpTy = IntegerType::get(Context, BitSize);
6171 return TLI.getValueType(OpTy, true);
6175 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6177 } // end anonymous namespace
6179 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6180 /// specified operand. We prefer to assign virtual registers, to allow the
6181 /// register allocator to handle the assignment process. However, if the asm
6182 /// uses features that we can't model on machineinstrs, we have SDISel do the
6183 /// allocation. This produces generally horrible, but correct, code.
6185 /// OpInfo describes the operand.
6187 static void GetRegistersForValue(SelectionDAG &DAG,
6188 const TargetLowering &TLI,
6190 SDISelAsmOperandInfo &OpInfo) {
6191 LLVMContext &Context = *DAG.getContext();
6193 MachineFunction &MF = DAG.getMachineFunction();
6194 SmallVector<unsigned, 4> Regs;
6196 // If this is a constraint for a single physreg, or a constraint for a
6197 // register class, find it.
6198 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6199 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6200 OpInfo.ConstraintCode,
6201 OpInfo.ConstraintVT);
6203 unsigned NumRegs = 1;
6204 if (OpInfo.ConstraintVT != MVT::Other) {
6205 // If this is a FP input in an integer register (or visa versa) insert a bit
6206 // cast of the input value. More generally, handle any case where the input
6207 // value disagrees with the register class we plan to stick this in.
6208 if (OpInfo.Type == InlineAsm::isInput &&
6209 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6210 // Try to convert to the first EVT that the reg class contains. If the
6211 // types are identical size, use a bitcast to convert (e.g. two differing
6213 MVT RegVT = *PhysReg.second->vt_begin();
6214 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6215 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6216 RegVT, OpInfo.CallOperand);
6217 OpInfo.ConstraintVT = RegVT;
6218 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6219 // If the input is a FP value and we want it in FP registers, do a
6220 // bitcast to the corresponding integer type. This turns an f64 value
6221 // into i64, which can be passed with two i32 values on a 32-bit
6223 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6224 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6225 RegVT, OpInfo.CallOperand);
6226 OpInfo.ConstraintVT = RegVT;
6230 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6234 EVT ValueVT = OpInfo.ConstraintVT;
6236 // If this is a constraint for a specific physical register, like {r17},
6238 if (unsigned AssignedReg = PhysReg.first) {
6239 const TargetRegisterClass *RC = PhysReg.second;
6240 if (OpInfo.ConstraintVT == MVT::Other)
6241 ValueVT = *RC->vt_begin();
6243 // Get the actual register value type. This is important, because the user
6244 // may have asked for (e.g.) the AX register in i32 type. We need to
6245 // remember that AX is actually i16 to get the right extension.
6246 RegVT = *RC->vt_begin();
6248 // This is a explicit reference to a physical register.
6249 Regs.push_back(AssignedReg);
6251 // If this is an expanded reference, add the rest of the regs to Regs.
6253 TargetRegisterClass::iterator I = RC->begin();
6254 for (; *I != AssignedReg; ++I)
6255 assert(I != RC->end() && "Didn't find reg!");
6257 // Already added the first reg.
6259 for (; NumRegs; --NumRegs, ++I) {
6260 assert(I != RC->end() && "Ran out of registers to allocate!");
6265 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6269 // Otherwise, if this was a reference to an LLVM register class, create vregs
6270 // for this reference.
6271 if (const TargetRegisterClass *RC = PhysReg.second) {
6272 RegVT = *RC->vt_begin();
6273 if (OpInfo.ConstraintVT == MVT::Other)
6276 // Create the appropriate number of virtual registers.
6277 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6278 for (; NumRegs; --NumRegs)
6279 Regs.push_back(RegInfo.createVirtualRegister(RC));
6281 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6285 // Otherwise, we couldn't allocate enough registers for this.
6288 /// visitInlineAsm - Handle a call to an InlineAsm object.
6290 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6291 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6293 /// ConstraintOperands - Information about all of the constraints.
6294 SDISelAsmOperandInfoVector ConstraintOperands;
6296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6297 TargetLowering::AsmOperandInfoVector TargetConstraints =
6298 TLI.ParseConstraints(DAG.getSubtarget().getRegisterInfo(), CS);
6300 bool hasMemory = false;
6302 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6303 unsigned ResNo = 0; // ResNo - The result number of the next output.
6304 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6305 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6306 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6308 MVT OpVT = MVT::Other;
6310 // Compute the value type for each operand.
6311 switch (OpInfo.Type) {
6312 case InlineAsm::isOutput:
6313 // Indirect outputs just consume an argument.
6314 if (OpInfo.isIndirect) {
6315 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6319 // The return value of the call is this value. As such, there is no
6320 // corresponding argument.
6321 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6322 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6323 OpVT = TLI.getSimpleValueType(STy->getElementType(ResNo));
6325 assert(ResNo == 0 && "Asm only has one result!");
6326 OpVT = TLI.getSimpleValueType(CS.getType());
6330 case InlineAsm::isInput:
6331 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6333 case InlineAsm::isClobber:
6338 // If this is an input or an indirect output, process the call argument.
6339 // BasicBlocks are labels, currently appearing only in asm's.
6340 if (OpInfo.CallOperandVal) {
6341 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6342 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6344 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6348 OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, DL).getSimpleVT();
6351 OpInfo.ConstraintVT = OpVT;
6353 // Indirect operand accesses access memory.
6354 if (OpInfo.isIndirect)
6357 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6358 TargetLowering::ConstraintType
6359 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6360 if (CType == TargetLowering::C_Memory) {
6368 SDValue Chain, Flag;
6370 // We won't need to flush pending loads if this asm doesn't touch
6371 // memory and is nonvolatile.
6372 if (hasMemory || IA->hasSideEffects())
6375 Chain = DAG.getRoot();
6377 // Second pass over the constraints: compute which constraint option to use
6378 // and assign registers to constraints that want a specific physreg.
6379 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6380 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6382 // If this is an output operand with a matching input operand, look up the
6383 // matching input. If their types mismatch, e.g. one is an integer, the
6384 // other is floating point, or their sizes are different, flag it as an
6386 if (OpInfo.hasMatchingInput()) {
6387 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6389 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6390 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6391 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6392 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6393 OpInfo.ConstraintVT);
6394 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6395 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6396 Input.ConstraintVT);
6397 if ((OpInfo.ConstraintVT.isInteger() !=
6398 Input.ConstraintVT.isInteger()) ||
6399 (MatchRC.second != InputRC.second)) {
6400 report_fatal_error("Unsupported asm: input constraint"
6401 " with a matching output constraint of"
6402 " incompatible type!");
6404 Input.ConstraintVT = OpInfo.ConstraintVT;
6408 // Compute the constraint code and ConstraintType to use.
6409 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6411 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6412 OpInfo.Type == InlineAsm::isClobber)
6415 // If this is a memory input, and if the operand is not indirect, do what we
6416 // need to to provide an address for the memory input.
6417 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6418 !OpInfo.isIndirect) {
6419 assert((OpInfo.isMultipleAlternative ||
6420 (OpInfo.Type == InlineAsm::isInput)) &&
6421 "Can only indirectify direct input operands!");
6423 // Memory operands really want the address of the value. If we don't have
6424 // an indirect input, put it in the constpool if we can, otherwise spill
6425 // it to a stack slot.
6426 // TODO: This isn't quite right. We need to handle these according to
6427 // the addressing mode that the constraint wants. Also, this may take
6428 // an additional register for the computation and we don't want that
6431 // If the operand is a float, integer, or vector constant, spill to a
6432 // constant pool entry to get its address.
6433 const Value *OpVal = OpInfo.CallOperandVal;
6434 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6435 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6436 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6437 TLI.getPointerTy());
6439 // Otherwise, create a stack slot and emit a store to it before the
6441 Type *Ty = OpVal->getType();
6442 uint64_t TySize = TLI.getDataLayout()->getTypeAllocSize(Ty);
6443 unsigned Align = TLI.getDataLayout()->getPrefTypeAlignment(Ty);
6444 MachineFunction &MF = DAG.getMachineFunction();
6445 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6446 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6447 Chain = DAG.getStore(Chain, getCurSDLoc(),
6448 OpInfo.CallOperand, StackSlot,
6449 MachinePointerInfo::getFixedStack(SSFI),
6451 OpInfo.CallOperand = StackSlot;
6454 // There is no longer a Value* corresponding to this operand.
6455 OpInfo.CallOperandVal = nullptr;
6457 // It is now an indirect operand.
6458 OpInfo.isIndirect = true;
6461 // If this constraint is for a specific register, allocate it before
6463 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6464 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6467 // Second pass - Loop over all of the operands, assigning virtual or physregs
6468 // to register class operands.
6469 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6470 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6472 // C_Register operands have already been allocated, Other/Memory don't need
6474 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6475 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6478 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6479 std::vector<SDValue> AsmNodeOperands;
6480 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6481 AsmNodeOperands.push_back(
6482 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6483 TLI.getPointerTy()));
6485 // If we have a !srcloc metadata node associated with it, we want to attach
6486 // this to the ultimately generated inline asm machineinstr. To do this, we
6487 // pass in the third operand as this (potentially null) inline asm MDNode.
6488 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6489 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6491 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6492 // bits as operand 3.
6493 unsigned ExtraInfo = 0;
6494 if (IA->hasSideEffects())
6495 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6496 if (IA->isAlignStack())
6497 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6498 // Set the asm dialect.
6499 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6501 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6502 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6503 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6505 // Compute the constraint code and ConstraintType to use.
6506 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6508 // Ideally, we would only check against memory constraints. However, the
6509 // meaning of an other constraint can be target-specific and we can't easily
6510 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6511 // for other constriants as well.
6512 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6513 OpInfo.ConstraintType == TargetLowering::C_Other) {
6514 if (OpInfo.Type == InlineAsm::isInput)
6515 ExtraInfo |= InlineAsm::Extra_MayLoad;
6516 else if (OpInfo.Type == InlineAsm::isOutput)
6517 ExtraInfo |= InlineAsm::Extra_MayStore;
6518 else if (OpInfo.Type == InlineAsm::isClobber)
6519 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6523 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6524 TLI.getPointerTy()));
6526 // Loop over all of the inputs, copying the operand values into the
6527 // appropriate registers and processing the output regs.
6528 RegsForValue RetValRegs;
6530 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6531 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6533 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6534 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6536 switch (OpInfo.Type) {
6537 case InlineAsm::isOutput: {
6538 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6539 OpInfo.ConstraintType != TargetLowering::C_Register) {
6540 // Memory output, or 'other' output (e.g. 'X' constraint).
6541 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6543 unsigned ConstraintID =
6544 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6545 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6546 "Failed to convert memory constraint code to constraint id.");
6548 // Add information to the INLINEASM node to know about this output.
6549 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6550 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6551 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, MVT::i32));
6552 AsmNodeOperands.push_back(OpInfo.CallOperand);
6556 // Otherwise, this is a register or register class output.
6558 // Copy the output from the appropriate register. Find a register that
6560 if (OpInfo.AssignedRegs.Regs.empty()) {
6561 LLVMContext &Ctx = *DAG.getContext();
6562 Ctx.emitError(CS.getInstruction(),
6563 "couldn't allocate output register for constraint '" +
6564 Twine(OpInfo.ConstraintCode) + "'");
6568 // If this is an indirect operand, store through the pointer after the
6570 if (OpInfo.isIndirect) {
6571 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6572 OpInfo.CallOperandVal));
6574 // This is the result value of the call.
6575 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6576 // Concatenate this output onto the outputs list.
6577 RetValRegs.append(OpInfo.AssignedRegs);
6580 // Add information to the INLINEASM node to know that this register is
6583 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6584 ? InlineAsm::Kind_RegDefEarlyClobber
6585 : InlineAsm::Kind_RegDef,
6586 false, 0, DAG, AsmNodeOperands);
6589 case InlineAsm::isInput: {
6590 SDValue InOperandVal = OpInfo.CallOperand;
6592 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6593 // If this is required to match an output register we have already set,
6594 // just use its register.
6595 unsigned OperandNo = OpInfo.getMatchedOperand();
6597 // Scan until we find the definition we already emitted of this operand.
6598 // When we find it, create a RegsForValue operand.
6599 unsigned CurOp = InlineAsm::Op_FirstOperand;
6600 for (; OperandNo; --OperandNo) {
6601 // Advance to the next operand.
6603 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6604 assert((InlineAsm::isRegDefKind(OpFlag) ||
6605 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6606 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6607 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6611 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6612 if (InlineAsm::isRegDefKind(OpFlag) ||
6613 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6614 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6615 if (OpInfo.isIndirect) {
6616 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6617 LLVMContext &Ctx = *DAG.getContext();
6618 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6619 " don't know how to handle tied "
6620 "indirect register inputs");
6624 RegsForValue MatchedRegs;
6625 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6626 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6627 MatchedRegs.RegVTs.push_back(RegVT);
6628 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6629 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6631 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6632 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6634 LLVMContext &Ctx = *DAG.getContext();
6635 Ctx.emitError(CS.getInstruction(),
6636 "inline asm error: This value"
6637 " type register class is not natively supported!");
6641 // Use the produced MatchedRegs object to
6642 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6643 Chain, &Flag, CS.getInstruction());
6644 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6645 true, OpInfo.getMatchedOperand(),
6646 DAG, AsmNodeOperands);
6650 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6651 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6652 "Unexpected number of operands");
6653 // Add information to the INLINEASM node to know about this input.
6654 // See InlineAsm.h isUseOperandTiedToDef.
6655 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6656 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6657 OpInfo.getMatchedOperand());
6658 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6659 TLI.getPointerTy()));
6660 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6664 // Treat indirect 'X' constraint as memory.
6665 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6667 OpInfo.ConstraintType = TargetLowering::C_Memory;
6669 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6670 std::vector<SDValue> Ops;
6671 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6674 LLVMContext &Ctx = *DAG.getContext();
6675 Ctx.emitError(CS.getInstruction(),
6676 "invalid operand for inline asm constraint '" +
6677 Twine(OpInfo.ConstraintCode) + "'");
6681 // Add information to the INLINEASM node to know about this input.
6682 unsigned ResOpType =
6683 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6684 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6685 TLI.getPointerTy()));
6686 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6690 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6691 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6692 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6693 "Memory operands expect pointer values");
6695 unsigned ConstraintID =
6696 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6697 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6698 "Failed to convert memory constraint code to constraint id.");
6700 // Add information to the INLINEASM node to know about this input.
6701 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6702 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6703 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, MVT::i32));
6704 AsmNodeOperands.push_back(InOperandVal);
6708 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6709 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6710 "Unknown constraint type!");
6712 // TODO: Support this.
6713 if (OpInfo.isIndirect) {
6714 LLVMContext &Ctx = *DAG.getContext();
6715 Ctx.emitError(CS.getInstruction(),
6716 "Don't know how to handle indirect register inputs yet "
6717 "for constraint '" +
6718 Twine(OpInfo.ConstraintCode) + "'");
6722 // Copy the input into the appropriate registers.
6723 if (OpInfo.AssignedRegs.Regs.empty()) {
6724 LLVMContext &Ctx = *DAG.getContext();
6725 Ctx.emitError(CS.getInstruction(),
6726 "couldn't allocate input reg for constraint '" +
6727 Twine(OpInfo.ConstraintCode) + "'");
6731 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6732 Chain, &Flag, CS.getInstruction());
6734 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6735 DAG, AsmNodeOperands);
6738 case InlineAsm::isClobber: {
6739 // Add the clobbered value to the operand list, so that the register
6740 // allocator is aware that the physreg got clobbered.
6741 if (!OpInfo.AssignedRegs.Regs.empty())
6742 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6750 // Finish up input operands. Set the input chain and add the flag last.
6751 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6752 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6754 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6755 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6756 Flag = Chain.getValue(1);
6758 // If this asm returns a register value, copy the result from that register
6759 // and set it as the value of the call.
6760 if (!RetValRegs.Regs.empty()) {
6761 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6762 Chain, &Flag, CS.getInstruction());
6764 // FIXME: Why don't we do this for inline asms with MRVs?
6765 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6766 EVT ResultType = TLI.getValueType(CS.getType());
6768 // If any of the results of the inline asm is a vector, it may have the
6769 // wrong width/num elts. This can happen for register classes that can
6770 // contain multiple different value types. The preg or vreg allocated may
6771 // not have the same VT as was expected. Convert it to the right type
6772 // with bit_convert.
6773 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6774 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6777 } else if (ResultType != Val.getValueType() &&
6778 ResultType.isInteger() && Val.getValueType().isInteger()) {
6779 // If a result value was tied to an input value, the computed result may
6780 // have a wider width than the expected result. Extract the relevant
6782 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6785 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6788 setValue(CS.getInstruction(), Val);
6789 // Don't need to use this as a chain in this case.
6790 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6794 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6796 // Process indirect outputs, first output all of the flagged copies out of
6798 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6799 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6800 const Value *Ptr = IndirectStoresToEmit[i].second;
6801 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6803 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6806 // Emit the non-flagged stores from the physregs.
6807 SmallVector<SDValue, 8> OutChains;
6808 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6809 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6810 StoresToEmit[i].first,
6811 getValue(StoresToEmit[i].second),
6812 MachinePointerInfo(StoresToEmit[i].second),
6814 OutChains.push_back(Val);
6817 if (!OutChains.empty())
6818 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6823 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6824 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6825 MVT::Other, getRoot(),
6826 getValue(I.getArgOperand(0)),
6827 DAG.getSrcValue(I.getArgOperand(0))));
6830 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6832 const DataLayout &DL = *TLI.getDataLayout();
6833 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurSDLoc(),
6834 getRoot(), getValue(I.getOperand(0)),
6835 DAG.getSrcValue(I.getOperand(0)),
6836 DL.getABITypeAlignment(I.getType()));
6838 DAG.setRoot(V.getValue(1));
6841 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6842 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6843 MVT::Other, getRoot(),
6844 getValue(I.getArgOperand(0)),
6845 DAG.getSrcValue(I.getArgOperand(0))));
6848 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6849 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6850 MVT::Other, getRoot(),
6851 getValue(I.getArgOperand(0)),
6852 getValue(I.getArgOperand(1)),
6853 DAG.getSrcValue(I.getArgOperand(0)),
6854 DAG.getSrcValue(I.getArgOperand(1))));
6857 /// \brief Lower an argument list according to the target calling convention.
6859 /// \return A tuple of <return-value, token-chain>
6861 /// This is a helper for lowering intrinsics that follow a target calling
6862 /// convention or require stack pointer adjustment. Only a subset of the
6863 /// intrinsic's operands need to participate in the calling convention.
6864 std::pair<SDValue, SDValue>
6865 SelectionDAGBuilder::lowerCallOperands(ImmutableCallSite CS, unsigned ArgIdx,
6866 unsigned NumArgs, SDValue Callee,
6868 MachineBasicBlock *LandingPad,
6869 bool IsPatchPoint) {
6870 TargetLowering::ArgListTy Args;
6871 Args.reserve(NumArgs);
6873 // Populate the argument list.
6874 // Attributes for args start at offset 1, after the return attribute.
6875 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6876 ArgI != ArgE; ++ArgI) {
6877 const Value *V = CS->getOperand(ArgI);
6879 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6881 TargetLowering::ArgListEntry Entry;
6882 Entry.Node = getValue(V);
6883 Entry.Ty = V->getType();
6884 Entry.setAttributes(&CS, AttrI);
6885 Args.push_back(Entry);
6888 Type *retTy = UseVoidTy ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6889 TargetLowering::CallLoweringInfo CLI(DAG);
6890 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6891 .setCallee(CS.getCallingConv(), retTy, Callee, std::move(Args), NumArgs)
6892 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6894 return lowerInvokable(CLI, LandingPad);
6897 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6898 /// or patchpoint target node's operand list.
6900 /// Constants are converted to TargetConstants purely as an optimization to
6901 /// avoid constant materialization and register allocation.
6903 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6904 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6905 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6906 /// address materialization and register allocation, but may also be required
6907 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6908 /// alloca in the entry block, then the runtime may assume that the alloca's
6909 /// StackMap location can be read immediately after compilation and that the
6910 /// location is valid at any point during execution (this is similar to the
6911 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6912 /// only available in a register, then the runtime would need to trap when
6913 /// execution reaches the StackMap in order to read the alloca's location.
6914 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6915 SmallVectorImpl<SDValue> &Ops,
6916 SelectionDAGBuilder &Builder) {
6917 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6918 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6919 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6921 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6923 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6924 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6925 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6927 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6929 Ops.push_back(OpVal);
6933 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6934 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6935 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6936 // [live variables...])
6938 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6940 SDValue Chain, InFlag, Callee, NullPtr;
6941 SmallVector<SDValue, 32> Ops;
6943 SDLoc DL = getCurSDLoc();
6944 Callee = getValue(CI.getCalledValue());
6945 NullPtr = DAG.getIntPtrConstant(0, true);
6947 // The stackmap intrinsic only records the live variables (the arguemnts
6948 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6949 // intrinsic, this won't be lowered to a function call. This means we don't
6950 // have to worry about calling conventions and target specific lowering code.
6951 // Instead we perform the call lowering right here.
6953 // chain, flag = CALLSEQ_START(chain, 0)
6954 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6955 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6957 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6958 InFlag = Chain.getValue(1);
6960 // Add the <id> and <numBytes> constants.
6961 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6962 Ops.push_back(DAG.getTargetConstant(
6963 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6964 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6965 Ops.push_back(DAG.getTargetConstant(
6966 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6968 // Push live variables for the stack map.
6969 addStackMapLiveVars(&CI, 2, Ops, *this);
6971 // We are not pushing any register mask info here on the operands list,
6972 // because the stackmap doesn't clobber anything.
6974 // Push the chain and the glue flag.
6975 Ops.push_back(Chain);
6976 Ops.push_back(InFlag);
6978 // Create the STACKMAP node.
6979 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6980 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6981 Chain = SDValue(SM, 0);
6982 InFlag = Chain.getValue(1);
6984 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6986 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6988 // Set the root to the target-lowered call chain.
6991 // Inform the Frame Information that we have a stackmap in this function.
6992 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6995 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6996 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6997 MachineBasicBlock *LandingPad) {
6998 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
7003 // [live variables...])
7005 CallingConv::ID CC = CS.getCallingConv();
7006 bool IsAnyRegCC = CC == CallingConv::AnyReg;
7007 bool HasDef = !CS->getType()->isVoidTy();
7008 SDValue Callee = getValue(CS->getOperand(2)); // <target>
7010 // Get the real number of arguments participating in the call <numArgs>
7011 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
7012 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
7014 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
7015 // Intrinsics include all meta-operands up to but not including CC.
7016 unsigned NumMetaOpers = PatchPointOpers::CCPos;
7017 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
7018 "Not enough arguments provided to the patchpoint intrinsic");
7020 // For AnyRegCC the arguments are lowered later on manually.
7021 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
7022 std::pair<SDValue, SDValue> Result =
7023 lowerCallOperands(CS, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC,
7026 SDNode *CallEnd = Result.second.getNode();
7027 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
7028 CallEnd = CallEnd->getOperand(0).getNode();
7030 /// Get a call instruction from the call sequence chain.
7031 /// Tail calls are not allowed.
7032 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7033 "Expected a callseq node.");
7034 SDNode *Call = CallEnd->getOperand(0).getNode();
7035 bool HasGlue = Call->getGluedNode();
7037 // Replace the target specific call node with the patchable intrinsic.
7038 SmallVector<SDValue, 8> Ops;
7040 // Add the <id> and <numBytes> constants.
7041 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
7042 Ops.push_back(DAG.getTargetConstant(
7043 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7044 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
7045 Ops.push_back(DAG.getTargetConstant(
7046 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7048 // Assume that the Callee is a constant address.
7049 // FIXME: handle function symbols in the future.
7051 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7052 /*isTarget=*/true));
7054 // Adjust <numArgs> to account for any arguments that have been passed on the
7056 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7057 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
7058 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
7059 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7061 // Add the calling convention
7062 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7064 // Add the arguments we omitted previously. The register allocator should
7065 // place these in any free register.
7067 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7068 Ops.push_back(getValue(CS.getArgument(i)));
7070 // Push the arguments from the call instruction up to the register mask.
7071 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
7072 Ops.append(Call->op_begin() + 2, e);
7074 // Push live variables for the stack map.
7075 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, Ops, *this);
7077 // Push the register mask info.
7079 Ops.push_back(*(Call->op_end()-2));
7081 Ops.push_back(*(Call->op_end()-1));
7083 // Push the chain (this is originally the first operand of the call, but
7084 // becomes now the last or second to last operand).
7085 Ops.push_back(*(Call->op_begin()));
7087 // Push the glue flag (last operand).
7089 Ops.push_back(*(Call->op_end()-1));
7092 if (IsAnyRegCC && HasDef) {
7093 // Create the return types based on the intrinsic definition
7094 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7095 SmallVector<EVT, 3> ValueVTs;
7096 ComputeValueVTs(TLI, CS->getType(), ValueVTs);
7097 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7099 // There is always a chain and a glue type at the end
7100 ValueVTs.push_back(MVT::Other);
7101 ValueVTs.push_back(MVT::Glue);
7102 NodeTys = DAG.getVTList(ValueVTs);
7104 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7106 // Replace the target specific call node with a PATCHPOINT node.
7107 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7108 getCurSDLoc(), NodeTys, Ops);
7110 // Update the NodeMap.
7113 setValue(CS.getInstruction(), SDValue(MN, 0));
7115 setValue(CS.getInstruction(), Result.first);
7118 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7119 // call sequence. Furthermore the location of the chain and glue can change
7120 // when the AnyReg calling convention is used and the intrinsic returns a
7122 if (IsAnyRegCC && HasDef) {
7123 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7124 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7125 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7127 DAG.ReplaceAllUsesWith(Call, MN);
7128 DAG.DeleteNode(Call);
7130 // Inform the Frame Information that we have a patchpoint in this function.
7131 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7134 /// Returns an AttributeSet representing the attributes applied to the return
7135 /// value of the given call.
7136 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
7137 SmallVector<Attribute::AttrKind, 2> Attrs;
7139 Attrs.push_back(Attribute::SExt);
7141 Attrs.push_back(Attribute::ZExt);
7143 Attrs.push_back(Attribute::InReg);
7145 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
7149 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7150 /// implementation, which just calls LowerCall.
7151 /// FIXME: When all targets are
7152 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7153 std::pair<SDValue, SDValue>
7154 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7155 // Handle the incoming return values from the call.
7157 Type *OrigRetTy = CLI.RetTy;
7158 SmallVector<EVT, 4> RetTys;
7159 SmallVector<uint64_t, 4> Offsets;
7160 ComputeValueVTs(*this, CLI.RetTy, RetTys, &Offsets);
7162 SmallVector<ISD::OutputArg, 4> Outs;
7163 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this);
7165 bool CanLowerReturn =
7166 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7167 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7169 SDValue DemoteStackSlot;
7170 int DemoteStackIdx = -100;
7171 if (!CanLowerReturn) {
7172 // FIXME: equivalent assert?
7173 // assert(!CS.hasInAllocaArgument() &&
7174 // "sret demotion is incompatible with inalloca");
7175 uint64_t TySize = getDataLayout()->getTypeAllocSize(CLI.RetTy);
7176 unsigned Align = getDataLayout()->getPrefTypeAlignment(CLI.RetTy);
7177 MachineFunction &MF = CLI.DAG.getMachineFunction();
7178 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7179 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7181 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy());
7183 Entry.Node = DemoteStackSlot;
7184 Entry.Ty = StackSlotPtrType;
7185 Entry.isSExt = false;
7186 Entry.isZExt = false;
7187 Entry.isInReg = false;
7188 Entry.isSRet = true;
7189 Entry.isNest = false;
7190 Entry.isByVal = false;
7191 Entry.isReturned = false;
7192 Entry.Alignment = Align;
7193 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7194 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7196 // sret demotion isn't compatible with tail-calls, since the sret argument
7197 // points into the callers stack frame.
7198 CLI.IsTailCall = false;
7200 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7202 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7203 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7204 for (unsigned i = 0; i != NumRegs; ++i) {
7205 ISD::InputArg MyFlags;
7206 MyFlags.VT = RegisterVT;
7208 MyFlags.Used = CLI.IsReturnValueUsed;
7210 MyFlags.Flags.setSExt();
7212 MyFlags.Flags.setZExt();
7214 MyFlags.Flags.setInReg();
7215 CLI.Ins.push_back(MyFlags);
7220 // Handle all of the outgoing arguments.
7222 CLI.OutVals.clear();
7223 ArgListTy &Args = CLI.getArgs();
7224 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7225 SmallVector<EVT, 4> ValueVTs;
7226 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7227 Type *FinalType = Args[i].Ty;
7228 if (Args[i].isByVal)
7229 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7230 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7231 FinalType, CLI.CallConv, CLI.IsVarArg);
7232 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7234 EVT VT = ValueVTs[Value];
7235 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7236 SDValue Op = SDValue(Args[i].Node.getNode(),
7237 Args[i].Node.getResNo() + Value);
7238 ISD::ArgFlagsTy Flags;
7239 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7245 if (Args[i].isInReg)
7249 if (Args[i].isByVal)
7251 if (Args[i].isInAlloca) {
7252 Flags.setInAlloca();
7253 // Set the byval flag for CCAssignFn callbacks that don't know about
7254 // inalloca. This way we can know how many bytes we should've allocated
7255 // and how many bytes a callee cleanup function will pop. If we port
7256 // inalloca to more targets, we'll have to add custom inalloca handling
7257 // in the various CC lowering callbacks.
7260 if (Args[i].isByVal || Args[i].isInAlloca) {
7261 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7262 Type *ElementTy = Ty->getElementType();
7263 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7264 // For ByVal, alignment should come from FE. BE will guess if this
7265 // info is not there but there are cases it cannot get right.
7266 unsigned FrameAlign;
7267 if (Args[i].Alignment)
7268 FrameAlign = Args[i].Alignment;
7270 FrameAlign = getByValTypeAlignment(ElementTy);
7271 Flags.setByValAlign(FrameAlign);
7276 Flags.setInConsecutiveRegs();
7277 Flags.setOrigAlign(OriginalAlignment);
7279 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7280 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7281 SmallVector<SDValue, 4> Parts(NumParts);
7282 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7285 ExtendKind = ISD::SIGN_EXTEND;
7286 else if (Args[i].isZExt)
7287 ExtendKind = ISD::ZERO_EXTEND;
7289 // Conservatively only handle 'returned' on non-vectors for now
7290 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7291 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7292 "unexpected use of 'returned'");
7293 // Before passing 'returned' to the target lowering code, ensure that
7294 // either the register MVT and the actual EVT are the same size or that
7295 // the return value and argument are extended in the same way; in these
7296 // cases it's safe to pass the argument register value unchanged as the
7297 // return register value (although it's at the target's option whether
7299 // TODO: allow code generation to take advantage of partially preserved
7300 // registers rather than clobbering the entire register when the
7301 // parameter extension method is not compatible with the return
7303 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7304 (ExtendKind != ISD::ANY_EXTEND &&
7305 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7306 Flags.setReturned();
7309 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7310 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7312 for (unsigned j = 0; j != NumParts; ++j) {
7313 // if it isn't first piece, alignment must be 1
7314 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7315 i < CLI.NumFixedArgs,
7316 i, j*Parts[j].getValueType().getStoreSize());
7317 if (NumParts > 1 && j == 0)
7318 MyFlags.Flags.setSplit();
7320 MyFlags.Flags.setOrigAlign(1);
7322 CLI.Outs.push_back(MyFlags);
7323 CLI.OutVals.push_back(Parts[j]);
7326 if (NeedsRegBlock && Value == NumValues - 1)
7327 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7331 SmallVector<SDValue, 4> InVals;
7332 CLI.Chain = LowerCall(CLI, InVals);
7334 // Verify that the target's LowerCall behaved as expected.
7335 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7336 "LowerCall didn't return a valid chain!");
7337 assert((!CLI.IsTailCall || InVals.empty()) &&
7338 "LowerCall emitted a return value for a tail call!");
7339 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7340 "LowerCall didn't emit the correct number of values!");
7342 // For a tail call, the return value is merely live-out and there aren't
7343 // any nodes in the DAG representing it. Return a special value to
7344 // indicate that a tail call has been emitted and no more Instructions
7345 // should be processed in the current block.
7346 if (CLI.IsTailCall) {
7347 CLI.DAG.setRoot(CLI.Chain);
7348 return std::make_pair(SDValue(), SDValue());
7351 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7352 assert(InVals[i].getNode() &&
7353 "LowerCall emitted a null value!");
7354 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7355 "LowerCall emitted a value with the wrong type!");
7358 SmallVector<SDValue, 4> ReturnValues;
7359 if (!CanLowerReturn) {
7360 // The instruction result is the result of loading from the
7361 // hidden sret parameter.
7362 SmallVector<EVT, 1> PVTs;
7363 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7365 ComputeValueVTs(*this, PtrRetTy, PVTs);
7366 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7367 EVT PtrVT = PVTs[0];
7369 unsigned NumValues = RetTys.size();
7370 ReturnValues.resize(NumValues);
7371 SmallVector<SDValue, 4> Chains(NumValues);
7373 for (unsigned i = 0; i < NumValues; ++i) {
7374 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7375 CLI.DAG.getConstant(Offsets[i], PtrVT));
7376 SDValue L = CLI.DAG.getLoad(
7377 RetTys[i], CLI.DL, CLI.Chain, Add,
7378 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), false,
7380 ReturnValues[i] = L;
7381 Chains[i] = L.getValue(1);
7384 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7386 // Collect the legal value parts into potentially illegal values
7387 // that correspond to the original function's return values.
7388 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7390 AssertOp = ISD::AssertSext;
7391 else if (CLI.RetZExt)
7392 AssertOp = ISD::AssertZext;
7393 unsigned CurReg = 0;
7394 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7396 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7397 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7399 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7400 NumRegs, RegisterVT, VT, nullptr,
7405 // For a function returning void, there is no return value. We can't create
7406 // such a node, so we just return a null return value in that case. In
7407 // that case, nothing will actually look at the value.
7408 if (ReturnValues.empty())
7409 return std::make_pair(SDValue(), CLI.Chain);
7412 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7413 CLI.DAG.getVTList(RetTys), ReturnValues);
7414 return std::make_pair(Res, CLI.Chain);
7417 void TargetLowering::LowerOperationWrapper(SDNode *N,
7418 SmallVectorImpl<SDValue> &Results,
7419 SelectionDAG &DAG) const {
7420 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7422 Results.push_back(Res);
7425 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7426 llvm_unreachable("LowerOperation not implemented for this target!");
7430 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7431 SDValue Op = getNonRegisterValue(V);
7432 assert((Op.getOpcode() != ISD::CopyFromReg ||
7433 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7434 "Copy from a reg to the same reg!");
7435 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7437 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7438 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
7439 SDValue Chain = DAG.getEntryNode();
7441 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7442 FuncInfo.PreferredExtendType.end())
7444 : FuncInfo.PreferredExtendType[V];
7445 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7446 PendingExports.push_back(Chain);
7449 #include "llvm/CodeGen/SelectionDAGISel.h"
7451 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7452 /// entry block, return true. This includes arguments used by switches, since
7453 /// the switch may expand into multiple basic blocks.
7454 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7455 // With FastISel active, we may be splitting blocks, so force creation
7456 // of virtual registers for all non-dead arguments.
7458 return A->use_empty();
7460 const BasicBlock *Entry = A->getParent()->begin();
7461 for (const User *U : A->users())
7462 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7463 return false; // Use not in entry block.
7468 void SelectionDAGISel::LowerArguments(const Function &F) {
7469 SelectionDAG &DAG = SDB->DAG;
7470 SDLoc dl = SDB->getCurSDLoc();
7471 const DataLayout *DL = TLI->getDataLayout();
7472 SmallVector<ISD::InputArg, 16> Ins;
7474 if (!FuncInfo->CanLowerReturn) {
7475 // Put in an sret pointer parameter before all the other parameters.
7476 SmallVector<EVT, 1> ValueVTs;
7477 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7479 // NOTE: Assuming that a pointer will never break down to more than one VT
7481 ISD::ArgFlagsTy Flags;
7483 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7484 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7485 ISD::InputArg::NoArgIndex, 0);
7486 Ins.push_back(RetArg);
7489 // Set up the incoming argument description vector.
7491 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7492 I != E; ++I, ++Idx) {
7493 SmallVector<EVT, 4> ValueVTs;
7494 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7495 bool isArgValueUsed = !I->use_empty();
7496 unsigned PartBase = 0;
7497 Type *FinalType = I->getType();
7498 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7499 FinalType = cast<PointerType>(FinalType)->getElementType();
7500 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7501 FinalType, F.getCallingConv(), F.isVarArg());
7502 for (unsigned Value = 0, NumValues = ValueVTs.size();
7503 Value != NumValues; ++Value) {
7504 EVT VT = ValueVTs[Value];
7505 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7506 ISD::ArgFlagsTy Flags;
7507 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7509 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7511 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7513 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7515 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7517 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7519 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7520 Flags.setInAlloca();
7521 // Set the byval flag for CCAssignFn callbacks that don't know about
7522 // inalloca. This way we can know how many bytes we should've allocated
7523 // and how many bytes a callee cleanup function will pop. If we port
7524 // inalloca to more targets, we'll have to add custom inalloca handling
7525 // in the various CC lowering callbacks.
7528 if (Flags.isByVal() || Flags.isInAlloca()) {
7529 PointerType *Ty = cast<PointerType>(I->getType());
7530 Type *ElementTy = Ty->getElementType();
7531 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7532 // For ByVal, alignment should be passed from FE. BE will guess if
7533 // this info is not there but there are cases it cannot get right.
7534 unsigned FrameAlign;
7535 if (F.getParamAlignment(Idx))
7536 FrameAlign = F.getParamAlignment(Idx);
7538 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7539 Flags.setByValAlign(FrameAlign);
7541 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7544 Flags.setInConsecutiveRegs();
7545 Flags.setOrigAlign(OriginalAlignment);
7547 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7548 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7549 for (unsigned i = 0; i != NumRegs; ++i) {
7550 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7551 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7552 if (NumRegs > 1 && i == 0)
7553 MyFlags.Flags.setSplit();
7554 // if it isn't first piece, alignment must be 1
7556 MyFlags.Flags.setOrigAlign(1);
7557 Ins.push_back(MyFlags);
7559 if (NeedsRegBlock && Value == NumValues - 1)
7560 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7561 PartBase += VT.getStoreSize();
7565 // Call the target to set up the argument values.
7566 SmallVector<SDValue, 8> InVals;
7567 SDValue NewRoot = TLI->LowerFormalArguments(
7568 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7570 // Verify that the target's LowerFormalArguments behaved as expected.
7571 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7572 "LowerFormalArguments didn't return a valid chain!");
7573 assert(InVals.size() == Ins.size() &&
7574 "LowerFormalArguments didn't emit the correct number of values!");
7576 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7577 assert(InVals[i].getNode() &&
7578 "LowerFormalArguments emitted a null value!");
7579 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7580 "LowerFormalArguments emitted a value with the wrong type!");
7584 // Update the DAG with the new chain value resulting from argument lowering.
7585 DAG.setRoot(NewRoot);
7587 // Set up the argument values.
7590 if (!FuncInfo->CanLowerReturn) {
7591 // Create a virtual register for the sret pointer, and put in a copy
7592 // from the sret argument into it.
7593 SmallVector<EVT, 1> ValueVTs;
7594 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7595 MVT VT = ValueVTs[0].getSimpleVT();
7596 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7597 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7598 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7599 RegVT, VT, nullptr, AssertOp);
7601 MachineFunction& MF = SDB->DAG.getMachineFunction();
7602 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7603 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7604 FuncInfo->DemoteRegister = SRetReg;
7606 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7607 DAG.setRoot(NewRoot);
7609 // i indexes lowered arguments. Bump it past the hidden sret argument.
7610 // Idx indexes LLVM arguments. Don't touch it.
7614 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7616 SmallVector<SDValue, 4> ArgValues;
7617 SmallVector<EVT, 4> ValueVTs;
7618 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7619 unsigned NumValues = ValueVTs.size();
7621 // If this argument is unused then remember its value. It is used to generate
7622 // debugging information.
7623 if (I->use_empty() && NumValues) {
7624 SDB->setUnusedArgValue(I, InVals[i]);
7626 // Also remember any frame index for use in FastISel.
7627 if (FrameIndexSDNode *FI =
7628 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7629 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7632 for (unsigned Val = 0; Val != NumValues; ++Val) {
7633 EVT VT = ValueVTs[Val];
7634 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7635 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7637 if (!I->use_empty()) {
7638 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7639 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7640 AssertOp = ISD::AssertSext;
7641 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7642 AssertOp = ISD::AssertZext;
7644 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7645 NumParts, PartVT, VT,
7646 nullptr, AssertOp));
7652 // We don't need to do anything else for unused arguments.
7653 if (ArgValues.empty())
7656 // Note down frame index.
7657 if (FrameIndexSDNode *FI =
7658 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7659 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7661 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7662 SDB->getCurSDLoc());
7664 SDB->setValue(I, Res);
7665 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7666 if (LoadSDNode *LNode =
7667 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7668 if (FrameIndexSDNode *FI =
7669 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7670 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7673 // If this argument is live outside of the entry block, insert a copy from
7674 // wherever we got it to the vreg that other BB's will reference it as.
7675 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7676 // If we can, though, try to skip creating an unnecessary vreg.
7677 // FIXME: This isn't very clean... it would be nice to make this more
7678 // general. It's also subtly incompatible with the hacks FastISel
7680 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7681 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7682 FuncInfo->ValueMap[I] = Reg;
7686 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7687 FuncInfo->InitializeRegForValue(I);
7688 SDB->CopyToExportRegsIfNeeded(I);
7692 assert(i == InVals.size() && "Argument register count mismatch!");
7694 // Finally, if the target has anything special to do, allow it to do so.
7695 EmitFunctionEntryCode();
7698 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7699 /// ensure constants are generated when needed. Remember the virtual registers
7700 /// that need to be added to the Machine PHI nodes as input. We cannot just
7701 /// directly add them, because expansion might result in multiple MBB's for one
7702 /// BB. As such, the start of the BB might correspond to a different MBB than
7706 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7707 const TerminatorInst *TI = LLVMBB->getTerminator();
7709 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7711 // Check PHI nodes in successors that expect a value to be available from this
7713 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7714 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7715 if (!isa<PHINode>(SuccBB->begin())) continue;
7716 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7718 // If this terminator has multiple identical successors (common for
7719 // switches), only handle each succ once.
7720 if (!SuccsHandled.insert(SuccMBB).second)
7723 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7725 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7726 // nodes and Machine PHI nodes, but the incoming operands have not been
7728 for (BasicBlock::const_iterator I = SuccBB->begin();
7729 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7730 // Ignore dead phi's.
7731 if (PN->use_empty()) continue;
7734 if (PN->getType()->isEmptyTy())
7738 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7740 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7741 unsigned &RegOut = ConstantsOut[C];
7743 RegOut = FuncInfo.CreateRegs(C->getType());
7744 CopyValueToVirtualRegister(C, RegOut);
7748 DenseMap<const Value *, unsigned>::iterator I =
7749 FuncInfo.ValueMap.find(PHIOp);
7750 if (I != FuncInfo.ValueMap.end())
7753 assert(isa<AllocaInst>(PHIOp) &&
7754 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7755 "Didn't codegen value into a register!??");
7756 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7757 CopyValueToVirtualRegister(PHIOp, Reg);
7761 // Remember that this register needs to added to the machine PHI node as
7762 // the input for this MBB.
7763 SmallVector<EVT, 4> ValueVTs;
7764 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7765 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
7766 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7767 EVT VT = ValueVTs[vti];
7768 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7769 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7770 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7771 Reg += NumRegisters;
7776 ConstantsOut.clear();
7779 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7782 SelectionDAGBuilder::StackProtectorDescriptor::
7783 AddSuccessorMBB(const BasicBlock *BB,
7784 MachineBasicBlock *ParentMBB,
7786 MachineBasicBlock *SuccMBB) {
7787 // If SuccBB has not been created yet, create it.
7789 MachineFunction *MF = ParentMBB->getParent();
7790 MachineFunction::iterator BBI = ParentMBB;
7791 SuccMBB = MF->CreateMachineBasicBlock(BB);
7792 MF->insert(++BBI, SuccMBB);
7794 // Add it as a successor of ParentMBB.
7795 ParentMBB->addSuccessor(
7796 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7800 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7801 MachineFunction::iterator I = MBB;
7802 if (++I == FuncInfo.MF->end())
7807 /// During lowering new call nodes can be created (such as memset, etc.).
7808 /// Those will become new roots of the current DAG, but complications arise
7809 /// when they are tail calls. In such cases, the call lowering will update
7810 /// the root, but the builder still needs to know that a tail call has been
7811 /// lowered in order to avoid generating an additional return.
7812 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7813 // If the node is null, we do have a tail call.
7814 if (MaybeTC.getNode() != nullptr)
7815 DAG.setRoot(MaybeTC);