1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameLowering.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Debug.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "llvm/Support/MathExtras.h"
57 #include "llvm/Support/raw_ostream.h"
61 /// LimitFloatPrecision - Generate low-precision inline sequences for
62 /// some float libcalls (6, 8 or 12 bits).
63 static unsigned LimitFloatPrecision;
65 static cl::opt<unsigned, true>
66 LimitFPPrecision("limit-float-precision",
67 cl::desc("Generate low-precision inline sequences "
68 "for some float libcalls"),
69 cl::location(LimitFloatPrecision),
72 // Limit the width of DAG chains. This is important in general to prevent
73 // prevent DAG-based analysis from blowing up. For example, alias analysis and
74 // load clustering may not complete in reasonable time. It is difficult to
75 // recognize and avoid this situation within each individual analysis, and
76 // future analyses are likely to have the same behavior. Limiting DAG width is
77 // the safe approach, and will be especially important with global DAGs.
79 // MaxParallelChains default is arbitrarily high to avoid affecting
80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
81 // sequence over this should have been converted to llvm.memcpy by the
82 // frontend. It easy to induce this behavior with .ll code such as:
83 // %buffer = alloca [4096 x i8]
84 // %data = load [4096 x i8]* %argPtr
85 // store [4096 x i8] %data, [4096 x i8]* %buffer
86 static const unsigned MaxParallelChains = 64;
88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
89 const SDValue *Parts, unsigned NumParts,
90 EVT PartVT, EVT ValueVT);
92 /// getCopyFromParts - Create a value that contains the specified legal parts
93 /// combined into the value they represent. If the parts combine to a type
94 /// larger then ValueVT then AssertOp can be used to specify whether the extra
95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
96 /// (ISD::AssertSext).
97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
99 unsigned NumParts, EVT PartVT, EVT ValueVT,
100 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
101 if (ValueVT.isVector())
102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
104 assert(NumParts > 0 && "No parts to assemble!");
105 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
106 SDValue Val = Parts[0];
109 // Assemble the value from multiple parts.
110 if (ValueVT.isInteger()) {
111 unsigned PartBits = PartVT.getSizeInBits();
112 unsigned ValueBits = ValueVT.getSizeInBits();
114 // Assemble the power of 2 part.
115 unsigned RoundParts = NumParts & (NumParts - 1) ?
116 1 << Log2_32(NumParts) : NumParts;
117 unsigned RoundBits = PartBits * RoundParts;
118 EVT RoundVT = RoundBits == ValueBits ?
119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
124 if (RoundParts > 2) {
125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
128 RoundParts / 2, PartVT, HalfVT);
130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
134 if (TLI.isBigEndian())
137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
139 if (RoundParts < NumParts) {
140 // Assemble the trailing non-power-of-2 part.
141 unsigned OddParts = NumParts - RoundParts;
142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
143 Hi = getCopyFromParts(DAG, DL,
144 Parts + RoundParts, OddParts, PartVT, OddVT);
146 // Combine the round and odd parts.
148 if (TLI.isBigEndian())
150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
153 DAG.getConstant(Lo.getValueType().getSizeInBits(),
154 TLI.getPointerTy()));
155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
158 } else if (PartVT.isFloatingPoint()) {
159 // FP split into multiple FP parts (for ppcf128)
160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
165 if (TLI.isBigEndian())
167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
169 // FP split into integer parts (soft fp)
170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
171 !PartVT.isVector() && "Unexpected split");
172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
177 // There is now one part, held in Val. Correct it to match ValueVT.
178 PartVT = Val.getValueType();
180 if (PartVT == ValueVT)
183 if (PartVT.isInteger() && ValueVT.isInteger()) {
184 if (ValueVT.bitsLT(PartVT)) {
185 // For a truncate, see if we have any information to
186 // indicate whether the truncated bits will always be
187 // zero or sign-extension.
188 if (AssertOp != ISD::DELETED_NODE)
189 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
190 DAG.getValueType(ValueVT));
191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
197 // FP_ROUND's are always exact here.
198 if (ValueVT.bitsLT(Val.getValueType()))
199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
200 DAG.getTargetConstant(1, TLI.getPointerTy()));
202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
208 llvm_unreachable("Unknown mismatch!");
211 /// getCopyFromParts - Create a value that contains the specified legal parts
212 /// combined into the value they represent. If the parts combine to a type
213 /// larger then ValueVT then AssertOp can be used to specify whether the extra
214 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
215 /// (ISD::AssertSext).
216 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
217 const SDValue *Parts, unsigned NumParts,
218 EVT PartVT, EVT ValueVT) {
219 assert(ValueVT.isVector() && "Not a vector value");
220 assert(NumParts > 0 && "No parts to assemble!");
221 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
222 SDValue Val = Parts[0];
224 // Handle a multi-element vector.
226 EVT IntermediateVT, RegisterVT;
227 unsigned NumIntermediates;
229 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
230 NumIntermediates, RegisterVT);
231 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
232 NumParts = NumRegs; // Silence a compiler warning.
233 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
234 assert(RegisterVT == Parts[0].getValueType() &&
235 "Part type doesn't match part!");
237 // Assemble the parts into intermediate operands.
238 SmallVector<SDValue, 8> Ops(NumIntermediates);
239 if (NumIntermediates == NumParts) {
240 // If the register was not expanded, truncate or copy the value,
242 for (unsigned i = 0; i != NumParts; ++i)
243 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
244 PartVT, IntermediateVT);
245 } else if (NumParts > 0) {
246 // If the intermediate type was expanded, build the intermediate
247 // operands from the parts.
248 assert(NumParts % NumIntermediates == 0 &&
249 "Must expand into a divisible number of parts!");
250 unsigned Factor = NumParts / NumIntermediates;
251 for (unsigned i = 0; i != NumIntermediates; ++i)
252 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
253 PartVT, IntermediateVT);
256 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
257 // intermediate operands.
258 Val = DAG.getNode(IntermediateVT.isVector() ?
259 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
260 ValueVT, &Ops[0], NumIntermediates);
263 // There is now one part, held in Val. Correct it to match ValueVT.
264 PartVT = Val.getValueType();
266 if (PartVT == ValueVT)
269 if (PartVT.isVector()) {
270 // If the element type of the source/dest vectors are the same, but the
271 // parts vector has more elements than the value vector, then we have a
272 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
274 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
275 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
276 "Cannot narrow, it would be a lossy transformation");
277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
278 DAG.getIntPtrConstant(0));
281 // Vector/Vector bitcast.
282 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
283 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
285 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
286 "Cannot handle this kind of promotion");
287 // Promoted vector extract
288 bool Smaller = ValueVT.bitsLE(PartVT);
289 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
294 // Trivial bitcast if the types are the same size and the destination
295 // vector type is legal.
296 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
297 TLI.isTypeLegal(ValueVT))
298 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
300 // Handle cases such as i8 -> <1 x i1>
301 assert(ValueVT.getVectorNumElements() == 1 &&
302 "Only trivial scalar-to-vector conversions should get here!");
304 if (ValueVT.getVectorNumElements() == 1 &&
305 ValueVT.getVectorElementType() != PartVT) {
306 bool Smaller = ValueVT.bitsLE(PartVT);
307 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
308 DL, ValueVT.getScalarType(), Val);
311 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
317 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
318 SDValue Val, SDValue *Parts, unsigned NumParts,
321 /// getCopyToParts - Create a series of nodes that contain the specified value
322 /// split into legal parts. If the parts contain more bits than Val, then, for
323 /// integers, ExtendKind can be used to specify how to generate the extra bits.
324 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
325 SDValue Val, SDValue *Parts, unsigned NumParts,
327 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
328 EVT ValueVT = Val.getValueType();
330 // Handle the vector case separately.
331 if (ValueVT.isVector())
332 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
334 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
335 unsigned PartBits = PartVT.getSizeInBits();
336 unsigned OrigNumParts = NumParts;
337 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
342 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
343 if (PartVT == ValueVT) {
344 assert(NumParts == 1 && "No-op copy with multiple parts!");
349 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
350 // If the parts cover more bits than the value has, promote the value.
351 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
352 assert(NumParts == 1 && "Do not know what to promote to!");
353 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
355 assert(PartVT.isInteger() && ValueVT.isInteger() &&
356 "Unknown mismatch!");
357 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
358 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
360 } else if (PartBits == ValueVT.getSizeInBits()) {
361 // Different types of the same size.
362 assert(NumParts == 1 && PartVT != ValueVT);
363 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
364 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
365 // If the parts cover less bits than value has, truncate the value.
366 assert(PartVT.isInteger() && ValueVT.isInteger() &&
367 "Unknown mismatch!");
368 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
369 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
372 // The value may have changed - recompute ValueVT.
373 ValueVT = Val.getValueType();
374 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
375 "Failed to tile the value with PartVT!");
378 assert(PartVT == ValueVT && "Type conversion failed!");
383 // Expand the value into multiple parts.
384 if (NumParts & (NumParts - 1)) {
385 // The number of parts is not a power of 2. Split off and copy the tail.
386 assert(PartVT.isInteger() && ValueVT.isInteger() &&
387 "Do not know what to expand to!");
388 unsigned RoundParts = 1 << Log2_32(NumParts);
389 unsigned RoundBits = RoundParts * PartBits;
390 unsigned OddParts = NumParts - RoundParts;
391 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
392 DAG.getIntPtrConstant(RoundBits));
393 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
395 if (TLI.isBigEndian())
396 // The odd parts were reversed by getCopyToParts - unreverse them.
397 std::reverse(Parts + RoundParts, Parts + NumParts);
399 NumParts = RoundParts;
400 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
401 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
404 // The number of parts is a power of 2. Repeatedly bisect the value using
406 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
407 EVT::getIntegerVT(*DAG.getContext(),
408 ValueVT.getSizeInBits()),
411 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
412 for (unsigned i = 0; i < NumParts; i += StepSize) {
413 unsigned ThisBits = StepSize * PartBits / 2;
414 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
415 SDValue &Part0 = Parts[i];
416 SDValue &Part1 = Parts[i+StepSize/2];
418 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
419 ThisVT, Part0, DAG.getIntPtrConstant(1));
420 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
421 ThisVT, Part0, DAG.getIntPtrConstant(0));
423 if (ThisBits == PartBits && ThisVT != PartVT) {
424 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
425 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
430 if (TLI.isBigEndian())
431 std::reverse(Parts, Parts + OrigNumParts);
435 /// getCopyToPartsVector - Create a series of nodes that contain the specified
436 /// value split into legal parts.
437 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
438 SDValue Val, SDValue *Parts, unsigned NumParts,
440 EVT ValueVT = Val.getValueType();
441 assert(ValueVT.isVector() && "Not a vector");
442 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
445 if (PartVT == ValueVT) {
447 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
448 // Bitconvert vector->vector case.
449 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
450 } else if (PartVT.isVector() &&
451 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
452 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
453 EVT ElementVT = PartVT.getVectorElementType();
454 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
456 SmallVector<SDValue, 16> Ops;
457 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
458 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
459 ElementVT, Val, DAG.getIntPtrConstant(i)));
461 for (unsigned i = ValueVT.getVectorNumElements(),
462 e = PartVT.getVectorNumElements(); i != e; ++i)
463 Ops.push_back(DAG.getUNDEF(ElementVT));
465 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
467 // FIXME: Use CONCAT for 2x -> 4x.
469 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
470 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
471 } else if (PartVT.isVector() &&
472 PartVT.getVectorElementType().bitsGE(
473 ValueVT.getVectorElementType()) &&
474 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
476 // Promoted vector extract
477 bool Smaller = PartVT.bitsLE(ValueVT);
478 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
481 // Vector -> scalar conversion.
482 assert(ValueVT.getVectorNumElements() == 1 &&
483 "Only trivial vector-to-scalar conversions should get here!");
484 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
485 PartVT, Val, DAG.getIntPtrConstant(0));
487 bool Smaller = ValueVT.bitsLE(PartVT);
488 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
496 // Handle a multi-element vector.
497 EVT IntermediateVT, RegisterVT;
498 unsigned NumIntermediates;
499 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
501 NumIntermediates, RegisterVT);
502 unsigned NumElements = ValueVT.getVectorNumElements();
504 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
505 NumParts = NumRegs; // Silence a compiler warning.
506 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
508 // Split the vector into intermediate operands.
509 SmallVector<SDValue, 8> Ops(NumIntermediates);
510 for (unsigned i = 0; i != NumIntermediates; ++i) {
511 if (IntermediateVT.isVector())
512 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
514 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
516 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
517 IntermediateVT, Val, DAG.getIntPtrConstant(i));
520 // Split the intermediate operands into legal parts.
521 if (NumParts == NumIntermediates) {
522 // If the register was not expanded, promote or copy the value,
524 for (unsigned i = 0; i != NumParts; ++i)
525 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
526 } else if (NumParts > 0) {
527 // If the intermediate type was expanded, split each the value into
529 assert(NumParts % NumIntermediates == 0 &&
530 "Must expand into a divisible number of parts!");
531 unsigned Factor = NumParts / NumIntermediates;
532 for (unsigned i = 0; i != NumIntermediates; ++i)
533 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
541 /// RegsForValue - This struct represents the registers (physical or virtual)
542 /// that a particular set of values is assigned, and the type information
543 /// about the value. The most common situation is to represent one value at a
544 /// time, but struct or array values are handled element-wise as multiple
545 /// values. The splitting of aggregates is performed recursively, so that we
546 /// never have aggregate-typed registers. The values at this point do not
547 /// necessarily have legal types, so each value may require one or more
548 /// registers of some legal type.
550 struct RegsForValue {
551 /// ValueVTs - The value types of the values, which may not be legal, and
552 /// may need be promoted or synthesized from one or more registers.
554 SmallVector<EVT, 4> ValueVTs;
556 /// RegVTs - The value types of the registers. This is the same size as
557 /// ValueVTs and it records, for each value, what the type of the assigned
558 /// register or registers are. (Individual values are never synthesized
559 /// from more than one type of register.)
561 /// With virtual registers, the contents of RegVTs is redundant with TLI's
562 /// getRegisterType member function, however when with physical registers
563 /// it is necessary to have a separate record of the types.
565 SmallVector<EVT, 4> RegVTs;
567 /// Regs - This list holds the registers assigned to the values.
568 /// Each legal or promoted value requires one register, and each
569 /// expanded value requires multiple registers.
571 SmallVector<unsigned, 4> Regs;
575 RegsForValue(const SmallVector<unsigned, 4> ®s,
576 EVT regvt, EVT valuevt)
577 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
579 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
580 unsigned Reg, Type *Ty) {
581 ComputeValueVTs(tli, Ty, ValueVTs);
583 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
584 EVT ValueVT = ValueVTs[Value];
585 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
586 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
587 for (unsigned i = 0; i != NumRegs; ++i)
588 Regs.push_back(Reg + i);
589 RegVTs.push_back(RegisterVT);
594 /// areValueTypesLegal - Return true if types of all the values are legal.
595 bool areValueTypesLegal(const TargetLowering &TLI) {
596 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
597 EVT RegisterVT = RegVTs[Value];
598 if (!TLI.isTypeLegal(RegisterVT))
604 /// append - Add the specified values to this one.
605 void append(const RegsForValue &RHS) {
606 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
607 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
608 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
611 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
612 /// this value and returns the result as a ValueVTs value. This uses
613 /// Chain/Flag as the input and updates them for the output Chain/Flag.
614 /// If the Flag pointer is NULL, no flag is used.
615 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
617 SDValue &Chain, SDValue *Flag) const;
619 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
620 /// specified value into the registers specified by this object. This uses
621 /// Chain/Flag as the input and updates them for the output Chain/Flag.
622 /// If the Flag pointer is NULL, no flag is used.
623 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
624 SDValue &Chain, SDValue *Flag) const;
626 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
627 /// operand list. This adds the code marker, matching input operand index
628 /// (if applicable), and includes the number of values added into it.
629 void AddInlineAsmOperands(unsigned Kind,
630 bool HasMatching, unsigned MatchingIdx,
632 std::vector<SDValue> &Ops) const;
636 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
637 /// this value and returns the result as a ValueVT value. This uses
638 /// Chain/Flag as the input and updates them for the output Chain/Flag.
639 /// If the Flag pointer is NULL, no flag is used.
640 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
641 FunctionLoweringInfo &FuncInfo,
643 SDValue &Chain, SDValue *Flag) const {
644 // A Value with type {} or [0 x %t] needs no registers.
645 if (ValueVTs.empty())
648 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
650 // Assemble the legal parts into the final values.
651 SmallVector<SDValue, 4> Values(ValueVTs.size());
652 SmallVector<SDValue, 8> Parts;
653 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
654 // Copy the legal parts from the registers.
655 EVT ValueVT = ValueVTs[Value];
656 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
657 EVT RegisterVT = RegVTs[Value];
659 Parts.resize(NumRegs);
660 for (unsigned i = 0; i != NumRegs; ++i) {
663 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
665 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
666 *Flag = P.getValue(2);
669 Chain = P.getValue(1);
672 // If the source register was virtual and if we know something about it,
673 // add an assert node.
674 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
675 !RegisterVT.isInteger() || RegisterVT.isVector())
678 const FunctionLoweringInfo::LiveOutInfo *LOI =
679 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
683 unsigned RegSize = RegisterVT.getSizeInBits();
684 unsigned NumSignBits = LOI->NumSignBits;
685 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
687 // FIXME: We capture more information than the dag can represent. For
688 // now, just use the tightest assertzext/assertsext possible.
690 EVT FromVT(MVT::Other);
691 if (NumSignBits == RegSize)
692 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
693 else if (NumZeroBits >= RegSize-1)
694 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
695 else if (NumSignBits > RegSize-8)
696 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
697 else if (NumZeroBits >= RegSize-8)
698 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
699 else if (NumSignBits > RegSize-16)
700 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
701 else if (NumZeroBits >= RegSize-16)
702 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
703 else if (NumSignBits > RegSize-32)
704 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
705 else if (NumZeroBits >= RegSize-32)
706 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
710 // Add an assertion node.
711 assert(FromVT != MVT::Other);
712 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
713 RegisterVT, P, DAG.getValueType(FromVT));
716 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
717 NumRegs, RegisterVT, ValueVT);
722 return DAG.getNode(ISD::MERGE_VALUES, dl,
723 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
724 &Values[0], ValueVTs.size());
727 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
728 /// specified value into the registers specified by this object. This uses
729 /// Chain/Flag as the input and updates them for the output Chain/Flag.
730 /// If the Flag pointer is NULL, no flag is used.
731 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
732 SDValue &Chain, SDValue *Flag) const {
733 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
735 // Get the list of the values's legal parts.
736 unsigned NumRegs = Regs.size();
737 SmallVector<SDValue, 8> Parts(NumRegs);
738 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
739 EVT ValueVT = ValueVTs[Value];
740 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
741 EVT RegisterVT = RegVTs[Value];
743 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
744 &Parts[Part], NumParts, RegisterVT);
748 // Copy the parts into the registers.
749 SmallVector<SDValue, 8> Chains(NumRegs);
750 for (unsigned i = 0; i != NumRegs; ++i) {
753 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
755 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
756 *Flag = Part.getValue(1);
759 Chains[i] = Part.getValue(0);
762 if (NumRegs == 1 || Flag)
763 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
764 // flagged to it. That is the CopyToReg nodes and the user are considered
765 // a single scheduling unit. If we create a TokenFactor and return it as
766 // chain, then the TokenFactor is both a predecessor (operand) of the
767 // user as well as a successor (the TF operands are flagged to the user).
768 // c1, f1 = CopyToReg
769 // c2, f2 = CopyToReg
770 // c3 = TokenFactor c1, c2
773 Chain = Chains[NumRegs-1];
775 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
778 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
779 /// operand list. This adds the code marker and includes the number of
780 /// values added into it.
781 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
782 unsigned MatchingIdx,
784 std::vector<SDValue> &Ops) const {
785 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
787 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
789 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
790 else if (!Regs.empty() &&
791 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
792 // Put the register class of the virtual registers in the flag word. That
793 // way, later passes can recompute register class constraints for inline
794 // assembly as well as normal instructions.
795 // Don't do this for tied operands that can use the regclass information
797 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
798 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
799 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
802 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
805 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
806 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
807 EVT RegisterVT = RegVTs[Value];
808 for (unsigned i = 0; i != NumRegs; ++i) {
809 assert(Reg < Regs.size() && "Mismatch in # registers expected");
810 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
815 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
816 const TargetLibraryInfo *li) {
820 TD = DAG.getTarget().getTargetData();
821 LPadToCallSiteMap.clear();
824 /// clear - Clear out the current SelectionDAG and the associated
825 /// state and prepare this SelectionDAGBuilder object to be used
826 /// for a new block. This doesn't clear out information about
827 /// additional blocks that are needed to complete switch lowering
828 /// or PHI node updating; that information is cleared out as it is
830 void SelectionDAGBuilder::clear() {
832 UnusedArgNodeMap.clear();
833 PendingLoads.clear();
834 PendingExports.clear();
835 CurDebugLoc = DebugLoc();
839 /// clearDanglingDebugInfo - Clear the dangling debug information
840 /// map. This function is seperated from the clear so that debug
841 /// information that is dangling in a basic block can be properly
842 /// resolved in a different basic block. This allows the
843 /// SelectionDAG to resolve dangling debug information attached
845 void SelectionDAGBuilder::clearDanglingDebugInfo() {
846 DanglingDebugInfoMap.clear();
849 /// getRoot - Return the current virtual root of the Selection DAG,
850 /// flushing any PendingLoad items. This must be done before emitting
851 /// a store or any other node that may need to be ordered after any
852 /// prior load instructions.
854 SDValue SelectionDAGBuilder::getRoot() {
855 if (PendingLoads.empty())
856 return DAG.getRoot();
858 if (PendingLoads.size() == 1) {
859 SDValue Root = PendingLoads[0];
861 PendingLoads.clear();
865 // Otherwise, we have to make a token factor node.
866 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
867 &PendingLoads[0], PendingLoads.size());
868 PendingLoads.clear();
873 /// getControlRoot - Similar to getRoot, but instead of flushing all the
874 /// PendingLoad items, flush all the PendingExports items. It is necessary
875 /// to do this before emitting a terminator instruction.
877 SDValue SelectionDAGBuilder::getControlRoot() {
878 SDValue Root = DAG.getRoot();
880 if (PendingExports.empty())
883 // Turn all of the CopyToReg chains into one factored node.
884 if (Root.getOpcode() != ISD::EntryToken) {
885 unsigned i = 0, e = PendingExports.size();
886 for (; i != e; ++i) {
887 assert(PendingExports[i].getNode()->getNumOperands() > 1);
888 if (PendingExports[i].getNode()->getOperand(0) == Root)
889 break; // Don't add the root if we already indirectly depend on it.
893 PendingExports.push_back(Root);
896 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
898 PendingExports.size());
899 PendingExports.clear();
904 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
905 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
906 DAG.AssignOrdering(Node, SDNodeOrder);
908 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
909 AssignOrderingToNode(Node->getOperand(I).getNode());
912 void SelectionDAGBuilder::visit(const Instruction &I) {
913 // Set up outgoing PHI node register values before emitting the terminator.
914 if (isa<TerminatorInst>(&I))
915 HandlePHINodesInSuccessorBlocks(I.getParent());
917 CurDebugLoc = I.getDebugLoc();
919 visit(I.getOpcode(), I);
921 if (!isa<TerminatorInst>(&I) && !HasTailCall)
922 CopyToExportRegsIfNeeded(&I);
924 CurDebugLoc = DebugLoc();
927 void SelectionDAGBuilder::visitPHI(const PHINode &) {
928 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
931 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
932 // Note: this doesn't use InstVisitor, because it has to work with
933 // ConstantExpr's in addition to instructions.
935 default: llvm_unreachable("Unknown instruction type encountered!");
936 // Build the switch statement using the Instruction.def file.
937 #define HANDLE_INST(NUM, OPCODE, CLASS) \
938 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
939 #include "llvm/Instruction.def"
942 // Assign the ordering to the freshly created DAG nodes.
943 if (NodeMap.count(&I)) {
945 AssignOrderingToNode(getValue(&I).getNode());
949 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
950 // generate the debug data structures now that we've seen its definition.
951 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
953 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
955 const DbgValueInst *DI = DDI.getDI();
956 DebugLoc dl = DDI.getdl();
957 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
958 MDNode *Variable = DI->getVariable();
959 uint64_t Offset = DI->getOffset();
962 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
963 SDV = DAG.getDbgValue(Variable, Val.getNode(),
964 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
965 DAG.AddDbgValue(SDV, Val.getNode(), false);
968 DEBUG(dbgs() << "Dropping debug info for " << DI);
969 DanglingDebugInfoMap[V] = DanglingDebugInfo();
973 /// getValue - Return an SDValue for the given Value.
974 SDValue SelectionDAGBuilder::getValue(const Value *V) {
975 // If we already have an SDValue for this value, use it. It's important
976 // to do this first, so that we don't create a CopyFromReg if we already
977 // have a regular SDValue.
978 SDValue &N = NodeMap[V];
979 if (N.getNode()) return N;
981 // If there's a virtual register allocated and initialized for this
983 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
984 if (It != FuncInfo.ValueMap.end()) {
985 unsigned InReg = It->second;
986 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
987 SDValue Chain = DAG.getEntryNode();
988 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
989 resolveDanglingDebugInfo(V, N);
993 // Otherwise create a new SDValue and remember it.
994 SDValue Val = getValueImpl(V);
996 resolveDanglingDebugInfo(V, Val);
1000 /// getNonRegisterValue - Return an SDValue for the given Value, but
1001 /// don't look in FuncInfo.ValueMap for a virtual register.
1002 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1003 // If we already have an SDValue for this value, use it.
1004 SDValue &N = NodeMap[V];
1005 if (N.getNode()) return N;
1007 // Otherwise create a new SDValue and remember it.
1008 SDValue Val = getValueImpl(V);
1010 resolveDanglingDebugInfo(V, Val);
1014 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1015 /// Create an SDValue for the given value.
1016 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1017 if (const Constant *C = dyn_cast<Constant>(V)) {
1018 EVT VT = TLI.getValueType(V->getType(), true);
1020 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1021 return DAG.getConstant(*CI, VT);
1023 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1024 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1026 if (isa<ConstantPointerNull>(C))
1027 return DAG.getConstant(0, TLI.getPointerTy());
1029 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1030 return DAG.getConstantFP(*CFP, VT);
1032 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1033 return DAG.getUNDEF(VT);
1035 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1036 visit(CE->getOpcode(), *CE);
1037 SDValue N1 = NodeMap[V];
1038 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1042 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1043 SmallVector<SDValue, 4> Constants;
1044 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1046 SDNode *Val = getValue(*OI).getNode();
1047 // If the operand is an empty aggregate, there are no values.
1049 // Add each leaf value from the operand to the Constants list
1050 // to form a flattened list of all the values.
1051 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1052 Constants.push_back(SDValue(Val, i));
1055 return DAG.getMergeValues(&Constants[0], Constants.size(),
1059 if (const ConstantDataSequential *CDS =
1060 dyn_cast<ConstantDataSequential>(C)) {
1061 SmallVector<SDValue, 4> Ops;
1062 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1063 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1064 // Add each leaf value from the operand to the Constants list
1065 // to form a flattened list of all the values.
1066 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1067 Ops.push_back(SDValue(Val, i));
1070 if (isa<ArrayType>(CDS->getType()))
1071 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1072 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1073 VT, &Ops[0], Ops.size());
1076 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1077 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1078 "Unknown struct or array constant!");
1080 SmallVector<EVT, 4> ValueVTs;
1081 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1082 unsigned NumElts = ValueVTs.size();
1084 return SDValue(); // empty struct
1085 SmallVector<SDValue, 4> Constants(NumElts);
1086 for (unsigned i = 0; i != NumElts; ++i) {
1087 EVT EltVT = ValueVTs[i];
1088 if (isa<UndefValue>(C))
1089 Constants[i] = DAG.getUNDEF(EltVT);
1090 else if (EltVT.isFloatingPoint())
1091 Constants[i] = DAG.getConstantFP(0, EltVT);
1093 Constants[i] = DAG.getConstant(0, EltVT);
1096 return DAG.getMergeValues(&Constants[0], NumElts,
1100 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1101 return DAG.getBlockAddress(BA, VT);
1103 VectorType *VecTy = cast<VectorType>(V->getType());
1104 unsigned NumElements = VecTy->getNumElements();
1106 // Now that we know the number and type of the elements, get that number of
1107 // elements into the Ops array based on what kind of constant it is.
1108 SmallVector<SDValue, 16> Ops;
1109 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1110 for (unsigned i = 0; i != NumElements; ++i)
1111 Ops.push_back(getValue(CV->getOperand(i)));
1113 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1114 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1117 if (EltVT.isFloatingPoint())
1118 Op = DAG.getConstantFP(0, EltVT);
1120 Op = DAG.getConstant(0, EltVT);
1121 Ops.assign(NumElements, Op);
1124 // Create a BUILD_VECTOR node.
1125 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1126 VT, &Ops[0], Ops.size());
1129 // If this is a static alloca, generate it as the frameindex instead of
1131 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1132 DenseMap<const AllocaInst*, int>::iterator SI =
1133 FuncInfo.StaticAllocaMap.find(AI);
1134 if (SI != FuncInfo.StaticAllocaMap.end())
1135 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1138 // If this is an instruction which fast-isel has deferred, select it now.
1139 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1140 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1141 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1142 SDValue Chain = DAG.getEntryNode();
1143 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1146 llvm_unreachable("Can't get register for value!");
1149 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1150 SDValue Chain = getControlRoot();
1151 SmallVector<ISD::OutputArg, 8> Outs;
1152 SmallVector<SDValue, 8> OutVals;
1154 if (!FuncInfo.CanLowerReturn) {
1155 unsigned DemoteReg = FuncInfo.DemoteRegister;
1156 const Function *F = I.getParent()->getParent();
1158 // Emit a store of the return value through the virtual register.
1159 // Leave Outs empty so that LowerReturn won't try to load return
1160 // registers the usual way.
1161 SmallVector<EVT, 1> PtrValueVTs;
1162 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1165 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1166 SDValue RetOp = getValue(I.getOperand(0));
1168 SmallVector<EVT, 4> ValueVTs;
1169 SmallVector<uint64_t, 4> Offsets;
1170 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1171 unsigned NumValues = ValueVTs.size();
1173 SmallVector<SDValue, 4> Chains(NumValues);
1174 for (unsigned i = 0; i != NumValues; ++i) {
1175 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1176 RetPtr.getValueType(), RetPtr,
1177 DAG.getIntPtrConstant(Offsets[i]));
1179 DAG.getStore(Chain, getCurDebugLoc(),
1180 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1181 // FIXME: better loc info would be nice.
1182 Add, MachinePointerInfo(), false, false, 0);
1185 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1186 MVT::Other, &Chains[0], NumValues);
1187 } else if (I.getNumOperands() != 0) {
1188 SmallVector<EVT, 4> ValueVTs;
1189 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1190 unsigned NumValues = ValueVTs.size();
1192 SDValue RetOp = getValue(I.getOperand(0));
1193 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1194 EVT VT = ValueVTs[j];
1196 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1198 const Function *F = I.getParent()->getParent();
1199 if (F->paramHasAttr(0, Attribute::SExt))
1200 ExtendKind = ISD::SIGN_EXTEND;
1201 else if (F->paramHasAttr(0, Attribute::ZExt))
1202 ExtendKind = ISD::ZERO_EXTEND;
1204 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1205 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1207 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1208 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1209 SmallVector<SDValue, 4> Parts(NumParts);
1210 getCopyToParts(DAG, getCurDebugLoc(),
1211 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1212 &Parts[0], NumParts, PartVT, ExtendKind);
1214 // 'inreg' on function refers to return value
1215 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1216 if (F->paramHasAttr(0, Attribute::InReg))
1219 // Propagate extension type if any
1220 if (ExtendKind == ISD::SIGN_EXTEND)
1222 else if (ExtendKind == ISD::ZERO_EXTEND)
1225 for (unsigned i = 0; i < NumParts; ++i) {
1226 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1228 OutVals.push_back(Parts[i]);
1234 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1235 CallingConv::ID CallConv =
1236 DAG.getMachineFunction().getFunction()->getCallingConv();
1237 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1238 Outs, OutVals, getCurDebugLoc(), DAG);
1240 // Verify that the target's LowerReturn behaved as expected.
1241 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1242 "LowerReturn didn't return a valid chain!");
1244 // Update the DAG with the new chain value resulting from return lowering.
1248 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1249 /// created for it, emit nodes to copy the value into the virtual
1251 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1253 if (V->getType()->isEmptyTy())
1256 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1257 if (VMI != FuncInfo.ValueMap.end()) {
1258 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1259 CopyValueToVirtualRegister(V, VMI->second);
1263 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1264 /// the current basic block, add it to ValueMap now so that we'll get a
1266 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1267 // No need to export constants.
1268 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1270 // Already exported?
1271 if (FuncInfo.isExportedInst(V)) return;
1273 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1274 CopyValueToVirtualRegister(V, Reg);
1277 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1278 const BasicBlock *FromBB) {
1279 // The operands of the setcc have to be in this block. We don't know
1280 // how to export them from some other block.
1281 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1282 // Can export from current BB.
1283 if (VI->getParent() == FromBB)
1286 // Is already exported, noop.
1287 return FuncInfo.isExportedInst(V);
1290 // If this is an argument, we can export it if the BB is the entry block or
1291 // if it is already exported.
1292 if (isa<Argument>(V)) {
1293 if (FromBB == &FromBB->getParent()->getEntryBlock())
1296 // Otherwise, can only export this if it is already exported.
1297 return FuncInfo.isExportedInst(V);
1300 // Otherwise, constants can always be exported.
1304 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1305 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1306 const MachineBasicBlock *Dst) const {
1307 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1310 const BasicBlock *SrcBB = Src->getBasicBlock();
1311 const BasicBlock *DstBB = Dst->getBasicBlock();
1312 return BPI->getEdgeWeight(SrcBB, DstBB);
1315 void SelectionDAGBuilder::
1316 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1317 uint32_t Weight /* = 0 */) {
1319 Weight = getEdgeWeight(Src, Dst);
1320 Src->addSuccessor(Dst, Weight);
1324 static bool InBlock(const Value *V, const BasicBlock *BB) {
1325 if (const Instruction *I = dyn_cast<Instruction>(V))
1326 return I->getParent() == BB;
1330 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1331 /// This function emits a branch and is used at the leaves of an OR or an
1332 /// AND operator tree.
1335 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1336 MachineBasicBlock *TBB,
1337 MachineBasicBlock *FBB,
1338 MachineBasicBlock *CurBB,
1339 MachineBasicBlock *SwitchBB) {
1340 const BasicBlock *BB = CurBB->getBasicBlock();
1342 // If the leaf of the tree is a comparison, merge the condition into
1344 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1345 // The operands of the cmp have to be in this block. We don't know
1346 // how to export them from some other block. If this is the first block
1347 // of the sequence, no exporting is needed.
1348 if (CurBB == SwitchBB ||
1349 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1350 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1351 ISD::CondCode Condition;
1352 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1353 Condition = getICmpCondCode(IC->getPredicate());
1354 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1355 Condition = getFCmpCondCode(FC->getPredicate());
1356 if (TM.Options.NoNaNsFPMath)
1357 Condition = getFCmpCodeWithoutNaN(Condition);
1359 Condition = ISD::SETEQ; // silence warning.
1360 llvm_unreachable("Unknown compare instruction");
1363 CaseBlock CB(Condition, BOp->getOperand(0),
1364 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1365 SwitchCases.push_back(CB);
1370 // Create a CaseBlock record representing this branch.
1371 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1372 NULL, TBB, FBB, CurBB);
1373 SwitchCases.push_back(CB);
1376 /// FindMergedConditions - If Cond is an expression like
1377 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1378 MachineBasicBlock *TBB,
1379 MachineBasicBlock *FBB,
1380 MachineBasicBlock *CurBB,
1381 MachineBasicBlock *SwitchBB,
1383 // If this node is not part of the or/and tree, emit it as a branch.
1384 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1385 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1386 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1387 BOp->getParent() != CurBB->getBasicBlock() ||
1388 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1389 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1390 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1394 // Create TmpBB after CurBB.
1395 MachineFunction::iterator BBI = CurBB;
1396 MachineFunction &MF = DAG.getMachineFunction();
1397 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1398 CurBB->getParent()->insert(++BBI, TmpBB);
1400 if (Opc == Instruction::Or) {
1401 // Codegen X | Y as:
1409 // Emit the LHS condition.
1410 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1412 // Emit the RHS condition into TmpBB.
1413 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1415 assert(Opc == Instruction::And && "Unknown merge op!");
1416 // Codegen X & Y as:
1423 // This requires creation of TmpBB after CurBB.
1425 // Emit the LHS condition.
1426 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1428 // Emit the RHS condition into TmpBB.
1429 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1433 /// If the set of cases should be emitted as a series of branches, return true.
1434 /// If we should emit this as a bunch of and/or'd together conditions, return
1437 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1438 if (Cases.size() != 2) return true;
1440 // If this is two comparisons of the same values or'd or and'd together, they
1441 // will get folded into a single comparison, so don't emit two blocks.
1442 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1443 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1444 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1445 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1449 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1450 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1451 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1452 Cases[0].CC == Cases[1].CC &&
1453 isa<Constant>(Cases[0].CmpRHS) &&
1454 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1455 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1457 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1464 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1465 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1467 // Update machine-CFG edges.
1468 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1470 // Figure out which block is immediately after the current one.
1471 MachineBasicBlock *NextBlock = 0;
1472 MachineFunction::iterator BBI = BrMBB;
1473 if (++BBI != FuncInfo.MF->end())
1476 if (I.isUnconditional()) {
1477 // Update machine-CFG edges.
1478 BrMBB->addSuccessor(Succ0MBB);
1480 // If this is not a fall-through branch, emit the branch.
1481 if (Succ0MBB != NextBlock)
1482 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1483 MVT::Other, getControlRoot(),
1484 DAG.getBasicBlock(Succ0MBB)));
1489 // If this condition is one of the special cases we handle, do special stuff
1491 const Value *CondVal = I.getCondition();
1492 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1494 // If this is a series of conditions that are or'd or and'd together, emit
1495 // this as a sequence of branches instead of setcc's with and/or operations.
1496 // As long as jumps are not expensive, this should improve performance.
1497 // For example, instead of something like:
1510 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1511 if (!TLI.isJumpExpensive() &&
1513 (BOp->getOpcode() == Instruction::And ||
1514 BOp->getOpcode() == Instruction::Or)) {
1515 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1517 // If the compares in later blocks need to use values not currently
1518 // exported from this block, export them now. This block should always
1519 // be the first entry.
1520 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1522 // Allow some cases to be rejected.
1523 if (ShouldEmitAsBranches(SwitchCases)) {
1524 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1525 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1526 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1529 // Emit the branch for this block.
1530 visitSwitchCase(SwitchCases[0], BrMBB);
1531 SwitchCases.erase(SwitchCases.begin());
1535 // Okay, we decided not to do this, remove any inserted MBB's and clear
1537 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1538 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1540 SwitchCases.clear();
1544 // Create a CaseBlock record representing this branch.
1545 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1546 NULL, Succ0MBB, Succ1MBB, BrMBB);
1548 // Use visitSwitchCase to actually insert the fast branch sequence for this
1550 visitSwitchCase(CB, BrMBB);
1553 /// visitSwitchCase - Emits the necessary code to represent a single node in
1554 /// the binary search tree resulting from lowering a switch instruction.
1555 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1556 MachineBasicBlock *SwitchBB) {
1558 SDValue CondLHS = getValue(CB.CmpLHS);
1559 DebugLoc dl = getCurDebugLoc();
1561 // Build the setcc now.
1562 if (CB.CmpMHS == NULL) {
1563 // Fold "(X == true)" to X and "(X == false)" to !X to
1564 // handle common cases produced by branch lowering.
1565 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1566 CB.CC == ISD::SETEQ)
1568 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1569 CB.CC == ISD::SETEQ) {
1570 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1571 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1573 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1575 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1577 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1578 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1580 SDValue CmpOp = getValue(CB.CmpMHS);
1581 EVT VT = CmpOp.getValueType();
1583 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1584 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1587 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1588 VT, CmpOp, DAG.getConstant(Low, VT));
1589 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1590 DAG.getConstant(High-Low, VT), ISD::SETULE);
1594 // Update successor info
1595 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1596 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1598 // Set NextBlock to be the MBB immediately after the current one, if any.
1599 // This is used to avoid emitting unnecessary branches to the next block.
1600 MachineBasicBlock *NextBlock = 0;
1601 MachineFunction::iterator BBI = SwitchBB;
1602 if (++BBI != FuncInfo.MF->end())
1605 // If the lhs block is the next block, invert the condition so that we can
1606 // fall through to the lhs instead of the rhs block.
1607 if (CB.TrueBB == NextBlock) {
1608 std::swap(CB.TrueBB, CB.FalseBB);
1609 SDValue True = DAG.getConstant(1, Cond.getValueType());
1610 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1613 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1614 MVT::Other, getControlRoot(), Cond,
1615 DAG.getBasicBlock(CB.TrueBB));
1617 // Insert the false branch. Do this even if it's a fall through branch,
1618 // this makes it easier to do DAG optimizations which require inverting
1619 // the branch condition.
1620 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1621 DAG.getBasicBlock(CB.FalseBB));
1623 DAG.setRoot(BrCond);
1626 /// visitJumpTable - Emit JumpTable node in the current MBB
1627 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1628 // Emit the code for the jump table
1629 assert(JT.Reg != -1U && "Should lower JT Header first!");
1630 EVT PTy = TLI.getPointerTy();
1631 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1633 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1634 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1635 MVT::Other, Index.getValue(1),
1637 DAG.setRoot(BrJumpTable);
1640 /// visitJumpTableHeader - This function emits necessary code to produce index
1641 /// in the JumpTable from switch case.
1642 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1643 JumpTableHeader &JTH,
1644 MachineBasicBlock *SwitchBB) {
1645 // Subtract the lowest switch case value from the value being switched on and
1646 // conditional branch to default mbb if the result is greater than the
1647 // difference between smallest and largest cases.
1648 SDValue SwitchOp = getValue(JTH.SValue);
1649 EVT VT = SwitchOp.getValueType();
1650 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1651 DAG.getConstant(JTH.First, VT));
1653 // The SDNode we just created, which holds the value being switched on minus
1654 // the smallest case value, needs to be copied to a virtual register so it
1655 // can be used as an index into the jump table in a subsequent basic block.
1656 // This value may be smaller or larger than the target's pointer type, and
1657 // therefore require extension or truncating.
1658 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1660 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1661 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1662 JumpTableReg, SwitchOp);
1663 JT.Reg = JumpTableReg;
1665 // Emit the range check for the jump table, and branch to the default block
1666 // for the switch statement if the value being switched on exceeds the largest
1667 // case in the switch.
1668 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1669 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1670 DAG.getConstant(JTH.Last-JTH.First,VT),
1673 // Set NextBlock to be the MBB immediately after the current one, if any.
1674 // This is used to avoid emitting unnecessary branches to the next block.
1675 MachineBasicBlock *NextBlock = 0;
1676 MachineFunction::iterator BBI = SwitchBB;
1678 if (++BBI != FuncInfo.MF->end())
1681 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1682 MVT::Other, CopyTo, CMP,
1683 DAG.getBasicBlock(JT.Default));
1685 if (JT.MBB != NextBlock)
1686 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1687 DAG.getBasicBlock(JT.MBB));
1689 DAG.setRoot(BrCond);
1692 /// visitBitTestHeader - This function emits necessary code to produce value
1693 /// suitable for "bit tests"
1694 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1695 MachineBasicBlock *SwitchBB) {
1696 // Subtract the minimum value
1697 SDValue SwitchOp = getValue(B.SValue);
1698 EVT VT = SwitchOp.getValueType();
1699 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1700 DAG.getConstant(B.First, VT));
1703 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1704 TLI.getSetCCResultType(Sub.getValueType()),
1705 Sub, DAG.getConstant(B.Range, VT),
1708 // Determine the type of the test operands.
1709 bool UsePtrType = false;
1710 if (!TLI.isTypeLegal(VT))
1713 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1714 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1715 // Switch table case range are encoded into series of masks.
1716 // Just use pointer type, it's guaranteed to fit.
1722 VT = TLI.getPointerTy();
1723 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1727 B.Reg = FuncInfo.CreateReg(VT);
1728 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1731 // Set NextBlock to be the MBB immediately after the current one, if any.
1732 // This is used to avoid emitting unnecessary branches to the next block.
1733 MachineBasicBlock *NextBlock = 0;
1734 MachineFunction::iterator BBI = SwitchBB;
1735 if (++BBI != FuncInfo.MF->end())
1738 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1740 addSuccessorWithWeight(SwitchBB, B.Default);
1741 addSuccessorWithWeight(SwitchBB, MBB);
1743 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1744 MVT::Other, CopyTo, RangeCmp,
1745 DAG.getBasicBlock(B.Default));
1747 if (MBB != NextBlock)
1748 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1749 DAG.getBasicBlock(MBB));
1751 DAG.setRoot(BrRange);
1754 /// visitBitTestCase - this function produces one "bit test"
1755 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1756 MachineBasicBlock* NextMBB,
1759 MachineBasicBlock *SwitchBB) {
1761 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1764 unsigned PopCount = CountPopulation_64(B.Mask);
1765 if (PopCount == 1) {
1766 // Testing for a single bit; just compare the shift count with what it
1767 // would need to be to shift a 1 bit in that position.
1768 Cmp = DAG.getSetCC(getCurDebugLoc(),
1769 TLI.getSetCCResultType(VT),
1771 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1773 } else if (PopCount == BB.Range) {
1774 // There is only one zero bit in the range, test for it directly.
1775 Cmp = DAG.getSetCC(getCurDebugLoc(),
1776 TLI.getSetCCResultType(VT),
1778 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1781 // Make desired shift
1782 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1783 DAG.getConstant(1, VT), ShiftOp);
1785 // Emit bit tests and jumps
1786 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1787 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1788 Cmp = DAG.getSetCC(getCurDebugLoc(),
1789 TLI.getSetCCResultType(VT),
1790 AndOp, DAG.getConstant(0, VT),
1794 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1795 addSuccessorWithWeight(SwitchBB, NextMBB);
1797 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1798 MVT::Other, getControlRoot(),
1799 Cmp, DAG.getBasicBlock(B.TargetBB));
1801 // Set NextBlock to be the MBB immediately after the current one, if any.
1802 // This is used to avoid emitting unnecessary branches to the next block.
1803 MachineBasicBlock *NextBlock = 0;
1804 MachineFunction::iterator BBI = SwitchBB;
1805 if (++BBI != FuncInfo.MF->end())
1808 if (NextMBB != NextBlock)
1809 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1810 DAG.getBasicBlock(NextMBB));
1815 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1816 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1818 // Retrieve successors.
1819 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1820 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1822 const Value *Callee(I.getCalledValue());
1823 if (isa<InlineAsm>(Callee))
1826 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1828 // If the value of the invoke is used outside of its defining block, make it
1829 // available as a virtual register.
1830 CopyToExportRegsIfNeeded(&I);
1832 // Update successor info
1833 addSuccessorWithWeight(InvokeMBB, Return);
1834 addSuccessorWithWeight(InvokeMBB, LandingPad);
1836 // Drop into normal successor.
1837 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1838 MVT::Other, getControlRoot(),
1839 DAG.getBasicBlock(Return)));
1842 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) {
1845 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1846 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1849 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1850 assert(FuncInfo.MBB->isLandingPad() &&
1851 "Call to landingpad not in landing pad!");
1853 MachineBasicBlock *MBB = FuncInfo.MBB;
1854 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1855 AddLandingPadInfo(LP, MMI, MBB);
1857 SmallVector<EVT, 2> ValueVTs;
1858 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1860 // Insert the EXCEPTIONADDR instruction.
1861 assert(FuncInfo.MBB->isLandingPad() &&
1862 "Call to eh.exception not in landing pad!");
1863 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1865 Ops[0] = DAG.getRoot();
1866 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1867 SDValue Chain = Op1.getValue(1);
1869 // Insert the EHSELECTION instruction.
1870 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1873 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1874 Chain = Op2.getValue(1);
1875 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1879 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1880 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1883 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1884 setValue(&LP, RetPair.first);
1885 DAG.setRoot(RetPair.second);
1888 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1889 /// small case ranges).
1890 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1891 CaseRecVector& WorkList,
1893 MachineBasicBlock *Default,
1894 MachineBasicBlock *SwitchBB) {
1895 Case& BackCase = *(CR.Range.second-1);
1897 // Size is the number of Cases represented by this range.
1898 size_t Size = CR.Range.second - CR.Range.first;
1902 // Get the MachineFunction which holds the current MBB. This is used when
1903 // inserting any additional MBBs necessary to represent the switch.
1904 MachineFunction *CurMF = FuncInfo.MF;
1906 // Figure out which block is immediately after the current one.
1907 MachineBasicBlock *NextBlock = 0;
1908 MachineFunction::iterator BBI = CR.CaseBB;
1910 if (++BBI != FuncInfo.MF->end())
1913 // If any two of the cases has the same destination, and if one value
1914 // is the same as the other, but has one bit unset that the other has set,
1915 // use bit manipulation to do two compares at once. For example:
1916 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1917 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1918 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1919 if (Size == 2 && CR.CaseBB == SwitchBB) {
1920 Case &Small = *CR.Range.first;
1921 Case &Big = *(CR.Range.second-1);
1923 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1924 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1925 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1927 // Check that there is only one bit different.
1928 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1929 (SmallValue | BigValue) == BigValue) {
1930 // Isolate the common bit.
1931 APInt CommonBit = BigValue & ~SmallValue;
1932 assert((SmallValue | CommonBit) == BigValue &&
1933 CommonBit.countPopulation() == 1 && "Not a common bit?");
1935 SDValue CondLHS = getValue(SV);
1936 EVT VT = CondLHS.getValueType();
1937 DebugLoc DL = getCurDebugLoc();
1939 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1940 DAG.getConstant(CommonBit, VT));
1941 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1942 Or, DAG.getConstant(BigValue, VT),
1945 // Update successor info.
1946 addSuccessorWithWeight(SwitchBB, Small.BB);
1947 addSuccessorWithWeight(SwitchBB, Default);
1949 // Insert the true branch.
1950 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1951 getControlRoot(), Cond,
1952 DAG.getBasicBlock(Small.BB));
1954 // Insert the false branch.
1955 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1956 DAG.getBasicBlock(Default));
1958 DAG.setRoot(BrCond);
1964 // Rearrange the case blocks so that the last one falls through if possible.
1965 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1966 // The last case block won't fall through into 'NextBlock' if we emit the
1967 // branches in this order. See if rearranging a case value would help.
1968 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1969 if (I->BB == NextBlock) {
1970 std::swap(*I, BackCase);
1976 // Create a CaseBlock record representing a conditional branch to
1977 // the Case's target mbb if the value being switched on SV is equal
1979 MachineBasicBlock *CurBlock = CR.CaseBB;
1980 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1981 MachineBasicBlock *FallThrough;
1983 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1984 CurMF->insert(BBI, FallThrough);
1986 // Put SV in a virtual register to make it available from the new blocks.
1987 ExportFromCurrentBlock(SV);
1989 // If the last case doesn't match, go to the default block.
1990 FallThrough = Default;
1993 const Value *RHS, *LHS, *MHS;
1995 if (I->High == I->Low) {
1996 // This is just small small case range :) containing exactly 1 case
1998 LHS = SV; RHS = I->High; MHS = NULL;
2001 LHS = I->Low; MHS = SV; RHS = I->High;
2004 uint32_t ExtraWeight = I->ExtraWeight;
2005 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2007 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
2009 // If emitting the first comparison, just call visitSwitchCase to emit the
2010 // code into the current block. Otherwise, push the CaseBlock onto the
2011 // vector to be later processed by SDISel, and insert the node's MBB
2012 // before the next MBB.
2013 if (CurBlock == SwitchBB)
2014 visitSwitchCase(CB, SwitchBB);
2016 SwitchCases.push_back(CB);
2018 CurBlock = FallThrough;
2024 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2025 return !TLI.getTargetMachine().Options.DisableJumpTables &&
2026 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2027 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2030 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2031 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2032 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2033 return (LastExt - FirstExt + 1ULL);
2036 /// handleJTSwitchCase - Emit jumptable for current switch case range
2037 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2038 CaseRecVector &WorkList,
2040 MachineBasicBlock *Default,
2041 MachineBasicBlock *SwitchBB) {
2042 Case& FrontCase = *CR.Range.first;
2043 Case& BackCase = *(CR.Range.second-1);
2045 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2046 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2048 APInt TSize(First.getBitWidth(), 0);
2049 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2052 if (!areJTsAllowed(TLI) || TSize.ult(4))
2055 APInt Range = ComputeRange(First, Last);
2056 // The density is TSize / Range. Require at least 40%.
2057 // It should not be possible for IntTSize to saturate for sane code, but make
2058 // sure we handle Range saturation correctly.
2059 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2060 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2061 if (IntTSize * 10 < IntRange * 4)
2064 DEBUG(dbgs() << "Lowering jump table\n"
2065 << "First entry: " << First << ". Last entry: " << Last << '\n'
2066 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2068 // Get the MachineFunction which holds the current MBB. This is used when
2069 // inserting any additional MBBs necessary to represent the switch.
2070 MachineFunction *CurMF = FuncInfo.MF;
2072 // Figure out which block is immediately after the current one.
2073 MachineFunction::iterator BBI = CR.CaseBB;
2076 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2078 // Create a new basic block to hold the code for loading the address
2079 // of the jump table, and jumping to it. Update successor information;
2080 // we will either branch to the default case for the switch, or the jump
2082 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2083 CurMF->insert(BBI, JumpTableBB);
2085 addSuccessorWithWeight(CR.CaseBB, Default);
2086 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2088 // Build a vector of destination BBs, corresponding to each target
2089 // of the jump table. If the value of the jump table slot corresponds to
2090 // a case statement, push the case's BB onto the vector, otherwise, push
2092 std::vector<MachineBasicBlock*> DestBBs;
2094 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2095 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2096 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2098 if (Low.sle(TEI) && TEI.sle(High)) {
2099 DestBBs.push_back(I->BB);
2103 DestBBs.push_back(Default);
2107 // Update successor info. Add one edge to each unique successor.
2108 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2109 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2110 E = DestBBs.end(); I != E; ++I) {
2111 if (!SuccsHandled[(*I)->getNumber()]) {
2112 SuccsHandled[(*I)->getNumber()] = true;
2113 addSuccessorWithWeight(JumpTableBB, *I);
2117 // Create a jump table index for this jump table.
2118 unsigned JTEncoding = TLI.getJumpTableEncoding();
2119 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2120 ->createJumpTableIndex(DestBBs);
2122 // Set the jump table information so that we can codegen it as a second
2123 // MachineBasicBlock
2124 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2125 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2126 if (CR.CaseBB == SwitchBB)
2127 visitJumpTableHeader(JT, JTH, SwitchBB);
2129 JTCases.push_back(JumpTableBlock(JTH, JT));
2133 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2135 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2136 CaseRecVector& WorkList,
2138 MachineBasicBlock *Default,
2139 MachineBasicBlock *SwitchBB) {
2140 // Get the MachineFunction which holds the current MBB. This is used when
2141 // inserting any additional MBBs necessary to represent the switch.
2142 MachineFunction *CurMF = FuncInfo.MF;
2144 // Figure out which block is immediately after the current one.
2145 MachineFunction::iterator BBI = CR.CaseBB;
2148 Case& FrontCase = *CR.Range.first;
2149 Case& BackCase = *(CR.Range.second-1);
2150 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2152 // Size is the number of Cases represented by this range.
2153 unsigned Size = CR.Range.second - CR.Range.first;
2155 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2156 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2158 CaseItr Pivot = CR.Range.first + Size/2;
2160 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2161 // (heuristically) allow us to emit JumpTable's later.
2162 APInt TSize(First.getBitWidth(), 0);
2163 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2167 APInt LSize = FrontCase.size();
2168 APInt RSize = TSize-LSize;
2169 DEBUG(dbgs() << "Selecting best pivot: \n"
2170 << "First: " << First << ", Last: " << Last <<'\n'
2171 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2172 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2174 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2175 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2176 APInt Range = ComputeRange(LEnd, RBegin);
2177 assert((Range - 2ULL).isNonNegative() &&
2178 "Invalid case distance");
2179 // Use volatile double here to avoid excess precision issues on some hosts,
2180 // e.g. that use 80-bit X87 registers.
2181 volatile double LDensity =
2182 (double)LSize.roundToDouble() /
2183 (LEnd - First + 1ULL).roundToDouble();
2184 volatile double RDensity =
2185 (double)RSize.roundToDouble() /
2186 (Last - RBegin + 1ULL).roundToDouble();
2187 double Metric = Range.logBase2()*(LDensity+RDensity);
2188 // Should always split in some non-trivial place
2189 DEBUG(dbgs() <<"=>Step\n"
2190 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2191 << "LDensity: " << LDensity
2192 << ", RDensity: " << RDensity << '\n'
2193 << "Metric: " << Metric << '\n');
2194 if (FMetric < Metric) {
2197 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2203 if (areJTsAllowed(TLI)) {
2204 // If our case is dense we *really* should handle it earlier!
2205 assert((FMetric > 0) && "Should handle dense range earlier!");
2207 Pivot = CR.Range.first + Size/2;
2210 CaseRange LHSR(CR.Range.first, Pivot);
2211 CaseRange RHSR(Pivot, CR.Range.second);
2212 const Constant *C = Pivot->Low;
2213 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2215 // We know that we branch to the LHS if the Value being switched on is
2216 // less than the Pivot value, C. We use this to optimize our binary
2217 // tree a bit, by recognizing that if SV is greater than or equal to the
2218 // LHS's Case Value, and that Case Value is exactly one less than the
2219 // Pivot's Value, then we can branch directly to the LHS's Target,
2220 // rather than creating a leaf node for it.
2221 if ((LHSR.second - LHSR.first) == 1 &&
2222 LHSR.first->High == CR.GE &&
2223 cast<ConstantInt>(C)->getValue() ==
2224 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2225 TrueBB = LHSR.first->BB;
2227 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2228 CurMF->insert(BBI, TrueBB);
2229 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2231 // Put SV in a virtual register to make it available from the new blocks.
2232 ExportFromCurrentBlock(SV);
2235 // Similar to the optimization above, if the Value being switched on is
2236 // known to be less than the Constant CR.LT, and the current Case Value
2237 // is CR.LT - 1, then we can branch directly to the target block for
2238 // the current Case Value, rather than emitting a RHS leaf node for it.
2239 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2240 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2241 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2242 FalseBB = RHSR.first->BB;
2244 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2245 CurMF->insert(BBI, FalseBB);
2246 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2248 // Put SV in a virtual register to make it available from the new blocks.
2249 ExportFromCurrentBlock(SV);
2252 // Create a CaseBlock record representing a conditional branch to
2253 // the LHS node if the value being switched on SV is less than C.
2254 // Otherwise, branch to LHS.
2255 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2257 if (CR.CaseBB == SwitchBB)
2258 visitSwitchCase(CB, SwitchBB);
2260 SwitchCases.push_back(CB);
2265 /// handleBitTestsSwitchCase - if current case range has few destination and
2266 /// range span less, than machine word bitwidth, encode case range into series
2267 /// of masks and emit bit tests with these masks.
2268 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2269 CaseRecVector& WorkList,
2271 MachineBasicBlock* Default,
2272 MachineBasicBlock *SwitchBB){
2273 EVT PTy = TLI.getPointerTy();
2274 unsigned IntPtrBits = PTy.getSizeInBits();
2276 Case& FrontCase = *CR.Range.first;
2277 Case& BackCase = *(CR.Range.second-1);
2279 // Get the MachineFunction which holds the current MBB. This is used when
2280 // inserting any additional MBBs necessary to represent the switch.
2281 MachineFunction *CurMF = FuncInfo.MF;
2283 // If target does not have legal shift left, do not emit bit tests at all.
2284 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2288 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2290 // Single case counts one, case range - two.
2291 numCmps += (I->Low == I->High ? 1 : 2);
2294 // Count unique destinations
2295 SmallSet<MachineBasicBlock*, 4> Dests;
2296 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2297 Dests.insert(I->BB);
2298 if (Dests.size() > 3)
2299 // Don't bother the code below, if there are too much unique destinations
2302 DEBUG(dbgs() << "Total number of unique destinations: "
2303 << Dests.size() << '\n'
2304 << "Total number of comparisons: " << numCmps << '\n');
2306 // Compute span of values.
2307 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2308 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2309 APInt cmpRange = maxValue - minValue;
2311 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2312 << "Low bound: " << minValue << '\n'
2313 << "High bound: " << maxValue << '\n');
2315 if (cmpRange.uge(IntPtrBits) ||
2316 (!(Dests.size() == 1 && numCmps >= 3) &&
2317 !(Dests.size() == 2 && numCmps >= 5) &&
2318 !(Dests.size() >= 3 && numCmps >= 6)))
2321 DEBUG(dbgs() << "Emitting bit tests\n");
2322 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2324 // Optimize the case where all the case values fit in a
2325 // word without having to subtract minValue. In this case,
2326 // we can optimize away the subtraction.
2327 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2328 cmpRange = maxValue;
2330 lowBound = minValue;
2333 CaseBitsVector CasesBits;
2334 unsigned i, count = 0;
2336 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2337 MachineBasicBlock* Dest = I->BB;
2338 for (i = 0; i < count; ++i)
2339 if (Dest == CasesBits[i].BB)
2343 assert((count < 3) && "Too much destinations to test!");
2344 CasesBits.push_back(CaseBits(0, Dest, 0));
2348 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2349 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2351 uint64_t lo = (lowValue - lowBound).getZExtValue();
2352 uint64_t hi = (highValue - lowBound).getZExtValue();
2354 for (uint64_t j = lo; j <= hi; j++) {
2355 CasesBits[i].Mask |= 1ULL << j;
2356 CasesBits[i].Bits++;
2360 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2364 // Figure out which block is immediately after the current one.
2365 MachineFunction::iterator BBI = CR.CaseBB;
2368 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2370 DEBUG(dbgs() << "Cases:\n");
2371 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2372 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2373 << ", Bits: " << CasesBits[i].Bits
2374 << ", BB: " << CasesBits[i].BB << '\n');
2376 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2377 CurMF->insert(BBI, CaseBB);
2378 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2382 // Put SV in a virtual register to make it available from the new blocks.
2383 ExportFromCurrentBlock(SV);
2386 BitTestBlock BTB(lowBound, cmpRange, SV,
2387 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2388 CR.CaseBB, Default, BTC);
2390 if (CR.CaseBB == SwitchBB)
2391 visitBitTestHeader(BTB, SwitchBB);
2393 BitTestCases.push_back(BTB);
2398 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2399 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2400 const SwitchInst& SI) {
2403 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2404 // Start with "simple" cases
2405 for (size_t i = 0; i < SI.getNumCases(); ++i) {
2406 BasicBlock *SuccBB = SI.getCaseSuccessor(i);
2407 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2409 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0;
2411 Cases.push_back(Case(SI.getCaseValue(i),
2413 SMBB, ExtraWeight));
2415 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2417 // Merge case into clusters
2418 if (Cases.size() >= 2)
2419 // Must recompute end() each iteration because it may be
2420 // invalidated by erase if we hold on to it
2421 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin());
2422 J != Cases.end(); ) {
2423 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2424 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2425 MachineBasicBlock* nextBB = J->BB;
2426 MachineBasicBlock* currentBB = I->BB;
2428 // If the two neighboring cases go to the same destination, merge them
2429 // into a single case.
2430 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2434 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) {
2435 uint32_t CurWeight = currentBB->getBasicBlock() ?
2436 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16;
2437 uint32_t NextWeight = nextBB->getBasicBlock() ?
2438 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16;
2440 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(),
2441 CurWeight + NextWeight);
2448 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2449 if (I->Low != I->High)
2450 // A range counts double, since it requires two compares.
2457 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2458 MachineBasicBlock *Last) {
2460 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2461 if (JTCases[i].first.HeaderBB == First)
2462 JTCases[i].first.HeaderBB = Last;
2464 // Update BitTestCases.
2465 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2466 if (BitTestCases[i].Parent == First)
2467 BitTestCases[i].Parent = Last;
2470 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2471 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2473 // Figure out which block is immediately after the current one.
2474 MachineBasicBlock *NextBlock = 0;
2475 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2477 // If there is only the default destination, branch to it if it is not the
2478 // next basic block. Otherwise, just fall through.
2479 if (!SI.getNumCases()) {
2480 // Update machine-CFG edges.
2482 // If this is not a fall-through branch, emit the branch.
2483 SwitchMBB->addSuccessor(Default);
2484 if (Default != NextBlock)
2485 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2486 MVT::Other, getControlRoot(),
2487 DAG.getBasicBlock(Default)));
2492 // If there are any non-default case statements, create a vector of Cases
2493 // representing each one, and sort the vector so that we can efficiently
2494 // create a binary search tree from them.
2496 size_t numCmps = Clusterify(Cases, SI);
2497 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2498 << ". Total compares: " << numCmps << '\n');
2501 // Get the Value to be switched on and default basic blocks, which will be
2502 // inserted into CaseBlock records, representing basic blocks in the binary
2504 const Value *SV = SI.getCondition();
2506 // Push the initial CaseRec onto the worklist
2507 CaseRecVector WorkList;
2508 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2509 CaseRange(Cases.begin(),Cases.end())));
2511 while (!WorkList.empty()) {
2512 // Grab a record representing a case range to process off the worklist
2513 CaseRec CR = WorkList.back();
2514 WorkList.pop_back();
2516 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2519 // If the range has few cases (two or less) emit a series of specific
2521 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2524 // If the switch has more than 5 blocks, and at least 40% dense, and the
2525 // target supports indirect branches, then emit a jump table rather than
2526 // lowering the switch to a binary tree of conditional branches.
2527 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2530 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2531 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2532 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2536 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2537 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2539 // Update machine-CFG edges with unique successors.
2540 SmallVector<BasicBlock*, 32> succs;
2541 succs.reserve(I.getNumSuccessors());
2542 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2543 succs.push_back(I.getSuccessor(i));
2544 array_pod_sort(succs.begin(), succs.end());
2545 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2546 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2547 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2548 addSuccessorWithWeight(IndirectBrMBB, Succ);
2551 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2552 MVT::Other, getControlRoot(),
2553 getValue(I.getAddress())));
2556 void SelectionDAGBuilder::visitFSub(const User &I) {
2557 // -0.0 - X --> fneg
2558 Type *Ty = I.getType();
2559 if (isa<Constant>(I.getOperand(0)) &&
2560 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2561 SDValue Op2 = getValue(I.getOperand(1));
2562 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2563 Op2.getValueType(), Op2));
2567 visitBinary(I, ISD::FSUB);
2570 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2571 SDValue Op1 = getValue(I.getOperand(0));
2572 SDValue Op2 = getValue(I.getOperand(1));
2573 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2574 Op1.getValueType(), Op1, Op2));
2577 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2578 SDValue Op1 = getValue(I.getOperand(0));
2579 SDValue Op2 = getValue(I.getOperand(1));
2581 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2583 // Coerce the shift amount to the right type if we can.
2584 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2585 unsigned ShiftSize = ShiftTy.getSizeInBits();
2586 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2587 DebugLoc DL = getCurDebugLoc();
2589 // If the operand is smaller than the shift count type, promote it.
2590 if (ShiftSize > Op2Size)
2591 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2593 // If the operand is larger than the shift count type but the shift
2594 // count type has enough bits to represent any shift value, truncate
2595 // it now. This is a common case and it exposes the truncate to
2596 // optimization early.
2597 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2598 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2599 // Otherwise we'll need to temporarily settle for some other convenient
2600 // type. Type legalization will make adjustments once the shiftee is split.
2602 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2605 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2606 Op1.getValueType(), Op1, Op2));
2609 void SelectionDAGBuilder::visitSDiv(const User &I) {
2610 SDValue Op1 = getValue(I.getOperand(0));
2611 SDValue Op2 = getValue(I.getOperand(1));
2613 // Turn exact SDivs into multiplications.
2614 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2616 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2617 !isa<ConstantSDNode>(Op1) &&
2618 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2619 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2621 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2625 void SelectionDAGBuilder::visitICmp(const User &I) {
2626 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2627 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2628 predicate = IC->getPredicate();
2629 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2630 predicate = ICmpInst::Predicate(IC->getPredicate());
2631 SDValue Op1 = getValue(I.getOperand(0));
2632 SDValue Op2 = getValue(I.getOperand(1));
2633 ISD::CondCode Opcode = getICmpCondCode(predicate);
2635 EVT DestVT = TLI.getValueType(I.getType());
2636 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2639 void SelectionDAGBuilder::visitFCmp(const User &I) {
2640 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2641 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2642 predicate = FC->getPredicate();
2643 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2644 predicate = FCmpInst::Predicate(FC->getPredicate());
2645 SDValue Op1 = getValue(I.getOperand(0));
2646 SDValue Op2 = getValue(I.getOperand(1));
2647 ISD::CondCode Condition = getFCmpCondCode(predicate);
2648 if (TM.Options.NoNaNsFPMath)
2649 Condition = getFCmpCodeWithoutNaN(Condition);
2650 EVT DestVT = TLI.getValueType(I.getType());
2651 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2654 void SelectionDAGBuilder::visitSelect(const User &I) {
2655 SmallVector<EVT, 4> ValueVTs;
2656 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2657 unsigned NumValues = ValueVTs.size();
2658 if (NumValues == 0) return;
2660 SmallVector<SDValue, 4> Values(NumValues);
2661 SDValue Cond = getValue(I.getOperand(0));
2662 SDValue TrueVal = getValue(I.getOperand(1));
2663 SDValue FalseVal = getValue(I.getOperand(2));
2664 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2665 ISD::VSELECT : ISD::SELECT;
2667 for (unsigned i = 0; i != NumValues; ++i)
2668 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2669 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2671 SDValue(TrueVal.getNode(),
2672 TrueVal.getResNo() + i),
2673 SDValue(FalseVal.getNode(),
2674 FalseVal.getResNo() + i));
2676 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2677 DAG.getVTList(&ValueVTs[0], NumValues),
2678 &Values[0], NumValues));
2681 void SelectionDAGBuilder::visitTrunc(const User &I) {
2682 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2683 SDValue N = getValue(I.getOperand(0));
2684 EVT DestVT = TLI.getValueType(I.getType());
2685 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2688 void SelectionDAGBuilder::visitZExt(const User &I) {
2689 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2690 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2691 SDValue N = getValue(I.getOperand(0));
2692 EVT DestVT = TLI.getValueType(I.getType());
2693 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2696 void SelectionDAGBuilder::visitSExt(const User &I) {
2697 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2698 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2699 SDValue N = getValue(I.getOperand(0));
2700 EVT DestVT = TLI.getValueType(I.getType());
2701 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2704 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2705 // FPTrunc is never a no-op cast, no need to check
2706 SDValue N = getValue(I.getOperand(0));
2707 EVT DestVT = TLI.getValueType(I.getType());
2708 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2710 DAG.getTargetConstant(0, TLI.getPointerTy())));
2713 void SelectionDAGBuilder::visitFPExt(const User &I){
2714 // FPExt is never a no-op cast, no need to check
2715 SDValue N = getValue(I.getOperand(0));
2716 EVT DestVT = TLI.getValueType(I.getType());
2717 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2720 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2721 // FPToUI is never a no-op cast, no need to check
2722 SDValue N = getValue(I.getOperand(0));
2723 EVT DestVT = TLI.getValueType(I.getType());
2724 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2727 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2728 // FPToSI is never a no-op cast, no need to check
2729 SDValue N = getValue(I.getOperand(0));
2730 EVT DestVT = TLI.getValueType(I.getType());
2731 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2734 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2735 // UIToFP is never a no-op cast, no need to check
2736 SDValue N = getValue(I.getOperand(0));
2737 EVT DestVT = TLI.getValueType(I.getType());
2738 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2741 void SelectionDAGBuilder::visitSIToFP(const User &I){
2742 // SIToFP is never a no-op cast, no need to check
2743 SDValue N = getValue(I.getOperand(0));
2744 EVT DestVT = TLI.getValueType(I.getType());
2745 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2748 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2749 // What to do depends on the size of the integer and the size of the pointer.
2750 // We can either truncate, zero extend, or no-op, accordingly.
2751 SDValue N = getValue(I.getOperand(0));
2752 EVT DestVT = TLI.getValueType(I.getType());
2753 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2756 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2757 // What to do depends on the size of the integer and the size of the pointer.
2758 // We can either truncate, zero extend, or no-op, accordingly.
2759 SDValue N = getValue(I.getOperand(0));
2760 EVT DestVT = TLI.getValueType(I.getType());
2761 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2764 void SelectionDAGBuilder::visitBitCast(const User &I) {
2765 SDValue N = getValue(I.getOperand(0));
2766 EVT DestVT = TLI.getValueType(I.getType());
2768 // BitCast assures us that source and destination are the same size so this is
2769 // either a BITCAST or a no-op.
2770 if (DestVT != N.getValueType())
2771 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2772 DestVT, N)); // convert types.
2774 setValue(&I, N); // noop cast.
2777 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2778 SDValue InVec = getValue(I.getOperand(0));
2779 SDValue InVal = getValue(I.getOperand(1));
2780 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2782 getValue(I.getOperand(2)));
2783 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2784 TLI.getValueType(I.getType()),
2785 InVec, InVal, InIdx));
2788 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2789 SDValue InVec = getValue(I.getOperand(0));
2790 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2792 getValue(I.getOperand(1)));
2793 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2794 TLI.getValueType(I.getType()), InVec, InIdx));
2797 // Utility for visitShuffleVector - Return true if every element in Mask,
2798 // begining // from position Pos and ending in Pos+Size, falls within the
2799 // specified sequential range [L, L+Pos). or is undef.
2800 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2801 int Pos, int Size, int Low) {
2802 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2803 if (Mask[i] >= 0 && Mask[i] != Low)
2808 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2809 SDValue Src1 = getValue(I.getOperand(0));
2810 SDValue Src2 = getValue(I.getOperand(1));
2812 SmallVector<int, 8> Mask;
2813 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2814 unsigned MaskNumElts = Mask.size();
2816 EVT VT = TLI.getValueType(I.getType());
2817 EVT SrcVT = Src1.getValueType();
2818 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2820 if (SrcNumElts == MaskNumElts) {
2821 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2826 // Normalize the shuffle vector since mask and vector length don't match.
2827 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2828 // Mask is longer than the source vectors and is a multiple of the source
2829 // vectors. We can use concatenate vector to make the mask and vectors
2831 if (SrcNumElts*2 == MaskNumElts) {
2832 // First check for Src1 in low and Src2 in high
2833 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2834 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2835 // The shuffle is concatenating two vectors together.
2836 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2840 // Then check for Src2 in low and Src1 in high
2841 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2842 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2843 // The shuffle is concatenating two vectors together.
2844 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2850 // Pad both vectors with undefs to make them the same length as the mask.
2851 unsigned NumConcat = MaskNumElts / SrcNumElts;
2852 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2853 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2854 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2856 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2857 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2861 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2862 getCurDebugLoc(), VT,
2863 &MOps1[0], NumConcat);
2864 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2865 getCurDebugLoc(), VT,
2866 &MOps2[0], NumConcat);
2868 // Readjust mask for new input vector length.
2869 SmallVector<int, 8> MappedOps;
2870 for (unsigned i = 0; i != MaskNumElts; ++i) {
2872 if (Idx < (int)SrcNumElts)
2873 MappedOps.push_back(Idx);
2875 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts);
2878 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2883 if (SrcNumElts > MaskNumElts) {
2884 // Analyze the access pattern of the vector to see if we can extract
2885 // two subvectors and do the shuffle. The analysis is done by calculating
2886 // the range of elements the mask access on both vectors.
2887 int MinRange[2] = { static_cast<int>(SrcNumElts+1),
2888 static_cast<int>(SrcNumElts+1)};
2889 int MaxRange[2] = {-1, -1};
2891 for (unsigned i = 0; i != MaskNumElts; ++i) {
2897 if (Idx >= (int)SrcNumElts) {
2901 if (Idx > MaxRange[Input])
2902 MaxRange[Input] = Idx;
2903 if (Idx < MinRange[Input])
2904 MinRange[Input] = Idx;
2907 // Check if the access is smaller than the vector size and can we find
2908 // a reasonable extract index.
2909 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not
2911 int StartIdx[2]; // StartIdx to extract from
2912 for (int Input=0; Input < 2; ++Input) {
2913 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) {
2914 RangeUse[Input] = 0; // Unused
2915 StartIdx[Input] = 0;
2916 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) {
2917 // Fits within range but we should see if we can find a good
2918 // start index that is a multiple of the mask length.
2919 if (MaxRange[Input] < (int)MaskNumElts) {
2920 RangeUse[Input] = 1; // Extract from beginning of the vector
2921 StartIdx[Input] = 0;
2923 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2924 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2925 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2926 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2931 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2932 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2935 else if (RangeUse[0] < 2 && RangeUse[1] < 2) {
2936 // Extract appropriate subvector and generate a vector shuffle
2937 for (int Input=0; Input < 2; ++Input) {
2938 SDValue &Src = Input == 0 ? Src1 : Src2;
2939 if (RangeUse[Input] == 0)
2940 Src = DAG.getUNDEF(VT);
2942 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2943 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2946 // Calculate new mask.
2947 SmallVector<int, 8> MappedOps;
2948 for (unsigned i = 0; i != MaskNumElts; ++i) {
2951 MappedOps.push_back(Idx);
2952 else if (Idx < (int)SrcNumElts)
2953 MappedOps.push_back(Idx - StartIdx[0]);
2955 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts);
2958 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2964 // We can't use either concat vectors or extract subvectors so fall back to
2965 // replacing the shuffle with extract and build vector.
2966 // to insert and build vector.
2967 EVT EltVT = VT.getVectorElementType();
2968 EVT PtrVT = TLI.getPointerTy();
2969 SmallVector<SDValue,8> Ops;
2970 for (unsigned i = 0; i != MaskNumElts; ++i) {
2972 Ops.push_back(DAG.getUNDEF(EltVT));
2977 if (Idx < (int)SrcNumElts)
2978 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2979 EltVT, Src1, DAG.getConstant(Idx, PtrVT));
2981 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2983 DAG.getConstant(Idx - SrcNumElts, PtrVT));
2989 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2990 VT, &Ops[0], Ops.size()));
2993 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2994 const Value *Op0 = I.getOperand(0);
2995 const Value *Op1 = I.getOperand(1);
2996 Type *AggTy = I.getType();
2997 Type *ValTy = Op1->getType();
2998 bool IntoUndef = isa<UndefValue>(Op0);
2999 bool FromUndef = isa<UndefValue>(Op1);
3001 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3003 SmallVector<EVT, 4> AggValueVTs;
3004 ComputeValueVTs(TLI, AggTy, AggValueVTs);
3005 SmallVector<EVT, 4> ValValueVTs;
3006 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3008 unsigned NumAggValues = AggValueVTs.size();
3009 unsigned NumValValues = ValValueVTs.size();
3010 SmallVector<SDValue, 4> Values(NumAggValues);
3012 SDValue Agg = getValue(Op0);
3014 // Copy the beginning value(s) from the original aggregate.
3015 for (; i != LinearIndex; ++i)
3016 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3017 SDValue(Agg.getNode(), Agg.getResNo() + i);
3018 // Copy values from the inserted value(s).
3020 SDValue Val = getValue(Op1);
3021 for (; i != LinearIndex + NumValValues; ++i)
3022 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3023 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3025 // Copy remaining value(s) from the original aggregate.
3026 for (; i != NumAggValues; ++i)
3027 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3028 SDValue(Agg.getNode(), Agg.getResNo() + i);
3030 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3031 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3032 &Values[0], NumAggValues));
3035 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3036 const Value *Op0 = I.getOperand(0);
3037 Type *AggTy = Op0->getType();
3038 Type *ValTy = I.getType();
3039 bool OutOfUndef = isa<UndefValue>(Op0);
3041 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3043 SmallVector<EVT, 4> ValValueVTs;
3044 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3046 unsigned NumValValues = ValValueVTs.size();
3048 // Ignore a extractvalue that produces an empty object
3049 if (!NumValValues) {
3050 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3054 SmallVector<SDValue, 4> Values(NumValValues);
3056 SDValue Agg = getValue(Op0);
3057 // Copy out the selected value(s).
3058 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3059 Values[i - LinearIndex] =
3061 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3062 SDValue(Agg.getNode(), Agg.getResNo() + i);
3064 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3065 DAG.getVTList(&ValValueVTs[0], NumValValues),
3066 &Values[0], NumValValues));
3069 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3070 SDValue N = getValue(I.getOperand(0));
3071 Type *Ty = I.getOperand(0)->getType();
3073 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3075 const Value *Idx = *OI;
3076 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3077 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3080 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3081 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3082 DAG.getIntPtrConstant(Offset));
3085 Ty = StTy->getElementType(Field);
3087 Ty = cast<SequentialType>(Ty)->getElementType();
3089 // If this is a constant subscript, handle it quickly.
3090 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3091 if (CI->isZero()) continue;
3093 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3095 EVT PTy = TLI.getPointerTy();
3096 unsigned PtrBits = PTy.getSizeInBits();
3098 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3100 DAG.getConstant(Offs, MVT::i64));
3102 OffsVal = DAG.getIntPtrConstant(Offs);
3104 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3109 // N = N + Idx * ElementSize;
3110 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3111 TD->getTypeAllocSize(Ty));
3112 SDValue IdxN = getValue(Idx);
3114 // If the index is smaller or larger than intptr_t, truncate or extend
3116 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3118 // If this is a multiply by a power of two, turn it into a shl
3119 // immediately. This is a very common case.
3120 if (ElementSize != 1) {
3121 if (ElementSize.isPowerOf2()) {
3122 unsigned Amt = ElementSize.logBase2();
3123 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3124 N.getValueType(), IdxN,
3125 DAG.getConstant(Amt, IdxN.getValueType()));
3127 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3128 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3129 N.getValueType(), IdxN, Scale);
3133 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3134 N.getValueType(), N, IdxN);
3141 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3142 // If this is a fixed sized alloca in the entry block of the function,
3143 // allocate it statically on the stack.
3144 if (FuncInfo.StaticAllocaMap.count(&I))
3145 return; // getValue will auto-populate this.
3147 Type *Ty = I.getAllocatedType();
3148 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3150 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3153 SDValue AllocSize = getValue(I.getArraySize());
3155 EVT IntPtr = TLI.getPointerTy();
3156 if (AllocSize.getValueType() != IntPtr)
3157 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3159 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3161 DAG.getConstant(TySize, IntPtr));
3163 // Handle alignment. If the requested alignment is less than or equal to
3164 // the stack alignment, ignore it. If the size is greater than or equal to
3165 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3166 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3167 if (Align <= StackAlign)
3170 // Round the size of the allocation up to the stack alignment size
3171 // by add SA-1 to the size.
3172 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3173 AllocSize.getValueType(), AllocSize,
3174 DAG.getIntPtrConstant(StackAlign-1));
3176 // Mask out the low bits for alignment purposes.
3177 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3178 AllocSize.getValueType(), AllocSize,
3179 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3181 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3182 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3183 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3186 DAG.setRoot(DSA.getValue(1));
3188 // Inform the Frame Information that we have just allocated a variable-sized
3190 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3193 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3195 return visitAtomicLoad(I);
3197 const Value *SV = I.getOperand(0);
3198 SDValue Ptr = getValue(SV);
3200 Type *Ty = I.getType();
3202 bool isVolatile = I.isVolatile();
3203 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3204 bool isInvariant = I.getMetadata("invariant.load") != 0;
3205 unsigned Alignment = I.getAlignment();
3206 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3208 SmallVector<EVT, 4> ValueVTs;
3209 SmallVector<uint64_t, 4> Offsets;
3210 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3211 unsigned NumValues = ValueVTs.size();
3216 bool ConstantMemory = false;
3217 if (I.isVolatile() || NumValues > MaxParallelChains)
3218 // Serialize volatile loads with other side effects.
3220 else if (AA->pointsToConstantMemory(
3221 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3222 // Do not serialize (non-volatile) loads of constant memory with anything.
3223 Root = DAG.getEntryNode();
3224 ConstantMemory = true;
3226 // Do not serialize non-volatile loads against each other.
3227 Root = DAG.getRoot();
3230 SmallVector<SDValue, 4> Values(NumValues);
3231 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3233 EVT PtrVT = Ptr.getValueType();
3234 unsigned ChainI = 0;
3235 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3236 // Serializing loads here may result in excessive register pressure, and
3237 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3238 // could recover a bit by hoisting nodes upward in the chain by recognizing
3239 // they are side-effect free or do not alias. The optimizer should really
3240 // avoid this case by converting large object/array copies to llvm.memcpy
3241 // (MaxParallelChains should always remain as failsafe).
3242 if (ChainI == MaxParallelChains) {
3243 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3244 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3245 MVT::Other, &Chains[0], ChainI);
3249 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3251 DAG.getConstant(Offsets[i], PtrVT));
3252 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3253 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3254 isNonTemporal, isInvariant, Alignment, TBAAInfo);
3257 Chains[ChainI] = L.getValue(1);
3260 if (!ConstantMemory) {
3261 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3262 MVT::Other, &Chains[0], ChainI);
3266 PendingLoads.push_back(Chain);
3269 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3270 DAG.getVTList(&ValueVTs[0], NumValues),
3271 &Values[0], NumValues));
3274 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3276 return visitAtomicStore(I);
3278 const Value *SrcV = I.getOperand(0);
3279 const Value *PtrV = I.getOperand(1);
3281 SmallVector<EVT, 4> ValueVTs;
3282 SmallVector<uint64_t, 4> Offsets;
3283 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3284 unsigned NumValues = ValueVTs.size();
3288 // Get the lowered operands. Note that we do this after
3289 // checking if NumResults is zero, because with zero results
3290 // the operands won't have values in the map.
3291 SDValue Src = getValue(SrcV);
3292 SDValue Ptr = getValue(PtrV);
3294 SDValue Root = getRoot();
3295 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3297 EVT PtrVT = Ptr.getValueType();
3298 bool isVolatile = I.isVolatile();
3299 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3300 unsigned Alignment = I.getAlignment();
3301 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3303 unsigned ChainI = 0;
3304 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3305 // See visitLoad comments.
3306 if (ChainI == MaxParallelChains) {
3307 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3308 MVT::Other, &Chains[0], ChainI);
3312 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3313 DAG.getConstant(Offsets[i], PtrVT));
3314 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3315 SDValue(Src.getNode(), Src.getResNo() + i),
3316 Add, MachinePointerInfo(PtrV, Offsets[i]),
3317 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3318 Chains[ChainI] = St;
3321 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3322 MVT::Other, &Chains[0], ChainI);
3324 AssignOrderingToNode(StoreNode.getNode());
3325 DAG.setRoot(StoreNode);
3328 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3329 SynchronizationScope Scope,
3330 bool Before, DebugLoc dl,
3332 const TargetLowering &TLI) {
3333 // Fence, if necessary
3335 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3337 else if (Order == Acquire || Order == Monotonic)
3340 if (Order == AcquireRelease)
3342 else if (Order == Release || Order == Monotonic)
3347 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3348 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3349 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3352 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3353 DebugLoc dl = getCurDebugLoc();
3354 AtomicOrdering Order = I.getOrdering();
3355 SynchronizationScope Scope = I.getSynchScope();
3357 SDValue InChain = getRoot();
3359 if (TLI.getInsertFencesForAtomic())
3360 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3364 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3365 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3367 getValue(I.getPointerOperand()),
3368 getValue(I.getCompareOperand()),
3369 getValue(I.getNewValOperand()),
3370 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3371 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3374 SDValue OutChain = L.getValue(1);
3376 if (TLI.getInsertFencesForAtomic())
3377 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3381 DAG.setRoot(OutChain);
3384 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3385 DebugLoc dl = getCurDebugLoc();
3387 switch (I.getOperation()) {
3388 default: llvm_unreachable("Unknown atomicrmw operation");
3389 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3390 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3391 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3392 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3393 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3394 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3395 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3396 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3397 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3398 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3399 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3401 AtomicOrdering Order = I.getOrdering();
3402 SynchronizationScope Scope = I.getSynchScope();
3404 SDValue InChain = getRoot();
3406 if (TLI.getInsertFencesForAtomic())
3407 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3411 DAG.getAtomic(NT, dl,
3412 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3414 getValue(I.getPointerOperand()),
3415 getValue(I.getValOperand()),
3416 I.getPointerOperand(), 0 /* Alignment */,
3417 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3420 SDValue OutChain = L.getValue(1);
3422 if (TLI.getInsertFencesForAtomic())
3423 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3427 DAG.setRoot(OutChain);
3430 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3431 DebugLoc dl = getCurDebugLoc();
3434 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3435 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3436 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3439 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3440 DebugLoc dl = getCurDebugLoc();
3441 AtomicOrdering Order = I.getOrdering();
3442 SynchronizationScope Scope = I.getSynchScope();
3444 SDValue InChain = getRoot();
3446 EVT VT = EVT::getEVT(I.getType());
3448 if (I.getAlignment() * 8 < VT.getSizeInBits())
3449 report_fatal_error("Cannot generate unaligned atomic load");
3452 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3453 getValue(I.getPointerOperand()),
3454 I.getPointerOperand(), I.getAlignment(),
3455 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3458 SDValue OutChain = L.getValue(1);
3460 if (TLI.getInsertFencesForAtomic())
3461 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3465 DAG.setRoot(OutChain);
3468 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3469 DebugLoc dl = getCurDebugLoc();
3471 AtomicOrdering Order = I.getOrdering();
3472 SynchronizationScope Scope = I.getSynchScope();
3474 SDValue InChain = getRoot();
3476 EVT VT = EVT::getEVT(I.getValueOperand()->getType());
3478 if (I.getAlignment() * 8 < VT.getSizeInBits())
3479 report_fatal_error("Cannot generate unaligned atomic store");
3481 if (TLI.getInsertFencesForAtomic())
3482 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3486 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3488 getValue(I.getPointerOperand()),
3489 getValue(I.getValueOperand()),
3490 I.getPointerOperand(), I.getAlignment(),
3491 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3494 if (TLI.getInsertFencesForAtomic())
3495 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3498 DAG.setRoot(OutChain);
3501 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3503 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3504 unsigned Intrinsic) {
3505 bool HasChain = !I.doesNotAccessMemory();
3506 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3508 // Build the operand list.
3509 SmallVector<SDValue, 8> Ops;
3510 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3512 // We don't need to serialize loads against other loads.
3513 Ops.push_back(DAG.getRoot());
3515 Ops.push_back(getRoot());
3519 // Info is set by getTgtMemInstrinsic
3520 TargetLowering::IntrinsicInfo Info;
3521 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3523 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3524 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3525 Info.opc == ISD::INTRINSIC_W_CHAIN)
3526 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3528 // Add all operands of the call to the operand list.
3529 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3530 SDValue Op = getValue(I.getArgOperand(i));
3534 SmallVector<EVT, 4> ValueVTs;
3535 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3538 ValueVTs.push_back(MVT::Other);
3540 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3544 if (IsTgtIntrinsic) {
3545 // This is target intrinsic that touches memory
3546 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3547 VTs, &Ops[0], Ops.size(),
3549 MachinePointerInfo(Info.ptrVal, Info.offset),
3550 Info.align, Info.vol,
3551 Info.readMem, Info.writeMem);
3552 } else if (!HasChain) {
3553 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3554 VTs, &Ops[0], Ops.size());
3555 } else if (!I.getType()->isVoidTy()) {
3556 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3557 VTs, &Ops[0], Ops.size());
3559 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3560 VTs, &Ops[0], Ops.size());
3564 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3566 PendingLoads.push_back(Chain);
3571 if (!I.getType()->isVoidTy()) {
3572 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3573 EVT VT = TLI.getValueType(PTy);
3574 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3577 setValue(&I, Result);
3581 /// GetSignificand - Get the significand and build it into a floating-point
3582 /// number with exponent of 1:
3584 /// Op = (Op & 0x007fffff) | 0x3f800000;
3586 /// where Op is the hexidecimal representation of floating point value.
3588 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3589 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3590 DAG.getConstant(0x007fffff, MVT::i32));
3591 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3592 DAG.getConstant(0x3f800000, MVT::i32));
3593 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3596 /// GetExponent - Get the exponent:
3598 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3600 /// where Op is the hexidecimal representation of floating point value.
3602 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3604 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3605 DAG.getConstant(0x7f800000, MVT::i32));
3606 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3607 DAG.getConstant(23, TLI.getPointerTy()));
3608 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3609 DAG.getConstant(127, MVT::i32));
3610 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3613 /// getF32Constant - Get 32-bit floating point constant.
3615 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3616 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3619 // implVisitAluOverflow - Lower arithmetic overflow instrinsics.
3621 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) {
3622 SDValue Op1 = getValue(I.getArgOperand(0));
3623 SDValue Op2 = getValue(I.getArgOperand(1));
3625 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
3626 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
3630 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3631 /// limited-precision mode.
3633 SelectionDAGBuilder::visitExp(const CallInst &I) {
3635 DebugLoc dl = getCurDebugLoc();
3637 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3638 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3639 SDValue Op = getValue(I.getArgOperand(0));
3641 // Put the exponent in the right bit position for later addition to the
3644 // #define LOG2OFe 1.4426950f
3645 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3646 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3647 getF32Constant(DAG, 0x3fb8aa3b));
3648 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3650 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3651 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3652 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3654 // IntegerPartOfX <<= 23;
3655 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3656 DAG.getConstant(23, TLI.getPointerTy()));
3658 if (LimitFloatPrecision <= 6) {
3659 // For floating-point precision of 6:
3661 // TwoToFractionalPartOfX =
3663 // (0.735607626f + 0.252464424f * x) * x;
3665 // error 0.0144103317, which is 6 bits
3666 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3667 getF32Constant(DAG, 0x3e814304));
3668 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3669 getF32Constant(DAG, 0x3f3c50c8));
3670 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3671 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3672 getF32Constant(DAG, 0x3f7f5e7e));
3673 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3675 // Add the exponent into the result in integer domain.
3676 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3677 TwoToFracPartOfX, IntegerPartOfX);
3679 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3680 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3681 // For floating-point precision of 12:
3683 // TwoToFractionalPartOfX =
3686 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3688 // 0.000107046256 error, which is 13 to 14 bits
3689 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3690 getF32Constant(DAG, 0x3da235e3));
3691 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3692 getF32Constant(DAG, 0x3e65b8f3));
3693 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3694 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3695 getF32Constant(DAG, 0x3f324b07));
3696 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3697 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3698 getF32Constant(DAG, 0x3f7ff8fd));
3699 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3701 // Add the exponent into the result in integer domain.
3702 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3703 TwoToFracPartOfX, IntegerPartOfX);
3705 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3706 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3707 // For floating-point precision of 18:
3709 // TwoToFractionalPartOfX =
3713 // (0.554906021e-1f +
3714 // (0.961591928e-2f +
3715 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3717 // error 2.47208000*10^(-7), which is better than 18 bits
3718 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3719 getF32Constant(DAG, 0x3924b03e));
3720 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3721 getF32Constant(DAG, 0x3ab24b87));
3722 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3723 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3724 getF32Constant(DAG, 0x3c1d8c17));
3725 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3726 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3727 getF32Constant(DAG, 0x3d634a1d));
3728 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3729 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3730 getF32Constant(DAG, 0x3e75fe14));
3731 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3732 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3733 getF32Constant(DAG, 0x3f317234));
3734 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3735 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3736 getF32Constant(DAG, 0x3f800000));
3737 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3740 // Add the exponent into the result in integer domain.
3741 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3742 TwoToFracPartOfX, IntegerPartOfX);
3744 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3747 // No special expansion.
3748 result = DAG.getNode(ISD::FEXP, dl,
3749 getValue(I.getArgOperand(0)).getValueType(),
3750 getValue(I.getArgOperand(0)));
3753 setValue(&I, result);
3756 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3757 /// limited-precision mode.
3759 SelectionDAGBuilder::visitLog(const CallInst &I) {
3761 DebugLoc dl = getCurDebugLoc();
3763 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3764 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3765 SDValue Op = getValue(I.getArgOperand(0));
3766 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3768 // Scale the exponent by log(2) [0.69314718f].
3769 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3770 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3771 getF32Constant(DAG, 0x3f317218));
3773 // Get the significand and build it into a floating-point number with
3775 SDValue X = GetSignificand(DAG, Op1, dl);
3777 if (LimitFloatPrecision <= 6) {
3778 // For floating-point precision of 6:
3782 // (1.4034025f - 0.23903021f * x) * x;
3784 // error 0.0034276066, which is better than 8 bits
3785 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3786 getF32Constant(DAG, 0xbe74c456));
3787 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3788 getF32Constant(DAG, 0x3fb3a2b1));
3789 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3790 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3791 getF32Constant(DAG, 0x3f949a29));
3793 result = DAG.getNode(ISD::FADD, dl,
3794 MVT::f32, LogOfExponent, LogOfMantissa);
3795 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3796 // For floating-point precision of 12:
3802 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3804 // error 0.000061011436, which is 14 bits
3805 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3806 getF32Constant(DAG, 0xbd67b6d6));
3807 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3808 getF32Constant(DAG, 0x3ee4f4b8));
3809 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3810 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3811 getF32Constant(DAG, 0x3fbc278b));
3812 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3813 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3814 getF32Constant(DAG, 0x40348e95));
3815 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3816 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3817 getF32Constant(DAG, 0x3fdef31a));
3819 result = DAG.getNode(ISD::FADD, dl,
3820 MVT::f32, LogOfExponent, LogOfMantissa);
3821 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3822 // For floating-point precision of 18:
3830 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3832 // error 0.0000023660568, which is better than 18 bits
3833 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3834 getF32Constant(DAG, 0xbc91e5ac));
3835 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3836 getF32Constant(DAG, 0x3e4350aa));
3837 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3838 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3839 getF32Constant(DAG, 0x3f60d3e3));
3840 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3841 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3842 getF32Constant(DAG, 0x4011cdf0));
3843 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3844 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3845 getF32Constant(DAG, 0x406cfd1c));
3846 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3847 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3848 getF32Constant(DAG, 0x408797cb));
3849 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3850 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3851 getF32Constant(DAG, 0x4006dcab));
3853 result = DAG.getNode(ISD::FADD, dl,
3854 MVT::f32, LogOfExponent, LogOfMantissa);
3857 // No special expansion.
3858 result = DAG.getNode(ISD::FLOG, dl,
3859 getValue(I.getArgOperand(0)).getValueType(),
3860 getValue(I.getArgOperand(0)));
3863 setValue(&I, result);
3866 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3867 /// limited-precision mode.
3869 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3871 DebugLoc dl = getCurDebugLoc();
3873 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3874 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3875 SDValue Op = getValue(I.getArgOperand(0));
3876 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3878 // Get the exponent.
3879 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3881 // Get the significand and build it into a floating-point number with
3883 SDValue X = GetSignificand(DAG, Op1, dl);
3885 // Different possible minimax approximations of significand in
3886 // floating-point for various degrees of accuracy over [1,2].
3887 if (LimitFloatPrecision <= 6) {
3888 // For floating-point precision of 6:
3890 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3892 // error 0.0049451742, which is more than 7 bits
3893 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3894 getF32Constant(DAG, 0xbeb08fe0));
3895 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3896 getF32Constant(DAG, 0x40019463));
3897 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3898 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3899 getF32Constant(DAG, 0x3fd6633d));
3901 result = DAG.getNode(ISD::FADD, dl,
3902 MVT::f32, LogOfExponent, Log2ofMantissa);
3903 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3904 // For floating-point precision of 12:
3910 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3912 // error 0.0000876136000, which is better than 13 bits
3913 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3914 getF32Constant(DAG, 0xbda7262e));
3915 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3916 getF32Constant(DAG, 0x3f25280b));
3917 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3918 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3919 getF32Constant(DAG, 0x4007b923));
3920 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3921 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3922 getF32Constant(DAG, 0x40823e2f));
3923 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3924 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3925 getF32Constant(DAG, 0x4020d29c));
3927 result = DAG.getNode(ISD::FADD, dl,
3928 MVT::f32, LogOfExponent, Log2ofMantissa);
3929 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3930 // For floating-point precision of 18:
3939 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3941 // error 0.0000018516, which is better than 18 bits
3942 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3943 getF32Constant(DAG, 0xbcd2769e));
3944 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3945 getF32Constant(DAG, 0x3e8ce0b9));
3946 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3947 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3948 getF32Constant(DAG, 0x3fa22ae7));
3949 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3950 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3951 getF32Constant(DAG, 0x40525723));
3952 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3953 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3954 getF32Constant(DAG, 0x40aaf200));
3955 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3956 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3957 getF32Constant(DAG, 0x40c39dad));
3958 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3959 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3960 getF32Constant(DAG, 0x4042902c));
3962 result = DAG.getNode(ISD::FADD, dl,
3963 MVT::f32, LogOfExponent, Log2ofMantissa);
3966 // No special expansion.
3967 result = DAG.getNode(ISD::FLOG2, dl,
3968 getValue(I.getArgOperand(0)).getValueType(),
3969 getValue(I.getArgOperand(0)));
3972 setValue(&I, result);
3975 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3976 /// limited-precision mode.
3978 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3980 DebugLoc dl = getCurDebugLoc();
3982 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3983 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3984 SDValue Op = getValue(I.getArgOperand(0));
3985 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3987 // Scale the exponent by log10(2) [0.30102999f].
3988 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3989 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3990 getF32Constant(DAG, 0x3e9a209a));
3992 // Get the significand and build it into a floating-point number with
3994 SDValue X = GetSignificand(DAG, Op1, dl);
3996 if (LimitFloatPrecision <= 6) {
3997 // For floating-point precision of 6:
3999 // Log10ofMantissa =
4001 // (0.60948995f - 0.10380950f * x) * x;
4003 // error 0.0014886165, which is 6 bits
4004 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4005 getF32Constant(DAG, 0xbdd49a13));
4006 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4007 getF32Constant(DAG, 0x3f1c0789));
4008 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4009 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4010 getF32Constant(DAG, 0x3f011300));
4012 result = DAG.getNode(ISD::FADD, dl,
4013 MVT::f32, LogOfExponent, Log10ofMantissa);
4014 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4015 // For floating-point precision of 12:
4017 // Log10ofMantissa =
4020 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4022 // error 0.00019228036, which is better than 12 bits
4023 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4024 getF32Constant(DAG, 0x3d431f31));
4025 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4026 getF32Constant(DAG, 0x3ea21fb2));
4027 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4028 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4029 getF32Constant(DAG, 0x3f6ae232));
4030 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4031 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4032 getF32Constant(DAG, 0x3f25f7c3));
4034 result = DAG.getNode(ISD::FADD, dl,
4035 MVT::f32, LogOfExponent, Log10ofMantissa);
4036 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4037 // For floating-point precision of 18:
4039 // Log10ofMantissa =
4044 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4046 // error 0.0000037995730, which is better than 18 bits
4047 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4048 getF32Constant(DAG, 0x3c5d51ce));
4049 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4050 getF32Constant(DAG, 0x3e00685a));
4051 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4052 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4053 getF32Constant(DAG, 0x3efb6798));
4054 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4055 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4056 getF32Constant(DAG, 0x3f88d192));
4057 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4058 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4059 getF32Constant(DAG, 0x3fc4316c));
4060 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4061 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4062 getF32Constant(DAG, 0x3f57ce70));
4064 result = DAG.getNode(ISD::FADD, dl,
4065 MVT::f32, LogOfExponent, Log10ofMantissa);
4068 // No special expansion.
4069 result = DAG.getNode(ISD::FLOG10, dl,
4070 getValue(I.getArgOperand(0)).getValueType(),
4071 getValue(I.getArgOperand(0)));
4074 setValue(&I, result);
4077 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4078 /// limited-precision mode.
4080 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4082 DebugLoc dl = getCurDebugLoc();
4084 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4085 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4086 SDValue Op = getValue(I.getArgOperand(0));
4088 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4090 // FractionalPartOfX = x - (float)IntegerPartOfX;
4091 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4092 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4094 // IntegerPartOfX <<= 23;
4095 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4096 DAG.getConstant(23, TLI.getPointerTy()));
4098 if (LimitFloatPrecision <= 6) {
4099 // For floating-point precision of 6:
4101 // TwoToFractionalPartOfX =
4103 // (0.735607626f + 0.252464424f * x) * x;
4105 // error 0.0144103317, which is 6 bits
4106 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4107 getF32Constant(DAG, 0x3e814304));
4108 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4109 getF32Constant(DAG, 0x3f3c50c8));
4110 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4111 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4112 getF32Constant(DAG, 0x3f7f5e7e));
4113 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4114 SDValue TwoToFractionalPartOfX =
4115 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4117 result = DAG.getNode(ISD::BITCAST, dl,
4118 MVT::f32, TwoToFractionalPartOfX);
4119 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4120 // For floating-point precision of 12:
4122 // TwoToFractionalPartOfX =
4125 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4127 // error 0.000107046256, which is 13 to 14 bits
4128 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4129 getF32Constant(DAG, 0x3da235e3));
4130 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4131 getF32Constant(DAG, 0x3e65b8f3));
4132 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4133 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4134 getF32Constant(DAG, 0x3f324b07));
4135 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4136 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4137 getF32Constant(DAG, 0x3f7ff8fd));
4138 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4139 SDValue TwoToFractionalPartOfX =
4140 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4142 result = DAG.getNode(ISD::BITCAST, dl,
4143 MVT::f32, TwoToFractionalPartOfX);
4144 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4145 // For floating-point precision of 18:
4147 // TwoToFractionalPartOfX =
4151 // (0.554906021e-1f +
4152 // (0.961591928e-2f +
4153 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4154 // error 2.47208000*10^(-7), which is better than 18 bits
4155 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4156 getF32Constant(DAG, 0x3924b03e));
4157 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4158 getF32Constant(DAG, 0x3ab24b87));
4159 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4160 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4161 getF32Constant(DAG, 0x3c1d8c17));
4162 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4163 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4164 getF32Constant(DAG, 0x3d634a1d));
4165 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4166 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4167 getF32Constant(DAG, 0x3e75fe14));
4168 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4169 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4170 getF32Constant(DAG, 0x3f317234));
4171 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4172 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4173 getF32Constant(DAG, 0x3f800000));
4174 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4175 SDValue TwoToFractionalPartOfX =
4176 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4178 result = DAG.getNode(ISD::BITCAST, dl,
4179 MVT::f32, TwoToFractionalPartOfX);
4182 // No special expansion.
4183 result = DAG.getNode(ISD::FEXP2, dl,
4184 getValue(I.getArgOperand(0)).getValueType(),
4185 getValue(I.getArgOperand(0)));
4188 setValue(&I, result);
4191 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4192 /// limited-precision mode with x == 10.0f.
4194 SelectionDAGBuilder::visitPow(const CallInst &I) {
4196 const Value *Val = I.getArgOperand(0);
4197 DebugLoc dl = getCurDebugLoc();
4198 bool IsExp10 = false;
4200 if (getValue(Val).getValueType() == MVT::f32 &&
4201 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4202 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4203 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4204 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4206 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4211 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4212 SDValue Op = getValue(I.getArgOperand(1));
4214 // Put the exponent in the right bit position for later addition to the
4217 // #define LOG2OF10 3.3219281f
4218 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4219 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4220 getF32Constant(DAG, 0x40549a78));
4221 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4223 // FractionalPartOfX = x - (float)IntegerPartOfX;
4224 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4225 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4227 // IntegerPartOfX <<= 23;
4228 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4229 DAG.getConstant(23, TLI.getPointerTy()));
4231 if (LimitFloatPrecision <= 6) {
4232 // For floating-point precision of 6:
4234 // twoToFractionalPartOfX =
4236 // (0.735607626f + 0.252464424f * x) * x;
4238 // error 0.0144103317, which is 6 bits
4239 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4240 getF32Constant(DAG, 0x3e814304));
4241 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4242 getF32Constant(DAG, 0x3f3c50c8));
4243 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4244 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4245 getF32Constant(DAG, 0x3f7f5e7e));
4246 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4247 SDValue TwoToFractionalPartOfX =
4248 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4250 result = DAG.getNode(ISD::BITCAST, dl,
4251 MVT::f32, TwoToFractionalPartOfX);
4252 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4253 // For floating-point precision of 12:
4255 // TwoToFractionalPartOfX =
4258 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4260 // error 0.000107046256, which is 13 to 14 bits
4261 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4262 getF32Constant(DAG, 0x3da235e3));
4263 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4264 getF32Constant(DAG, 0x3e65b8f3));
4265 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4266 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4267 getF32Constant(DAG, 0x3f324b07));
4268 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4269 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4270 getF32Constant(DAG, 0x3f7ff8fd));
4271 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4272 SDValue TwoToFractionalPartOfX =
4273 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4275 result = DAG.getNode(ISD::BITCAST, dl,
4276 MVT::f32, TwoToFractionalPartOfX);
4277 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4278 // For floating-point precision of 18:
4280 // TwoToFractionalPartOfX =
4284 // (0.554906021e-1f +
4285 // (0.961591928e-2f +
4286 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4287 // error 2.47208000*10^(-7), which is better than 18 bits
4288 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4289 getF32Constant(DAG, 0x3924b03e));
4290 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4291 getF32Constant(DAG, 0x3ab24b87));
4292 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4293 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4294 getF32Constant(DAG, 0x3c1d8c17));
4295 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4296 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4297 getF32Constant(DAG, 0x3d634a1d));
4298 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4299 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4300 getF32Constant(DAG, 0x3e75fe14));
4301 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4302 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4303 getF32Constant(DAG, 0x3f317234));
4304 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4305 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4306 getF32Constant(DAG, 0x3f800000));
4307 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4308 SDValue TwoToFractionalPartOfX =
4309 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4311 result = DAG.getNode(ISD::BITCAST, dl,
4312 MVT::f32, TwoToFractionalPartOfX);
4315 // No special expansion.
4316 result = DAG.getNode(ISD::FPOW, dl,
4317 getValue(I.getArgOperand(0)).getValueType(),
4318 getValue(I.getArgOperand(0)),
4319 getValue(I.getArgOperand(1)));
4322 setValue(&I, result);
4326 /// ExpandPowI - Expand a llvm.powi intrinsic.
4327 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4328 SelectionDAG &DAG) {
4329 // If RHS is a constant, we can expand this out to a multiplication tree,
4330 // otherwise we end up lowering to a call to __powidf2 (for example). When
4331 // optimizing for size, we only want to do this if the expansion would produce
4332 // a small number of multiplies, otherwise we do the full expansion.
4333 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4334 // Get the exponent as a positive value.
4335 unsigned Val = RHSC->getSExtValue();
4336 if ((int)Val < 0) Val = -Val;
4338 // powi(x, 0) -> 1.0
4340 return DAG.getConstantFP(1.0, LHS.getValueType());
4342 const Function *F = DAG.getMachineFunction().getFunction();
4343 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4344 // If optimizing for size, don't insert too many multiplies. This
4345 // inserts up to 5 multiplies.
4346 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4347 // We use the simple binary decomposition method to generate the multiply
4348 // sequence. There are more optimal ways to do this (for example,
4349 // powi(x,15) generates one more multiply than it should), but this has
4350 // the benefit of being both really simple and much better than a libcall.
4351 SDValue Res; // Logically starts equal to 1.0
4352 SDValue CurSquare = LHS;
4356 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4358 Res = CurSquare; // 1.0*CurSquare.
4361 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4362 CurSquare, CurSquare);
4366 // If the original was negative, invert the result, producing 1/(x*x*x).
4367 if (RHSC->getSExtValue() < 0)
4368 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4369 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4374 // Otherwise, expand to a libcall.
4375 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4378 // getTruncatedArgReg - Find underlying register used for an truncated
4380 static unsigned getTruncatedArgReg(const SDValue &N) {
4381 if (N.getOpcode() != ISD::TRUNCATE)
4384 const SDValue &Ext = N.getOperand(0);
4385 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4386 const SDValue &CFR = Ext.getOperand(0);
4387 if (CFR.getOpcode() == ISD::CopyFromReg)
4388 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4390 if (CFR.getOpcode() == ISD::TRUNCATE)
4391 return getTruncatedArgReg(CFR);
4396 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4397 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4398 /// At the end of instruction selection, they will be inserted to the entry BB.
4400 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4403 const Argument *Arg = dyn_cast<Argument>(V);
4407 MachineFunction &MF = DAG.getMachineFunction();
4408 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4409 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4411 // Ignore inlined function arguments here.
4412 DIVariable DV(Variable);
4413 if (DV.isInlinedFnArgument(MF.getFunction()))
4417 // Some arguments' frame index is recorded during argument lowering.
4418 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4420 Reg = TRI->getFrameRegister(MF);
4422 if (!Reg && N.getNode()) {
4423 if (N.getOpcode() == ISD::CopyFromReg)
4424 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4426 Reg = getTruncatedArgReg(N);
4427 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4428 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4429 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4436 // Check if ValueMap has reg number.
4437 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4438 if (VMI != FuncInfo.ValueMap.end())
4442 if (!Reg && N.getNode()) {
4443 // Check if frame index is available.
4444 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4445 if (FrameIndexSDNode *FINode =
4446 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4447 Reg = TRI->getFrameRegister(MF);
4448 Offset = FINode->getIndex();
4455 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4456 TII->get(TargetOpcode::DBG_VALUE))
4457 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4458 FuncInfo.ArgDbgValues.push_back(&*MIB);
4462 // VisualStudio defines setjmp as _setjmp
4463 #if defined(_MSC_VER) && defined(setjmp) && \
4464 !defined(setjmp_undefined_for_msvc)
4465 # pragma push_macro("setjmp")
4467 # define setjmp_undefined_for_msvc
4470 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4471 /// we want to emit this as a call to a named external function, return the name
4472 /// otherwise lower it and return null.
4474 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4475 DebugLoc dl = getCurDebugLoc();
4478 switch (Intrinsic) {
4480 // By default, turn this into a target intrinsic node.
4481 visitTargetIntrinsic(I, Intrinsic);
4483 case Intrinsic::vastart: visitVAStart(I); return 0;
4484 case Intrinsic::vaend: visitVAEnd(I); return 0;
4485 case Intrinsic::vacopy: visitVACopy(I); return 0;
4486 case Intrinsic::returnaddress:
4487 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4488 getValue(I.getArgOperand(0))));
4490 case Intrinsic::frameaddress:
4491 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4492 getValue(I.getArgOperand(0))));
4494 case Intrinsic::setjmp:
4495 return "_setjmp"+!TLI.usesUnderscoreSetJmp();
4496 case Intrinsic::longjmp:
4497 return "_longjmp"+!TLI.usesUnderscoreLongJmp();
4498 case Intrinsic::memcpy: {
4499 // Assert for address < 256 since we support only user defined address
4501 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4503 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4505 "Unknown address space");
4506 SDValue Op1 = getValue(I.getArgOperand(0));
4507 SDValue Op2 = getValue(I.getArgOperand(1));
4508 SDValue Op3 = getValue(I.getArgOperand(2));
4509 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4510 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4511 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4512 MachinePointerInfo(I.getArgOperand(0)),
4513 MachinePointerInfo(I.getArgOperand(1))));
4516 case Intrinsic::memset: {
4517 // Assert for address < 256 since we support only user defined address
4519 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4521 "Unknown address space");
4522 SDValue Op1 = getValue(I.getArgOperand(0));
4523 SDValue Op2 = getValue(I.getArgOperand(1));
4524 SDValue Op3 = getValue(I.getArgOperand(2));
4525 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4526 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4527 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4528 MachinePointerInfo(I.getArgOperand(0))));
4531 case Intrinsic::memmove: {
4532 // Assert for address < 256 since we support only user defined address
4534 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4536 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4538 "Unknown address space");
4539 SDValue Op1 = getValue(I.getArgOperand(0));
4540 SDValue Op2 = getValue(I.getArgOperand(1));
4541 SDValue Op3 = getValue(I.getArgOperand(2));
4542 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4543 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4544 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4545 MachinePointerInfo(I.getArgOperand(0)),
4546 MachinePointerInfo(I.getArgOperand(1))));
4549 case Intrinsic::dbg_declare: {
4550 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4551 MDNode *Variable = DI.getVariable();
4552 const Value *Address = DI.getAddress();
4553 if (!Address || !DIVariable(Variable).Verify())
4556 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4557 // but do not always have a corresponding SDNode built. The SDNodeOrder
4558 // absolute, but not relative, values are different depending on whether
4559 // debug info exists.
4562 // Check if address has undef value.
4563 if (isa<UndefValue>(Address) ||
4564 (Address->use_empty() && !isa<Argument>(Address))) {
4565 DEBUG(dbgs() << "Dropping debug info for " << DI);
4569 SDValue &N = NodeMap[Address];
4570 if (!N.getNode() && isa<Argument>(Address))
4571 // Check unused arguments map.
4572 N = UnusedArgNodeMap[Address];
4575 // Parameters are handled specially.
4577 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable;
4578 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4579 Address = BCI->getOperand(0);
4580 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4582 if (isParameter && !AI) {
4583 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4585 // Byval parameter. We have a frame index at this point.
4586 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4587 0, dl, SDNodeOrder);
4589 // Address is an argument, so try to emit its dbg value using
4590 // virtual register info from the FuncInfo.ValueMap.
4591 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4595 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4596 0, dl, SDNodeOrder);
4598 // Can't do anything with other non-AI cases yet.
4599 DEBUG(dbgs() << "Dropping debug info for " << DI);
4602 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4604 // If Address is an argument then try to emit its dbg value using
4605 // virtual register info from the FuncInfo.ValueMap.
4606 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4607 // If variable is pinned by a alloca in dominating bb then
4608 // use StaticAllocaMap.
4609 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4610 if (AI->getParent() != DI.getParent()) {
4611 DenseMap<const AllocaInst*, int>::iterator SI =
4612 FuncInfo.StaticAllocaMap.find(AI);
4613 if (SI != FuncInfo.StaticAllocaMap.end()) {
4614 SDV = DAG.getDbgValue(Variable, SI->second,
4615 0, dl, SDNodeOrder);
4616 DAG.AddDbgValue(SDV, 0, false);
4621 DEBUG(dbgs() << "Dropping debug info for " << DI);
4626 case Intrinsic::dbg_value: {
4627 const DbgValueInst &DI = cast<DbgValueInst>(I);
4628 if (!DIVariable(DI.getVariable()).Verify())
4631 MDNode *Variable = DI.getVariable();
4632 uint64_t Offset = DI.getOffset();
4633 const Value *V = DI.getValue();
4637 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4638 // but do not always have a corresponding SDNode built. The SDNodeOrder
4639 // absolute, but not relative, values are different depending on whether
4640 // debug info exists.
4643 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4644 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4645 DAG.AddDbgValue(SDV, 0, false);
4647 // Do not use getValue() in here; we don't want to generate code at
4648 // this point if it hasn't been done yet.
4649 SDValue N = NodeMap[V];
4650 if (!N.getNode() && isa<Argument>(V))
4651 // Check unused arguments map.
4652 N = UnusedArgNodeMap[V];
4654 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4655 SDV = DAG.getDbgValue(Variable, N.getNode(),
4656 N.getResNo(), Offset, dl, SDNodeOrder);
4657 DAG.AddDbgValue(SDV, N.getNode(), false);
4659 } else if (!V->use_empty() ) {
4660 // Do not call getValue(V) yet, as we don't want to generate code.
4661 // Remember it for later.
4662 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4663 DanglingDebugInfoMap[V] = DDI;
4665 // We may expand this to cover more cases. One case where we have no
4666 // data available is an unreferenced parameter.
4667 DEBUG(dbgs() << "Dropping debug info for " << DI);
4671 // Build a debug info table entry.
4672 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4673 V = BCI->getOperand(0);
4674 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4675 // Don't handle byval struct arguments or VLAs, for example.
4678 DenseMap<const AllocaInst*, int>::iterator SI =
4679 FuncInfo.StaticAllocaMap.find(AI);
4680 if (SI == FuncInfo.StaticAllocaMap.end())
4682 int FI = SI->second;
4684 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4685 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4686 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4690 case Intrinsic::eh_typeid_for: {
4691 // Find the type id for the given typeinfo.
4692 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4693 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4694 Res = DAG.getConstant(TypeID, MVT::i32);
4699 case Intrinsic::eh_return_i32:
4700 case Intrinsic::eh_return_i64:
4701 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4702 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4705 getValue(I.getArgOperand(0)),
4706 getValue(I.getArgOperand(1))));
4708 case Intrinsic::eh_unwind_init:
4709 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4711 case Intrinsic::eh_dwarf_cfa: {
4712 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4713 TLI.getPointerTy());
4714 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4716 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4717 TLI.getPointerTy()),
4719 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4721 DAG.getConstant(0, TLI.getPointerTy()));
4722 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4726 case Intrinsic::eh_sjlj_callsite: {
4727 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4728 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4729 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4730 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4732 MMI.setCurrentCallSite(CI->getZExtValue());
4735 case Intrinsic::eh_sjlj_functioncontext: {
4736 // Get and store the index of the function context.
4737 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4739 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4740 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4741 MFI->setFunctionContextIndex(FI);
4744 case Intrinsic::eh_sjlj_setjmp: {
4747 Ops[1] = getValue(I.getArgOperand(0));
4748 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4749 DAG.getVTList(MVT::i32, MVT::Other),
4751 setValue(&I, Op.getValue(0));
4752 DAG.setRoot(Op.getValue(1));
4755 case Intrinsic::eh_sjlj_longjmp: {
4756 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4757 getRoot(), getValue(I.getArgOperand(0))));
4761 case Intrinsic::x86_mmx_pslli_w:
4762 case Intrinsic::x86_mmx_pslli_d:
4763 case Intrinsic::x86_mmx_pslli_q:
4764 case Intrinsic::x86_mmx_psrli_w:
4765 case Intrinsic::x86_mmx_psrli_d:
4766 case Intrinsic::x86_mmx_psrli_q:
4767 case Intrinsic::x86_mmx_psrai_w:
4768 case Intrinsic::x86_mmx_psrai_d: {
4769 SDValue ShAmt = getValue(I.getArgOperand(1));
4770 if (isa<ConstantSDNode>(ShAmt)) {
4771 visitTargetIntrinsic(I, Intrinsic);
4774 unsigned NewIntrinsic = 0;
4775 EVT ShAmtVT = MVT::v2i32;
4776 switch (Intrinsic) {
4777 case Intrinsic::x86_mmx_pslli_w:
4778 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4780 case Intrinsic::x86_mmx_pslli_d:
4781 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4783 case Intrinsic::x86_mmx_pslli_q:
4784 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4786 case Intrinsic::x86_mmx_psrli_w:
4787 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4789 case Intrinsic::x86_mmx_psrli_d:
4790 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4792 case Intrinsic::x86_mmx_psrli_q:
4793 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4795 case Intrinsic::x86_mmx_psrai_w:
4796 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4798 case Intrinsic::x86_mmx_psrai_d:
4799 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4801 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4804 // The vector shift intrinsics with scalars uses 32b shift amounts but
4805 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4807 // We must do this early because v2i32 is not a legal type.
4808 DebugLoc dl = getCurDebugLoc();
4811 ShOps[1] = DAG.getConstant(0, MVT::i32);
4812 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4813 EVT DestVT = TLI.getValueType(I.getType());
4814 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4815 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4816 DAG.getConstant(NewIntrinsic, MVT::i32),
4817 getValue(I.getArgOperand(0)), ShAmt);
4821 case Intrinsic::convertff:
4822 case Intrinsic::convertfsi:
4823 case Intrinsic::convertfui:
4824 case Intrinsic::convertsif:
4825 case Intrinsic::convertuif:
4826 case Intrinsic::convertss:
4827 case Intrinsic::convertsu:
4828 case Intrinsic::convertus:
4829 case Intrinsic::convertuu: {
4830 ISD::CvtCode Code = ISD::CVT_INVALID;
4831 switch (Intrinsic) {
4832 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4833 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4834 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4835 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4836 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4837 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4838 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4839 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4840 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4842 EVT DestVT = TLI.getValueType(I.getType());
4843 const Value *Op1 = I.getArgOperand(0);
4844 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4845 DAG.getValueType(DestVT),
4846 DAG.getValueType(getValue(Op1).getValueType()),
4847 getValue(I.getArgOperand(1)),
4848 getValue(I.getArgOperand(2)),
4853 case Intrinsic::sqrt:
4854 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4855 getValue(I.getArgOperand(0)).getValueType(),
4856 getValue(I.getArgOperand(0))));
4858 case Intrinsic::powi:
4859 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4860 getValue(I.getArgOperand(1)), DAG));
4862 case Intrinsic::sin:
4863 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4864 getValue(I.getArgOperand(0)).getValueType(),
4865 getValue(I.getArgOperand(0))));
4867 case Intrinsic::cos:
4868 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4869 getValue(I.getArgOperand(0)).getValueType(),
4870 getValue(I.getArgOperand(0))));
4872 case Intrinsic::log:
4875 case Intrinsic::log2:
4878 case Intrinsic::log10:
4881 case Intrinsic::exp:
4884 case Intrinsic::exp2:
4887 case Intrinsic::pow:
4890 case Intrinsic::fma:
4891 setValue(&I, DAG.getNode(ISD::FMA, dl,
4892 getValue(I.getArgOperand(0)).getValueType(),
4893 getValue(I.getArgOperand(0)),
4894 getValue(I.getArgOperand(1)),
4895 getValue(I.getArgOperand(2))));
4897 case Intrinsic::convert_to_fp16:
4898 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4899 MVT::i16, getValue(I.getArgOperand(0))));
4901 case Intrinsic::convert_from_fp16:
4902 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4903 MVT::f32, getValue(I.getArgOperand(0))));
4905 case Intrinsic::pcmarker: {
4906 SDValue Tmp = getValue(I.getArgOperand(0));
4907 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4910 case Intrinsic::readcyclecounter: {
4911 SDValue Op = getRoot();
4912 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4913 DAG.getVTList(MVT::i64, MVT::Other),
4916 DAG.setRoot(Res.getValue(1));
4919 case Intrinsic::bswap:
4920 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4921 getValue(I.getArgOperand(0)).getValueType(),
4922 getValue(I.getArgOperand(0))));
4924 case Intrinsic::cttz: {
4925 SDValue Arg = getValue(I.getArgOperand(0));
4926 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4927 EVT Ty = Arg.getValueType();
4928 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4932 case Intrinsic::ctlz: {
4933 SDValue Arg = getValue(I.getArgOperand(0));
4934 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4935 EVT Ty = Arg.getValueType();
4936 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4940 case Intrinsic::ctpop: {
4941 SDValue Arg = getValue(I.getArgOperand(0));
4942 EVT Ty = Arg.getValueType();
4943 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4946 case Intrinsic::stacksave: {
4947 SDValue Op = getRoot();
4948 Res = DAG.getNode(ISD::STACKSAVE, dl,
4949 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4951 DAG.setRoot(Res.getValue(1));
4954 case Intrinsic::stackrestore: {
4955 Res = getValue(I.getArgOperand(0));
4956 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4959 case Intrinsic::stackprotector: {
4960 // Emit code into the DAG to store the stack guard onto the stack.
4961 MachineFunction &MF = DAG.getMachineFunction();
4962 MachineFrameInfo *MFI = MF.getFrameInfo();
4963 EVT PtrTy = TLI.getPointerTy();
4965 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4966 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4968 int FI = FuncInfo.StaticAllocaMap[Slot];
4969 MFI->setStackProtectorIndex(FI);
4971 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4973 // Store the stack protector onto the stack.
4974 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4975 MachinePointerInfo::getFixedStack(FI),
4981 case Intrinsic::objectsize: {
4982 // If we don't know by now, we're never going to know.
4983 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4985 assert(CI && "Non-constant type in __builtin_object_size?");
4987 SDValue Arg = getValue(I.getCalledValue());
4988 EVT Ty = Arg.getValueType();
4991 Res = DAG.getConstant(-1ULL, Ty);
4993 Res = DAG.getConstant(0, Ty);
4998 case Intrinsic::var_annotation:
4999 // Discard annotate attributes
5002 case Intrinsic::init_trampoline: {
5003 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5007 Ops[1] = getValue(I.getArgOperand(0));
5008 Ops[2] = getValue(I.getArgOperand(1));
5009 Ops[3] = getValue(I.getArgOperand(2));
5010 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5011 Ops[5] = DAG.getSrcValue(F);
5013 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5018 case Intrinsic::adjust_trampoline: {
5019 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5021 getValue(I.getArgOperand(0))));
5024 case Intrinsic::gcroot:
5026 const Value *Alloca = I.getArgOperand(0);
5027 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5029 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5030 GFI->addStackRoot(FI->getIndex(), TypeMap);
5033 case Intrinsic::gcread:
5034 case Intrinsic::gcwrite:
5035 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5036 case Intrinsic::flt_rounds:
5037 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5040 case Intrinsic::expect: {
5041 // Just replace __builtin_expect(exp, c) with EXP.
5042 setValue(&I, getValue(I.getArgOperand(0)));
5046 case Intrinsic::trap: {
5047 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5048 if (TrapFuncName.empty()) {
5049 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5052 TargetLowering::ArgListTy Args;
5053 std::pair<SDValue, SDValue> Result =
5054 TLI.LowerCallTo(getRoot(), I.getType(),
5055 false, false, false, false, 0, CallingConv::C,
5056 /*isTailCall=*/false, /*isReturnValueUsed=*/true,
5057 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5058 Args, DAG, getCurDebugLoc());
5059 DAG.setRoot(Result.second);
5062 case Intrinsic::uadd_with_overflow:
5063 return implVisitAluOverflow(I, ISD::UADDO);
5064 case Intrinsic::sadd_with_overflow:
5065 return implVisitAluOverflow(I, ISD::SADDO);
5066 case Intrinsic::usub_with_overflow:
5067 return implVisitAluOverflow(I, ISD::USUBO);
5068 case Intrinsic::ssub_with_overflow:
5069 return implVisitAluOverflow(I, ISD::SSUBO);
5070 case Intrinsic::umul_with_overflow:
5071 return implVisitAluOverflow(I, ISD::UMULO);
5072 case Intrinsic::smul_with_overflow:
5073 return implVisitAluOverflow(I, ISD::SMULO);
5075 case Intrinsic::prefetch: {
5077 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5079 Ops[1] = getValue(I.getArgOperand(0));
5080 Ops[2] = getValue(I.getArgOperand(1));
5081 Ops[3] = getValue(I.getArgOperand(2));
5082 Ops[4] = getValue(I.getArgOperand(3));
5083 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5084 DAG.getVTList(MVT::Other),
5086 EVT::getIntegerVT(*Context, 8),
5087 MachinePointerInfo(I.getArgOperand(0)),
5089 false, /* volatile */
5091 rw==1)); /* write */
5095 case Intrinsic::invariant_start:
5096 case Intrinsic::lifetime_start:
5097 // Discard region information.
5098 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5100 case Intrinsic::invariant_end:
5101 case Intrinsic::lifetime_end:
5102 // Discard region information.
5107 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5109 MachineBasicBlock *LandingPad) {
5110 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5111 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5112 Type *RetTy = FTy->getReturnType();
5113 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5114 MCSymbol *BeginLabel = 0;
5116 TargetLowering::ArgListTy Args;
5117 TargetLowering::ArgListEntry Entry;
5118 Args.reserve(CS.arg_size());
5120 // Check whether the function can return without sret-demotion.
5121 SmallVector<ISD::OutputArg, 4> Outs;
5122 SmallVector<uint64_t, 4> Offsets;
5123 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5124 Outs, TLI, &Offsets);
5126 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5127 DAG.getMachineFunction(),
5128 FTy->isVarArg(), Outs,
5131 SDValue DemoteStackSlot;
5132 int DemoteStackIdx = -100;
5134 if (!CanLowerReturn) {
5135 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5136 FTy->getReturnType());
5137 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5138 FTy->getReturnType());
5139 MachineFunction &MF = DAG.getMachineFunction();
5140 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5141 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5143 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5144 Entry.Node = DemoteStackSlot;
5145 Entry.Ty = StackSlotPtrType;
5146 Entry.isSExt = false;
5147 Entry.isZExt = false;
5148 Entry.isInReg = false;
5149 Entry.isSRet = true;
5150 Entry.isNest = false;
5151 Entry.isByVal = false;
5152 Entry.Alignment = Align;
5153 Args.push_back(Entry);
5154 RetTy = Type::getVoidTy(FTy->getContext());
5157 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5159 const Value *V = *i;
5162 if (V->getType()->isEmptyTy())
5165 SDValue ArgNode = getValue(V);
5166 Entry.Node = ArgNode; Entry.Ty = V->getType();
5168 unsigned attrInd = i - CS.arg_begin() + 1;
5169 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5170 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5171 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5172 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5173 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5174 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5175 Entry.Alignment = CS.getParamAlignment(attrInd);
5176 Args.push_back(Entry);
5180 // Insert a label before the invoke call to mark the try range. This can be
5181 // used to detect deletion of the invoke via the MachineModuleInfo.
5182 BeginLabel = MMI.getContext().CreateTempSymbol();
5184 // For SjLj, keep track of which landing pads go with which invokes
5185 // so as to maintain the ordering of pads in the LSDA.
5186 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5187 if (CallSiteIndex) {
5188 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5189 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5191 // Now that the call site is handled, stop tracking it.
5192 MMI.setCurrentCallSite(0);
5195 // Both PendingLoads and PendingExports must be flushed here;
5196 // this call might not return.
5198 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5201 // Check if target-independent constraints permit a tail call here.
5202 // Target-dependent constraints are checked within TLI.LowerCallTo.
5204 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5207 // If there's a possibility that fast-isel has already selected some amount
5208 // of the current basic block, don't emit a tail call.
5209 if (isTailCall && TM.Options.EnableFastISel)
5212 std::pair<SDValue,SDValue> Result =
5213 TLI.LowerCallTo(getRoot(), RetTy,
5214 CS.paramHasAttr(0, Attribute::SExt),
5215 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5216 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5217 CS.getCallingConv(),
5219 !CS.getInstruction()->use_empty(),
5220 Callee, Args, DAG, getCurDebugLoc());
5221 assert((isTailCall || Result.second.getNode()) &&
5222 "Non-null chain expected with non-tail call!");
5223 assert((Result.second.getNode() || !Result.first.getNode()) &&
5224 "Null value expected with tail call!");
5225 if (Result.first.getNode()) {
5226 setValue(CS.getInstruction(), Result.first);
5227 } else if (!CanLowerReturn && Result.second.getNode()) {
5228 // The instruction result is the result of loading from the
5229 // hidden sret parameter.
5230 SmallVector<EVT, 1> PVTs;
5231 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5233 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5234 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5235 EVT PtrVT = PVTs[0];
5236 unsigned NumValues = Outs.size();
5237 SmallVector<SDValue, 4> Values(NumValues);
5238 SmallVector<SDValue, 4> Chains(NumValues);
5240 for (unsigned i = 0; i < NumValues; ++i) {
5241 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5243 DAG.getConstant(Offsets[i], PtrVT));
5244 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5246 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5247 false, false, false, 1);
5249 Chains[i] = L.getValue(1);
5252 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5253 MVT::Other, &Chains[0], NumValues);
5254 PendingLoads.push_back(Chain);
5256 // Collect the legal value parts into potentially illegal values
5257 // that correspond to the original function's return values.
5258 SmallVector<EVT, 4> RetTys;
5259 RetTy = FTy->getReturnType();
5260 ComputeValueVTs(TLI, RetTy, RetTys);
5261 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5262 SmallVector<SDValue, 4> ReturnValues;
5263 unsigned CurReg = 0;
5264 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5266 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5267 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5269 SDValue ReturnValue =
5270 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5271 RegisterVT, VT, AssertOp);
5272 ReturnValues.push_back(ReturnValue);
5276 setValue(CS.getInstruction(),
5277 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5278 DAG.getVTList(&RetTys[0], RetTys.size()),
5279 &ReturnValues[0], ReturnValues.size()));
5282 // Assign order to nodes here. If the call does not produce a result, it won't
5283 // be mapped to a SDNode and visit() will not assign it an order number.
5284 if (!Result.second.getNode()) {
5285 // As a special case, a null chain means that a tail call has been emitted and
5286 // the DAG root is already updated.
5289 AssignOrderingToNode(DAG.getRoot().getNode());
5291 DAG.setRoot(Result.second);
5293 AssignOrderingToNode(Result.second.getNode());
5297 // Insert a label at the end of the invoke call to mark the try range. This
5298 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5299 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5300 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5302 // Inform MachineModuleInfo of range.
5303 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5307 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5308 /// value is equal or not-equal to zero.
5309 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5310 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5312 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5313 if (IC->isEquality())
5314 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5315 if (C->isNullValue())
5317 // Unknown instruction.
5323 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5325 SelectionDAGBuilder &Builder) {
5327 // Check to see if this load can be trivially constant folded, e.g. if the
5328 // input is from a string literal.
5329 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5330 // Cast pointer to the type we really want to load.
5331 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5332 PointerType::getUnqual(LoadTy));
5334 if (const Constant *LoadCst =
5335 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5337 return Builder.getValue(LoadCst);
5340 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5341 // still constant memory, the input chain can be the entry node.
5343 bool ConstantMemory = false;
5345 // Do not serialize (non-volatile) loads of constant memory with anything.
5346 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5347 Root = Builder.DAG.getEntryNode();
5348 ConstantMemory = true;
5350 // Do not serialize non-volatile loads against each other.
5351 Root = Builder.DAG.getRoot();
5354 SDValue Ptr = Builder.getValue(PtrVal);
5355 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5356 Ptr, MachinePointerInfo(PtrVal),
5358 false /*nontemporal*/,
5359 false /*isinvariant*/, 1 /* align=1 */);
5361 if (!ConstantMemory)
5362 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5367 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5368 /// If so, return true and lower it, otherwise return false and it will be
5369 /// lowered like a normal call.
5370 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5371 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5372 if (I.getNumArgOperands() != 3)
5375 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5376 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5377 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5378 !I.getType()->isIntegerTy())
5381 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5383 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5384 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5385 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5386 bool ActuallyDoIt = true;
5389 switch (Size->getZExtValue()) {
5391 LoadVT = MVT::Other;
5393 ActuallyDoIt = false;
5397 LoadTy = Type::getInt16Ty(Size->getContext());
5401 LoadTy = Type::getInt32Ty(Size->getContext());
5405 LoadTy = Type::getInt64Ty(Size->getContext());
5409 LoadVT = MVT::v4i32;
5410 LoadTy = Type::getInt32Ty(Size->getContext());
5411 LoadTy = VectorType::get(LoadTy, 4);
5416 // This turns into unaligned loads. We only do this if the target natively
5417 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5418 // we'll only produce a small number of byte loads.
5420 // Require that we can find a legal MVT, and only do this if the target
5421 // supports unaligned loads of that type. Expanding into byte loads would
5423 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5424 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5425 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5426 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5427 ActuallyDoIt = false;
5431 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5432 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5434 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5436 EVT CallVT = TLI.getValueType(I.getType(), true);
5437 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5447 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5448 // Handle inline assembly differently.
5449 if (isa<InlineAsm>(I.getCalledValue())) {
5454 // See if any floating point values are being passed to this function. This is
5455 // used to emit an undefined reference to fltused on Windows.
5457 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0));
5458 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5459 if (FT->isVarArg() &&
5460 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) {
5461 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
5462 Type* T = I.getArgOperand(i)->getType();
5463 for (po_iterator<Type*> i = po_begin(T), e = po_end(T);
5465 if (!i->isFloatingPointTy()) continue;
5466 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true);
5472 const char *RenameFn = 0;
5473 if (Function *F = I.getCalledFunction()) {
5474 if (F->isDeclaration()) {
5475 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5476 if (unsigned IID = II->getIntrinsicID(F)) {
5477 RenameFn = visitIntrinsicCall(I, IID);
5482 if (unsigned IID = F->getIntrinsicID()) {
5483 RenameFn = visitIntrinsicCall(I, IID);
5489 // Check for well-known libc/libm calls. If the function is internal, it
5490 // can't be a library call.
5491 if (!F->hasLocalLinkage() && F->hasName()) {
5492 StringRef Name = F->getName();
5493 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") ||
5494 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") ||
5495 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) {
5496 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5497 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5498 I.getType() == I.getArgOperand(0)->getType() &&
5499 I.getType() == I.getArgOperand(1)->getType()) {
5500 SDValue LHS = getValue(I.getArgOperand(0));
5501 SDValue RHS = getValue(I.getArgOperand(1));
5502 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5503 LHS.getValueType(), LHS, RHS));
5506 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") ||
5507 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") ||
5508 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) {
5509 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5510 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5511 I.getType() == I.getArgOperand(0)->getType()) {
5512 SDValue Tmp = getValue(I.getArgOperand(0));
5513 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5514 Tmp.getValueType(), Tmp));
5517 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") ||
5518 (LibInfo->has(LibFunc::sinf) && Name == "sinf") ||
5519 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) {
5520 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5521 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5522 I.getType() == I.getArgOperand(0)->getType() &&
5523 I.onlyReadsMemory()) {
5524 SDValue Tmp = getValue(I.getArgOperand(0));
5525 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5526 Tmp.getValueType(), Tmp));
5529 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") ||
5530 (LibInfo->has(LibFunc::cosf) && Name == "cosf") ||
5531 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) {
5532 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5533 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5534 I.getType() == I.getArgOperand(0)->getType() &&
5535 I.onlyReadsMemory()) {
5536 SDValue Tmp = getValue(I.getArgOperand(0));
5537 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5538 Tmp.getValueType(), Tmp));
5541 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") ||
5542 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") ||
5543 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) {
5544 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5545 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5546 I.getType() == I.getArgOperand(0)->getType() &&
5547 I.onlyReadsMemory()) {
5548 SDValue Tmp = getValue(I.getArgOperand(0));
5549 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5550 Tmp.getValueType(), Tmp));
5553 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") ||
5554 (LibInfo->has(LibFunc::floorf) && Name == "floorf") ||
5555 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) {
5556 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5557 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5558 I.getType() == I.getArgOperand(0)->getType()) {
5559 SDValue Tmp = getValue(I.getArgOperand(0));
5560 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(),
5561 Tmp.getValueType(), Tmp));
5564 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") ||
5565 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") ||
5566 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) {
5567 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5568 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5569 I.getType() == I.getArgOperand(0)->getType()) {
5570 SDValue Tmp = getValue(I.getArgOperand(0));
5571 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(),
5572 Tmp.getValueType(), Tmp));
5575 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") ||
5576 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") ||
5577 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) {
5578 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5579 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5580 I.getType() == I.getArgOperand(0)->getType()) {
5581 SDValue Tmp = getValue(I.getArgOperand(0));
5582 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(),
5583 Tmp.getValueType(), Tmp));
5586 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") ||
5587 (LibInfo->has(LibFunc::rintf) && Name == "rintf") ||
5588 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) {
5589 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5590 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5591 I.getType() == I.getArgOperand(0)->getType()) {
5592 SDValue Tmp = getValue(I.getArgOperand(0));
5593 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(),
5594 Tmp.getValueType(), Tmp));
5597 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") ||
5598 (LibInfo->has(LibFunc::truncf) && Name == "truncf") ||
5599 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) {
5600 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5601 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5602 I.getType() == I.getArgOperand(0)->getType()) {
5603 SDValue Tmp = getValue(I.getArgOperand(0));
5604 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(),
5605 Tmp.getValueType(), Tmp));
5608 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") ||
5609 (LibInfo->has(LibFunc::log2f) && Name == "log2f") ||
5610 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) {
5611 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5612 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5613 I.getType() == I.getArgOperand(0)->getType()) {
5614 SDValue Tmp = getValue(I.getArgOperand(0));
5615 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(),
5616 Tmp.getValueType(), Tmp));
5619 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") ||
5620 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") ||
5621 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) {
5622 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5623 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5624 I.getType() == I.getArgOperand(0)->getType()) {
5625 SDValue Tmp = getValue(I.getArgOperand(0));
5626 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(),
5627 Tmp.getValueType(), Tmp));
5630 } else if (Name == "memcmp") {
5631 if (visitMemCmpCall(I))
5639 Callee = getValue(I.getCalledValue());
5641 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5643 // Check if we can potentially perform a tail call. More detailed checking is
5644 // be done within LowerCallTo, after more information about the call is known.
5645 LowerCallTo(&I, Callee, I.isTailCall());
5650 /// AsmOperandInfo - This contains information for each constraint that we are
5652 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5654 /// CallOperand - If this is the result output operand or a clobber
5655 /// this is null, otherwise it is the incoming operand to the CallInst.
5656 /// This gets modified as the asm is processed.
5657 SDValue CallOperand;
5659 /// AssignedRegs - If this is a register or register class operand, this
5660 /// contains the set of register corresponding to the operand.
5661 RegsForValue AssignedRegs;
5663 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5664 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5667 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers
5668 /// busy in OutputRegs/InputRegs.
5669 void MarkAllocatedRegs(bool isOutReg, bool isInReg,
5670 std::set<unsigned> &OutputRegs,
5671 std::set<unsigned> &InputRegs,
5672 const TargetRegisterInfo &TRI) const {
5674 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5675 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI);
5678 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i)
5679 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI);
5683 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5684 /// corresponds to. If there is no Value* for this operand, it returns
5686 EVT getCallOperandValEVT(LLVMContext &Context,
5687 const TargetLowering &TLI,
5688 const TargetData *TD) const {
5689 if (CallOperandVal == 0) return MVT::Other;
5691 if (isa<BasicBlock>(CallOperandVal))
5692 return TLI.getPointerTy();
5694 llvm::Type *OpTy = CallOperandVal->getType();
5696 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5697 // If this is an indirect operand, the operand is a pointer to the
5700 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5702 report_fatal_error("Indirect operand for inline asm not a pointer!");
5703 OpTy = PtrTy->getElementType();
5706 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5707 if (StructType *STy = dyn_cast<StructType>(OpTy))
5708 if (STy->getNumElements() == 1)
5709 OpTy = STy->getElementType(0);
5711 // If OpTy is not a single value, it may be a struct/union that we
5712 // can tile with integers.
5713 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5714 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5723 OpTy = IntegerType::get(Context, BitSize);
5728 return TLI.getValueType(OpTy, true);
5732 /// MarkRegAndAliases - Mark the specified register and all aliases in the
5734 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs,
5735 const TargetRegisterInfo &TRI) {
5736 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg");
5738 if (const unsigned *Aliases = TRI.getAliasSet(Reg))
5739 for (; *Aliases; ++Aliases)
5740 Regs.insert(*Aliases);
5744 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5746 } // end anonymous namespace
5748 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5749 /// specified operand. We prefer to assign virtual registers, to allow the
5750 /// register allocator to handle the assignment process. However, if the asm
5751 /// uses features that we can't model on machineinstrs, we have SDISel do the
5752 /// allocation. This produces generally horrible, but correct, code.
5754 /// OpInfo describes the operand.
5755 /// Input and OutputRegs are the set of already allocated physical registers.
5757 static void GetRegistersForValue(SelectionDAG &DAG,
5758 const TargetLowering &TLI,
5760 SDISelAsmOperandInfo &OpInfo,
5761 std::set<unsigned> &OutputRegs,
5762 std::set<unsigned> &InputRegs) {
5763 LLVMContext &Context = *DAG.getContext();
5765 // Compute whether this value requires an input register, an output register,
5767 bool isOutReg = false;
5768 bool isInReg = false;
5769 switch (OpInfo.Type) {
5770 case InlineAsm::isOutput:
5773 // If there is an input constraint that matches this, we need to reserve
5774 // the input register so no other inputs allocate to it.
5775 isInReg = OpInfo.hasMatchingInput();
5777 case InlineAsm::isInput:
5781 case InlineAsm::isClobber:
5788 MachineFunction &MF = DAG.getMachineFunction();
5789 SmallVector<unsigned, 4> Regs;
5791 // If this is a constraint for a single physreg, or a constraint for a
5792 // register class, find it.
5793 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5794 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5795 OpInfo.ConstraintVT);
5797 unsigned NumRegs = 1;
5798 if (OpInfo.ConstraintVT != MVT::Other) {
5799 // If this is a FP input in an integer register (or visa versa) insert a bit
5800 // cast of the input value. More generally, handle any case where the input
5801 // value disagrees with the register class we plan to stick this in.
5802 if (OpInfo.Type == InlineAsm::isInput &&
5803 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5804 // Try to convert to the first EVT that the reg class contains. If the
5805 // types are identical size, use a bitcast to convert (e.g. two differing
5807 EVT RegVT = *PhysReg.second->vt_begin();
5808 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5809 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5810 RegVT, OpInfo.CallOperand);
5811 OpInfo.ConstraintVT = RegVT;
5812 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5813 // If the input is a FP value and we want it in FP registers, do a
5814 // bitcast to the corresponding integer type. This turns an f64 value
5815 // into i64, which can be passed with two i32 values on a 32-bit
5817 RegVT = EVT::getIntegerVT(Context,
5818 OpInfo.ConstraintVT.getSizeInBits());
5819 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5820 RegVT, OpInfo.CallOperand);
5821 OpInfo.ConstraintVT = RegVT;
5825 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5829 EVT ValueVT = OpInfo.ConstraintVT;
5831 // If this is a constraint for a specific physical register, like {r17},
5833 if (unsigned AssignedReg = PhysReg.first) {
5834 const TargetRegisterClass *RC = PhysReg.second;
5835 if (OpInfo.ConstraintVT == MVT::Other)
5836 ValueVT = *RC->vt_begin();
5838 // Get the actual register value type. This is important, because the user
5839 // may have asked for (e.g.) the AX register in i32 type. We need to
5840 // remember that AX is actually i16 to get the right extension.
5841 RegVT = *RC->vt_begin();
5843 // This is a explicit reference to a physical register.
5844 Regs.push_back(AssignedReg);
5846 // If this is an expanded reference, add the rest of the regs to Regs.
5848 TargetRegisterClass::iterator I = RC->begin();
5849 for (; *I != AssignedReg; ++I)
5850 assert(I != RC->end() && "Didn't find reg!");
5852 // Already added the first reg.
5854 for (; NumRegs; --NumRegs, ++I) {
5855 assert(I != RC->end() && "Ran out of registers to allocate!");
5860 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5861 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
5862 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI);
5866 // Otherwise, if this was a reference to an LLVM register class, create vregs
5867 // for this reference.
5868 if (const TargetRegisterClass *RC = PhysReg.second) {
5869 RegVT = *RC->vt_begin();
5870 if (OpInfo.ConstraintVT == MVT::Other)
5873 // Create the appropriate number of virtual registers.
5874 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5875 for (; NumRegs; --NumRegs)
5876 Regs.push_back(RegInfo.createVirtualRegister(RC));
5878 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5882 // Otherwise, we couldn't allocate enough registers for this.
5885 /// visitInlineAsm - Handle a call to an InlineAsm object.
5887 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5888 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5890 /// ConstraintOperands - Information about all of the constraints.
5891 SDISelAsmOperandInfoVector ConstraintOperands;
5893 std::set<unsigned> OutputRegs, InputRegs;
5895 TargetLowering::AsmOperandInfoVector
5896 TargetConstraints = TLI.ParseConstraints(CS);
5898 bool hasMemory = false;
5900 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5901 unsigned ResNo = 0; // ResNo - The result number of the next output.
5902 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5903 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5904 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5906 EVT OpVT = MVT::Other;
5908 // Compute the value type for each operand.
5909 switch (OpInfo.Type) {
5910 case InlineAsm::isOutput:
5911 // Indirect outputs just consume an argument.
5912 if (OpInfo.isIndirect) {
5913 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5917 // The return value of the call is this value. As such, there is no
5918 // corresponding argument.
5919 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5920 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5921 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5923 assert(ResNo == 0 && "Asm only has one result!");
5924 OpVT = TLI.getValueType(CS.getType());
5928 case InlineAsm::isInput:
5929 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5931 case InlineAsm::isClobber:
5936 // If this is an input or an indirect output, process the call argument.
5937 // BasicBlocks are labels, currently appearing only in asm's.
5938 if (OpInfo.CallOperandVal) {
5939 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5940 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5942 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5945 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5948 OpInfo.ConstraintVT = OpVT;
5950 // Indirect operand accesses access memory.
5951 if (OpInfo.isIndirect)
5954 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5955 TargetLowering::ConstraintType
5956 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5957 if (CType == TargetLowering::C_Memory) {
5965 SDValue Chain, Flag;
5967 // We won't need to flush pending loads if this asm doesn't touch
5968 // memory and is nonvolatile.
5969 if (hasMemory || IA->hasSideEffects())
5972 Chain = DAG.getRoot();
5974 // Second pass over the constraints: compute which constraint option to use
5975 // and assign registers to constraints that want a specific physreg.
5976 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5977 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5979 // If this is an output operand with a matching input operand, look up the
5980 // matching input. If their types mismatch, e.g. one is an integer, the
5981 // other is floating point, or their sizes are different, flag it as an
5983 if (OpInfo.hasMatchingInput()) {
5984 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5986 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5987 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5988 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5989 OpInfo.ConstraintVT);
5990 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5991 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5992 Input.ConstraintVT);
5993 if ((OpInfo.ConstraintVT.isInteger() !=
5994 Input.ConstraintVT.isInteger()) ||
5995 (MatchRC.second != InputRC.second)) {
5996 report_fatal_error("Unsupported asm: input constraint"
5997 " with a matching output constraint of"
5998 " incompatible type!");
6000 Input.ConstraintVT = OpInfo.ConstraintVT;
6004 // Compute the constraint code and ConstraintType to use.
6005 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6007 // If this is a memory input, and if the operand is not indirect, do what we
6008 // need to to provide an address for the memory input.
6009 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6010 !OpInfo.isIndirect) {
6011 assert((OpInfo.isMultipleAlternative ||
6012 (OpInfo.Type == InlineAsm::isInput)) &&
6013 "Can only indirectify direct input operands!");
6015 // Memory operands really want the address of the value. If we don't have
6016 // an indirect input, put it in the constpool if we can, otherwise spill
6017 // it to a stack slot.
6018 // TODO: This isn't quite right. We need to handle these according to
6019 // the addressing mode that the constraint wants. Also, this may take
6020 // an additional register for the computation and we don't want that
6023 // If the operand is a float, integer, or vector constant, spill to a
6024 // constant pool entry to get its address.
6025 const Value *OpVal = OpInfo.CallOperandVal;
6026 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6027 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6028 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6029 TLI.getPointerTy());
6031 // Otherwise, create a stack slot and emit a store to it before the
6033 Type *Ty = OpVal->getType();
6034 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
6035 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
6036 MachineFunction &MF = DAG.getMachineFunction();
6037 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6038 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
6039 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6040 OpInfo.CallOperand, StackSlot,
6041 MachinePointerInfo::getFixedStack(SSFI),
6043 OpInfo.CallOperand = StackSlot;
6046 // There is no longer a Value* corresponding to this operand.
6047 OpInfo.CallOperandVal = 0;
6049 // It is now an indirect operand.
6050 OpInfo.isIndirect = true;
6053 // If this constraint is for a specific register, allocate it before
6055 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6056 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
6060 // Second pass - Loop over all of the operands, assigning virtual or physregs
6061 // to register class operands.
6062 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6063 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6065 // C_Register operands have already been allocated, Other/Memory don't need
6067 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6068 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs,
6072 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6073 std::vector<SDValue> AsmNodeOperands;
6074 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6075 AsmNodeOperands.push_back(
6076 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6077 TLI.getPointerTy()));
6079 // If we have a !srcloc metadata node associated with it, we want to attach
6080 // this to the ultimately generated inline asm machineinstr. To do this, we
6081 // pass in the third operand as this (potentially null) inline asm MDNode.
6082 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6083 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6085 // Remember the HasSideEffect and AlignStack bits as operand 3.
6086 unsigned ExtraInfo = 0;
6087 if (IA->hasSideEffects())
6088 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6089 if (IA->isAlignStack())
6090 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6091 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6092 TLI.getPointerTy()));
6094 // Loop over all of the inputs, copying the operand values into the
6095 // appropriate registers and processing the output regs.
6096 RegsForValue RetValRegs;
6098 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6099 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6101 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6102 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6104 switch (OpInfo.Type) {
6105 case InlineAsm::isOutput: {
6106 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6107 OpInfo.ConstraintType != TargetLowering::C_Register) {
6108 // Memory output, or 'other' output (e.g. 'X' constraint).
6109 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6111 // Add information to the INLINEASM node to know about this output.
6112 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6113 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6114 TLI.getPointerTy()));
6115 AsmNodeOperands.push_back(OpInfo.CallOperand);
6119 // Otherwise, this is a register or register class output.
6121 // Copy the output from the appropriate register. Find a register that
6123 if (OpInfo.AssignedRegs.Regs.empty()) {
6124 LLVMContext &Ctx = *DAG.getContext();
6125 Ctx.emitError(CS.getInstruction(),
6126 "couldn't allocate output register for constraint '" +
6127 Twine(OpInfo.ConstraintCode) + "'");
6131 // If this is an indirect operand, store through the pointer after the
6133 if (OpInfo.isIndirect) {
6134 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6135 OpInfo.CallOperandVal));
6137 // This is the result value of the call.
6138 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6139 // Concatenate this output onto the outputs list.
6140 RetValRegs.append(OpInfo.AssignedRegs);
6143 // Add information to the INLINEASM node to know that this register is
6145 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6146 InlineAsm::Kind_RegDefEarlyClobber :
6147 InlineAsm::Kind_RegDef,
6154 case InlineAsm::isInput: {
6155 SDValue InOperandVal = OpInfo.CallOperand;
6157 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6158 // If this is required to match an output register we have already set,
6159 // just use its register.
6160 unsigned OperandNo = OpInfo.getMatchedOperand();
6162 // Scan until we find the definition we already emitted of this operand.
6163 // When we find it, create a RegsForValue operand.
6164 unsigned CurOp = InlineAsm::Op_FirstOperand;
6165 for (; OperandNo; --OperandNo) {
6166 // Advance to the next operand.
6168 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6169 assert((InlineAsm::isRegDefKind(OpFlag) ||
6170 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6171 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6172 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6176 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6177 if (InlineAsm::isRegDefKind(OpFlag) ||
6178 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6179 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6180 if (OpInfo.isIndirect) {
6181 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6182 LLVMContext &Ctx = *DAG.getContext();
6183 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6184 " don't know how to handle tied "
6185 "indirect register inputs");
6188 RegsForValue MatchedRegs;
6189 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6190 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6191 MatchedRegs.RegVTs.push_back(RegVT);
6192 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6193 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6195 MatchedRegs.Regs.push_back
6196 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6198 // Use the produced MatchedRegs object to
6199 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6201 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6202 true, OpInfo.getMatchedOperand(),
6203 DAG, AsmNodeOperands);
6207 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6208 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6209 "Unexpected number of operands");
6210 // Add information to the INLINEASM node to know about this input.
6211 // See InlineAsm.h isUseOperandTiedToDef.
6212 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6213 OpInfo.getMatchedOperand());
6214 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6215 TLI.getPointerTy()));
6216 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6220 // Treat indirect 'X' constraint as memory.
6221 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6223 OpInfo.ConstraintType = TargetLowering::C_Memory;
6225 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6226 std::vector<SDValue> Ops;
6227 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6230 LLVMContext &Ctx = *DAG.getContext();
6231 Ctx.emitError(CS.getInstruction(),
6232 "invalid operand for inline asm constraint '" +
6233 Twine(OpInfo.ConstraintCode) + "'");
6237 // Add information to the INLINEASM node to know about this input.
6238 unsigned ResOpType =
6239 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6240 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6241 TLI.getPointerTy()));
6242 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6246 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6247 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6248 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6249 "Memory operands expect pointer values");
6251 // Add information to the INLINEASM node to know about this input.
6252 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6253 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6254 TLI.getPointerTy()));
6255 AsmNodeOperands.push_back(InOperandVal);
6259 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6260 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6261 "Unknown constraint type!");
6262 assert(!OpInfo.isIndirect &&
6263 "Don't know how to handle indirect register inputs yet!");
6265 // Copy the input into the appropriate registers.
6266 if (OpInfo.AssignedRegs.Regs.empty()) {
6267 LLVMContext &Ctx = *DAG.getContext();
6268 Ctx.emitError(CS.getInstruction(),
6269 "couldn't allocate input reg for constraint '" +
6270 Twine(OpInfo.ConstraintCode) + "'");
6274 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6277 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6278 DAG, AsmNodeOperands);
6281 case InlineAsm::isClobber: {
6282 // Add the clobbered value to the operand list, so that the register
6283 // allocator is aware that the physreg got clobbered.
6284 if (!OpInfo.AssignedRegs.Regs.empty())
6285 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6293 // Finish up input operands. Set the input chain and add the flag last.
6294 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6295 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6297 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6298 DAG.getVTList(MVT::Other, MVT::Glue),
6299 &AsmNodeOperands[0], AsmNodeOperands.size());
6300 Flag = Chain.getValue(1);
6302 // If this asm returns a register value, copy the result from that register
6303 // and set it as the value of the call.
6304 if (!RetValRegs.Regs.empty()) {
6305 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6308 // FIXME: Why don't we do this for inline asms with MRVs?
6309 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6310 EVT ResultType = TLI.getValueType(CS.getType());
6312 // If any of the results of the inline asm is a vector, it may have the
6313 // wrong width/num elts. This can happen for register classes that can
6314 // contain multiple different value types. The preg or vreg allocated may
6315 // not have the same VT as was expected. Convert it to the right type
6316 // with bit_convert.
6317 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6318 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6321 } else if (ResultType != Val.getValueType() &&
6322 ResultType.isInteger() && Val.getValueType().isInteger()) {
6323 // If a result value was tied to an input value, the computed result may
6324 // have a wider width than the expected result. Extract the relevant
6326 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6329 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6332 setValue(CS.getInstruction(), Val);
6333 // Don't need to use this as a chain in this case.
6334 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6338 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6340 // Process indirect outputs, first output all of the flagged copies out of
6342 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6343 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6344 const Value *Ptr = IndirectStoresToEmit[i].second;
6345 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6347 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6350 // Emit the non-flagged stores from the physregs.
6351 SmallVector<SDValue, 8> OutChains;
6352 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6353 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6354 StoresToEmit[i].first,
6355 getValue(StoresToEmit[i].second),
6356 MachinePointerInfo(StoresToEmit[i].second),
6358 OutChains.push_back(Val);
6361 if (!OutChains.empty())
6362 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6363 &OutChains[0], OutChains.size());
6368 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6369 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6370 MVT::Other, getRoot(),
6371 getValue(I.getArgOperand(0)),
6372 DAG.getSrcValue(I.getArgOperand(0))));
6375 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6376 const TargetData &TD = *TLI.getTargetData();
6377 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6378 getRoot(), getValue(I.getOperand(0)),
6379 DAG.getSrcValue(I.getOperand(0)),
6380 TD.getABITypeAlignment(I.getType()));
6382 DAG.setRoot(V.getValue(1));
6385 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6386 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6387 MVT::Other, getRoot(),
6388 getValue(I.getArgOperand(0)),
6389 DAG.getSrcValue(I.getArgOperand(0))));
6392 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6393 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6394 MVT::Other, getRoot(),
6395 getValue(I.getArgOperand(0)),
6396 getValue(I.getArgOperand(1)),
6397 DAG.getSrcValue(I.getArgOperand(0)),
6398 DAG.getSrcValue(I.getArgOperand(1))));
6401 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6402 /// implementation, which just calls LowerCall.
6403 /// FIXME: When all targets are
6404 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6405 std::pair<SDValue, SDValue>
6406 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6407 bool RetSExt, bool RetZExt, bool isVarArg,
6408 bool isInreg, unsigned NumFixedArgs,
6409 CallingConv::ID CallConv, bool isTailCall,
6410 bool isReturnValueUsed,
6412 ArgListTy &Args, SelectionDAG &DAG,
6413 DebugLoc dl) const {
6414 // Handle all of the outgoing arguments.
6415 SmallVector<ISD::OutputArg, 32> Outs;
6416 SmallVector<SDValue, 32> OutVals;
6417 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6418 SmallVector<EVT, 4> ValueVTs;
6419 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6420 for (unsigned Value = 0, NumValues = ValueVTs.size();
6421 Value != NumValues; ++Value) {
6422 EVT VT = ValueVTs[Value];
6423 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6424 SDValue Op = SDValue(Args[i].Node.getNode(),
6425 Args[i].Node.getResNo() + Value);
6426 ISD::ArgFlagsTy Flags;
6427 unsigned OriginalAlignment =
6428 getTargetData()->getABITypeAlignment(ArgTy);
6434 if (Args[i].isInReg)
6438 if (Args[i].isByVal) {
6440 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6441 Type *ElementTy = Ty->getElementType();
6442 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6443 // For ByVal, alignment should come from FE. BE will guess if this
6444 // info is not there but there are cases it cannot get right.
6445 unsigned FrameAlign;
6446 if (Args[i].Alignment)
6447 FrameAlign = Args[i].Alignment;
6449 FrameAlign = getByValTypeAlignment(ElementTy);
6450 Flags.setByValAlign(FrameAlign);
6454 Flags.setOrigAlign(OriginalAlignment);
6456 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6457 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6458 SmallVector<SDValue, 4> Parts(NumParts);
6459 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6462 ExtendKind = ISD::SIGN_EXTEND;
6463 else if (Args[i].isZExt)
6464 ExtendKind = ISD::ZERO_EXTEND;
6466 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6467 PartVT, ExtendKind);
6469 for (unsigned j = 0; j != NumParts; ++j) {
6470 // if it isn't first piece, alignment must be 1
6471 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6473 if (NumParts > 1 && j == 0)
6474 MyFlags.Flags.setSplit();
6476 MyFlags.Flags.setOrigAlign(1);
6478 Outs.push_back(MyFlags);
6479 OutVals.push_back(Parts[j]);
6484 // Handle the incoming return values from the call.
6485 SmallVector<ISD::InputArg, 32> Ins;
6486 SmallVector<EVT, 4> RetTys;
6487 ComputeValueVTs(*this, RetTy, RetTys);
6488 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6490 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6491 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6492 for (unsigned i = 0; i != NumRegs; ++i) {
6493 ISD::InputArg MyFlags;
6494 MyFlags.VT = RegisterVT.getSimpleVT();
6495 MyFlags.Used = isReturnValueUsed;
6497 MyFlags.Flags.setSExt();
6499 MyFlags.Flags.setZExt();
6501 MyFlags.Flags.setInReg();
6502 Ins.push_back(MyFlags);
6506 SmallVector<SDValue, 4> InVals;
6507 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
6508 Outs, OutVals, Ins, dl, DAG, InVals);
6510 // Verify that the target's LowerCall behaved as expected.
6511 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6512 "LowerCall didn't return a valid chain!");
6513 assert((!isTailCall || InVals.empty()) &&
6514 "LowerCall emitted a return value for a tail call!");
6515 assert((isTailCall || InVals.size() == Ins.size()) &&
6516 "LowerCall didn't emit the correct number of values!");
6518 // For a tail call, the return value is merely live-out and there aren't
6519 // any nodes in the DAG representing it. Return a special value to
6520 // indicate that a tail call has been emitted and no more Instructions
6521 // should be processed in the current block.
6524 return std::make_pair(SDValue(), SDValue());
6527 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6528 assert(InVals[i].getNode() &&
6529 "LowerCall emitted a null value!");
6530 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6531 "LowerCall emitted a value with the wrong type!");
6534 // Collect the legal value parts into potentially illegal values
6535 // that correspond to the original function's return values.
6536 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6538 AssertOp = ISD::AssertSext;
6540 AssertOp = ISD::AssertZext;
6541 SmallVector<SDValue, 4> ReturnValues;
6542 unsigned CurReg = 0;
6543 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6545 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6546 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6548 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6549 NumRegs, RegisterVT, VT,
6554 // For a function returning void, there is no return value. We can't create
6555 // such a node, so we just return a null return value in that case. In
6556 // that case, nothing will actually look at the value.
6557 if (ReturnValues.empty())
6558 return std::make_pair(SDValue(), Chain);
6560 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6561 DAG.getVTList(&RetTys[0], RetTys.size()),
6562 &ReturnValues[0], ReturnValues.size());
6563 return std::make_pair(Res, Chain);
6566 void TargetLowering::LowerOperationWrapper(SDNode *N,
6567 SmallVectorImpl<SDValue> &Results,
6568 SelectionDAG &DAG) const {
6569 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6571 Results.push_back(Res);
6574 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6575 llvm_unreachable("LowerOperation not implemented for this target!");
6579 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6580 SDValue Op = getNonRegisterValue(V);
6581 assert((Op.getOpcode() != ISD::CopyFromReg ||
6582 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6583 "Copy from a reg to the same reg!");
6584 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6586 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6587 SDValue Chain = DAG.getEntryNode();
6588 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6589 PendingExports.push_back(Chain);
6592 #include "llvm/CodeGen/SelectionDAGISel.h"
6594 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6595 /// entry block, return true. This includes arguments used by switches, since
6596 /// the switch may expand into multiple basic blocks.
6597 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6598 // With FastISel active, we may be splitting blocks, so force creation
6599 // of virtual registers for all non-dead arguments.
6601 return A->use_empty();
6603 const BasicBlock *Entry = A->getParent()->begin();
6604 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6606 const User *U = *UI;
6607 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6608 return false; // Use not in entry block.
6613 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6614 // If this is the entry block, emit arguments.
6615 const Function &F = *LLVMBB->getParent();
6616 SelectionDAG &DAG = SDB->DAG;
6617 DebugLoc dl = SDB->getCurDebugLoc();
6618 const TargetData *TD = TLI.getTargetData();
6619 SmallVector<ISD::InputArg, 16> Ins;
6621 // Check whether the function can return without sret-demotion.
6622 SmallVector<ISD::OutputArg, 4> Outs;
6623 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6626 if (!FuncInfo->CanLowerReturn) {
6627 // Put in an sret pointer parameter before all the other parameters.
6628 SmallVector<EVT, 1> ValueVTs;
6629 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6631 // NOTE: Assuming that a pointer will never break down to more than one VT
6633 ISD::ArgFlagsTy Flags;
6635 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6636 ISD::InputArg RetArg(Flags, RegisterVT, true);
6637 Ins.push_back(RetArg);
6640 // Set up the incoming argument description vector.
6642 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6643 I != E; ++I, ++Idx) {
6644 SmallVector<EVT, 4> ValueVTs;
6645 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6646 bool isArgValueUsed = !I->use_empty();
6647 for (unsigned Value = 0, NumValues = ValueVTs.size();
6648 Value != NumValues; ++Value) {
6649 EVT VT = ValueVTs[Value];
6650 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6651 ISD::ArgFlagsTy Flags;
6652 unsigned OriginalAlignment =
6653 TD->getABITypeAlignment(ArgTy);
6655 if (F.paramHasAttr(Idx, Attribute::ZExt))
6657 if (F.paramHasAttr(Idx, Attribute::SExt))
6659 if (F.paramHasAttr(Idx, Attribute::InReg))
6661 if (F.paramHasAttr(Idx, Attribute::StructRet))
6663 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6665 PointerType *Ty = cast<PointerType>(I->getType());
6666 Type *ElementTy = Ty->getElementType();
6667 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6668 // For ByVal, alignment should be passed from FE. BE will guess if
6669 // this info is not there but there are cases it cannot get right.
6670 unsigned FrameAlign;
6671 if (F.getParamAlignment(Idx))
6672 FrameAlign = F.getParamAlignment(Idx);
6674 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6675 Flags.setByValAlign(FrameAlign);
6677 if (F.paramHasAttr(Idx, Attribute::Nest))
6679 Flags.setOrigAlign(OriginalAlignment);
6681 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6682 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6683 for (unsigned i = 0; i != NumRegs; ++i) {
6684 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6685 if (NumRegs > 1 && i == 0)
6686 MyFlags.Flags.setSplit();
6687 // if it isn't first piece, alignment must be 1
6689 MyFlags.Flags.setOrigAlign(1);
6690 Ins.push_back(MyFlags);
6695 // Call the target to set up the argument values.
6696 SmallVector<SDValue, 8> InVals;
6697 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6701 // Verify that the target's LowerFormalArguments behaved as expected.
6702 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6703 "LowerFormalArguments didn't return a valid chain!");
6704 assert(InVals.size() == Ins.size() &&
6705 "LowerFormalArguments didn't emit the correct number of values!");
6707 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6708 assert(InVals[i].getNode() &&
6709 "LowerFormalArguments emitted a null value!");
6710 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6711 "LowerFormalArguments emitted a value with the wrong type!");
6715 // Update the DAG with the new chain value resulting from argument lowering.
6716 DAG.setRoot(NewRoot);
6718 // Set up the argument values.
6721 if (!FuncInfo->CanLowerReturn) {
6722 // Create a virtual register for the sret pointer, and put in a copy
6723 // from the sret argument into it.
6724 SmallVector<EVT, 1> ValueVTs;
6725 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6726 EVT VT = ValueVTs[0];
6727 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6728 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6729 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6730 RegVT, VT, AssertOp);
6732 MachineFunction& MF = SDB->DAG.getMachineFunction();
6733 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6734 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6735 FuncInfo->DemoteRegister = SRetReg;
6736 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6738 DAG.setRoot(NewRoot);
6740 // i indexes lowered arguments. Bump it past the hidden sret argument.
6741 // Idx indexes LLVM arguments. Don't touch it.
6745 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6747 SmallVector<SDValue, 4> ArgValues;
6748 SmallVector<EVT, 4> ValueVTs;
6749 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6750 unsigned NumValues = ValueVTs.size();
6752 // If this argument is unused then remember its value. It is used to generate
6753 // debugging information.
6754 if (I->use_empty() && NumValues)
6755 SDB->setUnusedArgValue(I, InVals[i]);
6757 for (unsigned Val = 0; Val != NumValues; ++Val) {
6758 EVT VT = ValueVTs[Val];
6759 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6760 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6762 if (!I->use_empty()) {
6763 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6764 if (F.paramHasAttr(Idx, Attribute::SExt))
6765 AssertOp = ISD::AssertSext;
6766 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6767 AssertOp = ISD::AssertZext;
6769 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6770 NumParts, PartVT, VT,
6777 // We don't need to do anything else for unused arguments.
6778 if (ArgValues.empty())
6781 // Note down frame index.
6782 if (FrameIndexSDNode *FI =
6783 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6784 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6786 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6787 SDB->getCurDebugLoc());
6789 SDB->setValue(I, Res);
6790 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6791 if (LoadSDNode *LNode =
6792 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6793 if (FrameIndexSDNode *FI =
6794 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6795 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6798 // If this argument is live outside of the entry block, insert a copy from
6799 // wherever we got it to the vreg that other BB's will reference it as.
6800 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6801 // If we can, though, try to skip creating an unnecessary vreg.
6802 // FIXME: This isn't very clean... it would be nice to make this more
6803 // general. It's also subtly incompatible with the hacks FastISel
6805 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6806 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6807 FuncInfo->ValueMap[I] = Reg;
6811 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6812 FuncInfo->InitializeRegForValue(I);
6813 SDB->CopyToExportRegsIfNeeded(I);
6817 assert(i == InVals.size() && "Argument register count mismatch!");
6819 // Finally, if the target has anything special to do, allow it to do so.
6820 // FIXME: this should insert code into the DAG!
6821 EmitFunctionEntryCode();
6824 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6825 /// ensure constants are generated when needed. Remember the virtual registers
6826 /// that need to be added to the Machine PHI nodes as input. We cannot just
6827 /// directly add them, because expansion might result in multiple MBB's for one
6828 /// BB. As such, the start of the BB might correspond to a different MBB than
6832 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6833 const TerminatorInst *TI = LLVMBB->getTerminator();
6835 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6837 // Check successor nodes' PHI nodes that expect a constant to be available
6839 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6840 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6841 if (!isa<PHINode>(SuccBB->begin())) continue;
6842 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6844 // If this terminator has multiple identical successors (common for
6845 // switches), only handle each succ once.
6846 if (!SuccsHandled.insert(SuccMBB)) continue;
6848 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6850 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6851 // nodes and Machine PHI nodes, but the incoming operands have not been
6853 for (BasicBlock::const_iterator I = SuccBB->begin();
6854 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6855 // Ignore dead phi's.
6856 if (PN->use_empty()) continue;
6859 if (PN->getType()->isEmptyTy())
6863 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6865 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6866 unsigned &RegOut = ConstantsOut[C];
6868 RegOut = FuncInfo.CreateRegs(C->getType());
6869 CopyValueToVirtualRegister(C, RegOut);
6873 DenseMap<const Value *, unsigned>::iterator I =
6874 FuncInfo.ValueMap.find(PHIOp);
6875 if (I != FuncInfo.ValueMap.end())
6878 assert(isa<AllocaInst>(PHIOp) &&
6879 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6880 "Didn't codegen value into a register!??");
6881 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6882 CopyValueToVirtualRegister(PHIOp, Reg);
6886 // Remember that this register needs to added to the machine PHI node as
6887 // the input for this MBB.
6888 SmallVector<EVT, 4> ValueVTs;
6889 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6890 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6891 EVT VT = ValueVTs[vti];
6892 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6893 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6894 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6895 Reg += NumRegisters;
6899 ConstantsOut.clear();