1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isInteger()) {
202 if (ValueVT.bitsLT(PartEVT)) {
203 // For a truncate, see if we have any information to
204 // indicate whether the truncated bits will always be
205 // zero or sign-extension.
206 if (AssertOp != ISD::DELETED_NODE)
207 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
208 DAG.getValueType(ValueVT));
209 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
211 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
214 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
215 // FP_ROUND's are always exact here.
216 if (ValueVT.bitsLT(Val.getValueType()))
218 ISD::FP_ROUND, DL, ValueVT, Val,
219 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
221 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
224 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
225 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
227 llvm_unreachable("Unknown mismatch!");
230 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
231 const Twine &ErrMsg) {
232 const Instruction *I = dyn_cast_or_null<Instruction>(V);
234 return Ctx.emitError(ErrMsg);
236 const char *AsmError = ", possible invalid constraint for vector type";
237 if (const CallInst *CI = dyn_cast<CallInst>(I))
238 if (isa<InlineAsm>(CI->getCalledValue()))
239 return Ctx.emitError(I, ErrMsg + AsmError);
241 return Ctx.emitError(I, ErrMsg);
244 /// getCopyFromPartsVector - Create a value that contains the specified legal
245 /// parts combined into the value they represent. If the parts combine to a
246 /// type larger then ValueVT then AssertOp can be used to specify whether the
247 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
248 /// ValueVT (ISD::AssertSext).
249 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
250 const SDValue *Parts, unsigned NumParts,
251 MVT PartVT, EVT ValueVT, const Value *V) {
252 assert(ValueVT.isVector() && "Not a vector value");
253 assert(NumParts > 0 && "No parts to assemble!");
254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
255 SDValue Val = Parts[0];
257 // Handle a multi-element vector.
261 unsigned NumIntermediates;
263 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
264 NumIntermediates, RegisterVT);
265 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
266 NumParts = NumRegs; // Silence a compiler warning.
267 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
268 assert(RegisterVT.getSizeInBits() ==
269 Parts[0].getSimpleValueType().getSizeInBits() &&
270 "Part type sizes don't match!");
272 // Assemble the parts into intermediate operands.
273 SmallVector<SDValue, 8> Ops(NumIntermediates);
274 if (NumIntermediates == NumParts) {
275 // If the register was not expanded, truncate or copy the value,
277 for (unsigned i = 0; i != NumParts; ++i)
278 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
279 PartVT, IntermediateVT, V);
280 } else if (NumParts > 0) {
281 // If the intermediate type was expanded, build the intermediate
282 // operands from the parts.
283 assert(NumParts % NumIntermediates == 0 &&
284 "Must expand into a divisible number of parts!");
285 unsigned Factor = NumParts / NumIntermediates;
286 for (unsigned i = 0; i != NumIntermediates; ++i)
287 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
288 PartVT, IntermediateVT, V);
291 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
292 // intermediate operands.
293 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
298 // There is now one part, held in Val. Correct it to match ValueVT.
299 EVT PartEVT = Val.getValueType();
301 if (PartEVT == ValueVT)
304 if (PartEVT.isVector()) {
305 // If the element type of the source/dest vectors are the same, but the
306 // parts vector has more elements than the value vector, then we have a
307 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
309 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
310 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
311 "Cannot narrow, it would be a lossy transformation");
313 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
314 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
317 // Vector/Vector bitcast.
318 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
319 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
321 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
322 "Cannot handle this kind of promotion");
323 // Promoted vector extract
324 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
328 // Trivial bitcast if the types are the same size and the destination
329 // vector type is legal.
330 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
331 TLI.isTypeLegal(ValueVT))
332 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
334 // Handle cases such as i8 -> <1 x i1>
335 if (ValueVT.getVectorNumElements() != 1) {
336 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
337 "non-trivial scalar-to-vector conversion");
338 return DAG.getUNDEF(ValueVT);
341 if (ValueVT.getVectorNumElements() == 1 &&
342 ValueVT.getVectorElementType() != PartEVT)
343 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
345 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
348 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
349 SDValue Val, SDValue *Parts, unsigned NumParts,
350 MVT PartVT, const Value *V);
352 /// getCopyToParts - Create a series of nodes that contain the specified value
353 /// split into legal parts. If the parts contain more bits than Val, then, for
354 /// integers, ExtendKind can be used to specify how to generate the extra bits.
355 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
356 SDValue Val, SDValue *Parts, unsigned NumParts,
357 MVT PartVT, const Value *V,
358 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
359 EVT ValueVT = Val.getValueType();
361 // Handle the vector case separately.
362 if (ValueVT.isVector())
363 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
365 unsigned PartBits = PartVT.getSizeInBits();
366 unsigned OrigNumParts = NumParts;
367 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
368 "Copying to an illegal type!");
373 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
374 EVT PartEVT = PartVT;
375 if (PartEVT == ValueVT) {
376 assert(NumParts == 1 && "No-op copy with multiple parts!");
381 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
382 // If the parts cover more bits than the value has, promote the value.
383 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
384 assert(NumParts == 1 && "Do not know what to promote to!");
385 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
387 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
388 ValueVT.isInteger() &&
389 "Unknown mismatch!");
390 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
391 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
392 if (PartVT == MVT::x86mmx)
393 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
395 } else if (PartBits == ValueVT.getSizeInBits()) {
396 // Different types of the same size.
397 assert(NumParts == 1 && PartEVT != ValueVT);
398 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
399 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
400 // If the parts cover less bits than value has, truncate the value.
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
410 // The value may have changed - recompute ValueVT.
411 ValueVT = Val.getValueType();
412 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
413 "Failed to tile the value with PartVT!");
416 if (PartEVT != ValueVT)
417 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
418 "scalar-to-vector conversion failed");
424 // Expand the value into multiple parts.
425 if (NumParts & (NumParts - 1)) {
426 // The number of parts is not a power of 2. Split off and copy the tail.
427 assert(PartVT.isInteger() && ValueVT.isInteger() &&
428 "Do not know what to expand to!");
429 unsigned RoundParts = 1 << Log2_32(NumParts);
430 unsigned RoundBits = RoundParts * PartBits;
431 unsigned OddParts = NumParts - RoundParts;
432 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
433 DAG.getIntPtrConstant(RoundBits, DL));
434 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
436 if (DAG.getDataLayout().isBigEndian())
437 // The odd parts were reversed by getCopyToParts - unreverse them.
438 std::reverse(Parts + RoundParts, Parts + NumParts);
440 NumParts = RoundParts;
441 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
442 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
445 // The number of parts is a power of 2. Repeatedly bisect the value using
447 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
448 EVT::getIntegerVT(*DAG.getContext(),
449 ValueVT.getSizeInBits()),
452 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
453 for (unsigned i = 0; i < NumParts; i += StepSize) {
454 unsigned ThisBits = StepSize * PartBits / 2;
455 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
456 SDValue &Part0 = Parts[i];
457 SDValue &Part1 = Parts[i+StepSize/2];
459 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
460 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
461 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
462 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
464 if (ThisBits == PartBits && ThisVT != PartVT) {
465 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
466 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
471 if (DAG.getDataLayout().isBigEndian())
472 std::reverse(Parts, Parts + OrigNumParts);
476 /// getCopyToPartsVector - Create a series of nodes that contain the specified
477 /// value split into legal parts.
478 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
479 SDValue Val, SDValue *Parts, unsigned NumParts,
480 MVT PartVT, const Value *V) {
481 EVT ValueVT = Val.getValueType();
482 assert(ValueVT.isVector() && "Not a vector");
483 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
486 EVT PartEVT = PartVT;
487 if (PartEVT == ValueVT) {
489 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
490 // Bitconvert vector->vector case.
491 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
492 } else if (PartVT.isVector() &&
493 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
494 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
495 EVT ElementVT = PartVT.getVectorElementType();
496 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
498 SmallVector<SDValue, 16> Ops;
499 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
500 Ops.push_back(DAG.getNode(
501 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
502 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
504 for (unsigned i = ValueVT.getVectorNumElements(),
505 e = PartVT.getVectorNumElements(); i != e; ++i)
506 Ops.push_back(DAG.getUNDEF(ElementVT));
508 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
510 // FIXME: Use CONCAT for 2x -> 4x.
512 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
513 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
514 } else if (PartVT.isVector() &&
515 PartEVT.getVectorElementType().bitsGE(
516 ValueVT.getVectorElementType()) &&
517 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
519 // Promoted vector extract
520 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
522 // Vector -> scalar conversion.
523 assert(ValueVT.getVectorNumElements() == 1 &&
524 "Only trivial vector-to-scalar conversions should get here!");
526 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
527 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
529 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Handle a multi-element vector.
539 unsigned NumIntermediates;
540 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
542 NumIntermediates, RegisterVT);
543 unsigned NumElements = ValueVT.getVectorNumElements();
545 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
546 NumParts = NumRegs; // Silence a compiler warning.
547 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
549 // Split the vector into intermediate operands.
550 SmallVector<SDValue, 8> Ops(NumIntermediates);
551 for (unsigned i = 0; i != NumIntermediates; ++i) {
552 if (IntermediateVT.isVector())
554 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
555 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
556 TLI.getVectorIdxTy(DAG.getDataLayout())));
558 Ops[i] = DAG.getNode(
559 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
560 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
563 // Split the intermediate operands into legal parts.
564 if (NumParts == NumIntermediates) {
565 // If the register was not expanded, promote or copy the value,
567 for (unsigned i = 0; i != NumParts; ++i)
568 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
569 } else if (NumParts > 0) {
570 // If the intermediate type was expanded, split each the value into
572 assert(NumIntermediates != 0 && "division by zero");
573 assert(NumParts % NumIntermediates == 0 &&
574 "Must expand into a divisible number of parts!");
575 unsigned Factor = NumParts / NumIntermediates;
576 for (unsigned i = 0; i != NumIntermediates; ++i)
577 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
581 RegsForValue::RegsForValue() {}
583 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
585 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
587 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
588 const DataLayout &DL, unsigned Reg, Type *Ty) {
589 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
591 for (EVT ValueVT : ValueVTs) {
592 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
593 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
602 /// this value and returns the result as a ValueVT value. This uses
603 /// Chain/Flag as the input and updates them for the output Chain/Flag.
604 /// If the Flag pointer is NULL, no flag is used.
605 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
606 FunctionLoweringInfo &FuncInfo,
608 SDValue &Chain, SDValue *Flag,
609 const Value *V) const {
610 // A Value with type {} or [0 x %t] needs no registers.
611 if (ValueVTs.empty())
614 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
616 // Assemble the legal parts into the final values.
617 SmallVector<SDValue, 4> Values(ValueVTs.size());
618 SmallVector<SDValue, 8> Parts;
619 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
620 // Copy the legal parts from the registers.
621 EVT ValueVT = ValueVTs[Value];
622 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
623 MVT RegisterVT = RegVTs[Value];
625 Parts.resize(NumRegs);
626 for (unsigned i = 0; i != NumRegs; ++i) {
629 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
631 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
632 *Flag = P.getValue(2);
635 Chain = P.getValue(1);
638 // If the source register was virtual and if we know something about it,
639 // add an assert node.
640 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
641 !RegisterVT.isInteger() || RegisterVT.isVector())
644 const FunctionLoweringInfo::LiveOutInfo *LOI =
645 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
649 unsigned RegSize = RegisterVT.getSizeInBits();
650 unsigned NumSignBits = LOI->NumSignBits;
651 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
653 if (NumZeroBits == RegSize) {
654 // The current value is a zero.
655 // Explicitly express that as it would be easier for
656 // optimizations to kick in.
657 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
661 // FIXME: We capture more information than the dag can represent. For
662 // now, just use the tightest assertzext/assertsext possible.
664 EVT FromVT(MVT::Other);
665 if (NumSignBits == RegSize)
666 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
667 else if (NumZeroBits >= RegSize-1)
668 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
669 else if (NumSignBits > RegSize-8)
670 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
671 else if (NumZeroBits >= RegSize-8)
672 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
673 else if (NumSignBits > RegSize-16)
674 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
675 else if (NumZeroBits >= RegSize-16)
676 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
677 else if (NumSignBits > RegSize-32)
678 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
679 else if (NumZeroBits >= RegSize-32)
680 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
684 // Add an assertion node.
685 assert(FromVT != MVT::Other);
686 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
687 RegisterVT, P, DAG.getValueType(FromVT));
690 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
691 NumRegs, RegisterVT, ValueVT, V);
696 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
699 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
700 /// specified value into the registers specified by this object. This uses
701 /// Chain/Flag as the input and updates them for the output Chain/Flag.
702 /// If the Flag pointer is NULL, no flag is used.
703 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
704 SDValue &Chain, SDValue *Flag, const Value *V,
705 ISD::NodeType PreferredExtendType) const {
706 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
707 ISD::NodeType ExtendKind = PreferredExtendType;
709 // Get the list of the values's legal parts.
710 unsigned NumRegs = Regs.size();
711 SmallVector<SDValue, 8> Parts(NumRegs);
712 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
713 EVT ValueVT = ValueVTs[Value];
714 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
715 MVT RegisterVT = RegVTs[Value];
717 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
718 ExtendKind = ISD::ZERO_EXTEND;
720 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
721 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
725 // Copy the parts into the registers.
726 SmallVector<SDValue, 8> Chains(NumRegs);
727 for (unsigned i = 0; i != NumRegs; ++i) {
730 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
732 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
733 *Flag = Part.getValue(1);
736 Chains[i] = Part.getValue(0);
739 if (NumRegs == 1 || Flag)
740 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
741 // flagged to it. That is the CopyToReg nodes and the user are considered
742 // a single scheduling unit. If we create a TokenFactor and return it as
743 // chain, then the TokenFactor is both a predecessor (operand) of the
744 // user as well as a successor (the TF operands are flagged to the user).
745 // c1, f1 = CopyToReg
746 // c2, f2 = CopyToReg
747 // c3 = TokenFactor c1, c2
750 Chain = Chains[NumRegs-1];
752 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
755 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
756 /// operand list. This adds the code marker and includes the number of
757 /// values added into it.
758 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
759 unsigned MatchingIdx, SDLoc dl,
761 std::vector<SDValue> &Ops) const {
762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
764 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
766 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
767 else if (!Regs.empty() &&
768 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
769 // Put the register class of the virtual registers in the flag word. That
770 // way, later passes can recompute register class constraints for inline
771 // assembly as well as normal instructions.
772 // Don't do this for tied operands that can use the regclass information
774 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
775 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
776 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
779 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
782 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
783 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
784 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
785 MVT RegisterVT = RegVTs[Value];
786 for (unsigned i = 0; i != NumRegs; ++i) {
787 assert(Reg < Regs.size() && "Mismatch in # registers expected");
788 unsigned TheReg = Regs[Reg++];
789 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
791 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
792 // If we clobbered the stack pointer, MFI should know about it.
793 assert(DAG.getMachineFunction().getFrameInfo()->
794 hasOpaqueSPAdjustment());
800 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
801 const TargetLibraryInfo *li) {
805 DL = &DAG.getDataLayout();
806 Context = DAG.getContext();
807 LPadToCallSiteMap.clear();
810 /// clear - Clear out the current SelectionDAG and the associated
811 /// state and prepare this SelectionDAGBuilder object to be used
812 /// for a new block. This doesn't clear out information about
813 /// additional blocks that are needed to complete switch lowering
814 /// or PHI node updating; that information is cleared out as it is
816 void SelectionDAGBuilder::clear() {
818 UnusedArgNodeMap.clear();
819 PendingLoads.clear();
820 PendingExports.clear();
823 SDNodeOrder = LowestSDNodeOrder;
824 StatepointLowering.clear();
827 /// clearDanglingDebugInfo - Clear the dangling debug information
828 /// map. This function is separated from the clear so that debug
829 /// information that is dangling in a basic block can be properly
830 /// resolved in a different basic block. This allows the
831 /// SelectionDAG to resolve dangling debug information attached
833 void SelectionDAGBuilder::clearDanglingDebugInfo() {
834 DanglingDebugInfoMap.clear();
837 /// getRoot - Return the current virtual root of the Selection DAG,
838 /// flushing any PendingLoad items. This must be done before emitting
839 /// a store or any other node that may need to be ordered after any
840 /// prior load instructions.
842 SDValue SelectionDAGBuilder::getRoot() {
843 if (PendingLoads.empty())
844 return DAG.getRoot();
846 if (PendingLoads.size() == 1) {
847 SDValue Root = PendingLoads[0];
849 PendingLoads.clear();
853 // Otherwise, we have to make a token factor node.
854 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
856 PendingLoads.clear();
861 /// getControlRoot - Similar to getRoot, but instead of flushing all the
862 /// PendingLoad items, flush all the PendingExports items. It is necessary
863 /// to do this before emitting a terminator instruction.
865 SDValue SelectionDAGBuilder::getControlRoot() {
866 SDValue Root = DAG.getRoot();
868 if (PendingExports.empty())
871 // Turn all of the CopyToReg chains into one factored node.
872 if (Root.getOpcode() != ISD::EntryToken) {
873 unsigned i = 0, e = PendingExports.size();
874 for (; i != e; ++i) {
875 assert(PendingExports[i].getNode()->getNumOperands() > 1);
876 if (PendingExports[i].getNode()->getOperand(0) == Root)
877 break; // Don't add the root if we already indirectly depend on it.
881 PendingExports.push_back(Root);
884 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
886 PendingExports.clear();
891 void SelectionDAGBuilder::visit(const Instruction &I) {
892 // Set up outgoing PHI node register values before emitting the terminator.
893 if (isa<TerminatorInst>(&I))
894 HandlePHINodesInSuccessorBlocks(I.getParent());
900 visit(I.getOpcode(), I);
902 if (!isa<TerminatorInst>(&I) && !HasTailCall)
903 CopyToExportRegsIfNeeded(&I);
908 void SelectionDAGBuilder::visitPHI(const PHINode &) {
909 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
912 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
913 // Note: this doesn't use InstVisitor, because it has to work with
914 // ConstantExpr's in addition to instructions.
916 default: llvm_unreachable("Unknown instruction type encountered!");
917 // Build the switch statement using the Instruction.def file.
918 #define HANDLE_INST(NUM, OPCODE, CLASS) \
919 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
920 #include "llvm/IR/Instruction.def"
924 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
925 // generate the debug data structures now that we've seen its definition.
926 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
928 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
930 const DbgValueInst *DI = DDI.getDI();
931 DebugLoc dl = DDI.getdl();
932 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
933 DILocalVariable *Variable = DI->getVariable();
934 DIExpression *Expr = DI->getExpression();
935 assert(Variable->isValidLocationForIntrinsic(dl) &&
936 "Expected inlined-at fields to agree");
937 uint64_t Offset = DI->getOffset();
938 // A dbg.value for an alloca is always indirect.
939 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
942 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
944 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
945 IsIndirect, Offset, dl, DbgSDNodeOrder);
946 DAG.AddDbgValue(SDV, Val.getNode(), false);
949 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
950 DanglingDebugInfoMap[V] = DanglingDebugInfo();
954 /// getCopyFromRegs - If there was virtual register allocated for the value V
955 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
956 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
957 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
960 if (It != FuncInfo.ValueMap.end()) {
961 unsigned InReg = It->second;
962 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
963 DAG.getDataLayout(), InReg, Ty);
964 SDValue Chain = DAG.getEntryNode();
965 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
966 resolveDanglingDebugInfo(V, Result);
972 /// getValue - Return an SDValue for the given Value.
973 SDValue SelectionDAGBuilder::getValue(const Value *V) {
974 // If we already have an SDValue for this value, use it. It's important
975 // to do this first, so that we don't create a CopyFromReg if we already
976 // have a regular SDValue.
977 SDValue &N = NodeMap[V];
978 if (N.getNode()) return N;
980 // If there's a virtual register allocated and initialized for this
982 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
983 if (copyFromReg.getNode()) {
987 // Otherwise create a new SDValue and remember it.
988 SDValue Val = getValueImpl(V);
990 resolveDanglingDebugInfo(V, Val);
994 // Return true if SDValue exists for the given Value
995 bool SelectionDAGBuilder::findValue(const Value *V) const {
996 return (NodeMap.find(V) != NodeMap.end()) ||
997 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1000 /// getNonRegisterValue - Return an SDValue for the given Value, but
1001 /// don't look in FuncInfo.ValueMap for a virtual register.
1002 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1003 // If we already have an SDValue for this value, use it.
1004 SDValue &N = NodeMap[V];
1006 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1007 // Remove the debug location from the node as the node is about to be used
1008 // in a location which may differ from the original debug location. This
1009 // is relevant to Constant and ConstantFP nodes because they can appear
1010 // as constant expressions inside PHI nodes.
1011 N->setDebugLoc(DebugLoc());
1016 // Otherwise create a new SDValue and remember it.
1017 SDValue Val = getValueImpl(V);
1019 resolveDanglingDebugInfo(V, Val);
1023 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1024 /// Create an SDValue for the given value.
1025 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1026 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1028 if (const Constant *C = dyn_cast<Constant>(V)) {
1029 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1031 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1032 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1034 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1035 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1037 if (isa<ConstantPointerNull>(C)) {
1038 unsigned AS = V->getType()->getPointerAddressSpace();
1039 return DAG.getConstant(0, getCurSDLoc(),
1040 TLI.getPointerTy(DAG.getDataLayout(), AS));
1043 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1044 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1046 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1047 return DAG.getUNDEF(VT);
1049 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1050 visit(CE->getOpcode(), *CE);
1051 SDValue N1 = NodeMap[V];
1052 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1056 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1057 SmallVector<SDValue, 4> Constants;
1058 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1060 SDNode *Val = getValue(*OI).getNode();
1061 // If the operand is an empty aggregate, there are no values.
1063 // Add each leaf value from the operand to the Constants list
1064 // to form a flattened list of all the values.
1065 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1066 Constants.push_back(SDValue(Val, i));
1069 return DAG.getMergeValues(Constants, getCurSDLoc());
1072 if (const ConstantDataSequential *CDS =
1073 dyn_cast<ConstantDataSequential>(C)) {
1074 SmallVector<SDValue, 4> Ops;
1075 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1076 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1077 // Add each leaf value from the operand to the Constants list
1078 // to form a flattened list of all the values.
1079 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1080 Ops.push_back(SDValue(Val, i));
1083 if (isa<ArrayType>(CDS->getType()))
1084 return DAG.getMergeValues(Ops, getCurSDLoc());
1085 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1089 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1090 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1091 "Unknown struct or array constant!");
1093 SmallVector<EVT, 4> ValueVTs;
1094 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1095 unsigned NumElts = ValueVTs.size();
1097 return SDValue(); // empty struct
1098 SmallVector<SDValue, 4> Constants(NumElts);
1099 for (unsigned i = 0; i != NumElts; ++i) {
1100 EVT EltVT = ValueVTs[i];
1101 if (isa<UndefValue>(C))
1102 Constants[i] = DAG.getUNDEF(EltVT);
1103 else if (EltVT.isFloatingPoint())
1104 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1106 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1109 return DAG.getMergeValues(Constants, getCurSDLoc());
1112 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1113 return DAG.getBlockAddress(BA, VT);
1115 VectorType *VecTy = cast<VectorType>(V->getType());
1116 unsigned NumElements = VecTy->getNumElements();
1118 // Now that we know the number and type of the elements, get that number of
1119 // elements into the Ops array based on what kind of constant it is.
1120 SmallVector<SDValue, 16> Ops;
1121 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1122 for (unsigned i = 0; i != NumElements; ++i)
1123 Ops.push_back(getValue(CV->getOperand(i)));
1125 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1127 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1130 if (EltVT.isFloatingPoint())
1131 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1133 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1134 Ops.assign(NumElements, Op);
1137 // Create a BUILD_VECTOR node.
1138 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1141 // If this is a static alloca, generate it as the frameindex instead of
1143 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1144 DenseMap<const AllocaInst*, int>::iterator SI =
1145 FuncInfo.StaticAllocaMap.find(AI);
1146 if (SI != FuncInfo.StaticAllocaMap.end())
1147 return DAG.getFrameIndex(SI->second,
1148 TLI.getPointerTy(DAG.getDataLayout()));
1151 // If this is an instruction which fast-isel has deferred, select it now.
1152 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1153 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1154 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1156 SDValue Chain = DAG.getEntryNode();
1157 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1160 llvm_unreachable("Can't get register for value!");
1163 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1164 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1165 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1166 bool IsSEH = isAsynchronousEHPersonality(Pers);
1167 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1168 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1169 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1170 if (IsMSVCCXX || IsCoreCLR)
1171 CatchPadMBB->setIsEHFuncletEntry();
1173 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1175 // Update machine-CFG edge.
1176 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1178 // CatchPads in SEH are not funclets, they are merely markers which indicate
1179 // where to insert register restoration code.
1181 DAG.setRoot(DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1182 getControlRoot(), DAG.getBasicBlock(NormalDestMBB),
1183 DAG.getBasicBlock(&FuncInfo.MF->front())));
1187 // If this is not a fall-through branch or optimizations are switched off,
1189 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1190 TM.getOptLevel() == CodeGenOpt::None)
1191 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1193 DAG.getBasicBlock(NormalDestMBB)));
1196 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1197 // Update machine-CFG edge.
1198 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1199 FuncInfo.MBB->addSuccessor(TargetMBB);
1201 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1202 bool IsSEH = isAsynchronousEHPersonality(Pers);
1204 // If this is not a fall-through branch or optimizations are switched off,
1206 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1207 TM.getOptLevel() == CodeGenOpt::None)
1208 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1209 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1213 // Figure out the funclet membership for the catchret's successor.
1214 // This will be used by the FuncletLayout pass to determine how to order the
1216 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1217 WinEHFuncInfo &EHInfo =
1218 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
1219 const BasicBlock *SuccessorColor = EHInfo.CatchRetSuccessorColorMap[&I];
1220 assert(SuccessorColor && "No parent funclet for catchret!");
1221 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1222 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1224 // Create the terminator node.
1225 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1226 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1227 DAG.getBasicBlock(SuccessorColorMBB));
1231 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1232 llvm_unreachable("should never codegen catchendpads");
1235 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1236 // Don't emit any special code for the cleanuppad instruction. It just marks
1237 // the start of a funclet.
1238 FuncInfo.MBB->setIsEHFuncletEntry();
1239 FuncInfo.MBB->setIsCleanupFuncletEntry();
1242 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1243 /// many places it could ultimately go. In the IR, we have a single unwind
1244 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1245 /// This function skips over imaginary basic blocks that hold catchpad,
1246 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1247 /// basic block destinations. As those destinations may not be successors of
1248 /// EHPadBB, here we also calculate the edge weight to those destinations. The
1249 /// passed-in Weight is the edge weight to EHPadBB.
1250 static void findUnwindDestinations(
1251 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, uint32_t Weight,
1252 SmallVectorImpl<std::pair<MachineBasicBlock *, uint32_t>> &UnwindDests) {
1253 EHPersonality Personality =
1254 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1255 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1256 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1259 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1260 BasicBlock *NewEHPadBB = nullptr;
1261 if (isa<LandingPadInst>(Pad)) {
1262 // Stop on landingpads. They are not funclets.
1263 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1265 } else if (isa<CleanupPadInst>(Pad)) {
1266 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1268 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1269 UnwindDests.back().first->setIsEHFuncletEntry();
1271 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1272 // Add the catchpad handler to the possible destinations.
1273 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1274 // In MSVC C++, catchblocks are funclets and need prologues.
1275 if (IsMSVCCXX || IsCoreCLR)
1276 UnwindDests.back().first->setIsEHFuncletEntry();
1277 NewEHPadBB = CPI->getUnwindDest();
1278 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad))
1279 NewEHPadBB = CEPI->getUnwindDest();
1280 else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad))
1281 NewEHPadBB = CEPI->getUnwindDest();
1285 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1286 if (BPI && NewEHPadBB) {
1287 // When BPI is available, the calculated weight cannot be zero as zero
1288 // will be turned to a default weight in MachineBlockFrequencyInfo.
1289 Weight = std::max<uint32_t>(
1290 BPI->getEdgeProbability(EHPadBB, NewEHPadBB).scale(Weight), 1);
1292 EHPadBB = NewEHPadBB;
1296 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1297 // Update successor info.
1298 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
1299 auto UnwindDest = I.getUnwindDest();
1300 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1301 uint32_t UnwindDestWeight =
1302 BPI ? BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(), UnwindDest) : 0;
1303 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestWeight, UnwindDests);
1304 for (auto &UnwindDest : UnwindDests) {
1305 UnwindDest.first->setIsEHPad();
1306 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1309 // Create the terminator node.
1311 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1315 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1316 report_fatal_error("visitCleanupEndPad not yet implemented!");
1319 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1320 report_fatal_error("visitTerminatePad not yet implemented!");
1323 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1324 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1325 auto &DL = DAG.getDataLayout();
1326 SDValue Chain = getControlRoot();
1327 SmallVector<ISD::OutputArg, 8> Outs;
1328 SmallVector<SDValue, 8> OutVals;
1330 if (!FuncInfo.CanLowerReturn) {
1331 unsigned DemoteReg = FuncInfo.DemoteRegister;
1332 const Function *F = I.getParent()->getParent();
1334 // Emit a store of the return value through the virtual register.
1335 // Leave Outs empty so that LowerReturn won't try to load return
1336 // registers the usual way.
1337 SmallVector<EVT, 1> PtrValueVTs;
1338 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1341 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1342 SDValue RetOp = getValue(I.getOperand(0));
1344 SmallVector<EVT, 4> ValueVTs;
1345 SmallVector<uint64_t, 4> Offsets;
1346 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1347 unsigned NumValues = ValueVTs.size();
1349 SmallVector<SDValue, 4> Chains(NumValues);
1350 for (unsigned i = 0; i != NumValues; ++i) {
1351 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1352 RetPtr.getValueType(), RetPtr,
1353 DAG.getIntPtrConstant(Offsets[i],
1356 DAG.getStore(Chain, getCurSDLoc(),
1357 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1358 // FIXME: better loc info would be nice.
1359 Add, MachinePointerInfo(), false, false, 0);
1362 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1363 MVT::Other, Chains);
1364 } else if (I.getNumOperands() != 0) {
1365 SmallVector<EVT, 4> ValueVTs;
1366 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1367 unsigned NumValues = ValueVTs.size();
1369 SDValue RetOp = getValue(I.getOperand(0));
1371 const Function *F = I.getParent()->getParent();
1373 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1374 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1376 ExtendKind = ISD::SIGN_EXTEND;
1377 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1379 ExtendKind = ISD::ZERO_EXTEND;
1381 LLVMContext &Context = F->getContext();
1382 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1385 for (unsigned j = 0; j != NumValues; ++j) {
1386 EVT VT = ValueVTs[j];
1388 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1389 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1391 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1392 MVT PartVT = TLI.getRegisterType(Context, VT);
1393 SmallVector<SDValue, 4> Parts(NumParts);
1394 getCopyToParts(DAG, getCurSDLoc(),
1395 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1396 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1398 // 'inreg' on function refers to return value
1399 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1403 // Propagate extension type if any
1404 if (ExtendKind == ISD::SIGN_EXTEND)
1406 else if (ExtendKind == ISD::ZERO_EXTEND)
1409 for (unsigned i = 0; i < NumParts; ++i) {
1410 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1411 VT, /*isfixed=*/true, 0, 0));
1412 OutVals.push_back(Parts[i]);
1418 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1419 CallingConv::ID CallConv =
1420 DAG.getMachineFunction().getFunction()->getCallingConv();
1421 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1422 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1424 // Verify that the target's LowerReturn behaved as expected.
1425 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1426 "LowerReturn didn't return a valid chain!");
1428 // Update the DAG with the new chain value resulting from return lowering.
1432 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1433 /// created for it, emit nodes to copy the value into the virtual
1435 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1437 if (V->getType()->isEmptyTy())
1440 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1441 if (VMI != FuncInfo.ValueMap.end()) {
1442 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1443 CopyValueToVirtualRegister(V, VMI->second);
1447 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1448 /// the current basic block, add it to ValueMap now so that we'll get a
1450 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1451 // No need to export constants.
1452 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1454 // Already exported?
1455 if (FuncInfo.isExportedInst(V)) return;
1457 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1458 CopyValueToVirtualRegister(V, Reg);
1461 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1462 const BasicBlock *FromBB) {
1463 // The operands of the setcc have to be in this block. We don't know
1464 // how to export them from some other block.
1465 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1466 // Can export from current BB.
1467 if (VI->getParent() == FromBB)
1470 // Is already exported, noop.
1471 return FuncInfo.isExportedInst(V);
1474 // If this is an argument, we can export it if the BB is the entry block or
1475 // if it is already exported.
1476 if (isa<Argument>(V)) {
1477 if (FromBB == &FromBB->getParent()->getEntryBlock())
1480 // Otherwise, can only export this if it is already exported.
1481 return FuncInfo.isExportedInst(V);
1484 // Otherwise, constants can always be exported.
1488 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1489 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1490 const MachineBasicBlock *Dst) const {
1491 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1494 const BasicBlock *SrcBB = Src->getBasicBlock();
1495 const BasicBlock *DstBB = Dst->getBasicBlock();
1496 return BPI->getEdgeWeight(SrcBB, DstBB);
1499 void SelectionDAGBuilder::
1500 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1501 uint32_t Weight /* = 0 */) {
1503 Weight = getEdgeWeight(Src, Dst);
1504 Src->addSuccessor(Dst, Weight);
1508 static bool InBlock(const Value *V, const BasicBlock *BB) {
1509 if (const Instruction *I = dyn_cast<Instruction>(V))
1510 return I->getParent() == BB;
1514 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1515 /// This function emits a branch and is used at the leaves of an OR or an
1516 /// AND operator tree.
1519 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1520 MachineBasicBlock *TBB,
1521 MachineBasicBlock *FBB,
1522 MachineBasicBlock *CurBB,
1523 MachineBasicBlock *SwitchBB,
1526 const BasicBlock *BB = CurBB->getBasicBlock();
1528 // If the leaf of the tree is a comparison, merge the condition into
1530 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1531 // The operands of the cmp have to be in this block. We don't know
1532 // how to export them from some other block. If this is the first block
1533 // of the sequence, no exporting is needed.
1534 if (CurBB == SwitchBB ||
1535 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1536 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1537 ISD::CondCode Condition;
1538 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1539 Condition = getICmpCondCode(IC->getPredicate());
1541 const FCmpInst *FC = cast<FCmpInst>(Cond);
1542 Condition = getFCmpCondCode(FC->getPredicate());
1543 if (TM.Options.NoNaNsFPMath)
1544 Condition = getFCmpCodeWithoutNaN(Condition);
1547 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1548 TBB, FBB, CurBB, TWeight, FWeight);
1549 SwitchCases.push_back(CB);
1554 // Create a CaseBlock record representing this branch.
1555 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1556 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1557 SwitchCases.push_back(CB);
1560 /// Scale down both weights to fit into uint32_t.
1561 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1562 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1563 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1564 NewTrue = NewTrue / Scale;
1565 NewFalse = NewFalse / Scale;
1568 /// FindMergedConditions - If Cond is an expression like
1569 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1570 MachineBasicBlock *TBB,
1571 MachineBasicBlock *FBB,
1572 MachineBasicBlock *CurBB,
1573 MachineBasicBlock *SwitchBB,
1574 Instruction::BinaryOps Opc,
1577 // If this node is not part of the or/and tree, emit it as a branch.
1578 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1579 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1580 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1581 BOp->getParent() != CurBB->getBasicBlock() ||
1582 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1583 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1584 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1589 // Create TmpBB after CurBB.
1590 MachineFunction::iterator BBI(CurBB);
1591 MachineFunction &MF = DAG.getMachineFunction();
1592 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1593 CurBB->getParent()->insert(++BBI, TmpBB);
1595 if (Opc == Instruction::Or) {
1596 // Codegen X | Y as:
1605 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1606 // The requirement is that
1607 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1608 // = TrueProb for original BB.
1609 // Assuming the original weights are A and B, one choice is to set BB1's
1610 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1612 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1613 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1614 // TmpBB, but the math is more complicated.
1616 uint64_t NewTrueWeight = TWeight;
1617 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1618 ScaleWeights(NewTrueWeight, NewFalseWeight);
1619 // Emit the LHS condition.
1620 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1621 NewTrueWeight, NewFalseWeight);
1623 NewTrueWeight = TWeight;
1624 NewFalseWeight = 2 * (uint64_t)FWeight;
1625 ScaleWeights(NewTrueWeight, NewFalseWeight);
1626 // Emit the RHS condition into TmpBB.
1627 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1628 NewTrueWeight, NewFalseWeight);
1630 assert(Opc == Instruction::And && "Unknown merge op!");
1631 // Codegen X & Y as:
1639 // This requires creation of TmpBB after CurBB.
1641 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1642 // The requirement is that
1643 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1644 // = FalseProb for original BB.
1645 // Assuming the original weights are A and B, one choice is to set BB1's
1646 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1648 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1650 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1651 uint64_t NewFalseWeight = FWeight;
1652 ScaleWeights(NewTrueWeight, NewFalseWeight);
1653 // Emit the LHS condition.
1654 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1655 NewTrueWeight, NewFalseWeight);
1657 NewTrueWeight = 2 * (uint64_t)TWeight;
1658 NewFalseWeight = FWeight;
1659 ScaleWeights(NewTrueWeight, NewFalseWeight);
1660 // Emit the RHS condition into TmpBB.
1661 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1662 NewTrueWeight, NewFalseWeight);
1666 /// If the set of cases should be emitted as a series of branches, return true.
1667 /// If we should emit this as a bunch of and/or'd together conditions, return
1670 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1671 if (Cases.size() != 2) return true;
1673 // If this is two comparisons of the same values or'd or and'd together, they
1674 // will get folded into a single comparison, so don't emit two blocks.
1675 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1676 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1677 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1678 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1682 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1683 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1684 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1685 Cases[0].CC == Cases[1].CC &&
1686 isa<Constant>(Cases[0].CmpRHS) &&
1687 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1688 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1690 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1697 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1698 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1700 // Update machine-CFG edges.
1701 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1703 if (I.isUnconditional()) {
1704 // Update machine-CFG edges.
1705 BrMBB->addSuccessor(Succ0MBB);
1707 // If this is not a fall-through branch or optimizations are switched off,
1709 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1710 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1711 MVT::Other, getControlRoot(),
1712 DAG.getBasicBlock(Succ0MBB)));
1717 // If this condition is one of the special cases we handle, do special stuff
1719 const Value *CondVal = I.getCondition();
1720 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1722 // If this is a series of conditions that are or'd or and'd together, emit
1723 // this as a sequence of branches instead of setcc's with and/or operations.
1724 // As long as jumps are not expensive, this should improve performance.
1725 // For example, instead of something like:
1738 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1739 Instruction::BinaryOps Opcode = BOp->getOpcode();
1740 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1741 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1742 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1743 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1744 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1745 getEdgeWeight(BrMBB, Succ1MBB));
1746 // If the compares in later blocks need to use values not currently
1747 // exported from this block, export them now. This block should always
1748 // be the first entry.
1749 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1751 // Allow some cases to be rejected.
1752 if (ShouldEmitAsBranches(SwitchCases)) {
1753 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1754 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1755 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1758 // Emit the branch for this block.
1759 visitSwitchCase(SwitchCases[0], BrMBB);
1760 SwitchCases.erase(SwitchCases.begin());
1764 // Okay, we decided not to do this, remove any inserted MBB's and clear
1766 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1767 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1769 SwitchCases.clear();
1773 // Create a CaseBlock record representing this branch.
1774 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1775 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1777 // Use visitSwitchCase to actually insert the fast branch sequence for this
1779 visitSwitchCase(CB, BrMBB);
1782 /// visitSwitchCase - Emits the necessary code to represent a single node in
1783 /// the binary search tree resulting from lowering a switch instruction.
1784 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1785 MachineBasicBlock *SwitchBB) {
1787 SDValue CondLHS = getValue(CB.CmpLHS);
1788 SDLoc dl = getCurSDLoc();
1790 // Build the setcc now.
1792 // Fold "(X == true)" to X and "(X == false)" to !X to
1793 // handle common cases produced by branch lowering.
1794 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1795 CB.CC == ISD::SETEQ)
1797 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1798 CB.CC == ISD::SETEQ) {
1799 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1800 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1802 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1804 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1806 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1807 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1809 SDValue CmpOp = getValue(CB.CmpMHS);
1810 EVT VT = CmpOp.getValueType();
1812 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1813 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1816 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1817 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1818 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1819 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1823 // Update successor info
1824 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1825 // TrueBB and FalseBB are always different unless the incoming IR is
1826 // degenerate. This only happens when running llc on weird IR.
1827 if (CB.TrueBB != CB.FalseBB)
1828 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1830 // If the lhs block is the next block, invert the condition so that we can
1831 // fall through to the lhs instead of the rhs block.
1832 if (CB.TrueBB == NextBlock(SwitchBB)) {
1833 std::swap(CB.TrueBB, CB.FalseBB);
1834 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1835 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1838 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1839 MVT::Other, getControlRoot(), Cond,
1840 DAG.getBasicBlock(CB.TrueBB));
1842 // Insert the false branch. Do this even if it's a fall through branch,
1843 // this makes it easier to do DAG optimizations which require inverting
1844 // the branch condition.
1845 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1846 DAG.getBasicBlock(CB.FalseBB));
1848 DAG.setRoot(BrCond);
1851 /// visitJumpTable - Emit JumpTable node in the current MBB
1852 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1853 // Emit the code for the jump table
1854 assert(JT.Reg != -1U && "Should lower JT Header first!");
1855 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1856 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1858 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1859 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1860 MVT::Other, Index.getValue(1),
1862 DAG.setRoot(BrJumpTable);
1865 /// visitJumpTableHeader - This function emits necessary code to produce index
1866 /// in the JumpTable from switch case.
1867 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1868 JumpTableHeader &JTH,
1869 MachineBasicBlock *SwitchBB) {
1870 SDLoc dl = getCurSDLoc();
1872 // Subtract the lowest switch case value from the value being switched on and
1873 // conditional branch to default mbb if the result is greater than the
1874 // difference between smallest and largest cases.
1875 SDValue SwitchOp = getValue(JTH.SValue);
1876 EVT VT = SwitchOp.getValueType();
1877 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1878 DAG.getConstant(JTH.First, dl, VT));
1880 // The SDNode we just created, which holds the value being switched on minus
1881 // the smallest case value, needs to be copied to a virtual register so it
1882 // can be used as an index into the jump table in a subsequent basic block.
1883 // This value may be smaller or larger than the target's pointer type, and
1884 // therefore require extension or truncating.
1885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1886 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1888 unsigned JumpTableReg =
1889 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1890 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1891 JumpTableReg, SwitchOp);
1892 JT.Reg = JumpTableReg;
1894 // Emit the range check for the jump table, and branch to the default block
1895 // for the switch statement if the value being switched on exceeds the largest
1896 // case in the switch.
1897 SDValue CMP = DAG.getSetCC(
1898 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1899 Sub.getValueType()),
1900 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1902 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1903 MVT::Other, CopyTo, CMP,
1904 DAG.getBasicBlock(JT.Default));
1906 // Avoid emitting unnecessary branches to the next block.
1907 if (JT.MBB != NextBlock(SwitchBB))
1908 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1909 DAG.getBasicBlock(JT.MBB));
1911 DAG.setRoot(BrCond);
1914 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1915 /// tail spliced into a stack protector check success bb.
1917 /// For a high level explanation of how this fits into the stack protector
1918 /// generation see the comment on the declaration of class
1919 /// StackProtectorDescriptor.
1920 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1921 MachineBasicBlock *ParentBB) {
1923 // First create the loads to the guard/stack slot for the comparison.
1924 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1925 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1927 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1928 int FI = MFI->getStackProtectorIndex();
1930 const Value *IRGuard = SPD.getGuard();
1931 SDValue GuardPtr = getValue(IRGuard);
1932 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1934 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1937 SDLoc dl = getCurSDLoc();
1939 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1940 // guard value from the virtual register holding the value. Otherwise, emit a
1941 // volatile load to retrieve the stack guard value.
1942 unsigned GuardReg = SPD.getGuardReg();
1944 if (GuardReg && TLI.useLoadStackGuardNode())
1945 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1948 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1949 GuardPtr, MachinePointerInfo(IRGuard, 0),
1950 true, false, false, Align);
1952 SDValue StackSlot = DAG.getLoad(
1953 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1954 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1955 false, false, Align);
1957 // Perform the comparison via a subtract/getsetcc.
1958 EVT VT = Guard.getValueType();
1959 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1961 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1963 Sub.getValueType()),
1964 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1966 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1967 // branch to failure MBB.
1968 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1969 MVT::Other, StackSlot.getOperand(0),
1970 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1971 // Otherwise branch to success MBB.
1972 SDValue Br = DAG.getNode(ISD::BR, dl,
1974 DAG.getBasicBlock(SPD.getSuccessMBB()));
1979 /// Codegen the failure basic block for a stack protector check.
1981 /// A failure stack protector machine basic block consists simply of a call to
1982 /// __stack_chk_fail().
1984 /// For a high level explanation of how this fits into the stack protector
1985 /// generation see the comment on the declaration of class
1986 /// StackProtectorDescriptor.
1988 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1989 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1991 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
1992 nullptr, 0, false, getCurSDLoc(), false, false).second;
1996 /// visitBitTestHeader - This function emits necessary code to produce value
1997 /// suitable for "bit tests"
1998 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1999 MachineBasicBlock *SwitchBB) {
2000 SDLoc dl = getCurSDLoc();
2002 // Subtract the minimum value
2003 SDValue SwitchOp = getValue(B.SValue);
2004 EVT VT = SwitchOp.getValueType();
2005 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2006 DAG.getConstant(B.First, dl, VT));
2009 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2010 SDValue RangeCmp = DAG.getSetCC(
2011 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2012 Sub.getValueType()),
2013 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2015 // Determine the type of the test operands.
2016 bool UsePtrType = false;
2017 if (!TLI.isTypeLegal(VT))
2020 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2021 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2022 // Switch table case range are encoded into series of masks.
2023 // Just use pointer type, it's guaranteed to fit.
2029 VT = TLI.getPointerTy(DAG.getDataLayout());
2030 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2033 B.RegVT = VT.getSimpleVT();
2034 B.Reg = FuncInfo.CreateReg(B.RegVT);
2035 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2037 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2039 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2040 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2042 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2043 MVT::Other, CopyTo, RangeCmp,
2044 DAG.getBasicBlock(B.Default));
2046 // Avoid emitting unnecessary branches to the next block.
2047 if (MBB != NextBlock(SwitchBB))
2048 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2049 DAG.getBasicBlock(MBB));
2051 DAG.setRoot(BrRange);
2054 /// visitBitTestCase - this function produces one "bit test"
2055 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2056 MachineBasicBlock* NextMBB,
2057 uint32_t BranchWeightToNext,
2060 MachineBasicBlock *SwitchBB) {
2061 SDLoc dl = getCurSDLoc();
2063 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2065 unsigned PopCount = countPopulation(B.Mask);
2066 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2067 if (PopCount == 1) {
2068 // Testing for a single bit; just compare the shift count with what it
2069 // would need to be to shift a 1 bit in that position.
2071 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2072 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2074 } else if (PopCount == BB.Range) {
2075 // There is only one zero bit in the range, test for it directly.
2077 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2078 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2081 // Make desired shift
2082 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2083 DAG.getConstant(1, dl, VT), ShiftOp);
2085 // Emit bit tests and jumps
2086 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2087 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2089 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2090 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2093 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2094 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2095 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2096 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2098 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2099 MVT::Other, getControlRoot(),
2100 Cmp, DAG.getBasicBlock(B.TargetBB));
2102 // Avoid emitting unnecessary branches to the next block.
2103 if (NextMBB != NextBlock(SwitchBB))
2104 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2105 DAG.getBasicBlock(NextMBB));
2110 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2111 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2113 // Retrieve successors. Look through artificial IR level blocks like catchpads
2114 // and catchendpads for successors.
2115 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2116 const BasicBlock *EHPadBB = I.getSuccessor(1);
2118 const Value *Callee(I.getCalledValue());
2119 const Function *Fn = dyn_cast<Function>(Callee);
2120 if (isa<InlineAsm>(Callee))
2122 else if (Fn && Fn->isIntrinsic()) {
2123 switch (Fn->getIntrinsicID()) {
2125 llvm_unreachable("Cannot invoke this intrinsic");
2126 case Intrinsic::donothing:
2127 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2129 case Intrinsic::experimental_patchpoint_void:
2130 case Intrinsic::experimental_patchpoint_i64:
2131 visitPatchpoint(&I, EHPadBB);
2133 case Intrinsic::experimental_gc_statepoint:
2134 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2138 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2140 // If the value of the invoke is used outside of its defining block, make it
2141 // available as a virtual register.
2142 // We already took care of the exported value for the statepoint instruction
2143 // during call to the LowerStatepoint.
2144 if (!isStatepoint(I)) {
2145 CopyToExportRegsIfNeeded(&I);
2148 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
2149 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2150 uint32_t EHPadBBWeight =
2151 BPI ? BPI->getEdgeWeight(InvokeMBB->getBasicBlock(), EHPadBB) : 0;
2152 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBWeight, UnwindDests);
2154 // Update successor info.
2155 addSuccessorWithWeight(InvokeMBB, Return);
2156 for (auto &UnwindDest : UnwindDests) {
2157 UnwindDest.first->setIsEHPad();
2158 addSuccessorWithWeight(InvokeMBB, UnwindDest.first, UnwindDest.second);
2161 // Drop into normal successor.
2162 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2163 MVT::Other, getControlRoot(),
2164 DAG.getBasicBlock(Return)));
2167 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2168 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2171 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2172 assert(FuncInfo.MBB->isEHPad() &&
2173 "Call to landingpad not in landing pad!");
2175 MachineBasicBlock *MBB = FuncInfo.MBB;
2176 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2177 AddLandingPadInfo(LP, MMI, MBB);
2179 // If there aren't registers to copy the values into (e.g., during SjLj
2180 // exceptions), then don't bother to create these DAG nodes.
2181 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2182 if (TLI.getExceptionPointerRegister() == 0 &&
2183 TLI.getExceptionSelectorRegister() == 0)
2186 SmallVector<EVT, 2> ValueVTs;
2187 SDLoc dl = getCurSDLoc();
2188 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2189 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2191 // Get the two live-in registers as SDValues. The physregs have already been
2192 // copied into virtual registers.
2194 if (FuncInfo.ExceptionPointerVirtReg) {
2195 Ops[0] = DAG.getZExtOrTrunc(
2196 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2197 FuncInfo.ExceptionPointerVirtReg,
2198 TLI.getPointerTy(DAG.getDataLayout())),
2201 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2203 Ops[1] = DAG.getZExtOrTrunc(
2204 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2205 FuncInfo.ExceptionSelectorVirtReg,
2206 TLI.getPointerTy(DAG.getDataLayout())),
2210 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2211 DAG.getVTList(ValueVTs), Ops);
2215 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2217 for (const CaseCluster &CC : Clusters)
2218 assert(CC.Low == CC.High && "Input clusters must be single-case");
2221 std::sort(Clusters.begin(), Clusters.end(),
2222 [](const CaseCluster &a, const CaseCluster &b) {
2223 return a.Low->getValue().slt(b.Low->getValue());
2226 // Merge adjacent clusters with the same destination.
2227 const unsigned N = Clusters.size();
2228 unsigned DstIndex = 0;
2229 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2230 CaseCluster &CC = Clusters[SrcIndex];
2231 const ConstantInt *CaseVal = CC.Low;
2232 MachineBasicBlock *Succ = CC.MBB;
2234 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2235 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2236 // If this case has the same successor and is a neighbour, merge it into
2237 // the previous cluster.
2238 Clusters[DstIndex - 1].High = CaseVal;
2239 Clusters[DstIndex - 1].Weight += CC.Weight;
2240 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2242 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2243 sizeof(Clusters[SrcIndex]));
2246 Clusters.resize(DstIndex);
2249 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2250 MachineBasicBlock *Last) {
2252 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2253 if (JTCases[i].first.HeaderBB == First)
2254 JTCases[i].first.HeaderBB = Last;
2256 // Update BitTestCases.
2257 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2258 if (BitTestCases[i].Parent == First)
2259 BitTestCases[i].Parent = Last;
2262 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2263 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2265 // Update machine-CFG edges with unique successors.
2266 SmallSet<BasicBlock*, 32> Done;
2267 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2268 BasicBlock *BB = I.getSuccessor(i);
2269 bool Inserted = Done.insert(BB).second;
2273 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2274 addSuccessorWithWeight(IndirectBrMBB, Succ);
2277 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2278 MVT::Other, getControlRoot(),
2279 getValue(I.getAddress())));
2282 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2283 if (DAG.getTarget().Options.TrapUnreachable)
2285 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2288 void SelectionDAGBuilder::visitFSub(const User &I) {
2289 // -0.0 - X --> fneg
2290 Type *Ty = I.getType();
2291 if (isa<Constant>(I.getOperand(0)) &&
2292 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2293 SDValue Op2 = getValue(I.getOperand(1));
2294 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2295 Op2.getValueType(), Op2));
2299 visitBinary(I, ISD::FSUB);
2302 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2303 SDValue Op1 = getValue(I.getOperand(0));
2304 SDValue Op2 = getValue(I.getOperand(1));
2311 if (const OverflowingBinaryOperator *OFBinOp =
2312 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2313 nuw = OFBinOp->hasNoUnsignedWrap();
2314 nsw = OFBinOp->hasNoSignedWrap();
2316 if (const PossiblyExactOperator *ExactOp =
2317 dyn_cast<const PossiblyExactOperator>(&I))
2318 exact = ExactOp->isExact();
2319 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2320 FMF = FPOp->getFastMathFlags();
2323 Flags.setExact(exact);
2324 Flags.setNoSignedWrap(nsw);
2325 Flags.setNoUnsignedWrap(nuw);
2326 if (EnableFMFInDAG) {
2327 Flags.setAllowReciprocal(FMF.allowReciprocal());
2328 Flags.setNoInfs(FMF.noInfs());
2329 Flags.setNoNaNs(FMF.noNaNs());
2330 Flags.setNoSignedZeros(FMF.noSignedZeros());
2331 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2333 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2335 setValue(&I, BinNodeValue);
2338 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2339 SDValue Op1 = getValue(I.getOperand(0));
2340 SDValue Op2 = getValue(I.getOperand(1));
2342 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2343 Op2.getValueType(), DAG.getDataLayout());
2345 // Coerce the shift amount to the right type if we can.
2346 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2347 unsigned ShiftSize = ShiftTy.getSizeInBits();
2348 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2349 SDLoc DL = getCurSDLoc();
2351 // If the operand is smaller than the shift count type, promote it.
2352 if (ShiftSize > Op2Size)
2353 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2355 // If the operand is larger than the shift count type but the shift
2356 // count type has enough bits to represent any shift value, truncate
2357 // it now. This is a common case and it exposes the truncate to
2358 // optimization early.
2359 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2360 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2361 // Otherwise we'll need to temporarily settle for some other convenient
2362 // type. Type legalization will make adjustments once the shiftee is split.
2364 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2371 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2373 if (const OverflowingBinaryOperator *OFBinOp =
2374 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2375 nuw = OFBinOp->hasNoUnsignedWrap();
2376 nsw = OFBinOp->hasNoSignedWrap();
2378 if (const PossiblyExactOperator *ExactOp =
2379 dyn_cast<const PossiblyExactOperator>(&I))
2380 exact = ExactOp->isExact();
2383 Flags.setExact(exact);
2384 Flags.setNoSignedWrap(nsw);
2385 Flags.setNoUnsignedWrap(nuw);
2386 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2391 void SelectionDAGBuilder::visitSDiv(const User &I) {
2392 SDValue Op1 = getValue(I.getOperand(0));
2393 SDValue Op2 = getValue(I.getOperand(1));
2396 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2397 cast<PossiblyExactOperator>(&I)->isExact());
2398 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2402 void SelectionDAGBuilder::visitICmp(const User &I) {
2403 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2404 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2405 predicate = IC->getPredicate();
2406 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2407 predicate = ICmpInst::Predicate(IC->getPredicate());
2408 SDValue Op1 = getValue(I.getOperand(0));
2409 SDValue Op2 = getValue(I.getOperand(1));
2410 ISD::CondCode Opcode = getICmpCondCode(predicate);
2412 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2414 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2417 void SelectionDAGBuilder::visitFCmp(const User &I) {
2418 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2419 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2420 predicate = FC->getPredicate();
2421 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2422 predicate = FCmpInst::Predicate(FC->getPredicate());
2423 SDValue Op1 = getValue(I.getOperand(0));
2424 SDValue Op2 = getValue(I.getOperand(1));
2425 ISD::CondCode Condition = getFCmpCondCode(predicate);
2427 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2428 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2429 // further optimization, but currently FMF is only applicable to binary nodes.
2430 if (TM.Options.NoNaNsFPMath)
2431 Condition = getFCmpCodeWithoutNaN(Condition);
2432 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2434 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2437 void SelectionDAGBuilder::visitSelect(const User &I) {
2438 SmallVector<EVT, 4> ValueVTs;
2439 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2441 unsigned NumValues = ValueVTs.size();
2442 if (NumValues == 0) return;
2444 SmallVector<SDValue, 4> Values(NumValues);
2445 SDValue Cond = getValue(I.getOperand(0));
2446 SDValue LHSVal = getValue(I.getOperand(1));
2447 SDValue RHSVal = getValue(I.getOperand(2));
2448 auto BaseOps = {Cond};
2449 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2450 ISD::VSELECT : ISD::SELECT;
2452 // Min/max matching is only viable if all output VTs are the same.
2453 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2454 EVT VT = ValueVTs[0];
2455 LLVMContext &Ctx = *DAG.getContext();
2456 auto &TLI = DAG.getTargetLoweringInfo();
2457 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2458 VT = TLI.getTypeToTransformTo(Ctx, VT);
2461 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2462 ISD::NodeType Opc = ISD::DELETED_NODE;
2463 switch (SPR.Flavor) {
2464 case SPF_UMAX: Opc = ISD::UMAX; break;
2465 case SPF_UMIN: Opc = ISD::UMIN; break;
2466 case SPF_SMAX: Opc = ISD::SMAX; break;
2467 case SPF_SMIN: Opc = ISD::SMIN; break;
2469 switch (SPR.NaNBehavior) {
2470 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2471 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2472 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2473 case SPNB_RETURNS_ANY:
2474 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2480 switch (SPR.NaNBehavior) {
2481 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2482 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2483 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2484 case SPNB_RETURNS_ANY:
2485 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2493 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2494 // If the underlying comparison instruction is used by any other instruction,
2495 // the consumed instructions won't be destroyed, so it is not profitable
2496 // to convert to a min/max.
2497 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2499 LHSVal = getValue(LHS);
2500 RHSVal = getValue(RHS);
2505 for (unsigned i = 0; i != NumValues; ++i) {
2506 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2507 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2508 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2509 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2510 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2514 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2515 DAG.getVTList(ValueVTs), Values));
2518 void SelectionDAGBuilder::visitTrunc(const User &I) {
2519 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2520 SDValue N = getValue(I.getOperand(0));
2521 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2523 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2526 void SelectionDAGBuilder::visitZExt(const User &I) {
2527 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2528 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2529 SDValue N = getValue(I.getOperand(0));
2530 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2532 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2535 void SelectionDAGBuilder::visitSExt(const User &I) {
2536 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2537 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2538 SDValue N = getValue(I.getOperand(0));
2539 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2541 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2544 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2545 // FPTrunc is never a no-op cast, no need to check
2546 SDValue N = getValue(I.getOperand(0));
2547 SDLoc dl = getCurSDLoc();
2548 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2549 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2550 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2551 DAG.getTargetConstant(
2552 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2555 void SelectionDAGBuilder::visitFPExt(const User &I) {
2556 // FPExt is never a no-op cast, no need to check
2557 SDValue N = getValue(I.getOperand(0));
2558 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2560 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2563 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2564 // FPToUI is never a no-op cast, no need to check
2565 SDValue N = getValue(I.getOperand(0));
2566 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2568 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2571 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2572 // FPToSI is never a no-op cast, no need to check
2573 SDValue N = getValue(I.getOperand(0));
2574 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2576 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2579 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2580 // UIToFP is never a no-op cast, no need to check
2581 SDValue N = getValue(I.getOperand(0));
2582 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2584 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2587 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2588 // SIToFP is never a no-op cast, no need to check
2589 SDValue N = getValue(I.getOperand(0));
2590 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2592 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2595 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2596 // What to do depends on the size of the integer and the size of the pointer.
2597 // We can either truncate, zero extend, or no-op, accordingly.
2598 SDValue N = getValue(I.getOperand(0));
2599 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2601 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2604 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2605 // What to do depends on the size of the integer and the size of the pointer.
2606 // We can either truncate, zero extend, or no-op, accordingly.
2607 SDValue N = getValue(I.getOperand(0));
2608 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2610 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2613 void SelectionDAGBuilder::visitBitCast(const User &I) {
2614 SDValue N = getValue(I.getOperand(0));
2615 SDLoc dl = getCurSDLoc();
2616 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2619 // BitCast assures us that source and destination are the same size so this is
2620 // either a BITCAST or a no-op.
2621 if (DestVT != N.getValueType())
2622 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2623 DestVT, N)); // convert types.
2624 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2625 // might fold any kind of constant expression to an integer constant and that
2626 // is not what we are looking for. Only regcognize a bitcast of a genuine
2627 // constant integer as an opaque constant.
2628 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2629 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2632 setValue(&I, N); // noop cast.
2635 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2636 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2637 const Value *SV = I.getOperand(0);
2638 SDValue N = getValue(SV);
2639 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2641 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2642 unsigned DestAS = I.getType()->getPointerAddressSpace();
2644 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2645 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2650 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2651 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2652 SDValue InVec = getValue(I.getOperand(0));
2653 SDValue InVal = getValue(I.getOperand(1));
2654 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2655 TLI.getVectorIdxTy(DAG.getDataLayout()));
2656 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2657 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2658 InVec, InVal, InIdx));
2661 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2662 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2663 SDValue InVec = getValue(I.getOperand(0));
2664 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2665 TLI.getVectorIdxTy(DAG.getDataLayout()));
2666 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2667 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2671 // Utility for visitShuffleVector - Return true if every element in Mask,
2672 // beginning from position Pos and ending in Pos+Size, falls within the
2673 // specified sequential range [L, L+Pos). or is undef.
2674 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2675 unsigned Pos, unsigned Size, int Low) {
2676 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2677 if (Mask[i] >= 0 && Mask[i] != Low)
2682 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2683 SDValue Src1 = getValue(I.getOperand(0));
2684 SDValue Src2 = getValue(I.getOperand(1));
2686 SmallVector<int, 8> Mask;
2687 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2688 unsigned MaskNumElts = Mask.size();
2690 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2691 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2692 EVT SrcVT = Src1.getValueType();
2693 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2695 if (SrcNumElts == MaskNumElts) {
2696 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2701 // Normalize the shuffle vector since mask and vector length don't match.
2702 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2703 // Mask is longer than the source vectors and is a multiple of the source
2704 // vectors. We can use concatenate vector to make the mask and vectors
2706 if (SrcNumElts*2 == MaskNumElts) {
2707 // First check for Src1 in low and Src2 in high
2708 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2709 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2710 // The shuffle is concatenating two vectors together.
2711 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2715 // Then check for Src2 in low and Src1 in high
2716 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2717 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2718 // The shuffle is concatenating two vectors together.
2719 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2725 // Pad both vectors with undefs to make them the same length as the mask.
2726 unsigned NumConcat = MaskNumElts / SrcNumElts;
2727 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2728 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2729 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2731 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2732 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2736 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2737 getCurSDLoc(), VT, MOps1);
2738 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2739 getCurSDLoc(), VT, MOps2);
2741 // Readjust mask for new input vector length.
2742 SmallVector<int, 8> MappedOps;
2743 for (unsigned i = 0; i != MaskNumElts; ++i) {
2745 if (Idx >= (int)SrcNumElts)
2746 Idx -= SrcNumElts - MaskNumElts;
2747 MappedOps.push_back(Idx);
2750 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2755 if (SrcNumElts > MaskNumElts) {
2756 // Analyze the access pattern of the vector to see if we can extract
2757 // two subvectors and do the shuffle. The analysis is done by calculating
2758 // the range of elements the mask access on both vectors.
2759 int MinRange[2] = { static_cast<int>(SrcNumElts),
2760 static_cast<int>(SrcNumElts)};
2761 int MaxRange[2] = {-1, -1};
2763 for (unsigned i = 0; i != MaskNumElts; ++i) {
2769 if (Idx >= (int)SrcNumElts) {
2773 if (Idx > MaxRange[Input])
2774 MaxRange[Input] = Idx;
2775 if (Idx < MinRange[Input])
2776 MinRange[Input] = Idx;
2779 // Check if the access is smaller than the vector size and can we find
2780 // a reasonable extract index.
2781 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2783 int StartIdx[2]; // StartIdx to extract from
2784 for (unsigned Input = 0; Input < 2; ++Input) {
2785 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2786 RangeUse[Input] = 0; // Unused
2787 StartIdx[Input] = 0;
2791 // Find a good start index that is a multiple of the mask length. Then
2792 // see if the rest of the elements are in range.
2793 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2794 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2795 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2796 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2799 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2800 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2803 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2804 // Extract appropriate subvector and generate a vector shuffle
2805 for (unsigned Input = 0; Input < 2; ++Input) {
2806 SDValue &Src = Input == 0 ? Src1 : Src2;
2807 if (RangeUse[Input] == 0)
2808 Src = DAG.getUNDEF(VT);
2810 SDLoc dl = getCurSDLoc();
2812 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2813 DAG.getConstant(StartIdx[Input], dl,
2814 TLI.getVectorIdxTy(DAG.getDataLayout())));
2818 // Calculate new mask.
2819 SmallVector<int, 8> MappedOps;
2820 for (unsigned i = 0; i != MaskNumElts; ++i) {
2823 if (Idx < (int)SrcNumElts)
2826 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2828 MappedOps.push_back(Idx);
2831 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2837 // We can't use either concat vectors or extract subvectors so fall back to
2838 // replacing the shuffle with extract and build vector.
2839 // to insert and build vector.
2840 EVT EltVT = VT.getVectorElementType();
2841 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2842 SDLoc dl = getCurSDLoc();
2843 SmallVector<SDValue,8> Ops;
2844 for (unsigned i = 0; i != MaskNumElts; ++i) {
2849 Res = DAG.getUNDEF(EltVT);
2851 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2852 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2854 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2855 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2861 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2864 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2865 const Value *Op0 = I.getOperand(0);
2866 const Value *Op1 = I.getOperand(1);
2867 Type *AggTy = I.getType();
2868 Type *ValTy = Op1->getType();
2869 bool IntoUndef = isa<UndefValue>(Op0);
2870 bool FromUndef = isa<UndefValue>(Op1);
2872 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2874 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2875 SmallVector<EVT, 4> AggValueVTs;
2876 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2877 SmallVector<EVT, 4> ValValueVTs;
2878 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2880 unsigned NumAggValues = AggValueVTs.size();
2881 unsigned NumValValues = ValValueVTs.size();
2882 SmallVector<SDValue, 4> Values(NumAggValues);
2884 // Ignore an insertvalue that produces an empty object
2885 if (!NumAggValues) {
2886 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2890 SDValue Agg = getValue(Op0);
2892 // Copy the beginning value(s) from the original aggregate.
2893 for (; i != LinearIndex; ++i)
2894 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2895 SDValue(Agg.getNode(), Agg.getResNo() + i);
2896 // Copy values from the inserted value(s).
2898 SDValue Val = getValue(Op1);
2899 for (; i != LinearIndex + NumValValues; ++i)
2900 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2901 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2903 // Copy remaining value(s) from the original aggregate.
2904 for (; i != NumAggValues; ++i)
2905 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2906 SDValue(Agg.getNode(), Agg.getResNo() + i);
2908 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2909 DAG.getVTList(AggValueVTs), Values));
2912 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2913 const Value *Op0 = I.getOperand(0);
2914 Type *AggTy = Op0->getType();
2915 Type *ValTy = I.getType();
2916 bool OutOfUndef = isa<UndefValue>(Op0);
2918 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2920 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2921 SmallVector<EVT, 4> ValValueVTs;
2922 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2924 unsigned NumValValues = ValValueVTs.size();
2926 // Ignore a extractvalue that produces an empty object
2927 if (!NumValValues) {
2928 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2932 SmallVector<SDValue, 4> Values(NumValValues);
2934 SDValue Agg = getValue(Op0);
2935 // Copy out the selected value(s).
2936 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2937 Values[i - LinearIndex] =
2939 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2940 SDValue(Agg.getNode(), Agg.getResNo() + i);
2942 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2943 DAG.getVTList(ValValueVTs), Values));
2946 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2947 Value *Op0 = I.getOperand(0);
2948 // Note that the pointer operand may be a vector of pointers. Take the scalar
2949 // element which holds a pointer.
2950 Type *Ty = Op0->getType()->getScalarType();
2951 unsigned AS = Ty->getPointerAddressSpace();
2952 SDValue N = getValue(Op0);
2953 SDLoc dl = getCurSDLoc();
2955 // Normalize Vector GEP - all scalar operands should be converted to the
2957 unsigned VectorWidth = I.getType()->isVectorTy() ?
2958 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2960 if (VectorWidth && !N.getValueType().isVector()) {
2961 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2962 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2963 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2965 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2967 const Value *Idx = *OI;
2968 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2969 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2972 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2973 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2974 DAG.getConstant(Offset, dl, N.getValueType()));
2977 Ty = StTy->getElementType(Field);
2979 Ty = cast<SequentialType>(Ty)->getElementType();
2981 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2982 unsigned PtrSize = PtrTy.getSizeInBits();
2983 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2985 // If this is a scalar constant or a splat vector of constants,
2986 // handle it quickly.
2987 const auto *CI = dyn_cast<ConstantInt>(Idx);
2988 if (!CI && isa<ConstantDataVector>(Idx) &&
2989 cast<ConstantDataVector>(Idx)->getSplatValue())
2990 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
2995 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
2996 SDValue OffsVal = VectorWidth ?
2997 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
2998 DAG.getConstant(Offs, dl, PtrTy);
2999 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
3003 // N = N + Idx * ElementSize;
3004 SDValue IdxN = getValue(Idx);
3006 if (!IdxN.getValueType().isVector() && VectorWidth) {
3007 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3008 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3009 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3011 // If the index is smaller or larger than intptr_t, truncate or extend
3013 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3015 // If this is a multiply by a power of two, turn it into a shl
3016 // immediately. This is a very common case.
3017 if (ElementSize != 1) {
3018 if (ElementSize.isPowerOf2()) {
3019 unsigned Amt = ElementSize.logBase2();
3020 IdxN = DAG.getNode(ISD::SHL, dl,
3021 N.getValueType(), IdxN,
3022 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3024 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3025 IdxN = DAG.getNode(ISD::MUL, dl,
3026 N.getValueType(), IdxN, Scale);
3030 N = DAG.getNode(ISD::ADD, dl,
3031 N.getValueType(), N, IdxN);
3038 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3039 // If this is a fixed sized alloca in the entry block of the function,
3040 // allocate it statically on the stack.
3041 if (FuncInfo.StaticAllocaMap.count(&I))
3042 return; // getValue will auto-populate this.
3044 SDLoc dl = getCurSDLoc();
3045 Type *Ty = I.getAllocatedType();
3046 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3047 auto &DL = DAG.getDataLayout();
3048 uint64_t TySize = DL.getTypeAllocSize(Ty);
3050 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3052 SDValue AllocSize = getValue(I.getArraySize());
3054 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3055 if (AllocSize.getValueType() != IntPtr)
3056 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3058 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3060 DAG.getConstant(TySize, dl, IntPtr));
3062 // Handle alignment. If the requested alignment is less than or equal to
3063 // the stack alignment, ignore it. If the size is greater than or equal to
3064 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3065 unsigned StackAlign =
3066 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3067 if (Align <= StackAlign)
3070 // Round the size of the allocation up to the stack alignment size
3071 // by add SA-1 to the size.
3072 AllocSize = DAG.getNode(ISD::ADD, dl,
3073 AllocSize.getValueType(), AllocSize,
3074 DAG.getIntPtrConstant(StackAlign - 1, dl));
3076 // Mask out the low bits for alignment purposes.
3077 AllocSize = DAG.getNode(ISD::AND, dl,
3078 AllocSize.getValueType(), AllocSize,
3079 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3082 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3083 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3084 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3086 DAG.setRoot(DSA.getValue(1));
3088 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3091 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3093 return visitAtomicLoad(I);
3095 const Value *SV = I.getOperand(0);
3096 SDValue Ptr = getValue(SV);
3098 Type *Ty = I.getType();
3100 bool isVolatile = I.isVolatile();
3101 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3103 // The IR notion of invariant_load only guarantees that all *non-faulting*
3104 // invariant loads result in the same value. The MI notion of invariant load
3105 // guarantees that the load can be legally moved to any location within its
3106 // containing function. The MI notion of invariant_load is stronger than the
3107 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3108 // with a guarantee that the location being loaded from is dereferenceable
3109 // throughout the function's lifetime.
3111 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3112 isDereferenceablePointer(SV, DAG.getDataLayout());
3113 unsigned Alignment = I.getAlignment();
3116 I.getAAMetadata(AAInfo);
3117 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3119 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3120 SmallVector<EVT, 4> ValueVTs;
3121 SmallVector<uint64_t, 4> Offsets;
3122 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3123 unsigned NumValues = ValueVTs.size();
3128 bool ConstantMemory = false;
3129 if (isVolatile || NumValues > MaxParallelChains)
3130 // Serialize volatile loads with other side effects.
3132 else if (AA->pointsToConstantMemory(MemoryLocation(
3133 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3134 // Do not serialize (non-volatile) loads of constant memory with anything.
3135 Root = DAG.getEntryNode();
3136 ConstantMemory = true;
3138 // Do not serialize non-volatile loads against each other.
3139 Root = DAG.getRoot();
3142 SDLoc dl = getCurSDLoc();
3145 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3147 SmallVector<SDValue, 4> Values(NumValues);
3148 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3149 EVT PtrVT = Ptr.getValueType();
3150 unsigned ChainI = 0;
3151 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3152 // Serializing loads here may result in excessive register pressure, and
3153 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3154 // could recover a bit by hoisting nodes upward in the chain by recognizing
3155 // they are side-effect free or do not alias. The optimizer should really
3156 // avoid this case by converting large object/array copies to llvm.memcpy
3157 // (MaxParallelChains should always remain as failsafe).
3158 if (ChainI == MaxParallelChains) {
3159 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3160 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3161 makeArrayRef(Chains.data(), ChainI));
3165 SDValue A = DAG.getNode(ISD::ADD, dl,
3167 DAG.getConstant(Offsets[i], dl, PtrVT));
3168 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3169 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3170 isNonTemporal, isInvariant, Alignment, AAInfo,
3174 Chains[ChainI] = L.getValue(1);
3177 if (!ConstantMemory) {
3178 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3179 makeArrayRef(Chains.data(), ChainI));
3183 PendingLoads.push_back(Chain);
3186 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3187 DAG.getVTList(ValueVTs), Values));
3190 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3192 return visitAtomicStore(I);
3194 const Value *SrcV = I.getOperand(0);
3195 const Value *PtrV = I.getOperand(1);
3197 SmallVector<EVT, 4> ValueVTs;
3198 SmallVector<uint64_t, 4> Offsets;
3199 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3200 SrcV->getType(), ValueVTs, &Offsets);
3201 unsigned NumValues = ValueVTs.size();
3205 // Get the lowered operands. Note that we do this after
3206 // checking if NumResults is zero, because with zero results
3207 // the operands won't have values in the map.
3208 SDValue Src = getValue(SrcV);
3209 SDValue Ptr = getValue(PtrV);
3211 SDValue Root = getRoot();
3212 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3213 EVT PtrVT = Ptr.getValueType();
3214 bool isVolatile = I.isVolatile();
3215 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3216 unsigned Alignment = I.getAlignment();
3217 SDLoc dl = getCurSDLoc();
3220 I.getAAMetadata(AAInfo);
3222 unsigned ChainI = 0;
3223 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3224 // See visitLoad comments.
3225 if (ChainI == MaxParallelChains) {
3226 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3227 makeArrayRef(Chains.data(), ChainI));
3231 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3232 DAG.getConstant(Offsets[i], dl, PtrVT));
3233 SDValue St = DAG.getStore(Root, dl,
3234 SDValue(Src.getNode(), Src.getResNo() + i),
3235 Add, MachinePointerInfo(PtrV, Offsets[i]),
3236 isVolatile, isNonTemporal, Alignment, AAInfo);
3237 Chains[ChainI] = St;
3240 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3241 makeArrayRef(Chains.data(), ChainI));
3242 DAG.setRoot(StoreNode);
3245 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3246 SDLoc sdl = getCurSDLoc();
3248 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3249 Value *PtrOperand = I.getArgOperand(1);
3250 SDValue Ptr = getValue(PtrOperand);
3251 SDValue Src0 = getValue(I.getArgOperand(0));
3252 SDValue Mask = getValue(I.getArgOperand(3));
3253 EVT VT = Src0.getValueType();
3254 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3256 Alignment = DAG.getEVTAlignment(VT);
3259 I.getAAMetadata(AAInfo);
3261 MachineMemOperand *MMO =
3262 DAG.getMachineFunction().
3263 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3264 MachineMemOperand::MOStore, VT.getStoreSize(),
3266 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3268 DAG.setRoot(StoreNode);
3269 setValue(&I, StoreNode);
3272 // Get a uniform base for the Gather/Scatter intrinsic.
3273 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3274 // We try to represent it as a base pointer + vector of indices.
3275 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3276 // The first operand of the GEP may be a single pointer or a vector of pointers
3278 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3280 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3281 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3283 // When the first GEP operand is a single pointer - it is the uniform base we
3284 // are looking for. If first operand of the GEP is a splat vector - we
3285 // extract the spalt value and use it as a uniform base.
3286 // In all other cases the function returns 'false'.
3288 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3289 SelectionDAGBuilder* SDB) {
3291 SelectionDAG& DAG = SDB->DAG;
3292 LLVMContext &Context = *DAG.getContext();
3294 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3295 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3296 if (!GEP || GEP->getNumOperands() > 2)
3299 Value *GEPPtr = GEP->getPointerOperand();
3300 if (!GEPPtr->getType()->isVectorTy())
3302 else if (!(Ptr = getSplatValue(GEPPtr)))
3305 Value *IndexVal = GEP->getOperand(1);
3307 // The operands of the GEP may be defined in another basic block.
3308 // In this case we'll not find nodes for the operands.
3309 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3312 Base = SDB->getValue(Ptr);
3313 Index = SDB->getValue(IndexVal);
3315 // Suppress sign extension.
3316 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3317 if (SDB->findValue(Sext->getOperand(0))) {
3318 IndexVal = Sext->getOperand(0);
3319 Index = SDB->getValue(IndexVal);
3322 if (!Index.getValueType().isVector()) {
3323 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3324 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3325 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3326 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3331 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3332 SDLoc sdl = getCurSDLoc();
3334 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3335 Value *Ptr = I.getArgOperand(1);
3336 SDValue Src0 = getValue(I.getArgOperand(0));
3337 SDValue Mask = getValue(I.getArgOperand(3));
3338 EVT VT = Src0.getValueType();
3339 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3341 Alignment = DAG.getEVTAlignment(VT);
3342 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3345 I.getAAMetadata(AAInfo);
3349 Value *BasePtr = Ptr;
3350 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3352 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3353 MachineMemOperand *MMO = DAG.getMachineFunction().
3354 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3355 MachineMemOperand::MOStore, VT.getStoreSize(),
3358 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3359 Index = getValue(Ptr);
3361 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3362 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3364 DAG.setRoot(Scatter);
3365 setValue(&I, Scatter);
3368 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3369 SDLoc sdl = getCurSDLoc();
3371 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3372 Value *PtrOperand = I.getArgOperand(0);
3373 SDValue Ptr = getValue(PtrOperand);
3374 SDValue Src0 = getValue(I.getArgOperand(3));
3375 SDValue Mask = getValue(I.getArgOperand(2));
3377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3378 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3379 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3381 Alignment = DAG.getEVTAlignment(VT);
3384 I.getAAMetadata(AAInfo);
3385 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3387 SDValue InChain = DAG.getRoot();
3388 if (AA->pointsToConstantMemory(MemoryLocation(
3389 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3391 // Do not serialize (non-volatile) loads of constant memory with anything.
3392 InChain = DAG.getEntryNode();
3395 MachineMemOperand *MMO =
3396 DAG.getMachineFunction().
3397 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3398 MachineMemOperand::MOLoad, VT.getStoreSize(),
3399 Alignment, AAInfo, Ranges);
3401 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3403 SDValue OutChain = Load.getValue(1);
3404 DAG.setRoot(OutChain);
3408 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3409 SDLoc sdl = getCurSDLoc();
3411 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3412 Value *Ptr = I.getArgOperand(0);
3413 SDValue Src0 = getValue(I.getArgOperand(3));
3414 SDValue Mask = getValue(I.getArgOperand(2));
3416 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3417 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3418 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3420 Alignment = DAG.getEVTAlignment(VT);
3423 I.getAAMetadata(AAInfo);
3424 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3426 SDValue Root = DAG.getRoot();
3429 Value *BasePtr = Ptr;
3430 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3431 bool ConstantMemory = false;
3433 AA->pointsToConstantMemory(MemoryLocation(
3434 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3436 // Do not serialize (non-volatile) loads of constant memory with anything.
3437 Root = DAG.getEntryNode();
3438 ConstantMemory = true;
3441 MachineMemOperand *MMO =
3442 DAG.getMachineFunction().
3443 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3444 MachineMemOperand::MOLoad, VT.getStoreSize(),
3445 Alignment, AAInfo, Ranges);
3448 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3449 Index = getValue(Ptr);
3451 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3452 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3455 SDValue OutChain = Gather.getValue(1);
3456 if (!ConstantMemory)
3457 PendingLoads.push_back(OutChain);
3458 setValue(&I, Gather);
3461 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3462 SDLoc dl = getCurSDLoc();
3463 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3464 AtomicOrdering FailureOrder = I.getFailureOrdering();
3465 SynchronizationScope Scope = I.getSynchScope();
3467 SDValue InChain = getRoot();
3469 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3470 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3471 SDValue L = DAG.getAtomicCmpSwap(
3472 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3473 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3474 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3475 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3477 SDValue OutChain = L.getValue(2);
3480 DAG.setRoot(OutChain);
3483 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3484 SDLoc dl = getCurSDLoc();
3486 switch (I.getOperation()) {
3487 default: llvm_unreachable("Unknown atomicrmw operation");
3488 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3489 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3490 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3491 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3492 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3493 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3494 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3495 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3496 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3497 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3498 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3500 AtomicOrdering Order = I.getOrdering();
3501 SynchronizationScope Scope = I.getSynchScope();
3503 SDValue InChain = getRoot();
3506 DAG.getAtomic(NT, dl,
3507 getValue(I.getValOperand()).getSimpleValueType(),
3509 getValue(I.getPointerOperand()),
3510 getValue(I.getValOperand()),
3511 I.getPointerOperand(),
3512 /* Alignment=*/ 0, Order, Scope);
3514 SDValue OutChain = L.getValue(1);
3517 DAG.setRoot(OutChain);
3520 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3521 SDLoc dl = getCurSDLoc();
3522 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3525 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3526 TLI.getPointerTy(DAG.getDataLayout()));
3527 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3528 TLI.getPointerTy(DAG.getDataLayout()));
3529 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3532 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3533 SDLoc dl = getCurSDLoc();
3534 AtomicOrdering Order = I.getOrdering();
3535 SynchronizationScope Scope = I.getSynchScope();
3537 SDValue InChain = getRoot();
3539 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3540 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3542 if (I.getAlignment() < VT.getSizeInBits() / 8)
3543 report_fatal_error("Cannot generate unaligned atomic load");
3545 MachineMemOperand *MMO =
3546 DAG.getMachineFunction().
3547 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3548 MachineMemOperand::MOVolatile |
3549 MachineMemOperand::MOLoad,
3551 I.getAlignment() ? I.getAlignment() :
3552 DAG.getEVTAlignment(VT));
3554 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3556 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3557 getValue(I.getPointerOperand()), MMO,
3560 SDValue OutChain = L.getValue(1);
3563 DAG.setRoot(OutChain);
3566 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3567 SDLoc dl = getCurSDLoc();
3569 AtomicOrdering Order = I.getOrdering();
3570 SynchronizationScope Scope = I.getSynchScope();
3572 SDValue InChain = getRoot();
3574 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3576 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3578 if (I.getAlignment() < VT.getSizeInBits() / 8)
3579 report_fatal_error("Cannot generate unaligned atomic store");
3582 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3584 getValue(I.getPointerOperand()),
3585 getValue(I.getValueOperand()),
3586 I.getPointerOperand(), I.getAlignment(),
3589 DAG.setRoot(OutChain);
3592 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3594 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3595 unsigned Intrinsic) {
3596 bool HasChain = !I.doesNotAccessMemory();
3597 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3599 // Build the operand list.
3600 SmallVector<SDValue, 8> Ops;
3601 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3603 // We don't need to serialize loads against other loads.
3604 Ops.push_back(DAG.getRoot());
3606 Ops.push_back(getRoot());
3610 // Info is set by getTgtMemInstrinsic
3611 TargetLowering::IntrinsicInfo Info;
3612 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3613 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3615 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3616 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3617 Info.opc == ISD::INTRINSIC_W_CHAIN)
3618 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3619 TLI.getPointerTy(DAG.getDataLayout())));
3621 // Add all operands of the call to the operand list.
3622 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3623 SDValue Op = getValue(I.getArgOperand(i));
3627 SmallVector<EVT, 4> ValueVTs;
3628 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3631 ValueVTs.push_back(MVT::Other);
3633 SDVTList VTs = DAG.getVTList(ValueVTs);
3637 if (IsTgtIntrinsic) {
3638 // This is target intrinsic that touches memory
3639 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3640 VTs, Ops, Info.memVT,
3641 MachinePointerInfo(Info.ptrVal, Info.offset),
3642 Info.align, Info.vol,
3643 Info.readMem, Info.writeMem, Info.size);
3644 } else if (!HasChain) {
3645 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3646 } else if (!I.getType()->isVoidTy()) {
3647 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3649 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3653 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3655 PendingLoads.push_back(Chain);
3660 if (!I.getType()->isVoidTy()) {
3661 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3662 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3663 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3666 setValue(&I, Result);
3670 /// GetSignificand - Get the significand and build it into a floating-point
3671 /// number with exponent of 1:
3673 /// Op = (Op & 0x007fffff) | 0x3f800000;
3675 /// where Op is the hexadecimal representation of floating point value.
3677 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3678 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3679 DAG.getConstant(0x007fffff, dl, MVT::i32));
3680 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3681 DAG.getConstant(0x3f800000, dl, MVT::i32));
3682 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3685 /// GetExponent - Get the exponent:
3687 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3689 /// where Op is the hexadecimal representation of floating point value.
3691 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3693 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3694 DAG.getConstant(0x7f800000, dl, MVT::i32));
3695 SDValue t1 = DAG.getNode(
3696 ISD::SRL, dl, MVT::i32, t0,
3697 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3698 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3699 DAG.getConstant(127, dl, MVT::i32));
3700 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3703 /// getF32Constant - Get 32-bit floating point constant.
3705 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3706 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3710 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3711 SelectionDAG &DAG) {
3712 // TODO: What fast-math-flags should be set on the floating-point nodes?
3714 // IntegerPartOfX = ((int32_t)(t0);
3715 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3717 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3718 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3719 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3721 // IntegerPartOfX <<= 23;
3722 IntegerPartOfX = DAG.getNode(
3723 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3724 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3725 DAG.getDataLayout())));
3727 SDValue TwoToFractionalPartOfX;
3728 if (LimitFloatPrecision <= 6) {
3729 // For floating-point precision of 6:
3731 // TwoToFractionalPartOfX =
3733 // (0.735607626f + 0.252464424f * x) * x;
3735 // error 0.0144103317, which is 6 bits
3736 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3737 getF32Constant(DAG, 0x3e814304, dl));
3738 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3739 getF32Constant(DAG, 0x3f3c50c8, dl));
3740 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3741 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3742 getF32Constant(DAG, 0x3f7f5e7e, dl));
3743 } else if (LimitFloatPrecision <= 12) {
3744 // For floating-point precision of 12:
3746 // TwoToFractionalPartOfX =
3749 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3751 // error 0.000107046256, which is 13 to 14 bits
3752 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3753 getF32Constant(DAG, 0x3da235e3, dl));
3754 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3755 getF32Constant(DAG, 0x3e65b8f3, dl));
3756 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3757 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3758 getF32Constant(DAG, 0x3f324b07, dl));
3759 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3760 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3761 getF32Constant(DAG, 0x3f7ff8fd, dl));
3762 } else { // LimitFloatPrecision <= 18
3763 // For floating-point precision of 18:
3765 // TwoToFractionalPartOfX =
3769 // (0.554906021e-1f +
3770 // (0.961591928e-2f +
3771 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3772 // error 2.47208000*10^(-7), which is better than 18 bits
3773 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3774 getF32Constant(DAG, 0x3924b03e, dl));
3775 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3776 getF32Constant(DAG, 0x3ab24b87, dl));
3777 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3778 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3779 getF32Constant(DAG, 0x3c1d8c17, dl));
3780 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3781 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3782 getF32Constant(DAG, 0x3d634a1d, dl));
3783 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3784 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3785 getF32Constant(DAG, 0x3e75fe14, dl));
3786 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3787 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3788 getF32Constant(DAG, 0x3f317234, dl));
3789 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3790 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3791 getF32Constant(DAG, 0x3f800000, dl));
3794 // Add the exponent into the result in integer domain.
3795 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3796 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3797 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3800 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3801 /// limited-precision mode.
3802 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3803 const TargetLowering &TLI) {
3804 if (Op.getValueType() == MVT::f32 &&
3805 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3807 // Put the exponent in the right bit position for later addition to the
3810 // #define LOG2OFe 1.4426950f
3811 // t0 = Op * LOG2OFe
3813 // TODO: What fast-math-flags should be set here?
3814 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3815 getF32Constant(DAG, 0x3fb8aa3b, dl));
3816 return getLimitedPrecisionExp2(t0, dl, DAG);
3819 // No special expansion.
3820 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3823 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3824 /// limited-precision mode.
3825 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3826 const TargetLowering &TLI) {
3828 // TODO: What fast-math-flags should be set on the floating-point nodes?
3830 if (Op.getValueType() == MVT::f32 &&
3831 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3832 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3834 // Scale the exponent by log(2) [0.69314718f].
3835 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3836 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3837 getF32Constant(DAG, 0x3f317218, dl));
3839 // Get the significand and build it into a floating-point number with
3841 SDValue X = GetSignificand(DAG, Op1, dl);
3843 SDValue LogOfMantissa;
3844 if (LimitFloatPrecision <= 6) {
3845 // For floating-point precision of 6:
3849 // (1.4034025f - 0.23903021f * x) * x;
3851 // error 0.0034276066, which is better than 8 bits
3852 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3853 getF32Constant(DAG, 0xbe74c456, dl));
3854 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3855 getF32Constant(DAG, 0x3fb3a2b1, dl));
3856 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3857 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3858 getF32Constant(DAG, 0x3f949a29, dl));
3859 } else if (LimitFloatPrecision <= 12) {
3860 // For floating-point precision of 12:
3866 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3868 // error 0.000061011436, which is 14 bits
3869 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3870 getF32Constant(DAG, 0xbd67b6d6, dl));
3871 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3872 getF32Constant(DAG, 0x3ee4f4b8, dl));
3873 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3874 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3875 getF32Constant(DAG, 0x3fbc278b, dl));
3876 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3877 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3878 getF32Constant(DAG, 0x40348e95, dl));
3879 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3880 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3881 getF32Constant(DAG, 0x3fdef31a, dl));
3882 } else { // LimitFloatPrecision <= 18
3883 // For floating-point precision of 18:
3891 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3893 // error 0.0000023660568, which is better than 18 bits
3894 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3895 getF32Constant(DAG, 0xbc91e5ac, dl));
3896 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3897 getF32Constant(DAG, 0x3e4350aa, dl));
3898 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3899 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3900 getF32Constant(DAG, 0x3f60d3e3, dl));
3901 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3902 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3903 getF32Constant(DAG, 0x4011cdf0, dl));
3904 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3905 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3906 getF32Constant(DAG, 0x406cfd1c, dl));
3907 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3908 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3909 getF32Constant(DAG, 0x408797cb, dl));
3910 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3911 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3912 getF32Constant(DAG, 0x4006dcab, dl));
3915 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3918 // No special expansion.
3919 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3922 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3923 /// limited-precision mode.
3924 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3925 const TargetLowering &TLI) {
3927 // TODO: What fast-math-flags should be set on the floating-point nodes?
3929 if (Op.getValueType() == MVT::f32 &&
3930 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3931 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3933 // Get the exponent.
3934 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3936 // Get the significand and build it into a floating-point number with
3938 SDValue X = GetSignificand(DAG, Op1, dl);
3940 // Different possible minimax approximations of significand in
3941 // floating-point for various degrees of accuracy over [1,2].
3942 SDValue Log2ofMantissa;
3943 if (LimitFloatPrecision <= 6) {
3944 // For floating-point precision of 6:
3946 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3948 // error 0.0049451742, which is more than 7 bits
3949 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3950 getF32Constant(DAG, 0xbeb08fe0, dl));
3951 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3952 getF32Constant(DAG, 0x40019463, dl));
3953 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3954 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3955 getF32Constant(DAG, 0x3fd6633d, dl));
3956 } else if (LimitFloatPrecision <= 12) {
3957 // For floating-point precision of 12:
3963 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3965 // error 0.0000876136000, which is better than 13 bits
3966 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3967 getF32Constant(DAG, 0xbda7262e, dl));
3968 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3969 getF32Constant(DAG, 0x3f25280b, dl));
3970 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3971 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3972 getF32Constant(DAG, 0x4007b923, dl));
3973 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3974 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3975 getF32Constant(DAG, 0x40823e2f, dl));
3976 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3977 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3978 getF32Constant(DAG, 0x4020d29c, dl));
3979 } else { // LimitFloatPrecision <= 18
3980 // For floating-point precision of 18:
3989 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3991 // error 0.0000018516, which is better than 18 bits
3992 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3993 getF32Constant(DAG, 0xbcd2769e, dl));
3994 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3995 getF32Constant(DAG, 0x3e8ce0b9, dl));
3996 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3997 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3998 getF32Constant(DAG, 0x3fa22ae7, dl));
3999 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4000 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4001 getF32Constant(DAG, 0x40525723, dl));
4002 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4003 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4004 getF32Constant(DAG, 0x40aaf200, dl));
4005 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4006 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4007 getF32Constant(DAG, 0x40c39dad, dl));
4008 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4009 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4010 getF32Constant(DAG, 0x4042902c, dl));
4013 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4016 // No special expansion.
4017 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4020 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4021 /// limited-precision mode.
4022 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4023 const TargetLowering &TLI) {
4025 // TODO: What fast-math-flags should be set on the floating-point nodes?
4027 if (Op.getValueType() == MVT::f32 &&
4028 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4029 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4031 // Scale the exponent by log10(2) [0.30102999f].
4032 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4033 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4034 getF32Constant(DAG, 0x3e9a209a, dl));
4036 // Get the significand and build it into a floating-point number with
4038 SDValue X = GetSignificand(DAG, Op1, dl);
4040 SDValue Log10ofMantissa;
4041 if (LimitFloatPrecision <= 6) {
4042 // For floating-point precision of 6:
4044 // Log10ofMantissa =
4046 // (0.60948995f - 0.10380950f * x) * x;
4048 // error 0.0014886165, which is 6 bits
4049 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4050 getF32Constant(DAG, 0xbdd49a13, dl));
4051 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4052 getF32Constant(DAG, 0x3f1c0789, dl));
4053 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4054 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4055 getF32Constant(DAG, 0x3f011300, dl));
4056 } else if (LimitFloatPrecision <= 12) {
4057 // For floating-point precision of 12:
4059 // Log10ofMantissa =
4062 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4064 // error 0.00019228036, which is better than 12 bits
4065 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4066 getF32Constant(DAG, 0x3d431f31, dl));
4067 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4068 getF32Constant(DAG, 0x3ea21fb2, dl));
4069 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4070 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4071 getF32Constant(DAG, 0x3f6ae232, dl));
4072 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4073 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4074 getF32Constant(DAG, 0x3f25f7c3, dl));
4075 } else { // LimitFloatPrecision <= 18
4076 // For floating-point precision of 18:
4078 // Log10ofMantissa =
4083 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4085 // error 0.0000037995730, which is better than 18 bits
4086 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4087 getF32Constant(DAG, 0x3c5d51ce, dl));
4088 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4089 getF32Constant(DAG, 0x3e00685a, dl));
4090 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4091 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4092 getF32Constant(DAG, 0x3efb6798, dl));
4093 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4094 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4095 getF32Constant(DAG, 0x3f88d192, dl));
4096 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4097 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4098 getF32Constant(DAG, 0x3fc4316c, dl));
4099 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4100 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4101 getF32Constant(DAG, 0x3f57ce70, dl));
4104 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4107 // No special expansion.
4108 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4111 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4112 /// limited-precision mode.
4113 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4114 const TargetLowering &TLI) {
4115 if (Op.getValueType() == MVT::f32 &&
4116 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4117 return getLimitedPrecisionExp2(Op, dl, DAG);
4119 // No special expansion.
4120 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4123 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4124 /// limited-precision mode with x == 10.0f.
4125 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4126 SelectionDAG &DAG, const TargetLowering &TLI) {
4127 bool IsExp10 = false;
4128 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4129 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4130 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4132 IsExp10 = LHSC->isExactlyValue(Ten);
4136 // TODO: What fast-math-flags should be set on the FMUL node?
4138 // Put the exponent in the right bit position for later addition to the
4141 // #define LOG2OF10 3.3219281f
4142 // t0 = Op * LOG2OF10;
4143 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4144 getF32Constant(DAG, 0x40549a78, dl));
4145 return getLimitedPrecisionExp2(t0, dl, DAG);
4148 // No special expansion.
4149 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4153 /// ExpandPowI - Expand a llvm.powi intrinsic.
4154 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4155 SelectionDAG &DAG) {
4156 // If RHS is a constant, we can expand this out to a multiplication tree,
4157 // otherwise we end up lowering to a call to __powidf2 (for example). When
4158 // optimizing for size, we only want to do this if the expansion would produce
4159 // a small number of multiplies, otherwise we do the full expansion.
4160 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4161 // Get the exponent as a positive value.
4162 unsigned Val = RHSC->getSExtValue();
4163 if ((int)Val < 0) Val = -Val;
4165 // powi(x, 0) -> 1.0
4167 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4169 const Function *F = DAG.getMachineFunction().getFunction();
4170 if (!F->optForSize() ||
4171 // If optimizing for size, don't insert too many multiplies.
4172 // This inserts up to 5 multiplies.
4173 countPopulation(Val) + Log2_32(Val) < 7) {
4174 // We use the simple binary decomposition method to generate the multiply
4175 // sequence. There are more optimal ways to do this (for example,
4176 // powi(x,15) generates one more multiply than it should), but this has
4177 // the benefit of being both really simple and much better than a libcall.
4178 SDValue Res; // Logically starts equal to 1.0
4179 SDValue CurSquare = LHS;
4180 // TODO: Intrinsics should have fast-math-flags that propagate to these
4185 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4187 Res = CurSquare; // 1.0*CurSquare.
4190 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4191 CurSquare, CurSquare);
4195 // If the original was negative, invert the result, producing 1/(x*x*x).
4196 if (RHSC->getSExtValue() < 0)
4197 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4198 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4203 // Otherwise, expand to a libcall.
4204 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4207 // getUnderlyingArgReg - Find underlying register used for a truncated or
4208 // bitcasted argument.
4209 static unsigned getUnderlyingArgReg(const SDValue &N) {
4210 switch (N.getOpcode()) {
4211 case ISD::CopyFromReg:
4212 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4214 case ISD::AssertZext:
4215 case ISD::AssertSext:
4217 return getUnderlyingArgReg(N.getOperand(0));
4223 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4224 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4225 /// At the end of instruction selection, they will be inserted to the entry BB.
4226 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4227 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4228 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4229 const Argument *Arg = dyn_cast<Argument>(V);
4233 MachineFunction &MF = DAG.getMachineFunction();
4234 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4236 // Ignore inlined function arguments here.
4238 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4239 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4242 Optional<MachineOperand> Op;
4243 // Some arguments' frame index is recorded during argument lowering.
4244 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4245 Op = MachineOperand::CreateFI(FI);
4247 if (!Op && N.getNode()) {
4248 unsigned Reg = getUnderlyingArgReg(N);
4249 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4250 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4251 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4256 Op = MachineOperand::CreateReg(Reg, false);
4260 // Check if ValueMap has reg number.
4261 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4262 if (VMI != FuncInfo.ValueMap.end())
4263 Op = MachineOperand::CreateReg(VMI->second, false);
4266 if (!Op && N.getNode())
4267 // Check if frame index is available.
4268 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4269 if (FrameIndexSDNode *FINode =
4270 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4271 Op = MachineOperand::CreateFI(FINode->getIndex());
4276 assert(Variable->isValidLocationForIntrinsic(DL) &&
4277 "Expected inlined-at fields to agree");
4279 FuncInfo.ArgDbgValues.push_back(
4280 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4281 Op->getReg(), Offset, Variable, Expr));
4283 FuncInfo.ArgDbgValues.push_back(
4284 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4287 .addMetadata(Variable)
4288 .addMetadata(Expr));
4293 // VisualStudio defines setjmp as _setjmp
4294 #if defined(_MSC_VER) && defined(setjmp) && \
4295 !defined(setjmp_undefined_for_msvc)
4296 # pragma push_macro("setjmp")
4298 # define setjmp_undefined_for_msvc
4301 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4302 /// we want to emit this as a call to a named external function, return the name
4303 /// otherwise lower it and return null.
4305 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4306 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4307 SDLoc sdl = getCurSDLoc();
4308 DebugLoc dl = getCurDebugLoc();
4311 switch (Intrinsic) {
4313 // By default, turn this into a target intrinsic node.
4314 visitTargetIntrinsic(I, Intrinsic);
4316 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4317 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4318 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4319 case Intrinsic::returnaddress:
4320 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4321 TLI.getPointerTy(DAG.getDataLayout()),
4322 getValue(I.getArgOperand(0))));
4324 case Intrinsic::frameaddress:
4325 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4326 TLI.getPointerTy(DAG.getDataLayout()),
4327 getValue(I.getArgOperand(0))));
4329 case Intrinsic::read_register: {
4330 Value *Reg = I.getArgOperand(0);
4331 SDValue Chain = getRoot();
4333 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4334 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4335 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4336 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4338 DAG.setRoot(Res.getValue(1));
4341 case Intrinsic::write_register: {
4342 Value *Reg = I.getArgOperand(0);
4343 Value *RegValue = I.getArgOperand(1);
4344 SDValue Chain = getRoot();
4346 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4347 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4348 RegName, getValue(RegValue)));
4351 case Intrinsic::setjmp:
4352 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4353 case Intrinsic::longjmp:
4354 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4355 case Intrinsic::memcpy: {
4356 // FIXME: this definition of "user defined address space" is x86-specific
4357 // Assert for address < 256 since we support only user defined address
4359 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4361 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4363 "Unknown address space");
4364 SDValue Op1 = getValue(I.getArgOperand(0));
4365 SDValue Op2 = getValue(I.getArgOperand(1));
4366 SDValue Op3 = getValue(I.getArgOperand(2));
4367 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4369 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4370 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4371 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4372 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4374 MachinePointerInfo(I.getArgOperand(0)),
4375 MachinePointerInfo(I.getArgOperand(1)));
4376 updateDAGForMaybeTailCall(MC);
4379 case Intrinsic::memset: {
4380 // FIXME: this definition of "user defined address space" is x86-specific
4381 // Assert for address < 256 since we support only user defined address
4383 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4385 "Unknown address space");
4386 SDValue Op1 = getValue(I.getArgOperand(0));
4387 SDValue Op2 = getValue(I.getArgOperand(1));
4388 SDValue Op3 = getValue(I.getArgOperand(2));
4389 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4391 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4392 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4393 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4394 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4395 isTC, MachinePointerInfo(I.getArgOperand(0)));
4396 updateDAGForMaybeTailCall(MS);
4399 case Intrinsic::memmove: {
4400 // FIXME: this definition of "user defined address space" is x86-specific
4401 // Assert for address < 256 since we support only user defined address
4403 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4405 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4407 "Unknown address space");
4408 SDValue Op1 = getValue(I.getArgOperand(0));
4409 SDValue Op2 = getValue(I.getArgOperand(1));
4410 SDValue Op3 = getValue(I.getArgOperand(2));
4411 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4413 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4414 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4415 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4416 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4417 isTC, MachinePointerInfo(I.getArgOperand(0)),
4418 MachinePointerInfo(I.getArgOperand(1)));
4419 updateDAGForMaybeTailCall(MM);
4422 case Intrinsic::dbg_declare: {
4423 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4424 DILocalVariable *Variable = DI.getVariable();
4425 DIExpression *Expression = DI.getExpression();
4426 const Value *Address = DI.getAddress();
4427 assert(Variable && "Missing variable");
4429 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4433 // Check if address has undef value.
4434 if (isa<UndefValue>(Address) ||
4435 (Address->use_empty() && !isa<Argument>(Address))) {
4436 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4440 SDValue &N = NodeMap[Address];
4441 if (!N.getNode() && isa<Argument>(Address))
4442 // Check unused arguments map.
4443 N = UnusedArgNodeMap[Address];
4446 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4447 Address = BCI->getOperand(0);
4448 // Parameters are handled specially.
4449 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4451 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4453 if (isParameter && !AI) {
4454 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4456 // Byval parameter. We have a frame index at this point.
4457 SDV = DAG.getFrameIndexDbgValue(
4458 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4460 // Address is an argument, so try to emit its dbg value using
4461 // virtual register info from the FuncInfo.ValueMap.
4462 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4467 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4468 true, 0, dl, SDNodeOrder);
4470 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4472 // If Address is an argument then try to emit its dbg value using
4473 // virtual register info from the FuncInfo.ValueMap.
4474 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4476 // If variable is pinned by a alloca in dominating bb then
4477 // use StaticAllocaMap.
4478 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4479 if (AI->getParent() != DI.getParent()) {
4480 DenseMap<const AllocaInst*, int>::iterator SI =
4481 FuncInfo.StaticAllocaMap.find(AI);
4482 if (SI != FuncInfo.StaticAllocaMap.end()) {
4483 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4484 0, dl, SDNodeOrder);
4485 DAG.AddDbgValue(SDV, nullptr, false);
4490 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4495 case Intrinsic::dbg_value: {
4496 const DbgValueInst &DI = cast<DbgValueInst>(I);
4497 assert(DI.getVariable() && "Missing variable");
4499 DILocalVariable *Variable = DI.getVariable();
4500 DIExpression *Expression = DI.getExpression();
4501 uint64_t Offset = DI.getOffset();
4502 const Value *V = DI.getValue();
4507 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4508 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4510 DAG.AddDbgValue(SDV, nullptr, false);
4512 // Do not use getValue() in here; we don't want to generate code at
4513 // this point if it hasn't been done yet.
4514 SDValue N = NodeMap[V];
4515 if (!N.getNode() && isa<Argument>(V))
4516 // Check unused arguments map.
4517 N = UnusedArgNodeMap[V];
4519 // A dbg.value for an alloca is always indirect.
4520 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4521 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4523 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4524 IsIndirect, Offset, dl, SDNodeOrder);
4525 DAG.AddDbgValue(SDV, N.getNode(), false);
4527 } else if (!V->use_empty() ) {
4528 // Do not call getValue(V) yet, as we don't want to generate code.
4529 // Remember it for later.
4530 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4531 DanglingDebugInfoMap[V] = DDI;
4533 // We may expand this to cover more cases. One case where we have no
4534 // data available is an unreferenced parameter.
4535 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4539 // Build a debug info table entry.
4540 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4541 V = BCI->getOperand(0);
4542 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4543 // Don't handle byval struct arguments or VLAs, for example.
4545 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4546 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4549 DenseMap<const AllocaInst*, int>::iterator SI =
4550 FuncInfo.StaticAllocaMap.find(AI);
4551 if (SI == FuncInfo.StaticAllocaMap.end())
4552 return nullptr; // VLAs.
4556 case Intrinsic::eh_typeid_for: {
4557 // Find the type id for the given typeinfo.
4558 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4559 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4560 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4565 case Intrinsic::eh_return_i32:
4566 case Intrinsic::eh_return_i64:
4567 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4568 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4571 getValue(I.getArgOperand(0)),
4572 getValue(I.getArgOperand(1))));
4574 case Intrinsic::eh_unwind_init:
4575 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4577 case Intrinsic::eh_dwarf_cfa: {
4578 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4579 TLI.getPointerTy(DAG.getDataLayout()));
4580 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4581 CfaArg.getValueType(),
4582 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4583 CfaArg.getValueType()),
4585 SDValue FA = DAG.getNode(
4586 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4587 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4588 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4592 case Intrinsic::eh_sjlj_callsite: {
4593 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4594 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4595 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4596 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4598 MMI.setCurrentCallSite(CI->getZExtValue());
4601 case Intrinsic::eh_sjlj_functioncontext: {
4602 // Get and store the index of the function context.
4603 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4605 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4606 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4607 MFI->setFunctionContextIndex(FI);
4610 case Intrinsic::eh_sjlj_setjmp: {
4613 Ops[1] = getValue(I.getArgOperand(0));
4614 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4615 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4616 setValue(&I, Op.getValue(0));
4617 DAG.setRoot(Op.getValue(1));
4620 case Intrinsic::eh_sjlj_longjmp: {
4621 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4622 getRoot(), getValue(I.getArgOperand(0))));
4625 case Intrinsic::eh_sjlj_setup_dispatch: {
4626 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4631 case Intrinsic::masked_gather:
4632 visitMaskedGather(I);
4634 case Intrinsic::masked_load:
4637 case Intrinsic::masked_scatter:
4638 visitMaskedScatter(I);
4640 case Intrinsic::masked_store:
4641 visitMaskedStore(I);
4643 case Intrinsic::x86_mmx_pslli_w:
4644 case Intrinsic::x86_mmx_pslli_d:
4645 case Intrinsic::x86_mmx_pslli_q:
4646 case Intrinsic::x86_mmx_psrli_w:
4647 case Intrinsic::x86_mmx_psrli_d:
4648 case Intrinsic::x86_mmx_psrli_q:
4649 case Intrinsic::x86_mmx_psrai_w:
4650 case Intrinsic::x86_mmx_psrai_d: {
4651 SDValue ShAmt = getValue(I.getArgOperand(1));
4652 if (isa<ConstantSDNode>(ShAmt)) {
4653 visitTargetIntrinsic(I, Intrinsic);
4656 unsigned NewIntrinsic = 0;
4657 EVT ShAmtVT = MVT::v2i32;
4658 switch (Intrinsic) {
4659 case Intrinsic::x86_mmx_pslli_w:
4660 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4662 case Intrinsic::x86_mmx_pslli_d:
4663 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4665 case Intrinsic::x86_mmx_pslli_q:
4666 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4668 case Intrinsic::x86_mmx_psrli_w:
4669 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4671 case Intrinsic::x86_mmx_psrli_d:
4672 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4674 case Intrinsic::x86_mmx_psrli_q:
4675 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4677 case Intrinsic::x86_mmx_psrai_w:
4678 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4680 case Intrinsic::x86_mmx_psrai_d:
4681 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4683 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4686 // The vector shift intrinsics with scalars uses 32b shift amounts but
4687 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4689 // We must do this early because v2i32 is not a legal type.
4692 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4693 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4694 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4695 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4696 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4697 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4698 getValue(I.getArgOperand(0)), ShAmt);
4702 case Intrinsic::convertff:
4703 case Intrinsic::convertfsi:
4704 case Intrinsic::convertfui:
4705 case Intrinsic::convertsif:
4706 case Intrinsic::convertuif:
4707 case Intrinsic::convertss:
4708 case Intrinsic::convertsu:
4709 case Intrinsic::convertus:
4710 case Intrinsic::convertuu: {
4711 ISD::CvtCode Code = ISD::CVT_INVALID;
4712 switch (Intrinsic) {
4713 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4714 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4715 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4716 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4717 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4718 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4719 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4720 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4721 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4722 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4724 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4725 const Value *Op1 = I.getArgOperand(0);
4726 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4727 DAG.getValueType(DestVT),
4728 DAG.getValueType(getValue(Op1).getValueType()),
4729 getValue(I.getArgOperand(1)),
4730 getValue(I.getArgOperand(2)),
4735 case Intrinsic::powi:
4736 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4737 getValue(I.getArgOperand(1)), DAG));
4739 case Intrinsic::log:
4740 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4742 case Intrinsic::log2:
4743 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4745 case Intrinsic::log10:
4746 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4748 case Intrinsic::exp:
4749 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4751 case Intrinsic::exp2:
4752 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4754 case Intrinsic::pow:
4755 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4756 getValue(I.getArgOperand(1)), DAG, TLI));
4758 case Intrinsic::sqrt:
4759 case Intrinsic::fabs:
4760 case Intrinsic::sin:
4761 case Intrinsic::cos:
4762 case Intrinsic::floor:
4763 case Intrinsic::ceil:
4764 case Intrinsic::trunc:
4765 case Intrinsic::rint:
4766 case Intrinsic::nearbyint:
4767 case Intrinsic::round: {
4769 switch (Intrinsic) {
4770 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4771 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4772 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4773 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4774 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4775 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4776 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4777 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4778 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4779 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4780 case Intrinsic::round: Opcode = ISD::FROUND; break;
4783 setValue(&I, DAG.getNode(Opcode, sdl,
4784 getValue(I.getArgOperand(0)).getValueType(),
4785 getValue(I.getArgOperand(0))));
4788 case Intrinsic::minnum:
4789 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4790 getValue(I.getArgOperand(0)).getValueType(),
4791 getValue(I.getArgOperand(0)),
4792 getValue(I.getArgOperand(1))));
4794 case Intrinsic::maxnum:
4795 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4796 getValue(I.getArgOperand(0)).getValueType(),
4797 getValue(I.getArgOperand(0)),
4798 getValue(I.getArgOperand(1))));
4800 case Intrinsic::copysign:
4801 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4802 getValue(I.getArgOperand(0)).getValueType(),
4803 getValue(I.getArgOperand(0)),
4804 getValue(I.getArgOperand(1))));
4806 case Intrinsic::fma:
4807 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4808 getValue(I.getArgOperand(0)).getValueType(),
4809 getValue(I.getArgOperand(0)),
4810 getValue(I.getArgOperand(1)),
4811 getValue(I.getArgOperand(2))));
4813 case Intrinsic::fmuladd: {
4814 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4815 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4816 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4817 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4818 getValue(I.getArgOperand(0)).getValueType(),
4819 getValue(I.getArgOperand(0)),
4820 getValue(I.getArgOperand(1)),
4821 getValue(I.getArgOperand(2))));
4823 // TODO: Intrinsic calls should have fast-math-flags.
4824 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4825 getValue(I.getArgOperand(0)).getValueType(),
4826 getValue(I.getArgOperand(0)),
4827 getValue(I.getArgOperand(1)));
4828 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4829 getValue(I.getArgOperand(0)).getValueType(),
4831 getValue(I.getArgOperand(2)));
4836 case Intrinsic::convert_to_fp16:
4837 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4838 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4839 getValue(I.getArgOperand(0)),
4840 DAG.getTargetConstant(0, sdl,
4843 case Intrinsic::convert_from_fp16:
4844 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4845 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4846 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4847 getValue(I.getArgOperand(0)))));
4849 case Intrinsic::pcmarker: {
4850 SDValue Tmp = getValue(I.getArgOperand(0));
4851 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4854 case Intrinsic::readcyclecounter: {
4855 SDValue Op = getRoot();
4856 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4857 DAG.getVTList(MVT::i64, MVT::Other), Op);
4859 DAG.setRoot(Res.getValue(1));
4862 case Intrinsic::bswap:
4863 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4864 getValue(I.getArgOperand(0)).getValueType(),
4865 getValue(I.getArgOperand(0))));
4867 case Intrinsic::uabsdiff:
4868 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4869 getValue(I.getArgOperand(0)).getValueType(),
4870 getValue(I.getArgOperand(0)),
4871 getValue(I.getArgOperand(1))));
4873 case Intrinsic::sabsdiff:
4874 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4875 getValue(I.getArgOperand(0)).getValueType(),
4876 getValue(I.getArgOperand(0)),
4877 getValue(I.getArgOperand(1))));
4879 case Intrinsic::cttz: {
4880 SDValue Arg = getValue(I.getArgOperand(0));
4881 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4882 EVT Ty = Arg.getValueType();
4883 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4887 case Intrinsic::ctlz: {
4888 SDValue Arg = getValue(I.getArgOperand(0));
4889 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4890 EVT Ty = Arg.getValueType();
4891 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4895 case Intrinsic::ctpop: {
4896 SDValue Arg = getValue(I.getArgOperand(0));
4897 EVT Ty = Arg.getValueType();
4898 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4901 case Intrinsic::stacksave: {
4902 SDValue Op = getRoot();
4904 ISD::STACKSAVE, sdl,
4905 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4907 DAG.setRoot(Res.getValue(1));
4910 case Intrinsic::stackrestore: {
4911 Res = getValue(I.getArgOperand(0));
4912 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4915 case Intrinsic::stackprotector: {
4916 // Emit code into the DAG to store the stack guard onto the stack.
4917 MachineFunction &MF = DAG.getMachineFunction();
4918 MachineFrameInfo *MFI = MF.getFrameInfo();
4919 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4920 SDValue Src, Chain = getRoot();
4921 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4922 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4924 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4925 // global variable __stack_chk_guard.
4927 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4928 if (BC->getOpcode() == Instruction::BitCast)
4929 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4931 if (GV && TLI.useLoadStackGuardNode()) {
4932 // Emit a LOAD_STACK_GUARD node.
4933 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4935 MachinePointerInfo MPInfo(GV);
4936 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4937 unsigned Flags = MachineMemOperand::MOLoad |
4938 MachineMemOperand::MOInvariant;
4939 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4940 PtrTy.getSizeInBits() / 8,
4941 DAG.getEVTAlignment(PtrTy));
4942 Node->setMemRefs(MemRefs, MemRefs + 1);
4944 // Copy the guard value to a virtual register so that it can be
4945 // retrieved in the epilogue.
4946 Src = SDValue(Node, 0);
4947 const TargetRegisterClass *RC =
4948 TLI.getRegClassFor(Src.getSimpleValueType());
4949 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4951 SPDescriptor.setGuardReg(Reg);
4952 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4954 Src = getValue(I.getArgOperand(0)); // The guard's value.
4957 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4959 int FI = FuncInfo.StaticAllocaMap[Slot];
4960 MFI->setStackProtectorIndex(FI);
4962 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4964 // Store the stack protector onto the stack.
4965 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4966 DAG.getMachineFunction(), FI),
4972 case Intrinsic::objectsize: {
4973 // If we don't know by now, we're never going to know.
4974 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4976 assert(CI && "Non-constant type in __builtin_object_size?");
4978 SDValue Arg = getValue(I.getCalledValue());
4979 EVT Ty = Arg.getValueType();
4982 Res = DAG.getConstant(-1ULL, sdl, Ty);
4984 Res = DAG.getConstant(0, sdl, Ty);
4989 case Intrinsic::annotation:
4990 case Intrinsic::ptr_annotation:
4991 // Drop the intrinsic, but forward the value
4992 setValue(&I, getValue(I.getOperand(0)));
4994 case Intrinsic::assume:
4995 case Intrinsic::var_annotation:
4996 // Discard annotate attributes and assumptions
4999 case Intrinsic::init_trampoline: {
5000 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5004 Ops[1] = getValue(I.getArgOperand(0));
5005 Ops[2] = getValue(I.getArgOperand(1));
5006 Ops[3] = getValue(I.getArgOperand(2));
5007 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5008 Ops[5] = DAG.getSrcValue(F);
5010 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5015 case Intrinsic::adjust_trampoline: {
5016 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5017 TLI.getPointerTy(DAG.getDataLayout()),
5018 getValue(I.getArgOperand(0))));
5021 case Intrinsic::gcroot:
5023 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5024 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5026 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5027 GFI->addStackRoot(FI->getIndex(), TypeMap);
5030 case Intrinsic::gcread:
5031 case Intrinsic::gcwrite:
5032 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5033 case Intrinsic::flt_rounds:
5034 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5037 case Intrinsic::expect: {
5038 // Just replace __builtin_expect(exp, c) with EXP.
5039 setValue(&I, getValue(I.getArgOperand(0)));
5043 case Intrinsic::debugtrap:
5044 case Intrinsic::trap: {
5045 StringRef TrapFuncName =
5047 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5048 .getValueAsString();
5049 if (TrapFuncName.empty()) {
5050 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5051 ISD::TRAP : ISD::DEBUGTRAP;
5052 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5055 TargetLowering::ArgListTy Args;
5057 TargetLowering::CallLoweringInfo CLI(DAG);
5058 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5059 CallingConv::C, I.getType(),
5060 DAG.getExternalSymbol(TrapFuncName.data(),
5061 TLI.getPointerTy(DAG.getDataLayout())),
5062 std::move(Args), 0);
5064 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5065 DAG.setRoot(Result.second);
5069 case Intrinsic::uadd_with_overflow:
5070 case Intrinsic::sadd_with_overflow:
5071 case Intrinsic::usub_with_overflow:
5072 case Intrinsic::ssub_with_overflow:
5073 case Intrinsic::umul_with_overflow:
5074 case Intrinsic::smul_with_overflow: {
5076 switch (Intrinsic) {
5077 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5078 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5079 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5080 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5081 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5082 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5083 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5085 SDValue Op1 = getValue(I.getArgOperand(0));
5086 SDValue Op2 = getValue(I.getArgOperand(1));
5088 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5089 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5092 case Intrinsic::prefetch: {
5094 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5096 Ops[1] = getValue(I.getArgOperand(0));
5097 Ops[2] = getValue(I.getArgOperand(1));
5098 Ops[3] = getValue(I.getArgOperand(2));
5099 Ops[4] = getValue(I.getArgOperand(3));
5100 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5101 DAG.getVTList(MVT::Other), Ops,
5102 EVT::getIntegerVT(*Context, 8),
5103 MachinePointerInfo(I.getArgOperand(0)),
5105 false, /* volatile */
5107 rw==1)); /* write */
5110 case Intrinsic::lifetime_start:
5111 case Intrinsic::lifetime_end: {
5112 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5113 // Stack coloring is not enabled in O0, discard region information.
5114 if (TM.getOptLevel() == CodeGenOpt::None)
5117 SmallVector<Value *, 4> Allocas;
5118 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5120 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5121 E = Allocas.end(); Object != E; ++Object) {
5122 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5124 // Could not find an Alloca.
5125 if (!LifetimeObject)
5128 // First check that the Alloca is static, otherwise it won't have a
5129 // valid frame index.
5130 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5131 if (SI == FuncInfo.StaticAllocaMap.end())
5134 int FI = SI->second;
5139 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5140 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5142 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5147 case Intrinsic::invariant_start:
5148 // Discard region information.
5149 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5151 case Intrinsic::invariant_end:
5152 // Discard region information.
5154 case Intrinsic::stackprotectorcheck: {
5155 // Do not actually emit anything for this basic block. Instead we initialize
5156 // the stack protector descriptor and export the guard variable so we can
5157 // access it in FinishBasicBlock.
5158 const BasicBlock *BB = I.getParent();
5159 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5160 ExportFromCurrentBlock(SPDescriptor.getGuard());
5162 // Flush our exports since we are going to process a terminator.
5163 (void)getControlRoot();
5166 case Intrinsic::clear_cache:
5167 return TLI.getClearCacheBuiltinName();
5168 case Intrinsic::donothing:
5171 case Intrinsic::experimental_stackmap: {
5175 case Intrinsic::experimental_patchpoint_void:
5176 case Intrinsic::experimental_patchpoint_i64: {
5177 visitPatchpoint(&I);
5180 case Intrinsic::experimental_gc_statepoint: {
5184 case Intrinsic::experimental_gc_result_int:
5185 case Intrinsic::experimental_gc_result_float:
5186 case Intrinsic::experimental_gc_result_ptr:
5187 case Intrinsic::experimental_gc_result: {
5191 case Intrinsic::experimental_gc_relocate: {
5195 case Intrinsic::instrprof_increment:
5196 llvm_unreachable("instrprof failed to lower an increment");
5198 case Intrinsic::localescape: {
5199 MachineFunction &MF = DAG.getMachineFunction();
5200 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5202 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5203 // is the same on all targets.
5204 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5205 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5206 if (isa<ConstantPointerNull>(Arg))
5207 continue; // Skip null pointers. They represent a hole in index space.
5208 AllocaInst *Slot = cast<AllocaInst>(Arg);
5209 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5210 "can only escape static allocas");
5211 int FI = FuncInfo.StaticAllocaMap[Slot];
5212 MCSymbol *FrameAllocSym =
5213 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5214 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5215 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5216 TII->get(TargetOpcode::LOCAL_ESCAPE))
5217 .addSym(FrameAllocSym)
5224 case Intrinsic::localrecover: {
5225 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5226 MachineFunction &MF = DAG.getMachineFunction();
5227 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5229 // Get the symbol that defines the frame offset.
5230 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5231 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5232 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5233 MCSymbol *FrameAllocSym =
5234 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5235 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5237 // Create a MCSymbol for the label to avoid any target lowering
5238 // that would make this PC relative.
5239 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5241 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5243 // Add the offset to the FP.
5244 Value *FP = I.getArgOperand(1);
5245 SDValue FPVal = getValue(FP);
5246 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5252 case Intrinsic::eh_exceptionpointer:
5253 case Intrinsic::eh_exceptioncode: {
5254 // Get the exception pointer vreg, copy from it, and resize it to fit.
5255 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5256 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5257 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5258 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5260 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5261 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5268 std::pair<SDValue, SDValue>
5269 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5270 const BasicBlock *EHPadBB) {
5271 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5272 MCSymbol *BeginLabel = nullptr;
5275 // Insert a label before the invoke call to mark the try range. This can be
5276 // used to detect deletion of the invoke via the MachineModuleInfo.
5277 BeginLabel = MMI.getContext().createTempSymbol();
5279 // For SjLj, keep track of which landing pads go with which invokes
5280 // so as to maintain the ordering of pads in the LSDA.
5281 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5282 if (CallSiteIndex) {
5283 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5284 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5286 // Now that the call site is handled, stop tracking it.
5287 MMI.setCurrentCallSite(0);
5290 // Both PendingLoads and PendingExports must be flushed here;
5291 // this call might not return.
5293 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5295 CLI.setChain(getRoot());
5297 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5298 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5300 assert((CLI.IsTailCall || Result.second.getNode()) &&
5301 "Non-null chain expected with non-tail call!");
5302 assert((Result.second.getNode() || !Result.first.getNode()) &&
5303 "Null value expected with tail call!");
5305 if (!Result.second.getNode()) {
5306 // As a special case, a null chain means that a tail call has been emitted
5307 // and the DAG root is already updated.
5310 // Since there's no actual continuation from this block, nothing can be
5311 // relying on us setting vregs for them.
5312 PendingExports.clear();
5314 DAG.setRoot(Result.second);
5318 // Insert a label at the end of the invoke call to mark the try range. This
5319 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5320 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5321 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5323 // Inform MachineModuleInfo of range.
5324 if (MMI.hasEHFunclets()) {
5325 WinEHFuncInfo &EHInfo =
5326 MMI.getWinEHFuncInfo(DAG.getMachineFunction().getFunction());
5327 EHInfo.addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5329 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5336 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5338 const BasicBlock *EHPadBB) {
5339 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5340 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5341 Type *RetTy = FTy->getReturnType();
5343 TargetLowering::ArgListTy Args;
5344 TargetLowering::ArgListEntry Entry;
5345 Args.reserve(CS.arg_size());
5347 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5349 const Value *V = *i;
5352 if (V->getType()->isEmptyTy())
5355 SDValue ArgNode = getValue(V);
5356 Entry.Node = ArgNode; Entry.Ty = V->getType();
5358 // Skip the first return-type Attribute to get to params.
5359 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5360 Args.push_back(Entry);
5362 // If we have an explicit sret argument that is an Instruction, (i.e., it
5363 // might point to function-local memory), we can't meaningfully tail-call.
5364 if (Entry.isSRet && isa<Instruction>(V))
5368 // Check if target-independent constraints permit a tail call here.
5369 // Target-dependent constraints are checked within TLI->LowerCallTo.
5370 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5373 TargetLowering::CallLoweringInfo CLI(DAG);
5374 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5375 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5376 .setTailCall(isTailCall);
5377 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5379 if (Result.first.getNode())
5380 setValue(CS.getInstruction(), Result.first);
5383 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5384 /// value is equal or not-equal to zero.
5385 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5386 for (const User *U : V->users()) {
5387 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5388 if (IC->isEquality())
5389 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5390 if (C->isNullValue())
5392 // Unknown instruction.
5398 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5400 SelectionDAGBuilder &Builder) {
5402 // Check to see if this load can be trivially constant folded, e.g. if the
5403 // input is from a string literal.
5404 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5405 // Cast pointer to the type we really want to load.
5406 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5407 PointerType::getUnqual(LoadTy));
5409 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5410 const_cast<Constant *>(LoadInput), *Builder.DL))
5411 return Builder.getValue(LoadCst);
5414 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5415 // still constant memory, the input chain can be the entry node.
5417 bool ConstantMemory = false;
5419 // Do not serialize (non-volatile) loads of constant memory with anything.
5420 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5421 Root = Builder.DAG.getEntryNode();
5422 ConstantMemory = true;
5424 // Do not serialize non-volatile loads against each other.
5425 Root = Builder.DAG.getRoot();
5428 SDValue Ptr = Builder.getValue(PtrVal);
5429 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5430 Ptr, MachinePointerInfo(PtrVal),
5432 false /*nontemporal*/,
5433 false /*isinvariant*/, 1 /* align=1 */);
5435 if (!ConstantMemory)
5436 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5440 /// processIntegerCallValue - Record the value for an instruction that
5441 /// produces an integer result, converting the type where necessary.
5442 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5445 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5448 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5450 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5451 setValue(&I, Value);
5454 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5455 /// If so, return true and lower it, otherwise return false and it will be
5456 /// lowered like a normal call.
5457 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5458 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5459 if (I.getNumArgOperands() != 3)
5462 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5463 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5464 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5465 !I.getType()->isIntegerTy())
5468 const Value *Size = I.getArgOperand(2);
5469 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5470 if (CSize && CSize->getZExtValue() == 0) {
5471 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5473 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5477 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5478 std::pair<SDValue, SDValue> Res =
5479 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5480 getValue(LHS), getValue(RHS), getValue(Size),
5481 MachinePointerInfo(LHS),
5482 MachinePointerInfo(RHS));
5483 if (Res.first.getNode()) {
5484 processIntegerCallValue(I, Res.first, true);
5485 PendingLoads.push_back(Res.second);
5489 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5490 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5491 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5492 bool ActuallyDoIt = true;
5495 switch (CSize->getZExtValue()) {
5497 LoadVT = MVT::Other;
5499 ActuallyDoIt = false;
5503 LoadTy = Type::getInt16Ty(CSize->getContext());
5507 LoadTy = Type::getInt32Ty(CSize->getContext());
5511 LoadTy = Type::getInt64Ty(CSize->getContext());
5515 LoadVT = MVT::v4i32;
5516 LoadTy = Type::getInt32Ty(CSize->getContext());
5517 LoadTy = VectorType::get(LoadTy, 4);
5522 // This turns into unaligned loads. We only do this if the target natively
5523 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5524 // we'll only produce a small number of byte loads.
5526 // Require that we can find a legal MVT, and only do this if the target
5527 // supports unaligned loads of that type. Expanding into byte loads would
5529 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5530 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5531 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5532 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5533 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5534 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5535 // TODO: Check alignment of src and dest ptrs.
5536 if (!TLI.isTypeLegal(LoadVT) ||
5537 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5538 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5539 ActuallyDoIt = false;
5543 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5544 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5546 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5548 processIntegerCallValue(I, Res, false);
5557 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5558 /// form. If so, return true and lower it, otherwise return false and it
5559 /// will be lowered like a normal call.
5560 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5561 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5562 if (I.getNumArgOperands() != 3)
5565 const Value *Src = I.getArgOperand(0);
5566 const Value *Char = I.getArgOperand(1);
5567 const Value *Length = I.getArgOperand(2);
5568 if (!Src->getType()->isPointerTy() ||
5569 !Char->getType()->isIntegerTy() ||
5570 !Length->getType()->isIntegerTy() ||
5571 !I.getType()->isPointerTy())
5574 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5575 std::pair<SDValue, SDValue> Res =
5576 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5577 getValue(Src), getValue(Char), getValue(Length),
5578 MachinePointerInfo(Src));
5579 if (Res.first.getNode()) {
5580 setValue(&I, Res.first);
5581 PendingLoads.push_back(Res.second);
5588 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5589 /// optimized form. If so, return true and lower it, otherwise return false
5590 /// and it will be lowered like a normal call.
5591 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5592 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5593 if (I.getNumArgOperands() != 2)
5596 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5597 if (!Arg0->getType()->isPointerTy() ||
5598 !Arg1->getType()->isPointerTy() ||
5599 !I.getType()->isPointerTy())
5602 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5603 std::pair<SDValue, SDValue> Res =
5604 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5605 getValue(Arg0), getValue(Arg1),
5606 MachinePointerInfo(Arg0),
5607 MachinePointerInfo(Arg1), isStpcpy);
5608 if (Res.first.getNode()) {
5609 setValue(&I, Res.first);
5610 DAG.setRoot(Res.second);
5617 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5618 /// If so, return true and lower it, otherwise return false and it will be
5619 /// lowered like a normal call.
5620 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5621 // Verify that the prototype makes sense. int strcmp(void*,void*)
5622 if (I.getNumArgOperands() != 2)
5625 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5626 if (!Arg0->getType()->isPointerTy() ||
5627 !Arg1->getType()->isPointerTy() ||
5628 !I.getType()->isIntegerTy())
5631 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5632 std::pair<SDValue, SDValue> Res =
5633 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5634 getValue(Arg0), getValue(Arg1),
5635 MachinePointerInfo(Arg0),
5636 MachinePointerInfo(Arg1));
5637 if (Res.first.getNode()) {
5638 processIntegerCallValue(I, Res.first, true);
5639 PendingLoads.push_back(Res.second);
5646 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5647 /// form. If so, return true and lower it, otherwise return false and it
5648 /// will be lowered like a normal call.
5649 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5650 // Verify that the prototype makes sense. size_t strlen(char *)
5651 if (I.getNumArgOperands() != 1)
5654 const Value *Arg0 = I.getArgOperand(0);
5655 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5658 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5659 std::pair<SDValue, SDValue> Res =
5660 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5661 getValue(Arg0), MachinePointerInfo(Arg0));
5662 if (Res.first.getNode()) {
5663 processIntegerCallValue(I, Res.first, false);
5664 PendingLoads.push_back(Res.second);
5671 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5672 /// form. If so, return true and lower it, otherwise return false and it
5673 /// will be lowered like a normal call.
5674 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5675 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5676 if (I.getNumArgOperands() != 2)
5679 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5680 if (!Arg0->getType()->isPointerTy() ||
5681 !Arg1->getType()->isIntegerTy() ||
5682 !I.getType()->isIntegerTy())
5685 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5686 std::pair<SDValue, SDValue> Res =
5687 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5688 getValue(Arg0), getValue(Arg1),
5689 MachinePointerInfo(Arg0));
5690 if (Res.first.getNode()) {
5691 processIntegerCallValue(I, Res.first, false);
5692 PendingLoads.push_back(Res.second);
5699 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5700 /// operation (as expected), translate it to an SDNode with the specified opcode
5701 /// and return true.
5702 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5704 // Sanity check that it really is a unary floating-point call.
5705 if (I.getNumArgOperands() != 1 ||
5706 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5707 I.getType() != I.getArgOperand(0)->getType() ||
5708 !I.onlyReadsMemory())
5711 SDValue Tmp = getValue(I.getArgOperand(0));
5712 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5716 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5717 /// operation (as expected), translate it to an SDNode with the specified opcode
5718 /// and return true.
5719 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5721 // Sanity check that it really is a binary floating-point call.
5722 if (I.getNumArgOperands() != 2 ||
5723 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5724 I.getType() != I.getArgOperand(0)->getType() ||
5725 I.getType() != I.getArgOperand(1)->getType() ||
5726 !I.onlyReadsMemory())
5729 SDValue Tmp0 = getValue(I.getArgOperand(0));
5730 SDValue Tmp1 = getValue(I.getArgOperand(1));
5731 EVT VT = Tmp0.getValueType();
5732 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5736 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5737 // Handle inline assembly differently.
5738 if (isa<InlineAsm>(I.getCalledValue())) {
5743 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5744 ComputeUsesVAFloatArgument(I, &MMI);
5746 const char *RenameFn = nullptr;
5747 if (Function *F = I.getCalledFunction()) {
5748 if (F->isDeclaration()) {
5749 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5750 if (unsigned IID = II->getIntrinsicID(F)) {
5751 RenameFn = visitIntrinsicCall(I, IID);
5756 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5757 RenameFn = visitIntrinsicCall(I, IID);
5763 // Check for well-known libc/libm calls. If the function is internal, it
5764 // can't be a library call.
5766 if (!F->hasLocalLinkage() && F->hasName() &&
5767 LibInfo->getLibFunc(F->getName(), Func) &&
5768 LibInfo->hasOptimizedCodeGen(Func)) {
5771 case LibFunc::copysign:
5772 case LibFunc::copysignf:
5773 case LibFunc::copysignl:
5774 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5775 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5776 I.getType() == I.getArgOperand(0)->getType() &&
5777 I.getType() == I.getArgOperand(1)->getType() &&
5778 I.onlyReadsMemory()) {
5779 SDValue LHS = getValue(I.getArgOperand(0));
5780 SDValue RHS = getValue(I.getArgOperand(1));
5781 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5782 LHS.getValueType(), LHS, RHS));
5787 case LibFunc::fabsf:
5788 case LibFunc::fabsl:
5789 if (visitUnaryFloatCall(I, ISD::FABS))
5793 case LibFunc::fminf:
5794 case LibFunc::fminl:
5795 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5799 case LibFunc::fmaxf:
5800 case LibFunc::fmaxl:
5801 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5807 if (visitUnaryFloatCall(I, ISD::FSIN))
5813 if (visitUnaryFloatCall(I, ISD::FCOS))
5817 case LibFunc::sqrtf:
5818 case LibFunc::sqrtl:
5819 case LibFunc::sqrt_finite:
5820 case LibFunc::sqrtf_finite:
5821 case LibFunc::sqrtl_finite:
5822 if (visitUnaryFloatCall(I, ISD::FSQRT))
5825 case LibFunc::floor:
5826 case LibFunc::floorf:
5827 case LibFunc::floorl:
5828 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5831 case LibFunc::nearbyint:
5832 case LibFunc::nearbyintf:
5833 case LibFunc::nearbyintl:
5834 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5838 case LibFunc::ceilf:
5839 case LibFunc::ceill:
5840 if (visitUnaryFloatCall(I, ISD::FCEIL))
5844 case LibFunc::rintf:
5845 case LibFunc::rintl:
5846 if (visitUnaryFloatCall(I, ISD::FRINT))
5849 case LibFunc::round:
5850 case LibFunc::roundf:
5851 case LibFunc::roundl:
5852 if (visitUnaryFloatCall(I, ISD::FROUND))
5855 case LibFunc::trunc:
5856 case LibFunc::truncf:
5857 case LibFunc::truncl:
5858 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5862 case LibFunc::log2f:
5863 case LibFunc::log2l:
5864 if (visitUnaryFloatCall(I, ISD::FLOG2))
5868 case LibFunc::exp2f:
5869 case LibFunc::exp2l:
5870 if (visitUnaryFloatCall(I, ISD::FEXP2))
5873 case LibFunc::memcmp:
5874 if (visitMemCmpCall(I))
5877 case LibFunc::memchr:
5878 if (visitMemChrCall(I))
5881 case LibFunc::strcpy:
5882 if (visitStrCpyCall(I, false))
5885 case LibFunc::stpcpy:
5886 if (visitStrCpyCall(I, true))
5889 case LibFunc::strcmp:
5890 if (visitStrCmpCall(I))
5893 case LibFunc::strlen:
5894 if (visitStrLenCall(I))
5897 case LibFunc::strnlen:
5898 if (visitStrNLenCall(I))
5907 Callee = getValue(I.getCalledValue());
5909 Callee = DAG.getExternalSymbol(
5911 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5913 // Check if we can potentially perform a tail call. More detailed checking is
5914 // be done within LowerCallTo, after more information about the call is known.
5915 LowerCallTo(&I, Callee, I.isTailCall());
5920 /// AsmOperandInfo - This contains information for each constraint that we are
5922 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5924 /// CallOperand - If this is the result output operand or a clobber
5925 /// this is null, otherwise it is the incoming operand to the CallInst.
5926 /// This gets modified as the asm is processed.
5927 SDValue CallOperand;
5929 /// AssignedRegs - If this is a register or register class operand, this
5930 /// contains the set of register corresponding to the operand.
5931 RegsForValue AssignedRegs;
5933 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5934 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5937 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5938 /// corresponds to. If there is no Value* for this operand, it returns
5940 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5941 const DataLayout &DL) const {
5942 if (!CallOperandVal) return MVT::Other;
5944 if (isa<BasicBlock>(CallOperandVal))
5945 return TLI.getPointerTy(DL);
5947 llvm::Type *OpTy = CallOperandVal->getType();
5949 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5950 // If this is an indirect operand, the operand is a pointer to the
5953 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5955 report_fatal_error("Indirect operand for inline asm not a pointer!");
5956 OpTy = PtrTy->getElementType();
5959 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5960 if (StructType *STy = dyn_cast<StructType>(OpTy))
5961 if (STy->getNumElements() == 1)
5962 OpTy = STy->getElementType(0);
5964 // If OpTy is not a single value, it may be a struct/union that we
5965 // can tile with integers.
5966 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5967 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5976 OpTy = IntegerType::get(Context, BitSize);
5981 return TLI.getValueType(DL, OpTy, true);
5985 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5987 } // end anonymous namespace
5989 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5990 /// specified operand. We prefer to assign virtual registers, to allow the
5991 /// register allocator to handle the assignment process. However, if the asm
5992 /// uses features that we can't model on machineinstrs, we have SDISel do the
5993 /// allocation. This produces generally horrible, but correct, code.
5995 /// OpInfo describes the operand.
5997 static void GetRegistersForValue(SelectionDAG &DAG,
5998 const TargetLowering &TLI,
6000 SDISelAsmOperandInfo &OpInfo) {
6001 LLVMContext &Context = *DAG.getContext();
6003 MachineFunction &MF = DAG.getMachineFunction();
6004 SmallVector<unsigned, 4> Regs;
6006 // If this is a constraint for a single physreg, or a constraint for a
6007 // register class, find it.
6008 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6009 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6010 OpInfo.ConstraintCode,
6011 OpInfo.ConstraintVT);
6013 unsigned NumRegs = 1;
6014 if (OpInfo.ConstraintVT != MVT::Other) {
6015 // If this is a FP input in an integer register (or visa versa) insert a bit
6016 // cast of the input value. More generally, handle any case where the input
6017 // value disagrees with the register class we plan to stick this in.
6018 if (OpInfo.Type == InlineAsm::isInput &&
6019 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6020 // Try to convert to the first EVT that the reg class contains. If the
6021 // types are identical size, use a bitcast to convert (e.g. two differing
6023 MVT RegVT = *PhysReg.second->vt_begin();
6024 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6025 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6026 RegVT, OpInfo.CallOperand);
6027 OpInfo.ConstraintVT = RegVT;
6028 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6029 // If the input is a FP value and we want it in FP registers, do a
6030 // bitcast to the corresponding integer type. This turns an f64 value
6031 // into i64, which can be passed with two i32 values on a 32-bit
6033 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6034 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6035 RegVT, OpInfo.CallOperand);
6036 OpInfo.ConstraintVT = RegVT;
6040 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6044 EVT ValueVT = OpInfo.ConstraintVT;
6046 // If this is a constraint for a specific physical register, like {r17},
6048 if (unsigned AssignedReg = PhysReg.first) {
6049 const TargetRegisterClass *RC = PhysReg.second;
6050 if (OpInfo.ConstraintVT == MVT::Other)
6051 ValueVT = *RC->vt_begin();
6053 // Get the actual register value type. This is important, because the user
6054 // may have asked for (e.g.) the AX register in i32 type. We need to
6055 // remember that AX is actually i16 to get the right extension.
6056 RegVT = *RC->vt_begin();
6058 // This is a explicit reference to a physical register.
6059 Regs.push_back(AssignedReg);
6061 // If this is an expanded reference, add the rest of the regs to Regs.
6063 TargetRegisterClass::iterator I = RC->begin();
6064 for (; *I != AssignedReg; ++I)
6065 assert(I != RC->end() && "Didn't find reg!");
6067 // Already added the first reg.
6069 for (; NumRegs; --NumRegs, ++I) {
6070 assert(I != RC->end() && "Ran out of registers to allocate!");
6075 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6079 // Otherwise, if this was a reference to an LLVM register class, create vregs
6080 // for this reference.
6081 if (const TargetRegisterClass *RC = PhysReg.second) {
6082 RegVT = *RC->vt_begin();
6083 if (OpInfo.ConstraintVT == MVT::Other)
6086 // Create the appropriate number of virtual registers.
6087 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6088 for (; NumRegs; --NumRegs)
6089 Regs.push_back(RegInfo.createVirtualRegister(RC));
6091 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6095 // Otherwise, we couldn't allocate enough registers for this.
6098 /// visitInlineAsm - Handle a call to an InlineAsm object.
6100 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6101 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6103 /// ConstraintOperands - Information about all of the constraints.
6104 SDISelAsmOperandInfoVector ConstraintOperands;
6106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6107 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6108 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6110 bool hasMemory = false;
6112 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6113 unsigned ResNo = 0; // ResNo - The result number of the next output.
6114 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6115 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6116 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6118 MVT OpVT = MVT::Other;
6120 // Compute the value type for each operand.
6121 switch (OpInfo.Type) {
6122 case InlineAsm::isOutput:
6123 // Indirect outputs just consume an argument.
6124 if (OpInfo.isIndirect) {
6125 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6129 // The return value of the call is this value. As such, there is no
6130 // corresponding argument.
6131 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6132 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6133 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6134 STy->getElementType(ResNo));
6136 assert(ResNo == 0 && "Asm only has one result!");
6137 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6141 case InlineAsm::isInput:
6142 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6144 case InlineAsm::isClobber:
6149 // If this is an input or an indirect output, process the call argument.
6150 // BasicBlocks are labels, currently appearing only in asm's.
6151 if (OpInfo.CallOperandVal) {
6152 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6153 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6155 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6158 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6159 DAG.getDataLayout()).getSimpleVT();
6162 OpInfo.ConstraintVT = OpVT;
6164 // Indirect operand accesses access memory.
6165 if (OpInfo.isIndirect)
6168 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6169 TargetLowering::ConstraintType
6170 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6171 if (CType == TargetLowering::C_Memory) {
6179 SDValue Chain, Flag;
6181 // We won't need to flush pending loads if this asm doesn't touch
6182 // memory and is nonvolatile.
6183 if (hasMemory || IA->hasSideEffects())
6186 Chain = DAG.getRoot();
6188 // Second pass over the constraints: compute which constraint option to use
6189 // and assign registers to constraints that want a specific physreg.
6190 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6191 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6193 // If this is an output operand with a matching input operand, look up the
6194 // matching input. If their types mismatch, e.g. one is an integer, the
6195 // other is floating point, or their sizes are different, flag it as an
6197 if (OpInfo.hasMatchingInput()) {
6198 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6200 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6201 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6202 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6203 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6204 OpInfo.ConstraintVT);
6205 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6206 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6207 Input.ConstraintVT);
6208 if ((OpInfo.ConstraintVT.isInteger() !=
6209 Input.ConstraintVT.isInteger()) ||
6210 (MatchRC.second != InputRC.second)) {
6211 report_fatal_error("Unsupported asm: input constraint"
6212 " with a matching output constraint of"
6213 " incompatible type!");
6215 Input.ConstraintVT = OpInfo.ConstraintVT;
6219 // Compute the constraint code and ConstraintType to use.
6220 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6222 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6223 OpInfo.Type == InlineAsm::isClobber)
6226 // If this is a memory input, and if the operand is not indirect, do what we
6227 // need to to provide an address for the memory input.
6228 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6229 !OpInfo.isIndirect) {
6230 assert((OpInfo.isMultipleAlternative ||
6231 (OpInfo.Type == InlineAsm::isInput)) &&
6232 "Can only indirectify direct input operands!");
6234 // Memory operands really want the address of the value. If we don't have
6235 // an indirect input, put it in the constpool if we can, otherwise spill
6236 // it to a stack slot.
6237 // TODO: This isn't quite right. We need to handle these according to
6238 // the addressing mode that the constraint wants. Also, this may take
6239 // an additional register for the computation and we don't want that
6242 // If the operand is a float, integer, or vector constant, spill to a
6243 // constant pool entry to get its address.
6244 const Value *OpVal = OpInfo.CallOperandVal;
6245 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6246 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6247 OpInfo.CallOperand = DAG.getConstantPool(
6248 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6250 // Otherwise, create a stack slot and emit a store to it before the
6252 Type *Ty = OpVal->getType();
6253 auto &DL = DAG.getDataLayout();
6254 uint64_t TySize = DL.getTypeAllocSize(Ty);
6255 unsigned Align = DL.getPrefTypeAlignment(Ty);
6256 MachineFunction &MF = DAG.getMachineFunction();
6257 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6259 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6260 Chain = DAG.getStore(
6261 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6262 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6264 OpInfo.CallOperand = StackSlot;
6267 // There is no longer a Value* corresponding to this operand.
6268 OpInfo.CallOperandVal = nullptr;
6270 // It is now an indirect operand.
6271 OpInfo.isIndirect = true;
6274 // If this constraint is for a specific register, allocate it before
6276 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6277 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6280 // Second pass - Loop over all of the operands, assigning virtual or physregs
6281 // to register class operands.
6282 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6283 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6285 // C_Register operands have already been allocated, Other/Memory don't need
6287 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6288 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6291 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6292 std::vector<SDValue> AsmNodeOperands;
6293 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6294 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6295 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6297 // If we have a !srcloc metadata node associated with it, we want to attach
6298 // this to the ultimately generated inline asm machineinstr. To do this, we
6299 // pass in the third operand as this (potentially null) inline asm MDNode.
6300 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6301 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6303 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6304 // bits as operand 3.
6305 unsigned ExtraInfo = 0;
6306 if (IA->hasSideEffects())
6307 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6308 if (IA->isAlignStack())
6309 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6310 // Set the asm dialect.
6311 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6313 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6314 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6315 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6317 // Compute the constraint code and ConstraintType to use.
6318 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6320 // Ideally, we would only check against memory constraints. However, the
6321 // meaning of an other constraint can be target-specific and we can't easily
6322 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6323 // for other constriants as well.
6324 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6325 OpInfo.ConstraintType == TargetLowering::C_Other) {
6326 if (OpInfo.Type == InlineAsm::isInput)
6327 ExtraInfo |= InlineAsm::Extra_MayLoad;
6328 else if (OpInfo.Type == InlineAsm::isOutput)
6329 ExtraInfo |= InlineAsm::Extra_MayStore;
6330 else if (OpInfo.Type == InlineAsm::isClobber)
6331 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6335 AsmNodeOperands.push_back(DAG.getTargetConstant(
6336 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6338 // Loop over all of the inputs, copying the operand values into the
6339 // appropriate registers and processing the output regs.
6340 RegsForValue RetValRegs;
6342 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6343 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6345 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6346 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6348 switch (OpInfo.Type) {
6349 case InlineAsm::isOutput: {
6350 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6351 OpInfo.ConstraintType != TargetLowering::C_Register) {
6352 // Memory output, or 'other' output (e.g. 'X' constraint).
6353 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6355 unsigned ConstraintID =
6356 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6357 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6358 "Failed to convert memory constraint code to constraint id.");
6360 // Add information to the INLINEASM node to know about this output.
6361 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6362 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6363 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6365 AsmNodeOperands.push_back(OpInfo.CallOperand);
6369 // Otherwise, this is a register or register class output.
6371 // Copy the output from the appropriate register. Find a register that
6373 if (OpInfo.AssignedRegs.Regs.empty()) {
6374 LLVMContext &Ctx = *DAG.getContext();
6375 Ctx.emitError(CS.getInstruction(),
6376 "couldn't allocate output register for constraint '" +
6377 Twine(OpInfo.ConstraintCode) + "'");
6381 // If this is an indirect operand, store through the pointer after the
6383 if (OpInfo.isIndirect) {
6384 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6385 OpInfo.CallOperandVal));
6387 // This is the result value of the call.
6388 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6389 // Concatenate this output onto the outputs list.
6390 RetValRegs.append(OpInfo.AssignedRegs);
6393 // Add information to the INLINEASM node to know that this register is
6396 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6397 ? InlineAsm::Kind_RegDefEarlyClobber
6398 : InlineAsm::Kind_RegDef,
6399 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6402 case InlineAsm::isInput: {
6403 SDValue InOperandVal = OpInfo.CallOperand;
6405 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6406 // If this is required to match an output register we have already set,
6407 // just use its register.
6408 unsigned OperandNo = OpInfo.getMatchedOperand();
6410 // Scan until we find the definition we already emitted of this operand.
6411 // When we find it, create a RegsForValue operand.
6412 unsigned CurOp = InlineAsm::Op_FirstOperand;
6413 for (; OperandNo; --OperandNo) {
6414 // Advance to the next operand.
6416 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6417 assert((InlineAsm::isRegDefKind(OpFlag) ||
6418 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6419 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6420 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6424 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6425 if (InlineAsm::isRegDefKind(OpFlag) ||
6426 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6427 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6428 if (OpInfo.isIndirect) {
6429 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6430 LLVMContext &Ctx = *DAG.getContext();
6431 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6432 " don't know how to handle tied "
6433 "indirect register inputs");
6437 RegsForValue MatchedRegs;
6438 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6439 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6440 MatchedRegs.RegVTs.push_back(RegVT);
6441 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6442 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6444 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6445 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6447 LLVMContext &Ctx = *DAG.getContext();
6448 Ctx.emitError(CS.getInstruction(),
6449 "inline asm error: This value"
6450 " type register class is not natively supported!");
6454 SDLoc dl = getCurSDLoc();
6455 // Use the produced MatchedRegs object to
6456 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6457 Chain, &Flag, CS.getInstruction());
6458 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6459 true, OpInfo.getMatchedOperand(), dl,
6460 DAG, AsmNodeOperands);
6464 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6465 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6466 "Unexpected number of operands");
6467 // Add information to the INLINEASM node to know about this input.
6468 // See InlineAsm.h isUseOperandTiedToDef.
6469 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6470 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6471 OpInfo.getMatchedOperand());
6472 AsmNodeOperands.push_back(DAG.getTargetConstant(
6473 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6474 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6478 // Treat indirect 'X' constraint as memory.
6479 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6481 OpInfo.ConstraintType = TargetLowering::C_Memory;
6483 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6484 std::vector<SDValue> Ops;
6485 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6488 LLVMContext &Ctx = *DAG.getContext();
6489 Ctx.emitError(CS.getInstruction(),
6490 "invalid operand for inline asm constraint '" +
6491 Twine(OpInfo.ConstraintCode) + "'");
6495 // Add information to the INLINEASM node to know about this input.
6496 unsigned ResOpType =
6497 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6498 AsmNodeOperands.push_back(DAG.getTargetConstant(
6499 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6500 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6504 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6505 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6506 assert(InOperandVal.getValueType() ==
6507 TLI.getPointerTy(DAG.getDataLayout()) &&
6508 "Memory operands expect pointer values");
6510 unsigned ConstraintID =
6511 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6512 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6513 "Failed to convert memory constraint code to constraint id.");
6515 // Add information to the INLINEASM node to know about this input.
6516 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6517 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6518 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6521 AsmNodeOperands.push_back(InOperandVal);
6525 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6526 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6527 "Unknown constraint type!");
6529 // TODO: Support this.
6530 if (OpInfo.isIndirect) {
6531 LLVMContext &Ctx = *DAG.getContext();
6532 Ctx.emitError(CS.getInstruction(),
6533 "Don't know how to handle indirect register inputs yet "
6534 "for constraint '" +
6535 Twine(OpInfo.ConstraintCode) + "'");
6539 // Copy the input into the appropriate registers.
6540 if (OpInfo.AssignedRegs.Regs.empty()) {
6541 LLVMContext &Ctx = *DAG.getContext();
6542 Ctx.emitError(CS.getInstruction(),
6543 "couldn't allocate input reg for constraint '" +
6544 Twine(OpInfo.ConstraintCode) + "'");
6548 SDLoc dl = getCurSDLoc();
6550 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6551 Chain, &Flag, CS.getInstruction());
6553 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6554 dl, DAG, AsmNodeOperands);
6557 case InlineAsm::isClobber: {
6558 // Add the clobbered value to the operand list, so that the register
6559 // allocator is aware that the physreg got clobbered.
6560 if (!OpInfo.AssignedRegs.Regs.empty())
6561 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6562 false, 0, getCurSDLoc(), DAG,
6569 // Finish up input operands. Set the input chain and add the flag last.
6570 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6571 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6573 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6574 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6575 Flag = Chain.getValue(1);
6577 // If this asm returns a register value, copy the result from that register
6578 // and set it as the value of the call.
6579 if (!RetValRegs.Regs.empty()) {
6580 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6581 Chain, &Flag, CS.getInstruction());
6583 // FIXME: Why don't we do this for inline asms with MRVs?
6584 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6585 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6587 // If any of the results of the inline asm is a vector, it may have the
6588 // wrong width/num elts. This can happen for register classes that can
6589 // contain multiple different value types. The preg or vreg allocated may
6590 // not have the same VT as was expected. Convert it to the right type
6591 // with bit_convert.
6592 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6593 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6596 } else if (ResultType != Val.getValueType() &&
6597 ResultType.isInteger() && Val.getValueType().isInteger()) {
6598 // If a result value was tied to an input value, the computed result may
6599 // have a wider width than the expected result. Extract the relevant
6601 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6604 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6607 setValue(CS.getInstruction(), Val);
6608 // Don't need to use this as a chain in this case.
6609 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6613 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6615 // Process indirect outputs, first output all of the flagged copies out of
6617 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6618 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6619 const Value *Ptr = IndirectStoresToEmit[i].second;
6620 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6622 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6625 // Emit the non-flagged stores from the physregs.
6626 SmallVector<SDValue, 8> OutChains;
6627 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6628 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6629 StoresToEmit[i].first,
6630 getValue(StoresToEmit[i].second),
6631 MachinePointerInfo(StoresToEmit[i].second),
6633 OutChains.push_back(Val);
6636 if (!OutChains.empty())
6637 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6642 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6643 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6644 MVT::Other, getRoot(),
6645 getValue(I.getArgOperand(0)),
6646 DAG.getSrcValue(I.getArgOperand(0))));
6649 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6650 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6651 const DataLayout &DL = DAG.getDataLayout();
6652 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6653 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6654 DAG.getSrcValue(I.getOperand(0)),
6655 DL.getABITypeAlignment(I.getType()));
6657 DAG.setRoot(V.getValue(1));
6660 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6661 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6662 MVT::Other, getRoot(),
6663 getValue(I.getArgOperand(0)),
6664 DAG.getSrcValue(I.getArgOperand(0))));
6667 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6668 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6669 MVT::Other, getRoot(),
6670 getValue(I.getArgOperand(0)),
6671 getValue(I.getArgOperand(1)),
6672 DAG.getSrcValue(I.getArgOperand(0)),
6673 DAG.getSrcValue(I.getArgOperand(1))));
6676 /// \brief Lower an argument list according to the target calling convention.
6678 /// \return A tuple of <return-value, token-chain>
6680 /// This is a helper for lowering intrinsics that follow a target calling
6681 /// convention or require stack pointer adjustment. Only a subset of the
6682 /// intrinsic's operands need to participate in the calling convention.
6683 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6684 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6685 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6686 TargetLowering::ArgListTy Args;
6687 Args.reserve(NumArgs);
6689 // Populate the argument list.
6690 // Attributes for args start at offset 1, after the return attribute.
6691 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6692 ArgI != ArgE; ++ArgI) {
6693 const Value *V = CS->getOperand(ArgI);
6695 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6697 TargetLowering::ArgListEntry Entry;
6698 Entry.Node = getValue(V);
6699 Entry.Ty = V->getType();
6700 Entry.setAttributes(&CS, AttrI);
6701 Args.push_back(Entry);
6704 TargetLowering::CallLoweringInfo CLI(DAG);
6705 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6706 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6707 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6709 return lowerInvokable(CLI, EHPadBB);
6712 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6713 /// or patchpoint target node's operand list.
6715 /// Constants are converted to TargetConstants purely as an optimization to
6716 /// avoid constant materialization and register allocation.
6718 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6719 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6720 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6721 /// address materialization and register allocation, but may also be required
6722 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6723 /// alloca in the entry block, then the runtime may assume that the alloca's
6724 /// StackMap location can be read immediately after compilation and that the
6725 /// location is valid at any point during execution (this is similar to the
6726 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6727 /// only available in a register, then the runtime would need to trap when
6728 /// execution reaches the StackMap in order to read the alloca's location.
6729 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6730 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6731 SelectionDAGBuilder &Builder) {
6732 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6733 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6734 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6736 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6738 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6739 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6740 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6741 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6742 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6744 Ops.push_back(OpVal);
6748 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6749 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6750 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6751 // [live variables...])
6753 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6755 SDValue Chain, InFlag, Callee, NullPtr;
6756 SmallVector<SDValue, 32> Ops;
6758 SDLoc DL = getCurSDLoc();
6759 Callee = getValue(CI.getCalledValue());
6760 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6762 // The stackmap intrinsic only records the live variables (the arguemnts
6763 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6764 // intrinsic, this won't be lowered to a function call. This means we don't
6765 // have to worry about calling conventions and target specific lowering code.
6766 // Instead we perform the call lowering right here.
6768 // chain, flag = CALLSEQ_START(chain, 0)
6769 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6770 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6772 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6773 InFlag = Chain.getValue(1);
6775 // Add the <id> and <numBytes> constants.
6776 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6777 Ops.push_back(DAG.getTargetConstant(
6778 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6779 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6780 Ops.push_back(DAG.getTargetConstant(
6781 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6784 // Push live variables for the stack map.
6785 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6787 // We are not pushing any register mask info here on the operands list,
6788 // because the stackmap doesn't clobber anything.
6790 // Push the chain and the glue flag.
6791 Ops.push_back(Chain);
6792 Ops.push_back(InFlag);
6794 // Create the STACKMAP node.
6795 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6796 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6797 Chain = SDValue(SM, 0);
6798 InFlag = Chain.getValue(1);
6800 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6802 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6804 // Set the root to the target-lowered call chain.
6807 // Inform the Frame Information that we have a stackmap in this function.
6808 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6811 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6812 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6813 const BasicBlock *EHPadBB) {
6814 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6819 // [live variables...])
6821 CallingConv::ID CC = CS.getCallingConv();
6822 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6823 bool HasDef = !CS->getType()->isVoidTy();
6824 SDLoc dl = getCurSDLoc();
6825 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6827 // Handle immediate and symbolic callees.
6828 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6829 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6831 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6832 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6833 SDLoc(SymbolicCallee),
6834 SymbolicCallee->getValueType(0));
6836 // Get the real number of arguments participating in the call <numArgs>
6837 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6838 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6840 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6841 // Intrinsics include all meta-operands up to but not including CC.
6842 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6843 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6844 "Not enough arguments provided to the patchpoint intrinsic");
6846 // For AnyRegCC the arguments are lowered later on manually.
6847 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6849 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6850 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6851 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6853 SDNode *CallEnd = Result.second.getNode();
6854 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6855 CallEnd = CallEnd->getOperand(0).getNode();
6857 /// Get a call instruction from the call sequence chain.
6858 /// Tail calls are not allowed.
6859 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6860 "Expected a callseq node.");
6861 SDNode *Call = CallEnd->getOperand(0).getNode();
6862 bool HasGlue = Call->getGluedNode();
6864 // Replace the target specific call node with the patchable intrinsic.
6865 SmallVector<SDValue, 8> Ops;
6867 // Add the <id> and <numBytes> constants.
6868 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6869 Ops.push_back(DAG.getTargetConstant(
6870 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6871 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6872 Ops.push_back(DAG.getTargetConstant(
6873 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6877 Ops.push_back(Callee);
6879 // Adjust <numArgs> to account for any arguments that have been passed on the
6881 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6882 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6883 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6884 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6886 // Add the calling convention
6887 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6889 // Add the arguments we omitted previously. The register allocator should
6890 // place these in any free register.
6892 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6893 Ops.push_back(getValue(CS.getArgument(i)));
6895 // Push the arguments from the call instruction up to the register mask.
6896 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6897 Ops.append(Call->op_begin() + 2, e);
6899 // Push live variables for the stack map.
6900 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6902 // Push the register mask info.
6904 Ops.push_back(*(Call->op_end()-2));
6906 Ops.push_back(*(Call->op_end()-1));
6908 // Push the chain (this is originally the first operand of the call, but
6909 // becomes now the last or second to last operand).
6910 Ops.push_back(*(Call->op_begin()));
6912 // Push the glue flag (last operand).
6914 Ops.push_back(*(Call->op_end()-1));
6917 if (IsAnyRegCC && HasDef) {
6918 // Create the return types based on the intrinsic definition
6919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6920 SmallVector<EVT, 3> ValueVTs;
6921 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6922 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6924 // There is always a chain and a glue type at the end
6925 ValueVTs.push_back(MVT::Other);
6926 ValueVTs.push_back(MVT::Glue);
6927 NodeTys = DAG.getVTList(ValueVTs);
6929 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6931 // Replace the target specific call node with a PATCHPOINT node.
6932 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6935 // Update the NodeMap.
6938 setValue(CS.getInstruction(), SDValue(MN, 0));
6940 setValue(CS.getInstruction(), Result.first);
6943 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6944 // call sequence. Furthermore the location of the chain and glue can change
6945 // when the AnyReg calling convention is used and the intrinsic returns a
6947 if (IsAnyRegCC && HasDef) {
6948 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6949 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6950 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6952 DAG.ReplaceAllUsesWith(Call, MN);
6953 DAG.DeleteNode(Call);
6955 // Inform the Frame Information that we have a patchpoint in this function.
6956 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6959 /// Returns an AttributeSet representing the attributes applied to the return
6960 /// value of the given call.
6961 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6962 SmallVector<Attribute::AttrKind, 2> Attrs;
6964 Attrs.push_back(Attribute::SExt);
6966 Attrs.push_back(Attribute::ZExt);
6968 Attrs.push_back(Attribute::InReg);
6970 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6974 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6975 /// implementation, which just calls LowerCall.
6976 /// FIXME: When all targets are
6977 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6978 std::pair<SDValue, SDValue>
6979 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6980 // Handle the incoming return values from the call.
6982 Type *OrigRetTy = CLI.RetTy;
6983 SmallVector<EVT, 4> RetTys;
6984 SmallVector<uint64_t, 4> Offsets;
6985 auto &DL = CLI.DAG.getDataLayout();
6986 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
6988 SmallVector<ISD::OutputArg, 4> Outs;
6989 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
6991 bool CanLowerReturn =
6992 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
6993 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
6995 SDValue DemoteStackSlot;
6996 int DemoteStackIdx = -100;
6997 if (!CanLowerReturn) {
6998 // FIXME: equivalent assert?
6999 // assert(!CS.hasInAllocaArgument() &&
7000 // "sret demotion is incompatible with inalloca");
7001 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7002 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7003 MachineFunction &MF = CLI.DAG.getMachineFunction();
7004 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7005 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7007 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7009 Entry.Node = DemoteStackSlot;
7010 Entry.Ty = StackSlotPtrType;
7011 Entry.isSExt = false;
7012 Entry.isZExt = false;
7013 Entry.isInReg = false;
7014 Entry.isSRet = true;
7015 Entry.isNest = false;
7016 Entry.isByVal = false;
7017 Entry.isReturned = false;
7018 Entry.Alignment = Align;
7019 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7020 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7022 // sret demotion isn't compatible with tail-calls, since the sret argument
7023 // points into the callers stack frame.
7024 CLI.IsTailCall = false;
7026 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7028 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7029 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7030 for (unsigned i = 0; i != NumRegs; ++i) {
7031 ISD::InputArg MyFlags;
7032 MyFlags.VT = RegisterVT;
7034 MyFlags.Used = CLI.IsReturnValueUsed;
7036 MyFlags.Flags.setSExt();
7038 MyFlags.Flags.setZExt();
7040 MyFlags.Flags.setInReg();
7041 CLI.Ins.push_back(MyFlags);
7046 // Handle all of the outgoing arguments.
7048 CLI.OutVals.clear();
7049 ArgListTy &Args = CLI.getArgs();
7050 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7051 SmallVector<EVT, 4> ValueVTs;
7052 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7053 Type *FinalType = Args[i].Ty;
7054 if (Args[i].isByVal)
7055 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7056 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7057 FinalType, CLI.CallConv, CLI.IsVarArg);
7058 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7060 EVT VT = ValueVTs[Value];
7061 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7062 SDValue Op = SDValue(Args[i].Node.getNode(),
7063 Args[i].Node.getResNo() + Value);
7064 ISD::ArgFlagsTy Flags;
7065 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7071 if (Args[i].isInReg)
7075 if (Args[i].isByVal)
7077 if (Args[i].isInAlloca) {
7078 Flags.setInAlloca();
7079 // Set the byval flag for CCAssignFn callbacks that don't know about
7080 // inalloca. This way we can know how many bytes we should've allocated
7081 // and how many bytes a callee cleanup function will pop. If we port
7082 // inalloca to more targets, we'll have to add custom inalloca handling
7083 // in the various CC lowering callbacks.
7086 if (Args[i].isByVal || Args[i].isInAlloca) {
7087 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7088 Type *ElementTy = Ty->getElementType();
7089 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7090 // For ByVal, alignment should come from FE. BE will guess if this
7091 // info is not there but there are cases it cannot get right.
7092 unsigned FrameAlign;
7093 if (Args[i].Alignment)
7094 FrameAlign = Args[i].Alignment;
7096 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7097 Flags.setByValAlign(FrameAlign);
7102 Flags.setInConsecutiveRegs();
7103 Flags.setOrigAlign(OriginalAlignment);
7105 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7106 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7107 SmallVector<SDValue, 4> Parts(NumParts);
7108 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7111 ExtendKind = ISD::SIGN_EXTEND;
7112 else if (Args[i].isZExt)
7113 ExtendKind = ISD::ZERO_EXTEND;
7115 // Conservatively only handle 'returned' on non-vectors for now
7116 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7117 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7118 "unexpected use of 'returned'");
7119 // Before passing 'returned' to the target lowering code, ensure that
7120 // either the register MVT and the actual EVT are the same size or that
7121 // the return value and argument are extended in the same way; in these
7122 // cases it's safe to pass the argument register value unchanged as the
7123 // return register value (although it's at the target's option whether
7125 // TODO: allow code generation to take advantage of partially preserved
7126 // registers rather than clobbering the entire register when the
7127 // parameter extension method is not compatible with the return
7129 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7130 (ExtendKind != ISD::ANY_EXTEND &&
7131 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7132 Flags.setReturned();
7135 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7136 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7138 for (unsigned j = 0; j != NumParts; ++j) {
7139 // if it isn't first piece, alignment must be 1
7140 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7141 i < CLI.NumFixedArgs,
7142 i, j*Parts[j].getValueType().getStoreSize());
7143 if (NumParts > 1 && j == 0)
7144 MyFlags.Flags.setSplit();
7146 MyFlags.Flags.setOrigAlign(1);
7148 CLI.Outs.push_back(MyFlags);
7149 CLI.OutVals.push_back(Parts[j]);
7152 if (NeedsRegBlock && Value == NumValues - 1)
7153 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7157 SmallVector<SDValue, 4> InVals;
7158 CLI.Chain = LowerCall(CLI, InVals);
7160 // Verify that the target's LowerCall behaved as expected.
7161 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7162 "LowerCall didn't return a valid chain!");
7163 assert((!CLI.IsTailCall || InVals.empty()) &&
7164 "LowerCall emitted a return value for a tail call!");
7165 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7166 "LowerCall didn't emit the correct number of values!");
7168 // For a tail call, the return value is merely live-out and there aren't
7169 // any nodes in the DAG representing it. Return a special value to
7170 // indicate that a tail call has been emitted and no more Instructions
7171 // should be processed in the current block.
7172 if (CLI.IsTailCall) {
7173 CLI.DAG.setRoot(CLI.Chain);
7174 return std::make_pair(SDValue(), SDValue());
7177 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7178 assert(InVals[i].getNode() &&
7179 "LowerCall emitted a null value!");
7180 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7181 "LowerCall emitted a value with the wrong type!");
7184 SmallVector<SDValue, 4> ReturnValues;
7185 if (!CanLowerReturn) {
7186 // The instruction result is the result of loading from the
7187 // hidden sret parameter.
7188 SmallVector<EVT, 1> PVTs;
7189 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7191 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7192 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7193 EVT PtrVT = PVTs[0];
7195 unsigned NumValues = RetTys.size();
7196 ReturnValues.resize(NumValues);
7197 SmallVector<SDValue, 4> Chains(NumValues);
7199 for (unsigned i = 0; i < NumValues; ++i) {
7200 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7201 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7203 SDValue L = CLI.DAG.getLoad(
7204 RetTys[i], CLI.DL, CLI.Chain, Add,
7205 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7206 DemoteStackIdx, Offsets[i]),
7207 false, false, false, 1);
7208 ReturnValues[i] = L;
7209 Chains[i] = L.getValue(1);
7212 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7214 // Collect the legal value parts into potentially illegal values
7215 // that correspond to the original function's return values.
7216 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7218 AssertOp = ISD::AssertSext;
7219 else if (CLI.RetZExt)
7220 AssertOp = ISD::AssertZext;
7221 unsigned CurReg = 0;
7222 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7224 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7225 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7227 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7228 NumRegs, RegisterVT, VT, nullptr,
7233 // For a function returning void, there is no return value. We can't create
7234 // such a node, so we just return a null return value in that case. In
7235 // that case, nothing will actually look at the value.
7236 if (ReturnValues.empty())
7237 return std::make_pair(SDValue(), CLI.Chain);
7240 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7241 CLI.DAG.getVTList(RetTys), ReturnValues);
7242 return std::make_pair(Res, CLI.Chain);
7245 void TargetLowering::LowerOperationWrapper(SDNode *N,
7246 SmallVectorImpl<SDValue> &Results,
7247 SelectionDAG &DAG) const {
7248 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7250 Results.push_back(Res);
7253 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7254 llvm_unreachable("LowerOperation not implemented for this target!");
7258 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7259 SDValue Op = getNonRegisterValue(V);
7260 assert((Op.getOpcode() != ISD::CopyFromReg ||
7261 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7262 "Copy from a reg to the same reg!");
7263 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7265 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7266 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7268 SDValue Chain = DAG.getEntryNode();
7270 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7271 FuncInfo.PreferredExtendType.end())
7273 : FuncInfo.PreferredExtendType[V];
7274 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7275 PendingExports.push_back(Chain);
7278 #include "llvm/CodeGen/SelectionDAGISel.h"
7280 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7281 /// entry block, return true. This includes arguments used by switches, since
7282 /// the switch may expand into multiple basic blocks.
7283 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7284 // With FastISel active, we may be splitting blocks, so force creation
7285 // of virtual registers for all non-dead arguments.
7287 return A->use_empty();
7289 const BasicBlock &Entry = A->getParent()->front();
7290 for (const User *U : A->users())
7291 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7292 return false; // Use not in entry block.
7297 void SelectionDAGISel::LowerArguments(const Function &F) {
7298 SelectionDAG &DAG = SDB->DAG;
7299 SDLoc dl = SDB->getCurSDLoc();
7300 const DataLayout &DL = DAG.getDataLayout();
7301 SmallVector<ISD::InputArg, 16> Ins;
7303 if (!FuncInfo->CanLowerReturn) {
7304 // Put in an sret pointer parameter before all the other parameters.
7305 SmallVector<EVT, 1> ValueVTs;
7306 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7307 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7309 // NOTE: Assuming that a pointer will never break down to more than one VT
7311 ISD::ArgFlagsTy Flags;
7313 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7314 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7315 ISD::InputArg::NoArgIndex, 0);
7316 Ins.push_back(RetArg);
7319 // Set up the incoming argument description vector.
7321 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7322 I != E; ++I, ++Idx) {
7323 SmallVector<EVT, 4> ValueVTs;
7324 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7325 bool isArgValueUsed = !I->use_empty();
7326 unsigned PartBase = 0;
7327 Type *FinalType = I->getType();
7328 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7329 FinalType = cast<PointerType>(FinalType)->getElementType();
7330 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7331 FinalType, F.getCallingConv(), F.isVarArg());
7332 for (unsigned Value = 0, NumValues = ValueVTs.size();
7333 Value != NumValues; ++Value) {
7334 EVT VT = ValueVTs[Value];
7335 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7336 ISD::ArgFlagsTy Flags;
7337 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7339 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7341 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7343 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7345 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7347 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7349 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7350 Flags.setInAlloca();
7351 // Set the byval flag for CCAssignFn callbacks that don't know about
7352 // inalloca. This way we can know how many bytes we should've allocated
7353 // and how many bytes a callee cleanup function will pop. If we port
7354 // inalloca to more targets, we'll have to add custom inalloca handling
7355 // in the various CC lowering callbacks.
7358 if (Flags.isByVal() || Flags.isInAlloca()) {
7359 PointerType *Ty = cast<PointerType>(I->getType());
7360 Type *ElementTy = Ty->getElementType();
7361 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7362 // For ByVal, alignment should be passed from FE. BE will guess if
7363 // this info is not there but there are cases it cannot get right.
7364 unsigned FrameAlign;
7365 if (F.getParamAlignment(Idx))
7366 FrameAlign = F.getParamAlignment(Idx);
7368 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7369 Flags.setByValAlign(FrameAlign);
7371 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7374 Flags.setInConsecutiveRegs();
7375 Flags.setOrigAlign(OriginalAlignment);
7377 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7378 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7379 for (unsigned i = 0; i != NumRegs; ++i) {
7380 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7381 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7382 if (NumRegs > 1 && i == 0)
7383 MyFlags.Flags.setSplit();
7384 // if it isn't first piece, alignment must be 1
7386 MyFlags.Flags.setOrigAlign(1);
7387 Ins.push_back(MyFlags);
7389 if (NeedsRegBlock && Value == NumValues - 1)
7390 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7391 PartBase += VT.getStoreSize();
7395 // Call the target to set up the argument values.
7396 SmallVector<SDValue, 8> InVals;
7397 SDValue NewRoot = TLI->LowerFormalArguments(
7398 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7400 // Verify that the target's LowerFormalArguments behaved as expected.
7401 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7402 "LowerFormalArguments didn't return a valid chain!");
7403 assert(InVals.size() == Ins.size() &&
7404 "LowerFormalArguments didn't emit the correct number of values!");
7406 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7407 assert(InVals[i].getNode() &&
7408 "LowerFormalArguments emitted a null value!");
7409 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7410 "LowerFormalArguments emitted a value with the wrong type!");
7414 // Update the DAG with the new chain value resulting from argument lowering.
7415 DAG.setRoot(NewRoot);
7417 // Set up the argument values.
7420 if (!FuncInfo->CanLowerReturn) {
7421 // Create a virtual register for the sret pointer, and put in a copy
7422 // from the sret argument into it.
7423 SmallVector<EVT, 1> ValueVTs;
7424 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7425 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7426 MVT VT = ValueVTs[0].getSimpleVT();
7427 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7428 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7429 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7430 RegVT, VT, nullptr, AssertOp);
7432 MachineFunction& MF = SDB->DAG.getMachineFunction();
7433 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7434 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7435 FuncInfo->DemoteRegister = SRetReg;
7437 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7438 DAG.setRoot(NewRoot);
7440 // i indexes lowered arguments. Bump it past the hidden sret argument.
7441 // Idx indexes LLVM arguments. Don't touch it.
7445 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7447 SmallVector<SDValue, 4> ArgValues;
7448 SmallVector<EVT, 4> ValueVTs;
7449 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7450 unsigned NumValues = ValueVTs.size();
7452 // If this argument is unused then remember its value. It is used to generate
7453 // debugging information.
7454 if (I->use_empty() && NumValues) {
7455 SDB->setUnusedArgValue(&*I, InVals[i]);
7457 // Also remember any frame index for use in FastISel.
7458 if (FrameIndexSDNode *FI =
7459 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7460 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7463 for (unsigned Val = 0; Val != NumValues; ++Val) {
7464 EVT VT = ValueVTs[Val];
7465 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7466 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7468 if (!I->use_empty()) {
7469 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7470 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7471 AssertOp = ISD::AssertSext;
7472 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7473 AssertOp = ISD::AssertZext;
7475 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7476 NumParts, PartVT, VT,
7477 nullptr, AssertOp));
7483 // We don't need to do anything else for unused arguments.
7484 if (ArgValues.empty())
7487 // Note down frame index.
7488 if (FrameIndexSDNode *FI =
7489 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7490 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7492 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7493 SDB->getCurSDLoc());
7495 SDB->setValue(&*I, Res);
7496 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7497 if (LoadSDNode *LNode =
7498 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7499 if (FrameIndexSDNode *FI =
7500 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7501 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7504 // If this argument is live outside of the entry block, insert a copy from
7505 // wherever we got it to the vreg that other BB's will reference it as.
7506 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7507 // If we can, though, try to skip creating an unnecessary vreg.
7508 // FIXME: This isn't very clean... it would be nice to make this more
7509 // general. It's also subtly incompatible with the hacks FastISel
7511 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7512 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7513 FuncInfo->ValueMap[&*I] = Reg;
7517 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7518 FuncInfo->InitializeRegForValue(&*I);
7519 SDB->CopyToExportRegsIfNeeded(&*I);
7523 assert(i == InVals.size() && "Argument register count mismatch!");
7525 // Finally, if the target has anything special to do, allow it to do so.
7526 EmitFunctionEntryCode();
7529 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7530 /// ensure constants are generated when needed. Remember the virtual registers
7531 /// that need to be added to the Machine PHI nodes as input. We cannot just
7532 /// directly add them, because expansion might result in multiple MBB's for one
7533 /// BB. As such, the start of the BB might correspond to a different MBB than
7537 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7538 const TerminatorInst *TI = LLVMBB->getTerminator();
7540 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7542 // Check PHI nodes in successors that expect a value to be available from this
7544 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7545 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7546 if (!isa<PHINode>(SuccBB->begin())) continue;
7547 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7549 // If this terminator has multiple identical successors (common for
7550 // switches), only handle each succ once.
7551 if (!SuccsHandled.insert(SuccMBB).second)
7554 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7556 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7557 // nodes and Machine PHI nodes, but the incoming operands have not been
7559 for (BasicBlock::const_iterator I = SuccBB->begin();
7560 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7561 // Ignore dead phi's.
7562 if (PN->use_empty()) continue;
7565 if (PN->getType()->isEmptyTy())
7569 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7571 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7572 unsigned &RegOut = ConstantsOut[C];
7574 RegOut = FuncInfo.CreateRegs(C->getType());
7575 CopyValueToVirtualRegister(C, RegOut);
7579 DenseMap<const Value *, unsigned>::iterator I =
7580 FuncInfo.ValueMap.find(PHIOp);
7581 if (I != FuncInfo.ValueMap.end())
7584 assert(isa<AllocaInst>(PHIOp) &&
7585 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7586 "Didn't codegen value into a register!??");
7587 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7588 CopyValueToVirtualRegister(PHIOp, Reg);
7592 // Remember that this register needs to added to the machine PHI node as
7593 // the input for this MBB.
7594 SmallVector<EVT, 4> ValueVTs;
7595 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7596 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7597 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7598 EVT VT = ValueVTs[vti];
7599 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7600 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7601 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7602 Reg += NumRegisters;
7607 ConstantsOut.clear();
7610 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7613 SelectionDAGBuilder::StackProtectorDescriptor::
7614 AddSuccessorMBB(const BasicBlock *BB,
7615 MachineBasicBlock *ParentMBB,
7617 MachineBasicBlock *SuccMBB) {
7618 // If SuccBB has not been created yet, create it.
7620 MachineFunction *MF = ParentMBB->getParent();
7621 MachineFunction::iterator BBI(ParentMBB);
7622 SuccMBB = MF->CreateMachineBasicBlock(BB);
7623 MF->insert(++BBI, SuccMBB);
7625 // Add it as a successor of ParentMBB.
7626 ParentMBB->addSuccessor(
7627 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7631 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7632 MachineFunction::iterator I(MBB);
7633 if (++I == FuncInfo.MF->end())
7638 /// During lowering new call nodes can be created (such as memset, etc.).
7639 /// Those will become new roots of the current DAG, but complications arise
7640 /// when they are tail calls. In such cases, the call lowering will update
7641 /// the root, but the builder still needs to know that a tail call has been
7642 /// lowered in order to avoid generating an additional return.
7643 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7644 // If the node is null, we do have a tail call.
7645 if (MaybeTC.getNode() != nullptr)
7646 DAG.setRoot(MaybeTC);
7651 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7652 unsigned *TotalCases, unsigned First,
7654 assert(Last >= First);
7655 assert(TotalCases[Last] >= TotalCases[First]);
7657 APInt LowCase = Clusters[First].Low->getValue();
7658 APInt HighCase = Clusters[Last].High->getValue();
7659 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7661 // FIXME: A range of consecutive cases has 100% density, but only requires one
7662 // comparison to lower. We should discriminate against such consecutive ranges
7665 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7666 uint64_t Range = Diff + 1;
7669 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7671 assert(NumCases < UINT64_MAX / 100);
7672 assert(Range >= NumCases);
7674 return NumCases * 100 >= Range * MinJumpTableDensity;
7677 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7678 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7679 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7682 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7683 unsigned First, unsigned Last,
7684 const SwitchInst *SI,
7685 MachineBasicBlock *DefaultMBB,
7686 CaseCluster &JTCluster) {
7687 assert(First <= Last);
7689 uint32_t Weight = 0;
7690 unsigned NumCmps = 0;
7691 std::vector<MachineBasicBlock*> Table;
7692 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7693 for (unsigned I = First; I <= Last; ++I) {
7694 assert(Clusters[I].Kind == CC_Range);
7695 Weight += Clusters[I].Weight;
7696 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7697 APInt Low = Clusters[I].Low->getValue();
7698 APInt High = Clusters[I].High->getValue();
7699 NumCmps += (Low == High) ? 1 : 2;
7701 // Fill the gap between this and the previous cluster.
7702 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7703 assert(PreviousHigh.slt(Low));
7704 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7705 for (uint64_t J = 0; J < Gap; J++)
7706 Table.push_back(DefaultMBB);
7708 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7709 for (uint64_t J = 0; J < ClusterSize; ++J)
7710 Table.push_back(Clusters[I].MBB);
7711 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7714 unsigned NumDests = JTWeights.size();
7715 if (isSuitableForBitTests(NumDests, NumCmps,
7716 Clusters[First].Low->getValue(),
7717 Clusters[Last].High->getValue())) {
7718 // Clusters[First..Last] should be lowered as bit tests instead.
7722 // Create the MBB that will load from and jump through the table.
7723 // Note: We create it here, but it's not inserted into the function yet.
7724 MachineFunction *CurMF = FuncInfo.MF;
7725 MachineBasicBlock *JumpTableMBB =
7726 CurMF->CreateMachineBasicBlock(SI->getParent());
7728 // Add successors. Note: use table order for determinism.
7729 SmallPtrSet<MachineBasicBlock *, 8> Done;
7730 for (MachineBasicBlock *Succ : Table) {
7731 if (Done.count(Succ))
7733 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7737 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7738 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7739 ->createJumpTableIndex(Table);
7741 // Set up the jump table info.
7742 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7743 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7744 Clusters[Last].High->getValue(), SI->getCondition(),
7746 JTCases.emplace_back(std::move(JTH), std::move(JT));
7748 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7749 JTCases.size() - 1, Weight);
7753 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7754 const SwitchInst *SI,
7755 MachineBasicBlock *DefaultMBB) {
7757 // Clusters must be non-empty, sorted, and only contain Range clusters.
7758 assert(!Clusters.empty());
7759 for (CaseCluster &C : Clusters)
7760 assert(C.Kind == CC_Range);
7761 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7762 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7766 if (!areJTsAllowed(TLI))
7769 const int64_t N = Clusters.size();
7770 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7772 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7773 SmallVector<unsigned, 8> TotalCases(N);
7775 for (unsigned i = 0; i < N; ++i) {
7776 APInt Hi = Clusters[i].High->getValue();
7777 APInt Lo = Clusters[i].Low->getValue();
7778 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7780 TotalCases[i] += TotalCases[i - 1];
7783 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7784 // Cheap case: the whole range might be suitable for jump table.
7785 CaseCluster JTCluster;
7786 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7787 Clusters[0] = JTCluster;
7793 // The algorithm below is not suitable for -O0.
7794 if (TM.getOptLevel() == CodeGenOpt::None)
7797 // Split Clusters into minimum number of dense partitions. The algorithm uses
7798 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7799 // for the Case Statement'" (1994), but builds the MinPartitions array in
7800 // reverse order to make it easier to reconstruct the partitions in ascending
7801 // order. In the choice between two optimal partitionings, it picks the one
7802 // which yields more jump tables.
7804 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7805 SmallVector<unsigned, 8> MinPartitions(N);
7806 // LastElement[i] is the last element of the partition starting at i.
7807 SmallVector<unsigned, 8> LastElement(N);
7808 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7809 SmallVector<unsigned, 8> NumTables(N);
7811 // Base case: There is only one way to partition Clusters[N-1].
7812 MinPartitions[N - 1] = 1;
7813 LastElement[N - 1] = N - 1;
7814 assert(MinJumpTableSize > 1);
7815 NumTables[N - 1] = 0;
7817 // Note: loop indexes are signed to avoid underflow.
7818 for (int64_t i = N - 2; i >= 0; i--) {
7819 // Find optimal partitioning of Clusters[i..N-1].
7820 // Baseline: Put Clusters[i] into a partition on its own.
7821 MinPartitions[i] = MinPartitions[i + 1] + 1;
7823 NumTables[i] = NumTables[i + 1];
7825 // Search for a solution that results in fewer partitions.
7826 for (int64_t j = N - 1; j > i; j--) {
7827 // Try building a partition from Clusters[i..j].
7828 if (isDense(Clusters, &TotalCases[0], i, j)) {
7829 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7830 bool IsTable = j - i + 1 >= MinJumpTableSize;
7831 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7833 // If this j leads to fewer partitions, or same number of partitions
7834 // with more lookup tables, it is a better partitioning.
7835 if (NumPartitions < MinPartitions[i] ||
7836 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7837 MinPartitions[i] = NumPartitions;
7839 NumTables[i] = Tables;
7845 // Iterate over the partitions, replacing some with jump tables in-place.
7846 unsigned DstIndex = 0;
7847 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7848 Last = LastElement[First];
7849 assert(Last >= First);
7850 assert(DstIndex <= First);
7851 unsigned NumClusters = Last - First + 1;
7853 CaseCluster JTCluster;
7854 if (NumClusters >= MinJumpTableSize &&
7855 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7856 Clusters[DstIndex++] = JTCluster;
7858 for (unsigned I = First; I <= Last; ++I)
7859 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7862 Clusters.resize(DstIndex);
7865 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7866 // FIXME: Using the pointer type doesn't seem ideal.
7867 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7868 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7872 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7875 const APInt &High) {
7876 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7877 // range of cases both require only one branch to lower. Just looking at the
7878 // number of clusters and destinations should be enough to decide whether to
7881 // To lower a range with bit tests, the range must fit the bitwidth of a
7883 if (!rangeFitsInWord(Low, High))
7886 // Decide whether it's profitable to lower this range with bit tests. Each
7887 // destination requires a bit test and branch, and there is an overall range
7888 // check branch. For a small number of clusters, separate comparisons might be
7889 // cheaper, and for many destinations, splitting the range might be better.
7890 return (NumDests == 1 && NumCmps >= 3) ||
7891 (NumDests == 2 && NumCmps >= 5) ||
7892 (NumDests == 3 && NumCmps >= 6);
7895 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7896 unsigned First, unsigned Last,
7897 const SwitchInst *SI,
7898 CaseCluster &BTCluster) {
7899 assert(First <= Last);
7903 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7904 unsigned NumCmps = 0;
7905 for (int64_t I = First; I <= Last; ++I) {
7906 assert(Clusters[I].Kind == CC_Range);
7907 Dests.set(Clusters[I].MBB->getNumber());
7908 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7910 unsigned NumDests = Dests.count();
7912 APInt Low = Clusters[First].Low->getValue();
7913 APInt High = Clusters[Last].High->getValue();
7914 assert(Low.slt(High));
7916 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7922 const int BitWidth = DAG.getTargetLoweringInfo()
7923 .getPointerTy(DAG.getDataLayout())
7925 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7927 // Check if the clusters cover a contiguous range such that no value in the
7928 // range will jump to the default statement.
7929 bool ContiguousRange = true;
7930 for (int64_t I = First + 1; I <= Last; ++I) {
7931 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7932 ContiguousRange = false;
7937 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7938 // Optimize the case where all the case values fit in a word without having
7939 // to subtract minValue. In this case, we can optimize away the subtraction.
7940 LowBound = APInt::getNullValue(Low.getBitWidth());
7942 ContiguousRange = false;
7945 CmpRange = High - Low;
7949 uint32_t TotalWeight = 0;
7950 for (unsigned i = First; i <= Last; ++i) {
7951 // Find the CaseBits for this destination.
7953 for (j = 0; j < CBV.size(); ++j)
7954 if (CBV[j].BB == Clusters[i].MBB)
7956 if (j == CBV.size())
7957 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7958 CaseBits *CB = &CBV[j];
7960 // Update Mask, Bits and ExtraWeight.
7961 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7962 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7963 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7964 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7965 CB->Bits += Hi - Lo + 1;
7966 CB->ExtraWeight += Clusters[i].Weight;
7967 TotalWeight += Clusters[i].Weight;
7968 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7972 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7973 // Sort by weight first, number of bits second.
7974 if (a.ExtraWeight != b.ExtraWeight)
7975 return a.ExtraWeight > b.ExtraWeight;
7976 return a.Bits > b.Bits;
7979 for (auto &CB : CBV) {
7980 MachineBasicBlock *BitTestBB =
7981 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7982 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
7984 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
7985 SI->getCondition(), -1U, MVT::Other, false,
7986 ContiguousRange, nullptr, nullptr, std::move(BTI),
7989 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
7990 BitTestCases.size() - 1, TotalWeight);
7994 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
7995 const SwitchInst *SI) {
7996 // Partition Clusters into as few subsets as possible, where each subset has a
7997 // range that fits in a machine word and has <= 3 unique destinations.
8000 // Clusters must be sorted and contain Range or JumpTable clusters.
8001 assert(!Clusters.empty());
8002 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8003 for (const CaseCluster &C : Clusters)
8004 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8005 for (unsigned i = 1; i < Clusters.size(); ++i)
8006 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8009 // The algorithm below is not suitable for -O0.
8010 if (TM.getOptLevel() == CodeGenOpt::None)
8013 // If target does not have legal shift left, do not emit bit tests at all.
8014 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8015 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8016 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8019 int BitWidth = PTy.getSizeInBits();
8020 const int64_t N = Clusters.size();
8022 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8023 SmallVector<unsigned, 8> MinPartitions(N);
8024 // LastElement[i] is the last element of the partition starting at i.
8025 SmallVector<unsigned, 8> LastElement(N);
8027 // FIXME: This might not be the best algorithm for finding bit test clusters.
8029 // Base case: There is only one way to partition Clusters[N-1].
8030 MinPartitions[N - 1] = 1;
8031 LastElement[N - 1] = N - 1;
8033 // Note: loop indexes are signed to avoid underflow.
8034 for (int64_t i = N - 2; i >= 0; --i) {
8035 // Find optimal partitioning of Clusters[i..N-1].
8036 // Baseline: Put Clusters[i] into a partition on its own.
8037 MinPartitions[i] = MinPartitions[i + 1] + 1;
8040 // Search for a solution that results in fewer partitions.
8041 // Note: the search is limited by BitWidth, reducing time complexity.
8042 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8043 // Try building a partition from Clusters[i..j].
8046 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8047 Clusters[j].High->getValue()))
8050 // Check nbr of destinations and cluster types.
8051 // FIXME: This works, but doesn't seem very efficient.
8052 bool RangesOnly = true;
8053 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8054 for (int64_t k = i; k <= j; k++) {
8055 if (Clusters[k].Kind != CC_Range) {
8059 Dests.set(Clusters[k].MBB->getNumber());
8061 if (!RangesOnly || Dests.count() > 3)
8064 // Check if it's a better partition.
8065 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8066 if (NumPartitions < MinPartitions[i]) {
8067 // Found a better partition.
8068 MinPartitions[i] = NumPartitions;
8074 // Iterate over the partitions, replacing with bit-test clusters in-place.
8075 unsigned DstIndex = 0;
8076 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8077 Last = LastElement[First];
8078 assert(First <= Last);
8079 assert(DstIndex <= First);
8081 CaseCluster BitTestCluster;
8082 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8083 Clusters[DstIndex++] = BitTestCluster;
8085 size_t NumClusters = Last - First + 1;
8086 std::memmove(&Clusters[DstIndex], &Clusters[First],
8087 sizeof(Clusters[0]) * NumClusters);
8088 DstIndex += NumClusters;
8091 Clusters.resize(DstIndex);
8094 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8095 MachineBasicBlock *SwitchMBB,
8096 MachineBasicBlock *DefaultMBB) {
8097 MachineFunction *CurMF = FuncInfo.MF;
8098 MachineBasicBlock *NextMBB = nullptr;
8099 MachineFunction::iterator BBI(W.MBB);
8100 if (++BBI != FuncInfo.MF->end())
8103 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8105 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8107 if (Size == 2 && W.MBB == SwitchMBB) {
8108 // If any two of the cases has the same destination, and if one value
8109 // is the same as the other, but has one bit unset that the other has set,
8110 // use bit manipulation to do two compares at once. For example:
8111 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8112 // TODO: This could be extended to merge any 2 cases in switches with 3
8114 // TODO: Handle cases where W.CaseBB != SwitchBB.
8115 CaseCluster &Small = *W.FirstCluster;
8116 CaseCluster &Big = *W.LastCluster;
8118 if (Small.Low == Small.High && Big.Low == Big.High &&
8119 Small.MBB == Big.MBB) {
8120 const APInt &SmallValue = Small.Low->getValue();
8121 const APInt &BigValue = Big.Low->getValue();
8123 // Check that there is only one bit different.
8124 APInt CommonBit = BigValue ^ SmallValue;
8125 if (CommonBit.isPowerOf2()) {
8126 SDValue CondLHS = getValue(Cond);
8127 EVT VT = CondLHS.getValueType();
8128 SDLoc DL = getCurSDLoc();
8130 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8131 DAG.getConstant(CommonBit, DL, VT));
8132 SDValue Cond = DAG.getSetCC(
8133 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8136 // Update successor info.
8137 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8138 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8139 addSuccessorWithWeight(
8140 SwitchMBB, DefaultMBB,
8141 // The default destination is the first successor in IR.
8142 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8145 // Insert the true branch.
8147 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8148 DAG.getBasicBlock(Small.MBB));
8149 // Insert the false branch.
8150 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8151 DAG.getBasicBlock(DefaultMBB));
8153 DAG.setRoot(BrCond);
8159 if (TM.getOptLevel() != CodeGenOpt::None) {
8160 // Order cases by weight so the most likely case will be checked first.
8161 std::sort(W.FirstCluster, W.LastCluster + 1,
8162 [](const CaseCluster &a, const CaseCluster &b) {
8163 return a.Weight > b.Weight;
8166 // Rearrange the case blocks so that the last one falls through if possible
8167 // without without changing the order of weights.
8168 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8170 if (I->Weight > W.LastCluster->Weight)
8172 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8173 std::swap(*I, *W.LastCluster);
8179 // Compute total weight.
8180 uint32_t DefaultWeight = W.DefaultWeight;
8181 uint32_t UnhandledWeights = DefaultWeight;
8182 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8183 UnhandledWeights += I->Weight;
8184 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8187 MachineBasicBlock *CurMBB = W.MBB;
8188 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8189 MachineBasicBlock *Fallthrough;
8190 if (I == W.LastCluster) {
8191 // For the last cluster, fall through to the default destination.
8192 Fallthrough = DefaultMBB;
8194 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8195 CurMF->insert(BBI, Fallthrough);
8196 // Put Cond in a virtual register to make it available from the new blocks.
8197 ExportFromCurrentBlock(Cond);
8199 UnhandledWeights -= I->Weight;
8202 case CC_JumpTable: {
8203 // FIXME: Optimize away range check based on pivot comparisons.
8204 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8205 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8207 // The jump block hasn't been inserted yet; insert it here.
8208 MachineBasicBlock *JumpMBB = JT->MBB;
8209 CurMF->insert(BBI, JumpMBB);
8211 uint32_t JumpWeight = I->Weight;
8212 uint32_t FallthroughWeight = UnhandledWeights;
8214 // If the default statement is a target of the jump table, we evenly
8215 // distribute the default weight to successors of CurMBB. Also update
8216 // the weight on the edge from JumpMBB to Fallthrough.
8217 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8218 SE = JumpMBB->succ_end();
8220 if (*SI == DefaultMBB) {
8221 JumpWeight += DefaultWeight / 2;
8222 FallthroughWeight -= DefaultWeight / 2;
8223 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8228 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8229 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8231 // The jump table header will be inserted in our current block, do the
8232 // range check, and fall through to our fallthrough block.
8233 JTH->HeaderBB = CurMBB;
8234 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8236 // If we're in the right place, emit the jump table header right now.
8237 if (CurMBB == SwitchMBB) {
8238 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8239 JTH->Emitted = true;
8244 // FIXME: Optimize away range check based on pivot comparisons.
8245 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8247 // The bit test blocks haven't been inserted yet; insert them here.
8248 for (BitTestCase &BTC : BTB->Cases)
8249 CurMF->insert(BBI, BTC.ThisBB);
8251 // Fill in fields of the BitTestBlock.
8252 BTB->Parent = CurMBB;
8253 BTB->Default = Fallthrough;
8255 BTB->DefaultWeight = UnhandledWeights;
8256 // If the cases in bit test don't form a contiguous range, we evenly
8257 // distribute the weight on the edge to Fallthrough to two successors
8259 if (!BTB->ContiguousRange) {
8260 BTB->Weight += DefaultWeight / 2;
8261 BTB->DefaultWeight -= DefaultWeight / 2;
8264 // If we're in the right place, emit the bit test header right now.
8265 if (CurMBB == SwitchMBB) {
8266 visitBitTestHeader(*BTB, SwitchMBB);
8267 BTB->Emitted = true;
8272 const Value *RHS, *LHS, *MHS;
8274 if (I->Low == I->High) {
8275 // Check Cond == I->Low.
8281 // Check I->Low <= Cond <= I->High.
8288 // The false weight is the sum of all unhandled cases.
8289 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8292 if (CurMBB == SwitchMBB)
8293 visitSwitchCase(CB, SwitchMBB);
8295 SwitchCases.push_back(CB);
8300 CurMBB = Fallthrough;
8304 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8305 CaseClusterIt First,
8306 CaseClusterIt Last) {
8307 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8308 if (X.Weight != CC.Weight)
8309 return X.Weight > CC.Weight;
8311 // Ties are broken by comparing the case value.
8312 return X.Low->getValue().slt(CC.Low->getValue());
8316 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8317 const SwitchWorkListItem &W,
8319 MachineBasicBlock *SwitchMBB) {
8320 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8321 "Clusters not sorted?");
8323 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8325 // Balance the tree based on branch weights to create a near-optimal (in terms
8326 // of search time given key frequency) binary search tree. See e.g. Kurt
8327 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8328 CaseClusterIt LastLeft = W.FirstCluster;
8329 CaseClusterIt FirstRight = W.LastCluster;
8330 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8331 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8333 // Move LastLeft and FirstRight towards each other from opposite directions to
8334 // find a partitioning of the clusters which balances the weight on both
8335 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8336 // taken to ensure 0-weight nodes are distributed evenly.
8338 while (LastLeft + 1 < FirstRight) {
8339 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8340 LeftWeight += (++LastLeft)->Weight;
8342 RightWeight += (--FirstRight)->Weight;
8347 // Our binary search tree differs from a typical BST in that ours can have up
8348 // to three values in each leaf. The pivot selection above doesn't take that
8349 // into account, which means the tree might require more nodes and be less
8350 // efficient. We compensate for this here.
8352 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8353 unsigned NumRight = W.LastCluster - FirstRight + 1;
8355 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8356 // If one side has less than 3 clusters, and the other has more than 3,
8357 // consider taking a cluster from the other side.
8359 if (NumLeft < NumRight) {
8360 // Consider moving the first cluster on the right to the left side.
8361 CaseCluster &CC = *FirstRight;
8362 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8363 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8364 if (LeftSideRank <= RightSideRank) {
8365 // Moving the cluster to the left does not demote it.
8371 assert(NumRight < NumLeft);
8372 // Consider moving the last element on the left to the right side.
8373 CaseCluster &CC = *LastLeft;
8374 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8375 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8376 if (RightSideRank <= LeftSideRank) {
8377 // Moving the cluster to the right does not demot it.
8387 assert(LastLeft + 1 == FirstRight);
8388 assert(LastLeft >= W.FirstCluster);
8389 assert(FirstRight <= W.LastCluster);
8391 // Use the first element on the right as pivot since we will make less-than
8392 // comparisons against it.
8393 CaseClusterIt PivotCluster = FirstRight;
8394 assert(PivotCluster > W.FirstCluster);
8395 assert(PivotCluster <= W.LastCluster);
8397 CaseClusterIt FirstLeft = W.FirstCluster;
8398 CaseClusterIt LastRight = W.LastCluster;
8400 const ConstantInt *Pivot = PivotCluster->Low;
8402 // New blocks will be inserted immediately after the current one.
8403 MachineFunction::iterator BBI(W.MBB);
8406 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8407 // we can branch to its destination directly if it's squeezed exactly in
8408 // between the known lower bound and Pivot - 1.
8409 MachineBasicBlock *LeftMBB;
8410 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8411 FirstLeft->Low == W.GE &&
8412 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8413 LeftMBB = FirstLeft->MBB;
8415 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8416 FuncInfo.MF->insert(BBI, LeftMBB);
8418 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8419 // Put Cond in a virtual register to make it available from the new blocks.
8420 ExportFromCurrentBlock(Cond);
8423 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8424 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8425 // directly if RHS.High equals the current upper bound.
8426 MachineBasicBlock *RightMBB;
8427 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8428 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8429 RightMBB = FirstRight->MBB;
8431 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8432 FuncInfo.MF->insert(BBI, RightMBB);
8434 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8435 // Put Cond in a virtual register to make it available from the new blocks.
8436 ExportFromCurrentBlock(Cond);
8439 // Create the CaseBlock record that will be used to lower the branch.
8440 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8441 LeftWeight, RightWeight);
8443 if (W.MBB == SwitchMBB)
8444 visitSwitchCase(CB, SwitchMBB);
8446 SwitchCases.push_back(CB);
8449 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8450 // Extract cases from the switch.
8451 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8452 CaseClusterVector Clusters;
8453 Clusters.reserve(SI.getNumCases());
8454 for (auto I : SI.cases()) {
8455 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8456 const ConstantInt *CaseVal = I.getCaseValue();
8458 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8459 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8462 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8464 // Cluster adjacent cases with the same destination. We do this at all
8465 // optimization levels because it's cheap to do and will make codegen faster
8466 // if there are many clusters.
8467 sortAndRangeify(Clusters);
8469 if (TM.getOptLevel() != CodeGenOpt::None) {
8470 // Replace an unreachable default with the most popular destination.
8471 // FIXME: Exploit unreachable default more aggressively.
8472 bool UnreachableDefault =
8473 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8474 if (UnreachableDefault && !Clusters.empty()) {
8475 DenseMap<const BasicBlock *, unsigned> Popularity;
8476 unsigned MaxPop = 0;
8477 const BasicBlock *MaxBB = nullptr;
8478 for (auto I : SI.cases()) {
8479 const BasicBlock *BB = I.getCaseSuccessor();
8480 if (++Popularity[BB] > MaxPop) {
8481 MaxPop = Popularity[BB];
8486 assert(MaxPop > 0 && MaxBB);
8487 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8489 // Remove cases that were pointing to the destination that is now the
8491 CaseClusterVector New;
8492 New.reserve(Clusters.size());
8493 for (CaseCluster &CC : Clusters) {
8494 if (CC.MBB != DefaultMBB)
8497 Clusters = std::move(New);
8501 // If there is only the default destination, jump there directly.
8502 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8503 if (Clusters.empty()) {
8504 SwitchMBB->addSuccessor(DefaultMBB);
8505 if (DefaultMBB != NextBlock(SwitchMBB)) {
8506 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8507 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8512 findJumpTables(Clusters, &SI, DefaultMBB);
8513 findBitTestClusters(Clusters, &SI);
8516 dbgs() << "Case clusters: ";
8517 for (const CaseCluster &C : Clusters) {
8518 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8519 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8521 C.Low->getValue().print(dbgs(), true);
8522 if (C.Low != C.High) {
8524 C.High->getValue().print(dbgs(), true);
8531 assert(!Clusters.empty());
8532 SwitchWorkList WorkList;
8533 CaseClusterIt First = Clusters.begin();
8534 CaseClusterIt Last = Clusters.end() - 1;
8535 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8536 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8538 while (!WorkList.empty()) {
8539 SwitchWorkListItem W = WorkList.back();
8540 WorkList.pop_back();
8541 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8543 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8544 // For optimized builds, lower large range as a balanced binary tree.
8545 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8549 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);