1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "isel"
15 #include "SDNodeDbgValue.h"
16 #include "SelectionDAGBuilder.h"
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/PostOrderIterator.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Constants.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Function.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/InlineAsm.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/IntrinsicInst.h"
31 #include "llvm/LLVMContext.h"
32 #include "llvm/Module.h"
33 #include "llvm/CodeGen/Analysis.h"
34 #include "llvm/CodeGen/FastISel.h"
35 #include "llvm/CodeGen/FunctionLoweringInfo.h"
36 #include "llvm/CodeGen/GCStrategy.h"
37 #include "llvm/CodeGen/GCMetadata.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineJumpTableInfo.h"
42 #include "llvm/CodeGen/MachineModuleInfo.h"
43 #include "llvm/CodeGen/MachineRegisterInfo.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Analysis/DebugInfo.h"
46 #include "llvm/Target/TargetData.h"
47 #include "llvm/Target/TargetFrameLowering.h"
48 #include "llvm/Target/TargetInstrInfo.h"
49 #include "llvm/Target/TargetIntrinsicInfo.h"
50 #include "llvm/Target/TargetLibraryInfo.h"
51 #include "llvm/Target/TargetLowering.h"
52 #include "llvm/Target/TargetOptions.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/CRSBuilder.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
62 /// LimitFloatPrecision - Generate low-precision inline sequences for
63 /// some float libcalls (6, 8 or 12 bits).
64 static unsigned LimitFloatPrecision;
66 static cl::opt<unsigned, true>
67 LimitFPPrecision("limit-float-precision",
68 cl::desc("Generate low-precision inline sequences "
69 "for some float libcalls"),
70 cl::location(LimitFloatPrecision),
73 // Limit the width of DAG chains. This is important in general to prevent
74 // prevent DAG-based analysis from blowing up. For example, alias analysis and
75 // load clustering may not complete in reasonable time. It is difficult to
76 // recognize and avoid this situation within each individual analysis, and
77 // future analyses are likely to have the same behavior. Limiting DAG width is
78 // the safe approach, and will be especially important with global DAGs.
80 // MaxParallelChains default is arbitrarily high to avoid affecting
81 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
82 // sequence over this should have been converted to llvm.memcpy by the
83 // frontend. It easy to induce this behavior with .ll code such as:
84 // %buffer = alloca [4096 x i8]
85 // %data = load [4096 x i8]* %argPtr
86 // store [4096 x i8] %data, [4096 x i8]* %buffer
87 static const unsigned MaxParallelChains = 64;
89 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
90 const SDValue *Parts, unsigned NumParts,
91 EVT PartVT, EVT ValueVT);
93 /// getCopyFromParts - Create a value that contains the specified legal parts
94 /// combined into the value they represent. If the parts combine to a type
95 /// larger then ValueVT then AssertOp can be used to specify whether the extra
96 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
97 /// (ISD::AssertSext).
98 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL,
100 unsigned NumParts, EVT PartVT, EVT ValueVT,
101 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
102 if (ValueVT.isVector())
103 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT);
105 assert(NumParts > 0 && "No parts to assemble!");
106 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
107 SDValue Val = Parts[0];
110 // Assemble the value from multiple parts.
111 if (ValueVT.isInteger()) {
112 unsigned PartBits = PartVT.getSizeInBits();
113 unsigned ValueBits = ValueVT.getSizeInBits();
115 // Assemble the power of 2 part.
116 unsigned RoundParts = NumParts & (NumParts - 1) ?
117 1 << Log2_32(NumParts) : NumParts;
118 unsigned RoundBits = PartBits * RoundParts;
119 EVT RoundVT = RoundBits == ValueBits ?
120 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
123 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
125 if (RoundParts > 2) {
126 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
128 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
129 RoundParts / 2, PartVT, HalfVT);
131 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
132 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
135 if (TLI.isBigEndian())
138 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
140 if (RoundParts < NumParts) {
141 // Assemble the trailing non-power-of-2 part.
142 unsigned OddParts = NumParts - RoundParts;
143 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
144 Hi = getCopyFromParts(DAG, DL,
145 Parts + RoundParts, OddParts, PartVT, OddVT);
147 // Combine the round and odd parts.
149 if (TLI.isBigEndian())
151 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
152 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
153 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
154 DAG.getConstant(Lo.getValueType().getSizeInBits(),
155 TLI.getPointerTy()));
156 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
157 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
159 } else if (PartVT.isFloatingPoint()) {
160 // FP split into multiple FP parts (for ppcf128)
161 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) &&
164 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
165 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
166 if (TLI.isBigEndian())
168 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
170 // FP split into integer parts (soft fp)
171 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
172 !PartVT.isVector() && "Unexpected split");
173 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
174 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT);
178 // There is now one part, held in Val. Correct it to match ValueVT.
179 PartVT = Val.getValueType();
181 if (PartVT == ValueVT)
184 if (PartVT.isInteger() && ValueVT.isInteger()) {
185 if (ValueVT.bitsLT(PartVT)) {
186 // For a truncate, see if we have any information to
187 // indicate whether the truncated bits will always be
188 // zero or sign-extension.
189 if (AssertOp != ISD::DELETED_NODE)
190 Val = DAG.getNode(AssertOp, DL, PartVT, Val,
191 DAG.getValueType(ValueVT));
192 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
194 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
197 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
198 // FP_ROUND's are always exact here.
199 if (ValueVT.bitsLT(Val.getValueType()))
200 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
201 DAG.getTargetConstant(1, TLI.getPointerTy()));
203 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
206 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits())
207 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
209 llvm_unreachable("Unknown mismatch!");
212 /// getCopyFromParts - Create a value that contains the specified legal parts
213 /// combined into the value they represent. If the parts combine to a type
214 /// larger then ValueVT then AssertOp can be used to specify whether the extra
215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
216 /// (ISD::AssertSext).
217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL,
218 const SDValue *Parts, unsigned NumParts,
219 EVT PartVT, EVT ValueVT) {
220 assert(ValueVT.isVector() && "Not a vector value");
221 assert(NumParts > 0 && "No parts to assemble!");
222 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
223 SDValue Val = Parts[0];
225 // Handle a multi-element vector.
227 EVT IntermediateVT, RegisterVT;
228 unsigned NumIntermediates;
230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
231 NumIntermediates, RegisterVT);
232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
233 NumParts = NumRegs; // Silence a compiler warning.
234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
235 assert(RegisterVT == Parts[0].getValueType() &&
236 "Part type doesn't match part!");
238 // Assemble the parts into intermediate operands.
239 SmallVector<SDValue, 8> Ops(NumIntermediates);
240 if (NumIntermediates == NumParts) {
241 // If the register was not expanded, truncate or copy the value,
243 for (unsigned i = 0; i != NumParts; ++i)
244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
245 PartVT, IntermediateVT);
246 } else if (NumParts > 0) {
247 // If the intermediate type was expanded, build the intermediate
248 // operands from the parts.
249 assert(NumParts % NumIntermediates == 0 &&
250 "Must expand into a divisible number of parts!");
251 unsigned Factor = NumParts / NumIntermediates;
252 for (unsigned i = 0; i != NumIntermediates; ++i)
253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
254 PartVT, IntermediateVT);
257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
258 // intermediate operands.
259 Val = DAG.getNode(IntermediateVT.isVector() ?
260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
261 ValueVT, &Ops[0], NumIntermediates);
264 // There is now one part, held in Val. Correct it to match ValueVT.
265 PartVT = Val.getValueType();
267 if (PartVT == ValueVT)
270 if (PartVT.isVector()) {
271 // If the element type of the source/dest vectors are the same, but the
272 // parts vector has more elements than the value vector, then we have a
273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) {
276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
277 "Cannot narrow, it would be a lossy transformation");
278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
279 DAG.getIntPtrConstant(0));
282 // Vector/Vector bitcast.
283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits())
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
287 "Cannot handle this kind of promotion");
288 // Promoted vector extract
289 bool Smaller = ValueVT.bitsLE(PartVT);
290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
295 // Trivial bitcast if the types are the same size and the destination
296 // vector type is legal.
297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() &&
298 TLI.isTypeLegal(ValueVT))
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
301 // Handle cases such as i8 -> <1 x i1>
302 assert(ValueVT.getVectorNumElements() == 1 &&
303 "Only trivial scalar-to-vector conversions should get here!");
305 if (ValueVT.getVectorNumElements() == 1 &&
306 ValueVT.getVectorElementType() != PartVT) {
307 bool Smaller = ValueVT.bitsLE(PartVT);
308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
309 DL, ValueVT.getScalarType(), Val);
312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl,
319 SDValue Val, SDValue *Parts, unsigned NumParts,
322 /// getCopyToParts - Create a series of nodes that contain the specified value
323 /// split into legal parts. If the parts contain more bits than Val, then, for
324 /// integers, ExtendKind can be used to specify how to generate the extra bits.
325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL,
326 SDValue Val, SDValue *Parts, unsigned NumParts,
328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
329 EVT ValueVT = Val.getValueType();
331 // Handle the vector case separately.
332 if (ValueVT.isVector())
333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT);
335 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
336 unsigned PartBits = PartVT.getSizeInBits();
337 unsigned OrigNumParts = NumParts;
338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
343 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
344 if (PartVT == ValueVT) {
345 assert(NumParts == 1 && "No-op copy with multiple parts!");
350 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
351 // If the parts cover more bits than the value has, promote the value.
352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
353 assert(NumParts == 1 && "Do not know what to promote to!");
354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
356 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
357 ValueVT.isInteger() &&
358 "Unknown mismatch!");
359 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
360 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
361 if (PartVT == MVT::x86mmx)
362 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
364 } else if (PartBits == ValueVT.getSizeInBits()) {
365 // Different types of the same size.
366 assert(NumParts == 1 && PartVT != ValueVT);
367 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
368 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
369 // If the parts cover less bits than value has, truncate the value.
370 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
371 ValueVT.isInteger() &&
372 "Unknown mismatch!");
373 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
374 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
375 if (PartVT == MVT::x86mmx)
376 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
379 // The value may have changed - recompute ValueVT.
380 ValueVT = Val.getValueType();
381 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
382 "Failed to tile the value with PartVT!");
385 assert(PartVT == ValueVT && "Type conversion failed!");
390 // Expand the value into multiple parts.
391 if (NumParts & (NumParts - 1)) {
392 // The number of parts is not a power of 2. Split off and copy the tail.
393 assert(PartVT.isInteger() && ValueVT.isInteger() &&
394 "Do not know what to expand to!");
395 unsigned RoundParts = 1 << Log2_32(NumParts);
396 unsigned RoundBits = RoundParts * PartBits;
397 unsigned OddParts = NumParts - RoundParts;
398 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
399 DAG.getIntPtrConstant(RoundBits));
400 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT);
402 if (TLI.isBigEndian())
403 // The odd parts were reversed by getCopyToParts - unreverse them.
404 std::reverse(Parts + RoundParts, Parts + NumParts);
406 NumParts = RoundParts;
407 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
408 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
411 // The number of parts is a power of 2. Repeatedly bisect the value using
413 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
414 EVT::getIntegerVT(*DAG.getContext(),
415 ValueVT.getSizeInBits()),
418 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
419 for (unsigned i = 0; i < NumParts; i += StepSize) {
420 unsigned ThisBits = StepSize * PartBits / 2;
421 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
422 SDValue &Part0 = Parts[i];
423 SDValue &Part1 = Parts[i+StepSize/2];
425 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
426 ThisVT, Part0, DAG.getIntPtrConstant(1));
427 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
428 ThisVT, Part0, DAG.getIntPtrConstant(0));
430 if (ThisBits == PartBits && ThisVT != PartVT) {
431 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
432 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
437 if (TLI.isBigEndian())
438 std::reverse(Parts, Parts + OrigNumParts);
442 /// getCopyToPartsVector - Create a series of nodes that contain the specified
443 /// value split into legal parts.
444 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL,
445 SDValue Val, SDValue *Parts, unsigned NumParts,
447 EVT ValueVT = Val.getValueType();
448 assert(ValueVT.isVector() && "Not a vector");
449 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
452 if (PartVT == ValueVT) {
454 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
455 // Bitconvert vector->vector case.
456 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
457 } else if (PartVT.isVector() &&
458 PartVT.getVectorElementType() == ValueVT.getVectorElementType() &&
459 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
460 EVT ElementVT = PartVT.getVectorElementType();
461 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
463 SmallVector<SDValue, 16> Ops;
464 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
465 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
466 ElementVT, Val, DAG.getIntPtrConstant(i)));
468 for (unsigned i = ValueVT.getVectorNumElements(),
469 e = PartVT.getVectorNumElements(); i != e; ++i)
470 Ops.push_back(DAG.getUNDEF(ElementVT));
472 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
474 // FIXME: Use CONCAT for 2x -> 4x.
476 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
477 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
478 } else if (PartVT.isVector() &&
479 PartVT.getVectorElementType().bitsGE(
480 ValueVT.getVectorElementType()) &&
481 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
483 // Promoted vector extract
484 bool Smaller = PartVT.bitsLE(ValueVT);
485 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
488 // Vector -> scalar conversion.
489 assert(ValueVT.getVectorNumElements() == 1 &&
490 "Only trivial vector-to-scalar conversions should get here!");
491 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 PartVT, Val, DAG.getIntPtrConstant(0));
494 bool Smaller = ValueVT.bitsLE(PartVT);
495 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
503 // Handle a multi-element vector.
504 EVT IntermediateVT, RegisterVT;
505 unsigned NumIntermediates;
506 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
508 NumIntermediates, RegisterVT);
509 unsigned NumElements = ValueVT.getVectorNumElements();
511 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
512 NumParts = NumRegs; // Silence a compiler warning.
513 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
515 // Split the vector into intermediate operands.
516 SmallVector<SDValue, 8> Ops(NumIntermediates);
517 for (unsigned i = 0; i != NumIntermediates; ++i) {
518 if (IntermediateVT.isVector())
519 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
521 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates)));
523 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
524 IntermediateVT, Val, DAG.getIntPtrConstant(i));
527 // Split the intermediate operands into legal parts.
528 if (NumParts == NumIntermediates) {
529 // If the register was not expanded, promote or copy the value,
531 for (unsigned i = 0; i != NumParts; ++i)
532 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT);
533 } else if (NumParts > 0) {
534 // If the intermediate type was expanded, split each the value into
536 assert(NumParts % NumIntermediates == 0 &&
537 "Must expand into a divisible number of parts!");
538 unsigned Factor = NumParts / NumIntermediates;
539 for (unsigned i = 0; i != NumIntermediates; ++i)
540 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT);
548 /// RegsForValue - This struct represents the registers (physical or virtual)
549 /// that a particular set of values is assigned, and the type information
550 /// about the value. The most common situation is to represent one value at a
551 /// time, but struct or array values are handled element-wise as multiple
552 /// values. The splitting of aggregates is performed recursively, so that we
553 /// never have aggregate-typed registers. The values at this point do not
554 /// necessarily have legal types, so each value may require one or more
555 /// registers of some legal type.
557 struct RegsForValue {
558 /// ValueVTs - The value types of the values, which may not be legal, and
559 /// may need be promoted or synthesized from one or more registers.
561 SmallVector<EVT, 4> ValueVTs;
563 /// RegVTs - The value types of the registers. This is the same size as
564 /// ValueVTs and it records, for each value, what the type of the assigned
565 /// register or registers are. (Individual values are never synthesized
566 /// from more than one type of register.)
568 /// With virtual registers, the contents of RegVTs is redundant with TLI's
569 /// getRegisterType member function, however when with physical registers
570 /// it is necessary to have a separate record of the types.
572 SmallVector<EVT, 4> RegVTs;
574 /// Regs - This list holds the registers assigned to the values.
575 /// Each legal or promoted value requires one register, and each
576 /// expanded value requires multiple registers.
578 SmallVector<unsigned, 4> Regs;
582 RegsForValue(const SmallVector<unsigned, 4> ®s,
583 EVT regvt, EVT valuevt)
584 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
586 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
587 unsigned Reg, Type *Ty) {
588 ComputeValueVTs(tli, Ty, ValueVTs);
590 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
591 EVT ValueVT = ValueVTs[Value];
592 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
593 EVT RegisterVT = tli.getRegisterType(Context, ValueVT);
594 for (unsigned i = 0; i != NumRegs; ++i)
595 Regs.push_back(Reg + i);
596 RegVTs.push_back(RegisterVT);
601 /// areValueTypesLegal - Return true if types of all the values are legal.
602 bool areValueTypesLegal(const TargetLowering &TLI) {
603 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
604 EVT RegisterVT = RegVTs[Value];
605 if (!TLI.isTypeLegal(RegisterVT))
611 /// append - Add the specified values to this one.
612 void append(const RegsForValue &RHS) {
613 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
614 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
615 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
618 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
619 /// this value and returns the result as a ValueVTs value. This uses
620 /// Chain/Flag as the input and updates them for the output Chain/Flag.
621 /// If the Flag pointer is NULL, no flag is used.
622 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
624 SDValue &Chain, SDValue *Flag) const;
626 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
627 /// specified value into the registers specified by this object. This uses
628 /// Chain/Flag as the input and updates them for the output Chain/Flag.
629 /// If the Flag pointer is NULL, no flag is used.
630 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
631 SDValue &Chain, SDValue *Flag) const;
633 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
634 /// operand list. This adds the code marker, matching input operand index
635 /// (if applicable), and includes the number of values added into it.
636 void AddInlineAsmOperands(unsigned Kind,
637 bool HasMatching, unsigned MatchingIdx,
639 std::vector<SDValue> &Ops) const;
643 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
644 /// this value and returns the result as a ValueVT value. This uses
645 /// Chain/Flag as the input and updates them for the output Chain/Flag.
646 /// If the Flag pointer is NULL, no flag is used.
647 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
648 FunctionLoweringInfo &FuncInfo,
650 SDValue &Chain, SDValue *Flag) const {
651 // A Value with type {} or [0 x %t] needs no registers.
652 if (ValueVTs.empty())
655 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
657 // Assemble the legal parts into the final values.
658 SmallVector<SDValue, 4> Values(ValueVTs.size());
659 SmallVector<SDValue, 8> Parts;
660 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
661 // Copy the legal parts from the registers.
662 EVT ValueVT = ValueVTs[Value];
663 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
664 EVT RegisterVT = RegVTs[Value];
666 Parts.resize(NumRegs);
667 for (unsigned i = 0; i != NumRegs; ++i) {
670 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
672 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
673 *Flag = P.getValue(2);
676 Chain = P.getValue(1);
679 // If the source register was virtual and if we know something about it,
680 // add an assert node.
681 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
682 !RegisterVT.isInteger() || RegisterVT.isVector())
685 const FunctionLoweringInfo::LiveOutInfo *LOI =
686 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
690 unsigned RegSize = RegisterVT.getSizeInBits();
691 unsigned NumSignBits = LOI->NumSignBits;
692 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
694 // FIXME: We capture more information than the dag can represent. For
695 // now, just use the tightest assertzext/assertsext possible.
697 EVT FromVT(MVT::Other);
698 if (NumSignBits == RegSize)
699 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
700 else if (NumZeroBits >= RegSize-1)
701 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
702 else if (NumSignBits > RegSize-8)
703 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
704 else if (NumZeroBits >= RegSize-8)
705 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
706 else if (NumSignBits > RegSize-16)
707 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
708 else if (NumZeroBits >= RegSize-16)
709 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
710 else if (NumSignBits > RegSize-32)
711 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
712 else if (NumZeroBits >= RegSize-32)
713 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
717 // Add an assertion node.
718 assert(FromVT != MVT::Other);
719 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
720 RegisterVT, P, DAG.getValueType(FromVT));
723 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
724 NumRegs, RegisterVT, ValueVT);
729 return DAG.getNode(ISD::MERGE_VALUES, dl,
730 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
731 &Values[0], ValueVTs.size());
734 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
735 /// specified value into the registers specified by this object. This uses
736 /// Chain/Flag as the input and updates them for the output Chain/Flag.
737 /// If the Flag pointer is NULL, no flag is used.
738 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl,
739 SDValue &Chain, SDValue *Flag) const {
740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
742 // Get the list of the values's legal parts.
743 unsigned NumRegs = Regs.size();
744 SmallVector<SDValue, 8> Parts(NumRegs);
745 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
746 EVT ValueVT = ValueVTs[Value];
747 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
748 EVT RegisterVT = RegVTs[Value];
750 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
751 &Parts[Part], NumParts, RegisterVT);
755 // Copy the parts into the registers.
756 SmallVector<SDValue, 8> Chains(NumRegs);
757 for (unsigned i = 0; i != NumRegs; ++i) {
760 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
762 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
763 *Flag = Part.getValue(1);
766 Chains[i] = Part.getValue(0);
769 if (NumRegs == 1 || Flag)
770 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
771 // flagged to it. That is the CopyToReg nodes and the user are considered
772 // a single scheduling unit. If we create a TokenFactor and return it as
773 // chain, then the TokenFactor is both a predecessor (operand) of the
774 // user as well as a successor (the TF operands are flagged to the user).
775 // c1, f1 = CopyToReg
776 // c2, f2 = CopyToReg
777 // c3 = TokenFactor c1, c2
780 Chain = Chains[NumRegs-1];
782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
785 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
786 /// operand list. This adds the code marker and includes the number of
787 /// values added into it.
788 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
789 unsigned MatchingIdx,
791 std::vector<SDValue> &Ops) const {
792 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
794 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
796 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
797 else if (!Regs.empty() &&
798 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
799 // Put the register class of the virtual registers in the flag word. That
800 // way, later passes can recompute register class constraints for inline
801 // assembly as well as normal instructions.
802 // Don't do this for tied operands that can use the regclass information
804 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
805 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
806 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
809 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
812 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
813 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
814 EVT RegisterVT = RegVTs[Value];
815 for (unsigned i = 0; i != NumRegs; ++i) {
816 assert(Reg < Regs.size() && "Mismatch in # registers expected");
817 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
822 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
823 const TargetLibraryInfo *li) {
827 TD = DAG.getTarget().getTargetData();
828 LPadToCallSiteMap.clear();
831 /// clear - Clear out the current SelectionDAG and the associated
832 /// state and prepare this SelectionDAGBuilder object to be used
833 /// for a new block. This doesn't clear out information about
834 /// additional blocks that are needed to complete switch lowering
835 /// or PHI node updating; that information is cleared out as it is
837 void SelectionDAGBuilder::clear() {
839 UnusedArgNodeMap.clear();
840 PendingLoads.clear();
841 PendingExports.clear();
842 CurDebugLoc = DebugLoc();
846 /// clearDanglingDebugInfo - Clear the dangling debug information
847 /// map. This function is seperated from the clear so that debug
848 /// information that is dangling in a basic block can be properly
849 /// resolved in a different basic block. This allows the
850 /// SelectionDAG to resolve dangling debug information attached
852 void SelectionDAGBuilder::clearDanglingDebugInfo() {
853 DanglingDebugInfoMap.clear();
856 /// getRoot - Return the current virtual root of the Selection DAG,
857 /// flushing any PendingLoad items. This must be done before emitting
858 /// a store or any other node that may need to be ordered after any
859 /// prior load instructions.
861 SDValue SelectionDAGBuilder::getRoot() {
862 if (PendingLoads.empty())
863 return DAG.getRoot();
865 if (PendingLoads.size() == 1) {
866 SDValue Root = PendingLoads[0];
868 PendingLoads.clear();
872 // Otherwise, we have to make a token factor node.
873 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
874 &PendingLoads[0], PendingLoads.size());
875 PendingLoads.clear();
880 /// getControlRoot - Similar to getRoot, but instead of flushing all the
881 /// PendingLoad items, flush all the PendingExports items. It is necessary
882 /// to do this before emitting a terminator instruction.
884 SDValue SelectionDAGBuilder::getControlRoot() {
885 SDValue Root = DAG.getRoot();
887 if (PendingExports.empty())
890 // Turn all of the CopyToReg chains into one factored node.
891 if (Root.getOpcode() != ISD::EntryToken) {
892 unsigned i = 0, e = PendingExports.size();
893 for (; i != e; ++i) {
894 assert(PendingExports[i].getNode()->getNumOperands() > 1);
895 if (PendingExports[i].getNode()->getOperand(0) == Root)
896 break; // Don't add the root if we already indirectly depend on it.
900 PendingExports.push_back(Root);
903 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
905 PendingExports.size());
906 PendingExports.clear();
911 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
912 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
913 DAG.AssignOrdering(Node, SDNodeOrder);
915 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
916 AssignOrderingToNode(Node->getOperand(I).getNode());
919 void SelectionDAGBuilder::visit(const Instruction &I) {
920 // Set up outgoing PHI node register values before emitting the terminator.
921 if (isa<TerminatorInst>(&I))
922 HandlePHINodesInSuccessorBlocks(I.getParent());
924 CurDebugLoc = I.getDebugLoc();
926 visit(I.getOpcode(), I);
928 if (!isa<TerminatorInst>(&I) && !HasTailCall)
929 CopyToExportRegsIfNeeded(&I);
931 CurDebugLoc = DebugLoc();
934 void SelectionDAGBuilder::visitPHI(const PHINode &) {
935 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
938 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
939 // Note: this doesn't use InstVisitor, because it has to work with
940 // ConstantExpr's in addition to instructions.
942 default: llvm_unreachable("Unknown instruction type encountered!");
943 // Build the switch statement using the Instruction.def file.
944 #define HANDLE_INST(NUM, OPCODE, CLASS) \
945 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break;
946 #include "llvm/Instruction.def"
949 // Assign the ordering to the freshly created DAG nodes.
950 if (NodeMap.count(&I)) {
952 AssignOrderingToNode(getValue(&I).getNode());
956 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
957 // generate the debug data structures now that we've seen its definition.
958 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
960 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
962 const DbgValueInst *DI = DDI.getDI();
963 DebugLoc dl = DDI.getdl();
964 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
965 MDNode *Variable = DI->getVariable();
966 uint64_t Offset = DI->getOffset();
969 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
970 SDV = DAG.getDbgValue(Variable, Val.getNode(),
971 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
972 DAG.AddDbgValue(SDV, Val.getNode(), false);
975 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
976 DanglingDebugInfoMap[V] = DanglingDebugInfo();
980 /// getValue - Return an SDValue for the given Value.
981 SDValue SelectionDAGBuilder::getValue(const Value *V) {
982 // If we already have an SDValue for this value, use it. It's important
983 // to do this first, so that we don't create a CopyFromReg if we already
984 // have a regular SDValue.
985 SDValue &N = NodeMap[V];
986 if (N.getNode()) return N;
988 // If there's a virtual register allocated and initialized for this
990 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
991 if (It != FuncInfo.ValueMap.end()) {
992 unsigned InReg = It->second;
993 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType());
994 SDValue Chain = DAG.getEntryNode();
995 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
996 resolveDanglingDebugInfo(V, N);
1000 // Otherwise create a new SDValue and remember it.
1001 SDValue Val = getValueImpl(V);
1003 resolveDanglingDebugInfo(V, Val);
1007 /// getNonRegisterValue - Return an SDValue for the given Value, but
1008 /// don't look in FuncInfo.ValueMap for a virtual register.
1009 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1010 // If we already have an SDValue for this value, use it.
1011 SDValue &N = NodeMap[V];
1012 if (N.getNode()) return N;
1014 // Otherwise create a new SDValue and remember it.
1015 SDValue Val = getValueImpl(V);
1017 resolveDanglingDebugInfo(V, Val);
1021 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1022 /// Create an SDValue for the given value.
1023 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1024 if (const Constant *C = dyn_cast<Constant>(V)) {
1025 EVT VT = TLI.getValueType(V->getType(), true);
1027 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1028 return DAG.getConstant(*CI, VT);
1030 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1031 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT);
1033 if (isa<ConstantPointerNull>(C))
1034 return DAG.getConstant(0, TLI.getPointerTy());
1036 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1037 return DAG.getConstantFP(*CFP, VT);
1039 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1040 return DAG.getUNDEF(VT);
1042 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1043 visit(CE->getOpcode(), *CE);
1044 SDValue N1 = NodeMap[V];
1045 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1049 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1050 SmallVector<SDValue, 4> Constants;
1051 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1053 SDNode *Val = getValue(*OI).getNode();
1054 // If the operand is an empty aggregate, there are no values.
1056 // Add each leaf value from the operand to the Constants list
1057 // to form a flattened list of all the values.
1058 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1059 Constants.push_back(SDValue(Val, i));
1062 return DAG.getMergeValues(&Constants[0], Constants.size(),
1066 if (const ConstantDataSequential *CDS =
1067 dyn_cast<ConstantDataSequential>(C)) {
1068 SmallVector<SDValue, 4> Ops;
1069 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1070 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1071 // Add each leaf value from the operand to the Constants list
1072 // to form a flattened list of all the values.
1073 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1074 Ops.push_back(SDValue(Val, i));
1077 if (isa<ArrayType>(CDS->getType()))
1078 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurDebugLoc());
1079 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1080 VT, &Ops[0], Ops.size());
1083 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1084 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1085 "Unknown struct or array constant!");
1087 SmallVector<EVT, 4> ValueVTs;
1088 ComputeValueVTs(TLI, C->getType(), ValueVTs);
1089 unsigned NumElts = ValueVTs.size();
1091 return SDValue(); // empty struct
1092 SmallVector<SDValue, 4> Constants(NumElts);
1093 for (unsigned i = 0; i != NumElts; ++i) {
1094 EVT EltVT = ValueVTs[i];
1095 if (isa<UndefValue>(C))
1096 Constants[i] = DAG.getUNDEF(EltVT);
1097 else if (EltVT.isFloatingPoint())
1098 Constants[i] = DAG.getConstantFP(0, EltVT);
1100 Constants[i] = DAG.getConstant(0, EltVT);
1103 return DAG.getMergeValues(&Constants[0], NumElts,
1107 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1108 return DAG.getBlockAddress(BA, VT);
1110 VectorType *VecTy = cast<VectorType>(V->getType());
1111 unsigned NumElements = VecTy->getNumElements();
1113 // Now that we know the number and type of the elements, get that number of
1114 // elements into the Ops array based on what kind of constant it is.
1115 SmallVector<SDValue, 16> Ops;
1116 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1117 for (unsigned i = 0; i != NumElements; ++i)
1118 Ops.push_back(getValue(CV->getOperand(i)));
1120 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1121 EVT EltVT = TLI.getValueType(VecTy->getElementType());
1124 if (EltVT.isFloatingPoint())
1125 Op = DAG.getConstantFP(0, EltVT);
1127 Op = DAG.getConstant(0, EltVT);
1128 Ops.assign(NumElements, Op);
1131 // Create a BUILD_VECTOR node.
1132 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
1133 VT, &Ops[0], Ops.size());
1136 // If this is a static alloca, generate it as the frameindex instead of
1138 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1139 DenseMap<const AllocaInst*, int>::iterator SI =
1140 FuncInfo.StaticAllocaMap.find(AI);
1141 if (SI != FuncInfo.StaticAllocaMap.end())
1142 return DAG.getFrameIndex(SI->second, TLI.getPointerTy());
1145 // If this is an instruction which fast-isel has deferred, select it now.
1146 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1147 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1148 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
1149 SDValue Chain = DAG.getEntryNode();
1150 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
1153 llvm_unreachable("Can't get register for value!");
1156 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1157 SDValue Chain = getControlRoot();
1158 SmallVector<ISD::OutputArg, 8> Outs;
1159 SmallVector<SDValue, 8> OutVals;
1161 if (!FuncInfo.CanLowerReturn) {
1162 unsigned DemoteReg = FuncInfo.DemoteRegister;
1163 const Function *F = I.getParent()->getParent();
1165 // Emit a store of the return value through the virtual register.
1166 // Leave Outs empty so that LowerReturn won't try to load return
1167 // registers the usual way.
1168 SmallVector<EVT, 1> PtrValueVTs;
1169 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()),
1172 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1173 SDValue RetOp = getValue(I.getOperand(0));
1175 SmallVector<EVT, 4> ValueVTs;
1176 SmallVector<uint64_t, 4> Offsets;
1177 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1178 unsigned NumValues = ValueVTs.size();
1180 SmallVector<SDValue, 4> Chains(NumValues);
1181 for (unsigned i = 0; i != NumValues; ++i) {
1182 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(),
1183 RetPtr.getValueType(), RetPtr,
1184 DAG.getIntPtrConstant(Offsets[i]));
1186 DAG.getStore(Chain, getCurDebugLoc(),
1187 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1188 // FIXME: better loc info would be nice.
1189 Add, MachinePointerInfo(), false, false, 0);
1192 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
1193 MVT::Other, &Chains[0], NumValues);
1194 } else if (I.getNumOperands() != 0) {
1195 SmallVector<EVT, 4> ValueVTs;
1196 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs);
1197 unsigned NumValues = ValueVTs.size();
1199 SDValue RetOp = getValue(I.getOperand(0));
1200 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1201 EVT VT = ValueVTs[j];
1203 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1205 const Function *F = I.getParent()->getParent();
1206 if (F->paramHasAttr(0, Attribute::SExt))
1207 ExtendKind = ISD::SIGN_EXTEND;
1208 else if (F->paramHasAttr(0, Attribute::ZExt))
1209 ExtendKind = ISD::ZERO_EXTEND;
1211 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1212 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind);
1214 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT);
1215 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT);
1216 SmallVector<SDValue, 4> Parts(NumParts);
1217 getCopyToParts(DAG, getCurDebugLoc(),
1218 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1219 &Parts[0], NumParts, PartVT, ExtendKind);
1221 // 'inreg' on function refers to return value
1222 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1223 if (F->paramHasAttr(0, Attribute::InReg))
1226 // Propagate extension type if any
1227 if (ExtendKind == ISD::SIGN_EXTEND)
1229 else if (ExtendKind == ISD::ZERO_EXTEND)
1232 for (unsigned i = 0; i < NumParts; ++i) {
1233 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1235 OutVals.push_back(Parts[i]);
1241 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1242 CallingConv::ID CallConv =
1243 DAG.getMachineFunction().getFunction()->getCallingConv();
1244 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg,
1245 Outs, OutVals, getCurDebugLoc(), DAG);
1247 // Verify that the target's LowerReturn behaved as expected.
1248 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1249 "LowerReturn didn't return a valid chain!");
1251 // Update the DAG with the new chain value resulting from return lowering.
1255 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1256 /// created for it, emit nodes to copy the value into the virtual
1258 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1260 if (V->getType()->isEmptyTy())
1263 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1264 if (VMI != FuncInfo.ValueMap.end()) {
1265 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1266 CopyValueToVirtualRegister(V, VMI->second);
1270 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1271 /// the current basic block, add it to ValueMap now so that we'll get a
1273 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1274 // No need to export constants.
1275 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1277 // Already exported?
1278 if (FuncInfo.isExportedInst(V)) return;
1280 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1281 CopyValueToVirtualRegister(V, Reg);
1284 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1285 const BasicBlock *FromBB) {
1286 // The operands of the setcc have to be in this block. We don't know
1287 // how to export them from some other block.
1288 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1289 // Can export from current BB.
1290 if (VI->getParent() == FromBB)
1293 // Is already exported, noop.
1294 return FuncInfo.isExportedInst(V);
1297 // If this is an argument, we can export it if the BB is the entry block or
1298 // if it is already exported.
1299 if (isa<Argument>(V)) {
1300 if (FromBB == &FromBB->getParent()->getEntryBlock())
1303 // Otherwise, can only export this if it is already exported.
1304 return FuncInfo.isExportedInst(V);
1307 // Otherwise, constants can always be exported.
1311 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1312 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1313 const MachineBasicBlock *Dst) const {
1314 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1317 const BasicBlock *SrcBB = Src->getBasicBlock();
1318 const BasicBlock *DstBB = Dst->getBasicBlock();
1319 return BPI->getEdgeWeight(SrcBB, DstBB);
1322 void SelectionDAGBuilder::
1323 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1324 uint32_t Weight /* = 0 */) {
1326 Weight = getEdgeWeight(Src, Dst);
1327 Src->addSuccessor(Dst, Weight);
1331 static bool InBlock(const Value *V, const BasicBlock *BB) {
1332 if (const Instruction *I = dyn_cast<Instruction>(V))
1333 return I->getParent() == BB;
1337 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1338 /// This function emits a branch and is used at the leaves of an OR or an
1339 /// AND operator tree.
1342 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1343 MachineBasicBlock *TBB,
1344 MachineBasicBlock *FBB,
1345 MachineBasicBlock *CurBB,
1346 MachineBasicBlock *SwitchBB) {
1347 const BasicBlock *BB = CurBB->getBasicBlock();
1349 // If the leaf of the tree is a comparison, merge the condition into
1351 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1352 // The operands of the cmp have to be in this block. We don't know
1353 // how to export them from some other block. If this is the first block
1354 // of the sequence, no exporting is needed.
1355 if (CurBB == SwitchBB ||
1356 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1357 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1358 ISD::CondCode Condition;
1359 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1360 Condition = getICmpCondCode(IC->getPredicate());
1361 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1362 Condition = getFCmpCondCode(FC->getPredicate());
1363 if (TM.Options.NoNaNsFPMath)
1364 Condition = getFCmpCodeWithoutNaN(Condition);
1366 Condition = ISD::SETEQ; // silence warning.
1367 llvm_unreachable("Unknown compare instruction");
1370 CaseBlock CB(Condition, BOp->getOperand(0),
1371 BOp->getOperand(1), NULL, TBB, FBB, CurBB);
1372 SwitchCases.push_back(CB);
1377 // Create a CaseBlock record representing this branch.
1378 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1379 NULL, TBB, FBB, CurBB);
1380 SwitchCases.push_back(CB);
1383 /// FindMergedConditions - If Cond is an expression like
1384 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1385 MachineBasicBlock *TBB,
1386 MachineBasicBlock *FBB,
1387 MachineBasicBlock *CurBB,
1388 MachineBasicBlock *SwitchBB,
1390 // If this node is not part of the or/and tree, emit it as a branch.
1391 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1392 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1393 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1394 BOp->getParent() != CurBB->getBasicBlock() ||
1395 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1396 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1397 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB);
1401 // Create TmpBB after CurBB.
1402 MachineFunction::iterator BBI = CurBB;
1403 MachineFunction &MF = DAG.getMachineFunction();
1404 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1405 CurBB->getParent()->insert(++BBI, TmpBB);
1407 if (Opc == Instruction::Or) {
1408 // Codegen X | Y as:
1416 // Emit the LHS condition.
1417 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc);
1419 // Emit the RHS condition into TmpBB.
1420 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1422 assert(Opc == Instruction::And && "Unknown merge op!");
1423 // Codegen X & Y as:
1430 // This requires creation of TmpBB after CurBB.
1432 // Emit the LHS condition.
1433 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc);
1435 // Emit the RHS condition into TmpBB.
1436 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc);
1440 /// If the set of cases should be emitted as a series of branches, return true.
1441 /// If we should emit this as a bunch of and/or'd together conditions, return
1444 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
1445 if (Cases.size() != 2) return true;
1447 // If this is two comparisons of the same values or'd or and'd together, they
1448 // will get folded into a single comparison, so don't emit two blocks.
1449 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1450 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1451 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1452 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1456 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1457 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1458 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1459 Cases[0].CC == Cases[1].CC &&
1460 isa<Constant>(Cases[0].CmpRHS) &&
1461 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1462 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1464 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1471 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1472 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1474 // Update machine-CFG edges.
1475 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1477 // Figure out which block is immediately after the current one.
1478 MachineBasicBlock *NextBlock = 0;
1479 MachineFunction::iterator BBI = BrMBB;
1480 if (++BBI != FuncInfo.MF->end())
1483 if (I.isUnconditional()) {
1484 // Update machine-CFG edges.
1485 BrMBB->addSuccessor(Succ0MBB);
1487 // If this is not a fall-through branch, emit the branch.
1488 if (Succ0MBB != NextBlock)
1489 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1490 MVT::Other, getControlRoot(),
1491 DAG.getBasicBlock(Succ0MBB)));
1496 // If this condition is one of the special cases we handle, do special stuff
1498 const Value *CondVal = I.getCondition();
1499 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1501 // If this is a series of conditions that are or'd or and'd together, emit
1502 // this as a sequence of branches instead of setcc's with and/or operations.
1503 // As long as jumps are not expensive, this should improve performance.
1504 // For example, instead of something like:
1517 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1518 if (!TLI.isJumpExpensive() &&
1520 (BOp->getOpcode() == Instruction::And ||
1521 BOp->getOpcode() == Instruction::Or)) {
1522 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1524 // If the compares in later blocks need to use values not currently
1525 // exported from this block, export them now. This block should always
1526 // be the first entry.
1527 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1529 // Allow some cases to be rejected.
1530 if (ShouldEmitAsBranches(SwitchCases)) {
1531 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1532 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1533 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1536 // Emit the branch for this block.
1537 visitSwitchCase(SwitchCases[0], BrMBB);
1538 SwitchCases.erase(SwitchCases.begin());
1542 // Okay, we decided not to do this, remove any inserted MBB's and clear
1544 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1545 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1547 SwitchCases.clear();
1551 // Create a CaseBlock record representing this branch.
1552 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1553 NULL, Succ0MBB, Succ1MBB, BrMBB);
1555 // Use visitSwitchCase to actually insert the fast branch sequence for this
1557 visitSwitchCase(CB, BrMBB);
1560 /// visitSwitchCase - Emits the necessary code to represent a single node in
1561 /// the binary search tree resulting from lowering a switch instruction.
1562 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1563 MachineBasicBlock *SwitchBB) {
1565 SDValue CondLHS = getValue(CB.CmpLHS);
1566 DebugLoc dl = getCurDebugLoc();
1568 // Build the setcc now.
1569 if (CB.CmpMHS == NULL) {
1570 // Fold "(X == true)" to X and "(X == false)" to !X to
1571 // handle common cases produced by branch lowering.
1572 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1573 CB.CC == ISD::SETEQ)
1575 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1576 CB.CC == ISD::SETEQ) {
1577 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1578 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1580 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1582 assert(CB.CC == ISD::SETCC_INVALID &&
1583 "Condition is undefined for to-the-range belonging check.");
1585 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1586 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1588 SDValue CmpOp = getValue(CB.CmpMHS);
1589 EVT VT = CmpOp.getValueType();
1591 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(false)) {
1592 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1595 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1596 VT, CmpOp, DAG.getConstant(Low, VT));
1597 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1598 DAG.getConstant(High-Low, VT), ISD::SETULE);
1602 // Update successor info
1603 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1604 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1606 // Set NextBlock to be the MBB immediately after the current one, if any.
1607 // This is used to avoid emitting unnecessary branches to the next block.
1608 MachineBasicBlock *NextBlock = 0;
1609 MachineFunction::iterator BBI = SwitchBB;
1610 if (++BBI != FuncInfo.MF->end())
1613 // If the lhs block is the next block, invert the condition so that we can
1614 // fall through to the lhs instead of the rhs block.
1615 if (CB.TrueBB == NextBlock) {
1616 std::swap(CB.TrueBB, CB.FalseBB);
1617 SDValue True = DAG.getConstant(1, Cond.getValueType());
1618 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1621 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1622 MVT::Other, getControlRoot(), Cond,
1623 DAG.getBasicBlock(CB.TrueBB));
1625 // Insert the false branch. Do this even if it's a fall through branch,
1626 // this makes it easier to do DAG optimizations which require inverting
1627 // the branch condition.
1628 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1629 DAG.getBasicBlock(CB.FalseBB));
1631 DAG.setRoot(BrCond);
1634 /// visitJumpTable - Emit JumpTable node in the current MBB
1635 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1636 // Emit the code for the jump table
1637 assert(JT.Reg != -1U && "Should lower JT Header first!");
1638 EVT PTy = TLI.getPointerTy();
1639 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1641 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1642 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
1643 MVT::Other, Index.getValue(1),
1645 DAG.setRoot(BrJumpTable);
1648 /// visitJumpTableHeader - This function emits necessary code to produce index
1649 /// in the JumpTable from switch case.
1650 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1651 JumpTableHeader &JTH,
1652 MachineBasicBlock *SwitchBB) {
1653 // Subtract the lowest switch case value from the value being switched on and
1654 // conditional branch to default mbb if the result is greater than the
1655 // difference between smallest and largest cases.
1656 SDValue SwitchOp = getValue(JTH.SValue);
1657 EVT VT = SwitchOp.getValueType();
1658 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1659 DAG.getConstant(JTH.First, VT));
1661 // The SDNode we just created, which holds the value being switched on minus
1662 // the smallest case value, needs to be copied to a virtual register so it
1663 // can be used as an index into the jump table in a subsequent basic block.
1664 // This value may be smaller or larger than the target's pointer type, and
1665 // therefore require extension or truncating.
1666 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy());
1668 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy());
1669 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1670 JumpTableReg, SwitchOp);
1671 JT.Reg = JumpTableReg;
1673 // Emit the range check for the jump table, and branch to the default block
1674 // for the switch statement if the value being switched on exceeds the largest
1675 // case in the switch.
1676 SDValue CMP = DAG.getSetCC(getCurDebugLoc(),
1677 TLI.getSetCCResultType(Sub.getValueType()), Sub,
1678 DAG.getConstant(JTH.Last-JTH.First,VT),
1681 // Set NextBlock to be the MBB immediately after the current one, if any.
1682 // This is used to avoid emitting unnecessary branches to the next block.
1683 MachineBasicBlock *NextBlock = 0;
1684 MachineFunction::iterator BBI = SwitchBB;
1686 if (++BBI != FuncInfo.MF->end())
1689 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1690 MVT::Other, CopyTo, CMP,
1691 DAG.getBasicBlock(JT.Default));
1693 if (JT.MBB != NextBlock)
1694 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
1695 DAG.getBasicBlock(JT.MBB));
1697 DAG.setRoot(BrCond);
1700 /// visitBitTestHeader - This function emits necessary code to produce value
1701 /// suitable for "bit tests"
1702 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1703 MachineBasicBlock *SwitchBB) {
1704 // Subtract the minimum value
1705 SDValue SwitchOp = getValue(B.SValue);
1706 EVT VT = SwitchOp.getValueType();
1707 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
1708 DAG.getConstant(B.First, VT));
1711 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(),
1712 TLI.getSetCCResultType(Sub.getValueType()),
1713 Sub, DAG.getConstant(B.Range, VT),
1716 // Determine the type of the test operands.
1717 bool UsePtrType = false;
1718 if (!TLI.isTypeLegal(VT))
1721 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1722 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1723 // Switch table case range are encoded into series of masks.
1724 // Just use pointer type, it's guaranteed to fit.
1730 VT = TLI.getPointerTy();
1731 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT);
1735 B.Reg = FuncInfo.CreateReg(VT);
1736 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(),
1739 // Set NextBlock to be the MBB immediately after the current one, if any.
1740 // This is used to avoid emitting unnecessary branches to the next block.
1741 MachineBasicBlock *NextBlock = 0;
1742 MachineFunction::iterator BBI = SwitchBB;
1743 if (++BBI != FuncInfo.MF->end())
1746 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1748 addSuccessorWithWeight(SwitchBB, B.Default);
1749 addSuccessorWithWeight(SwitchBB, MBB);
1751 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1752 MVT::Other, CopyTo, RangeCmp,
1753 DAG.getBasicBlock(B.Default));
1755 if (MBB != NextBlock)
1756 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
1757 DAG.getBasicBlock(MBB));
1759 DAG.setRoot(BrRange);
1762 /// visitBitTestCase - this function produces one "bit test"
1763 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1764 MachineBasicBlock* NextMBB,
1767 MachineBasicBlock *SwitchBB) {
1769 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
1772 unsigned PopCount = CountPopulation_64(B.Mask);
1773 if (PopCount == 1) {
1774 // Testing for a single bit; just compare the shift count with what it
1775 // would need to be to shift a 1 bit in that position.
1776 Cmp = DAG.getSetCC(getCurDebugLoc(),
1777 TLI.getSetCCResultType(VT),
1779 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT),
1781 } else if (PopCount == BB.Range) {
1782 // There is only one zero bit in the range, test for it directly.
1783 Cmp = DAG.getSetCC(getCurDebugLoc(),
1784 TLI.getSetCCResultType(VT),
1786 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1789 // Make desired shift
1790 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT,
1791 DAG.getConstant(1, VT), ShiftOp);
1793 // Emit bit tests and jumps
1794 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(),
1795 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1796 Cmp = DAG.getSetCC(getCurDebugLoc(),
1797 TLI.getSetCCResultType(VT),
1798 AndOp, DAG.getConstant(0, VT),
1802 addSuccessorWithWeight(SwitchBB, B.TargetBB);
1803 addSuccessorWithWeight(SwitchBB, NextMBB);
1805 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
1806 MVT::Other, getControlRoot(),
1807 Cmp, DAG.getBasicBlock(B.TargetBB));
1809 // Set NextBlock to be the MBB immediately after the current one, if any.
1810 // This is used to avoid emitting unnecessary branches to the next block.
1811 MachineBasicBlock *NextBlock = 0;
1812 MachineFunction::iterator BBI = SwitchBB;
1813 if (++BBI != FuncInfo.MF->end())
1816 if (NextMBB != NextBlock)
1817 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
1818 DAG.getBasicBlock(NextMBB));
1823 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1824 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1826 // Retrieve successors.
1827 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
1828 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
1830 const Value *Callee(I.getCalledValue());
1831 if (isa<InlineAsm>(Callee))
1834 LowerCallTo(&I, getValue(Callee), false, LandingPad);
1836 // If the value of the invoke is used outside of its defining block, make it
1837 // available as a virtual register.
1838 CopyToExportRegsIfNeeded(&I);
1840 // Update successor info
1841 addSuccessorWithWeight(InvokeMBB, Return);
1842 addSuccessorWithWeight(InvokeMBB, LandingPad);
1844 // Drop into normal successor.
1845 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
1846 MVT::Other, getControlRoot(),
1847 DAG.getBasicBlock(Return)));
1850 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
1851 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
1854 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
1855 assert(FuncInfo.MBB->isLandingPad() &&
1856 "Call to landingpad not in landing pad!");
1858 MachineBasicBlock *MBB = FuncInfo.MBB;
1859 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
1860 AddLandingPadInfo(LP, MMI, MBB);
1862 // If there aren't registers to copy the values into (e.g., during SjLj
1863 // exceptions), then don't bother to create these DAG nodes.
1864 if (TLI.getExceptionPointerRegister() == 0 &&
1865 TLI.getExceptionSelectorRegister() == 0)
1868 SmallVector<EVT, 2> ValueVTs;
1869 ComputeValueVTs(TLI, LP.getType(), ValueVTs);
1871 // Insert the EXCEPTIONADDR instruction.
1872 assert(FuncInfo.MBB->isLandingPad() &&
1873 "Call to eh.exception not in landing pad!");
1874 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1876 Ops[0] = DAG.getRoot();
1877 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1);
1878 SDValue Chain = Op1.getValue(1);
1880 // Insert the EHSELECTION instruction.
1881 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
1884 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2);
1885 Chain = Op2.getValue(1);
1886 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32);
1890 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
1891 DAG.getVTList(&ValueVTs[0], ValueVTs.size()),
1894 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain);
1895 setValue(&LP, RetPair.first);
1896 DAG.setRoot(RetPair.second);
1899 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
1900 /// small case ranges).
1901 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
1902 CaseRecVector& WorkList,
1904 MachineBasicBlock *Default,
1905 MachineBasicBlock *SwitchBB) {
1906 Case& BackCase = *(CR.Range.second-1);
1908 // Size is the number of Cases represented by this range.
1909 size_t Size = CR.Range.second - CR.Range.first;
1913 // Get the MachineFunction which holds the current MBB. This is used when
1914 // inserting any additional MBBs necessary to represent the switch.
1915 MachineFunction *CurMF = FuncInfo.MF;
1917 // Figure out which block is immediately after the current one.
1918 MachineBasicBlock *NextBlock = 0;
1919 MachineFunction::iterator BBI = CR.CaseBB;
1921 if (++BBI != FuncInfo.MF->end())
1924 // If any two of the cases has the same destination, and if one value
1925 // is the same as the other, but has one bit unset that the other has set,
1926 // use bit manipulation to do two compares at once. For example:
1927 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
1928 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
1929 // TODO: Handle cases where CR.CaseBB != SwitchBB.
1930 if (Size == 2 && CR.CaseBB == SwitchBB) {
1931 Case &Small = *CR.Range.first;
1932 Case &Big = *(CR.Range.second-1);
1934 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
1935 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
1936 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
1938 // Check that there is only one bit different.
1939 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
1940 (SmallValue | BigValue) == BigValue) {
1941 // Isolate the common bit.
1942 APInt CommonBit = BigValue & ~SmallValue;
1943 assert((SmallValue | CommonBit) == BigValue &&
1944 CommonBit.countPopulation() == 1 && "Not a common bit?");
1946 SDValue CondLHS = getValue(SV);
1947 EVT VT = CondLHS.getValueType();
1948 DebugLoc DL = getCurDebugLoc();
1950 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
1951 DAG.getConstant(CommonBit, VT));
1952 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
1953 Or, DAG.getConstant(BigValue, VT),
1956 // Update successor info.
1957 addSuccessorWithWeight(SwitchBB, Small.BB);
1958 addSuccessorWithWeight(SwitchBB, Default);
1960 // Insert the true branch.
1961 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
1962 getControlRoot(), Cond,
1963 DAG.getBasicBlock(Small.BB));
1965 // Insert the false branch.
1966 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
1967 DAG.getBasicBlock(Default));
1969 DAG.setRoot(BrCond);
1975 // Rearrange the case blocks so that the last one falls through if possible.
1976 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
1977 // The last case block won't fall through into 'NextBlock' if we emit the
1978 // branches in this order. See if rearranging a case value would help.
1979 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) {
1980 if (I->BB == NextBlock) {
1981 std::swap(*I, BackCase);
1987 // Create a CaseBlock record representing a conditional branch to
1988 // the Case's target mbb if the value being switched on SV is equal
1990 MachineBasicBlock *CurBlock = CR.CaseBB;
1991 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
1992 MachineBasicBlock *FallThrough;
1994 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
1995 CurMF->insert(BBI, FallThrough);
1997 // Put SV in a virtual register to make it available from the new blocks.
1998 ExportFromCurrentBlock(SV);
2000 // If the last case doesn't match, go to the default block.
2001 FallThrough = Default;
2004 const Value *RHS, *LHS, *MHS;
2006 if (I->High == I->Low) {
2007 // This is just small small case range :) containing exactly 1 case
2009 LHS = SV; RHS = I->High; MHS = NULL;
2011 CC = ISD::SETCC_INVALID;
2012 LHS = I->Low; MHS = SV; RHS = I->High;
2015 uint32_t ExtraWeight = I->ExtraWeight;
2016 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2018 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2);
2020 // If emitting the first comparison, just call visitSwitchCase to emit the
2021 // code into the current block. Otherwise, push the CaseBlock onto the
2022 // vector to be later processed by SDISel, and insert the node's MBB
2023 // before the next MBB.
2024 if (CurBlock == SwitchBB)
2025 visitSwitchCase(CB, SwitchBB);
2027 SwitchCases.push_back(CB);
2029 CurBlock = FallThrough;
2035 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2036 return !TLI.getTargetMachine().Options.DisableJumpTables &&
2037 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2038 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2041 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2042 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2043 APInt LastExt = Last.zext(BitWidth), FirstExt = First.zext(BitWidth);
2044 return (LastExt - FirstExt + 1ULL);
2047 /// handleJTSwitchCase - Emit jumptable for current switch case range
2048 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2049 CaseRecVector &WorkList,
2051 MachineBasicBlock *Default,
2052 MachineBasicBlock *SwitchBB) {
2053 Case& FrontCase = *CR.Range.first;
2054 Case& BackCase = *(CR.Range.second-1);
2056 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2057 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2059 APInt TSize(First.getBitWidth(), 0);
2060 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2063 if (!areJTsAllowed(TLI) || TSize.ult(4))
2066 APInt Range = ComputeRange(First, Last);
2067 // The density is TSize / Range. Require at least 40%.
2068 // It should not be possible for IntTSize to saturate for sane code, but make
2069 // sure we handle Range saturation correctly.
2070 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2071 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2072 if (IntTSize * 10 < IntRange * 4)
2075 DEBUG(dbgs() << "Lowering jump table\n"
2076 << "First entry: " << First << ". Last entry: " << Last << '\n'
2077 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2079 // Get the MachineFunction which holds the current MBB. This is used when
2080 // inserting any additional MBBs necessary to represent the switch.
2081 MachineFunction *CurMF = FuncInfo.MF;
2083 // Figure out which block is immediately after the current one.
2084 MachineFunction::iterator BBI = CR.CaseBB;
2087 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2089 // Create a new basic block to hold the code for loading the address
2090 // of the jump table, and jumping to it. Update successor information;
2091 // we will either branch to the default case for the switch, or the jump
2093 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2094 CurMF->insert(BBI, JumpTableBB);
2096 addSuccessorWithWeight(CR.CaseBB, Default);
2097 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2099 // Build a vector of destination BBs, corresponding to each target
2100 // of the jump table. If the value of the jump table slot corresponds to
2101 // a case statement, push the case's BB onto the vector, otherwise, push
2103 std::vector<MachineBasicBlock*> DestBBs;
2105 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2106 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2107 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2109 if (Low.ule(TEI) && TEI.ule(High)) {
2110 DestBBs.push_back(I->BB);
2114 DestBBs.push_back(Default);
2118 // Update successor info. Add one edge to each unique successor.
2119 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2120 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2121 E = DestBBs.end(); I != E; ++I) {
2122 if (!SuccsHandled[(*I)->getNumber()]) {
2123 SuccsHandled[(*I)->getNumber()] = true;
2124 addSuccessorWithWeight(JumpTableBB, *I);
2128 // Create a jump table index for this jump table.
2129 unsigned JTEncoding = TLI.getJumpTableEncoding();
2130 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2131 ->createJumpTableIndex(DestBBs);
2133 // Set the jump table information so that we can codegen it as a second
2134 // MachineBasicBlock
2135 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2136 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2137 if (CR.CaseBB == SwitchBB)
2138 visitJumpTableHeader(JT, JTH, SwitchBB);
2140 JTCases.push_back(JumpTableBlock(JTH, JT));
2144 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2146 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2147 CaseRecVector& WorkList,
2149 MachineBasicBlock *Default,
2150 MachineBasicBlock *SwitchBB) {
2151 // Get the MachineFunction which holds the current MBB. This is used when
2152 // inserting any additional MBBs necessary to represent the switch.
2153 MachineFunction *CurMF = FuncInfo.MF;
2155 // Figure out which block is immediately after the current one.
2156 MachineFunction::iterator BBI = CR.CaseBB;
2159 Case& FrontCase = *CR.Range.first;
2160 Case& BackCase = *(CR.Range.second-1);
2161 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2163 // Size is the number of Cases represented by this range.
2164 unsigned Size = CR.Range.second - CR.Range.first;
2166 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2167 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2169 CaseItr Pivot = CR.Range.first + Size/2;
2171 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2172 // (heuristically) allow us to emit JumpTable's later.
2173 APInt TSize(First.getBitWidth(), 0);
2174 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2178 APInt LSize = FrontCase.size();
2179 APInt RSize = TSize-LSize;
2180 DEBUG(dbgs() << "Selecting best pivot: \n"
2181 << "First: " << First << ", Last: " << Last <<'\n'
2182 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2183 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2185 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2186 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2187 APInt Range = ComputeRange(LEnd, RBegin);
2188 assert((Range - 2ULL).isNonNegative() &&
2189 "Invalid case distance");
2190 // Use volatile double here to avoid excess precision issues on some hosts,
2191 // e.g. that use 80-bit X87 registers.
2192 volatile double LDensity =
2193 (double)LSize.roundToDouble() /
2194 (LEnd - First + 1ULL).roundToDouble();
2195 volatile double RDensity =
2196 (double)RSize.roundToDouble() /
2197 (Last - RBegin + 1ULL).roundToDouble();
2198 double Metric = Range.logBase2()*(LDensity+RDensity);
2199 // Should always split in some non-trivial place
2200 DEBUG(dbgs() <<"=>Step\n"
2201 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2202 << "LDensity: " << LDensity
2203 << ", RDensity: " << RDensity << '\n'
2204 << "Metric: " << Metric << '\n');
2205 if (FMetric < Metric) {
2208 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2214 if (areJTsAllowed(TLI)) {
2215 // If our case is dense we *really* should handle it earlier!
2216 assert((FMetric > 0) && "Should handle dense range earlier!");
2218 Pivot = CR.Range.first + Size/2;
2221 CaseRange LHSR(CR.Range.first, Pivot);
2222 CaseRange RHSR(Pivot, CR.Range.second);
2223 const Constant *C = Pivot->Low;
2224 MachineBasicBlock *FalseBB = 0, *TrueBB = 0;
2226 // We know that we branch to the LHS if the Value being switched on is
2227 // less than the Pivot value, C. We use this to optimize our binary
2228 // tree a bit, by recognizing that if SV is greater than or equal to the
2229 // LHS's Case Value, and that Case Value is exactly one less than the
2230 // Pivot's Value, then we can branch directly to the LHS's Target,
2231 // rather than creating a leaf node for it.
2232 if ((LHSR.second - LHSR.first) == 1 &&
2233 LHSR.first->High == CR.GE &&
2234 cast<ConstantInt>(C)->getValue() ==
2235 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2236 TrueBB = LHSR.first->BB;
2238 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2239 CurMF->insert(BBI, TrueBB);
2240 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2242 // Put SV in a virtual register to make it available from the new blocks.
2243 ExportFromCurrentBlock(SV);
2246 // Similar to the optimization above, if the Value being switched on is
2247 // known to be less than the Constant CR.LT, and the current Case Value
2248 // is CR.LT - 1, then we can branch directly to the target block for
2249 // the current Case Value, rather than emitting a RHS leaf node for it.
2250 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2251 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2252 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2253 FalseBB = RHSR.first->BB;
2255 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2256 CurMF->insert(BBI, FalseBB);
2257 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2259 // Put SV in a virtual register to make it available from the new blocks.
2260 ExportFromCurrentBlock(SV);
2263 // Create a CaseBlock record representing a conditional branch to
2264 // the LHS node if the value being switched on SV is less than C.
2265 // Otherwise, branch to LHS.
2266 CaseBlock CB(ISD::SETULT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB);
2268 if (CR.CaseBB == SwitchBB)
2269 visitSwitchCase(CB, SwitchBB);
2271 SwitchCases.push_back(CB);
2276 /// handleBitTestsSwitchCase - if current case range has few destination and
2277 /// range span less, than machine word bitwidth, encode case range into series
2278 /// of masks and emit bit tests with these masks.
2279 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2280 CaseRecVector& WorkList,
2282 MachineBasicBlock* Default,
2283 MachineBasicBlock *SwitchBB){
2284 EVT PTy = TLI.getPointerTy();
2285 unsigned IntPtrBits = PTy.getSizeInBits();
2287 Case& FrontCase = *CR.Range.first;
2288 Case& BackCase = *(CR.Range.second-1);
2290 // Get the MachineFunction which holds the current MBB. This is used when
2291 // inserting any additional MBBs necessary to represent the switch.
2292 MachineFunction *CurMF = FuncInfo.MF;
2294 // If target does not have legal shift left, do not emit bit tests at all.
2295 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy()))
2299 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2301 // Single case counts one, case range - two.
2302 numCmps += (I->Low == I->High ? 1 : 2);
2305 // Count unique destinations
2306 SmallSet<MachineBasicBlock*, 4> Dests;
2307 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2308 Dests.insert(I->BB);
2309 if (Dests.size() > 3)
2310 // Don't bother the code below, if there are too much unique destinations
2313 DEBUG(dbgs() << "Total number of unique destinations: "
2314 << Dests.size() << '\n'
2315 << "Total number of comparisons: " << numCmps << '\n');
2317 // Compute span of values.
2318 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2319 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2320 APInt cmpRange = maxValue - minValue;
2322 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2323 << "Low bound: " << minValue << '\n'
2324 << "High bound: " << maxValue << '\n');
2326 if (cmpRange.uge(IntPtrBits) ||
2327 (!(Dests.size() == 1 && numCmps >= 3) &&
2328 !(Dests.size() == 2 && numCmps >= 5) &&
2329 !(Dests.size() >= 3 && numCmps >= 6)))
2332 DEBUG(dbgs() << "Emitting bit tests\n");
2333 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2335 // Optimize the case where all the case values fit in a
2336 // word without having to subtract minValue. In this case,
2337 // we can optimize away the subtraction.
2338 if (maxValue.ult(IntPtrBits)) {
2339 cmpRange = maxValue;
2341 lowBound = minValue;
2344 CaseBitsVector CasesBits;
2345 unsigned i, count = 0;
2347 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2348 MachineBasicBlock* Dest = I->BB;
2349 for (i = 0; i < count; ++i)
2350 if (Dest == CasesBits[i].BB)
2354 assert((count < 3) && "Too much destinations to test!");
2355 CasesBits.push_back(CaseBits(0, Dest, 0));
2359 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2360 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2362 uint64_t lo = (lowValue - lowBound).getZExtValue();
2363 uint64_t hi = (highValue - lowBound).getZExtValue();
2365 for (uint64_t j = lo; j <= hi; j++) {
2366 CasesBits[i].Mask |= 1ULL << j;
2367 CasesBits[i].Bits++;
2371 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2375 // Figure out which block is immediately after the current one.
2376 MachineFunction::iterator BBI = CR.CaseBB;
2379 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2381 DEBUG(dbgs() << "Cases:\n");
2382 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2383 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2384 << ", Bits: " << CasesBits[i].Bits
2385 << ", BB: " << CasesBits[i].BB << '\n');
2387 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2388 CurMF->insert(BBI, CaseBB);
2389 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2393 // Put SV in a virtual register to make it available from the new blocks.
2394 ExportFromCurrentBlock(SV);
2397 BitTestBlock BTB(lowBound, cmpRange, SV,
2398 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2399 CR.CaseBB, Default, BTC);
2401 if (CR.CaseBB == SwitchBB)
2402 visitBitTestHeader(BTB, SwitchBB);
2404 BitTestCases.push_back(BTB);
2409 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2410 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2411 const SwitchInst& SI) {
2413 /// Use a shorter form of declaration, and also
2414 /// show the we want to use CRSBuilder as Clusterifier.
2415 typedef CRSBuilderBase<MachineBasicBlock, true> Clusterifier;
2417 Clusterifier TheClusterifier;
2419 // Start with "simple" cases
2420 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2422 const BasicBlock *SuccBB = i.getCaseSuccessor();
2423 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2425 TheClusterifier.add(i.getCaseValueEx(), SMBB);
2428 TheClusterifier.optimize();
2430 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2432 for (Clusterifier::RangeIterator i = TheClusterifier.begin(),
2433 e = TheClusterifier.end(); i != e; ++i, ++numCmps) {
2434 Clusterifier::Cluster &C = *i;
2437 W = BPI->getEdgeWeight(SI.getParent(), C.second->getBasicBlock());
2440 W *= C.first.Weight;
2441 BPI->setEdgeWeight(SI.getParent(), C.second->getBasicBlock(), W);
2444 Cases.push_back(Case(C.first.Low, C.first.High, C.second, W));
2446 if (C.first.Low != C.first.High)
2447 // A range counts double, since it requires two compares.
2454 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2455 MachineBasicBlock *Last) {
2457 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2458 if (JTCases[i].first.HeaderBB == First)
2459 JTCases[i].first.HeaderBB = Last;
2461 // Update BitTestCases.
2462 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2463 if (BitTestCases[i].Parent == First)
2464 BitTestCases[i].Parent = Last;
2467 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2468 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2470 // Figure out which block is immediately after the current one.
2471 MachineBasicBlock *NextBlock = 0;
2472 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2474 // If there is only the default destination, branch to it if it is not the
2475 // next basic block. Otherwise, just fall through.
2476 if (!SI.getNumCases()) {
2477 // Update machine-CFG edges.
2479 // If this is not a fall-through branch, emit the branch.
2480 SwitchMBB->addSuccessor(Default);
2481 if (Default != NextBlock)
2482 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
2483 MVT::Other, getControlRoot(),
2484 DAG.getBasicBlock(Default)));
2489 // If there are any non-default case statements, create a vector of Cases
2490 // representing each one, and sort the vector so that we can efficiently
2491 // create a binary search tree from them.
2493 size_t numCmps = Clusterify(Cases, SI);
2494 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2495 << ". Total compares: " << numCmps << '\n');
2498 // Get the Value to be switched on and default basic blocks, which will be
2499 // inserted into CaseBlock records, representing basic blocks in the binary
2501 const Value *SV = SI.getCondition();
2503 // Push the initial CaseRec onto the worklist
2504 CaseRecVector WorkList;
2505 WorkList.push_back(CaseRec(SwitchMBB,0,0,
2506 CaseRange(Cases.begin(),Cases.end())));
2508 while (!WorkList.empty()) {
2509 // Grab a record representing a case range to process off the worklist
2510 CaseRec CR = WorkList.back();
2511 WorkList.pop_back();
2513 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2516 // If the range has few cases (two or less) emit a series of specific
2518 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2521 // If the switch has more than 5 blocks, and at least 40% dense, and the
2522 // target supports indirect branches, then emit a jump table rather than
2523 // lowering the switch to a binary tree of conditional branches.
2524 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2527 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2528 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2529 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2533 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2534 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2536 // Update machine-CFG edges with unique successors.
2537 SmallVector<BasicBlock*, 32> succs;
2538 succs.reserve(I.getNumSuccessors());
2539 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i)
2540 succs.push_back(I.getSuccessor(i));
2541 array_pod_sort(succs.begin(), succs.end());
2542 succs.erase(std::unique(succs.begin(), succs.end()), succs.end());
2543 for (unsigned i = 0, e = succs.size(); i != e; ++i) {
2544 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]];
2545 addSuccessorWithWeight(IndirectBrMBB, Succ);
2548 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(),
2549 MVT::Other, getControlRoot(),
2550 getValue(I.getAddress())));
2553 void SelectionDAGBuilder::visitFSub(const User &I) {
2554 // -0.0 - X --> fneg
2555 Type *Ty = I.getType();
2556 if (isa<Constant>(I.getOperand(0)) &&
2557 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2558 SDValue Op2 = getValue(I.getOperand(1));
2559 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(),
2560 Op2.getValueType(), Op2));
2564 visitBinary(I, ISD::FSUB);
2567 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2568 SDValue Op1 = getValue(I.getOperand(0));
2569 SDValue Op2 = getValue(I.getOperand(1));
2570 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(),
2571 Op1.getValueType(), Op1, Op2));
2574 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2575 SDValue Op1 = getValue(I.getOperand(0));
2576 SDValue Op2 = getValue(I.getOperand(1));
2578 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType());
2580 // Coerce the shift amount to the right type if we can.
2581 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2582 unsigned ShiftSize = ShiftTy.getSizeInBits();
2583 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2584 DebugLoc DL = getCurDebugLoc();
2586 // If the operand is smaller than the shift count type, promote it.
2587 if (ShiftSize > Op2Size)
2588 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2590 // If the operand is larger than the shift count type but the shift
2591 // count type has enough bits to represent any shift value, truncate
2592 // it now. This is a common case and it exposes the truncate to
2593 // optimization early.
2594 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2595 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2596 // Otherwise we'll need to temporarily settle for some other convenient
2597 // type. Type legalization will make adjustments once the shiftee is split.
2599 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2602 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(),
2603 Op1.getValueType(), Op1, Op2));
2606 void SelectionDAGBuilder::visitSDiv(const User &I) {
2607 SDValue Op1 = getValue(I.getOperand(0));
2608 SDValue Op2 = getValue(I.getOperand(1));
2610 // Turn exact SDivs into multiplications.
2611 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2613 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2614 !isa<ConstantSDNode>(Op1) &&
2615 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2616 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG));
2618 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(),
2622 void SelectionDAGBuilder::visitICmp(const User &I) {
2623 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2624 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2625 predicate = IC->getPredicate();
2626 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2627 predicate = ICmpInst::Predicate(IC->getPredicate());
2628 SDValue Op1 = getValue(I.getOperand(0));
2629 SDValue Op2 = getValue(I.getOperand(1));
2630 ISD::CondCode Opcode = getICmpCondCode(predicate);
2632 EVT DestVT = TLI.getValueType(I.getType());
2633 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
2636 void SelectionDAGBuilder::visitFCmp(const User &I) {
2637 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2638 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2639 predicate = FC->getPredicate();
2640 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2641 predicate = FCmpInst::Predicate(FC->getPredicate());
2642 SDValue Op1 = getValue(I.getOperand(0));
2643 SDValue Op2 = getValue(I.getOperand(1));
2644 ISD::CondCode Condition = getFCmpCondCode(predicate);
2645 if (TM.Options.NoNaNsFPMath)
2646 Condition = getFCmpCodeWithoutNaN(Condition);
2647 EVT DestVT = TLI.getValueType(I.getType());
2648 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
2651 void SelectionDAGBuilder::visitSelect(const User &I) {
2652 SmallVector<EVT, 4> ValueVTs;
2653 ComputeValueVTs(TLI, I.getType(), ValueVTs);
2654 unsigned NumValues = ValueVTs.size();
2655 if (NumValues == 0) return;
2657 SmallVector<SDValue, 4> Values(NumValues);
2658 SDValue Cond = getValue(I.getOperand(0));
2659 SDValue TrueVal = getValue(I.getOperand(1));
2660 SDValue FalseVal = getValue(I.getOperand(2));
2661 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2662 ISD::VSELECT : ISD::SELECT;
2664 for (unsigned i = 0; i != NumValues; ++i)
2665 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(),
2666 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2668 SDValue(TrueVal.getNode(),
2669 TrueVal.getResNo() + i),
2670 SDValue(FalseVal.getNode(),
2671 FalseVal.getResNo() + i));
2673 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
2674 DAG.getVTList(&ValueVTs[0], NumValues),
2675 &Values[0], NumValues));
2678 void SelectionDAGBuilder::visitTrunc(const User &I) {
2679 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2680 SDValue N = getValue(I.getOperand(0));
2681 EVT DestVT = TLI.getValueType(I.getType());
2682 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
2685 void SelectionDAGBuilder::visitZExt(const User &I) {
2686 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2687 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2688 SDValue N = getValue(I.getOperand(0));
2689 EVT DestVT = TLI.getValueType(I.getType());
2690 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
2693 void SelectionDAGBuilder::visitSExt(const User &I) {
2694 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2695 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2696 SDValue N = getValue(I.getOperand(0));
2697 EVT DestVT = TLI.getValueType(I.getType());
2698 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
2701 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2702 // FPTrunc is never a no-op cast, no need to check
2703 SDValue N = getValue(I.getOperand(0));
2704 EVT DestVT = TLI.getValueType(I.getType());
2705 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
2707 DAG.getTargetConstant(0, TLI.getPointerTy())));
2710 void SelectionDAGBuilder::visitFPExt(const User &I){
2711 // FPExt is never a no-op cast, no need to check
2712 SDValue N = getValue(I.getOperand(0));
2713 EVT DestVT = TLI.getValueType(I.getType());
2714 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
2717 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2718 // FPToUI is never a no-op cast, no need to check
2719 SDValue N = getValue(I.getOperand(0));
2720 EVT DestVT = TLI.getValueType(I.getType());
2721 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
2724 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2725 // FPToSI is never a no-op cast, no need to check
2726 SDValue N = getValue(I.getOperand(0));
2727 EVT DestVT = TLI.getValueType(I.getType());
2728 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
2731 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2732 // UIToFP is never a no-op cast, no need to check
2733 SDValue N = getValue(I.getOperand(0));
2734 EVT DestVT = TLI.getValueType(I.getType());
2735 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
2738 void SelectionDAGBuilder::visitSIToFP(const User &I){
2739 // SIToFP is never a no-op cast, no need to check
2740 SDValue N = getValue(I.getOperand(0));
2741 EVT DestVT = TLI.getValueType(I.getType());
2742 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
2745 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2746 // What to do depends on the size of the integer and the size of the pointer.
2747 // We can either truncate, zero extend, or no-op, accordingly.
2748 SDValue N = getValue(I.getOperand(0));
2749 EVT DestVT = TLI.getValueType(I.getType());
2750 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2753 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2754 // What to do depends on the size of the integer and the size of the pointer.
2755 // We can either truncate, zero extend, or no-op, accordingly.
2756 SDValue N = getValue(I.getOperand(0));
2757 EVT DestVT = TLI.getValueType(I.getType());
2758 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT));
2761 void SelectionDAGBuilder::visitBitCast(const User &I) {
2762 SDValue N = getValue(I.getOperand(0));
2763 EVT DestVT = TLI.getValueType(I.getType());
2765 // BitCast assures us that source and destination are the same size so this is
2766 // either a BITCAST or a no-op.
2767 if (DestVT != N.getValueType())
2768 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
2769 DestVT, N)); // convert types.
2771 setValue(&I, N); // noop cast.
2774 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2775 SDValue InVec = getValue(I.getOperand(0));
2776 SDValue InVal = getValue(I.getOperand(1));
2777 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2779 getValue(I.getOperand(2)));
2780 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(),
2781 TLI.getValueType(I.getType()),
2782 InVec, InVal, InIdx));
2785 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2786 SDValue InVec = getValue(I.getOperand(0));
2787 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(),
2789 getValue(I.getOperand(1)));
2790 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2791 TLI.getValueType(I.getType()), InVec, InIdx));
2794 // Utility for visitShuffleVector - Return true if every element in Mask,
2795 // begining from position Pos and ending in Pos+Size, falls within the
2796 // specified sequential range [L, L+Pos). or is undef.
2797 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2798 unsigned Pos, unsigned Size, int Low) {
2799 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2800 if (Mask[i] >= 0 && Mask[i] != Low)
2805 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2806 SDValue Src1 = getValue(I.getOperand(0));
2807 SDValue Src2 = getValue(I.getOperand(1));
2809 SmallVector<int, 8> Mask;
2810 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2811 unsigned MaskNumElts = Mask.size();
2813 EVT VT = TLI.getValueType(I.getType());
2814 EVT SrcVT = Src1.getValueType();
2815 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2817 if (SrcNumElts == MaskNumElts) {
2818 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2823 // Normalize the shuffle vector since mask and vector length don't match.
2824 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2825 // Mask is longer than the source vectors and is a multiple of the source
2826 // vectors. We can use concatenate vector to make the mask and vectors
2828 if (SrcNumElts*2 == MaskNumElts) {
2829 // First check for Src1 in low and Src2 in high
2830 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2831 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2832 // The shuffle is concatenating two vectors together.
2833 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2837 // Then check for Src2 in low and Src1 in high
2838 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2839 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2840 // The shuffle is concatenating two vectors together.
2841 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(),
2847 // Pad both vectors with undefs to make them the same length as the mask.
2848 unsigned NumConcat = MaskNumElts / SrcNumElts;
2849 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2850 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2851 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2853 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2854 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2858 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2859 getCurDebugLoc(), VT,
2860 &MOps1[0], NumConcat);
2861 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2862 getCurDebugLoc(), VT,
2863 &MOps2[0], NumConcat);
2865 // Readjust mask for new input vector length.
2866 SmallVector<int, 8> MappedOps;
2867 for (unsigned i = 0; i != MaskNumElts; ++i) {
2869 if (Idx >= (int)SrcNumElts)
2870 Idx -= SrcNumElts - MaskNumElts;
2871 MappedOps.push_back(Idx);
2874 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2879 if (SrcNumElts > MaskNumElts) {
2880 // Analyze the access pattern of the vector to see if we can extract
2881 // two subvectors and do the shuffle. The analysis is done by calculating
2882 // the range of elements the mask access on both vectors.
2883 int MinRange[2] = { static_cast<int>(SrcNumElts),
2884 static_cast<int>(SrcNumElts)};
2885 int MaxRange[2] = {-1, -1};
2887 for (unsigned i = 0; i != MaskNumElts; ++i) {
2893 if (Idx >= (int)SrcNumElts) {
2897 if (Idx > MaxRange[Input])
2898 MaxRange[Input] = Idx;
2899 if (Idx < MinRange[Input])
2900 MinRange[Input] = Idx;
2903 // Check if the access is smaller than the vector size and can we find
2904 // a reasonable extract index.
2905 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2907 int StartIdx[2]; // StartIdx to extract from
2908 for (unsigned Input = 0; Input < 2; ++Input) {
2909 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2910 RangeUse[Input] = 0; // Unused
2911 StartIdx[Input] = 0;
2915 // Find a good start index that is a multiple of the mask length. Then
2916 // see if the rest of the elements are in range.
2917 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2918 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2919 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2920 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2923 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2924 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2927 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2928 // Extract appropriate subvector and generate a vector shuffle
2929 for (unsigned Input = 0; Input < 2; ++Input) {
2930 SDValue &Src = Input == 0 ? Src1 : Src2;
2931 if (RangeUse[Input] == 0)
2932 Src = DAG.getUNDEF(VT);
2934 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT,
2935 Src, DAG.getIntPtrConstant(StartIdx[Input]));
2938 // Calculate new mask.
2939 SmallVector<int, 8> MappedOps;
2940 for (unsigned i = 0; i != MaskNumElts; ++i) {
2943 if (Idx < (int)SrcNumElts)
2946 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2948 MappedOps.push_back(Idx);
2951 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2,
2957 // We can't use either concat vectors or extract subvectors so fall back to
2958 // replacing the shuffle with extract and build vector.
2959 // to insert and build vector.
2960 EVT EltVT = VT.getVectorElementType();
2961 EVT PtrVT = TLI.getPointerTy();
2962 SmallVector<SDValue,8> Ops;
2963 for (unsigned i = 0; i != MaskNumElts; ++i) {
2968 Res = DAG.getUNDEF(EltVT);
2970 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2971 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2973 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(),
2974 EltVT, Src, DAG.getConstant(Idx, PtrVT));
2980 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(),
2981 VT, &Ops[0], Ops.size()));
2984 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2985 const Value *Op0 = I.getOperand(0);
2986 const Value *Op1 = I.getOperand(1);
2987 Type *AggTy = I.getType();
2988 Type *ValTy = Op1->getType();
2989 bool IntoUndef = isa<UndefValue>(Op0);
2990 bool FromUndef = isa<UndefValue>(Op1);
2992 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2994 SmallVector<EVT, 4> AggValueVTs;
2995 ComputeValueVTs(TLI, AggTy, AggValueVTs);
2996 SmallVector<EVT, 4> ValValueVTs;
2997 ComputeValueVTs(TLI, ValTy, ValValueVTs);
2999 unsigned NumAggValues = AggValueVTs.size();
3000 unsigned NumValValues = ValValueVTs.size();
3001 SmallVector<SDValue, 4> Values(NumAggValues);
3003 SDValue Agg = getValue(Op0);
3005 // Copy the beginning value(s) from the original aggregate.
3006 for (; i != LinearIndex; ++i)
3007 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3008 SDValue(Agg.getNode(), Agg.getResNo() + i);
3009 // Copy values from the inserted value(s).
3011 SDValue Val = getValue(Op1);
3012 for (; i != LinearIndex + NumValValues; ++i)
3013 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3014 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3016 // Copy remaining value(s) from the original aggregate.
3017 for (; i != NumAggValues; ++i)
3018 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3019 SDValue(Agg.getNode(), Agg.getResNo() + i);
3021 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3022 DAG.getVTList(&AggValueVTs[0], NumAggValues),
3023 &Values[0], NumAggValues));
3026 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3027 const Value *Op0 = I.getOperand(0);
3028 Type *AggTy = Op0->getType();
3029 Type *ValTy = I.getType();
3030 bool OutOfUndef = isa<UndefValue>(Op0);
3032 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3034 SmallVector<EVT, 4> ValValueVTs;
3035 ComputeValueVTs(TLI, ValTy, ValValueVTs);
3037 unsigned NumValValues = ValValueVTs.size();
3039 // Ignore a extractvalue that produces an empty object
3040 if (!NumValValues) {
3041 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3045 SmallVector<SDValue, 4> Values(NumValValues);
3047 SDValue Agg = getValue(Op0);
3048 // Copy out the selected value(s).
3049 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3050 Values[i - LinearIndex] =
3052 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3053 SDValue(Agg.getNode(), Agg.getResNo() + i);
3055 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3056 DAG.getVTList(&ValValueVTs[0], NumValValues),
3057 &Values[0], NumValValues));
3060 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3061 SDValue N = getValue(I.getOperand(0));
3062 // Note that the pointer operand may be a vector of pointers. Take the scalar
3063 // element which holds a pointer.
3064 Type *Ty = I.getOperand(0)->getType()->getScalarType();
3066 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3068 const Value *Idx = *OI;
3069 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3070 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
3073 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field);
3074 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3075 DAG.getIntPtrConstant(Offset));
3078 Ty = StTy->getElementType(Field);
3080 Ty = cast<SequentialType>(Ty)->getElementType();
3082 // If this is a constant subscript, handle it quickly.
3083 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3084 if (CI->isZero()) continue;
3086 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3088 EVT PTy = TLI.getPointerTy();
3089 unsigned PtrBits = PTy.getSizeInBits();
3091 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
3093 DAG.getConstant(Offs, MVT::i64));
3095 OffsVal = DAG.getIntPtrConstant(Offs);
3097 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
3102 // N = N + Idx * ElementSize;
3103 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(),
3104 TD->getTypeAllocSize(Ty));
3105 SDValue IdxN = getValue(Idx);
3107 // If the index is smaller or larger than intptr_t, truncate or extend
3109 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType());
3111 // If this is a multiply by a power of two, turn it into a shl
3112 // immediately. This is a very common case.
3113 if (ElementSize != 1) {
3114 if (ElementSize.isPowerOf2()) {
3115 unsigned Amt = ElementSize.logBase2();
3116 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(),
3117 N.getValueType(), IdxN,
3118 DAG.getConstant(Amt, IdxN.getValueType()));
3120 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy());
3121 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(),
3122 N.getValueType(), IdxN, Scale);
3126 N = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3127 N.getValueType(), N, IdxN);
3134 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3135 // If this is a fixed sized alloca in the entry block of the function,
3136 // allocate it statically on the stack.
3137 if (FuncInfo.StaticAllocaMap.count(&I))
3138 return; // getValue will auto-populate this.
3140 Type *Ty = I.getAllocatedType();
3141 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
3143 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty),
3146 SDValue AllocSize = getValue(I.getArraySize());
3148 EVT IntPtr = TLI.getPointerTy();
3149 if (AllocSize.getValueType() != IntPtr)
3150 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr);
3152 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr,
3154 DAG.getConstant(TySize, IntPtr));
3156 // Handle alignment. If the requested alignment is less than or equal to
3157 // the stack alignment, ignore it. If the size is greater than or equal to
3158 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3159 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3160 if (Align <= StackAlign)
3163 // Round the size of the allocation up to the stack alignment size
3164 // by add SA-1 to the size.
3165 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3166 AllocSize.getValueType(), AllocSize,
3167 DAG.getIntPtrConstant(StackAlign-1));
3169 // Mask out the low bits for alignment purposes.
3170 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(),
3171 AllocSize.getValueType(), AllocSize,
3172 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3174 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3175 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3176 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
3179 DAG.setRoot(DSA.getValue(1));
3181 // Inform the Frame Information that we have just allocated a variable-sized
3183 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1);
3186 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3188 return visitAtomicLoad(I);
3190 const Value *SV = I.getOperand(0);
3191 SDValue Ptr = getValue(SV);
3193 Type *Ty = I.getType();
3195 bool isVolatile = I.isVolatile();
3196 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3197 bool isInvariant = I.getMetadata("invariant.load") != 0;
3198 unsigned Alignment = I.getAlignment();
3199 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3200 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3202 SmallVector<EVT, 4> ValueVTs;
3203 SmallVector<uint64_t, 4> Offsets;
3204 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
3205 unsigned NumValues = ValueVTs.size();
3210 bool ConstantMemory = false;
3211 if (I.isVolatile() || NumValues > MaxParallelChains)
3212 // Serialize volatile loads with other side effects.
3214 else if (AA->pointsToConstantMemory(
3215 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3216 // Do not serialize (non-volatile) loads of constant memory with anything.
3217 Root = DAG.getEntryNode();
3218 ConstantMemory = true;
3220 // Do not serialize non-volatile loads against each other.
3221 Root = DAG.getRoot();
3224 SmallVector<SDValue, 4> Values(NumValues);
3225 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3227 EVT PtrVT = Ptr.getValueType();
3228 unsigned ChainI = 0;
3229 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3230 // Serializing loads here may result in excessive register pressure, and
3231 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3232 // could recover a bit by hoisting nodes upward in the chain by recognizing
3233 // they are side-effect free or do not alias. The optimizer should really
3234 // avoid this case by converting large object/array copies to llvm.memcpy
3235 // (MaxParallelChains should always remain as failsafe).
3236 if (ChainI == MaxParallelChains) {
3237 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3238 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3239 MVT::Other, &Chains[0], ChainI);
3243 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(),
3245 DAG.getConstant(Offsets[i], PtrVT));
3246 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
3247 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3248 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3252 Chains[ChainI] = L.getValue(1);
3255 if (!ConstantMemory) {
3256 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3257 MVT::Other, &Chains[0], ChainI);
3261 PendingLoads.push_back(Chain);
3264 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
3265 DAG.getVTList(&ValueVTs[0], NumValues),
3266 &Values[0], NumValues));
3269 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3271 return visitAtomicStore(I);
3273 const Value *SrcV = I.getOperand(0);
3274 const Value *PtrV = I.getOperand(1);
3276 SmallVector<EVT, 4> ValueVTs;
3277 SmallVector<uint64_t, 4> Offsets;
3278 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
3279 unsigned NumValues = ValueVTs.size();
3283 // Get the lowered operands. Note that we do this after
3284 // checking if NumResults is zero, because with zero results
3285 // the operands won't have values in the map.
3286 SDValue Src = getValue(SrcV);
3287 SDValue Ptr = getValue(PtrV);
3289 SDValue Root = getRoot();
3290 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3292 EVT PtrVT = Ptr.getValueType();
3293 bool isVolatile = I.isVolatile();
3294 bool isNonTemporal = I.getMetadata("nontemporal") != 0;
3295 unsigned Alignment = I.getAlignment();
3296 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3298 unsigned ChainI = 0;
3299 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3300 // See visitLoad comments.
3301 if (ChainI == MaxParallelChains) {
3302 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3303 MVT::Other, &Chains[0], ChainI);
3307 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr,
3308 DAG.getConstant(Offsets[i], PtrVT));
3309 SDValue St = DAG.getStore(Root, getCurDebugLoc(),
3310 SDValue(Src.getNode(), Src.getResNo() + i),
3311 Add, MachinePointerInfo(PtrV, Offsets[i]),
3312 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3313 Chains[ChainI] = St;
3316 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
3317 MVT::Other, &Chains[0], ChainI);
3319 AssignOrderingToNode(StoreNode.getNode());
3320 DAG.setRoot(StoreNode);
3323 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3324 SynchronizationScope Scope,
3325 bool Before, DebugLoc dl,
3327 const TargetLowering &TLI) {
3328 // Fence, if necessary
3330 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3332 else if (Order == Acquire || Order == Monotonic)
3335 if (Order == AcquireRelease)
3337 else if (Order == Release || Order == Monotonic)
3342 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3343 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3344 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3347 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3348 DebugLoc dl = getCurDebugLoc();
3349 AtomicOrdering Order = I.getOrdering();
3350 SynchronizationScope Scope = I.getSynchScope();
3352 SDValue InChain = getRoot();
3354 if (TLI.getInsertFencesForAtomic())
3355 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3359 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3360 getValue(I.getCompareOperand()).getValueType().getSimpleVT(),
3362 getValue(I.getPointerOperand()),
3363 getValue(I.getCompareOperand()),
3364 getValue(I.getNewValOperand()),
3365 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3366 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3369 SDValue OutChain = L.getValue(1);
3371 if (TLI.getInsertFencesForAtomic())
3372 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3376 DAG.setRoot(OutChain);
3379 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3380 DebugLoc dl = getCurDebugLoc();
3382 switch (I.getOperation()) {
3383 default: llvm_unreachable("Unknown atomicrmw operation");
3384 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3385 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3386 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3387 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3388 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3389 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3390 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3391 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3392 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3393 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3394 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3396 AtomicOrdering Order = I.getOrdering();
3397 SynchronizationScope Scope = I.getSynchScope();
3399 SDValue InChain = getRoot();
3401 if (TLI.getInsertFencesForAtomic())
3402 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3406 DAG.getAtomic(NT, dl,
3407 getValue(I.getValOperand()).getValueType().getSimpleVT(),
3409 getValue(I.getPointerOperand()),
3410 getValue(I.getValOperand()),
3411 I.getPointerOperand(), 0 /* Alignment */,
3412 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3415 SDValue OutChain = L.getValue(1);
3417 if (TLI.getInsertFencesForAtomic())
3418 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3422 DAG.setRoot(OutChain);
3425 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3426 DebugLoc dl = getCurDebugLoc();
3429 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy());
3430 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy());
3431 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3434 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3435 DebugLoc dl = getCurDebugLoc();
3436 AtomicOrdering Order = I.getOrdering();
3437 SynchronizationScope Scope = I.getSynchScope();
3439 SDValue InChain = getRoot();
3441 EVT VT = EVT::getEVT(I.getType());
3443 if (I.getAlignment() * 8 < VT.getSizeInBits())
3444 report_fatal_error("Cannot generate unaligned atomic load");
3447 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3448 getValue(I.getPointerOperand()),
3449 I.getPointerOperand(), I.getAlignment(),
3450 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3453 SDValue OutChain = L.getValue(1);
3455 if (TLI.getInsertFencesForAtomic())
3456 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3460 DAG.setRoot(OutChain);
3463 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3464 DebugLoc dl = getCurDebugLoc();
3466 AtomicOrdering Order = I.getOrdering();
3467 SynchronizationScope Scope = I.getSynchScope();
3469 SDValue InChain = getRoot();
3471 EVT VT = EVT::getEVT(I.getValueOperand()->getType());
3473 if (I.getAlignment() * 8 < VT.getSizeInBits())
3474 report_fatal_error("Cannot generate unaligned atomic store");
3476 if (TLI.getInsertFencesForAtomic())
3477 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3481 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3483 getValue(I.getPointerOperand()),
3484 getValue(I.getValueOperand()),
3485 I.getPointerOperand(), I.getAlignment(),
3486 TLI.getInsertFencesForAtomic() ? Monotonic : Order,
3489 if (TLI.getInsertFencesForAtomic())
3490 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3493 DAG.setRoot(OutChain);
3496 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3498 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3499 unsigned Intrinsic) {
3500 bool HasChain = !I.doesNotAccessMemory();
3501 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3503 // Build the operand list.
3504 SmallVector<SDValue, 8> Ops;
3505 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3507 // We don't need to serialize loads against other loads.
3508 Ops.push_back(DAG.getRoot());
3510 Ops.push_back(getRoot());
3514 // Info is set by getTgtMemInstrinsic
3515 TargetLowering::IntrinsicInfo Info;
3516 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3518 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3519 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3520 Info.opc == ISD::INTRINSIC_W_CHAIN)
3521 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI.getPointerTy()));
3523 // Add all operands of the call to the operand list.
3524 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3525 SDValue Op = getValue(I.getArgOperand(i));
3529 SmallVector<EVT, 4> ValueVTs;
3530 ComputeValueVTs(TLI, I.getType(), ValueVTs);
3533 ValueVTs.push_back(MVT::Other);
3535 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
3539 if (IsTgtIntrinsic) {
3540 // This is target intrinsic that touches memory
3541 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(),
3542 VTs, &Ops[0], Ops.size(),
3544 MachinePointerInfo(Info.ptrVal, Info.offset),
3545 Info.align, Info.vol,
3546 Info.readMem, Info.writeMem);
3547 } else if (!HasChain) {
3548 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(),
3549 VTs, &Ops[0], Ops.size());
3550 } else if (!I.getType()->isVoidTy()) {
3551 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(),
3552 VTs, &Ops[0], Ops.size());
3554 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(),
3555 VTs, &Ops[0], Ops.size());
3559 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3561 PendingLoads.push_back(Chain);
3566 if (!I.getType()->isVoidTy()) {
3567 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3568 EVT VT = TLI.getValueType(PTy);
3569 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result);
3572 setValue(&I, Result);
3574 // Assign order to result here. If the intrinsic does not produce a result,
3575 // it won't be mapped to a SDNode and visit() will not assign it an order
3578 AssignOrderingToNode(Result.getNode());
3582 /// GetSignificand - Get the significand and build it into a floating-point
3583 /// number with exponent of 1:
3585 /// Op = (Op & 0x007fffff) | 0x3f800000;
3587 /// where Op is the hexidecimal representation of floating point value.
3589 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
3590 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3591 DAG.getConstant(0x007fffff, MVT::i32));
3592 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3593 DAG.getConstant(0x3f800000, MVT::i32));
3594 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3597 /// GetExponent - Get the exponent:
3599 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3601 /// where Op is the hexidecimal representation of floating point value.
3603 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3605 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3606 DAG.getConstant(0x7f800000, MVT::i32));
3607 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3608 DAG.getConstant(23, TLI.getPointerTy()));
3609 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3610 DAG.getConstant(127, MVT::i32));
3611 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3614 /// getF32Constant - Get 32-bit floating point constant.
3616 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3617 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
3620 /// visitExp - Lower an exp intrinsic. Handles the special sequences for
3621 /// limited-precision mode.
3623 SelectionDAGBuilder::visitExp(const CallInst &I) {
3625 DebugLoc dl = getCurDebugLoc();
3627 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3628 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3629 SDValue Op = getValue(I.getArgOperand(0));
3631 // Put the exponent in the right bit position for later addition to the
3634 // #define LOG2OFe 1.4426950f
3635 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3636 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3637 getF32Constant(DAG, 0x3fb8aa3b));
3638 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3640 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3641 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3642 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3644 // IntegerPartOfX <<= 23;
3645 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3646 DAG.getConstant(23, TLI.getPointerTy()));
3648 if (LimitFloatPrecision <= 6) {
3649 // For floating-point precision of 6:
3651 // TwoToFractionalPartOfX =
3653 // (0.735607626f + 0.252464424f * x) * x;
3655 // error 0.0144103317, which is 6 bits
3656 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3657 getF32Constant(DAG, 0x3e814304));
3658 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3659 getF32Constant(DAG, 0x3f3c50c8));
3660 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3661 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3662 getF32Constant(DAG, 0x3f7f5e7e));
3663 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5);
3665 // Add the exponent into the result in integer domain.
3666 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3667 TwoToFracPartOfX, IntegerPartOfX);
3669 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6);
3670 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3671 // For floating-point precision of 12:
3673 // TwoToFractionalPartOfX =
3676 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3678 // 0.000107046256 error, which is 13 to 14 bits
3679 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3680 getF32Constant(DAG, 0x3da235e3));
3681 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3682 getF32Constant(DAG, 0x3e65b8f3));
3683 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3684 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3685 getF32Constant(DAG, 0x3f324b07));
3686 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3687 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3688 getF32Constant(DAG, 0x3f7ff8fd));
3689 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7);
3691 // Add the exponent into the result in integer domain.
3692 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3693 TwoToFracPartOfX, IntegerPartOfX);
3695 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8);
3696 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3697 // For floating-point precision of 18:
3699 // TwoToFractionalPartOfX =
3703 // (0.554906021e-1f +
3704 // (0.961591928e-2f +
3705 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3707 // error 2.47208000*10^(-7), which is better than 18 bits
3708 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3709 getF32Constant(DAG, 0x3924b03e));
3710 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3711 getF32Constant(DAG, 0x3ab24b87));
3712 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3713 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3714 getF32Constant(DAG, 0x3c1d8c17));
3715 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3716 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3717 getF32Constant(DAG, 0x3d634a1d));
3718 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3719 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3720 getF32Constant(DAG, 0x3e75fe14));
3721 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3722 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3723 getF32Constant(DAG, 0x3f317234));
3724 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3725 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3726 getF32Constant(DAG, 0x3f800000));
3727 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,
3730 // Add the exponent into the result in integer domain.
3731 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
3732 TwoToFracPartOfX, IntegerPartOfX);
3734 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14);
3737 // No special expansion.
3738 result = DAG.getNode(ISD::FEXP, dl,
3739 getValue(I.getArgOperand(0)).getValueType(),
3740 getValue(I.getArgOperand(0)));
3743 setValue(&I, result);
3746 /// visitLog - Lower a log intrinsic. Handles the special sequences for
3747 /// limited-precision mode.
3749 SelectionDAGBuilder::visitLog(const CallInst &I) {
3751 DebugLoc dl = getCurDebugLoc();
3753 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3754 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3755 SDValue Op = getValue(I.getArgOperand(0));
3756 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3758 // Scale the exponent by log(2) [0.69314718f].
3759 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3760 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3761 getF32Constant(DAG, 0x3f317218));
3763 // Get the significand and build it into a floating-point number with
3765 SDValue X = GetSignificand(DAG, Op1, dl);
3767 if (LimitFloatPrecision <= 6) {
3768 // For floating-point precision of 6:
3772 // (1.4034025f - 0.23903021f * x) * x;
3774 // error 0.0034276066, which is better than 8 bits
3775 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3776 getF32Constant(DAG, 0xbe74c456));
3777 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3778 getF32Constant(DAG, 0x3fb3a2b1));
3779 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3780 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3781 getF32Constant(DAG, 0x3f949a29));
3783 result = DAG.getNode(ISD::FADD, dl,
3784 MVT::f32, LogOfExponent, LogOfMantissa);
3785 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3786 // For floating-point precision of 12:
3792 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3794 // error 0.000061011436, which is 14 bits
3795 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3796 getF32Constant(DAG, 0xbd67b6d6));
3797 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3798 getF32Constant(DAG, 0x3ee4f4b8));
3799 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3800 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3801 getF32Constant(DAG, 0x3fbc278b));
3802 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3803 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3804 getF32Constant(DAG, 0x40348e95));
3805 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3806 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3807 getF32Constant(DAG, 0x3fdef31a));
3809 result = DAG.getNode(ISD::FADD, dl,
3810 MVT::f32, LogOfExponent, LogOfMantissa);
3811 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3812 // For floating-point precision of 18:
3820 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3822 // error 0.0000023660568, which is better than 18 bits
3823 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3824 getF32Constant(DAG, 0xbc91e5ac));
3825 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3826 getF32Constant(DAG, 0x3e4350aa));
3827 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3828 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3829 getF32Constant(DAG, 0x3f60d3e3));
3830 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3831 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3832 getF32Constant(DAG, 0x4011cdf0));
3833 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3834 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3835 getF32Constant(DAG, 0x406cfd1c));
3836 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3837 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3838 getF32Constant(DAG, 0x408797cb));
3839 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3840 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3841 getF32Constant(DAG, 0x4006dcab));
3843 result = DAG.getNode(ISD::FADD, dl,
3844 MVT::f32, LogOfExponent, LogOfMantissa);
3847 // No special expansion.
3848 result = DAG.getNode(ISD::FLOG, dl,
3849 getValue(I.getArgOperand(0)).getValueType(),
3850 getValue(I.getArgOperand(0)));
3853 setValue(&I, result);
3856 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for
3857 /// limited-precision mode.
3859 SelectionDAGBuilder::visitLog2(const CallInst &I) {
3861 DebugLoc dl = getCurDebugLoc();
3863 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3864 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3865 SDValue Op = getValue(I.getArgOperand(0));
3866 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3868 // Get the exponent.
3869 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3871 // Get the significand and build it into a floating-point number with
3873 SDValue X = GetSignificand(DAG, Op1, dl);
3875 // Different possible minimax approximations of significand in
3876 // floating-point for various degrees of accuracy over [1,2].
3877 if (LimitFloatPrecision <= 6) {
3878 // For floating-point precision of 6:
3880 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3882 // error 0.0049451742, which is more than 7 bits
3883 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3884 getF32Constant(DAG, 0xbeb08fe0));
3885 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3886 getF32Constant(DAG, 0x40019463));
3887 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3888 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3889 getF32Constant(DAG, 0x3fd6633d));
3891 result = DAG.getNode(ISD::FADD, dl,
3892 MVT::f32, LogOfExponent, Log2ofMantissa);
3893 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
3894 // For floating-point precision of 12:
3900 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3902 // error 0.0000876136000, which is better than 13 bits
3903 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3904 getF32Constant(DAG, 0xbda7262e));
3905 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3906 getF32Constant(DAG, 0x3f25280b));
3907 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3908 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3909 getF32Constant(DAG, 0x4007b923));
3910 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3911 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3912 getF32Constant(DAG, 0x40823e2f));
3913 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3914 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3915 getF32Constant(DAG, 0x4020d29c));
3917 result = DAG.getNode(ISD::FADD, dl,
3918 MVT::f32, LogOfExponent, Log2ofMantissa);
3919 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
3920 // For floating-point precision of 18:
3929 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
3931 // error 0.0000018516, which is better than 18 bits
3932 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3933 getF32Constant(DAG, 0xbcd2769e));
3934 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3935 getF32Constant(DAG, 0x3e8ce0b9));
3936 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3937 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3938 getF32Constant(DAG, 0x3fa22ae7));
3939 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3940 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3941 getF32Constant(DAG, 0x40525723));
3942 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3943 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3944 getF32Constant(DAG, 0x40aaf200));
3945 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3946 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3947 getF32Constant(DAG, 0x40c39dad));
3948 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3949 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3950 getF32Constant(DAG, 0x4042902c));
3952 result = DAG.getNode(ISD::FADD, dl,
3953 MVT::f32, LogOfExponent, Log2ofMantissa);
3956 // No special expansion.
3957 result = DAG.getNode(ISD::FLOG2, dl,
3958 getValue(I.getArgOperand(0)).getValueType(),
3959 getValue(I.getArgOperand(0)));
3962 setValue(&I, result);
3965 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for
3966 /// limited-precision mode.
3968 SelectionDAGBuilder::visitLog10(const CallInst &I) {
3970 DebugLoc dl = getCurDebugLoc();
3972 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
3973 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3974 SDValue Op = getValue(I.getArgOperand(0));
3975 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3977 // Scale the exponent by log10(2) [0.30102999f].
3978 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3979 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3980 getF32Constant(DAG, 0x3e9a209a));
3982 // Get the significand and build it into a floating-point number with
3984 SDValue X = GetSignificand(DAG, Op1, dl);
3986 if (LimitFloatPrecision <= 6) {
3987 // For floating-point precision of 6:
3989 // Log10ofMantissa =
3991 // (0.60948995f - 0.10380950f * x) * x;
3993 // error 0.0014886165, which is 6 bits
3994 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3995 getF32Constant(DAG, 0xbdd49a13));
3996 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3997 getF32Constant(DAG, 0x3f1c0789));
3998 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3999 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4000 getF32Constant(DAG, 0x3f011300));
4002 result = DAG.getNode(ISD::FADD, dl,
4003 MVT::f32, LogOfExponent, Log10ofMantissa);
4004 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4005 // For floating-point precision of 12:
4007 // Log10ofMantissa =
4010 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4012 // error 0.00019228036, which is better than 12 bits
4013 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4014 getF32Constant(DAG, 0x3d431f31));
4015 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4016 getF32Constant(DAG, 0x3ea21fb2));
4017 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4018 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4019 getF32Constant(DAG, 0x3f6ae232));
4020 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4021 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4022 getF32Constant(DAG, 0x3f25f7c3));
4024 result = DAG.getNode(ISD::FADD, dl,
4025 MVT::f32, LogOfExponent, Log10ofMantissa);
4026 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4027 // For floating-point precision of 18:
4029 // Log10ofMantissa =
4034 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4036 // error 0.0000037995730, which is better than 18 bits
4037 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4038 getF32Constant(DAG, 0x3c5d51ce));
4039 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4040 getF32Constant(DAG, 0x3e00685a));
4041 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4042 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4043 getF32Constant(DAG, 0x3efb6798));
4044 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4045 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4046 getF32Constant(DAG, 0x3f88d192));
4047 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4048 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4049 getF32Constant(DAG, 0x3fc4316c));
4050 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4051 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4052 getF32Constant(DAG, 0x3f57ce70));
4054 result = DAG.getNode(ISD::FADD, dl,
4055 MVT::f32, LogOfExponent, Log10ofMantissa);
4058 // No special expansion.
4059 result = DAG.getNode(ISD::FLOG10, dl,
4060 getValue(I.getArgOperand(0)).getValueType(),
4061 getValue(I.getArgOperand(0)));
4064 setValue(&I, result);
4067 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4068 /// limited-precision mode.
4070 SelectionDAGBuilder::visitExp2(const CallInst &I) {
4072 DebugLoc dl = getCurDebugLoc();
4074 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 &&
4075 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4076 SDValue Op = getValue(I.getArgOperand(0));
4078 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4080 // FractionalPartOfX = x - (float)IntegerPartOfX;
4081 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4082 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4084 // IntegerPartOfX <<= 23;
4085 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4086 DAG.getConstant(23, TLI.getPointerTy()));
4088 if (LimitFloatPrecision <= 6) {
4089 // For floating-point precision of 6:
4091 // TwoToFractionalPartOfX =
4093 // (0.735607626f + 0.252464424f * x) * x;
4095 // error 0.0144103317, which is 6 bits
4096 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4097 getF32Constant(DAG, 0x3e814304));
4098 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4099 getF32Constant(DAG, 0x3f3c50c8));
4100 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4101 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4102 getF32Constant(DAG, 0x3f7f5e7e));
4103 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4104 SDValue TwoToFractionalPartOfX =
4105 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4107 result = DAG.getNode(ISD::BITCAST, dl,
4108 MVT::f32, TwoToFractionalPartOfX);
4109 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4110 // For floating-point precision of 12:
4112 // TwoToFractionalPartOfX =
4115 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4117 // error 0.000107046256, which is 13 to 14 bits
4118 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4119 getF32Constant(DAG, 0x3da235e3));
4120 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4121 getF32Constant(DAG, 0x3e65b8f3));
4122 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4123 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4124 getF32Constant(DAG, 0x3f324b07));
4125 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4126 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4127 getF32Constant(DAG, 0x3f7ff8fd));
4128 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4129 SDValue TwoToFractionalPartOfX =
4130 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4132 result = DAG.getNode(ISD::BITCAST, dl,
4133 MVT::f32, TwoToFractionalPartOfX);
4134 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4135 // For floating-point precision of 18:
4137 // TwoToFractionalPartOfX =
4141 // (0.554906021e-1f +
4142 // (0.961591928e-2f +
4143 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4144 // error 2.47208000*10^(-7), which is better than 18 bits
4145 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4146 getF32Constant(DAG, 0x3924b03e));
4147 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4148 getF32Constant(DAG, 0x3ab24b87));
4149 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4150 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4151 getF32Constant(DAG, 0x3c1d8c17));
4152 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4153 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4154 getF32Constant(DAG, 0x3d634a1d));
4155 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4156 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4157 getF32Constant(DAG, 0x3e75fe14));
4158 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4159 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4160 getF32Constant(DAG, 0x3f317234));
4161 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4162 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4163 getF32Constant(DAG, 0x3f800000));
4164 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4165 SDValue TwoToFractionalPartOfX =
4166 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4168 result = DAG.getNode(ISD::BITCAST, dl,
4169 MVT::f32, TwoToFractionalPartOfX);
4172 // No special expansion.
4173 result = DAG.getNode(ISD::FEXP2, dl,
4174 getValue(I.getArgOperand(0)).getValueType(),
4175 getValue(I.getArgOperand(0)));
4178 setValue(&I, result);
4181 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4182 /// limited-precision mode with x == 10.0f.
4184 SelectionDAGBuilder::visitPow(const CallInst &I) {
4186 const Value *Val = I.getArgOperand(0);
4187 DebugLoc dl = getCurDebugLoc();
4188 bool IsExp10 = false;
4190 if (getValue(Val).getValueType() == MVT::f32 &&
4191 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 &&
4192 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4193 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
4194 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
4196 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten);
4201 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4202 SDValue Op = getValue(I.getArgOperand(1));
4204 // Put the exponent in the right bit position for later addition to the
4207 // #define LOG2OF10 3.3219281f
4208 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4209 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
4210 getF32Constant(DAG, 0x40549a78));
4211 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4213 // FractionalPartOfX = x - (float)IntegerPartOfX;
4214 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4215 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4217 // IntegerPartOfX <<= 23;
4218 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4219 DAG.getConstant(23, TLI.getPointerTy()));
4221 if (LimitFloatPrecision <= 6) {
4222 // For floating-point precision of 6:
4224 // twoToFractionalPartOfX =
4226 // (0.735607626f + 0.252464424f * x) * x;
4228 // error 0.0144103317, which is 6 bits
4229 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4230 getF32Constant(DAG, 0x3e814304));
4231 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4232 getF32Constant(DAG, 0x3f3c50c8));
4233 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4234 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4235 getF32Constant(DAG, 0x3f7f5e7e));
4236 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5);
4237 SDValue TwoToFractionalPartOfX =
4238 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
4240 result = DAG.getNode(ISD::BITCAST, dl,
4241 MVT::f32, TwoToFractionalPartOfX);
4242 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
4243 // For floating-point precision of 12:
4245 // TwoToFractionalPartOfX =
4248 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4250 // error 0.000107046256, which is 13 to 14 bits
4251 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4252 getF32Constant(DAG, 0x3da235e3));
4253 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4254 getF32Constant(DAG, 0x3e65b8f3));
4255 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4256 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4257 getF32Constant(DAG, 0x3f324b07));
4258 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4259 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4260 getF32Constant(DAG, 0x3f7ff8fd));
4261 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7);
4262 SDValue TwoToFractionalPartOfX =
4263 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
4265 result = DAG.getNode(ISD::BITCAST, dl,
4266 MVT::f32, TwoToFractionalPartOfX);
4267 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
4268 // For floating-point precision of 18:
4270 // TwoToFractionalPartOfX =
4274 // (0.554906021e-1f +
4275 // (0.961591928e-2f +
4276 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4277 // error 2.47208000*10^(-7), which is better than 18 bits
4278 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4279 getF32Constant(DAG, 0x3924b03e));
4280 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4281 getF32Constant(DAG, 0x3ab24b87));
4282 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4283 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4284 getF32Constant(DAG, 0x3c1d8c17));
4285 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4286 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4287 getF32Constant(DAG, 0x3d634a1d));
4288 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4289 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4290 getF32Constant(DAG, 0x3e75fe14));
4291 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4292 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4293 getF32Constant(DAG, 0x3f317234));
4294 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4295 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4296 getF32Constant(DAG, 0x3f800000));
4297 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13);
4298 SDValue TwoToFractionalPartOfX =
4299 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
4301 result = DAG.getNode(ISD::BITCAST, dl,
4302 MVT::f32, TwoToFractionalPartOfX);
4305 // No special expansion.
4306 result = DAG.getNode(ISD::FPOW, dl,
4307 getValue(I.getArgOperand(0)).getValueType(),
4308 getValue(I.getArgOperand(0)),
4309 getValue(I.getArgOperand(1)));
4312 setValue(&I, result);
4316 /// ExpandPowI - Expand a llvm.powi intrinsic.
4317 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS,
4318 SelectionDAG &DAG) {
4319 // If RHS is a constant, we can expand this out to a multiplication tree,
4320 // otherwise we end up lowering to a call to __powidf2 (for example). When
4321 // optimizing for size, we only want to do this if the expansion would produce
4322 // a small number of multiplies, otherwise we do the full expansion.
4323 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4324 // Get the exponent as a positive value.
4325 unsigned Val = RHSC->getSExtValue();
4326 if ((int)Val < 0) Val = -Val;
4328 // powi(x, 0) -> 1.0
4330 return DAG.getConstantFP(1.0, LHS.getValueType());
4332 const Function *F = DAG.getMachineFunction().getFunction();
4333 if (!F->hasFnAttr(Attribute::OptimizeForSize) ||
4334 // If optimizing for size, don't insert too many multiplies. This
4335 // inserts up to 5 multiplies.
4336 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4337 // We use the simple binary decomposition method to generate the multiply
4338 // sequence. There are more optimal ways to do this (for example,
4339 // powi(x,15) generates one more multiply than it should), but this has
4340 // the benefit of being both really simple and much better than a libcall.
4341 SDValue Res; // Logically starts equal to 1.0
4342 SDValue CurSquare = LHS;
4346 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4348 Res = CurSquare; // 1.0*CurSquare.
4351 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4352 CurSquare, CurSquare);
4356 // If the original was negative, invert the result, producing 1/(x*x*x).
4357 if (RHSC->getSExtValue() < 0)
4358 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4359 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4364 // Otherwise, expand to a libcall.
4365 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4368 // getTruncatedArgReg - Find underlying register used for an truncated
4370 static unsigned getTruncatedArgReg(const SDValue &N) {
4371 if (N.getOpcode() != ISD::TRUNCATE)
4374 const SDValue &Ext = N.getOperand(0);
4375 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
4376 const SDValue &CFR = Ext.getOperand(0);
4377 if (CFR.getOpcode() == ISD::CopyFromReg)
4378 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4379 if (CFR.getOpcode() == ISD::TRUNCATE)
4380 return getTruncatedArgReg(CFR);
4385 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4386 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4387 /// At the end of instruction selection, they will be inserted to the entry BB.
4389 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4392 const Argument *Arg = dyn_cast<Argument>(V);
4396 MachineFunction &MF = DAG.getMachineFunction();
4397 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4398 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo();
4400 // Ignore inlined function arguments here.
4401 DIVariable DV(Variable);
4402 if (DV.isInlinedFnArgument(MF.getFunction()))
4406 // Some arguments' frame index is recorded during argument lowering.
4407 Offset = FuncInfo.getArgumentFrameIndex(Arg);
4409 Reg = TRI->getFrameRegister(MF);
4411 if (!Reg && N.getNode()) {
4412 if (N.getOpcode() == ISD::CopyFromReg)
4413 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4415 Reg = getTruncatedArgReg(N);
4416 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4417 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4418 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4425 // Check if ValueMap has reg number.
4426 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4427 if (VMI != FuncInfo.ValueMap.end())
4431 if (!Reg && N.getNode()) {
4432 // Check if frame index is available.
4433 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4434 if (FrameIndexSDNode *FINode =
4435 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) {
4436 Reg = TRI->getFrameRegister(MF);
4437 Offset = FINode->getIndex();
4444 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(),
4445 TII->get(TargetOpcode::DBG_VALUE))
4446 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable);
4447 FuncInfo.ArgDbgValues.push_back(&*MIB);
4451 // VisualStudio defines setjmp as _setjmp
4452 #if defined(_MSC_VER) && defined(setjmp) && \
4453 !defined(setjmp_undefined_for_msvc)
4454 # pragma push_macro("setjmp")
4456 # define setjmp_undefined_for_msvc
4459 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4460 /// we want to emit this as a call to a named external function, return the name
4461 /// otherwise lower it and return null.
4463 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4464 DebugLoc dl = getCurDebugLoc();
4467 switch (Intrinsic) {
4469 // By default, turn this into a target intrinsic node.
4470 visitTargetIntrinsic(I, Intrinsic);
4472 case Intrinsic::vastart: visitVAStart(I); return 0;
4473 case Intrinsic::vaend: visitVAEnd(I); return 0;
4474 case Intrinsic::vacopy: visitVACopy(I); return 0;
4475 case Intrinsic::returnaddress:
4476 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(),
4477 getValue(I.getArgOperand(0))));
4479 case Intrinsic::frameaddress:
4480 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(),
4481 getValue(I.getArgOperand(0))));
4483 case Intrinsic::setjmp:
4484 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4485 case Intrinsic::longjmp:
4486 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4487 case Intrinsic::memcpy: {
4488 // Assert for address < 256 since we support only user defined address
4490 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4492 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4494 "Unknown address space");
4495 SDValue Op1 = getValue(I.getArgOperand(0));
4496 SDValue Op2 = getValue(I.getArgOperand(1));
4497 SDValue Op3 = getValue(I.getArgOperand(2));
4498 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4499 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4500 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false,
4501 MachinePointerInfo(I.getArgOperand(0)),
4502 MachinePointerInfo(I.getArgOperand(1))));
4505 case Intrinsic::memset: {
4506 // Assert for address < 256 since we support only user defined address
4508 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4510 "Unknown address space");
4511 SDValue Op1 = getValue(I.getArgOperand(0));
4512 SDValue Op2 = getValue(I.getArgOperand(1));
4513 SDValue Op3 = getValue(I.getArgOperand(2));
4514 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4515 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4516 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4517 MachinePointerInfo(I.getArgOperand(0))));
4520 case Intrinsic::memmove: {
4521 // Assert for address < 256 since we support only user defined address
4523 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4525 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4527 "Unknown address space");
4528 SDValue Op1 = getValue(I.getArgOperand(0));
4529 SDValue Op2 = getValue(I.getArgOperand(1));
4530 SDValue Op3 = getValue(I.getArgOperand(2));
4531 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4532 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4533 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol,
4534 MachinePointerInfo(I.getArgOperand(0)),
4535 MachinePointerInfo(I.getArgOperand(1))));
4538 case Intrinsic::dbg_declare: {
4539 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4540 MDNode *Variable = DI.getVariable();
4541 const Value *Address = DI.getAddress();
4542 if (!Address || !DIVariable(Variable).Verify()) {
4543 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4547 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4548 // but do not always have a corresponding SDNode built. The SDNodeOrder
4549 // absolute, but not relative, values are different depending on whether
4550 // debug info exists.
4553 // Check if address has undef value.
4554 if (isa<UndefValue>(Address) ||
4555 (Address->use_empty() && !isa<Argument>(Address))) {
4556 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4560 SDValue &N = NodeMap[Address];
4561 if (!N.getNode() && isa<Argument>(Address))
4562 // Check unused arguments map.
4563 N = UnusedArgNodeMap[Address];
4566 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4567 Address = BCI->getOperand(0);
4568 // Parameters are handled specially.
4570 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4571 isa<Argument>(Address));
4573 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4575 if (isParameter && !AI) {
4576 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4578 // Byval parameter. We have a frame index at this point.
4579 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4580 0, dl, SDNodeOrder);
4582 // Address is an argument, so try to emit its dbg value using
4583 // virtual register info from the FuncInfo.ValueMap.
4584 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4588 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4589 0, dl, SDNodeOrder);
4591 // Can't do anything with other non-AI cases yet.
4592 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4593 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4594 DEBUG(Address->dump());
4597 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4599 // If Address is an argument then try to emit its dbg value using
4600 // virtual register info from the FuncInfo.ValueMap.
4601 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4602 // If variable is pinned by a alloca in dominating bb then
4603 // use StaticAllocaMap.
4604 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4605 if (AI->getParent() != DI.getParent()) {
4606 DenseMap<const AllocaInst*, int>::iterator SI =
4607 FuncInfo.StaticAllocaMap.find(AI);
4608 if (SI != FuncInfo.StaticAllocaMap.end()) {
4609 SDV = DAG.getDbgValue(Variable, SI->second,
4610 0, dl, SDNodeOrder);
4611 DAG.AddDbgValue(SDV, 0, false);
4616 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4621 case Intrinsic::dbg_value: {
4622 const DbgValueInst &DI = cast<DbgValueInst>(I);
4623 if (!DIVariable(DI.getVariable()).Verify())
4626 MDNode *Variable = DI.getVariable();
4627 uint64_t Offset = DI.getOffset();
4628 const Value *V = DI.getValue();
4632 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
4633 // but do not always have a corresponding SDNode built. The SDNodeOrder
4634 // absolute, but not relative, values are different depending on whether
4635 // debug info exists.
4638 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4639 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4640 DAG.AddDbgValue(SDV, 0, false);
4642 // Do not use getValue() in here; we don't want to generate code at
4643 // this point if it hasn't been done yet.
4644 SDValue N = NodeMap[V];
4645 if (!N.getNode() && isa<Argument>(V))
4646 // Check unused arguments map.
4647 N = UnusedArgNodeMap[V];
4649 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4650 SDV = DAG.getDbgValue(Variable, N.getNode(),
4651 N.getResNo(), Offset, dl, SDNodeOrder);
4652 DAG.AddDbgValue(SDV, N.getNode(), false);
4654 } else if (!V->use_empty() ) {
4655 // Do not call getValue(V) yet, as we don't want to generate code.
4656 // Remember it for later.
4657 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4658 DanglingDebugInfoMap[V] = DDI;
4660 // We may expand this to cover more cases. One case where we have no
4661 // data available is an unreferenced parameter.
4662 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4666 // Build a debug info table entry.
4667 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4668 V = BCI->getOperand(0);
4669 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4670 // Don't handle byval struct arguments or VLAs, for example.
4672 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4673 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4676 DenseMap<const AllocaInst*, int>::iterator SI =
4677 FuncInfo.StaticAllocaMap.find(AI);
4678 if (SI == FuncInfo.StaticAllocaMap.end())
4680 int FI = SI->second;
4682 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4683 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4684 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4688 case Intrinsic::eh_typeid_for: {
4689 // Find the type id for the given typeinfo.
4690 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4691 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4692 Res = DAG.getConstant(TypeID, MVT::i32);
4697 case Intrinsic::eh_return_i32:
4698 case Intrinsic::eh_return_i64:
4699 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4700 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
4703 getValue(I.getArgOperand(0)),
4704 getValue(I.getArgOperand(1))));
4706 case Intrinsic::eh_unwind_init:
4707 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4709 case Intrinsic::eh_dwarf_cfa: {
4710 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl,
4711 TLI.getPointerTy());
4712 SDValue Offset = DAG.getNode(ISD::ADD, dl,
4714 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl,
4715 TLI.getPointerTy()),
4717 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl,
4719 DAG.getConstant(0, TLI.getPointerTy()));
4720 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
4724 case Intrinsic::eh_sjlj_callsite: {
4725 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4726 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4727 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4728 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4730 MMI.setCurrentCallSite(CI->getZExtValue());
4733 case Intrinsic::eh_sjlj_functioncontext: {
4734 // Get and store the index of the function context.
4735 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4737 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4738 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4739 MFI->setFunctionContextIndex(FI);
4742 case Intrinsic::eh_sjlj_setjmp: {
4745 Ops[1] = getValue(I.getArgOperand(0));
4746 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl,
4747 DAG.getVTList(MVT::i32, MVT::Other),
4749 setValue(&I, Op.getValue(0));
4750 DAG.setRoot(Op.getValue(1));
4753 case Intrinsic::eh_sjlj_longjmp: {
4754 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other,
4755 getRoot(), getValue(I.getArgOperand(0))));
4759 case Intrinsic::x86_mmx_pslli_w:
4760 case Intrinsic::x86_mmx_pslli_d:
4761 case Intrinsic::x86_mmx_pslli_q:
4762 case Intrinsic::x86_mmx_psrli_w:
4763 case Intrinsic::x86_mmx_psrli_d:
4764 case Intrinsic::x86_mmx_psrli_q:
4765 case Intrinsic::x86_mmx_psrai_w:
4766 case Intrinsic::x86_mmx_psrai_d: {
4767 SDValue ShAmt = getValue(I.getArgOperand(1));
4768 if (isa<ConstantSDNode>(ShAmt)) {
4769 visitTargetIntrinsic(I, Intrinsic);
4772 unsigned NewIntrinsic = 0;
4773 EVT ShAmtVT = MVT::v2i32;
4774 switch (Intrinsic) {
4775 case Intrinsic::x86_mmx_pslli_w:
4776 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4778 case Intrinsic::x86_mmx_pslli_d:
4779 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4781 case Intrinsic::x86_mmx_pslli_q:
4782 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4784 case Intrinsic::x86_mmx_psrli_w:
4785 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4787 case Intrinsic::x86_mmx_psrli_d:
4788 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4790 case Intrinsic::x86_mmx_psrli_q:
4791 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4793 case Intrinsic::x86_mmx_psrai_w:
4794 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4796 case Intrinsic::x86_mmx_psrai_d:
4797 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4799 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4802 // The vector shift intrinsics with scalars uses 32b shift amounts but
4803 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4805 // We must do this early because v2i32 is not a legal type.
4806 DebugLoc dl = getCurDebugLoc();
4809 ShOps[1] = DAG.getConstant(0, MVT::i32);
4810 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
4811 EVT DestVT = TLI.getValueType(I.getType());
4812 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt);
4813 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4814 DAG.getConstant(NewIntrinsic, MVT::i32),
4815 getValue(I.getArgOperand(0)), ShAmt);
4819 case Intrinsic::x86_avx_vinsertf128_pd_256:
4820 case Intrinsic::x86_avx_vinsertf128_ps_256:
4821 case Intrinsic::x86_avx_vinsertf128_si_256:
4822 case Intrinsic::x86_avx2_vinserti128: {
4823 DebugLoc dl = getCurDebugLoc();
4824 EVT DestVT = TLI.getValueType(I.getType());
4825 EVT ElVT = TLI.getValueType(I.getArgOperand(1)->getType());
4826 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4827 ElVT.getVectorNumElements();
4828 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, DestVT,
4829 getValue(I.getArgOperand(0)),
4830 getValue(I.getArgOperand(1)),
4831 DAG.getConstant(Idx, MVT::i32));
4835 case Intrinsic::convertff:
4836 case Intrinsic::convertfsi:
4837 case Intrinsic::convertfui:
4838 case Intrinsic::convertsif:
4839 case Intrinsic::convertuif:
4840 case Intrinsic::convertss:
4841 case Intrinsic::convertsu:
4842 case Intrinsic::convertus:
4843 case Intrinsic::convertuu: {
4844 ISD::CvtCode Code = ISD::CVT_INVALID;
4845 switch (Intrinsic) {
4846 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4847 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4848 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4849 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4850 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4851 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4852 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4853 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4854 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4855 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4857 EVT DestVT = TLI.getValueType(I.getType());
4858 const Value *Op1 = I.getArgOperand(0);
4859 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
4860 DAG.getValueType(DestVT),
4861 DAG.getValueType(getValue(Op1).getValueType()),
4862 getValue(I.getArgOperand(1)),
4863 getValue(I.getArgOperand(2)),
4868 case Intrinsic::sqrt:
4869 setValue(&I, DAG.getNode(ISD::FSQRT, dl,
4870 getValue(I.getArgOperand(0)).getValueType(),
4871 getValue(I.getArgOperand(0))));
4873 case Intrinsic::powi:
4874 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)),
4875 getValue(I.getArgOperand(1)), DAG));
4877 case Intrinsic::sin:
4878 setValue(&I, DAG.getNode(ISD::FSIN, dl,
4879 getValue(I.getArgOperand(0)).getValueType(),
4880 getValue(I.getArgOperand(0))));
4882 case Intrinsic::cos:
4883 setValue(&I, DAG.getNode(ISD::FCOS, dl,
4884 getValue(I.getArgOperand(0)).getValueType(),
4885 getValue(I.getArgOperand(0))));
4887 case Intrinsic::log:
4890 case Intrinsic::log2:
4893 case Intrinsic::log10:
4896 case Intrinsic::exp:
4899 case Intrinsic::exp2:
4902 case Intrinsic::pow:
4905 case Intrinsic::fma:
4906 setValue(&I, DAG.getNode(ISD::FMA, dl,
4907 getValue(I.getArgOperand(0)).getValueType(),
4908 getValue(I.getArgOperand(0)),
4909 getValue(I.getArgOperand(1)),
4910 getValue(I.getArgOperand(2))));
4912 case Intrinsic::convert_to_fp16:
4913 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl,
4914 MVT::i16, getValue(I.getArgOperand(0))));
4916 case Intrinsic::convert_from_fp16:
4917 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl,
4918 MVT::f32, getValue(I.getArgOperand(0))));
4920 case Intrinsic::pcmarker: {
4921 SDValue Tmp = getValue(I.getArgOperand(0));
4922 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
4925 case Intrinsic::readcyclecounter: {
4926 SDValue Op = getRoot();
4927 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl,
4928 DAG.getVTList(MVT::i64, MVT::Other),
4931 DAG.setRoot(Res.getValue(1));
4934 case Intrinsic::bswap:
4935 setValue(&I, DAG.getNode(ISD::BSWAP, dl,
4936 getValue(I.getArgOperand(0)).getValueType(),
4937 getValue(I.getArgOperand(0))));
4939 case Intrinsic::cttz: {
4940 SDValue Arg = getValue(I.getArgOperand(0));
4941 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4942 EVT Ty = Arg.getValueType();
4943 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4947 case Intrinsic::ctlz: {
4948 SDValue Arg = getValue(I.getArgOperand(0));
4949 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4950 EVT Ty = Arg.getValueType();
4951 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4955 case Intrinsic::ctpop: {
4956 SDValue Arg = getValue(I.getArgOperand(0));
4957 EVT Ty = Arg.getValueType();
4958 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg));
4961 case Intrinsic::stacksave: {
4962 SDValue Op = getRoot();
4963 Res = DAG.getNode(ISD::STACKSAVE, dl,
4964 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
4966 DAG.setRoot(Res.getValue(1));
4969 case Intrinsic::stackrestore: {
4970 Res = getValue(I.getArgOperand(0));
4971 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res));
4974 case Intrinsic::stackprotector: {
4975 // Emit code into the DAG to store the stack guard onto the stack.
4976 MachineFunction &MF = DAG.getMachineFunction();
4977 MachineFrameInfo *MFI = MF.getFrameInfo();
4978 EVT PtrTy = TLI.getPointerTy();
4980 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
4981 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4983 int FI = FuncInfo.StaticAllocaMap[Slot];
4984 MFI->setStackProtectorIndex(FI);
4986 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4988 // Store the stack protector onto the stack.
4989 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN,
4990 MachinePointerInfo::getFixedStack(FI),
4996 case Intrinsic::objectsize: {
4997 // If we don't know by now, we're never going to know.
4998 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5000 assert(CI && "Non-constant type in __builtin_object_size?");
5002 SDValue Arg = getValue(I.getCalledValue());
5003 EVT Ty = Arg.getValueType();
5006 Res = DAG.getConstant(-1ULL, Ty);
5008 Res = DAG.getConstant(0, Ty);
5013 case Intrinsic::var_annotation:
5014 // Discard annotate attributes
5017 case Intrinsic::init_trampoline: {
5018 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5022 Ops[1] = getValue(I.getArgOperand(0));
5023 Ops[2] = getValue(I.getArgOperand(1));
5024 Ops[3] = getValue(I.getArgOperand(2));
5025 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5026 Ops[5] = DAG.getSrcValue(F);
5028 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6);
5033 case Intrinsic::adjust_trampoline: {
5034 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl,
5036 getValue(I.getArgOperand(0))));
5039 case Intrinsic::gcroot:
5041 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5042 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5044 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5045 GFI->addStackRoot(FI->getIndex(), TypeMap);
5048 case Intrinsic::gcread:
5049 case Intrinsic::gcwrite:
5050 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5051 case Intrinsic::flt_rounds:
5052 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
5055 case Intrinsic::expect: {
5056 // Just replace __builtin_expect(exp, c) with EXP.
5057 setValue(&I, getValue(I.getArgOperand(0)));
5061 case Intrinsic::trap: {
5062 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5063 if (TrapFuncName.empty()) {
5064 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
5067 TargetLowering::ArgListTy Args;
5068 std::pair<SDValue, SDValue> Result =
5069 TLI.LowerCallTo(getRoot(), I.getType(),
5070 false, false, false, false, 0, CallingConv::C,
5071 /*isTailCall=*/false,
5072 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5073 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
5074 Args, DAG, getCurDebugLoc());
5075 DAG.setRoot(Result.second);
5078 case Intrinsic::debugtrap: {
5079 DAG.setRoot(DAG.getNode(ISD::DEBUGTRAP, dl,MVT::Other, getRoot()));
5082 case Intrinsic::uadd_with_overflow:
5083 case Intrinsic::sadd_with_overflow:
5084 case Intrinsic::usub_with_overflow:
5085 case Intrinsic::ssub_with_overflow:
5086 case Intrinsic::umul_with_overflow:
5087 case Intrinsic::smul_with_overflow: {
5089 switch (Intrinsic) {
5090 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5091 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5092 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5093 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5094 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5095 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5096 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5098 SDValue Op1 = getValue(I.getArgOperand(0));
5099 SDValue Op2 = getValue(I.getArgOperand(1));
5101 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5102 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2));
5105 case Intrinsic::prefetch: {
5107 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5109 Ops[1] = getValue(I.getArgOperand(0));
5110 Ops[2] = getValue(I.getArgOperand(1));
5111 Ops[3] = getValue(I.getArgOperand(2));
5112 Ops[4] = getValue(I.getArgOperand(3));
5113 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
5114 DAG.getVTList(MVT::Other),
5116 EVT::getIntegerVT(*Context, 8),
5117 MachinePointerInfo(I.getArgOperand(0)),
5119 false, /* volatile */
5121 rw==1)); /* write */
5125 case Intrinsic::invariant_start:
5126 case Intrinsic::lifetime_start:
5127 // Discard region information.
5128 setValue(&I, DAG.getUNDEF(TLI.getPointerTy()));
5130 case Intrinsic::invariant_end:
5131 case Intrinsic::lifetime_end:
5132 // Discard region information.
5137 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5139 MachineBasicBlock *LandingPad) {
5140 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5141 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5142 Type *RetTy = FTy->getReturnType();
5143 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5144 MCSymbol *BeginLabel = 0;
5146 TargetLowering::ArgListTy Args;
5147 TargetLowering::ArgListEntry Entry;
5148 Args.reserve(CS.arg_size());
5150 // Check whether the function can return without sret-demotion.
5151 SmallVector<ISD::OutputArg, 4> Outs;
5152 SmallVector<uint64_t, 4> Offsets;
5153 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
5154 Outs, TLI, &Offsets);
5156 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
5157 DAG.getMachineFunction(),
5158 FTy->isVarArg(), Outs,
5161 SDValue DemoteStackSlot;
5162 int DemoteStackIdx = -100;
5164 if (!CanLowerReturn) {
5165 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(
5166 FTy->getReturnType());
5167 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(
5168 FTy->getReturnType());
5169 MachineFunction &MF = DAG.getMachineFunction();
5170 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5171 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5173 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy());
5174 Entry.Node = DemoteStackSlot;
5175 Entry.Ty = StackSlotPtrType;
5176 Entry.isSExt = false;
5177 Entry.isZExt = false;
5178 Entry.isInReg = false;
5179 Entry.isSRet = true;
5180 Entry.isNest = false;
5181 Entry.isByVal = false;
5182 Entry.Alignment = Align;
5183 Args.push_back(Entry);
5184 RetTy = Type::getVoidTy(FTy->getContext());
5187 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5189 const Value *V = *i;
5192 if (V->getType()->isEmptyTy())
5195 SDValue ArgNode = getValue(V);
5196 Entry.Node = ArgNode; Entry.Ty = V->getType();
5198 unsigned attrInd = i - CS.arg_begin() + 1;
5199 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt);
5200 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt);
5201 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg);
5202 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet);
5203 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest);
5204 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal);
5205 Entry.Alignment = CS.getParamAlignment(attrInd);
5206 Args.push_back(Entry);
5210 // Insert a label before the invoke call to mark the try range. This can be
5211 // used to detect deletion of the invoke via the MachineModuleInfo.
5212 BeginLabel = MMI.getContext().CreateTempSymbol();
5214 // For SjLj, keep track of which landing pads go with which invokes
5215 // so as to maintain the ordering of pads in the LSDA.
5216 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5217 if (CallSiteIndex) {
5218 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5219 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5221 // Now that the call site is handled, stop tracking it.
5222 MMI.setCurrentCallSite(0);
5225 // Both PendingLoads and PendingExports must be flushed here;
5226 // this call might not return.
5228 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel));
5231 // Check if target-independent constraints permit a tail call here.
5232 // Target-dependent constraints are checked within TLI.LowerCallTo.
5234 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI))
5237 // If there's a possibility that fast-isel has already selected some amount
5238 // of the current basic block, don't emit a tail call.
5239 if (isTailCall && TM.Options.EnableFastISel)
5242 std::pair<SDValue,SDValue> Result =
5243 TLI.LowerCallTo(getRoot(), RetTy,
5244 CS.paramHasAttr(0, Attribute::SExt),
5245 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(),
5246 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
5247 CS.getCallingConv(),
5250 !CS.getInstruction()->use_empty(),
5251 Callee, Args, DAG, getCurDebugLoc());
5252 assert((isTailCall || Result.second.getNode()) &&
5253 "Non-null chain expected with non-tail call!");
5254 assert((Result.second.getNode() || !Result.first.getNode()) &&
5255 "Null value expected with tail call!");
5256 if (Result.first.getNode()) {
5257 setValue(CS.getInstruction(), Result.first);
5258 } else if (!CanLowerReturn && Result.second.getNode()) {
5259 // The instruction result is the result of loading from the
5260 // hidden sret parameter.
5261 SmallVector<EVT, 1> PVTs;
5262 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5264 ComputeValueVTs(TLI, PtrRetTy, PVTs);
5265 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5266 EVT PtrVT = PVTs[0];
5267 unsigned NumValues = Outs.size();
5268 SmallVector<SDValue, 4> Values(NumValues);
5269 SmallVector<SDValue, 4> Chains(NumValues);
5271 for (unsigned i = 0; i < NumValues; ++i) {
5272 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
5274 DAG.getConstant(Offsets[i], PtrVT));
5275 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
5277 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5278 false, false, false, 1);
5280 Chains[i] = L.getValue(1);
5283 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
5284 MVT::Other, &Chains[0], NumValues);
5285 PendingLoads.push_back(Chain);
5287 // Collect the legal value parts into potentially illegal values
5288 // that correspond to the original function's return values.
5289 SmallVector<EVT, 4> RetTys;
5290 RetTy = FTy->getReturnType();
5291 ComputeValueVTs(TLI, RetTy, RetTys);
5292 ISD::NodeType AssertOp = ISD::DELETED_NODE;
5293 SmallVector<SDValue, 4> ReturnValues;
5294 unsigned CurReg = 0;
5295 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
5297 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT);
5298 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT);
5300 SDValue ReturnValue =
5301 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs,
5302 RegisterVT, VT, AssertOp);
5303 ReturnValues.push_back(ReturnValue);
5307 setValue(CS.getInstruction(),
5308 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(),
5309 DAG.getVTList(&RetTys[0], RetTys.size()),
5310 &ReturnValues[0], ReturnValues.size()));
5313 // Assign order to nodes here. If the call does not produce a result, it won't
5314 // be mapped to a SDNode and visit() will not assign it an order number.
5315 if (!Result.second.getNode()) {
5316 // As a special case, a null chain means that a tail call has been emitted and
5317 // the DAG root is already updated.
5320 AssignOrderingToNode(DAG.getRoot().getNode());
5322 DAG.setRoot(Result.second);
5324 AssignOrderingToNode(Result.second.getNode());
5328 // Insert a label at the end of the invoke call to mark the try range. This
5329 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5330 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5331 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel));
5333 // Inform MachineModuleInfo of range.
5334 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5338 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5339 /// value is equal or not-equal to zero.
5340 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5341 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end();
5343 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI))
5344 if (IC->isEquality())
5345 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5346 if (C->isNullValue())
5348 // Unknown instruction.
5354 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5356 SelectionDAGBuilder &Builder) {
5358 // Check to see if this load can be trivially constant folded, e.g. if the
5359 // input is from a string literal.
5360 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5361 // Cast pointer to the type we really want to load.
5362 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5363 PointerType::getUnqual(LoadTy));
5365 if (const Constant *LoadCst =
5366 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5368 return Builder.getValue(LoadCst);
5371 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5372 // still constant memory, the input chain can be the entry node.
5374 bool ConstantMemory = false;
5376 // Do not serialize (non-volatile) loads of constant memory with anything.
5377 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5378 Root = Builder.DAG.getEntryNode();
5379 ConstantMemory = true;
5381 // Do not serialize non-volatile loads against each other.
5382 Root = Builder.DAG.getRoot();
5385 SDValue Ptr = Builder.getValue(PtrVal);
5386 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root,
5387 Ptr, MachinePointerInfo(PtrVal),
5389 false /*nontemporal*/,
5390 false /*isinvariant*/, 1 /* align=1 */);
5392 if (!ConstantMemory)
5393 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5398 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5399 /// If so, return true and lower it, otherwise return false and it will be
5400 /// lowered like a normal call.
5401 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5402 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5403 if (I.getNumArgOperands() != 3)
5406 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5407 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5408 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5409 !I.getType()->isIntegerTy())
5412 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2));
5414 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5415 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5416 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) {
5417 bool ActuallyDoIt = true;
5420 switch (Size->getZExtValue()) {
5422 LoadVT = MVT::Other;
5424 ActuallyDoIt = false;
5428 LoadTy = Type::getInt16Ty(Size->getContext());
5432 LoadTy = Type::getInt32Ty(Size->getContext());
5436 LoadTy = Type::getInt64Ty(Size->getContext());
5440 LoadVT = MVT::v4i32;
5441 LoadTy = Type::getInt32Ty(Size->getContext());
5442 LoadTy = VectorType::get(LoadTy, 4);
5447 // This turns into unaligned loads. We only do this if the target natively
5448 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5449 // we'll only produce a small number of byte loads.
5451 // Require that we can find a legal MVT, and only do this if the target
5452 // supports unaligned loads of that type. Expanding into byte loads would
5454 if (ActuallyDoIt && Size->getZExtValue() > 4) {
5455 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5456 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5457 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT))
5458 ActuallyDoIt = false;
5462 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5463 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5465 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
5467 EVT CallVT = TLI.getValueType(I.getType(), true);
5468 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT));
5478 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5479 // Handle inline assembly differently.
5480 if (isa<InlineAsm>(I.getCalledValue())) {
5485 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5486 ComputeUsesVAFloatArgument(I, &MMI);
5488 const char *RenameFn = 0;
5489 if (Function *F = I.getCalledFunction()) {
5490 if (F->isDeclaration()) {
5491 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5492 if (unsigned IID = II->getIntrinsicID(F)) {
5493 RenameFn = visitIntrinsicCall(I, IID);
5498 if (unsigned IID = F->getIntrinsicID()) {
5499 RenameFn = visitIntrinsicCall(I, IID);
5505 // Check for well-known libc/libm calls. If the function is internal, it
5506 // can't be a library call.
5507 if (!F->hasLocalLinkage() && F->hasName()) {
5508 StringRef Name = F->getName();
5509 if ((LibInfo->has(LibFunc::copysign) && Name == "copysign") ||
5510 (LibInfo->has(LibFunc::copysignf) && Name == "copysignf") ||
5511 (LibInfo->has(LibFunc::copysignl) && Name == "copysignl")) {
5512 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5513 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5514 I.getType() == I.getArgOperand(0)->getType() &&
5515 I.getType() == I.getArgOperand(1)->getType()) {
5516 SDValue LHS = getValue(I.getArgOperand(0));
5517 SDValue RHS = getValue(I.getArgOperand(1));
5518 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(),
5519 LHS.getValueType(), LHS, RHS));
5522 } else if ((LibInfo->has(LibFunc::fabs) && Name == "fabs") ||
5523 (LibInfo->has(LibFunc::fabsf) && Name == "fabsf") ||
5524 (LibInfo->has(LibFunc::fabsl) && Name == "fabsl")) {
5525 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5526 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5527 I.getType() == I.getArgOperand(0)->getType()) {
5528 SDValue Tmp = getValue(I.getArgOperand(0));
5529 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(),
5530 Tmp.getValueType(), Tmp));
5533 } else if ((LibInfo->has(LibFunc::sin) && Name == "sin") ||
5534 (LibInfo->has(LibFunc::sinf) && Name == "sinf") ||
5535 (LibInfo->has(LibFunc::sinl) && Name == "sinl")) {
5536 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5537 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5538 I.getType() == I.getArgOperand(0)->getType() &&
5539 I.onlyReadsMemory()) {
5540 SDValue Tmp = getValue(I.getArgOperand(0));
5541 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(),
5542 Tmp.getValueType(), Tmp));
5545 } else if ((LibInfo->has(LibFunc::cos) && Name == "cos") ||
5546 (LibInfo->has(LibFunc::cosf) && Name == "cosf") ||
5547 (LibInfo->has(LibFunc::cosl) && Name == "cosl")) {
5548 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5549 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5550 I.getType() == I.getArgOperand(0)->getType() &&
5551 I.onlyReadsMemory()) {
5552 SDValue Tmp = getValue(I.getArgOperand(0));
5553 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(),
5554 Tmp.getValueType(), Tmp));
5557 } else if ((LibInfo->has(LibFunc::sqrt) && Name == "sqrt") ||
5558 (LibInfo->has(LibFunc::sqrtf) && Name == "sqrtf") ||
5559 (LibInfo->has(LibFunc::sqrtl) && Name == "sqrtl")) {
5560 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5561 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5562 I.getType() == I.getArgOperand(0)->getType() &&
5563 I.onlyReadsMemory()) {
5564 SDValue Tmp = getValue(I.getArgOperand(0));
5565 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(),
5566 Tmp.getValueType(), Tmp));
5569 } else if ((LibInfo->has(LibFunc::floor) && Name == "floor") ||
5570 (LibInfo->has(LibFunc::floorf) && Name == "floorf") ||
5571 (LibInfo->has(LibFunc::floorl) && Name == "floorl")) {
5572 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5573 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5574 I.getType() == I.getArgOperand(0)->getType()) {
5575 SDValue Tmp = getValue(I.getArgOperand(0));
5576 setValue(&I, DAG.getNode(ISD::FFLOOR, getCurDebugLoc(),
5577 Tmp.getValueType(), Tmp));
5580 } else if ((LibInfo->has(LibFunc::nearbyint) && Name == "nearbyint") ||
5581 (LibInfo->has(LibFunc::nearbyintf) && Name == "nearbyintf") ||
5582 (LibInfo->has(LibFunc::nearbyintl) && Name == "nearbyintl")) {
5583 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5584 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5585 I.getType() == I.getArgOperand(0)->getType()) {
5586 SDValue Tmp = getValue(I.getArgOperand(0));
5587 setValue(&I, DAG.getNode(ISD::FNEARBYINT, getCurDebugLoc(),
5588 Tmp.getValueType(), Tmp));
5591 } else if ((LibInfo->has(LibFunc::ceil) && Name == "ceil") ||
5592 (LibInfo->has(LibFunc::ceilf) && Name == "ceilf") ||
5593 (LibInfo->has(LibFunc::ceill) && Name == "ceill")) {
5594 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5595 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5596 I.getType() == I.getArgOperand(0)->getType()) {
5597 SDValue Tmp = getValue(I.getArgOperand(0));
5598 setValue(&I, DAG.getNode(ISD::FCEIL, getCurDebugLoc(),
5599 Tmp.getValueType(), Tmp));
5602 } else if ((LibInfo->has(LibFunc::rint) && Name == "rint") ||
5603 (LibInfo->has(LibFunc::rintf) && Name == "rintf") ||
5604 (LibInfo->has(LibFunc::rintl) && Name == "rintl")) {
5605 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5606 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5607 I.getType() == I.getArgOperand(0)->getType()) {
5608 SDValue Tmp = getValue(I.getArgOperand(0));
5609 setValue(&I, DAG.getNode(ISD::FRINT, getCurDebugLoc(),
5610 Tmp.getValueType(), Tmp));
5613 } else if ((LibInfo->has(LibFunc::trunc) && Name == "trunc") ||
5614 (LibInfo->has(LibFunc::truncf) && Name == "truncf") ||
5615 (LibInfo->has(LibFunc::truncl) && Name == "truncl")) {
5616 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5617 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5618 I.getType() == I.getArgOperand(0)->getType()) {
5619 SDValue Tmp = getValue(I.getArgOperand(0));
5620 setValue(&I, DAG.getNode(ISD::FTRUNC, getCurDebugLoc(),
5621 Tmp.getValueType(), Tmp));
5624 } else if ((LibInfo->has(LibFunc::log2) && Name == "log2") ||
5625 (LibInfo->has(LibFunc::log2f) && Name == "log2f") ||
5626 (LibInfo->has(LibFunc::log2l) && Name == "log2l")) {
5627 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5628 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5629 I.getType() == I.getArgOperand(0)->getType() &&
5630 I.onlyReadsMemory()) {
5631 SDValue Tmp = getValue(I.getArgOperand(0));
5632 setValue(&I, DAG.getNode(ISD::FLOG2, getCurDebugLoc(),
5633 Tmp.getValueType(), Tmp));
5636 } else if ((LibInfo->has(LibFunc::exp2) && Name == "exp2") ||
5637 (LibInfo->has(LibFunc::exp2f) && Name == "exp2f") ||
5638 (LibInfo->has(LibFunc::exp2l) && Name == "exp2l")) {
5639 if (I.getNumArgOperands() == 1 && // Basic sanity checks.
5640 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5641 I.getType() == I.getArgOperand(0)->getType() &&
5642 I.onlyReadsMemory()) {
5643 SDValue Tmp = getValue(I.getArgOperand(0));
5644 setValue(&I, DAG.getNode(ISD::FEXP2, getCurDebugLoc(),
5645 Tmp.getValueType(), Tmp));
5648 } else if (Name == "memcmp") {
5649 if (visitMemCmpCall(I))
5657 Callee = getValue(I.getCalledValue());
5659 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy());
5661 // Check if we can potentially perform a tail call. More detailed checking is
5662 // be done within LowerCallTo, after more information about the call is known.
5663 LowerCallTo(&I, Callee, I.isTailCall());
5668 /// AsmOperandInfo - This contains information for each constraint that we are
5670 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5672 /// CallOperand - If this is the result output operand or a clobber
5673 /// this is null, otherwise it is the incoming operand to the CallInst.
5674 /// This gets modified as the asm is processed.
5675 SDValue CallOperand;
5677 /// AssignedRegs - If this is a register or register class operand, this
5678 /// contains the set of register corresponding to the operand.
5679 RegsForValue AssignedRegs;
5681 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5682 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) {
5685 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5686 /// corresponds to. If there is no Value* for this operand, it returns
5688 EVT getCallOperandValEVT(LLVMContext &Context,
5689 const TargetLowering &TLI,
5690 const TargetData *TD) const {
5691 if (CallOperandVal == 0) return MVT::Other;
5693 if (isa<BasicBlock>(CallOperandVal))
5694 return TLI.getPointerTy();
5696 llvm::Type *OpTy = CallOperandVal->getType();
5698 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5699 // If this is an indirect operand, the operand is a pointer to the
5702 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5704 report_fatal_error("Indirect operand for inline asm not a pointer!");
5705 OpTy = PtrTy->getElementType();
5708 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5709 if (StructType *STy = dyn_cast<StructType>(OpTy))
5710 if (STy->getNumElements() == 1)
5711 OpTy = STy->getElementType(0);
5713 // If OpTy is not a single value, it may be a struct/union that we
5714 // can tile with integers.
5715 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5716 unsigned BitSize = TD->getTypeSizeInBits(OpTy);
5725 OpTy = IntegerType::get(Context, BitSize);
5730 return TLI.getValueType(OpTy, true);
5734 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
5736 } // end anonymous namespace
5738 /// GetRegistersForValue - Assign registers (virtual or physical) for the
5739 /// specified operand. We prefer to assign virtual registers, to allow the
5740 /// register allocator to handle the assignment process. However, if the asm
5741 /// uses features that we can't model on machineinstrs, we have SDISel do the
5742 /// allocation. This produces generally horrible, but correct, code.
5744 /// OpInfo describes the operand.
5746 static void GetRegistersForValue(SelectionDAG &DAG,
5747 const TargetLowering &TLI,
5749 SDISelAsmOperandInfo &OpInfo) {
5750 LLVMContext &Context = *DAG.getContext();
5752 MachineFunction &MF = DAG.getMachineFunction();
5753 SmallVector<unsigned, 4> Regs;
5755 // If this is a constraint for a single physreg, or a constraint for a
5756 // register class, find it.
5757 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
5758 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5759 OpInfo.ConstraintVT);
5761 unsigned NumRegs = 1;
5762 if (OpInfo.ConstraintVT != MVT::Other) {
5763 // If this is a FP input in an integer register (or visa versa) insert a bit
5764 // cast of the input value. More generally, handle any case where the input
5765 // value disagrees with the register class we plan to stick this in.
5766 if (OpInfo.Type == InlineAsm::isInput &&
5767 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
5768 // Try to convert to the first EVT that the reg class contains. If the
5769 // types are identical size, use a bitcast to convert (e.g. two differing
5771 EVT RegVT = *PhysReg.second->vt_begin();
5772 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
5773 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5774 RegVT, OpInfo.CallOperand);
5775 OpInfo.ConstraintVT = RegVT;
5776 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
5777 // If the input is a FP value and we want it in FP registers, do a
5778 // bitcast to the corresponding integer type. This turns an f64 value
5779 // into i64, which can be passed with two i32 values on a 32-bit
5781 RegVT = EVT::getIntegerVT(Context,
5782 OpInfo.ConstraintVT.getSizeInBits());
5783 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
5784 RegVT, OpInfo.CallOperand);
5785 OpInfo.ConstraintVT = RegVT;
5789 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
5793 EVT ValueVT = OpInfo.ConstraintVT;
5795 // If this is a constraint for a specific physical register, like {r17},
5797 if (unsigned AssignedReg = PhysReg.first) {
5798 const TargetRegisterClass *RC = PhysReg.second;
5799 if (OpInfo.ConstraintVT == MVT::Other)
5800 ValueVT = *RC->vt_begin();
5802 // Get the actual register value type. This is important, because the user
5803 // may have asked for (e.g.) the AX register in i32 type. We need to
5804 // remember that AX is actually i16 to get the right extension.
5805 RegVT = *RC->vt_begin();
5807 // This is a explicit reference to a physical register.
5808 Regs.push_back(AssignedReg);
5810 // If this is an expanded reference, add the rest of the regs to Regs.
5812 TargetRegisterClass::iterator I = RC->begin();
5813 for (; *I != AssignedReg; ++I)
5814 assert(I != RC->end() && "Didn't find reg!");
5816 // Already added the first reg.
5818 for (; NumRegs; --NumRegs, ++I) {
5819 assert(I != RC->end() && "Ran out of registers to allocate!");
5824 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5828 // Otherwise, if this was a reference to an LLVM register class, create vregs
5829 // for this reference.
5830 if (const TargetRegisterClass *RC = PhysReg.second) {
5831 RegVT = *RC->vt_begin();
5832 if (OpInfo.ConstraintVT == MVT::Other)
5835 // Create the appropriate number of virtual registers.
5836 MachineRegisterInfo &RegInfo = MF.getRegInfo();
5837 for (; NumRegs; --NumRegs)
5838 Regs.push_back(RegInfo.createVirtualRegister(RC));
5840 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
5844 // Otherwise, we couldn't allocate enough registers for this.
5847 /// visitInlineAsm - Handle a call to an InlineAsm object.
5849 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
5850 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
5852 /// ConstraintOperands - Information about all of the constraints.
5853 SDISelAsmOperandInfoVector ConstraintOperands;
5855 TargetLowering::AsmOperandInfoVector
5856 TargetConstraints = TLI.ParseConstraints(CS);
5858 bool hasMemory = false;
5860 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
5861 unsigned ResNo = 0; // ResNo - The result number of the next output.
5862 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
5863 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
5864 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
5866 EVT OpVT = MVT::Other;
5868 // Compute the value type for each operand.
5869 switch (OpInfo.Type) {
5870 case InlineAsm::isOutput:
5871 // Indirect outputs just consume an argument.
5872 if (OpInfo.isIndirect) {
5873 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5877 // The return value of the call is this value. As such, there is no
5878 // corresponding argument.
5879 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
5880 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
5881 OpVT = TLI.getValueType(STy->getElementType(ResNo));
5883 assert(ResNo == 0 && "Asm only has one result!");
5884 OpVT = TLI.getValueType(CS.getType());
5888 case InlineAsm::isInput:
5889 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
5891 case InlineAsm::isClobber:
5896 // If this is an input or an indirect output, process the call argument.
5897 // BasicBlocks are labels, currently appearing only in asm's.
5898 if (OpInfo.CallOperandVal) {
5899 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
5900 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
5902 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
5905 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD);
5908 OpInfo.ConstraintVT = OpVT;
5910 // Indirect operand accesses access memory.
5911 if (OpInfo.isIndirect)
5914 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
5915 TargetLowering::ConstraintType
5916 CType = TLI.getConstraintType(OpInfo.Codes[j]);
5917 if (CType == TargetLowering::C_Memory) {
5925 SDValue Chain, Flag;
5927 // We won't need to flush pending loads if this asm doesn't touch
5928 // memory and is nonvolatile.
5929 if (hasMemory || IA->hasSideEffects())
5932 Chain = DAG.getRoot();
5934 // Second pass over the constraints: compute which constraint option to use
5935 // and assign registers to constraints that want a specific physreg.
5936 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
5937 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
5939 // If this is an output operand with a matching input operand, look up the
5940 // matching input. If their types mismatch, e.g. one is an integer, the
5941 // other is floating point, or their sizes are different, flag it as an
5943 if (OpInfo.hasMatchingInput()) {
5944 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
5946 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
5947 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
5948 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
5949 OpInfo.ConstraintVT);
5950 std::pair<unsigned, const TargetRegisterClass*> InputRC =
5951 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode,
5952 Input.ConstraintVT);
5953 if ((OpInfo.ConstraintVT.isInteger() !=
5954 Input.ConstraintVT.isInteger()) ||
5955 (MatchRC.second != InputRC.second)) {
5956 report_fatal_error("Unsupported asm: input constraint"
5957 " with a matching output constraint of"
5958 " incompatible type!");
5960 Input.ConstraintVT = OpInfo.ConstraintVT;
5964 // Compute the constraint code and ConstraintType to use.
5965 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
5967 // If this is a memory input, and if the operand is not indirect, do what we
5968 // need to to provide an address for the memory input.
5969 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
5970 !OpInfo.isIndirect) {
5971 assert((OpInfo.isMultipleAlternative ||
5972 (OpInfo.Type == InlineAsm::isInput)) &&
5973 "Can only indirectify direct input operands!");
5975 // Memory operands really want the address of the value. If we don't have
5976 // an indirect input, put it in the constpool if we can, otherwise spill
5977 // it to a stack slot.
5978 // TODO: This isn't quite right. We need to handle these according to
5979 // the addressing mode that the constraint wants. Also, this may take
5980 // an additional register for the computation and we don't want that
5983 // If the operand is a float, integer, or vector constant, spill to a
5984 // constant pool entry to get its address.
5985 const Value *OpVal = OpInfo.CallOperandVal;
5986 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
5987 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
5988 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
5989 TLI.getPointerTy());
5991 // Otherwise, create a stack slot and emit a store to it before the
5993 Type *Ty = OpVal->getType();
5994 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty);
5995 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
5996 MachineFunction &MF = DAG.getMachineFunction();
5997 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5998 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
5999 Chain = DAG.getStore(Chain, getCurDebugLoc(),
6000 OpInfo.CallOperand, StackSlot,
6001 MachinePointerInfo::getFixedStack(SSFI),
6003 OpInfo.CallOperand = StackSlot;
6006 // There is no longer a Value* corresponding to this operand.
6007 OpInfo.CallOperandVal = 0;
6009 // It is now an indirect operand.
6010 OpInfo.isIndirect = true;
6013 // If this constraint is for a specific register, allocate it before
6015 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6016 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6019 // Second pass - Loop over all of the operands, assigning virtual or physregs
6020 // to register class operands.
6021 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6022 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6024 // C_Register operands have already been allocated, Other/Memory don't need
6026 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6027 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo);
6030 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6031 std::vector<SDValue> AsmNodeOperands;
6032 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6033 AsmNodeOperands.push_back(
6034 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6035 TLI.getPointerTy()));
6037 // If we have a !srcloc metadata node associated with it, we want to attach
6038 // this to the ultimately generated inline asm machineinstr. To do this, we
6039 // pass in the third operand as this (potentially null) inline asm MDNode.
6040 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6041 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6043 // Remember the HasSideEffect and AlignStack bits as operand 3.
6044 unsigned ExtraInfo = 0;
6045 if (IA->hasSideEffects())
6046 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6047 if (IA->isAlignStack())
6048 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6049 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6050 TLI.getPointerTy()));
6052 // Loop over all of the inputs, copying the operand values into the
6053 // appropriate registers and processing the output regs.
6054 RegsForValue RetValRegs;
6056 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6057 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6059 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6060 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6062 switch (OpInfo.Type) {
6063 case InlineAsm::isOutput: {
6064 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6065 OpInfo.ConstraintType != TargetLowering::C_Register) {
6066 // Memory output, or 'other' output (e.g. 'X' constraint).
6067 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6069 // Add information to the INLINEASM node to know about this output.
6070 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6071 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6072 TLI.getPointerTy()));
6073 AsmNodeOperands.push_back(OpInfo.CallOperand);
6077 // Otherwise, this is a register or register class output.
6079 // Copy the output from the appropriate register. Find a register that
6081 if (OpInfo.AssignedRegs.Regs.empty()) {
6082 LLVMContext &Ctx = *DAG.getContext();
6083 Ctx.emitError(CS.getInstruction(),
6084 "couldn't allocate output register for constraint '" +
6085 Twine(OpInfo.ConstraintCode) + "'");
6089 // If this is an indirect operand, store through the pointer after the
6091 if (OpInfo.isIndirect) {
6092 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6093 OpInfo.CallOperandVal));
6095 // This is the result value of the call.
6096 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6097 // Concatenate this output onto the outputs list.
6098 RetValRegs.append(OpInfo.AssignedRegs);
6101 // Add information to the INLINEASM node to know that this register is
6103 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ?
6104 InlineAsm::Kind_RegDefEarlyClobber :
6105 InlineAsm::Kind_RegDef,
6112 case InlineAsm::isInput: {
6113 SDValue InOperandVal = OpInfo.CallOperand;
6115 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6116 // If this is required to match an output register we have already set,
6117 // just use its register.
6118 unsigned OperandNo = OpInfo.getMatchedOperand();
6120 // Scan until we find the definition we already emitted of this operand.
6121 // When we find it, create a RegsForValue operand.
6122 unsigned CurOp = InlineAsm::Op_FirstOperand;
6123 for (; OperandNo; --OperandNo) {
6124 // Advance to the next operand.
6126 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6127 assert((InlineAsm::isRegDefKind(OpFlag) ||
6128 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6129 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6130 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6134 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6135 if (InlineAsm::isRegDefKind(OpFlag) ||
6136 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6137 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6138 if (OpInfo.isIndirect) {
6139 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6140 LLVMContext &Ctx = *DAG.getContext();
6141 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6142 " don't know how to handle tied "
6143 "indirect register inputs");
6146 RegsForValue MatchedRegs;
6147 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6148 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
6149 MatchedRegs.RegVTs.push_back(RegVT);
6150 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6151 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6153 MatchedRegs.Regs.push_back
6154 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)));
6156 // Use the produced MatchedRegs object to
6157 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6159 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6160 true, OpInfo.getMatchedOperand(),
6161 DAG, AsmNodeOperands);
6165 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6166 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6167 "Unexpected number of operands");
6168 // Add information to the INLINEASM node to know about this input.
6169 // See InlineAsm.h isUseOperandTiedToDef.
6170 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6171 OpInfo.getMatchedOperand());
6172 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6173 TLI.getPointerTy()));
6174 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6178 // Treat indirect 'X' constraint as memory.
6179 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6181 OpInfo.ConstraintType = TargetLowering::C_Memory;
6183 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6184 std::vector<SDValue> Ops;
6185 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6188 LLVMContext &Ctx = *DAG.getContext();
6189 Ctx.emitError(CS.getInstruction(),
6190 "invalid operand for inline asm constraint '" +
6191 Twine(OpInfo.ConstraintCode) + "'");
6195 // Add information to the INLINEASM node to know about this input.
6196 unsigned ResOpType =
6197 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6198 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6199 TLI.getPointerTy()));
6200 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6204 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6205 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6206 assert(InOperandVal.getValueType() == TLI.getPointerTy() &&
6207 "Memory operands expect pointer values");
6209 // Add information to the INLINEASM node to know about this input.
6210 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6211 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6212 TLI.getPointerTy()));
6213 AsmNodeOperands.push_back(InOperandVal);
6217 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6218 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6219 "Unknown constraint type!");
6220 assert(!OpInfo.isIndirect &&
6221 "Don't know how to handle indirect register inputs yet!");
6223 // Copy the input into the appropriate registers.
6224 if (OpInfo.AssignedRegs.Regs.empty()) {
6225 LLVMContext &Ctx = *DAG.getContext();
6226 Ctx.emitError(CS.getInstruction(),
6227 "couldn't allocate input reg for constraint '" +
6228 Twine(OpInfo.ConstraintCode) + "'");
6232 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(),
6235 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6236 DAG, AsmNodeOperands);
6239 case InlineAsm::isClobber: {
6240 // Add the clobbered value to the operand list, so that the register
6241 // allocator is aware that the physreg got clobbered.
6242 if (!OpInfo.AssignedRegs.Regs.empty())
6243 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6251 // Finish up input operands. Set the input chain and add the flag last.
6252 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6253 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6255 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
6256 DAG.getVTList(MVT::Other, MVT::Glue),
6257 &AsmNodeOperands[0], AsmNodeOperands.size());
6258 Flag = Chain.getValue(1);
6260 // If this asm returns a register value, copy the result from that register
6261 // and set it as the value of the call.
6262 if (!RetValRegs.Regs.empty()) {
6263 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6266 // FIXME: Why don't we do this for inline asms with MRVs?
6267 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6268 EVT ResultType = TLI.getValueType(CS.getType());
6270 // If any of the results of the inline asm is a vector, it may have the
6271 // wrong width/num elts. This can happen for register classes that can
6272 // contain multiple different value types. The preg or vreg allocated may
6273 // not have the same VT as was expected. Convert it to the right type
6274 // with bit_convert.
6275 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6276 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(),
6279 } else if (ResultType != Val.getValueType() &&
6280 ResultType.isInteger() && Val.getValueType().isInteger()) {
6281 // If a result value was tied to an input value, the computed result may
6282 // have a wider width than the expected result. Extract the relevant
6284 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val);
6287 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6290 setValue(CS.getInstruction(), Val);
6291 // Don't need to use this as a chain in this case.
6292 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6296 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6298 // Process indirect outputs, first output all of the flagged copies out of
6300 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6301 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6302 const Value *Ptr = IndirectStoresToEmit[i].second;
6303 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(),
6305 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6308 // Emit the non-flagged stores from the physregs.
6309 SmallVector<SDValue, 8> OutChains;
6310 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6311 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(),
6312 StoresToEmit[i].first,
6313 getValue(StoresToEmit[i].second),
6314 MachinePointerInfo(StoresToEmit[i].second),
6316 OutChains.push_back(Val);
6319 if (!OutChains.empty())
6320 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
6321 &OutChains[0], OutChains.size());
6326 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6327 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
6328 MVT::Other, getRoot(),
6329 getValue(I.getArgOperand(0)),
6330 DAG.getSrcValue(I.getArgOperand(0))));
6333 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6334 const TargetData &TD = *TLI.getTargetData();
6335 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(),
6336 getRoot(), getValue(I.getOperand(0)),
6337 DAG.getSrcValue(I.getOperand(0)),
6338 TD.getABITypeAlignment(I.getType()));
6340 DAG.setRoot(V.getValue(1));
6343 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6344 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
6345 MVT::Other, getRoot(),
6346 getValue(I.getArgOperand(0)),
6347 DAG.getSrcValue(I.getArgOperand(0))));
6350 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6351 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
6352 MVT::Other, getRoot(),
6353 getValue(I.getArgOperand(0)),
6354 getValue(I.getArgOperand(1)),
6355 DAG.getSrcValue(I.getArgOperand(0)),
6356 DAG.getSrcValue(I.getArgOperand(1))));
6359 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6360 /// implementation, which just calls LowerCall.
6361 /// FIXME: When all targets are
6362 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6363 std::pair<SDValue, SDValue>
6364 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
6365 bool RetSExt, bool RetZExt, bool isVarArg,
6366 bool isInreg, unsigned NumFixedArgs,
6367 CallingConv::ID CallConv, bool isTailCall,
6368 bool doesNotRet, bool isReturnValueUsed,
6370 ArgListTy &Args, SelectionDAG &DAG,
6371 DebugLoc dl) const {
6372 // Handle all of the outgoing arguments.
6373 SmallVector<ISD::OutputArg, 32> Outs;
6374 SmallVector<SDValue, 32> OutVals;
6375 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
6376 SmallVector<EVT, 4> ValueVTs;
6377 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
6378 for (unsigned Value = 0, NumValues = ValueVTs.size();
6379 Value != NumValues; ++Value) {
6380 EVT VT = ValueVTs[Value];
6381 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext());
6382 SDValue Op = SDValue(Args[i].Node.getNode(),
6383 Args[i].Node.getResNo() + Value);
6384 ISD::ArgFlagsTy Flags;
6385 unsigned OriginalAlignment =
6386 getTargetData()->getABITypeAlignment(ArgTy);
6392 if (Args[i].isInReg)
6396 if (Args[i].isByVal) {
6398 PointerType *Ty = cast<PointerType>(Args[i].Ty);
6399 Type *ElementTy = Ty->getElementType();
6400 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy));
6401 // For ByVal, alignment should come from FE. BE will guess if this
6402 // info is not there but there are cases it cannot get right.
6403 unsigned FrameAlign;
6404 if (Args[i].Alignment)
6405 FrameAlign = Args[i].Alignment;
6407 FrameAlign = getByValTypeAlignment(ElementTy);
6408 Flags.setByValAlign(FrameAlign);
6412 Flags.setOrigAlign(OriginalAlignment);
6414 EVT PartVT = getRegisterType(RetTy->getContext(), VT);
6415 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT);
6416 SmallVector<SDValue, 4> Parts(NumParts);
6417 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
6420 ExtendKind = ISD::SIGN_EXTEND;
6421 else if (Args[i].isZExt)
6422 ExtendKind = ISD::ZERO_EXTEND;
6424 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts,
6425 PartVT, ExtendKind);
6427 for (unsigned j = 0; j != NumParts; ++j) {
6428 // if it isn't first piece, alignment must be 1
6429 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(),
6431 if (NumParts > 1 && j == 0)
6432 MyFlags.Flags.setSplit();
6434 MyFlags.Flags.setOrigAlign(1);
6436 Outs.push_back(MyFlags);
6437 OutVals.push_back(Parts[j]);
6442 // Handle the incoming return values from the call.
6443 SmallVector<ISD::InputArg, 32> Ins;
6444 SmallVector<EVT, 4> RetTys;
6445 ComputeValueVTs(*this, RetTy, RetTys);
6446 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6448 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6449 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6450 for (unsigned i = 0; i != NumRegs; ++i) {
6451 ISD::InputArg MyFlags;
6452 MyFlags.VT = RegisterVT.getSimpleVT();
6453 MyFlags.Used = isReturnValueUsed;
6455 MyFlags.Flags.setSExt();
6457 MyFlags.Flags.setZExt();
6459 MyFlags.Flags.setInReg();
6460 Ins.push_back(MyFlags);
6464 SmallVector<SDValue, 4> InVals;
6465 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, doesNotRet, isTailCall,
6466 Outs, OutVals, Ins, dl, DAG, InVals);
6468 // Verify that the target's LowerCall behaved as expected.
6469 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
6470 "LowerCall didn't return a valid chain!");
6471 assert((!isTailCall || InVals.empty()) &&
6472 "LowerCall emitted a return value for a tail call!");
6473 assert((isTailCall || InVals.size() == Ins.size()) &&
6474 "LowerCall didn't emit the correct number of values!");
6476 // For a tail call, the return value is merely live-out and there aren't
6477 // any nodes in the DAG representing it. Return a special value to
6478 // indicate that a tail call has been emitted and no more Instructions
6479 // should be processed in the current block.
6482 return std::make_pair(SDValue(), SDValue());
6485 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6486 assert(InVals[i].getNode() &&
6487 "LowerCall emitted a null value!");
6488 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6489 "LowerCall emitted a value with the wrong type!");
6492 // Collect the legal value parts into potentially illegal values
6493 // that correspond to the original function's return values.
6494 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6496 AssertOp = ISD::AssertSext;
6498 AssertOp = ISD::AssertZext;
6499 SmallVector<SDValue, 4> ReturnValues;
6500 unsigned CurReg = 0;
6501 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
6503 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT);
6504 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT);
6506 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg],
6507 NumRegs, RegisterVT, VT,
6512 // For a function returning void, there is no return value. We can't create
6513 // such a node, so we just return a null return value in that case. In
6514 // that case, nothing will actually look at the value.
6515 if (ReturnValues.empty())
6516 return std::make_pair(SDValue(), Chain);
6518 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
6519 DAG.getVTList(&RetTys[0], RetTys.size()),
6520 &ReturnValues[0], ReturnValues.size());
6521 return std::make_pair(Res, Chain);
6524 void TargetLowering::LowerOperationWrapper(SDNode *N,
6525 SmallVectorImpl<SDValue> &Results,
6526 SelectionDAG &DAG) const {
6527 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
6529 Results.push_back(Res);
6532 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6533 llvm_unreachable("LowerOperation not implemented for this target!");
6537 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
6538 SDValue Op = getNonRegisterValue(V);
6539 assert((Op.getOpcode() != ISD::CopyFromReg ||
6540 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
6541 "Copy from a reg to the same reg!");
6542 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
6544 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType());
6545 SDValue Chain = DAG.getEntryNode();
6546 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0);
6547 PendingExports.push_back(Chain);
6550 #include "llvm/CodeGen/SelectionDAGISel.h"
6552 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
6553 /// entry block, return true. This includes arguments used by switches, since
6554 /// the switch may expand into multiple basic blocks.
6555 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
6556 // With FastISel active, we may be splitting blocks, so force creation
6557 // of virtual registers for all non-dead arguments.
6559 return A->use_empty();
6561 const BasicBlock *Entry = A->getParent()->begin();
6562 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end();
6564 const User *U = *UI;
6565 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
6566 return false; // Use not in entry block.
6571 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) {
6572 // If this is the entry block, emit arguments.
6573 const Function &F = *LLVMBB->getParent();
6574 SelectionDAG &DAG = SDB->DAG;
6575 DebugLoc dl = SDB->getCurDebugLoc();
6576 const TargetData *TD = TLI.getTargetData();
6577 SmallVector<ISD::InputArg, 16> Ins;
6579 // Check whether the function can return without sret-demotion.
6580 SmallVector<ISD::OutputArg, 4> Outs;
6581 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
6584 if (!FuncInfo->CanLowerReturn) {
6585 // Put in an sret pointer parameter before all the other parameters.
6586 SmallVector<EVT, 1> ValueVTs;
6587 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6589 // NOTE: Assuming that a pointer will never break down to more than one VT
6591 ISD::ArgFlagsTy Flags;
6593 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]);
6594 ISD::InputArg RetArg(Flags, RegisterVT, true);
6595 Ins.push_back(RetArg);
6598 // Set up the incoming argument description vector.
6600 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
6601 I != E; ++I, ++Idx) {
6602 SmallVector<EVT, 4> ValueVTs;
6603 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6604 bool isArgValueUsed = !I->use_empty();
6605 for (unsigned Value = 0, NumValues = ValueVTs.size();
6606 Value != NumValues; ++Value) {
6607 EVT VT = ValueVTs[Value];
6608 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
6609 ISD::ArgFlagsTy Flags;
6610 unsigned OriginalAlignment =
6611 TD->getABITypeAlignment(ArgTy);
6613 if (F.paramHasAttr(Idx, Attribute::ZExt))
6615 if (F.paramHasAttr(Idx, Attribute::SExt))
6617 if (F.paramHasAttr(Idx, Attribute::InReg))
6619 if (F.paramHasAttr(Idx, Attribute::StructRet))
6621 if (F.paramHasAttr(Idx, Attribute::ByVal)) {
6623 PointerType *Ty = cast<PointerType>(I->getType());
6624 Type *ElementTy = Ty->getElementType();
6625 Flags.setByValSize(TD->getTypeAllocSize(ElementTy));
6626 // For ByVal, alignment should be passed from FE. BE will guess if
6627 // this info is not there but there are cases it cannot get right.
6628 unsigned FrameAlign;
6629 if (F.getParamAlignment(Idx))
6630 FrameAlign = F.getParamAlignment(Idx);
6632 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
6633 Flags.setByValAlign(FrameAlign);
6635 if (F.paramHasAttr(Idx, Attribute::Nest))
6637 Flags.setOrigAlign(OriginalAlignment);
6639 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6640 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6641 for (unsigned i = 0; i != NumRegs; ++i) {
6642 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
6643 if (NumRegs > 1 && i == 0)
6644 MyFlags.Flags.setSplit();
6645 // if it isn't first piece, alignment must be 1
6647 MyFlags.Flags.setOrigAlign(1);
6648 Ins.push_back(MyFlags);
6653 // Call the target to set up the argument values.
6654 SmallVector<SDValue, 8> InVals;
6655 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
6659 // Verify that the target's LowerFormalArguments behaved as expected.
6660 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
6661 "LowerFormalArguments didn't return a valid chain!");
6662 assert(InVals.size() == Ins.size() &&
6663 "LowerFormalArguments didn't emit the correct number of values!");
6665 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6666 assert(InVals[i].getNode() &&
6667 "LowerFormalArguments emitted a null value!");
6668 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6669 "LowerFormalArguments emitted a value with the wrong type!");
6673 // Update the DAG with the new chain value resulting from argument lowering.
6674 DAG.setRoot(NewRoot);
6676 // Set up the argument values.
6679 if (!FuncInfo->CanLowerReturn) {
6680 // Create a virtual register for the sret pointer, and put in a copy
6681 // from the sret argument into it.
6682 SmallVector<EVT, 1> ValueVTs;
6683 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
6684 EVT VT = ValueVTs[0];
6685 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6686 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6687 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
6688 RegVT, VT, AssertOp);
6690 MachineFunction& MF = SDB->DAG.getMachineFunction();
6691 MachineRegisterInfo& RegInfo = MF.getRegInfo();
6692 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT));
6693 FuncInfo->DemoteRegister = SRetReg;
6694 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(),
6696 DAG.setRoot(NewRoot);
6698 // i indexes lowered arguments. Bump it past the hidden sret argument.
6699 // Idx indexes LLVM arguments. Don't touch it.
6703 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
6705 SmallVector<SDValue, 4> ArgValues;
6706 SmallVector<EVT, 4> ValueVTs;
6707 ComputeValueVTs(TLI, I->getType(), ValueVTs);
6708 unsigned NumValues = ValueVTs.size();
6710 // If this argument is unused then remember its value. It is used to generate
6711 // debugging information.
6712 if (I->use_empty() && NumValues)
6713 SDB->setUnusedArgValue(I, InVals[i]);
6715 for (unsigned Val = 0; Val != NumValues; ++Val) {
6716 EVT VT = ValueVTs[Val];
6717 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT);
6718 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT);
6720 if (!I->use_empty()) {
6721 ISD::NodeType AssertOp = ISD::DELETED_NODE;
6722 if (F.paramHasAttr(Idx, Attribute::SExt))
6723 AssertOp = ISD::AssertSext;
6724 else if (F.paramHasAttr(Idx, Attribute::ZExt))
6725 AssertOp = ISD::AssertZext;
6727 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
6728 NumParts, PartVT, VT,
6735 // We don't need to do anything else for unused arguments.
6736 if (ArgValues.empty())
6739 // Note down frame index.
6740 if (FrameIndexSDNode *FI =
6741 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
6742 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6744 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
6745 SDB->getCurDebugLoc());
6747 SDB->setValue(I, Res);
6748 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
6749 if (LoadSDNode *LNode =
6750 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
6751 if (FrameIndexSDNode *FI =
6752 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6753 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
6756 // If this argument is live outside of the entry block, insert a copy from
6757 // wherever we got it to the vreg that other BB's will reference it as.
6758 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
6759 // If we can, though, try to skip creating an unnecessary vreg.
6760 // FIXME: This isn't very clean... it would be nice to make this more
6761 // general. It's also subtly incompatible with the hacks FastISel
6763 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
6764 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
6765 FuncInfo->ValueMap[I] = Reg;
6769 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
6770 FuncInfo->InitializeRegForValue(I);
6771 SDB->CopyToExportRegsIfNeeded(I);
6775 assert(i == InVals.size() && "Argument register count mismatch!");
6777 // Finally, if the target has anything special to do, allow it to do so.
6778 // FIXME: this should insert code into the DAG!
6779 EmitFunctionEntryCode();
6782 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
6783 /// ensure constants are generated when needed. Remember the virtual registers
6784 /// that need to be added to the Machine PHI nodes as input. We cannot just
6785 /// directly add them, because expansion might result in multiple MBB's for one
6786 /// BB. As such, the start of the BB might correspond to a different MBB than
6790 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
6791 const TerminatorInst *TI = LLVMBB->getTerminator();
6793 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
6795 // Check successor nodes' PHI nodes that expect a constant to be available
6797 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
6798 const BasicBlock *SuccBB = TI->getSuccessor(succ);
6799 if (!isa<PHINode>(SuccBB->begin())) continue;
6800 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
6802 // If this terminator has multiple identical successors (common for
6803 // switches), only handle each succ once.
6804 if (!SuccsHandled.insert(SuccMBB)) continue;
6806 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
6808 // At this point we know that there is a 1-1 correspondence between LLVM PHI
6809 // nodes and Machine PHI nodes, but the incoming operands have not been
6811 for (BasicBlock::const_iterator I = SuccBB->begin();
6812 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
6813 // Ignore dead phi's.
6814 if (PN->use_empty()) continue;
6817 if (PN->getType()->isEmptyTy())
6821 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
6823 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
6824 unsigned &RegOut = ConstantsOut[C];
6826 RegOut = FuncInfo.CreateRegs(C->getType());
6827 CopyValueToVirtualRegister(C, RegOut);
6831 DenseMap<const Value *, unsigned>::iterator I =
6832 FuncInfo.ValueMap.find(PHIOp);
6833 if (I != FuncInfo.ValueMap.end())
6836 assert(isa<AllocaInst>(PHIOp) &&
6837 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
6838 "Didn't codegen value into a register!??");
6839 Reg = FuncInfo.CreateRegs(PHIOp->getType());
6840 CopyValueToVirtualRegister(PHIOp, Reg);
6844 // Remember that this register needs to added to the machine PHI node as
6845 // the input for this MBB.
6846 SmallVector<EVT, 4> ValueVTs;
6847 ComputeValueVTs(TLI, PN->getType(), ValueVTs);
6848 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
6849 EVT VT = ValueVTs[vti];
6850 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
6851 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
6852 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
6853 Reg += NumRegisters;
6857 ConstantsOut.clear();