1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/ConstantFolding.h"
22 #include "llvm/Analysis/ValueTracking.h"
23 #include "llvm/CodeGen/Analysis.h"
24 #include "llvm/CodeGen/FastISel.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/GCMetadata.h"
27 #include "llvm/CodeGen/GCStrategy.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/StackMaps.h"
36 #include "llvm/IR/CallingConv.h"
37 #include "llvm/IR/Constants.h"
38 #include "llvm/IR/DataLayout.h"
39 #include "llvm/IR/DebugInfo.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/InlineAsm.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/IntrinsicInst.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/IR/LLVMContext.h"
48 #include "llvm/IR/Module.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetFrameLowering.h"
55 #include "llvm/Target/TargetInstrInfo.h"
56 #include "llvm/Target/TargetIntrinsicInfo.h"
57 #include "llvm/Target/TargetLibraryInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetOptions.h"
60 #include "llvm/Target/TargetSelectionDAGInfo.h"
64 #define DEBUG_TYPE "isel"
66 /// LimitFloatPrecision - Generate low-precision inline sequences for
67 /// some float libcalls (6, 8 or 12 bits).
68 static unsigned LimitFloatPrecision;
70 static cl::opt<unsigned, true>
71 LimitFPPrecision("limit-float-precision",
72 cl::desc("Generate low-precision inline sequences "
73 "for some float libcalls"),
74 cl::location(LimitFloatPrecision),
77 // Limit the width of DAG chains. This is important in general to prevent
78 // prevent DAG-based analysis from blowing up. For example, alias analysis and
79 // load clustering may not complete in reasonable time. It is difficult to
80 // recognize and avoid this situation within each individual analysis, and
81 // future analyses are likely to have the same behavior. Limiting DAG width is
82 // the safe approach, and will be especially important with global DAGs.
84 // MaxParallelChains default is arbitrarily high to avoid affecting
85 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
86 // sequence over this should have been converted to llvm.memcpy by the
87 // frontend. It easy to induce this behavior with .ll code such as:
88 // %buffer = alloca [4096 x i8]
89 // %data = load [4096 x i8]* %argPtr
90 // store [4096 x i8] %data, [4096 x i8]* %buffer
91 static const unsigned MaxParallelChains = 64;
93 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
94 const SDValue *Parts, unsigned NumParts,
95 MVT PartVT, EVT ValueVT, const Value *V);
97 /// getCopyFromParts - Create a value that contains the specified legal parts
98 /// combined into the value they represent. If the parts combine to a type
99 /// larger then ValueVT then AssertOp can be used to specify whether the extra
100 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
101 /// (ISD::AssertSext).
102 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
103 const SDValue *Parts,
104 unsigned NumParts, MVT PartVT, EVT ValueVT,
106 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
107 if (ValueVT.isVector())
108 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
111 assert(NumParts > 0 && "No parts to assemble!");
112 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
113 SDValue Val = Parts[0];
116 // Assemble the value from multiple parts.
117 if (ValueVT.isInteger()) {
118 unsigned PartBits = PartVT.getSizeInBits();
119 unsigned ValueBits = ValueVT.getSizeInBits();
121 // Assemble the power of 2 part.
122 unsigned RoundParts = NumParts & (NumParts - 1) ?
123 1 << Log2_32(NumParts) : NumParts;
124 unsigned RoundBits = PartBits * RoundParts;
125 EVT RoundVT = RoundBits == ValueBits ?
126 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
129 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
131 if (RoundParts > 2) {
132 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
134 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
135 RoundParts / 2, PartVT, HalfVT, V);
137 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
138 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
141 if (TLI.isBigEndian())
144 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
146 if (RoundParts < NumParts) {
147 // Assemble the trailing non-power-of-2 part.
148 unsigned OddParts = NumParts - RoundParts;
149 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
150 Hi = getCopyFromParts(DAG, DL,
151 Parts + RoundParts, OddParts, PartVT, OddVT, V);
153 // Combine the round and odd parts.
155 if (TLI.isBigEndian())
157 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
158 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
159 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
160 DAG.getConstant(Lo.getValueType().getSizeInBits(),
161 TLI.getPointerTy()));
162 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
163 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
165 } else if (PartVT.isFloatingPoint()) {
166 // FP split into multiple FP parts (for ppcf128)
167 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
170 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
171 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
172 if (TLI.isBigEndian())
174 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
176 // FP split into integer parts (soft fp)
177 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
178 !PartVT.isVector() && "Unexpected split");
179 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
180 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
184 // There is now one part, held in Val. Correct it to match ValueVT.
185 EVT PartEVT = Val.getValueType();
187 if (PartEVT == ValueVT)
190 if (PartEVT.isInteger() && ValueVT.isInteger()) {
191 if (ValueVT.bitsLT(PartEVT)) {
192 // For a truncate, see if we have any information to
193 // indicate whether the truncated bits will always be
194 // zero or sign-extension.
195 if (AssertOp != ISD::DELETED_NODE)
196 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
197 DAG.getValueType(ValueVT));
198 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
200 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
203 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
204 // FP_ROUND's are always exact here.
205 if (ValueVT.bitsLT(Val.getValueType()))
206 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
207 DAG.getTargetConstant(1, TLI.getPointerTy()));
209 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
212 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
213 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
215 llvm_unreachable("Unknown mismatch!");
218 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
219 const Twine &ErrMsg) {
220 const Instruction *I = dyn_cast_or_null<Instruction>(V);
222 return Ctx.emitError(ErrMsg);
224 const char *AsmError = ", possible invalid constraint for vector type";
225 if (const CallInst *CI = dyn_cast<CallInst>(I))
226 if (isa<InlineAsm>(CI->getCalledValue()))
227 return Ctx.emitError(I, ErrMsg + AsmError);
229 return Ctx.emitError(I, ErrMsg);
232 /// getCopyFromPartsVector - Create a value that contains the specified legal
233 /// parts combined into the value they represent. If the parts combine to a
234 /// type larger then ValueVT then AssertOp can be used to specify whether the
235 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
236 /// ValueVT (ISD::AssertSext).
237 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
238 const SDValue *Parts, unsigned NumParts,
239 MVT PartVT, EVT ValueVT, const Value *V) {
240 assert(ValueVT.isVector() && "Not a vector value");
241 assert(NumParts > 0 && "No parts to assemble!");
242 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
243 SDValue Val = Parts[0];
245 // Handle a multi-element vector.
249 unsigned NumIntermediates;
251 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
252 NumIntermediates, RegisterVT);
253 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
254 NumParts = NumRegs; // Silence a compiler warning.
255 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
256 assert(RegisterVT == Parts[0].getSimpleValueType() &&
257 "Part type doesn't match part!");
259 // Assemble the parts into intermediate operands.
260 SmallVector<SDValue, 8> Ops(NumIntermediates);
261 if (NumIntermediates == NumParts) {
262 // If the register was not expanded, truncate or copy the value,
264 for (unsigned i = 0; i != NumParts; ++i)
265 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
266 PartVT, IntermediateVT, V);
267 } else if (NumParts > 0) {
268 // If the intermediate type was expanded, build the intermediate
269 // operands from the parts.
270 assert(NumParts % NumIntermediates == 0 &&
271 "Must expand into a divisible number of parts!");
272 unsigned Factor = NumParts / NumIntermediates;
273 for (unsigned i = 0; i != NumIntermediates; ++i)
274 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
275 PartVT, IntermediateVT, V);
278 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
279 // intermediate operands.
280 Val = DAG.getNode(IntermediateVT.isVector() ?
281 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL,
282 ValueVT, &Ops[0], NumIntermediates);
285 // There is now one part, held in Val. Correct it to match ValueVT.
286 EVT PartEVT = Val.getValueType();
288 if (PartEVT == ValueVT)
291 if (PartEVT.isVector()) {
292 // If the element type of the source/dest vectors are the same, but the
293 // parts vector has more elements than the value vector, then we have a
294 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
296 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
297 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
298 "Cannot narrow, it would be a lossy transformation");
299 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
300 DAG.getConstant(0, TLI.getVectorIdxTy()));
303 // Vector/Vector bitcast.
304 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
305 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
307 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
308 "Cannot handle this kind of promotion");
309 // Promoted vector extract
310 bool Smaller = ValueVT.bitsLE(PartEVT);
311 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
316 // Trivial bitcast if the types are the same size and the destination
317 // vector type is legal.
318 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
319 TLI.isTypeLegal(ValueVT))
320 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
322 // Handle cases such as i8 -> <1 x i1>
323 if (ValueVT.getVectorNumElements() != 1) {
324 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
325 "non-trivial scalar-to-vector conversion");
326 return DAG.getUNDEF(ValueVT);
329 if (ValueVT.getVectorNumElements() == 1 &&
330 ValueVT.getVectorElementType() != PartEVT) {
331 bool Smaller = ValueVT.bitsLE(PartEVT);
332 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
333 DL, ValueVT.getScalarType(), Val);
336 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
339 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
340 SDValue Val, SDValue *Parts, unsigned NumParts,
341 MVT PartVT, const Value *V);
343 /// getCopyToParts - Create a series of nodes that contain the specified value
344 /// split into legal parts. If the parts contain more bits than Val, then, for
345 /// integers, ExtendKind can be used to specify how to generate the extra bits.
346 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
347 SDValue Val, SDValue *Parts, unsigned NumParts,
348 MVT PartVT, const Value *V,
349 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
350 EVT ValueVT = Val.getValueType();
352 // Handle the vector case separately.
353 if (ValueVT.isVector())
354 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
356 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
357 unsigned PartBits = PartVT.getSizeInBits();
358 unsigned OrigNumParts = NumParts;
359 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
364 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
365 EVT PartEVT = PartVT;
366 if (PartEVT == ValueVT) {
367 assert(NumParts == 1 && "No-op copy with multiple parts!");
372 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
373 // If the parts cover more bits than the value has, promote the value.
374 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
375 assert(NumParts == 1 && "Do not know what to promote to!");
376 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
378 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
379 ValueVT.isInteger() &&
380 "Unknown mismatch!");
381 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
382 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
383 if (PartVT == MVT::x86mmx)
384 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
386 } else if (PartBits == ValueVT.getSizeInBits()) {
387 // Different types of the same size.
388 assert(NumParts == 1 && PartEVT != ValueVT);
389 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
390 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
391 // If the parts cover less bits than value has, truncate the value.
392 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
393 ValueVT.isInteger() &&
394 "Unknown mismatch!");
395 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
396 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
397 if (PartVT == MVT::x86mmx)
398 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
401 // The value may have changed - recompute ValueVT.
402 ValueVT = Val.getValueType();
403 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
404 "Failed to tile the value with PartVT!");
407 if (PartEVT != ValueVT)
408 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
409 "scalar-to-vector conversion failed");
415 // Expand the value into multiple parts.
416 if (NumParts & (NumParts - 1)) {
417 // The number of parts is not a power of 2. Split off and copy the tail.
418 assert(PartVT.isInteger() && ValueVT.isInteger() &&
419 "Do not know what to expand to!");
420 unsigned RoundParts = 1 << Log2_32(NumParts);
421 unsigned RoundBits = RoundParts * PartBits;
422 unsigned OddParts = NumParts - RoundParts;
423 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
424 DAG.getIntPtrConstant(RoundBits));
425 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
427 if (TLI.isBigEndian())
428 // The odd parts were reversed by getCopyToParts - unreverse them.
429 std::reverse(Parts + RoundParts, Parts + NumParts);
431 NumParts = RoundParts;
432 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
433 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
436 // The number of parts is a power of 2. Repeatedly bisect the value using
438 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
439 EVT::getIntegerVT(*DAG.getContext(),
440 ValueVT.getSizeInBits()),
443 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
444 for (unsigned i = 0; i < NumParts; i += StepSize) {
445 unsigned ThisBits = StepSize * PartBits / 2;
446 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
447 SDValue &Part0 = Parts[i];
448 SDValue &Part1 = Parts[i+StepSize/2];
450 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
451 ThisVT, Part0, DAG.getIntPtrConstant(1));
452 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
453 ThisVT, Part0, DAG.getIntPtrConstant(0));
455 if (ThisBits == PartBits && ThisVT != PartVT) {
456 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
457 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
462 if (TLI.isBigEndian())
463 std::reverse(Parts, Parts + OrigNumParts);
467 /// getCopyToPartsVector - Create a series of nodes that contain the specified
468 /// value split into legal parts.
469 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
470 SDValue Val, SDValue *Parts, unsigned NumParts,
471 MVT PartVT, const Value *V) {
472 EVT ValueVT = Val.getValueType();
473 assert(ValueVT.isVector() && "Not a vector");
474 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
477 EVT PartEVT = PartVT;
478 if (PartEVT == ValueVT) {
480 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
481 // Bitconvert vector->vector case.
482 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
483 } else if (PartVT.isVector() &&
484 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
485 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
486 EVT ElementVT = PartVT.getVectorElementType();
487 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
489 SmallVector<SDValue, 16> Ops;
490 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
491 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
492 ElementVT, Val, DAG.getConstant(i,
493 TLI.getVectorIdxTy())));
495 for (unsigned i = ValueVT.getVectorNumElements(),
496 e = PartVT.getVectorNumElements(); i != e; ++i)
497 Ops.push_back(DAG.getUNDEF(ElementVT));
499 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size());
501 // FIXME: Use CONCAT for 2x -> 4x.
503 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
504 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
505 } else if (PartVT.isVector() &&
506 PartEVT.getVectorElementType().bitsGE(
507 ValueVT.getVectorElementType()) &&
508 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
510 // Promoted vector extract
511 bool Smaller = PartEVT.bitsLE(ValueVT);
512 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
515 // Vector -> scalar conversion.
516 assert(ValueVT.getVectorNumElements() == 1 &&
517 "Only trivial vector-to-scalar conversions should get here!");
518 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
519 PartVT, Val, DAG.getConstant(0, TLI.getVectorIdxTy()));
521 bool Smaller = ValueVT.bitsLE(PartVT);
522 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND),
530 // Handle a multi-element vector.
533 unsigned NumIntermediates;
534 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
536 NumIntermediates, RegisterVT);
537 unsigned NumElements = ValueVT.getVectorNumElements();
539 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
540 NumParts = NumRegs; // Silence a compiler warning.
541 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
543 // Split the vector into intermediate operands.
544 SmallVector<SDValue, 8> Ops(NumIntermediates);
545 for (unsigned i = 0; i != NumIntermediates; ++i) {
546 if (IntermediateVT.isVector())
547 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL,
549 DAG.getConstant(i * (NumElements / NumIntermediates),
550 TLI.getVectorIdxTy()));
552 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
554 DAG.getConstant(i, TLI.getVectorIdxTy()));
557 // Split the intermediate operands into legal parts.
558 if (NumParts == NumIntermediates) {
559 // If the register was not expanded, promote or copy the value,
561 for (unsigned i = 0; i != NumParts; ++i)
562 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
563 } else if (NumParts > 0) {
564 // If the intermediate type was expanded, split each the value into
566 assert(NumParts % NumIntermediates == 0 &&
567 "Must expand into a divisible number of parts!");
568 unsigned Factor = NumParts / NumIntermediates;
569 for (unsigned i = 0; i != NumIntermediates; ++i)
570 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
575 /// RegsForValue - This struct represents the registers (physical or virtual)
576 /// that a particular set of values is assigned, and the type information
577 /// about the value. The most common situation is to represent one value at a
578 /// time, but struct or array values are handled element-wise as multiple
579 /// values. The splitting of aggregates is performed recursively, so that we
580 /// never have aggregate-typed registers. The values at this point do not
581 /// necessarily have legal types, so each value may require one or more
582 /// registers of some legal type.
584 struct RegsForValue {
585 /// ValueVTs - The value types of the values, which may not be legal, and
586 /// may need be promoted or synthesized from one or more registers.
588 SmallVector<EVT, 4> ValueVTs;
590 /// RegVTs - The value types of the registers. This is the same size as
591 /// ValueVTs and it records, for each value, what the type of the assigned
592 /// register or registers are. (Individual values are never synthesized
593 /// from more than one type of register.)
595 /// With virtual registers, the contents of RegVTs is redundant with TLI's
596 /// getRegisterType member function, however when with physical registers
597 /// it is necessary to have a separate record of the types.
599 SmallVector<MVT, 4> RegVTs;
601 /// Regs - This list holds the registers assigned to the values.
602 /// Each legal or promoted value requires one register, and each
603 /// expanded value requires multiple registers.
605 SmallVector<unsigned, 4> Regs;
609 RegsForValue(const SmallVector<unsigned, 4> ®s,
610 MVT regvt, EVT valuevt)
611 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
613 RegsForValue(LLVMContext &Context, const TargetLowering &tli,
614 unsigned Reg, Type *Ty) {
615 ComputeValueVTs(tli, Ty, ValueVTs);
617 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
618 EVT ValueVT = ValueVTs[Value];
619 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT);
620 MVT RegisterVT = tli.getRegisterType(Context, ValueVT);
621 for (unsigned i = 0; i != NumRegs; ++i)
622 Regs.push_back(Reg + i);
623 RegVTs.push_back(RegisterVT);
628 /// append - Add the specified values to this one.
629 void append(const RegsForValue &RHS) {
630 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end());
631 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end());
632 Regs.append(RHS.Regs.begin(), RHS.Regs.end());
635 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
636 /// this value and returns the result as a ValueVTs value. This uses
637 /// Chain/Flag as the input and updates them for the output Chain/Flag.
638 /// If the Flag pointer is NULL, no flag is used.
639 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo,
641 SDValue &Chain, SDValue *Flag,
642 const Value *V = nullptr) const;
644 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
645 /// specified value into the registers specified by this object. This uses
646 /// Chain/Flag as the input and updates them for the output Chain/Flag.
647 /// If the Flag pointer is NULL, no flag is used.
648 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
649 SDValue &Chain, SDValue *Flag, const Value *V) const;
651 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
652 /// operand list. This adds the code marker, matching input operand index
653 /// (if applicable), and includes the number of values added into it.
654 void AddInlineAsmOperands(unsigned Kind,
655 bool HasMatching, unsigned MatchingIdx,
657 std::vector<SDValue> &Ops) const;
661 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
662 /// this value and returns the result as a ValueVT value. This uses
663 /// Chain/Flag as the input and updates them for the output Chain/Flag.
664 /// If the Flag pointer is NULL, no flag is used.
665 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
666 FunctionLoweringInfo &FuncInfo,
668 SDValue &Chain, SDValue *Flag,
669 const Value *V) const {
670 // A Value with type {} or [0 x %t] needs no registers.
671 if (ValueVTs.empty())
674 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
676 // Assemble the legal parts into the final values.
677 SmallVector<SDValue, 4> Values(ValueVTs.size());
678 SmallVector<SDValue, 8> Parts;
679 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
680 // Copy the legal parts from the registers.
681 EVT ValueVT = ValueVTs[Value];
682 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
683 MVT RegisterVT = RegVTs[Value];
685 Parts.resize(NumRegs);
686 for (unsigned i = 0; i != NumRegs; ++i) {
689 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
691 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
692 *Flag = P.getValue(2);
695 Chain = P.getValue(1);
698 // If the source register was virtual and if we know something about it,
699 // add an assert node.
700 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
701 !RegisterVT.isInteger() || RegisterVT.isVector())
704 const FunctionLoweringInfo::LiveOutInfo *LOI =
705 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
709 unsigned RegSize = RegisterVT.getSizeInBits();
710 unsigned NumSignBits = LOI->NumSignBits;
711 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
713 if (NumZeroBits == RegSize) {
714 // The current value is a zero.
715 // Explicitly express that as it would be easier for
716 // optimizations to kick in.
717 Parts[i] = DAG.getConstant(0, RegisterVT);
721 // FIXME: We capture more information than the dag can represent. For
722 // now, just use the tightest assertzext/assertsext possible.
724 EVT FromVT(MVT::Other);
725 if (NumSignBits == RegSize)
726 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
727 else if (NumZeroBits >= RegSize-1)
728 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
729 else if (NumSignBits > RegSize-8)
730 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
731 else if (NumZeroBits >= RegSize-8)
732 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
733 else if (NumSignBits > RegSize-16)
734 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
735 else if (NumZeroBits >= RegSize-16)
736 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
737 else if (NumSignBits > RegSize-32)
738 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
739 else if (NumZeroBits >= RegSize-32)
740 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
744 // Add an assertion node.
745 assert(FromVT != MVT::Other);
746 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
747 RegisterVT, P, DAG.getValueType(FromVT));
750 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
751 NumRegs, RegisterVT, ValueVT, V);
756 return DAG.getNode(ISD::MERGE_VALUES, dl,
757 DAG.getVTList(ValueVTs),
758 &Values[0], ValueVTs.size());
761 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
762 /// specified value into the registers specified by this object. This uses
763 /// Chain/Flag as the input and updates them for the output Chain/Flag.
764 /// If the Flag pointer is NULL, no flag is used.
765 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
766 SDValue &Chain, SDValue *Flag,
767 const Value *V) const {
768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
770 // Get the list of the values's legal parts.
771 unsigned NumRegs = Regs.size();
772 SmallVector<SDValue, 8> Parts(NumRegs);
773 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
774 EVT ValueVT = ValueVTs[Value];
775 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
776 MVT RegisterVT = RegVTs[Value];
777 ISD::NodeType ExtendKind =
778 TLI.isZExtFree(Val, RegisterVT)? ISD::ZERO_EXTEND: ISD::ANY_EXTEND;
780 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
781 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
785 // Copy the parts into the registers.
786 SmallVector<SDValue, 8> Chains(NumRegs);
787 for (unsigned i = 0; i != NumRegs; ++i) {
790 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
792 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
793 *Flag = Part.getValue(1);
796 Chains[i] = Part.getValue(0);
799 if (NumRegs == 1 || Flag)
800 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
801 // flagged to it. That is the CopyToReg nodes and the user are considered
802 // a single scheduling unit. If we create a TokenFactor and return it as
803 // chain, then the TokenFactor is both a predecessor (operand) of the
804 // user as well as a successor (the TF operands are flagged to the user).
805 // c1, f1 = CopyToReg
806 // c2, f2 = CopyToReg
807 // c3 = TokenFactor c1, c2
810 Chain = Chains[NumRegs-1];
812 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
815 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
816 /// operand list. This adds the code marker and includes the number of
817 /// values added into it.
818 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
819 unsigned MatchingIdx,
821 std::vector<SDValue> &Ops) const {
822 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
824 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
826 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
827 else if (!Regs.empty() &&
828 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
829 // Put the register class of the virtual registers in the flag word. That
830 // way, later passes can recompute register class constraints for inline
831 // assembly as well as normal instructions.
832 // Don't do this for tied operands that can use the regclass information
834 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
835 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
836 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
839 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32);
842 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
843 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
844 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
845 MVT RegisterVT = RegVTs[Value];
846 for (unsigned i = 0; i != NumRegs; ++i) {
847 assert(Reg < Regs.size() && "Mismatch in # registers expected");
848 unsigned TheReg = Regs[Reg++];
849 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
851 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
852 // If we clobbered the stack pointer, MFI should know about it.
853 assert(DAG.getMachineFunction().getFrameInfo()->
854 hasInlineAsmWithSPAdjust());
860 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
861 const TargetLibraryInfo *li) {
865 DL = DAG.getTarget().getDataLayout();
866 Context = DAG.getContext();
867 LPadToCallSiteMap.clear();
870 /// clear - Clear out the current SelectionDAG and the associated
871 /// state and prepare this SelectionDAGBuilder object to be used
872 /// for a new block. This doesn't clear out information about
873 /// additional blocks that are needed to complete switch lowering
874 /// or PHI node updating; that information is cleared out as it is
876 void SelectionDAGBuilder::clear() {
878 UnusedArgNodeMap.clear();
879 PendingLoads.clear();
880 PendingExports.clear();
883 SDNodeOrder = LowestSDNodeOrder;
886 /// clearDanglingDebugInfo - Clear the dangling debug information
887 /// map. This function is separated from the clear so that debug
888 /// information that is dangling in a basic block can be properly
889 /// resolved in a different basic block. This allows the
890 /// SelectionDAG to resolve dangling debug information attached
892 void SelectionDAGBuilder::clearDanglingDebugInfo() {
893 DanglingDebugInfoMap.clear();
896 /// getRoot - Return the current virtual root of the Selection DAG,
897 /// flushing any PendingLoad items. This must be done before emitting
898 /// a store or any other node that may need to be ordered after any
899 /// prior load instructions.
901 SDValue SelectionDAGBuilder::getRoot() {
902 if (PendingLoads.empty())
903 return DAG.getRoot();
905 if (PendingLoads.size() == 1) {
906 SDValue Root = PendingLoads[0];
908 PendingLoads.clear();
912 // Otherwise, we have to make a token factor node.
913 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
914 &PendingLoads[0], PendingLoads.size());
915 PendingLoads.clear();
920 /// getControlRoot - Similar to getRoot, but instead of flushing all the
921 /// PendingLoad items, flush all the PendingExports items. It is necessary
922 /// to do this before emitting a terminator instruction.
924 SDValue SelectionDAGBuilder::getControlRoot() {
925 SDValue Root = DAG.getRoot();
927 if (PendingExports.empty())
930 // Turn all of the CopyToReg chains into one factored node.
931 if (Root.getOpcode() != ISD::EntryToken) {
932 unsigned i = 0, e = PendingExports.size();
933 for (; i != e; ++i) {
934 assert(PendingExports[i].getNode()->getNumOperands() > 1);
935 if (PendingExports[i].getNode()->getOperand(0) == Root)
936 break; // Don't add the root if we already indirectly depend on it.
940 PendingExports.push_back(Root);
943 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
945 PendingExports.size());
946 PendingExports.clear();
951 void SelectionDAGBuilder::visit(const Instruction &I) {
952 // Set up outgoing PHI node register values before emitting the terminator.
953 if (isa<TerminatorInst>(&I))
954 HandlePHINodesInSuccessorBlocks(I.getParent());
960 visit(I.getOpcode(), I);
962 if (!isa<TerminatorInst>(&I) && !HasTailCall)
963 CopyToExportRegsIfNeeded(&I);
968 void SelectionDAGBuilder::visitPHI(const PHINode &) {
969 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
972 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
973 // Note: this doesn't use InstVisitor, because it has to work with
974 // ConstantExpr's in addition to instructions.
976 default: llvm_unreachable("Unknown instruction type encountered!");
977 // Build the switch statement using the Instruction.def file.
978 #define HANDLE_INST(NUM, OPCODE, CLASS) \
979 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
980 #include "llvm/IR/Instruction.def"
984 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
985 // generate the debug data structures now that we've seen its definition.
986 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
988 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
990 const DbgValueInst *DI = DDI.getDI();
991 DebugLoc dl = DDI.getdl();
992 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
993 MDNode *Variable = DI->getVariable();
994 uint64_t Offset = DI->getOffset();
997 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) {
998 SDV = DAG.getDbgValue(Variable, Val.getNode(),
999 Val.getResNo(), Offset, dl, DbgSDNodeOrder);
1000 DAG.AddDbgValue(SDV, Val.getNode(), false);
1003 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1004 DanglingDebugInfoMap[V] = DanglingDebugInfo();
1008 /// getValue - Return an SDValue for the given Value.
1009 SDValue SelectionDAGBuilder::getValue(const Value *V) {
1010 // If we already have an SDValue for this value, use it. It's important
1011 // to do this first, so that we don't create a CopyFromReg if we already
1012 // have a regular SDValue.
1013 SDValue &N = NodeMap[V];
1014 if (N.getNode()) return N;
1016 // If there's a virtual register allocated and initialized for this
1018 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
1019 if (It != FuncInfo.ValueMap.end()) {
1020 unsigned InReg = It->second;
1021 RegsForValue RFV(*DAG.getContext(), *TM.getTargetLowering(),
1022 InReg, V->getType());
1023 SDValue Chain = DAG.getEntryNode();
1024 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1025 resolveDanglingDebugInfo(V, N);
1029 // Otherwise create a new SDValue and remember it.
1030 SDValue Val = getValueImpl(V);
1032 resolveDanglingDebugInfo(V, Val);
1036 /// getNonRegisterValue - Return an SDValue for the given Value, but
1037 /// don't look in FuncInfo.ValueMap for a virtual register.
1038 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1039 // If we already have an SDValue for this value, use it.
1040 SDValue &N = NodeMap[V];
1041 if (N.getNode()) return N;
1043 // Otherwise create a new SDValue and remember it.
1044 SDValue Val = getValueImpl(V);
1046 resolveDanglingDebugInfo(V, Val);
1050 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1051 /// Create an SDValue for the given value.
1052 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1053 const TargetLowering *TLI = TM.getTargetLowering();
1055 if (const Constant *C = dyn_cast<Constant>(V)) {
1056 EVT VT = TLI->getValueType(V->getType(), true);
1058 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1059 return DAG.getConstant(*CI, VT);
1061 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1062 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1064 if (isa<ConstantPointerNull>(C)) {
1065 unsigned AS = V->getType()->getPointerAddressSpace();
1066 return DAG.getConstant(0, TLI->getPointerTy(AS));
1069 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1070 return DAG.getConstantFP(*CFP, VT);
1072 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1073 return DAG.getUNDEF(VT);
1075 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1076 visit(CE->getOpcode(), *CE);
1077 SDValue N1 = NodeMap[V];
1078 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1082 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1083 SmallVector<SDValue, 4> Constants;
1084 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1086 SDNode *Val = getValue(*OI).getNode();
1087 // If the operand is an empty aggregate, there are no values.
1089 // Add each leaf value from the operand to the Constants list
1090 // to form a flattened list of all the values.
1091 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1092 Constants.push_back(SDValue(Val, i));
1095 return DAG.getMergeValues(&Constants[0], Constants.size(),
1099 if (const ConstantDataSequential *CDS =
1100 dyn_cast<ConstantDataSequential>(C)) {
1101 SmallVector<SDValue, 4> Ops;
1102 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1103 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1104 // Add each leaf value from the operand to the Constants list
1105 // to form a flattened list of all the values.
1106 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1107 Ops.push_back(SDValue(Val, i));
1110 if (isa<ArrayType>(CDS->getType()))
1111 return DAG.getMergeValues(&Ops[0], Ops.size(), getCurSDLoc());
1112 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1113 VT, &Ops[0], Ops.size());
1116 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1117 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1118 "Unknown struct or array constant!");
1120 SmallVector<EVT, 4> ValueVTs;
1121 ComputeValueVTs(*TLI, C->getType(), ValueVTs);
1122 unsigned NumElts = ValueVTs.size();
1124 return SDValue(); // empty struct
1125 SmallVector<SDValue, 4> Constants(NumElts);
1126 for (unsigned i = 0; i != NumElts; ++i) {
1127 EVT EltVT = ValueVTs[i];
1128 if (isa<UndefValue>(C))
1129 Constants[i] = DAG.getUNDEF(EltVT);
1130 else if (EltVT.isFloatingPoint())
1131 Constants[i] = DAG.getConstantFP(0, EltVT);
1133 Constants[i] = DAG.getConstant(0, EltVT);
1136 return DAG.getMergeValues(&Constants[0], NumElts,
1140 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1141 return DAG.getBlockAddress(BA, VT);
1143 VectorType *VecTy = cast<VectorType>(V->getType());
1144 unsigned NumElements = VecTy->getNumElements();
1146 // Now that we know the number and type of the elements, get that number of
1147 // elements into the Ops array based on what kind of constant it is.
1148 SmallVector<SDValue, 16> Ops;
1149 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1150 for (unsigned i = 0; i != NumElements; ++i)
1151 Ops.push_back(getValue(CV->getOperand(i)));
1153 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1154 EVT EltVT = TLI->getValueType(VecTy->getElementType());
1157 if (EltVT.isFloatingPoint())
1158 Op = DAG.getConstantFP(0, EltVT);
1160 Op = DAG.getConstant(0, EltVT);
1161 Ops.assign(NumElements, Op);
1164 // Create a BUILD_VECTOR node.
1165 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1166 VT, &Ops[0], Ops.size());
1169 // If this is a static alloca, generate it as the frameindex instead of
1171 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1172 DenseMap<const AllocaInst*, int>::iterator SI =
1173 FuncInfo.StaticAllocaMap.find(AI);
1174 if (SI != FuncInfo.StaticAllocaMap.end())
1175 return DAG.getFrameIndex(SI->second, TLI->getPointerTy());
1178 // If this is an instruction which fast-isel has deferred, select it now.
1179 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1180 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1181 RegsForValue RFV(*DAG.getContext(), *TLI, InReg, Inst->getType());
1182 SDValue Chain = DAG.getEntryNode();
1183 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1186 llvm_unreachable("Can't get register for value!");
1189 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1190 const TargetLowering *TLI = TM.getTargetLowering();
1191 SDValue Chain = getControlRoot();
1192 SmallVector<ISD::OutputArg, 8> Outs;
1193 SmallVector<SDValue, 8> OutVals;
1195 if (!FuncInfo.CanLowerReturn) {
1196 unsigned DemoteReg = FuncInfo.DemoteRegister;
1197 const Function *F = I.getParent()->getParent();
1199 // Emit a store of the return value through the virtual register.
1200 // Leave Outs empty so that LowerReturn won't try to load return
1201 // registers the usual way.
1202 SmallVector<EVT, 1> PtrValueVTs;
1203 ComputeValueVTs(*TLI, PointerType::getUnqual(F->getReturnType()),
1206 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1207 SDValue RetOp = getValue(I.getOperand(0));
1209 SmallVector<EVT, 4> ValueVTs;
1210 SmallVector<uint64_t, 4> Offsets;
1211 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1212 unsigned NumValues = ValueVTs.size();
1214 SmallVector<SDValue, 4> Chains(NumValues);
1215 for (unsigned i = 0; i != NumValues; ++i) {
1216 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1217 RetPtr.getValueType(), RetPtr,
1218 DAG.getIntPtrConstant(Offsets[i]));
1220 DAG.getStore(Chain, getCurSDLoc(),
1221 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1222 // FIXME: better loc info would be nice.
1223 Add, MachinePointerInfo(), false, false, 0);
1226 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1227 MVT::Other, &Chains[0], NumValues);
1228 } else if (I.getNumOperands() != 0) {
1229 SmallVector<EVT, 4> ValueVTs;
1230 ComputeValueVTs(*TLI, I.getOperand(0)->getType(), ValueVTs);
1231 unsigned NumValues = ValueVTs.size();
1233 SDValue RetOp = getValue(I.getOperand(0));
1234 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1235 EVT VT = ValueVTs[j];
1237 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1239 const Function *F = I.getParent()->getParent();
1240 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1242 ExtendKind = ISD::SIGN_EXTEND;
1243 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1245 ExtendKind = ISD::ZERO_EXTEND;
1247 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1248 VT = TLI->getTypeForExtArgOrReturn(VT.getSimpleVT(), ExtendKind);
1250 unsigned NumParts = TLI->getNumRegisters(*DAG.getContext(), VT);
1251 MVT PartVT = TLI->getRegisterType(*DAG.getContext(), VT);
1252 SmallVector<SDValue, 4> Parts(NumParts);
1253 getCopyToParts(DAG, getCurSDLoc(),
1254 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1255 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1257 // 'inreg' on function refers to return value
1258 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1259 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1263 // Propagate extension type if any
1264 if (ExtendKind == ISD::SIGN_EXTEND)
1266 else if (ExtendKind == ISD::ZERO_EXTEND)
1269 for (unsigned i = 0; i < NumParts; ++i) {
1270 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1271 VT, /*isfixed=*/true, 0, 0));
1272 OutVals.push_back(Parts[i]);
1278 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1279 CallingConv::ID CallConv =
1280 DAG.getMachineFunction().getFunction()->getCallingConv();
1281 Chain = TM.getTargetLowering()->LowerReturn(Chain, CallConv, isVarArg,
1282 Outs, OutVals, getCurSDLoc(),
1285 // Verify that the target's LowerReturn behaved as expected.
1286 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1287 "LowerReturn didn't return a valid chain!");
1289 // Update the DAG with the new chain value resulting from return lowering.
1293 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1294 /// created for it, emit nodes to copy the value into the virtual
1296 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1298 if (V->getType()->isEmptyTy())
1301 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1302 if (VMI != FuncInfo.ValueMap.end()) {
1303 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1304 CopyValueToVirtualRegister(V, VMI->second);
1308 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1309 /// the current basic block, add it to ValueMap now so that we'll get a
1311 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1312 // No need to export constants.
1313 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1315 // Already exported?
1316 if (FuncInfo.isExportedInst(V)) return;
1318 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1319 CopyValueToVirtualRegister(V, Reg);
1322 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1323 const BasicBlock *FromBB) {
1324 // The operands of the setcc have to be in this block. We don't know
1325 // how to export them from some other block.
1326 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1327 // Can export from current BB.
1328 if (VI->getParent() == FromBB)
1331 // Is already exported, noop.
1332 return FuncInfo.isExportedInst(V);
1335 // If this is an argument, we can export it if the BB is the entry block or
1336 // if it is already exported.
1337 if (isa<Argument>(V)) {
1338 if (FromBB == &FromBB->getParent()->getEntryBlock())
1341 // Otherwise, can only export this if it is already exported.
1342 return FuncInfo.isExportedInst(V);
1345 // Otherwise, constants can always be exported.
1349 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1350 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1351 const MachineBasicBlock *Dst) const {
1352 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1355 const BasicBlock *SrcBB = Src->getBasicBlock();
1356 const BasicBlock *DstBB = Dst->getBasicBlock();
1357 return BPI->getEdgeWeight(SrcBB, DstBB);
1360 void SelectionDAGBuilder::
1361 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1362 uint32_t Weight /* = 0 */) {
1364 Weight = getEdgeWeight(Src, Dst);
1365 Src->addSuccessor(Dst, Weight);
1369 static bool InBlock(const Value *V, const BasicBlock *BB) {
1370 if (const Instruction *I = dyn_cast<Instruction>(V))
1371 return I->getParent() == BB;
1375 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1376 /// This function emits a branch and is used at the leaves of an OR or an
1377 /// AND operator tree.
1380 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1381 MachineBasicBlock *TBB,
1382 MachineBasicBlock *FBB,
1383 MachineBasicBlock *CurBB,
1384 MachineBasicBlock *SwitchBB,
1387 const BasicBlock *BB = CurBB->getBasicBlock();
1389 // If the leaf of the tree is a comparison, merge the condition into
1391 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1392 // The operands of the cmp have to be in this block. We don't know
1393 // how to export them from some other block. If this is the first block
1394 // of the sequence, no exporting is needed.
1395 if (CurBB == SwitchBB ||
1396 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1397 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1398 ISD::CondCode Condition;
1399 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1400 Condition = getICmpCondCode(IC->getPredicate());
1401 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) {
1402 Condition = getFCmpCondCode(FC->getPredicate());
1403 if (TM.Options.NoNaNsFPMath)
1404 Condition = getFCmpCodeWithoutNaN(Condition);
1406 Condition = ISD::SETEQ; // silence warning.
1407 llvm_unreachable("Unknown compare instruction");
1410 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1411 TBB, FBB, CurBB, TWeight, FWeight);
1412 SwitchCases.push_back(CB);
1417 // Create a CaseBlock record representing this branch.
1418 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1419 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1420 SwitchCases.push_back(CB);
1423 /// Scale down both weights to fit into uint32_t.
1424 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1425 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1426 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1427 NewTrue = NewTrue / Scale;
1428 NewFalse = NewFalse / Scale;
1431 /// FindMergedConditions - If Cond is an expression like
1432 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1433 MachineBasicBlock *TBB,
1434 MachineBasicBlock *FBB,
1435 MachineBasicBlock *CurBB,
1436 MachineBasicBlock *SwitchBB,
1437 unsigned Opc, uint32_t TWeight,
1439 // If this node is not part of the or/and tree, emit it as a branch.
1440 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1441 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1442 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1443 BOp->getParent() != CurBB->getBasicBlock() ||
1444 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1445 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1446 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1451 // Create TmpBB after CurBB.
1452 MachineFunction::iterator BBI = CurBB;
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1455 CurBB->getParent()->insert(++BBI, TmpBB);
1457 if (Opc == Instruction::Or) {
1458 // Codegen X | Y as:
1467 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1468 // The requirement is that
1469 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1470 // = TrueProb for orignal BB.
1471 // Assuming the orignal weights are A and B, one choice is to set BB1's
1472 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1474 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1475 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1476 // TmpBB, but the math is more complicated.
1478 uint64_t NewTrueWeight = TWeight;
1479 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1480 ScaleWeights(NewTrueWeight, NewFalseWeight);
1481 // Emit the LHS condition.
1482 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1483 NewTrueWeight, NewFalseWeight);
1485 NewTrueWeight = TWeight;
1486 NewFalseWeight = 2 * (uint64_t)FWeight;
1487 ScaleWeights(NewTrueWeight, NewFalseWeight);
1488 // Emit the RHS condition into TmpBB.
1489 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1490 NewTrueWeight, NewFalseWeight);
1492 assert(Opc == Instruction::And && "Unknown merge op!");
1493 // Codegen X & Y as:
1501 // This requires creation of TmpBB after CurBB.
1503 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1504 // The requirement is that
1505 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1506 // = FalseProb for orignal BB.
1507 // Assuming the orignal weights are A and B, one choice is to set BB1's
1508 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1510 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1512 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1513 uint64_t NewFalseWeight = FWeight;
1514 ScaleWeights(NewTrueWeight, NewFalseWeight);
1515 // Emit the LHS condition.
1516 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1517 NewTrueWeight, NewFalseWeight);
1519 NewTrueWeight = 2 * (uint64_t)TWeight;
1520 NewFalseWeight = FWeight;
1521 ScaleWeights(NewTrueWeight, NewFalseWeight);
1522 // Emit the RHS condition into TmpBB.
1523 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1524 NewTrueWeight, NewFalseWeight);
1528 /// If the set of cases should be emitted as a series of branches, return true.
1529 /// If we should emit this as a bunch of and/or'd together conditions, return
1532 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1533 if (Cases.size() != 2) return true;
1535 // If this is two comparisons of the same values or'd or and'd together, they
1536 // will get folded into a single comparison, so don't emit two blocks.
1537 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1538 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1539 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1540 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1544 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1545 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1546 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1547 Cases[0].CC == Cases[1].CC &&
1548 isa<Constant>(Cases[0].CmpRHS) &&
1549 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1550 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1552 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1559 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1560 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1562 // Update machine-CFG edges.
1563 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1565 // Figure out which block is immediately after the current one.
1566 MachineBasicBlock *NextBlock = nullptr;
1567 MachineFunction::iterator BBI = BrMBB;
1568 if (++BBI != FuncInfo.MF->end())
1571 if (I.isUnconditional()) {
1572 // Update machine-CFG edges.
1573 BrMBB->addSuccessor(Succ0MBB);
1575 // If this is not a fall-through branch or optimizations are switched off,
1577 if (Succ0MBB != NextBlock || TM.getOptLevel() == CodeGenOpt::None)
1578 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1579 MVT::Other, getControlRoot(),
1580 DAG.getBasicBlock(Succ0MBB)));
1585 // If this condition is one of the special cases we handle, do special stuff
1587 const Value *CondVal = I.getCondition();
1588 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1590 // If this is a series of conditions that are or'd or and'd together, emit
1591 // this as a sequence of branches instead of setcc's with and/or operations.
1592 // As long as jumps are not expensive, this should improve performance.
1593 // For example, instead of something like:
1606 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1607 if (!TM.getTargetLowering()->isJumpExpensive() &&
1609 (BOp->getOpcode() == Instruction::And ||
1610 BOp->getOpcode() == Instruction::Or)) {
1611 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1612 BOp->getOpcode(), getEdgeWeight(BrMBB, Succ0MBB),
1613 getEdgeWeight(BrMBB, Succ1MBB));
1614 // If the compares in later blocks need to use values not currently
1615 // exported from this block, export them now. This block should always
1616 // be the first entry.
1617 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1619 // Allow some cases to be rejected.
1620 if (ShouldEmitAsBranches(SwitchCases)) {
1621 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1622 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1623 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1626 // Emit the branch for this block.
1627 visitSwitchCase(SwitchCases[0], BrMBB);
1628 SwitchCases.erase(SwitchCases.begin());
1632 // Okay, we decided not to do this, remove any inserted MBB's and clear
1634 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1635 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1637 SwitchCases.clear();
1641 // Create a CaseBlock record representing this branch.
1642 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1643 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1645 // Use visitSwitchCase to actually insert the fast branch sequence for this
1647 visitSwitchCase(CB, BrMBB);
1650 /// visitSwitchCase - Emits the necessary code to represent a single node in
1651 /// the binary search tree resulting from lowering a switch instruction.
1652 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1653 MachineBasicBlock *SwitchBB) {
1655 SDValue CondLHS = getValue(CB.CmpLHS);
1656 SDLoc dl = getCurSDLoc();
1658 // Build the setcc now.
1660 // Fold "(X == true)" to X and "(X == false)" to !X to
1661 // handle common cases produced by branch lowering.
1662 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1663 CB.CC == ISD::SETEQ)
1665 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1666 CB.CC == ISD::SETEQ) {
1667 SDValue True = DAG.getConstant(1, CondLHS.getValueType());
1668 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1670 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1672 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1674 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1675 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1677 SDValue CmpOp = getValue(CB.CmpMHS);
1678 EVT VT = CmpOp.getValueType();
1680 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1681 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1684 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1685 VT, CmpOp, DAG.getConstant(Low, VT));
1686 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1687 DAG.getConstant(High-Low, VT), ISD::SETULE);
1691 // Update successor info
1692 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1693 // TrueBB and FalseBB are always different unless the incoming IR is
1694 // degenerate. This only happens when running llc on weird IR.
1695 if (CB.TrueBB != CB.FalseBB)
1696 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1698 // Set NextBlock to be the MBB immediately after the current one, if any.
1699 // This is used to avoid emitting unnecessary branches to the next block.
1700 MachineBasicBlock *NextBlock = nullptr;
1701 MachineFunction::iterator BBI = SwitchBB;
1702 if (++BBI != FuncInfo.MF->end())
1705 // If the lhs block is the next block, invert the condition so that we can
1706 // fall through to the lhs instead of the rhs block.
1707 if (CB.TrueBB == NextBlock) {
1708 std::swap(CB.TrueBB, CB.FalseBB);
1709 SDValue True = DAG.getConstant(1, Cond.getValueType());
1710 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1713 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1714 MVT::Other, getControlRoot(), Cond,
1715 DAG.getBasicBlock(CB.TrueBB));
1717 // Insert the false branch. Do this even if it's a fall through branch,
1718 // this makes it easier to do DAG optimizations which require inverting
1719 // the branch condition.
1720 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1721 DAG.getBasicBlock(CB.FalseBB));
1723 DAG.setRoot(BrCond);
1726 /// visitJumpTable - Emit JumpTable node in the current MBB
1727 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1728 // Emit the code for the jump table
1729 assert(JT.Reg != -1U && "Should lower JT Header first!");
1730 EVT PTy = TM.getTargetLowering()->getPointerTy();
1731 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1733 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1734 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1735 MVT::Other, Index.getValue(1),
1737 DAG.setRoot(BrJumpTable);
1740 /// visitJumpTableHeader - This function emits necessary code to produce index
1741 /// in the JumpTable from switch case.
1742 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1743 JumpTableHeader &JTH,
1744 MachineBasicBlock *SwitchBB) {
1745 // Subtract the lowest switch case value from the value being switched on and
1746 // conditional branch to default mbb if the result is greater than the
1747 // difference between smallest and largest cases.
1748 SDValue SwitchOp = getValue(JTH.SValue);
1749 EVT VT = SwitchOp.getValueType();
1750 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1751 DAG.getConstant(JTH.First, VT));
1753 // The SDNode we just created, which holds the value being switched on minus
1754 // the smallest case value, needs to be copied to a virtual register so it
1755 // can be used as an index into the jump table in a subsequent basic block.
1756 // This value may be smaller or larger than the target's pointer type, and
1757 // therefore require extension or truncating.
1758 const TargetLowering *TLI = TM.getTargetLowering();
1759 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), TLI->getPointerTy());
1761 unsigned JumpTableReg = FuncInfo.CreateReg(TLI->getPointerTy());
1762 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1763 JumpTableReg, SwitchOp);
1764 JT.Reg = JumpTableReg;
1766 // Emit the range check for the jump table, and branch to the default block
1767 // for the switch statement if the value being switched on exceeds the largest
1768 // case in the switch.
1769 SDValue CMP = DAG.getSetCC(getCurSDLoc(),
1770 TLI->getSetCCResultType(*DAG.getContext(),
1771 Sub.getValueType()),
1773 DAG.getConstant(JTH.Last - JTH.First,VT),
1776 // Set NextBlock to be the MBB immediately after the current one, if any.
1777 // This is used to avoid emitting unnecessary branches to the next block.
1778 MachineBasicBlock *NextBlock = nullptr;
1779 MachineFunction::iterator BBI = SwitchBB;
1781 if (++BBI != FuncInfo.MF->end())
1784 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1785 MVT::Other, CopyTo, CMP,
1786 DAG.getBasicBlock(JT.Default));
1788 if (JT.MBB != NextBlock)
1789 BrCond = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrCond,
1790 DAG.getBasicBlock(JT.MBB));
1792 DAG.setRoot(BrCond);
1795 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1796 /// tail spliced into a stack protector check success bb.
1798 /// For a high level explanation of how this fits into the stack protector
1799 /// generation see the comment on the declaration of class
1800 /// StackProtectorDescriptor.
1801 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1802 MachineBasicBlock *ParentBB) {
1804 // First create the loads to the guard/stack slot for the comparison.
1805 const TargetLowering *TLI = TM.getTargetLowering();
1806 EVT PtrTy = TLI->getPointerTy();
1808 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1809 int FI = MFI->getStackProtectorIndex();
1811 const Value *IRGuard = SPD.getGuard();
1812 SDValue GuardPtr = getValue(IRGuard);
1813 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1816 TLI->getDataLayout()->getPrefTypeAlignment(IRGuard->getType());
1817 SDValue Guard = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1818 GuardPtr, MachinePointerInfo(IRGuard, 0),
1819 true, false, false, Align);
1821 SDValue StackSlot = DAG.getLoad(PtrTy, getCurSDLoc(), DAG.getEntryNode(),
1823 MachinePointerInfo::getFixedStack(FI),
1824 true, false, false, Align);
1826 // Perform the comparison via a subtract/getsetcc.
1827 EVT VT = Guard.getValueType();
1828 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, Guard, StackSlot);
1830 SDValue Cmp = DAG.getSetCC(getCurSDLoc(),
1831 TLI->getSetCCResultType(*DAG.getContext(),
1832 Sub.getValueType()),
1833 Sub, DAG.getConstant(0, VT),
1836 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1837 // branch to failure MBB.
1838 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1839 MVT::Other, StackSlot.getOperand(0),
1840 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1841 // Otherwise branch to success MBB.
1842 SDValue Br = DAG.getNode(ISD::BR, getCurSDLoc(),
1844 DAG.getBasicBlock(SPD.getSuccessMBB()));
1849 /// Codegen the failure basic block for a stack protector check.
1851 /// A failure stack protector machine basic block consists simply of a call to
1852 /// __stack_chk_fail().
1854 /// For a high level explanation of how this fits into the stack protector
1855 /// generation see the comment on the declaration of class
1856 /// StackProtectorDescriptor.
1858 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1859 const TargetLowering *TLI = TM.getTargetLowering();
1860 SDValue Chain = TLI->makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
1861 MVT::isVoid, nullptr, 0, false,
1862 getCurSDLoc(), false, false).second;
1866 /// visitBitTestHeader - This function emits necessary code to produce value
1867 /// suitable for "bit tests"
1868 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
1869 MachineBasicBlock *SwitchBB) {
1870 // Subtract the minimum value
1871 SDValue SwitchOp = getValue(B.SValue);
1872 EVT VT = SwitchOp.getValueType();
1873 SDValue Sub = DAG.getNode(ISD::SUB, getCurSDLoc(), VT, SwitchOp,
1874 DAG.getConstant(B.First, VT));
1877 const TargetLowering *TLI = TM.getTargetLowering();
1878 SDValue RangeCmp = DAG.getSetCC(getCurSDLoc(),
1879 TLI->getSetCCResultType(*DAG.getContext(),
1880 Sub.getValueType()),
1881 Sub, DAG.getConstant(B.Range, VT),
1884 // Determine the type of the test operands.
1885 bool UsePtrType = false;
1886 if (!TLI->isTypeLegal(VT))
1889 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
1890 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
1891 // Switch table case range are encoded into series of masks.
1892 // Just use pointer type, it's guaranteed to fit.
1898 VT = TLI->getPointerTy();
1899 Sub = DAG.getZExtOrTrunc(Sub, getCurSDLoc(), VT);
1902 B.RegVT = VT.getSimpleVT();
1903 B.Reg = FuncInfo.CreateReg(B.RegVT);
1904 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurSDLoc(),
1907 // Set NextBlock to be the MBB immediately after the current one, if any.
1908 // This is used to avoid emitting unnecessary branches to the next block.
1909 MachineBasicBlock *NextBlock = nullptr;
1910 MachineFunction::iterator BBI = SwitchBB;
1911 if (++BBI != FuncInfo.MF->end())
1914 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
1916 addSuccessorWithWeight(SwitchBB, B.Default);
1917 addSuccessorWithWeight(SwitchBB, MBB);
1919 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1920 MVT::Other, CopyTo, RangeCmp,
1921 DAG.getBasicBlock(B.Default));
1923 if (MBB != NextBlock)
1924 BrRange = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, CopyTo,
1925 DAG.getBasicBlock(MBB));
1927 DAG.setRoot(BrRange);
1930 /// visitBitTestCase - this function produces one "bit test"
1931 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
1932 MachineBasicBlock* NextMBB,
1933 uint32_t BranchWeightToNext,
1936 MachineBasicBlock *SwitchBB) {
1938 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1941 unsigned PopCount = CountPopulation_64(B.Mask);
1942 const TargetLowering *TLI = TM.getTargetLowering();
1943 if (PopCount == 1) {
1944 // Testing for a single bit; just compare the shift count with what it
1945 // would need to be to shift a 1 bit in that position.
1946 Cmp = DAG.getSetCC(getCurSDLoc(),
1947 TLI->getSetCCResultType(*DAG.getContext(), VT),
1949 DAG.getConstant(countTrailingZeros(B.Mask), VT),
1951 } else if (PopCount == BB.Range) {
1952 // There is only one zero bit in the range, test for it directly.
1953 Cmp = DAG.getSetCC(getCurSDLoc(),
1954 TLI->getSetCCResultType(*DAG.getContext(), VT),
1956 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT),
1959 // Make desired shift
1960 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurSDLoc(), VT,
1961 DAG.getConstant(1, VT), ShiftOp);
1963 // Emit bit tests and jumps
1964 SDValue AndOp = DAG.getNode(ISD::AND, getCurSDLoc(),
1965 VT, SwitchVal, DAG.getConstant(B.Mask, VT));
1966 Cmp = DAG.getSetCC(getCurSDLoc(),
1967 TLI->getSetCCResultType(*DAG.getContext(), VT),
1968 AndOp, DAG.getConstant(0, VT),
1972 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
1973 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
1974 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
1975 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
1977 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurSDLoc(),
1978 MVT::Other, getControlRoot(),
1979 Cmp, DAG.getBasicBlock(B.TargetBB));
1981 // Set NextBlock to be the MBB immediately after the current one, if any.
1982 // This is used to avoid emitting unnecessary branches to the next block.
1983 MachineBasicBlock *NextBlock = nullptr;
1984 MachineFunction::iterator BBI = SwitchBB;
1985 if (++BBI != FuncInfo.MF->end())
1988 if (NextMBB != NextBlock)
1989 BrAnd = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, BrAnd,
1990 DAG.getBasicBlock(NextMBB));
1995 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1996 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1998 // Retrieve successors.
1999 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2000 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)];
2002 const Value *Callee(I.getCalledValue());
2003 const Function *Fn = dyn_cast<Function>(Callee);
2004 if (isa<InlineAsm>(Callee))
2006 else if (Fn && Fn->isIntrinsic()) {
2007 assert(Fn->getIntrinsicID() == Intrinsic::donothing);
2008 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2010 LowerCallTo(&I, getValue(Callee), false, LandingPad);
2012 // If the value of the invoke is used outside of its defining block, make it
2013 // available as a virtual register.
2014 CopyToExportRegsIfNeeded(&I);
2016 // Update successor info
2017 addSuccessorWithWeight(InvokeMBB, Return);
2018 addSuccessorWithWeight(InvokeMBB, LandingPad);
2020 // Drop into normal successor.
2021 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2022 MVT::Other, getControlRoot(),
2023 DAG.getBasicBlock(Return)));
2026 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2027 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2030 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2031 assert(FuncInfo.MBB->isLandingPad() &&
2032 "Call to landingpad not in landing pad!");
2034 MachineBasicBlock *MBB = FuncInfo.MBB;
2035 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2036 AddLandingPadInfo(LP, MMI, MBB);
2038 // If there aren't registers to copy the values into (e.g., during SjLj
2039 // exceptions), then don't bother to create these DAG nodes.
2040 const TargetLowering *TLI = TM.getTargetLowering();
2041 if (TLI->getExceptionPointerRegister() == 0 &&
2042 TLI->getExceptionSelectorRegister() == 0)
2045 SmallVector<EVT, 2> ValueVTs;
2046 ComputeValueVTs(*TLI, LP.getType(), ValueVTs);
2047 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2049 // Get the two live-in registers as SDValues. The physregs have already been
2050 // copied into virtual registers.
2052 Ops[0] = DAG.getZExtOrTrunc(
2053 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2054 FuncInfo.ExceptionPointerVirtReg, TLI->getPointerTy()),
2055 getCurSDLoc(), ValueVTs[0]);
2056 Ops[1] = DAG.getZExtOrTrunc(
2057 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(),
2058 FuncInfo.ExceptionSelectorVirtReg, TLI->getPointerTy()),
2059 getCurSDLoc(), ValueVTs[1]);
2062 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2063 DAG.getVTList(ValueVTs),
2068 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for
2069 /// small case ranges).
2070 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
2071 CaseRecVector& WorkList,
2073 MachineBasicBlock *Default,
2074 MachineBasicBlock *SwitchBB) {
2075 // Size is the number of Cases represented by this range.
2076 size_t Size = CR.Range.second - CR.Range.first;
2080 // Get the MachineFunction which holds the current MBB. This is used when
2081 // inserting any additional MBBs necessary to represent the switch.
2082 MachineFunction *CurMF = FuncInfo.MF;
2084 // Figure out which block is immediately after the current one.
2085 MachineBasicBlock *NextBlock = nullptr;
2086 MachineFunction::iterator BBI = CR.CaseBB;
2088 if (++BBI != FuncInfo.MF->end())
2091 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2092 // If any two of the cases has the same destination, and if one value
2093 // is the same as the other, but has one bit unset that the other has set,
2094 // use bit manipulation to do two compares at once. For example:
2095 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
2096 // TODO: This could be extended to merge any 2 cases in switches with 3 cases.
2097 // TODO: Handle cases where CR.CaseBB != SwitchBB.
2098 if (Size == 2 && CR.CaseBB == SwitchBB) {
2099 Case &Small = *CR.Range.first;
2100 Case &Big = *(CR.Range.second-1);
2102 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) {
2103 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue();
2104 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue();
2106 // Check that there is only one bit different.
2107 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 &&
2108 (SmallValue | BigValue) == BigValue) {
2109 // Isolate the common bit.
2110 APInt CommonBit = BigValue & ~SmallValue;
2111 assert((SmallValue | CommonBit) == BigValue &&
2112 CommonBit.countPopulation() == 1 && "Not a common bit?");
2114 SDValue CondLHS = getValue(SV);
2115 EVT VT = CondLHS.getValueType();
2116 SDLoc DL = getCurSDLoc();
2118 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
2119 DAG.getConstant(CommonBit, VT));
2120 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
2121 Or, DAG.getConstant(BigValue, VT),
2124 // Update successor info.
2125 // Both Small and Big will jump to Small.BB, so we sum up the weights.
2126 addSuccessorWithWeight(SwitchBB, Small.BB,
2127 Small.ExtraWeight + Big.ExtraWeight);
2128 addSuccessorWithWeight(SwitchBB, Default,
2129 // The default destination is the first successor in IR.
2130 BPI ? BPI->getEdgeWeight(SwitchBB->getBasicBlock(), (unsigned)0) : 0);
2132 // Insert the true branch.
2133 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other,
2134 getControlRoot(), Cond,
2135 DAG.getBasicBlock(Small.BB));
2137 // Insert the false branch.
2138 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
2139 DAG.getBasicBlock(Default));
2141 DAG.setRoot(BrCond);
2147 // Order cases by weight so the most likely case will be checked first.
2148 uint32_t UnhandledWeights = 0;
2150 for (CaseItr I = CR.Range.first, IE = CR.Range.second; I != IE; ++I) {
2151 uint32_t IWeight = I->ExtraWeight;
2152 UnhandledWeights += IWeight;
2153 for (CaseItr J = CR.Range.first; J < I; ++J) {
2154 uint32_t JWeight = J->ExtraWeight;
2155 if (IWeight > JWeight)
2160 // Rearrange the case blocks so that the last one falls through if possible.
2161 Case &BackCase = *(CR.Range.second-1);
2163 NextBlock && Default != NextBlock && BackCase.BB != NextBlock) {
2164 // The last case block won't fall through into 'NextBlock' if we emit the
2165 // branches in this order. See if rearranging a case value would help.
2166 // We start at the bottom as it's the case with the least weight.
2167 for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
2168 if (I->BB == NextBlock) {
2169 std::swap(*I, BackCase);
2174 // Create a CaseBlock record representing a conditional branch to
2175 // the Case's target mbb if the value being switched on SV is equal
2177 MachineBasicBlock *CurBlock = CR.CaseBB;
2178 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2179 MachineBasicBlock *FallThrough;
2181 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock());
2182 CurMF->insert(BBI, FallThrough);
2184 // Put SV in a virtual register to make it available from the new blocks.
2185 ExportFromCurrentBlock(SV);
2187 // If the last case doesn't match, go to the default block.
2188 FallThrough = Default;
2191 const Value *RHS, *LHS, *MHS;
2193 if (I->High == I->Low) {
2194 // This is just small small case range :) containing exactly 1 case
2196 LHS = SV; RHS = I->High; MHS = nullptr;
2199 LHS = I->Low; MHS = SV; RHS = I->High;
2202 // The false weight should be sum of all un-handled cases.
2203 UnhandledWeights -= I->ExtraWeight;
2204 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough,
2206 /* trueweight */ I->ExtraWeight,
2207 /* falseweight */ UnhandledWeights);
2209 // If emitting the first comparison, just call visitSwitchCase to emit the
2210 // code into the current block. Otherwise, push the CaseBlock onto the
2211 // vector to be later processed by SDISel, and insert the node's MBB
2212 // before the next MBB.
2213 if (CurBlock == SwitchBB)
2214 visitSwitchCase(CB, SwitchBB);
2216 SwitchCases.push_back(CB);
2218 CurBlock = FallThrough;
2224 static inline bool areJTsAllowed(const TargetLowering &TLI) {
2225 return TLI.supportJumpTables() &&
2226 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
2227 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
2230 static APInt ComputeRange(const APInt &First, const APInt &Last) {
2231 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1;
2232 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth);
2233 return (LastExt - FirstExt + 1ULL);
2236 /// handleJTSwitchCase - Emit jumptable for current switch case range
2237 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
2238 CaseRecVector &WorkList,
2240 MachineBasicBlock *Default,
2241 MachineBasicBlock *SwitchBB) {
2242 Case& FrontCase = *CR.Range.first;
2243 Case& BackCase = *(CR.Range.second-1);
2245 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2246 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2248 APInt TSize(First.getBitWidth(), 0);
2249 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I)
2252 const TargetLowering *TLI = TM.getTargetLowering();
2253 if (!areJTsAllowed(*TLI) || TSize.ult(TLI->getMinimumJumpTableEntries()))
2256 APInt Range = ComputeRange(First, Last);
2257 // The density is TSize / Range. Require at least 40%.
2258 // It should not be possible for IntTSize to saturate for sane code, but make
2259 // sure we handle Range saturation correctly.
2260 uint64_t IntRange = Range.getLimitedValue(UINT64_MAX/10);
2261 uint64_t IntTSize = TSize.getLimitedValue(UINT64_MAX/10);
2262 if (IntTSize * 10 < IntRange * 4)
2265 DEBUG(dbgs() << "Lowering jump table\n"
2266 << "First entry: " << First << ". Last entry: " << Last << '\n'
2267 << "Range: " << Range << ". Size: " << TSize << ".\n\n");
2269 // Get the MachineFunction which holds the current MBB. This is used when
2270 // inserting any additional MBBs necessary to represent the switch.
2271 MachineFunction *CurMF = FuncInfo.MF;
2273 // Figure out which block is immediately after the current one.
2274 MachineFunction::iterator BBI = CR.CaseBB;
2277 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2279 // Create a new basic block to hold the code for loading the address
2280 // of the jump table, and jumping to it. Update successor information;
2281 // we will either branch to the default case for the switch, or the jump
2283 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2284 CurMF->insert(BBI, JumpTableBB);
2286 addSuccessorWithWeight(CR.CaseBB, Default);
2287 addSuccessorWithWeight(CR.CaseBB, JumpTableBB);
2289 // Build a vector of destination BBs, corresponding to each target
2290 // of the jump table. If the value of the jump table slot corresponds to
2291 // a case statement, push the case's BB onto the vector, otherwise, push
2293 std::vector<MachineBasicBlock*> DestBBs;
2295 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) {
2296 const APInt &Low = cast<ConstantInt>(I->Low)->getValue();
2297 const APInt &High = cast<ConstantInt>(I->High)->getValue();
2299 if (Low.sle(TEI) && TEI.sle(High)) {
2300 DestBBs.push_back(I->BB);
2304 DestBBs.push_back(Default);
2308 // Calculate weight for each unique destination in CR.
2309 DenseMap<MachineBasicBlock*, uint32_t> DestWeights;
2311 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) {
2312 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2313 DestWeights.find(I->BB);
2314 if (Itr != DestWeights.end())
2315 Itr->second += I->ExtraWeight;
2317 DestWeights[I->BB] = I->ExtraWeight;
2320 // Update successor info. Add one edge to each unique successor.
2321 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs());
2322 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(),
2323 E = DestBBs.end(); I != E; ++I) {
2324 if (!SuccsHandled[(*I)->getNumber()]) {
2325 SuccsHandled[(*I)->getNumber()] = true;
2326 DenseMap<MachineBasicBlock*, uint32_t>::iterator Itr =
2327 DestWeights.find(*I);
2328 addSuccessorWithWeight(JumpTableBB, *I,
2329 Itr != DestWeights.end() ? Itr->second : 0);
2333 // Create a jump table index for this jump table.
2334 unsigned JTEncoding = TLI->getJumpTableEncoding();
2335 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding)
2336 ->createJumpTableIndex(DestBBs);
2338 // Set the jump table information so that we can codegen it as a second
2339 // MachineBasicBlock
2340 JumpTable JT(-1U, JTI, JumpTableBB, Default);
2341 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB));
2342 if (CR.CaseBB == SwitchBB)
2343 visitJumpTableHeader(JT, JTH, SwitchBB);
2345 JTCases.push_back(JumpTableBlock(JTH, JT));
2349 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into
2351 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
2352 CaseRecVector& WorkList,
2354 MachineBasicBlock* Default,
2355 MachineBasicBlock* SwitchBB) {
2356 // Get the MachineFunction which holds the current MBB. This is used when
2357 // inserting any additional MBBs necessary to represent the switch.
2358 MachineFunction *CurMF = FuncInfo.MF;
2360 // Figure out which block is immediately after the current one.
2361 MachineFunction::iterator BBI = CR.CaseBB;
2364 Case& FrontCase = *CR.Range.first;
2365 Case& BackCase = *(CR.Range.second-1);
2366 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2368 // Size is the number of Cases represented by this range.
2369 unsigned Size = CR.Range.second - CR.Range.first;
2371 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue();
2372 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue();
2374 CaseItr Pivot = CR.Range.first + Size/2;
2376 // Select optimal pivot, maximizing sum density of LHS and RHS. This will
2377 // (heuristically) allow us to emit JumpTable's later.
2378 APInt TSize(First.getBitWidth(), 0);
2379 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2383 APInt LSize = FrontCase.size();
2384 APInt RSize = TSize-LSize;
2385 DEBUG(dbgs() << "Selecting best pivot: \n"
2386 << "First: " << First << ", Last: " << Last <<'\n'
2387 << "LSize: " << LSize << ", RSize: " << RSize << '\n');
2388 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second;
2390 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue();
2391 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue();
2392 APInt Range = ComputeRange(LEnd, RBegin);
2393 assert((Range - 2ULL).isNonNegative() &&
2394 "Invalid case distance");
2395 // Use volatile double here to avoid excess precision issues on some hosts,
2396 // e.g. that use 80-bit X87 registers.
2397 volatile double LDensity =
2398 (double)LSize.roundToDouble() /
2399 (LEnd - First + 1ULL).roundToDouble();
2400 volatile double RDensity =
2401 (double)RSize.roundToDouble() /
2402 (Last - RBegin + 1ULL).roundToDouble();
2403 volatile double Metric = Range.logBase2()*(LDensity+RDensity);
2404 // Should always split in some non-trivial place
2405 DEBUG(dbgs() <<"=>Step\n"
2406 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n'
2407 << "LDensity: " << LDensity
2408 << ", RDensity: " << RDensity << '\n'
2409 << "Metric: " << Metric << '\n');
2410 if (FMetric < Metric) {
2413 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n');
2420 const TargetLowering *TLI = TM.getTargetLowering();
2421 if (areJTsAllowed(*TLI)) {
2422 // If our case is dense we *really* should handle it earlier!
2423 assert((FMetric > 0) && "Should handle dense range earlier!");
2425 Pivot = CR.Range.first + Size/2;
2428 CaseRange LHSR(CR.Range.first, Pivot);
2429 CaseRange RHSR(Pivot, CR.Range.second);
2430 const Constant *C = Pivot->Low;
2431 MachineBasicBlock *FalseBB = nullptr, *TrueBB = nullptr;
2433 // We know that we branch to the LHS if the Value being switched on is
2434 // less than the Pivot value, C. We use this to optimize our binary
2435 // tree a bit, by recognizing that if SV is greater than or equal to the
2436 // LHS's Case Value, and that Case Value is exactly one less than the
2437 // Pivot's Value, then we can branch directly to the LHS's Target,
2438 // rather than creating a leaf node for it.
2439 if ((LHSR.second - LHSR.first) == 1 &&
2440 LHSR.first->High == CR.GE &&
2441 cast<ConstantInt>(C)->getValue() ==
2442 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) {
2443 TrueBB = LHSR.first->BB;
2445 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2446 CurMF->insert(BBI, TrueBB);
2447 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR));
2449 // Put SV in a virtual register to make it available from the new blocks.
2450 ExportFromCurrentBlock(SV);
2453 // Similar to the optimization above, if the Value being switched on is
2454 // known to be less than the Constant CR.LT, and the current Case Value
2455 // is CR.LT - 1, then we can branch directly to the target block for
2456 // the current Case Value, rather than emitting a RHS leaf node for it.
2457 if ((RHSR.second - RHSR.first) == 1 && CR.LT &&
2458 cast<ConstantInt>(RHSR.first->Low)->getValue() ==
2459 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) {
2460 FalseBB = RHSR.first->BB;
2462 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2463 CurMF->insert(BBI, FalseBB);
2464 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR));
2466 // Put SV in a virtual register to make it available from the new blocks.
2467 ExportFromCurrentBlock(SV);
2470 // Create a CaseBlock record representing a conditional branch to
2471 // the LHS node if the value being switched on SV is less than C.
2472 // Otherwise, branch to LHS.
2473 CaseBlock CB(ISD::SETLT, SV, C, nullptr, TrueBB, FalseBB, CR.CaseBB);
2475 if (CR.CaseBB == SwitchBB)
2476 visitSwitchCase(CB, SwitchBB);
2478 SwitchCases.push_back(CB);
2483 /// handleBitTestsSwitchCase - if current case range has few destination and
2484 /// range span less, than machine word bitwidth, encode case range into series
2485 /// of masks and emit bit tests with these masks.
2486 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
2487 CaseRecVector& WorkList,
2489 MachineBasicBlock* Default,
2490 MachineBasicBlock* SwitchBB) {
2491 const TargetLowering *TLI = TM.getTargetLowering();
2492 EVT PTy = TLI->getPointerTy();
2493 unsigned IntPtrBits = PTy.getSizeInBits();
2495 Case& FrontCase = *CR.Range.first;
2496 Case& BackCase = *(CR.Range.second-1);
2498 // Get the MachineFunction which holds the current MBB. This is used when
2499 // inserting any additional MBBs necessary to represent the switch.
2500 MachineFunction *CurMF = FuncInfo.MF;
2502 // If target does not have legal shift left, do not emit bit tests at all.
2503 if (!TLI->isOperationLegal(ISD::SHL, PTy))
2507 for (CaseItr I = CR.Range.first, E = CR.Range.second;
2509 // Single case counts one, case range - two.
2510 numCmps += (I->Low == I->High ? 1 : 2);
2513 // Count unique destinations
2514 SmallSet<MachineBasicBlock*, 4> Dests;
2515 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2516 Dests.insert(I->BB);
2517 if (Dests.size() > 3)
2518 // Don't bother the code below, if there are too much unique destinations
2521 DEBUG(dbgs() << "Total number of unique destinations: "
2522 << Dests.size() << '\n'
2523 << "Total number of comparisons: " << numCmps << '\n');
2525 // Compute span of values.
2526 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue();
2527 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue();
2528 APInt cmpRange = maxValue - minValue;
2530 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n'
2531 << "Low bound: " << minValue << '\n'
2532 << "High bound: " << maxValue << '\n');
2534 if (cmpRange.uge(IntPtrBits) ||
2535 (!(Dests.size() == 1 && numCmps >= 3) &&
2536 !(Dests.size() == 2 && numCmps >= 5) &&
2537 !(Dests.size() >= 3 && numCmps >= 6)))
2540 DEBUG(dbgs() << "Emitting bit tests\n");
2541 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth());
2543 // Optimize the case where all the case values fit in a
2544 // word without having to subtract minValue. In this case,
2545 // we can optimize away the subtraction.
2546 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) {
2547 cmpRange = maxValue;
2549 lowBound = minValue;
2552 CaseBitsVector CasesBits;
2553 unsigned i, count = 0;
2555 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) {
2556 MachineBasicBlock* Dest = I->BB;
2557 for (i = 0; i < count; ++i)
2558 if (Dest == CasesBits[i].BB)
2562 assert((count < 3) && "Too much destinations to test!");
2563 CasesBits.push_back(CaseBits(0, Dest, 0, 0/*Weight*/));
2567 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue();
2568 const APInt& highValue = cast<ConstantInt>(I->High)->getValue();
2570 uint64_t lo = (lowValue - lowBound).getZExtValue();
2571 uint64_t hi = (highValue - lowBound).getZExtValue();
2572 CasesBits[i].ExtraWeight += I->ExtraWeight;
2574 for (uint64_t j = lo; j <= hi; j++) {
2575 CasesBits[i].Mask |= 1ULL << j;
2576 CasesBits[i].Bits++;
2580 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp());
2584 // Figure out which block is immediately after the current one.
2585 MachineFunction::iterator BBI = CR.CaseBB;
2588 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock();
2590 DEBUG(dbgs() << "Cases:\n");
2591 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) {
2592 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask
2593 << ", Bits: " << CasesBits[i].Bits
2594 << ", BB: " << CasesBits[i].BB << '\n');
2596 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB);
2597 CurMF->insert(BBI, CaseBB);
2598 BTC.push_back(BitTestCase(CasesBits[i].Mask,
2600 CasesBits[i].BB, CasesBits[i].ExtraWeight));
2602 // Put SV in a virtual register to make it available from the new blocks.
2603 ExportFromCurrentBlock(SV);
2606 BitTestBlock BTB(lowBound, cmpRange, SV,
2607 -1U, MVT::Other, (CR.CaseBB == SwitchBB),
2608 CR.CaseBB, Default, BTC);
2610 if (CR.CaseBB == SwitchBB)
2611 visitBitTestHeader(BTB, SwitchBB);
2613 BitTestCases.push_back(BTB);
2618 /// Clusterify - Transform simple list of Cases into list of CaseRange's
2619 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases,
2620 const SwitchInst& SI) {
2623 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2624 // Start with "simple" cases
2625 for (SwitchInst::ConstCaseIt i = SI.case_begin(), e = SI.case_end();
2627 const BasicBlock *SuccBB = i.getCaseSuccessor();
2628 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB];
2630 uint32_t ExtraWeight =
2631 BPI ? BPI->getEdgeWeight(SI.getParent(), i.getSuccessorIndex()) : 0;
2633 Cases.push_back(Case(i.getCaseValue(), i.getCaseValue(),
2634 SMBB, ExtraWeight));
2636 std::sort(Cases.begin(), Cases.end(), CaseCmp());
2638 // Merge case into clusters
2639 if (Cases.size() >= 2)
2640 // Must recompute end() each iteration because it may be
2641 // invalidated by erase if we hold on to it
2642 for (CaseItr I = Cases.begin(), J = std::next(Cases.begin());
2643 J != Cases.end(); ) {
2644 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue();
2645 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue();
2646 MachineBasicBlock* nextBB = J->BB;
2647 MachineBasicBlock* currentBB = I->BB;
2649 // If the two neighboring cases go to the same destination, merge them
2650 // into a single case.
2651 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) {
2653 I->ExtraWeight += J->ExtraWeight;
2660 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) {
2661 if (I->Low != I->High)
2662 // A range counts double, since it requires two compares.
2669 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2670 MachineBasicBlock *Last) {
2672 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2673 if (JTCases[i].first.HeaderBB == First)
2674 JTCases[i].first.HeaderBB = Last;
2676 // Update BitTestCases.
2677 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2678 if (BitTestCases[i].Parent == First)
2679 BitTestCases[i].Parent = Last;
2682 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2683 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2685 // Figure out which block is immediately after the current one.
2686 MachineBasicBlock *NextBlock = nullptr;
2687 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()];
2689 // If there is only the default destination, branch to it if it is not the
2690 // next basic block. Otherwise, just fall through.
2691 if (!SI.getNumCases()) {
2692 // Update machine-CFG edges.
2694 // If this is not a fall-through branch, emit the branch.
2695 SwitchMBB->addSuccessor(Default);
2696 if (Default != NextBlock)
2697 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2698 MVT::Other, getControlRoot(),
2699 DAG.getBasicBlock(Default)));
2704 // If there are any non-default case statements, create a vector of Cases
2705 // representing each one, and sort the vector so that we can efficiently
2706 // create a binary search tree from them.
2708 size_t numCmps = Clusterify(Cases, SI);
2709 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size()
2710 << ". Total compares: " << numCmps << '\n');
2713 // Get the Value to be switched on and default basic blocks, which will be
2714 // inserted into CaseBlock records, representing basic blocks in the binary
2716 const Value *SV = SI.getCondition();
2718 // Push the initial CaseRec onto the worklist
2719 CaseRecVector WorkList;
2720 WorkList.push_back(CaseRec(SwitchMBB,nullptr,nullptr,
2721 CaseRange(Cases.begin(),Cases.end())));
2723 while (!WorkList.empty()) {
2724 // Grab a record representing a case range to process off the worklist
2725 CaseRec CR = WorkList.back();
2726 WorkList.pop_back();
2728 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2731 // If the range has few cases (two or less) emit a series of specific
2733 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB))
2736 // If the switch has more than N blocks, and is at least 40% dense, and the
2737 // target supports indirect branches, then emit a jump table rather than
2738 // lowering the switch to a binary tree of conditional branches.
2739 // N defaults to 4 and is controlled via TLS.getMinimumJumpTableEntries().
2740 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB))
2743 // Emit binary tree. We need to pick a pivot, and push left and right ranges
2744 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call.
2745 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB);
2749 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2750 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2752 // Update machine-CFG edges with unique successors.
2753 SmallSet<BasicBlock*, 32> Done;
2754 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2755 BasicBlock *BB = I.getSuccessor(i);
2756 bool Inserted = Done.insert(BB);
2760 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2761 addSuccessorWithWeight(IndirectBrMBB, Succ);
2764 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2765 MVT::Other, getControlRoot(),
2766 getValue(I.getAddress())));
2769 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2770 if (DAG.getTarget().Options.TrapUnreachable)
2771 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2774 void SelectionDAGBuilder::visitFSub(const User &I) {
2775 // -0.0 - X --> fneg
2776 Type *Ty = I.getType();
2777 if (isa<Constant>(I.getOperand(0)) &&
2778 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2779 SDValue Op2 = getValue(I.getOperand(1));
2780 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2781 Op2.getValueType(), Op2));
2785 visitBinary(I, ISD::FSUB);
2788 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2789 SDValue Op1 = getValue(I.getOperand(0));
2790 SDValue Op2 = getValue(I.getOperand(1));
2791 setValue(&I, DAG.getNode(OpCode, getCurSDLoc(),
2792 Op1.getValueType(), Op1, Op2));
2795 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2796 SDValue Op1 = getValue(I.getOperand(0));
2797 SDValue Op2 = getValue(I.getOperand(1));
2799 EVT ShiftTy = TM.getTargetLowering()->getShiftAmountTy(Op2.getValueType());
2801 // Coerce the shift amount to the right type if we can.
2802 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2803 unsigned ShiftSize = ShiftTy.getSizeInBits();
2804 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2805 SDLoc DL = getCurSDLoc();
2807 // If the operand is smaller than the shift count type, promote it.
2808 if (ShiftSize > Op2Size)
2809 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2811 // If the operand is larger than the shift count type but the shift
2812 // count type has enough bits to represent any shift value, truncate
2813 // it now. This is a common case and it exposes the truncate to
2814 // optimization early.
2815 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2816 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2817 // Otherwise we'll need to temporarily settle for some other convenient
2818 // type. Type legalization will make adjustments once the shiftee is split.
2820 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2823 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(),
2824 Op1.getValueType(), Op1, Op2));
2827 void SelectionDAGBuilder::visitSDiv(const User &I) {
2828 SDValue Op1 = getValue(I.getOperand(0));
2829 SDValue Op2 = getValue(I.getOperand(1));
2831 // Turn exact SDivs into multiplications.
2832 // FIXME: This should be in DAGCombiner, but it doesn't have access to the
2834 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() &&
2835 !isa<ConstantSDNode>(Op1) &&
2836 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue())
2837 setValue(&I, TM.getTargetLowering()->BuildExactSDIV(Op1, Op2,
2838 getCurSDLoc(), DAG));
2840 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(),
2844 void SelectionDAGBuilder::visitICmp(const User &I) {
2845 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2846 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2847 predicate = IC->getPredicate();
2848 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2849 predicate = ICmpInst::Predicate(IC->getPredicate());
2850 SDValue Op1 = getValue(I.getOperand(0));
2851 SDValue Op2 = getValue(I.getOperand(1));
2852 ISD::CondCode Opcode = getICmpCondCode(predicate);
2854 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2855 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2858 void SelectionDAGBuilder::visitFCmp(const User &I) {
2859 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2860 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2861 predicate = FC->getPredicate();
2862 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2863 predicate = FCmpInst::Predicate(FC->getPredicate());
2864 SDValue Op1 = getValue(I.getOperand(0));
2865 SDValue Op2 = getValue(I.getOperand(1));
2866 ISD::CondCode Condition = getFCmpCondCode(predicate);
2867 if (TM.Options.NoNaNsFPMath)
2868 Condition = getFCmpCodeWithoutNaN(Condition);
2869 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2870 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2873 void SelectionDAGBuilder::visitSelect(const User &I) {
2874 SmallVector<EVT, 4> ValueVTs;
2875 ComputeValueVTs(*TM.getTargetLowering(), I.getType(), ValueVTs);
2876 unsigned NumValues = ValueVTs.size();
2877 if (NumValues == 0) return;
2879 SmallVector<SDValue, 4> Values(NumValues);
2880 SDValue Cond = getValue(I.getOperand(0));
2881 SDValue TrueVal = getValue(I.getOperand(1));
2882 SDValue FalseVal = getValue(I.getOperand(2));
2883 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2884 ISD::VSELECT : ISD::SELECT;
2886 for (unsigned i = 0; i != NumValues; ++i)
2887 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2888 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i),
2890 SDValue(TrueVal.getNode(),
2891 TrueVal.getResNo() + i),
2892 SDValue(FalseVal.getNode(),
2893 FalseVal.getResNo() + i));
2895 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2896 DAG.getVTList(ValueVTs),
2897 &Values[0], NumValues));
2900 void SelectionDAGBuilder::visitTrunc(const User &I) {
2901 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2902 SDValue N = getValue(I.getOperand(0));
2903 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2904 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2907 void SelectionDAGBuilder::visitZExt(const User &I) {
2908 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2909 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2910 SDValue N = getValue(I.getOperand(0));
2911 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2912 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2915 void SelectionDAGBuilder::visitSExt(const User &I) {
2916 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2917 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2918 SDValue N = getValue(I.getOperand(0));
2919 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2920 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2923 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2924 // FPTrunc is never a no-op cast, no need to check
2925 SDValue N = getValue(I.getOperand(0));
2926 const TargetLowering *TLI = TM.getTargetLowering();
2927 EVT DestVT = TLI->getValueType(I.getType());
2928 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurSDLoc(),
2930 DAG.getTargetConstant(0, TLI->getPointerTy())));
2933 void SelectionDAGBuilder::visitFPExt(const User &I) {
2934 // FPExt is never a no-op cast, no need to check
2935 SDValue N = getValue(I.getOperand(0));
2936 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2937 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2940 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2941 // FPToUI is never a no-op cast, no need to check
2942 SDValue N = getValue(I.getOperand(0));
2943 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2944 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2947 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2948 // FPToSI is never a no-op cast, no need to check
2949 SDValue N = getValue(I.getOperand(0));
2950 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2951 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2954 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2955 // UIToFP is never a no-op cast, no need to check
2956 SDValue N = getValue(I.getOperand(0));
2957 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2958 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2961 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2962 // SIToFP is never a no-op cast, no need to check
2963 SDValue N = getValue(I.getOperand(0));
2964 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2965 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2968 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2969 // What to do depends on the size of the integer and the size of the pointer.
2970 // We can either truncate, zero extend, or no-op, accordingly.
2971 SDValue N = getValue(I.getOperand(0));
2972 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2973 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2976 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2977 // What to do depends on the size of the integer and the size of the pointer.
2978 // We can either truncate, zero extend, or no-op, accordingly.
2979 SDValue N = getValue(I.getOperand(0));
2980 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2981 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2984 void SelectionDAGBuilder::visitBitCast(const User &I) {
2985 SDValue N = getValue(I.getOperand(0));
2986 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
2988 // BitCast assures us that source and destination are the same size so this is
2989 // either a BITCAST or a no-op.
2990 if (DestVT != N.getValueType())
2991 setValue(&I, DAG.getNode(ISD::BITCAST, getCurSDLoc(),
2992 DestVT, N)); // convert types.
2993 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2994 // might fold any kind of constant expression to an integer constant and that
2995 // is not what we are looking for. Only regcognize a bitcast of a genuine
2996 // constant integer as an opaque constant.
2997 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2998 setValue(&I, DAG.getConstant(C->getValue(), DestVT, /*isTarget=*/false,
3001 setValue(&I, N); // noop cast.
3004 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
3005 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3006 const Value *SV = I.getOperand(0);
3007 SDValue N = getValue(SV);
3008 EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
3010 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
3011 unsigned DestAS = I.getType()->getPointerAddressSpace();
3013 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
3014 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
3019 void SelectionDAGBuilder::visitInsertElement(const User &I) {
3020 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3021 SDValue InVec = getValue(I.getOperand(0));
3022 SDValue InVal = getValue(I.getOperand(1));
3023 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)),
3024 getCurSDLoc(), TLI.getVectorIdxTy());
3025 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
3026 TM.getTargetLowering()->getValueType(I.getType()),
3027 InVec, InVal, InIdx));
3030 void SelectionDAGBuilder::visitExtractElement(const User &I) {
3031 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3032 SDValue InVec = getValue(I.getOperand(0));
3033 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)),
3034 getCurSDLoc(), TLI.getVectorIdxTy());
3035 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3036 TM.getTargetLowering()->getValueType(I.getType()),
3040 // Utility for visitShuffleVector - Return true if every element in Mask,
3041 // beginning from position Pos and ending in Pos+Size, falls within the
3042 // specified sequential range [L, L+Pos). or is undef.
3043 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
3044 unsigned Pos, unsigned Size, int Low) {
3045 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3046 if (Mask[i] >= 0 && Mask[i] != Low)
3051 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
3052 SDValue Src1 = getValue(I.getOperand(0));
3053 SDValue Src2 = getValue(I.getOperand(1));
3055 SmallVector<int, 8> Mask;
3056 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
3057 unsigned MaskNumElts = Mask.size();
3059 const TargetLowering *TLI = TM.getTargetLowering();
3060 EVT VT = TLI->getValueType(I.getType());
3061 EVT SrcVT = Src1.getValueType();
3062 unsigned SrcNumElts = SrcVT.getVectorNumElements();
3064 if (SrcNumElts == MaskNumElts) {
3065 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3070 // Normalize the shuffle vector since mask and vector length don't match.
3071 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
3072 // Mask is longer than the source vectors and is a multiple of the source
3073 // vectors. We can use concatenate vector to make the mask and vectors
3075 if (SrcNumElts*2 == MaskNumElts) {
3076 // First check for Src1 in low and Src2 in high
3077 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
3078 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
3079 // The shuffle is concatenating two vectors together.
3080 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3084 // Then check for Src2 in low and Src1 in high
3085 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
3086 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
3087 // The shuffle is concatenating two vectors together.
3088 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
3094 // Pad both vectors with undefs to make them the same length as the mask.
3095 unsigned NumConcat = MaskNumElts / SrcNumElts;
3096 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
3097 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
3098 SDValue UndefVal = DAG.getUNDEF(SrcVT);
3100 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
3101 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
3105 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3107 &MOps1[0], NumConcat);
3108 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
3110 &MOps2[0], NumConcat);
3112 // Readjust mask for new input vector length.
3113 SmallVector<int, 8> MappedOps;
3114 for (unsigned i = 0; i != MaskNumElts; ++i) {
3116 if (Idx >= (int)SrcNumElts)
3117 Idx -= SrcNumElts - MaskNumElts;
3118 MappedOps.push_back(Idx);
3121 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3126 if (SrcNumElts > MaskNumElts) {
3127 // Analyze the access pattern of the vector to see if we can extract
3128 // two subvectors and do the shuffle. The analysis is done by calculating
3129 // the range of elements the mask access on both vectors.
3130 int MinRange[2] = { static_cast<int>(SrcNumElts),
3131 static_cast<int>(SrcNumElts)};
3132 int MaxRange[2] = {-1, -1};
3134 for (unsigned i = 0; i != MaskNumElts; ++i) {
3140 if (Idx >= (int)SrcNumElts) {
3144 if (Idx > MaxRange[Input])
3145 MaxRange[Input] = Idx;
3146 if (Idx < MinRange[Input])
3147 MinRange[Input] = Idx;
3150 // Check if the access is smaller than the vector size and can we find
3151 // a reasonable extract index.
3152 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
3154 int StartIdx[2]; // StartIdx to extract from
3155 for (unsigned Input = 0; Input < 2; ++Input) {
3156 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
3157 RangeUse[Input] = 0; // Unused
3158 StartIdx[Input] = 0;
3162 // Find a good start index that is a multiple of the mask length. Then
3163 // see if the rest of the elements are in range.
3164 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
3165 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
3166 StartIdx[Input] + MaskNumElts <= SrcNumElts)
3167 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
3170 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
3171 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
3174 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
3175 // Extract appropriate subvector and generate a vector shuffle
3176 for (unsigned Input = 0; Input < 2; ++Input) {
3177 SDValue &Src = Input == 0 ? Src1 : Src2;
3178 if (RangeUse[Input] == 0)
3179 Src = DAG.getUNDEF(VT);
3181 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurSDLoc(), VT,
3182 Src, DAG.getConstant(StartIdx[Input],
3183 TLI->getVectorIdxTy()));
3186 // Calculate new mask.
3187 SmallVector<int, 8> MappedOps;
3188 for (unsigned i = 0; i != MaskNumElts; ++i) {
3191 if (Idx < (int)SrcNumElts)
3194 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
3196 MappedOps.push_back(Idx);
3199 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
3205 // We can't use either concat vectors or extract subvectors so fall back to
3206 // replacing the shuffle with extract and build vector.
3207 // to insert and build vector.
3208 EVT EltVT = VT.getVectorElementType();
3209 EVT IdxVT = TLI->getVectorIdxTy();
3210 SmallVector<SDValue,8> Ops;
3211 for (unsigned i = 0; i != MaskNumElts; ++i) {
3216 Res = DAG.getUNDEF(EltVT);
3218 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
3219 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
3221 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
3222 EltVT, Src, DAG.getConstant(Idx, IdxVT));
3228 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
3229 VT, &Ops[0], Ops.size()));
3232 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
3233 const Value *Op0 = I.getOperand(0);
3234 const Value *Op1 = I.getOperand(1);
3235 Type *AggTy = I.getType();
3236 Type *ValTy = Op1->getType();
3237 bool IntoUndef = isa<UndefValue>(Op0);
3238 bool FromUndef = isa<UndefValue>(Op1);
3240 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3242 const TargetLowering *TLI = TM.getTargetLowering();
3243 SmallVector<EVT, 4> AggValueVTs;
3244 ComputeValueVTs(*TLI, AggTy, AggValueVTs);
3245 SmallVector<EVT, 4> ValValueVTs;
3246 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3248 unsigned NumAggValues = AggValueVTs.size();
3249 unsigned NumValValues = ValValueVTs.size();
3250 SmallVector<SDValue, 4> Values(NumAggValues);
3252 SDValue Agg = getValue(Op0);
3254 // Copy the beginning value(s) from the original aggregate.
3255 for (; i != LinearIndex; ++i)
3256 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3257 SDValue(Agg.getNode(), Agg.getResNo() + i);
3258 // Copy values from the inserted value(s).
3260 SDValue Val = getValue(Op1);
3261 for (; i != LinearIndex + NumValValues; ++i)
3262 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3263 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
3265 // Copy remaining value(s) from the original aggregate.
3266 for (; i != NumAggValues; ++i)
3267 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
3268 SDValue(Agg.getNode(), Agg.getResNo() + i);
3270 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3271 DAG.getVTList(AggValueVTs),
3272 &Values[0], NumAggValues));
3275 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
3276 const Value *Op0 = I.getOperand(0);
3277 Type *AggTy = Op0->getType();
3278 Type *ValTy = I.getType();
3279 bool OutOfUndef = isa<UndefValue>(Op0);
3281 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
3283 const TargetLowering *TLI = TM.getTargetLowering();
3284 SmallVector<EVT, 4> ValValueVTs;
3285 ComputeValueVTs(*TLI, ValTy, ValValueVTs);
3287 unsigned NumValValues = ValValueVTs.size();
3289 // Ignore a extractvalue that produces an empty object
3290 if (!NumValValues) {
3291 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
3295 SmallVector<SDValue, 4> Values(NumValValues);
3297 SDValue Agg = getValue(Op0);
3298 // Copy out the selected value(s).
3299 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
3300 Values[i - LinearIndex] =
3302 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
3303 SDValue(Agg.getNode(), Agg.getResNo() + i);
3305 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3306 DAG.getVTList(ValValueVTs),
3307 &Values[0], NumValValues));
3310 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
3311 Value *Op0 = I.getOperand(0);
3312 // Note that the pointer operand may be a vector of pointers. Take the scalar
3313 // element which holds a pointer.
3314 Type *Ty = Op0->getType()->getScalarType();
3315 unsigned AS = Ty->getPointerAddressSpace();
3316 SDValue N = getValue(Op0);
3318 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
3320 const Value *Idx = *OI;
3321 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
3322 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
3325 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
3326 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3327 DAG.getConstant(Offset, N.getValueType()));
3330 Ty = StTy->getElementType(Field);
3332 Ty = cast<SequentialType>(Ty)->getElementType();
3334 // If this is a constant subscript, handle it quickly.
3335 const TargetLowering *TLI = TM.getTargetLowering();
3336 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
3337 if (CI->isZero()) continue;
3339 DL->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
3341 EVT PTy = TLI->getPointerTy(AS);
3342 unsigned PtrBits = PTy.getSizeInBits();
3344 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), PTy,
3345 DAG.getConstant(Offs, MVT::i64));
3347 OffsVal = DAG.getConstant(Offs, PTy);
3349 N = DAG.getNode(ISD::ADD, getCurSDLoc(), N.getValueType(), N,
3354 // N = N + Idx * ElementSize;
3355 APInt ElementSize = APInt(TLI->getPointerSizeInBits(AS),
3356 DL->getTypeAllocSize(Ty));
3357 SDValue IdxN = getValue(Idx);
3359 // If the index is smaller or larger than intptr_t, truncate or extend
3361 IdxN = DAG.getSExtOrTrunc(IdxN, getCurSDLoc(), N.getValueType());
3363 // If this is a multiply by a power of two, turn it into a shl
3364 // immediately. This is a very common case.
3365 if (ElementSize != 1) {
3366 if (ElementSize.isPowerOf2()) {
3367 unsigned Amt = ElementSize.logBase2();
3368 IdxN = DAG.getNode(ISD::SHL, getCurSDLoc(),
3369 N.getValueType(), IdxN,
3370 DAG.getConstant(Amt, IdxN.getValueType()));
3372 SDValue Scale = DAG.getConstant(ElementSize, IdxN.getValueType());
3373 IdxN = DAG.getNode(ISD::MUL, getCurSDLoc(),
3374 N.getValueType(), IdxN, Scale);
3378 N = DAG.getNode(ISD::ADD, getCurSDLoc(),
3379 N.getValueType(), N, IdxN);
3386 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3387 // If this is a fixed sized alloca in the entry block of the function,
3388 // allocate it statically on the stack.
3389 if (FuncInfo.StaticAllocaMap.count(&I))
3390 return; // getValue will auto-populate this.
3392 Type *Ty = I.getAllocatedType();
3393 const TargetLowering *TLI = TM.getTargetLowering();
3394 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
3396 std::max((unsigned)TLI->getDataLayout()->getPrefTypeAlignment(Ty),
3399 SDValue AllocSize = getValue(I.getArraySize());
3401 EVT IntPtr = TLI->getPointerTy();
3402 if (AllocSize.getValueType() != IntPtr)
3403 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurSDLoc(), IntPtr);
3405 AllocSize = DAG.getNode(ISD::MUL, getCurSDLoc(), IntPtr,
3407 DAG.getConstant(TySize, IntPtr));
3409 // Handle alignment. If the requested alignment is less than or equal to
3410 // the stack alignment, ignore it. If the size is greater than or equal to
3411 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3412 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
3413 if (Align <= StackAlign)
3416 // Round the size of the allocation up to the stack alignment size
3417 // by add SA-1 to the size.
3418 AllocSize = DAG.getNode(ISD::ADD, getCurSDLoc(),
3419 AllocSize.getValueType(), AllocSize,
3420 DAG.getIntPtrConstant(StackAlign-1));
3422 // Mask out the low bits for alignment purposes.
3423 AllocSize = DAG.getNode(ISD::AND, getCurSDLoc(),
3424 AllocSize.getValueType(), AllocSize,
3425 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
3427 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
3428 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3429 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurSDLoc(),
3432 DAG.setRoot(DSA.getValue(1));
3434 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3437 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3439 return visitAtomicLoad(I);
3441 const Value *SV = I.getOperand(0);
3442 SDValue Ptr = getValue(SV);
3444 Type *Ty = I.getType();
3446 bool isVolatile = I.isVolatile();
3447 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3448 bool isInvariant = I.getMetadata("invariant.load") != nullptr;
3449 unsigned Alignment = I.getAlignment();
3450 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3451 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3453 SmallVector<EVT, 4> ValueVTs;
3454 SmallVector<uint64_t, 4> Offsets;
3455 ComputeValueVTs(*TM.getTargetLowering(), Ty, ValueVTs, &Offsets);
3456 unsigned NumValues = ValueVTs.size();
3461 bool ConstantMemory = false;
3462 if (isVolatile || NumValues > MaxParallelChains)
3463 // Serialize volatile loads with other side effects.
3465 else if (AA->pointsToConstantMemory(
3466 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) {
3467 // Do not serialize (non-volatile) loads of constant memory with anything.
3468 Root = DAG.getEntryNode();
3469 ConstantMemory = true;
3471 // Do not serialize non-volatile loads against each other.
3472 Root = DAG.getRoot();
3475 const TargetLowering *TLI = TM.getTargetLowering();
3477 Root = TLI->prepareVolatileOrAtomicLoad(Root, getCurSDLoc(), DAG);
3479 SmallVector<SDValue, 4> Values(NumValues);
3480 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3482 EVT PtrVT = Ptr.getValueType();
3483 unsigned ChainI = 0;
3484 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3485 // Serializing loads here may result in excessive register pressure, and
3486 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3487 // could recover a bit by hoisting nodes upward in the chain by recognizing
3488 // they are side-effect free or do not alias. The optimizer should really
3489 // avoid this case by converting large object/array copies to llvm.memcpy
3490 // (MaxParallelChains should always remain as failsafe).
3491 if (ChainI == MaxParallelChains) {
3492 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3493 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3494 MVT::Other, &Chains[0], ChainI);
3498 SDValue A = DAG.getNode(ISD::ADD, getCurSDLoc(),
3500 DAG.getConstant(Offsets[i], PtrVT));
3501 SDValue L = DAG.getLoad(ValueVTs[i], getCurSDLoc(), Root,
3502 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3503 isNonTemporal, isInvariant, Alignment, TBAAInfo,
3507 Chains[ChainI] = L.getValue(1);
3510 if (!ConstantMemory) {
3511 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3512 MVT::Other, &Chains[0], ChainI);
3516 PendingLoads.push_back(Chain);
3519 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
3520 DAG.getVTList(ValueVTs),
3521 &Values[0], NumValues));
3524 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3526 return visitAtomicStore(I);
3528 const Value *SrcV = I.getOperand(0);
3529 const Value *PtrV = I.getOperand(1);
3531 SmallVector<EVT, 4> ValueVTs;
3532 SmallVector<uint64_t, 4> Offsets;
3533 ComputeValueVTs(*TM.getTargetLowering(), SrcV->getType(), ValueVTs, &Offsets);
3534 unsigned NumValues = ValueVTs.size();
3538 // Get the lowered operands. Note that we do this after
3539 // checking if NumResults is zero, because with zero results
3540 // the operands won't have values in the map.
3541 SDValue Src = getValue(SrcV);
3542 SDValue Ptr = getValue(PtrV);
3544 SDValue Root = getRoot();
3545 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains),
3547 EVT PtrVT = Ptr.getValueType();
3548 bool isVolatile = I.isVolatile();
3549 bool isNonTemporal = I.getMetadata("nontemporal") != nullptr;
3550 unsigned Alignment = I.getAlignment();
3551 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa);
3553 unsigned ChainI = 0;
3554 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3555 // See visitLoad comments.
3556 if (ChainI == MaxParallelChains) {
3557 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3558 MVT::Other, &Chains[0], ChainI);
3562 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT, Ptr,
3563 DAG.getConstant(Offsets[i], PtrVT));
3564 SDValue St = DAG.getStore(Root, getCurSDLoc(),
3565 SDValue(Src.getNode(), Src.getResNo() + i),
3566 Add, MachinePointerInfo(PtrV, Offsets[i]),
3567 isVolatile, isNonTemporal, Alignment, TBAAInfo);
3568 Chains[ChainI] = St;
3571 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
3572 MVT::Other, &Chains[0], ChainI);
3573 DAG.setRoot(StoreNode);
3576 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order,
3577 SynchronizationScope Scope,
3578 bool Before, SDLoc dl,
3580 const TargetLowering &TLI) {
3581 // Fence, if necessary
3583 if (Order == AcquireRelease || Order == SequentiallyConsistent)
3585 else if (Order == Acquire || Order == Monotonic)
3588 if (Order == AcquireRelease)
3590 else if (Order == Release || Order == Monotonic)
3595 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy());
3596 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy());
3597 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3);
3600 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3601 SDLoc dl = getCurSDLoc();
3602 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3603 AtomicOrdering FailureOrder = I.getFailureOrdering();
3604 SynchronizationScope Scope = I.getSynchScope();
3606 SDValue InChain = getRoot();
3608 const TargetLowering *TLI = TM.getTargetLowering();
3609 if (TLI->getInsertFencesForAtomic())
3610 InChain = InsertFenceForAtomic(InChain, SuccessOrder, Scope, true, dl,
3614 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl,
3615 getValue(I.getCompareOperand()).getSimpleValueType(),
3617 getValue(I.getPointerOperand()),
3618 getValue(I.getCompareOperand()),
3619 getValue(I.getNewValOperand()),
3620 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */,
3621 TLI->getInsertFencesForAtomic() ? Monotonic : SuccessOrder,
3622 TLI->getInsertFencesForAtomic() ? Monotonic : FailureOrder,
3625 SDValue OutChain = L.getValue(1);
3627 if (TLI->getInsertFencesForAtomic())
3628 OutChain = InsertFenceForAtomic(OutChain, SuccessOrder, Scope, false, dl,
3632 DAG.setRoot(OutChain);
3635 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3636 SDLoc dl = getCurSDLoc();
3638 switch (I.getOperation()) {
3639 default: llvm_unreachable("Unknown atomicrmw operation");
3640 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3641 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3642 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3643 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3644 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3645 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3646 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3647 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3648 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3649 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3650 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3652 AtomicOrdering Order = I.getOrdering();
3653 SynchronizationScope Scope = I.getSynchScope();
3655 SDValue InChain = getRoot();
3657 const TargetLowering *TLI = TM.getTargetLowering();
3658 if (TLI->getInsertFencesForAtomic())
3659 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3663 DAG.getAtomic(NT, dl,
3664 getValue(I.getValOperand()).getSimpleValueType(),
3666 getValue(I.getPointerOperand()),
3667 getValue(I.getValOperand()),
3668 I.getPointerOperand(), 0 /* Alignment */,
3669 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3672 SDValue OutChain = L.getValue(1);
3674 if (TLI->getInsertFencesForAtomic())
3675 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3679 DAG.setRoot(OutChain);
3682 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3683 SDLoc dl = getCurSDLoc();
3684 const TargetLowering *TLI = TM.getTargetLowering();
3687 Ops[1] = DAG.getConstant(I.getOrdering(), TLI->getPointerTy());
3688 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI->getPointerTy());
3689 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3));
3692 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3693 SDLoc dl = getCurSDLoc();
3694 AtomicOrdering Order = I.getOrdering();
3695 SynchronizationScope Scope = I.getSynchScope();
3697 SDValue InChain = getRoot();
3699 const TargetLowering *TLI = TM.getTargetLowering();
3700 EVT VT = TLI->getValueType(I.getType());
3702 if (I.getAlignment() < VT.getSizeInBits() / 8)
3703 report_fatal_error("Cannot generate unaligned atomic load");
3705 MachineMemOperand *MMO =
3706 DAG.getMachineFunction().
3707 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3708 MachineMemOperand::MOVolatile |
3709 MachineMemOperand::MOLoad,
3711 I.getAlignment() ? I.getAlignment() :
3712 DAG.getEVTAlignment(VT));
3714 InChain = TLI->prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3716 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3717 getValue(I.getPointerOperand()), MMO,
3718 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3721 SDValue OutChain = L.getValue(1);
3723 if (TLI->getInsertFencesForAtomic())
3724 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3728 DAG.setRoot(OutChain);
3731 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3732 SDLoc dl = getCurSDLoc();
3734 AtomicOrdering Order = I.getOrdering();
3735 SynchronizationScope Scope = I.getSynchScope();
3737 SDValue InChain = getRoot();
3739 const TargetLowering *TLI = TM.getTargetLowering();
3740 EVT VT = TLI->getValueType(I.getValueOperand()->getType());
3742 if (I.getAlignment() < VT.getSizeInBits() / 8)
3743 report_fatal_error("Cannot generate unaligned atomic store");
3745 if (TLI->getInsertFencesForAtomic())
3746 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl,
3750 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3752 getValue(I.getPointerOperand()),
3753 getValue(I.getValueOperand()),
3754 I.getPointerOperand(), I.getAlignment(),
3755 TLI->getInsertFencesForAtomic() ? Monotonic : Order,
3758 if (TLI->getInsertFencesForAtomic())
3759 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl,
3762 DAG.setRoot(OutChain);
3765 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3767 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3768 unsigned Intrinsic) {
3769 bool HasChain = !I.doesNotAccessMemory();
3770 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3772 // Build the operand list.
3773 SmallVector<SDValue, 8> Ops;
3774 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3776 // We don't need to serialize loads against other loads.
3777 Ops.push_back(DAG.getRoot());
3779 Ops.push_back(getRoot());
3783 // Info is set by getTgtMemInstrinsic
3784 TargetLowering::IntrinsicInfo Info;
3785 const TargetLowering *TLI = TM.getTargetLowering();
3786 bool IsTgtIntrinsic = TLI->getTgtMemIntrinsic(Info, I, Intrinsic);
3788 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3789 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3790 Info.opc == ISD::INTRINSIC_W_CHAIN)
3791 Ops.push_back(DAG.getTargetConstant(Intrinsic, TLI->getPointerTy()));
3793 // Add all operands of the call to the operand list.
3794 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3795 SDValue Op = getValue(I.getArgOperand(i));
3799 SmallVector<EVT, 4> ValueVTs;
3800 ComputeValueVTs(*TLI, I.getType(), ValueVTs);
3803 ValueVTs.push_back(MVT::Other);
3805 SDVTList VTs = DAG.getVTList(ValueVTs);
3809 if (IsTgtIntrinsic) {
3810 // This is target intrinsic that touches memory
3811 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3812 VTs, &Ops[0], Ops.size(),
3814 MachinePointerInfo(Info.ptrVal, Info.offset),
3815 Info.align, Info.vol,
3816 Info.readMem, Info.writeMem);
3817 } else if (!HasChain) {
3818 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(),
3819 VTs, &Ops[0], Ops.size());
3820 } else if (!I.getType()->isVoidTy()) {
3821 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(),
3822 VTs, &Ops[0], Ops.size());
3824 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(),
3825 VTs, &Ops[0], Ops.size());
3829 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3831 PendingLoads.push_back(Chain);
3836 if (!I.getType()->isVoidTy()) {
3837 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3838 EVT VT = TLI->getValueType(PTy);
3839 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3842 setValue(&I, Result);
3846 /// GetSignificand - Get the significand and build it into a floating-point
3847 /// number with exponent of 1:
3849 /// Op = (Op & 0x007fffff) | 0x3f800000;
3851 /// where Op is the hexadecimal representation of floating point value.
3853 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3854 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3855 DAG.getConstant(0x007fffff, MVT::i32));
3856 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3857 DAG.getConstant(0x3f800000, MVT::i32));
3858 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3861 /// GetExponent - Get the exponent:
3863 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3865 /// where Op is the hexadecimal representation of floating point value.
3867 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3869 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3870 DAG.getConstant(0x7f800000, MVT::i32));
3871 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
3872 DAG.getConstant(23, TLI.getPointerTy()));
3873 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3874 DAG.getConstant(127, MVT::i32));
3875 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3878 /// getF32Constant - Get 32-bit floating point constant.
3880 getF32Constant(SelectionDAG &DAG, unsigned Flt) {
3881 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)),
3885 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3886 /// limited-precision mode.
3887 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3888 const TargetLowering &TLI) {
3889 if (Op.getValueType() == MVT::f32 &&
3890 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3892 // Put the exponent in the right bit position for later addition to the
3895 // #define LOG2OFe 1.4426950f
3896 // IntegerPartOfX = ((int32_t)(X * LOG2OFe));
3897 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3898 getF32Constant(DAG, 0x3fb8aa3b));
3899 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3901 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
3902 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3903 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3905 // IntegerPartOfX <<= 23;
3906 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3907 DAG.getConstant(23, TLI.getPointerTy()));
3909 SDValue TwoToFracPartOfX;
3910 if (LimitFloatPrecision <= 6) {
3911 // For floating-point precision of 6:
3913 // TwoToFractionalPartOfX =
3915 // (0.735607626f + 0.252464424f * x) * x;
3917 // error 0.0144103317, which is 6 bits
3918 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3919 getF32Constant(DAG, 0x3e814304));
3920 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3921 getF32Constant(DAG, 0x3f3c50c8));
3922 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3923 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3924 getF32Constant(DAG, 0x3f7f5e7e));
3925 } else if (LimitFloatPrecision <= 12) {
3926 // For floating-point precision of 12:
3928 // TwoToFractionalPartOfX =
3931 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3933 // 0.000107046256 error, which is 13 to 14 bits
3934 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3935 getF32Constant(DAG, 0x3da235e3));
3936 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3937 getF32Constant(DAG, 0x3e65b8f3));
3938 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3939 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3940 getF32Constant(DAG, 0x3f324b07));
3941 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3942 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3943 getF32Constant(DAG, 0x3f7ff8fd));
3944 } else { // LimitFloatPrecision <= 18
3945 // For floating-point precision of 18:
3947 // TwoToFractionalPartOfX =
3951 // (0.554906021e-1f +
3952 // (0.961591928e-2f +
3953 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3955 // error 2.47208000*10^(-7), which is better than 18 bits
3956 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3957 getF32Constant(DAG, 0x3924b03e));
3958 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3959 getF32Constant(DAG, 0x3ab24b87));
3960 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3961 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3962 getF32Constant(DAG, 0x3c1d8c17));
3963 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3964 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3965 getF32Constant(DAG, 0x3d634a1d));
3966 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3967 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3968 getF32Constant(DAG, 0x3e75fe14));
3969 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3970 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3971 getF32Constant(DAG, 0x3f317234));
3972 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3973 TwoToFracPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3974 getF32Constant(DAG, 0x3f800000));
3977 // Add the exponent into the result in integer domain.
3978 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFracPartOfX);
3979 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3980 DAG.getNode(ISD::ADD, dl, MVT::i32,
3981 t13, IntegerPartOfX));
3984 // No special expansion.
3985 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3988 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3989 /// limited-precision mode.
3990 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3991 const TargetLowering &TLI) {
3992 if (Op.getValueType() == MVT::f32 &&
3993 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3994 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3996 // Scale the exponent by log(2) [0.69314718f].
3997 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3998 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3999 getF32Constant(DAG, 0x3f317218));
4001 // Get the significand and build it into a floating-point number with
4003 SDValue X = GetSignificand(DAG, Op1, dl);
4005 SDValue LogOfMantissa;
4006 if (LimitFloatPrecision <= 6) {
4007 // For floating-point precision of 6:
4011 // (1.4034025f - 0.23903021f * x) * x;
4013 // error 0.0034276066, which is better than 8 bits
4014 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4015 getF32Constant(DAG, 0xbe74c456));
4016 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4017 getF32Constant(DAG, 0x3fb3a2b1));
4018 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4019 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4020 getF32Constant(DAG, 0x3f949a29));
4021 } else if (LimitFloatPrecision <= 12) {
4022 // For floating-point precision of 12:
4028 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
4030 // error 0.000061011436, which is 14 bits
4031 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4032 getF32Constant(DAG, 0xbd67b6d6));
4033 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4034 getF32Constant(DAG, 0x3ee4f4b8));
4035 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4036 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4037 getF32Constant(DAG, 0x3fbc278b));
4038 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4039 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4040 getF32Constant(DAG, 0x40348e95));
4041 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4042 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4043 getF32Constant(DAG, 0x3fdef31a));
4044 } else { // LimitFloatPrecision <= 18
4045 // For floating-point precision of 18:
4053 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
4055 // error 0.0000023660568, which is better than 18 bits
4056 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4057 getF32Constant(DAG, 0xbc91e5ac));
4058 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4059 getF32Constant(DAG, 0x3e4350aa));
4060 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4061 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4062 getF32Constant(DAG, 0x3f60d3e3));
4063 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4064 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4065 getF32Constant(DAG, 0x4011cdf0));
4066 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4067 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4068 getF32Constant(DAG, 0x406cfd1c));
4069 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4070 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4071 getF32Constant(DAG, 0x408797cb));
4072 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4073 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4074 getF32Constant(DAG, 0x4006dcab));
4077 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
4080 // No special expansion.
4081 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
4084 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
4085 /// limited-precision mode.
4086 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4087 const TargetLowering &TLI) {
4088 if (Op.getValueType() == MVT::f32 &&
4089 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4090 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4092 // Get the exponent.
4093 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
4095 // Get the significand and build it into a floating-point number with
4097 SDValue X = GetSignificand(DAG, Op1, dl);
4099 // Different possible minimax approximations of significand in
4100 // floating-point for various degrees of accuracy over [1,2].
4101 SDValue Log2ofMantissa;
4102 if (LimitFloatPrecision <= 6) {
4103 // For floating-point precision of 6:
4105 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
4107 // error 0.0049451742, which is more than 7 bits
4108 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4109 getF32Constant(DAG, 0xbeb08fe0));
4110 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4111 getF32Constant(DAG, 0x40019463));
4112 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4113 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4114 getF32Constant(DAG, 0x3fd6633d));
4115 } else if (LimitFloatPrecision <= 12) {
4116 // For floating-point precision of 12:
4122 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
4124 // error 0.0000876136000, which is better than 13 bits
4125 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4126 getF32Constant(DAG, 0xbda7262e));
4127 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4128 getF32Constant(DAG, 0x3f25280b));
4129 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4130 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4131 getF32Constant(DAG, 0x4007b923));
4132 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4133 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4134 getF32Constant(DAG, 0x40823e2f));
4135 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4136 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4137 getF32Constant(DAG, 0x4020d29c));
4138 } else { // LimitFloatPrecision <= 18
4139 // For floating-point precision of 18:
4148 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4150 // error 0.0000018516, which is better than 18 bits
4151 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4152 getF32Constant(DAG, 0xbcd2769e));
4153 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4154 getF32Constant(DAG, 0x3e8ce0b9));
4155 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4156 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4157 getF32Constant(DAG, 0x3fa22ae7));
4158 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4159 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4160 getF32Constant(DAG, 0x40525723));
4161 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4162 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4163 getF32Constant(DAG, 0x40aaf200));
4164 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4165 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4166 getF32Constant(DAG, 0x40c39dad));
4167 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4168 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4169 getF32Constant(DAG, 0x4042902c));
4172 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4175 // No special expansion.
4176 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4179 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4180 /// limited-precision mode.
4181 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4182 const TargetLowering &TLI) {
4183 if (Op.getValueType() == MVT::f32 &&
4184 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4185 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4187 // Scale the exponent by log10(2) [0.30102999f].
4188 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4189 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4190 getF32Constant(DAG, 0x3e9a209a));
4192 // Get the significand and build it into a floating-point number with
4194 SDValue X = GetSignificand(DAG, Op1, dl);
4196 SDValue Log10ofMantissa;
4197 if (LimitFloatPrecision <= 6) {
4198 // For floating-point precision of 6:
4200 // Log10ofMantissa =
4202 // (0.60948995f - 0.10380950f * x) * x;
4204 // error 0.0014886165, which is 6 bits
4205 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4206 getF32Constant(DAG, 0xbdd49a13));
4207 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4208 getF32Constant(DAG, 0x3f1c0789));
4209 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4210 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4211 getF32Constant(DAG, 0x3f011300));
4212 } else if (LimitFloatPrecision <= 12) {
4213 // For floating-point precision of 12:
4215 // Log10ofMantissa =
4218 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4220 // error 0.00019228036, which is better than 12 bits
4221 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4222 getF32Constant(DAG, 0x3d431f31));
4223 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4224 getF32Constant(DAG, 0x3ea21fb2));
4225 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4226 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4227 getF32Constant(DAG, 0x3f6ae232));
4228 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4229 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4230 getF32Constant(DAG, 0x3f25f7c3));
4231 } else { // LimitFloatPrecision <= 18
4232 // For floating-point precision of 18:
4234 // Log10ofMantissa =
4239 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4241 // error 0.0000037995730, which is better than 18 bits
4242 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4243 getF32Constant(DAG, 0x3c5d51ce));
4244 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4245 getF32Constant(DAG, 0x3e00685a));
4246 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4247 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4248 getF32Constant(DAG, 0x3efb6798));
4249 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4250 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4251 getF32Constant(DAG, 0x3f88d192));
4252 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4253 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4254 getF32Constant(DAG, 0x3fc4316c));
4255 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4256 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4257 getF32Constant(DAG, 0x3f57ce70));
4260 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4263 // No special expansion.
4264 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4267 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4268 /// limited-precision mode.
4269 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4270 const TargetLowering &TLI) {
4271 if (Op.getValueType() == MVT::f32 &&
4272 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4273 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
4275 // FractionalPartOfX = x - (float)IntegerPartOfX;
4276 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4277 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
4279 // IntegerPartOfX <<= 23;
4280 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4281 DAG.getConstant(23, TLI.getPointerTy()));
4283 SDValue TwoToFractionalPartOfX;
4284 if (LimitFloatPrecision <= 6) {
4285 // For floating-point precision of 6:
4287 // TwoToFractionalPartOfX =
4289 // (0.735607626f + 0.252464424f * x) * x;
4291 // error 0.0144103317, which is 6 bits
4292 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4293 getF32Constant(DAG, 0x3e814304));
4294 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4295 getF32Constant(DAG, 0x3f3c50c8));
4296 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4297 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4298 getF32Constant(DAG, 0x3f7f5e7e));
4299 } else if (LimitFloatPrecision <= 12) {
4300 // For floating-point precision of 12:
4302 // TwoToFractionalPartOfX =
4305 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4307 // error 0.000107046256, which is 13 to 14 bits
4308 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4309 getF32Constant(DAG, 0x3da235e3));
4310 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4311 getF32Constant(DAG, 0x3e65b8f3));
4312 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4313 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4314 getF32Constant(DAG, 0x3f324b07));
4315 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4316 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4317 getF32Constant(DAG, 0x3f7ff8fd));
4318 } else { // LimitFloatPrecision <= 18
4319 // For floating-point precision of 18:
4321 // TwoToFractionalPartOfX =
4325 // (0.554906021e-1f +
4326 // (0.961591928e-2f +
4327 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4328 // error 2.47208000*10^(-7), which is better than 18 bits
4329 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4330 getF32Constant(DAG, 0x3924b03e));
4331 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4332 getF32Constant(DAG, 0x3ab24b87));
4333 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4334 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4335 getF32Constant(DAG, 0x3c1d8c17));
4336 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4337 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4338 getF32Constant(DAG, 0x3d634a1d));
4339 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4340 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4341 getF32Constant(DAG, 0x3e75fe14));
4342 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4343 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4344 getF32Constant(DAG, 0x3f317234));
4345 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4346 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4347 getF32Constant(DAG, 0x3f800000));
4350 // Add the exponent into the result in integer domain.
4351 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4352 TwoToFractionalPartOfX);
4353 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4354 DAG.getNode(ISD::ADD, dl, MVT::i32,
4355 t13, IntegerPartOfX));
4358 // No special expansion.
4359 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4362 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4363 /// limited-precision mode with x == 10.0f.
4364 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4365 SelectionDAG &DAG, const TargetLowering &TLI) {
4366 bool IsExp10 = false;
4367 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4368 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4369 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4371 IsExp10 = LHSC->isExactlyValue(Ten);
4376 // Put the exponent in the right bit position for later addition to the
4379 // #define LOG2OF10 3.3219281f
4380 // IntegerPartOfX = (int32_t)(x * LOG2OF10);
4381 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4382 getF32Constant(DAG, 0x40549a78));
4383 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
4385 // FractionalPartOfX = x - (float)IntegerPartOfX;
4386 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
4387 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
4389 // IntegerPartOfX <<= 23;
4390 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
4391 DAG.getConstant(23, TLI.getPointerTy()));
4393 SDValue TwoToFractionalPartOfX;
4394 if (LimitFloatPrecision <= 6) {
4395 // For floating-point precision of 6:
4397 // twoToFractionalPartOfX =
4399 // (0.735607626f + 0.252464424f * x) * x;
4401 // error 0.0144103317, which is 6 bits
4402 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4403 getF32Constant(DAG, 0x3e814304));
4404 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4405 getF32Constant(DAG, 0x3f3c50c8));
4406 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4407 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4408 getF32Constant(DAG, 0x3f7f5e7e));
4409 } else if (LimitFloatPrecision <= 12) {
4410 // For floating-point precision of 12:
4412 // TwoToFractionalPartOfX =
4415 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
4417 // error 0.000107046256, which is 13 to 14 bits
4418 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4419 getF32Constant(DAG, 0x3da235e3));
4420 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4421 getF32Constant(DAG, 0x3e65b8f3));
4422 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4423 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4424 getF32Constant(DAG, 0x3f324b07));
4425 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4426 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4427 getF32Constant(DAG, 0x3f7ff8fd));
4428 } else { // LimitFloatPrecision <= 18
4429 // For floating-point precision of 18:
4431 // TwoToFractionalPartOfX =
4435 // (0.554906021e-1f +
4436 // (0.961591928e-2f +
4437 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
4438 // error 2.47208000*10^(-7), which is better than 18 bits
4439 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4440 getF32Constant(DAG, 0x3924b03e));
4441 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4442 getF32Constant(DAG, 0x3ab24b87));
4443 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4444 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4445 getF32Constant(DAG, 0x3c1d8c17));
4446 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4447 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4448 getF32Constant(DAG, 0x3d634a1d));
4449 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4450 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4451 getF32Constant(DAG, 0x3e75fe14));
4452 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4453 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
4454 getF32Constant(DAG, 0x3f317234));
4455 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
4456 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
4457 getF32Constant(DAG, 0x3f800000));
4460 SDValue t13 = DAG.getNode(ISD::BITCAST, dl,MVT::i32,TwoToFractionalPartOfX);
4461 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4462 DAG.getNode(ISD::ADD, dl, MVT::i32,
4463 t13, IntegerPartOfX));
4466 // No special expansion.
4467 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4471 /// ExpandPowI - Expand a llvm.powi intrinsic.
4472 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4473 SelectionDAG &DAG) {
4474 // If RHS is a constant, we can expand this out to a multiplication tree,
4475 // otherwise we end up lowering to a call to __powidf2 (for example). When
4476 // optimizing for size, we only want to do this if the expansion would produce
4477 // a small number of multiplies, otherwise we do the full expansion.
4478 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4479 // Get the exponent as a positive value.
4480 unsigned Val = RHSC->getSExtValue();
4481 if ((int)Val < 0) Val = -Val;
4483 // powi(x, 0) -> 1.0
4485 return DAG.getConstantFP(1.0, LHS.getValueType());
4487 const Function *F = DAG.getMachineFunction().getFunction();
4488 if (!F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
4489 Attribute::OptimizeForSize) ||
4490 // If optimizing for size, don't insert too many multiplies. This
4491 // inserts up to 5 multiplies.
4492 CountPopulation_32(Val)+Log2_32(Val) < 7) {
4493 // We use the simple binary decomposition method to generate the multiply
4494 // sequence. There are more optimal ways to do this (for example,
4495 // powi(x,15) generates one more multiply than it should), but this has
4496 // the benefit of being both really simple and much better than a libcall.
4497 SDValue Res; // Logically starts equal to 1.0
4498 SDValue CurSquare = LHS;
4502 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4504 Res = CurSquare; // 1.0*CurSquare.
4507 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4508 CurSquare, CurSquare);
4512 // If the original was negative, invert the result, producing 1/(x*x*x).
4513 if (RHSC->getSExtValue() < 0)
4514 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4515 DAG.getConstantFP(1.0, LHS.getValueType()), Res);
4520 // Otherwise, expand to a libcall.
4521 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4524 // getTruncatedArgReg - Find underlying register used for an truncated
4526 static unsigned getTruncatedArgReg(const SDValue &N) {
4527 if (N.getOpcode() != ISD::TRUNCATE)
4530 const SDValue &Ext = N.getOperand(0);
4531 if (Ext.getOpcode() == ISD::AssertZext ||
4532 Ext.getOpcode() == ISD::AssertSext) {
4533 const SDValue &CFR = Ext.getOperand(0);
4534 if (CFR.getOpcode() == ISD::CopyFromReg)
4535 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
4536 if (CFR.getOpcode() == ISD::TRUNCATE)
4537 return getTruncatedArgReg(CFR);
4542 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4543 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4544 /// At the end of instruction selection, they will be inserted to the entry BB.
4546 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
4549 const Argument *Arg = dyn_cast<Argument>(V);
4553 MachineFunction &MF = DAG.getMachineFunction();
4554 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo();
4556 // Ignore inlined function arguments here.
4557 DIVariable DV(Variable);
4558 if (DV.isInlinedFnArgument(MF.getFunction()))
4561 Optional<MachineOperand> Op;
4562 // Some arguments' frame index is recorded during argument lowering.
4563 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4564 Op = MachineOperand::CreateFI(FI);
4566 if (!Op && N.getNode()) {
4568 if (N.getOpcode() == ISD::CopyFromReg)
4569 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg();
4571 Reg = getTruncatedArgReg(N);
4572 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4573 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4574 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4579 Op = MachineOperand::CreateReg(Reg, false);
4583 // Check if ValueMap has reg number.
4584 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4585 if (VMI != FuncInfo.ValueMap.end())
4586 Op = MachineOperand::CreateReg(VMI->second, false);
4589 if (!Op && N.getNode())
4590 // Check if frame index is available.
4591 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4592 if (FrameIndexSDNode *FINode =
4593 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4594 Op = MachineOperand::CreateFI(FINode->getIndex());
4599 // FIXME: This does not handle register-indirect values at offset 0.
4600 bool IsIndirect = Offset != 0;
4602 FuncInfo.ArgDbgValues.push_back(BuildMI(MF, getCurDebugLoc(),
4603 TII->get(TargetOpcode::DBG_VALUE),
4605 Op->getReg(), Offset, Variable));
4607 FuncInfo.ArgDbgValues.push_back(
4608 BuildMI(MF, getCurDebugLoc(), TII->get(TargetOpcode::DBG_VALUE))
4609 .addOperand(*Op).addImm(Offset).addMetadata(Variable));
4614 // VisualStudio defines setjmp as _setjmp
4615 #if defined(_MSC_VER) && defined(setjmp) && \
4616 !defined(setjmp_undefined_for_msvc)
4617 # pragma push_macro("setjmp")
4619 # define setjmp_undefined_for_msvc
4622 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4623 /// we want to emit this as a call to a named external function, return the name
4624 /// otherwise lower it and return null.
4626 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4627 const TargetLowering *TLI = TM.getTargetLowering();
4628 SDLoc sdl = getCurSDLoc();
4629 DebugLoc dl = getCurDebugLoc();
4632 switch (Intrinsic) {
4634 // By default, turn this into a target intrinsic node.
4635 visitTargetIntrinsic(I, Intrinsic);
4637 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4638 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4639 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4640 case Intrinsic::returnaddress:
4641 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl, TLI->getPointerTy(),
4642 getValue(I.getArgOperand(0))));
4644 case Intrinsic::frameaddress:
4645 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl, TLI->getPointerTy(),
4646 getValue(I.getArgOperand(0))));
4648 case Intrinsic::setjmp:
4649 return &"_setjmp"[!TLI->usesUnderscoreSetJmp()];
4650 case Intrinsic::longjmp:
4651 return &"_longjmp"[!TLI->usesUnderscoreLongJmp()];
4652 case Intrinsic::memcpy: {
4653 // Assert for address < 256 since we support only user defined address
4655 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4657 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4659 "Unknown address space");
4660 SDValue Op1 = getValue(I.getArgOperand(0));
4661 SDValue Op2 = getValue(I.getArgOperand(1));
4662 SDValue Op3 = getValue(I.getArgOperand(2));
4663 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4665 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4666 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4667 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false,
4668 MachinePointerInfo(I.getArgOperand(0)),
4669 MachinePointerInfo(I.getArgOperand(1))));
4672 case Intrinsic::memset: {
4673 // Assert for address < 256 since we support only user defined address
4675 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4677 "Unknown address space");
4678 SDValue Op1 = getValue(I.getArgOperand(0));
4679 SDValue Op2 = getValue(I.getArgOperand(1));
4680 SDValue Op3 = getValue(I.getArgOperand(2));
4681 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4683 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4684 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4685 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4686 MachinePointerInfo(I.getArgOperand(0))));
4689 case Intrinsic::memmove: {
4690 // Assert for address < 256 since we support only user defined address
4692 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4694 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4696 "Unknown address space");
4697 SDValue Op1 = getValue(I.getArgOperand(0));
4698 SDValue Op2 = getValue(I.getArgOperand(1));
4699 SDValue Op3 = getValue(I.getArgOperand(2));
4700 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4702 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4703 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4704 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4705 MachinePointerInfo(I.getArgOperand(0)),
4706 MachinePointerInfo(I.getArgOperand(1))));
4709 case Intrinsic::dbg_declare: {
4710 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4711 MDNode *Variable = DI.getVariable();
4712 const Value *Address = DI.getAddress();
4713 DIVariable DIVar(Variable);
4714 assert((!DIVar || DIVar.isVariable()) &&
4715 "Variable in DbgDeclareInst should be either null or a DIVariable.");
4716 if (!Address || !DIVar) {
4717 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4721 // Check if address has undef value.
4722 if (isa<UndefValue>(Address) ||
4723 (Address->use_empty() && !isa<Argument>(Address))) {
4724 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4728 SDValue &N = NodeMap[Address];
4729 if (!N.getNode() && isa<Argument>(Address))
4730 // Check unused arguments map.
4731 N = UnusedArgNodeMap[Address];
4734 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4735 Address = BCI->getOperand(0);
4736 // Parameters are handled specially.
4738 (DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable ||
4739 isa<Argument>(Address));
4741 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4743 if (isParameter && !AI) {
4744 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4746 // Byval parameter. We have a frame index at this point.
4747 SDV = DAG.getDbgValue(Variable, FINode->getIndex(),
4748 0, dl, SDNodeOrder);
4750 // Address is an argument, so try to emit its dbg value using
4751 // virtual register info from the FuncInfo.ValueMap.
4752 EmitFuncArgumentDbgValue(Address, Variable, 0, N);
4756 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(),
4757 0, dl, SDNodeOrder);
4759 // Can't do anything with other non-AI cases yet.
4760 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4761 DEBUG(dbgs() << "non-AllocaInst issue for Address: \n\t");
4762 DEBUG(Address->dump());
4765 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4767 // If Address is an argument then try to emit its dbg value using
4768 // virtual register info from the FuncInfo.ValueMap.
4769 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) {
4770 // If variable is pinned by a alloca in dominating bb then
4771 // use StaticAllocaMap.
4772 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4773 if (AI->getParent() != DI.getParent()) {
4774 DenseMap<const AllocaInst*, int>::iterator SI =
4775 FuncInfo.StaticAllocaMap.find(AI);
4776 if (SI != FuncInfo.StaticAllocaMap.end()) {
4777 SDV = DAG.getDbgValue(Variable, SI->second,
4778 0, dl, SDNodeOrder);
4779 DAG.AddDbgValue(SDV, nullptr, false);
4784 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4789 case Intrinsic::dbg_value: {
4790 const DbgValueInst &DI = cast<DbgValueInst>(I);
4791 DIVariable DIVar(DI.getVariable());
4792 assert((!DIVar || DIVar.isVariable()) &&
4793 "Variable in DbgValueInst should be either null or a DIVariable.");
4797 MDNode *Variable = DI.getVariable();
4798 uint64_t Offset = DI.getOffset();
4799 const Value *V = DI.getValue();
4804 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4805 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
4806 DAG.AddDbgValue(SDV, nullptr, false);
4808 // Do not use getValue() in here; we don't want to generate code at
4809 // this point if it hasn't been done yet.
4810 SDValue N = NodeMap[V];
4811 if (!N.getNode() && isa<Argument>(V))
4812 // Check unused arguments map.
4813 N = UnusedArgNodeMap[V];
4815 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) {
4816 SDV = DAG.getDbgValue(Variable, N.getNode(),
4817 N.getResNo(), Offset, dl, SDNodeOrder);
4818 DAG.AddDbgValue(SDV, N.getNode(), false);
4820 } else if (!V->use_empty() ) {
4821 // Do not call getValue(V) yet, as we don't want to generate code.
4822 // Remember it for later.
4823 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4824 DanglingDebugInfoMap[V] = DDI;
4826 // We may expand this to cover more cases. One case where we have no
4827 // data available is an unreferenced parameter.
4828 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4832 // Build a debug info table entry.
4833 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4834 V = BCI->getOperand(0);
4835 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4836 // Don't handle byval struct arguments or VLAs, for example.
4838 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4839 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4842 DenseMap<const AllocaInst*, int>::iterator SI =
4843 FuncInfo.StaticAllocaMap.find(AI);
4844 if (SI == FuncInfo.StaticAllocaMap.end())
4845 return nullptr; // VLAs.
4846 int FI = SI->second;
4848 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4849 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo())
4850 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc());
4854 case Intrinsic::eh_typeid_for: {
4855 // Find the type id for the given typeinfo.
4856 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0));
4857 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4858 Res = DAG.getConstant(TypeID, MVT::i32);
4863 case Intrinsic::eh_return_i32:
4864 case Intrinsic::eh_return_i64:
4865 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4866 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4869 getValue(I.getArgOperand(0)),
4870 getValue(I.getArgOperand(1))));
4872 case Intrinsic::eh_unwind_init:
4873 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4875 case Intrinsic::eh_dwarf_cfa: {
4876 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4877 TLI->getPointerTy());
4878 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4879 CfaArg.getValueType(),
4880 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4881 CfaArg.getValueType()),
4883 SDValue FA = DAG.getNode(ISD::FRAMEADDR, sdl,
4884 TLI->getPointerTy(),
4885 DAG.getConstant(0, TLI->getPointerTy()));
4886 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4890 case Intrinsic::eh_sjlj_callsite: {
4891 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4892 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4893 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4894 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4896 MMI.setCurrentCallSite(CI->getZExtValue());
4899 case Intrinsic::eh_sjlj_functioncontext: {
4900 // Get and store the index of the function context.
4901 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4903 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4904 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4905 MFI->setFunctionContextIndex(FI);
4908 case Intrinsic::eh_sjlj_setjmp: {
4911 Ops[1] = getValue(I.getArgOperand(0));
4912 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4913 DAG.getVTList(MVT::i32, MVT::Other),
4915 setValue(&I, Op.getValue(0));
4916 DAG.setRoot(Op.getValue(1));
4919 case Intrinsic::eh_sjlj_longjmp: {
4920 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4921 getRoot(), getValue(I.getArgOperand(0))));
4925 case Intrinsic::x86_mmx_pslli_w:
4926 case Intrinsic::x86_mmx_pslli_d:
4927 case Intrinsic::x86_mmx_pslli_q:
4928 case Intrinsic::x86_mmx_psrli_w:
4929 case Intrinsic::x86_mmx_psrli_d:
4930 case Intrinsic::x86_mmx_psrli_q:
4931 case Intrinsic::x86_mmx_psrai_w:
4932 case Intrinsic::x86_mmx_psrai_d: {
4933 SDValue ShAmt = getValue(I.getArgOperand(1));
4934 if (isa<ConstantSDNode>(ShAmt)) {
4935 visitTargetIntrinsic(I, Intrinsic);
4938 unsigned NewIntrinsic = 0;
4939 EVT ShAmtVT = MVT::v2i32;
4940 switch (Intrinsic) {
4941 case Intrinsic::x86_mmx_pslli_w:
4942 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4944 case Intrinsic::x86_mmx_pslli_d:
4945 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4947 case Intrinsic::x86_mmx_pslli_q:
4948 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4950 case Intrinsic::x86_mmx_psrli_w:
4951 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4953 case Intrinsic::x86_mmx_psrli_d:
4954 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4956 case Intrinsic::x86_mmx_psrli_q:
4957 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4959 case Intrinsic::x86_mmx_psrai_w:
4960 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4962 case Intrinsic::x86_mmx_psrai_d:
4963 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4965 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4968 // The vector shift intrinsics with scalars uses 32b shift amounts but
4969 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4971 // We must do this early because v2i32 is not a legal type.
4974 ShOps[1] = DAG.getConstant(0, MVT::i32);
4975 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, &ShOps[0], 2);
4976 EVT DestVT = TLI->getValueType(I.getType());
4977 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4978 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4979 DAG.getConstant(NewIntrinsic, MVT::i32),
4980 getValue(I.getArgOperand(0)), ShAmt);
4984 case Intrinsic::x86_avx_vinsertf128_pd_256:
4985 case Intrinsic::x86_avx_vinsertf128_ps_256:
4986 case Intrinsic::x86_avx_vinsertf128_si_256:
4987 case Intrinsic::x86_avx2_vinserti128: {
4988 EVT DestVT = TLI->getValueType(I.getType());
4989 EVT ElVT = TLI->getValueType(I.getArgOperand(1)->getType());
4990 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(2))->getZExtValue() & 1) *
4991 ElVT.getVectorNumElements();
4992 Res = DAG.getNode(ISD::INSERT_SUBVECTOR, sdl, DestVT,
4993 getValue(I.getArgOperand(0)),
4994 getValue(I.getArgOperand(1)),
4995 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
4999 case Intrinsic::x86_avx_vextractf128_pd_256:
5000 case Intrinsic::x86_avx_vextractf128_ps_256:
5001 case Intrinsic::x86_avx_vextractf128_si_256:
5002 case Intrinsic::x86_avx2_vextracti128: {
5003 EVT DestVT = TLI->getValueType(I.getType());
5004 uint64_t Idx = (cast<ConstantInt>(I.getArgOperand(1))->getZExtValue() & 1) *
5005 DestVT.getVectorNumElements();
5006 Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, DestVT,
5007 getValue(I.getArgOperand(0)),
5008 DAG.getConstant(Idx, TLI->getVectorIdxTy()));
5012 case Intrinsic::convertff:
5013 case Intrinsic::convertfsi:
5014 case Intrinsic::convertfui:
5015 case Intrinsic::convertsif:
5016 case Intrinsic::convertuif:
5017 case Intrinsic::convertss:
5018 case Intrinsic::convertsu:
5019 case Intrinsic::convertus:
5020 case Intrinsic::convertuu: {
5021 ISD::CvtCode Code = ISD::CVT_INVALID;
5022 switch (Intrinsic) {
5023 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5024 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
5025 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
5026 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
5027 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
5028 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
5029 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
5030 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
5031 case Intrinsic::convertus: Code = ISD::CVT_US; break;
5032 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
5034 EVT DestVT = TLI->getValueType(I.getType());
5035 const Value *Op1 = I.getArgOperand(0);
5036 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
5037 DAG.getValueType(DestVT),
5038 DAG.getValueType(getValue(Op1).getValueType()),
5039 getValue(I.getArgOperand(1)),
5040 getValue(I.getArgOperand(2)),
5045 case Intrinsic::powi:
5046 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
5047 getValue(I.getArgOperand(1)), DAG));
5049 case Intrinsic::log:
5050 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5052 case Intrinsic::log2:
5053 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5055 case Intrinsic::log10:
5056 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5058 case Intrinsic::exp:
5059 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5061 case Intrinsic::exp2:
5062 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, *TLI));
5064 case Intrinsic::pow:
5065 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
5066 getValue(I.getArgOperand(1)), DAG, *TLI));
5068 case Intrinsic::sqrt:
5069 case Intrinsic::fabs:
5070 case Intrinsic::sin:
5071 case Intrinsic::cos:
5072 case Intrinsic::floor:
5073 case Intrinsic::ceil:
5074 case Intrinsic::trunc:
5075 case Intrinsic::rint:
5076 case Intrinsic::nearbyint:
5077 case Intrinsic::round: {
5079 switch (Intrinsic) {
5080 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5081 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
5082 case Intrinsic::fabs: Opcode = ISD::FABS; break;
5083 case Intrinsic::sin: Opcode = ISD::FSIN; break;
5084 case Intrinsic::cos: Opcode = ISD::FCOS; break;
5085 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
5086 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
5087 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
5088 case Intrinsic::rint: Opcode = ISD::FRINT; break;
5089 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
5090 case Intrinsic::round: Opcode = ISD::FROUND; break;
5093 setValue(&I, DAG.getNode(Opcode, sdl,
5094 getValue(I.getArgOperand(0)).getValueType(),
5095 getValue(I.getArgOperand(0))));
5098 case Intrinsic::copysign:
5099 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
5100 getValue(I.getArgOperand(0)).getValueType(),
5101 getValue(I.getArgOperand(0)),
5102 getValue(I.getArgOperand(1))));
5104 case Intrinsic::fma:
5105 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5106 getValue(I.getArgOperand(0)).getValueType(),
5107 getValue(I.getArgOperand(0)),
5108 getValue(I.getArgOperand(1)),
5109 getValue(I.getArgOperand(2))));
5111 case Intrinsic::fmuladd: {
5112 EVT VT = TLI->getValueType(I.getType());
5113 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
5114 TLI->isFMAFasterThanFMulAndFAdd(VT)) {
5115 setValue(&I, DAG.getNode(ISD::FMA, sdl,
5116 getValue(I.getArgOperand(0)).getValueType(),
5117 getValue(I.getArgOperand(0)),
5118 getValue(I.getArgOperand(1)),
5119 getValue(I.getArgOperand(2))));
5121 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
5122 getValue(I.getArgOperand(0)).getValueType(),
5123 getValue(I.getArgOperand(0)),
5124 getValue(I.getArgOperand(1)));
5125 SDValue Add = DAG.getNode(ISD::FADD, sdl,
5126 getValue(I.getArgOperand(0)).getValueType(),
5128 getValue(I.getArgOperand(2)));
5133 case Intrinsic::convert_to_fp16:
5134 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, sdl,
5135 MVT::i16, getValue(I.getArgOperand(0))));
5137 case Intrinsic::convert_from_fp16:
5138 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, sdl,
5139 MVT::f32, getValue(I.getArgOperand(0))));
5141 case Intrinsic::pcmarker: {
5142 SDValue Tmp = getValue(I.getArgOperand(0));
5143 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
5146 case Intrinsic::readcyclecounter: {
5147 SDValue Op = getRoot();
5148 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
5149 DAG.getVTList(MVT::i64, MVT::Other),
5152 DAG.setRoot(Res.getValue(1));
5155 case Intrinsic::bswap:
5156 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
5157 getValue(I.getArgOperand(0)).getValueType(),
5158 getValue(I.getArgOperand(0))));
5160 case Intrinsic::cttz: {
5161 SDValue Arg = getValue(I.getArgOperand(0));
5162 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5163 EVT Ty = Arg.getValueType();
5164 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
5168 case Intrinsic::ctlz: {
5169 SDValue Arg = getValue(I.getArgOperand(0));
5170 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
5171 EVT Ty = Arg.getValueType();
5172 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
5176 case Intrinsic::ctpop: {
5177 SDValue Arg = getValue(I.getArgOperand(0));
5178 EVT Ty = Arg.getValueType();
5179 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
5182 case Intrinsic::stacksave: {
5183 SDValue Op = getRoot();
5184 Res = DAG.getNode(ISD::STACKSAVE, sdl,
5185 DAG.getVTList(TLI->getPointerTy(), MVT::Other), &Op, 1);
5187 DAG.setRoot(Res.getValue(1));
5190 case Intrinsic::stackrestore: {
5191 Res = getValue(I.getArgOperand(0));
5192 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
5195 case Intrinsic::stackprotector: {
5196 // Emit code into the DAG to store the stack guard onto the stack.
5197 MachineFunction &MF = DAG.getMachineFunction();
5198 MachineFrameInfo *MFI = MF.getFrameInfo();
5199 EVT PtrTy = TLI->getPointerTy();
5201 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value.
5202 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
5204 int FI = FuncInfo.StaticAllocaMap[Slot];
5205 MFI->setStackProtectorIndex(FI);
5207 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
5209 // Store the stack protector onto the stack.
5210 Res = DAG.getStore(getRoot(), sdl, Src, FIN,
5211 MachinePointerInfo::getFixedStack(FI),
5217 case Intrinsic::objectsize: {
5218 // If we don't know by now, we're never going to know.
5219 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
5221 assert(CI && "Non-constant type in __builtin_object_size?");
5223 SDValue Arg = getValue(I.getCalledValue());
5224 EVT Ty = Arg.getValueType();
5227 Res = DAG.getConstant(-1ULL, Ty);
5229 Res = DAG.getConstant(0, Ty);
5234 case Intrinsic::annotation:
5235 case Intrinsic::ptr_annotation:
5236 // Drop the intrinsic, but forward the value
5237 setValue(&I, getValue(I.getOperand(0)));
5239 case Intrinsic::var_annotation:
5240 // Discard annotate attributes
5243 case Intrinsic::init_trampoline: {
5244 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5248 Ops[1] = getValue(I.getArgOperand(0));
5249 Ops[2] = getValue(I.getArgOperand(1));
5250 Ops[3] = getValue(I.getArgOperand(2));
5251 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5252 Ops[5] = DAG.getSrcValue(F);
5254 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops, 6);
5259 case Intrinsic::adjust_trampoline: {
5260 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5261 TLI->getPointerTy(),
5262 getValue(I.getArgOperand(0))));
5265 case Intrinsic::gcroot:
5267 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5268 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5270 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5271 GFI->addStackRoot(FI->getIndex(), TypeMap);
5274 case Intrinsic::gcread:
5275 case Intrinsic::gcwrite:
5276 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5277 case Intrinsic::flt_rounds:
5278 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5281 case Intrinsic::expect: {
5282 // Just replace __builtin_expect(exp, c) with EXP.
5283 setValue(&I, getValue(I.getArgOperand(0)));
5287 case Intrinsic::debugtrap:
5288 case Intrinsic::trap: {
5289 StringRef TrapFuncName = TM.Options.getTrapFunctionName();
5290 if (TrapFuncName.empty()) {
5291 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5292 ISD::TRAP : ISD::DEBUGTRAP;
5293 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5296 TargetLowering::ArgListTy Args;
5298 CallLoweringInfo CLI(getRoot(), I.getType(),
5299 false, false, false, false, 0, CallingConv::C,
5300 /*isTailCall=*/false,
5301 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
5302 DAG.getExternalSymbol(TrapFuncName.data(),
5303 TLI->getPointerTy()),
5305 std::pair<SDValue, SDValue> Result = TLI->LowerCallTo(CLI);
5306 DAG.setRoot(Result.second);
5310 case Intrinsic::uadd_with_overflow:
5311 case Intrinsic::sadd_with_overflow:
5312 case Intrinsic::usub_with_overflow:
5313 case Intrinsic::ssub_with_overflow:
5314 case Intrinsic::umul_with_overflow:
5315 case Intrinsic::smul_with_overflow: {
5317 switch (Intrinsic) {
5318 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5319 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5320 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5321 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5322 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5323 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5324 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5326 SDValue Op1 = getValue(I.getArgOperand(0));
5327 SDValue Op2 = getValue(I.getArgOperand(1));
5329 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5330 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5333 case Intrinsic::prefetch: {
5335 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5337 Ops[1] = getValue(I.getArgOperand(0));
5338 Ops[2] = getValue(I.getArgOperand(1));
5339 Ops[3] = getValue(I.getArgOperand(2));
5340 Ops[4] = getValue(I.getArgOperand(3));
5341 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5342 DAG.getVTList(MVT::Other),
5344 EVT::getIntegerVT(*Context, 8),
5345 MachinePointerInfo(I.getArgOperand(0)),
5347 false, /* volatile */
5349 rw==1)); /* write */
5352 case Intrinsic::lifetime_start:
5353 case Intrinsic::lifetime_end: {
5354 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5355 // Stack coloring is not enabled in O0, discard region information.
5356 if (TM.getOptLevel() == CodeGenOpt::None)
5359 SmallVector<Value *, 4> Allocas;
5360 GetUnderlyingObjects(I.getArgOperand(1), Allocas, DL);
5362 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5363 E = Allocas.end(); Object != E; ++Object) {
5364 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5366 // Could not find an Alloca.
5367 if (!LifetimeObject)
5370 int FI = FuncInfo.StaticAllocaMap[LifetimeObject];
5374 Ops[1] = DAG.getFrameIndex(FI, TLI->getPointerTy(), true);
5375 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5377 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops, 2);
5382 case Intrinsic::invariant_start:
5383 // Discard region information.
5384 setValue(&I, DAG.getUNDEF(TLI->getPointerTy()));
5386 case Intrinsic::invariant_end:
5387 // Discard region information.
5389 case Intrinsic::stackprotectorcheck: {
5390 // Do not actually emit anything for this basic block. Instead we initialize
5391 // the stack protector descriptor and export the guard variable so we can
5392 // access it in FinishBasicBlock.
5393 const BasicBlock *BB = I.getParent();
5394 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5395 ExportFromCurrentBlock(SPDescriptor.getGuard());
5397 // Flush our exports since we are going to process a terminator.
5398 (void)getControlRoot();
5401 case Intrinsic::clear_cache:
5402 return TLI->getClearCacheBuiltinName();
5403 case Intrinsic::donothing:
5406 case Intrinsic::experimental_stackmap: {
5410 case Intrinsic::experimental_patchpoint_void:
5411 case Intrinsic::experimental_patchpoint_i64: {
5418 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5420 MachineBasicBlock *LandingPad) {
5421 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5422 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5423 Type *RetTy = FTy->getReturnType();
5424 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5425 MCSymbol *BeginLabel = nullptr;
5427 TargetLowering::ArgListTy Args;
5428 TargetLowering::ArgListEntry Entry;
5429 Args.reserve(CS.arg_size());
5431 // Check whether the function can return without sret-demotion.
5432 SmallVector<ISD::OutputArg, 4> Outs;
5433 const TargetLowering *TLI = TM.getTargetLowering();
5434 GetReturnInfo(RetTy, CS.getAttributes(), Outs, *TLI);
5436 bool CanLowerReturn = TLI->CanLowerReturn(CS.getCallingConv(),
5437 DAG.getMachineFunction(),
5438 FTy->isVarArg(), Outs,
5441 SDValue DemoteStackSlot;
5442 int DemoteStackIdx = -100;
5444 if (!CanLowerReturn) {
5445 assert(!CS.hasInAllocaArgument() &&
5446 "sret demotion is incompatible with inalloca");
5447 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(
5448 FTy->getReturnType());
5449 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(
5450 FTy->getReturnType());
5451 MachineFunction &MF = DAG.getMachineFunction();
5452 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
5453 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType());
5455 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI->getPointerTy());
5456 Entry.Node = DemoteStackSlot;
5457 Entry.Ty = StackSlotPtrType;
5458 Entry.isSExt = false;
5459 Entry.isZExt = false;
5460 Entry.isInReg = false;
5461 Entry.isSRet = true;
5462 Entry.isNest = false;
5463 Entry.isByVal = false;
5464 Entry.isReturned = false;
5465 Entry.Alignment = Align;
5466 Args.push_back(Entry);
5467 RetTy = Type::getVoidTy(FTy->getContext());
5470 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5472 const Value *V = *i;
5475 if (V->getType()->isEmptyTy())
5478 SDValue ArgNode = getValue(V);
5479 Entry.Node = ArgNode; Entry.Ty = V->getType();
5481 // Skip the first return-type Attribute to get to params.
5482 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5483 Args.push_back(Entry);
5487 // Insert a label before the invoke call to mark the try range. This can be
5488 // used to detect deletion of the invoke via the MachineModuleInfo.
5489 BeginLabel = MMI.getContext().CreateTempSymbol();
5491 // For SjLj, keep track of which landing pads go with which invokes
5492 // so as to maintain the ordering of pads in the LSDA.
5493 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5494 if (CallSiteIndex) {
5495 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5496 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex);
5498 // Now that the call site is handled, stop tracking it.
5499 MMI.setCurrentCallSite(0);
5502 // Both PendingLoads and PendingExports must be flushed here;
5503 // this call might not return.
5505 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5508 // Check if target-independent constraints permit a tail call here.
5509 // Target-dependent constraints are checked within TLI->LowerCallTo.
5510 if (isTailCall && !isInTailCallPosition(CS, *TLI))
5514 CallLoweringInfo CLI(getRoot(), RetTy, FTy, isTailCall, Callee, Args, DAG,
5516 std::pair<SDValue,SDValue> Result = TLI->LowerCallTo(CLI);
5517 assert((isTailCall || Result.second.getNode()) &&
5518 "Non-null chain expected with non-tail call!");
5519 assert((Result.second.getNode() || !Result.first.getNode()) &&
5520 "Null value expected with tail call!");
5521 if (Result.first.getNode()) {
5522 setValue(CS.getInstruction(), Result.first);
5523 } else if (!CanLowerReturn && Result.second.getNode()) {
5524 // The instruction result is the result of loading from the
5525 // hidden sret parameter.
5526 SmallVector<EVT, 1> PVTs;
5527 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType());
5529 ComputeValueVTs(*TLI, PtrRetTy, PVTs);
5530 assert(PVTs.size() == 1 && "Pointers should fit in one register");
5531 EVT PtrVT = PVTs[0];
5533 SmallVector<EVT, 4> RetTys;
5534 SmallVector<uint64_t, 4> Offsets;
5535 RetTy = FTy->getReturnType();
5536 ComputeValueVTs(*TLI, RetTy, RetTys, &Offsets);
5538 unsigned NumValues = RetTys.size();
5539 SmallVector<SDValue, 4> Values(NumValues);
5540 SmallVector<SDValue, 4> Chains(NumValues);
5542 for (unsigned i = 0; i < NumValues; ++i) {
5543 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(), PtrVT,
5545 DAG.getConstant(Offsets[i], PtrVT));
5546 SDValue L = DAG.getLoad(RetTys[i], getCurSDLoc(), Result.second, Add,
5547 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]),
5548 false, false, false, 1);
5550 Chains[i] = L.getValue(1);
5553 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
5554 MVT::Other, &Chains[0], NumValues);
5555 PendingLoads.push_back(Chain);
5557 setValue(CS.getInstruction(),
5558 DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
5559 DAG.getVTList(RetTys),
5560 &Values[0], Values.size()));
5563 if (!Result.second.getNode()) {
5564 // As a special case, a null chain means that a tail call has been emitted
5565 // and the DAG root is already updated.
5568 // Since there's no actual continuation from this block, nothing can be
5569 // relying on us setting vregs for them.
5570 PendingExports.clear();
5572 DAG.setRoot(Result.second);
5576 // Insert a label at the end of the invoke call to mark the try range. This
5577 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5578 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol();
5579 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5581 // Inform MachineModuleInfo of range.
5582 MMI.addInvoke(LandingPad, BeginLabel, EndLabel);
5586 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5587 /// value is equal or not-equal to zero.
5588 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5589 for (const User *U : V->users()) {
5590 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5591 if (IC->isEquality())
5592 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5593 if (C->isNullValue())
5595 // Unknown instruction.
5601 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5603 SelectionDAGBuilder &Builder) {
5605 // Check to see if this load can be trivially constant folded, e.g. if the
5606 // input is from a string literal.
5607 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5608 // Cast pointer to the type we really want to load.
5609 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5610 PointerType::getUnqual(LoadTy));
5612 if (const Constant *LoadCst =
5613 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput),
5615 return Builder.getValue(LoadCst);
5618 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5619 // still constant memory, the input chain can be the entry node.
5621 bool ConstantMemory = false;
5623 // Do not serialize (non-volatile) loads of constant memory with anything.
5624 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5625 Root = Builder.DAG.getEntryNode();
5626 ConstantMemory = true;
5628 // Do not serialize non-volatile loads against each other.
5629 Root = Builder.DAG.getRoot();
5632 SDValue Ptr = Builder.getValue(PtrVal);
5633 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5634 Ptr, MachinePointerInfo(PtrVal),
5636 false /*nontemporal*/,
5637 false /*isinvariant*/, 1 /* align=1 */);
5639 if (!ConstantMemory)
5640 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5644 /// processIntegerCallValue - Record the value for an instruction that
5645 /// produces an integer result, converting the type where necessary.
5646 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5649 EVT VT = TM.getTargetLowering()->getValueType(I.getType(), true);
5651 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5653 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5654 setValue(&I, Value);
5657 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5658 /// If so, return true and lower it, otherwise return false and it will be
5659 /// lowered like a normal call.
5660 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5661 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5662 if (I.getNumArgOperands() != 3)
5665 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5666 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5667 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5668 !I.getType()->isIntegerTy())
5671 const Value *Size = I.getArgOperand(2);
5672 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5673 if (CSize && CSize->getZExtValue() == 0) {
5674 EVT CallVT = TM.getTargetLowering()->getValueType(I.getType(), true);
5675 setValue(&I, DAG.getConstant(0, CallVT));
5679 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5680 std::pair<SDValue, SDValue> Res =
5681 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5682 getValue(LHS), getValue(RHS), getValue(Size),
5683 MachinePointerInfo(LHS),
5684 MachinePointerInfo(RHS));
5685 if (Res.first.getNode()) {
5686 processIntegerCallValue(I, Res.first, true);
5687 PendingLoads.push_back(Res.second);
5691 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5692 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5693 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5694 bool ActuallyDoIt = true;
5697 switch (CSize->getZExtValue()) {
5699 LoadVT = MVT::Other;
5701 ActuallyDoIt = false;
5705 LoadTy = Type::getInt16Ty(CSize->getContext());
5709 LoadTy = Type::getInt32Ty(CSize->getContext());
5713 LoadTy = Type::getInt64Ty(CSize->getContext());
5717 LoadVT = MVT::v4i32;
5718 LoadTy = Type::getInt32Ty(CSize->getContext());
5719 LoadTy = VectorType::get(LoadTy, 4);
5724 // This turns into unaligned loads. We only do this if the target natively
5725 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5726 // we'll only produce a small number of byte loads.
5728 // Require that we can find a legal MVT, and only do this if the target
5729 // supports unaligned loads of that type. Expanding into byte loads would
5731 const TargetLowering *TLI = TM.getTargetLowering();
5732 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5733 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5734 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5735 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5736 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5737 if (!TLI->isTypeLegal(LoadVT) ||
5738 !TLI->allowsUnalignedMemoryAccesses(LoadVT, SrcAS) ||
5739 !TLI->allowsUnalignedMemoryAccesses(LoadVT, DstAS))
5740 ActuallyDoIt = false;
5744 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5745 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5747 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5749 processIntegerCallValue(I, Res, false);
5758 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5759 /// form. If so, return true and lower it, otherwise return false and it
5760 /// will be lowered like a normal call.
5761 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5762 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5763 if (I.getNumArgOperands() != 3)
5766 const Value *Src = I.getArgOperand(0);
5767 const Value *Char = I.getArgOperand(1);
5768 const Value *Length = I.getArgOperand(2);
5769 if (!Src->getType()->isPointerTy() ||
5770 !Char->getType()->isIntegerTy() ||
5771 !Length->getType()->isIntegerTy() ||
5772 !I.getType()->isPointerTy())
5775 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5776 std::pair<SDValue, SDValue> Res =
5777 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5778 getValue(Src), getValue(Char), getValue(Length),
5779 MachinePointerInfo(Src));
5780 if (Res.first.getNode()) {
5781 setValue(&I, Res.first);
5782 PendingLoads.push_back(Res.second);
5789 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5790 /// optimized form. If so, return true and lower it, otherwise return false
5791 /// and it will be lowered like a normal call.
5792 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5793 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5794 if (I.getNumArgOperands() != 2)
5797 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5798 if (!Arg0->getType()->isPointerTy() ||
5799 !Arg1->getType()->isPointerTy() ||
5800 !I.getType()->isPointerTy())
5803 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5804 std::pair<SDValue, SDValue> Res =
5805 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5806 getValue(Arg0), getValue(Arg1),
5807 MachinePointerInfo(Arg0),
5808 MachinePointerInfo(Arg1), isStpcpy);
5809 if (Res.first.getNode()) {
5810 setValue(&I, Res.first);
5811 DAG.setRoot(Res.second);
5818 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5819 /// If so, return true and lower it, otherwise return false and it will be
5820 /// lowered like a normal call.
5821 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5822 // Verify that the prototype makes sense. int strcmp(void*,void*)
5823 if (I.getNumArgOperands() != 2)
5826 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5827 if (!Arg0->getType()->isPointerTy() ||
5828 !Arg1->getType()->isPointerTy() ||
5829 !I.getType()->isIntegerTy())
5832 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5833 std::pair<SDValue, SDValue> Res =
5834 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5835 getValue(Arg0), getValue(Arg1),
5836 MachinePointerInfo(Arg0),
5837 MachinePointerInfo(Arg1));
5838 if (Res.first.getNode()) {
5839 processIntegerCallValue(I, Res.first, true);
5840 PendingLoads.push_back(Res.second);
5847 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5848 /// form. If so, return true and lower it, otherwise return false and it
5849 /// will be lowered like a normal call.
5850 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5851 // Verify that the prototype makes sense. size_t strlen(char *)
5852 if (I.getNumArgOperands() != 1)
5855 const Value *Arg0 = I.getArgOperand(0);
5856 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5859 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5860 std::pair<SDValue, SDValue> Res =
5861 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5862 getValue(Arg0), MachinePointerInfo(Arg0));
5863 if (Res.first.getNode()) {
5864 processIntegerCallValue(I, Res.first, false);
5865 PendingLoads.push_back(Res.second);
5872 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5873 /// form. If so, return true and lower it, otherwise return false and it
5874 /// will be lowered like a normal call.
5875 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5876 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5877 if (I.getNumArgOperands() != 2)
5880 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5881 if (!Arg0->getType()->isPointerTy() ||
5882 !Arg1->getType()->isIntegerTy() ||
5883 !I.getType()->isIntegerTy())
5886 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5887 std::pair<SDValue, SDValue> Res =
5888 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5889 getValue(Arg0), getValue(Arg1),
5890 MachinePointerInfo(Arg0));
5891 if (Res.first.getNode()) {
5892 processIntegerCallValue(I, Res.first, false);
5893 PendingLoads.push_back(Res.second);
5900 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5901 /// operation (as expected), translate it to an SDNode with the specified opcode
5902 /// and return true.
5903 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5905 // Sanity check that it really is a unary floating-point call.
5906 if (I.getNumArgOperands() != 1 ||
5907 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5908 I.getType() != I.getArgOperand(0)->getType() ||
5909 !I.onlyReadsMemory())
5912 SDValue Tmp = getValue(I.getArgOperand(0));
5913 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5917 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5918 // Handle inline assembly differently.
5919 if (isa<InlineAsm>(I.getCalledValue())) {
5924 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5925 ComputeUsesVAFloatArgument(I, &MMI);
5927 const char *RenameFn = nullptr;
5928 if (Function *F = I.getCalledFunction()) {
5929 if (F->isDeclaration()) {
5930 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5931 if (unsigned IID = II->getIntrinsicID(F)) {
5932 RenameFn = visitIntrinsicCall(I, IID);
5937 if (unsigned IID = F->getIntrinsicID()) {
5938 RenameFn = visitIntrinsicCall(I, IID);
5944 // Check for well-known libc/libm calls. If the function is internal, it
5945 // can't be a library call.
5947 if (!F->hasLocalLinkage() && F->hasName() &&
5948 LibInfo->getLibFunc(F->getName(), Func) &&
5949 LibInfo->hasOptimizedCodeGen(Func)) {
5952 case LibFunc::copysign:
5953 case LibFunc::copysignf:
5954 case LibFunc::copysignl:
5955 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5956 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5957 I.getType() == I.getArgOperand(0)->getType() &&
5958 I.getType() == I.getArgOperand(1)->getType() &&
5959 I.onlyReadsMemory()) {
5960 SDValue LHS = getValue(I.getArgOperand(0));
5961 SDValue RHS = getValue(I.getArgOperand(1));
5962 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5963 LHS.getValueType(), LHS, RHS));
5968 case LibFunc::fabsf:
5969 case LibFunc::fabsl:
5970 if (visitUnaryFloatCall(I, ISD::FABS))
5976 if (visitUnaryFloatCall(I, ISD::FSIN))
5982 if (visitUnaryFloatCall(I, ISD::FCOS))
5986 case LibFunc::sqrtf:
5987 case LibFunc::sqrtl:
5988 case LibFunc::sqrt_finite:
5989 case LibFunc::sqrtf_finite:
5990 case LibFunc::sqrtl_finite:
5991 if (visitUnaryFloatCall(I, ISD::FSQRT))
5994 case LibFunc::floor:
5995 case LibFunc::floorf:
5996 case LibFunc::floorl:
5997 if (visitUnaryFloatCall(I, ISD::FFLOOR))
6000 case LibFunc::nearbyint:
6001 case LibFunc::nearbyintf:
6002 case LibFunc::nearbyintl:
6003 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
6007 case LibFunc::ceilf:
6008 case LibFunc::ceill:
6009 if (visitUnaryFloatCall(I, ISD::FCEIL))
6013 case LibFunc::rintf:
6014 case LibFunc::rintl:
6015 if (visitUnaryFloatCall(I, ISD::FRINT))
6018 case LibFunc::round:
6019 case LibFunc::roundf:
6020 case LibFunc::roundl:
6021 if (visitUnaryFloatCall(I, ISD::FROUND))
6024 case LibFunc::trunc:
6025 case LibFunc::truncf:
6026 case LibFunc::truncl:
6027 if (visitUnaryFloatCall(I, ISD::FTRUNC))
6031 case LibFunc::log2f:
6032 case LibFunc::log2l:
6033 if (visitUnaryFloatCall(I, ISD::FLOG2))
6037 case LibFunc::exp2f:
6038 case LibFunc::exp2l:
6039 if (visitUnaryFloatCall(I, ISD::FEXP2))
6042 case LibFunc::memcmp:
6043 if (visitMemCmpCall(I))
6046 case LibFunc::memchr:
6047 if (visitMemChrCall(I))
6050 case LibFunc::strcpy:
6051 if (visitStrCpyCall(I, false))
6054 case LibFunc::stpcpy:
6055 if (visitStrCpyCall(I, true))
6058 case LibFunc::strcmp:
6059 if (visitStrCmpCall(I))
6062 case LibFunc::strlen:
6063 if (visitStrLenCall(I))
6066 case LibFunc::strnlen:
6067 if (visitStrNLenCall(I))
6076 Callee = getValue(I.getCalledValue());
6078 Callee = DAG.getExternalSymbol(RenameFn,
6079 TM.getTargetLowering()->getPointerTy());
6081 // Check if we can potentially perform a tail call. More detailed checking is
6082 // be done within LowerCallTo, after more information about the call is known.
6083 LowerCallTo(&I, Callee, I.isTailCall());
6088 /// AsmOperandInfo - This contains information for each constraint that we are
6090 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
6092 /// CallOperand - If this is the result output operand or a clobber
6093 /// this is null, otherwise it is the incoming operand to the CallInst.
6094 /// This gets modified as the asm is processed.
6095 SDValue CallOperand;
6097 /// AssignedRegs - If this is a register or register class operand, this
6098 /// contains the set of register corresponding to the operand.
6099 RegsForValue AssignedRegs;
6101 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
6102 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
6105 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
6106 /// corresponds to. If there is no Value* for this operand, it returns
6108 EVT getCallOperandValEVT(LLVMContext &Context,
6109 const TargetLowering &TLI,
6110 const DataLayout *DL) const {
6111 if (!CallOperandVal) return MVT::Other;
6113 if (isa<BasicBlock>(CallOperandVal))
6114 return TLI.getPointerTy();
6116 llvm::Type *OpTy = CallOperandVal->getType();
6118 // FIXME: code duplicated from TargetLowering::ParseConstraints().
6119 // If this is an indirect operand, the operand is a pointer to the
6122 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
6124 report_fatal_error("Indirect operand for inline asm not a pointer!");
6125 OpTy = PtrTy->getElementType();
6128 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
6129 if (StructType *STy = dyn_cast<StructType>(OpTy))
6130 if (STy->getNumElements() == 1)
6131 OpTy = STy->getElementType(0);
6133 // If OpTy is not a single value, it may be a struct/union that we
6134 // can tile with integers.
6135 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
6136 unsigned BitSize = DL->getTypeSizeInBits(OpTy);
6145 OpTy = IntegerType::get(Context, BitSize);
6150 return TLI.getValueType(OpTy, true);
6154 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6156 } // end anonymous namespace
6158 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6159 /// specified operand. We prefer to assign virtual registers, to allow the
6160 /// register allocator to handle the assignment process. However, if the asm
6161 /// uses features that we can't model on machineinstrs, we have SDISel do the
6162 /// allocation. This produces generally horrible, but correct, code.
6164 /// OpInfo describes the operand.
6166 static void GetRegistersForValue(SelectionDAG &DAG,
6167 const TargetLowering &TLI,
6169 SDISelAsmOperandInfo &OpInfo) {
6170 LLVMContext &Context = *DAG.getContext();
6172 MachineFunction &MF = DAG.getMachineFunction();
6173 SmallVector<unsigned, 4> Regs;
6175 // If this is a constraint for a single physreg, or a constraint for a
6176 // register class, find it.
6177 std::pair<unsigned, const TargetRegisterClass*> PhysReg =
6178 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6179 OpInfo.ConstraintVT);
6181 unsigned NumRegs = 1;
6182 if (OpInfo.ConstraintVT != MVT::Other) {
6183 // If this is a FP input in an integer register (or visa versa) insert a bit
6184 // cast of the input value. More generally, handle any case where the input
6185 // value disagrees with the register class we plan to stick this in.
6186 if (OpInfo.Type == InlineAsm::isInput &&
6187 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6188 // Try to convert to the first EVT that the reg class contains. If the
6189 // types are identical size, use a bitcast to convert (e.g. two differing
6191 MVT RegVT = *PhysReg.second->vt_begin();
6192 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6193 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6194 RegVT, OpInfo.CallOperand);
6195 OpInfo.ConstraintVT = RegVT;
6196 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6197 // If the input is a FP value and we want it in FP registers, do a
6198 // bitcast to the corresponding integer type. This turns an f64 value
6199 // into i64, which can be passed with two i32 values on a 32-bit
6201 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6202 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6203 RegVT, OpInfo.CallOperand);
6204 OpInfo.ConstraintVT = RegVT;
6208 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6212 EVT ValueVT = OpInfo.ConstraintVT;
6214 // If this is a constraint for a specific physical register, like {r17},
6216 if (unsigned AssignedReg = PhysReg.first) {
6217 const TargetRegisterClass *RC = PhysReg.second;
6218 if (OpInfo.ConstraintVT == MVT::Other)
6219 ValueVT = *RC->vt_begin();
6221 // Get the actual register value type. This is important, because the user
6222 // may have asked for (e.g.) the AX register in i32 type. We need to
6223 // remember that AX is actually i16 to get the right extension.
6224 RegVT = *RC->vt_begin();
6226 // This is a explicit reference to a physical register.
6227 Regs.push_back(AssignedReg);
6229 // If this is an expanded reference, add the rest of the regs to Regs.
6231 TargetRegisterClass::iterator I = RC->begin();
6232 for (; *I != AssignedReg; ++I)
6233 assert(I != RC->end() && "Didn't find reg!");
6235 // Already added the first reg.
6237 for (; NumRegs; --NumRegs, ++I) {
6238 assert(I != RC->end() && "Ran out of registers to allocate!");
6243 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6247 // Otherwise, if this was a reference to an LLVM register class, create vregs
6248 // for this reference.
6249 if (const TargetRegisterClass *RC = PhysReg.second) {
6250 RegVT = *RC->vt_begin();
6251 if (OpInfo.ConstraintVT == MVT::Other)
6254 // Create the appropriate number of virtual registers.
6255 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6256 for (; NumRegs; --NumRegs)
6257 Regs.push_back(RegInfo.createVirtualRegister(RC));
6259 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6263 // Otherwise, we couldn't allocate enough registers for this.
6266 /// visitInlineAsm - Handle a call to an InlineAsm object.
6268 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6269 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6271 /// ConstraintOperands - Information about all of the constraints.
6272 SDISelAsmOperandInfoVector ConstraintOperands;
6274 const TargetLowering *TLI = TM.getTargetLowering();
6275 TargetLowering::AsmOperandInfoVector
6276 TargetConstraints = TLI->ParseConstraints(CS);
6278 bool hasMemory = false;
6280 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6281 unsigned ResNo = 0; // ResNo - The result number of the next output.
6282 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6283 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6284 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6286 MVT OpVT = MVT::Other;
6288 // Compute the value type for each operand.
6289 switch (OpInfo.Type) {
6290 case InlineAsm::isOutput:
6291 // Indirect outputs just consume an argument.
6292 if (OpInfo.isIndirect) {
6293 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6297 // The return value of the call is this value. As such, there is no
6298 // corresponding argument.
6299 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6300 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6301 OpVT = TLI->getSimpleValueType(STy->getElementType(ResNo));
6303 assert(ResNo == 0 && "Asm only has one result!");
6304 OpVT = TLI->getSimpleValueType(CS.getType());
6308 case InlineAsm::isInput:
6309 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6311 case InlineAsm::isClobber:
6316 // If this is an input or an indirect output, process the call argument.
6317 // BasicBlocks are labels, currently appearing only in asm's.
6318 if (OpInfo.CallOperandVal) {
6319 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6320 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6322 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6325 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), *TLI, DL).
6329 OpInfo.ConstraintVT = OpVT;
6331 // Indirect operand accesses access memory.
6332 if (OpInfo.isIndirect)
6335 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6336 TargetLowering::ConstraintType
6337 CType = TLI->getConstraintType(OpInfo.Codes[j]);
6338 if (CType == TargetLowering::C_Memory) {
6346 SDValue Chain, Flag;
6348 // We won't need to flush pending loads if this asm doesn't touch
6349 // memory and is nonvolatile.
6350 if (hasMemory || IA->hasSideEffects())
6353 Chain = DAG.getRoot();
6355 // Second pass over the constraints: compute which constraint option to use
6356 // and assign registers to constraints that want a specific physreg.
6357 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6358 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6360 // If this is an output operand with a matching input operand, look up the
6361 // matching input. If their types mismatch, e.g. one is an integer, the
6362 // other is floating point, or their sizes are different, flag it as an
6364 if (OpInfo.hasMatchingInput()) {
6365 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6367 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6368 std::pair<unsigned, const TargetRegisterClass*> MatchRC =
6369 TLI->getRegForInlineAsmConstraint(OpInfo.ConstraintCode,
6370 OpInfo.ConstraintVT);
6371 std::pair<unsigned, const TargetRegisterClass*> InputRC =
6372 TLI->getRegForInlineAsmConstraint(Input.ConstraintCode,
6373 Input.ConstraintVT);
6374 if ((OpInfo.ConstraintVT.isInteger() !=
6375 Input.ConstraintVT.isInteger()) ||
6376 (MatchRC.second != InputRC.second)) {
6377 report_fatal_error("Unsupported asm: input constraint"
6378 " with a matching output constraint of"
6379 " incompatible type!");
6381 Input.ConstraintVT = OpInfo.ConstraintVT;
6385 // Compute the constraint code and ConstraintType to use.
6386 TLI->ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6388 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6389 OpInfo.Type == InlineAsm::isClobber)
6392 // If this is a memory input, and if the operand is not indirect, do what we
6393 // need to to provide an address for the memory input.
6394 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6395 !OpInfo.isIndirect) {
6396 assert((OpInfo.isMultipleAlternative ||
6397 (OpInfo.Type == InlineAsm::isInput)) &&
6398 "Can only indirectify direct input operands!");
6400 // Memory operands really want the address of the value. If we don't have
6401 // an indirect input, put it in the constpool if we can, otherwise spill
6402 // it to a stack slot.
6403 // TODO: This isn't quite right. We need to handle these according to
6404 // the addressing mode that the constraint wants. Also, this may take
6405 // an additional register for the computation and we don't want that
6408 // If the operand is a float, integer, or vector constant, spill to a
6409 // constant pool entry to get its address.
6410 const Value *OpVal = OpInfo.CallOperandVal;
6411 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6412 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6413 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal),
6414 TLI->getPointerTy());
6416 // Otherwise, create a stack slot and emit a store to it before the
6418 Type *Ty = OpVal->getType();
6419 uint64_t TySize = TLI->getDataLayout()->getTypeAllocSize(Ty);
6420 unsigned Align = TLI->getDataLayout()->getPrefTypeAlignment(Ty);
6421 MachineFunction &MF = DAG.getMachineFunction();
6422 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6423 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI->getPointerTy());
6424 Chain = DAG.getStore(Chain, getCurSDLoc(),
6425 OpInfo.CallOperand, StackSlot,
6426 MachinePointerInfo::getFixedStack(SSFI),
6428 OpInfo.CallOperand = StackSlot;
6431 // There is no longer a Value* corresponding to this operand.
6432 OpInfo.CallOperandVal = nullptr;
6434 // It is now an indirect operand.
6435 OpInfo.isIndirect = true;
6438 // If this constraint is for a specific register, allocate it before
6440 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6441 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6444 // Second pass - Loop over all of the operands, assigning virtual or physregs
6445 // to register class operands.
6446 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6447 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6449 // C_Register operands have already been allocated, Other/Memory don't need
6451 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6452 GetRegistersForValue(DAG, *TLI, getCurSDLoc(), OpInfo);
6455 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6456 std::vector<SDValue> AsmNodeOperands;
6457 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6458 AsmNodeOperands.push_back(
6459 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(),
6460 TLI->getPointerTy()));
6462 // If we have a !srcloc metadata node associated with it, we want to attach
6463 // this to the ultimately generated inline asm machineinstr. To do this, we
6464 // pass in the third operand as this (potentially null) inline asm MDNode.
6465 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6466 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6468 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6469 // bits as operand 3.
6470 unsigned ExtraInfo = 0;
6471 if (IA->hasSideEffects())
6472 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6473 if (IA->isAlignStack())
6474 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6475 // Set the asm dialect.
6476 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6478 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6479 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6480 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6482 // Compute the constraint code and ConstraintType to use.
6483 TLI->ComputeConstraintToUse(OpInfo, SDValue());
6485 // Ideally, we would only check against memory constraints. However, the
6486 // meaning of an other constraint can be target-specific and we can't easily
6487 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6488 // for other constriants as well.
6489 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6490 OpInfo.ConstraintType == TargetLowering::C_Other) {
6491 if (OpInfo.Type == InlineAsm::isInput)
6492 ExtraInfo |= InlineAsm::Extra_MayLoad;
6493 else if (OpInfo.Type == InlineAsm::isOutput)
6494 ExtraInfo |= InlineAsm::Extra_MayStore;
6495 else if (OpInfo.Type == InlineAsm::isClobber)
6496 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6500 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo,
6501 TLI->getPointerTy()));
6503 // Loop over all of the inputs, copying the operand values into the
6504 // appropriate registers and processing the output regs.
6505 RegsForValue RetValRegs;
6507 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6508 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6510 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6511 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6513 switch (OpInfo.Type) {
6514 case InlineAsm::isOutput: {
6515 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6516 OpInfo.ConstraintType != TargetLowering::C_Register) {
6517 // Memory output, or 'other' output (e.g. 'X' constraint).
6518 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6520 // Add information to the INLINEASM node to know about this output.
6521 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6522 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags,
6523 TLI->getPointerTy()));
6524 AsmNodeOperands.push_back(OpInfo.CallOperand);
6528 // Otherwise, this is a register or register class output.
6530 // Copy the output from the appropriate register. Find a register that
6532 if (OpInfo.AssignedRegs.Regs.empty()) {
6533 LLVMContext &Ctx = *DAG.getContext();
6534 Ctx.emitError(CS.getInstruction(),
6535 "couldn't allocate output register for constraint '" +
6536 Twine(OpInfo.ConstraintCode) + "'");
6540 // If this is an indirect operand, store through the pointer after the
6542 if (OpInfo.isIndirect) {
6543 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6544 OpInfo.CallOperandVal));
6546 // This is the result value of the call.
6547 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6548 // Concatenate this output onto the outputs list.
6549 RetValRegs.append(OpInfo.AssignedRegs);
6552 // Add information to the INLINEASM node to know that this register is
6555 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6556 ? InlineAsm::Kind_RegDefEarlyClobber
6557 : InlineAsm::Kind_RegDef,
6558 false, 0, DAG, AsmNodeOperands);
6561 case InlineAsm::isInput: {
6562 SDValue InOperandVal = OpInfo.CallOperand;
6564 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6565 // If this is required to match an output register we have already set,
6566 // just use its register.
6567 unsigned OperandNo = OpInfo.getMatchedOperand();
6569 // Scan until we find the definition we already emitted of this operand.
6570 // When we find it, create a RegsForValue operand.
6571 unsigned CurOp = InlineAsm::Op_FirstOperand;
6572 for (; OperandNo; --OperandNo) {
6573 // Advance to the next operand.
6575 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6576 assert((InlineAsm::isRegDefKind(OpFlag) ||
6577 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6578 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6579 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6583 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6584 if (InlineAsm::isRegDefKind(OpFlag) ||
6585 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6586 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6587 if (OpInfo.isIndirect) {
6588 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6589 LLVMContext &Ctx = *DAG.getContext();
6590 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6591 " don't know how to handle tied "
6592 "indirect register inputs");
6596 RegsForValue MatchedRegs;
6597 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6598 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6599 MatchedRegs.RegVTs.push_back(RegVT);
6600 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6601 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6603 if (const TargetRegisterClass *RC = TLI->getRegClassFor(RegVT))
6604 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6606 LLVMContext &Ctx = *DAG.getContext();
6607 Ctx.emitError(CS.getInstruction(),
6608 "inline asm error: This value"
6609 " type register class is not natively supported!");
6613 // Use the produced MatchedRegs object to
6614 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6615 Chain, &Flag, CS.getInstruction());
6616 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6617 true, OpInfo.getMatchedOperand(),
6618 DAG, AsmNodeOperands);
6622 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6623 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6624 "Unexpected number of operands");
6625 // Add information to the INLINEASM node to know about this input.
6626 // See InlineAsm.h isUseOperandTiedToDef.
6627 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6628 OpInfo.getMatchedOperand());
6629 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag,
6630 TLI->getPointerTy()));
6631 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6635 // Treat indirect 'X' constraint as memory.
6636 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6638 OpInfo.ConstraintType = TargetLowering::C_Memory;
6640 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6641 std::vector<SDValue> Ops;
6642 TLI->LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6645 LLVMContext &Ctx = *DAG.getContext();
6646 Ctx.emitError(CS.getInstruction(),
6647 "invalid operand for inline asm constraint '" +
6648 Twine(OpInfo.ConstraintCode) + "'");
6652 // Add information to the INLINEASM node to know about this input.
6653 unsigned ResOpType =
6654 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6655 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6656 TLI->getPointerTy()));
6657 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6661 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6662 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6663 assert(InOperandVal.getValueType() == TLI->getPointerTy() &&
6664 "Memory operands expect pointer values");
6666 // Add information to the INLINEASM node to know about this input.
6667 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6668 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6669 TLI->getPointerTy()));
6670 AsmNodeOperands.push_back(InOperandVal);
6674 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6675 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6676 "Unknown constraint type!");
6678 // TODO: Support this.
6679 if (OpInfo.isIndirect) {
6680 LLVMContext &Ctx = *DAG.getContext();
6681 Ctx.emitError(CS.getInstruction(),
6682 "Don't know how to handle indirect register inputs yet "
6683 "for constraint '" +
6684 Twine(OpInfo.ConstraintCode) + "'");
6688 // Copy the input into the appropriate registers.
6689 if (OpInfo.AssignedRegs.Regs.empty()) {
6690 LLVMContext &Ctx = *DAG.getContext();
6691 Ctx.emitError(CS.getInstruction(),
6692 "couldn't allocate input reg for constraint '" +
6693 Twine(OpInfo.ConstraintCode) + "'");
6697 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurSDLoc(),
6698 Chain, &Flag, CS.getInstruction());
6700 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6701 DAG, AsmNodeOperands);
6704 case InlineAsm::isClobber: {
6705 // Add the clobbered value to the operand list, so that the register
6706 // allocator is aware that the physreg got clobbered.
6707 if (!OpInfo.AssignedRegs.Regs.empty())
6708 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6716 // Finish up input operands. Set the input chain and add the flag last.
6717 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6718 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6720 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6721 DAG.getVTList(MVT::Other, MVT::Glue),
6722 &AsmNodeOperands[0], AsmNodeOperands.size());
6723 Flag = Chain.getValue(1);
6725 // If this asm returns a register value, copy the result from that register
6726 // and set it as the value of the call.
6727 if (!RetValRegs.Regs.empty()) {
6728 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6729 Chain, &Flag, CS.getInstruction());
6731 // FIXME: Why don't we do this for inline asms with MRVs?
6732 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6733 EVT ResultType = TLI->getValueType(CS.getType());
6735 // If any of the results of the inline asm is a vector, it may have the
6736 // wrong width/num elts. This can happen for register classes that can
6737 // contain multiple different value types. The preg or vreg allocated may
6738 // not have the same VT as was expected. Convert it to the right type
6739 // with bit_convert.
6740 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6741 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6744 } else if (ResultType != Val.getValueType() &&
6745 ResultType.isInteger() && Val.getValueType().isInteger()) {
6746 // If a result value was tied to an input value, the computed result may
6747 // have a wider width than the expected result. Extract the relevant
6749 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6752 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6755 setValue(CS.getInstruction(), Val);
6756 // Don't need to use this as a chain in this case.
6757 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6761 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6763 // Process indirect outputs, first output all of the flagged copies out of
6765 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6766 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6767 const Value *Ptr = IndirectStoresToEmit[i].second;
6768 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6770 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6773 // Emit the non-flagged stores from the physregs.
6774 SmallVector<SDValue, 8> OutChains;
6775 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6776 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6777 StoresToEmit[i].first,
6778 getValue(StoresToEmit[i].second),
6779 MachinePointerInfo(StoresToEmit[i].second),
6781 OutChains.push_back(Val);
6784 if (!OutChains.empty())
6785 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
6786 &OutChains[0], OutChains.size());
6791 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6792 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6793 MVT::Other, getRoot(),
6794 getValue(I.getArgOperand(0)),
6795 DAG.getSrcValue(I.getArgOperand(0))));
6798 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6799 const TargetLowering *TLI = TM.getTargetLowering();
6800 const DataLayout &DL = *TLI->getDataLayout();
6801 SDValue V = DAG.getVAArg(TLI->getValueType(I.getType()), getCurSDLoc(),
6802 getRoot(), getValue(I.getOperand(0)),
6803 DAG.getSrcValue(I.getOperand(0)),
6804 DL.getABITypeAlignment(I.getType()));
6806 DAG.setRoot(V.getValue(1));
6809 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6810 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6811 MVT::Other, getRoot(),
6812 getValue(I.getArgOperand(0)),
6813 DAG.getSrcValue(I.getArgOperand(0))));
6816 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6817 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6818 MVT::Other, getRoot(),
6819 getValue(I.getArgOperand(0)),
6820 getValue(I.getArgOperand(1)),
6821 DAG.getSrcValue(I.getArgOperand(0)),
6822 DAG.getSrcValue(I.getArgOperand(1))));
6825 /// \brief Lower an argument list according to the target calling convention.
6827 /// \return A tuple of <return-value, token-chain>
6829 /// This is a helper for lowering intrinsics that follow a target calling
6830 /// convention or require stack pointer adjustment. Only a subset of the
6831 /// intrinsic's operands need to participate in the calling convention.
6832 std::pair<SDValue, SDValue>
6833 SelectionDAGBuilder::LowerCallOperands(const CallInst &CI, unsigned ArgIdx,
6834 unsigned NumArgs, SDValue Callee,
6836 TargetLowering::ArgListTy Args;
6837 Args.reserve(NumArgs);
6839 // Populate the argument list.
6840 // Attributes for args start at offset 1, after the return attribute.
6841 ImmutableCallSite CS(&CI);
6842 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6843 ArgI != ArgE; ++ArgI) {
6844 const Value *V = CI.getOperand(ArgI);
6846 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6848 TargetLowering::ArgListEntry Entry;
6849 Entry.Node = getValue(V);
6850 Entry.Ty = V->getType();
6851 Entry.setAttributes(&CS, AttrI);
6852 Args.push_back(Entry);
6855 Type *retTy = useVoidTy ? Type::getVoidTy(*DAG.getContext()) : CI.getType();
6856 TargetLowering::CallLoweringInfo CLI(getRoot(), retTy, /*retSExt*/ false,
6857 /*retZExt*/ false, /*isVarArg*/ false, /*isInReg*/ false, NumArgs,
6858 CI.getCallingConv(), /*isTailCall*/ false, /*doesNotReturn*/ false,
6859 /*isReturnValueUsed*/ CI.use_empty(), Callee, Args, DAG, getCurSDLoc());
6861 const TargetLowering *TLI = TM.getTargetLowering();
6862 return TLI->LowerCallTo(CLI);
6865 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6866 /// or patchpoint target node's operand list.
6868 /// Constants are converted to TargetConstants purely as an optimization to
6869 /// avoid constant materialization and register allocation.
6871 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6872 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6873 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6874 /// address materialization and register allocation, but may also be required
6875 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6876 /// alloca in the entry block, then the runtime may assume that the alloca's
6877 /// StackMap location can be read immediately after compilation and that the
6878 /// location is valid at any point during execution (this is similar to the
6879 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6880 /// only available in a register, then the runtime would need to trap when
6881 /// execution reaches the StackMap in order to read the alloca's location.
6882 static void addStackMapLiveVars(const CallInst &CI, unsigned StartIdx,
6883 SmallVectorImpl<SDValue> &Ops,
6884 SelectionDAGBuilder &Builder) {
6885 for (unsigned i = StartIdx, e = CI.getNumArgOperands(); i != e; ++i) {
6886 SDValue OpVal = Builder.getValue(CI.getArgOperand(i));
6887 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6889 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, MVT::i64));
6891 Builder.DAG.getTargetConstant(C->getSExtValue(), MVT::i64));
6892 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6893 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6895 Builder.DAG.getTargetFrameIndex(FI->getIndex(), TLI.getPointerTy()));
6897 Ops.push_back(OpVal);
6901 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6902 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6903 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6904 // [live variables...])
6906 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6908 SDValue Chain, InFlag, Callee, NullPtr;
6909 SmallVector<SDValue, 32> Ops;
6911 SDLoc DL = getCurSDLoc();
6912 Callee = getValue(CI.getCalledValue());
6913 NullPtr = DAG.getIntPtrConstant(0, true);
6915 // The stackmap intrinsic only records the live variables (the arguemnts
6916 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6917 // intrinsic, this won't be lowered to a function call. This means we don't
6918 // have to worry about calling conventions and target specific lowering code.
6919 // Instead we perform the call lowering right here.
6921 // chain, flag = CALLSEQ_START(chain, 0)
6922 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6923 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6925 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6926 InFlag = Chain.getValue(1);
6928 // Add the <id> and <numBytes> constants.
6929 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6930 Ops.push_back(DAG.getTargetConstant(
6931 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
6932 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6933 Ops.push_back(DAG.getTargetConstant(
6934 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
6936 // Push live variables for the stack map.
6937 addStackMapLiveVars(CI, 2, Ops, *this);
6939 // We are not pushing any register mask info here on the operands list,
6940 // because the stackmap doesn't clobber anything.
6942 // Push the chain and the glue flag.
6943 Ops.push_back(Chain);
6944 Ops.push_back(InFlag);
6946 // Create the STACKMAP node.
6947 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6948 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6949 Chain = SDValue(SM, 0);
6950 InFlag = Chain.getValue(1);
6952 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6954 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6956 // Set the root to the target-lowered call chain.
6959 // Inform the Frame Information that we have a stackmap in this function.
6960 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6963 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6964 void SelectionDAGBuilder::visitPatchpoint(const CallInst &CI) {
6965 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6970 // [live variables...])
6972 CallingConv::ID CC = CI.getCallingConv();
6973 bool isAnyRegCC = CC == CallingConv::AnyReg;
6974 bool hasDef = !CI.getType()->isVoidTy();
6975 SDValue Callee = getValue(CI.getOperand(2)); // <target>
6977 // Get the real number of arguments participating in the call <numArgs>
6978 SDValue NArgVal = getValue(CI.getArgOperand(PatchPointOpers::NArgPos));
6979 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6981 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6982 // Intrinsics include all meta-operands up to but not including CC.
6983 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6984 assert(CI.getNumArgOperands() >= NumMetaOpers + NumArgs &&
6985 "Not enough arguments provided to the patchpoint intrinsic");
6987 // For AnyRegCC the arguments are lowered later on manually.
6988 unsigned NumCallArgs = isAnyRegCC ? 0 : NumArgs;
6989 std::pair<SDValue, SDValue> Result =
6990 LowerCallOperands(CI, NumMetaOpers, NumCallArgs, Callee, isAnyRegCC);
6992 // Set the root to the target-lowered call chain.
6993 SDValue Chain = Result.second;
6996 SDNode *CallEnd = Chain.getNode();
6997 if (hasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6998 CallEnd = CallEnd->getOperand(0).getNode();
7000 /// Get a call instruction from the call sequence chain.
7001 /// Tail calls are not allowed.
7002 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
7003 "Expected a callseq node.");
7004 SDNode *Call = CallEnd->getOperand(0).getNode();
7005 bool hasGlue = Call->getGluedNode();
7007 // Replace the target specific call node with the patchable intrinsic.
7008 SmallVector<SDValue, 8> Ops;
7010 // Add the <id> and <numBytes> constants.
7011 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
7012 Ops.push_back(DAG.getTargetConstant(
7013 cast<ConstantSDNode>(IDVal)->getZExtValue(), MVT::i64));
7014 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
7015 Ops.push_back(DAG.getTargetConstant(
7016 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), MVT::i32));
7018 // Assume that the Callee is a constant address.
7019 // FIXME: handle function symbols in the future.
7021 DAG.getIntPtrConstant(cast<ConstantSDNode>(Callee)->getZExtValue(),
7022 /*isTarget=*/true));
7024 // Adjust <numArgs> to account for any arguments that have been passed on the
7026 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
7027 unsigned NumCallRegArgs = Call->getNumOperands() - (hasGlue ? 4 : 3);
7028 NumCallRegArgs = isAnyRegCC ? NumArgs : NumCallRegArgs;
7029 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, MVT::i32));
7031 // Add the calling convention
7032 Ops.push_back(DAG.getTargetConstant((unsigned)CC, MVT::i32));
7034 // Add the arguments we omitted previously. The register allocator should
7035 // place these in any free register.
7037 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
7038 Ops.push_back(getValue(CI.getArgOperand(i)));
7040 // Push the arguments from the call instruction up to the register mask.
7041 SDNode::op_iterator e = hasGlue ? Call->op_end()-2 : Call->op_end()-1;
7042 for (SDNode::op_iterator i = Call->op_begin()+2; i != e; ++i)
7045 // Push live variables for the stack map.
7046 addStackMapLiveVars(CI, NumMetaOpers + NumArgs, Ops, *this);
7048 // Push the register mask info.
7050 Ops.push_back(*(Call->op_end()-2));
7052 Ops.push_back(*(Call->op_end()-1));
7054 // Push the chain (this is originally the first operand of the call, but
7055 // becomes now the last or second to last operand).
7056 Ops.push_back(*(Call->op_begin()));
7058 // Push the glue flag (last operand).
7060 Ops.push_back(*(Call->op_end()-1));
7063 if (isAnyRegCC && hasDef) {
7064 // Create the return types based on the intrinsic definition
7065 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7066 SmallVector<EVT, 3> ValueVTs;
7067 ComputeValueVTs(TLI, CI.getType(), ValueVTs);
7068 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
7070 // There is always a chain and a glue type at the end
7071 ValueVTs.push_back(MVT::Other);
7072 ValueVTs.push_back(MVT::Glue);
7073 NodeTys = DAG.getVTList(ValueVTs);
7075 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7077 // Replace the target specific call node with a PATCHPOINT node.
7078 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
7079 getCurSDLoc(), NodeTys, Ops);
7081 // Update the NodeMap.
7084 setValue(&CI, SDValue(MN, 0));
7086 setValue(&CI, Result.first);
7089 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
7090 // call sequence. Furthermore the location of the chain and glue can change
7091 // when the AnyReg calling convention is used and the intrinsic returns a
7093 if (isAnyRegCC && hasDef) {
7094 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
7095 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
7096 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
7098 DAG.ReplaceAllUsesWith(Call, MN);
7099 DAG.DeleteNode(Call);
7101 // Inform the Frame Information that we have a patchpoint in this function.
7102 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
7105 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
7106 /// implementation, which just calls LowerCall.
7107 /// FIXME: When all targets are
7108 /// migrated to using LowerCall, this hook should be integrated into SDISel.
7109 std::pair<SDValue, SDValue>
7110 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
7111 // Handle the incoming return values from the call.
7113 SmallVector<EVT, 4> RetTys;
7114 ComputeValueVTs(*this, CLI.RetTy, RetTys);
7115 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7117 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7118 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7119 for (unsigned i = 0; i != NumRegs; ++i) {
7120 ISD::InputArg MyFlags;
7121 MyFlags.VT = RegisterVT;
7123 MyFlags.Used = CLI.IsReturnValueUsed;
7125 MyFlags.Flags.setSExt();
7127 MyFlags.Flags.setZExt();
7129 MyFlags.Flags.setInReg();
7130 CLI.Ins.push_back(MyFlags);
7134 // Handle all of the outgoing arguments.
7136 CLI.OutVals.clear();
7137 ArgListTy &Args = CLI.Args;
7138 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7139 SmallVector<EVT, 4> ValueVTs;
7140 ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
7141 for (unsigned Value = 0, NumValues = ValueVTs.size();
7142 Value != NumValues; ++Value) {
7143 EVT VT = ValueVTs[Value];
7144 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7145 SDValue Op = SDValue(Args[i].Node.getNode(),
7146 Args[i].Node.getResNo() + Value);
7147 ISD::ArgFlagsTy Flags;
7148 unsigned OriginalAlignment = getDataLayout()->getABITypeAlignment(ArgTy);
7154 if (Args[i].isInReg)
7158 if (Args[i].isByVal)
7160 if (Args[i].isInAlloca) {
7161 Flags.setInAlloca();
7162 // Set the byval flag for CCAssignFn callbacks that don't know about
7163 // inalloca. This way we can know how many bytes we should've allocated
7164 // and how many bytes a callee cleanup function will pop. If we port
7165 // inalloca to more targets, we'll have to add custom inalloca handling
7166 // in the various CC lowering callbacks.
7169 if (Args[i].isByVal || Args[i].isInAlloca) {
7170 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7171 Type *ElementTy = Ty->getElementType();
7172 Flags.setByValSize(getDataLayout()->getTypeAllocSize(ElementTy));
7173 // For ByVal, alignment should come from FE. BE will guess if this
7174 // info is not there but there are cases it cannot get right.
7175 unsigned FrameAlign;
7176 if (Args[i].Alignment)
7177 FrameAlign = Args[i].Alignment;
7179 FrameAlign = getByValTypeAlignment(ElementTy);
7180 Flags.setByValAlign(FrameAlign);
7184 Flags.setOrigAlign(OriginalAlignment);
7186 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7187 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7188 SmallVector<SDValue, 4> Parts(NumParts);
7189 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7192 ExtendKind = ISD::SIGN_EXTEND;
7193 else if (Args[i].isZExt)
7194 ExtendKind = ISD::ZERO_EXTEND;
7196 // Conservatively only handle 'returned' on non-vectors for now
7197 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7198 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7199 "unexpected use of 'returned'");
7200 // Before passing 'returned' to the target lowering code, ensure that
7201 // either the register MVT and the actual EVT are the same size or that
7202 // the return value and argument are extended in the same way; in these
7203 // cases it's safe to pass the argument register value unchanged as the
7204 // return register value (although it's at the target's option whether
7206 // TODO: allow code generation to take advantage of partially preserved
7207 // registers rather than clobbering the entire register when the
7208 // parameter extension method is not compatible with the return
7210 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7211 (ExtendKind != ISD::ANY_EXTEND &&
7212 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7213 Flags.setReturned();
7216 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7217 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7219 for (unsigned j = 0; j != NumParts; ++j) {
7220 // if it isn't first piece, alignment must be 1
7221 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7222 i < CLI.NumFixedArgs,
7223 i, j*Parts[j].getValueType().getStoreSize());
7224 if (NumParts > 1 && j == 0)
7225 MyFlags.Flags.setSplit();
7227 MyFlags.Flags.setOrigAlign(1);
7229 CLI.Outs.push_back(MyFlags);
7230 CLI.OutVals.push_back(Parts[j]);
7235 SmallVector<SDValue, 4> InVals;
7236 CLI.Chain = LowerCall(CLI, InVals);
7238 // Verify that the target's LowerCall behaved as expected.
7239 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7240 "LowerCall didn't return a valid chain!");
7241 assert((!CLI.IsTailCall || InVals.empty()) &&
7242 "LowerCall emitted a return value for a tail call!");
7243 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7244 "LowerCall didn't emit the correct number of values!");
7246 // For a tail call, the return value is merely live-out and there aren't
7247 // any nodes in the DAG representing it. Return a special value to
7248 // indicate that a tail call has been emitted and no more Instructions
7249 // should be processed in the current block.
7250 if (CLI.IsTailCall) {
7251 CLI.DAG.setRoot(CLI.Chain);
7252 return std::make_pair(SDValue(), SDValue());
7255 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7256 assert(InVals[i].getNode() &&
7257 "LowerCall emitted a null value!");
7258 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7259 "LowerCall emitted a value with the wrong type!");
7262 // Collect the legal value parts into potentially illegal values
7263 // that correspond to the original function's return values.
7264 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7266 AssertOp = ISD::AssertSext;
7267 else if (CLI.RetZExt)
7268 AssertOp = ISD::AssertZext;
7269 SmallVector<SDValue, 4> ReturnValues;
7270 unsigned CurReg = 0;
7271 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7273 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7274 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7276 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7277 NumRegs, RegisterVT, VT, nullptr,
7282 // For a function returning void, there is no return value. We can't create
7283 // such a node, so we just return a null return value in that case. In
7284 // that case, nothing will actually look at the value.
7285 if (ReturnValues.empty())
7286 return std::make_pair(SDValue(), CLI.Chain);
7288 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7289 CLI.DAG.getVTList(RetTys),
7290 &ReturnValues[0], ReturnValues.size());
7291 return std::make_pair(Res, CLI.Chain);
7294 void TargetLowering::LowerOperationWrapper(SDNode *N,
7295 SmallVectorImpl<SDValue> &Results,
7296 SelectionDAG &DAG) const {
7297 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7299 Results.push_back(Res);
7302 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7303 llvm_unreachable("LowerOperation not implemented for this target!");
7307 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7308 SDValue Op = getNonRegisterValue(V);
7309 assert((Op.getOpcode() != ISD::CopyFromReg ||
7310 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7311 "Copy from a reg to the same reg!");
7312 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7314 const TargetLowering *TLI = TM.getTargetLowering();
7315 RegsForValue RFV(V->getContext(), *TLI, Reg, V->getType());
7316 SDValue Chain = DAG.getEntryNode();
7317 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V);
7318 PendingExports.push_back(Chain);
7321 #include "llvm/CodeGen/SelectionDAGISel.h"
7323 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7324 /// entry block, return true. This includes arguments used by switches, since
7325 /// the switch may expand into multiple basic blocks.
7326 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7327 // With FastISel active, we may be splitting blocks, so force creation
7328 // of virtual registers for all non-dead arguments.
7330 return A->use_empty();
7332 const BasicBlock *Entry = A->getParent()->begin();
7333 for (const User *U : A->users())
7334 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U))
7335 return false; // Use not in entry block.
7340 void SelectionDAGISel::LowerArguments(const Function &F) {
7341 SelectionDAG &DAG = SDB->DAG;
7342 SDLoc dl = SDB->getCurSDLoc();
7343 const TargetLowering *TLI = getTargetLowering();
7344 const DataLayout *DL = TLI->getDataLayout();
7345 SmallVector<ISD::InputArg, 16> Ins;
7347 if (!FuncInfo->CanLowerReturn) {
7348 // Put in an sret pointer parameter before all the other parameters.
7349 SmallVector<EVT, 1> ValueVTs;
7350 ComputeValueVTs(*getTargetLowering(),
7351 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7353 // NOTE: Assuming that a pointer will never break down to more than one VT
7355 ISD::ArgFlagsTy Flags;
7357 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7358 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true, 0, 0);
7359 Ins.push_back(RetArg);
7362 // Set up the incoming argument description vector.
7364 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7365 I != E; ++I, ++Idx) {
7366 SmallVector<EVT, 4> ValueVTs;
7367 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7368 bool isArgValueUsed = !I->use_empty();
7369 unsigned PartBase = 0;
7370 for (unsigned Value = 0, NumValues = ValueVTs.size();
7371 Value != NumValues; ++Value) {
7372 EVT VT = ValueVTs[Value];
7373 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7374 ISD::ArgFlagsTy Flags;
7375 unsigned OriginalAlignment = DL->getABITypeAlignment(ArgTy);
7377 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7379 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7381 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7383 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7385 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7387 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7388 Flags.setInAlloca();
7389 // Set the byval flag for CCAssignFn callbacks that don't know about
7390 // inalloca. This way we can know how many bytes we should've allocated
7391 // and how many bytes a callee cleanup function will pop. If we port
7392 // inalloca to more targets, we'll have to add custom inalloca handling
7393 // in the various CC lowering callbacks.
7396 if (Flags.isByVal() || Flags.isInAlloca()) {
7397 PointerType *Ty = cast<PointerType>(I->getType());
7398 Type *ElementTy = Ty->getElementType();
7399 Flags.setByValSize(DL->getTypeAllocSize(ElementTy));
7400 // For ByVal, alignment should be passed from FE. BE will guess if
7401 // this info is not there but there are cases it cannot get right.
7402 unsigned FrameAlign;
7403 if (F.getParamAlignment(Idx))
7404 FrameAlign = F.getParamAlignment(Idx);
7406 FrameAlign = TLI->getByValTypeAlignment(ElementTy);
7407 Flags.setByValAlign(FrameAlign);
7409 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7411 Flags.setOrigAlign(OriginalAlignment);
7413 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7414 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7415 for (unsigned i = 0; i != NumRegs; ++i) {
7416 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7417 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7418 if (NumRegs > 1 && i == 0)
7419 MyFlags.Flags.setSplit();
7420 // if it isn't first piece, alignment must be 1
7422 MyFlags.Flags.setOrigAlign(1);
7423 Ins.push_back(MyFlags);
7425 PartBase += VT.getStoreSize();
7429 // Call the target to set up the argument values.
7430 SmallVector<SDValue, 8> InVals;
7431 SDValue NewRoot = TLI->LowerFormalArguments(DAG.getRoot(), F.getCallingConv(),
7435 // Verify that the target's LowerFormalArguments behaved as expected.
7436 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7437 "LowerFormalArguments didn't return a valid chain!");
7438 assert(InVals.size() == Ins.size() &&
7439 "LowerFormalArguments didn't emit the correct number of values!");
7441 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7442 assert(InVals[i].getNode() &&
7443 "LowerFormalArguments emitted a null value!");
7444 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7445 "LowerFormalArguments emitted a value with the wrong type!");
7449 // Update the DAG with the new chain value resulting from argument lowering.
7450 DAG.setRoot(NewRoot);
7452 // Set up the argument values.
7455 if (!FuncInfo->CanLowerReturn) {
7456 // Create a virtual register for the sret pointer, and put in a copy
7457 // from the sret argument into it.
7458 SmallVector<EVT, 1> ValueVTs;
7459 ComputeValueVTs(*TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs);
7460 MVT VT = ValueVTs[0].getSimpleVT();
7461 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7462 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7463 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7464 RegVT, VT, nullptr, AssertOp);
7466 MachineFunction& MF = SDB->DAG.getMachineFunction();
7467 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7468 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7469 FuncInfo->DemoteRegister = SRetReg;
7470 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(),
7472 DAG.setRoot(NewRoot);
7474 // i indexes lowered arguments. Bump it past the hidden sret argument.
7475 // Idx indexes LLVM arguments. Don't touch it.
7479 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7481 SmallVector<SDValue, 4> ArgValues;
7482 SmallVector<EVT, 4> ValueVTs;
7483 ComputeValueVTs(*TLI, I->getType(), ValueVTs);
7484 unsigned NumValues = ValueVTs.size();
7486 // If this argument is unused then remember its value. It is used to generate
7487 // debugging information.
7488 if (I->use_empty() && NumValues) {
7489 SDB->setUnusedArgValue(I, InVals[i]);
7491 // Also remember any frame index for use in FastISel.
7492 if (FrameIndexSDNode *FI =
7493 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7494 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7497 for (unsigned Val = 0; Val != NumValues; ++Val) {
7498 EVT VT = ValueVTs[Val];
7499 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7500 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7502 if (!I->use_empty()) {
7503 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7504 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7505 AssertOp = ISD::AssertSext;
7506 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7507 AssertOp = ISD::AssertZext;
7509 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7510 NumParts, PartVT, VT,
7511 nullptr, AssertOp));
7517 // We don't need to do anything else for unused arguments.
7518 if (ArgValues.empty())
7521 // Note down frame index.
7522 if (FrameIndexSDNode *FI =
7523 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7524 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7526 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues,
7527 SDB->getCurSDLoc());
7529 SDB->setValue(I, Res);
7530 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7531 if (LoadSDNode *LNode =
7532 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7533 if (FrameIndexSDNode *FI =
7534 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7535 FuncInfo->setArgumentFrameIndex(I, FI->getIndex());
7538 // If this argument is live outside of the entry block, insert a copy from
7539 // wherever we got it to the vreg that other BB's will reference it as.
7540 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7541 // If we can, though, try to skip creating an unnecessary vreg.
7542 // FIXME: This isn't very clean... it would be nice to make this more
7543 // general. It's also subtly incompatible with the hacks FastISel
7545 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7546 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7547 FuncInfo->ValueMap[I] = Reg;
7551 if (!isOnlyUsedInEntryBlock(I, TM.Options.EnableFastISel)) {
7552 FuncInfo->InitializeRegForValue(I);
7553 SDB->CopyToExportRegsIfNeeded(I);
7557 assert(i == InVals.size() && "Argument register count mismatch!");
7559 // Finally, if the target has anything special to do, allow it to do so.
7560 // FIXME: this should insert code into the DAG!
7561 EmitFunctionEntryCode();
7564 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7565 /// ensure constants are generated when needed. Remember the virtual registers
7566 /// that need to be added to the Machine PHI nodes as input. We cannot just
7567 /// directly add them, because expansion might result in multiple MBB's for one
7568 /// BB. As such, the start of the BB might correspond to a different MBB than
7572 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7573 const TerminatorInst *TI = LLVMBB->getTerminator();
7575 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7577 // Check successor nodes' PHI nodes that expect a constant to be available
7579 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7580 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7581 if (!isa<PHINode>(SuccBB->begin())) continue;
7582 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7584 // If this terminator has multiple identical successors (common for
7585 // switches), only handle each succ once.
7586 if (!SuccsHandled.insert(SuccMBB)) continue;
7588 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7590 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7591 // nodes and Machine PHI nodes, but the incoming operands have not been
7593 for (BasicBlock::const_iterator I = SuccBB->begin();
7594 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7595 // Ignore dead phi's.
7596 if (PN->use_empty()) continue;
7599 if (PN->getType()->isEmptyTy())
7603 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7605 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7606 unsigned &RegOut = ConstantsOut[C];
7608 RegOut = FuncInfo.CreateRegs(C->getType());
7609 CopyValueToVirtualRegister(C, RegOut);
7613 DenseMap<const Value *, unsigned>::iterator I =
7614 FuncInfo.ValueMap.find(PHIOp);
7615 if (I != FuncInfo.ValueMap.end())
7618 assert(isa<AllocaInst>(PHIOp) &&
7619 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7620 "Didn't codegen value into a register!??");
7621 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7622 CopyValueToVirtualRegister(PHIOp, Reg);
7626 // Remember that this register needs to added to the machine PHI node as
7627 // the input for this MBB.
7628 SmallVector<EVT, 4> ValueVTs;
7629 const TargetLowering *TLI = TM.getTargetLowering();
7630 ComputeValueVTs(*TLI, PN->getType(), ValueVTs);
7631 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7632 EVT VT = ValueVTs[vti];
7633 unsigned NumRegisters = TLI->getNumRegisters(*DAG.getContext(), VT);
7634 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7635 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7636 Reg += NumRegisters;
7641 ConstantsOut.clear();
7644 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7647 SelectionDAGBuilder::StackProtectorDescriptor::
7648 AddSuccessorMBB(const BasicBlock *BB,
7649 MachineBasicBlock *ParentMBB,
7650 MachineBasicBlock *SuccMBB) {
7651 // If SuccBB has not been created yet, create it.
7653 MachineFunction *MF = ParentMBB->getParent();
7654 MachineFunction::iterator BBI = ParentMBB;
7655 SuccMBB = MF->CreateMachineBasicBlock(BB);
7656 MF->insert(++BBI, SuccMBB);
7658 // Add it as a successor of ParentMBB.
7659 ParentMBB->addSuccessor(SuccMBB);