1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating from LLVM IR into SelectionDAG IR.
12 //===----------------------------------------------------------------------===//
14 #include "SelectionDAGBuilder.h"
15 #include "SDNodeDbgValue.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/Optional.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/ADT/Statistic.h"
20 #include "llvm/Analysis/AliasAnalysis.h"
21 #include "llvm/Analysis/BranchProbabilityInfo.h"
22 #include "llvm/Analysis/ConstantFolding.h"
23 #include "llvm/Analysis/TargetLibraryInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/Analysis/VectorUtils.h"
26 #include "llvm/CodeGen/FastISel.h"
27 #include "llvm/CodeGen/FunctionLoweringInfo.h"
28 #include "llvm/CodeGen/GCMetadata.h"
29 #include "llvm/CodeGen/GCStrategy.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/CodeGen/StackMaps.h"
38 #include "llvm/CodeGen/WinEHFuncInfo.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DataLayout.h"
42 #include "llvm/IR/DebugInfo.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalVariable.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Module.h"
52 #include "llvm/IR/Statepoint.h"
53 #include "llvm/MC/MCSymbol.h"
54 #include "llvm/Support/CommandLine.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/MathExtras.h"
58 #include "llvm/Support/raw_ostream.h"
59 #include "llvm/Target/TargetFrameLowering.h"
60 #include "llvm/Target/TargetInstrInfo.h"
61 #include "llvm/Target/TargetIntrinsicInfo.h"
62 #include "llvm/Target/TargetLowering.h"
63 #include "llvm/Target/TargetOptions.h"
64 #include "llvm/Target/TargetSelectionDAGInfo.h"
65 #include "llvm/Target/TargetSubtargetInfo.h"
70 #define DEBUG_TYPE "isel"
72 /// LimitFloatPrecision - Generate low-precision inline sequences for
73 /// some float libcalls (6, 8 or 12 bits).
74 static unsigned LimitFloatPrecision;
76 static cl::opt<unsigned, true>
77 LimitFPPrecision("limit-float-precision",
78 cl::desc("Generate low-precision inline sequences "
79 "for some float libcalls"),
80 cl::location(LimitFloatPrecision),
84 EnableFMFInDAG("enable-fmf-dag", cl::init(true), cl::Hidden,
85 cl::desc("Enable fast-math-flags for DAG nodes"));
87 // Limit the width of DAG chains. This is important in general to prevent
88 // DAG-based analysis from blowing up. For example, alias analysis and
89 // load clustering may not complete in reasonable time. It is difficult to
90 // recognize and avoid this situation within each individual analysis, and
91 // future analyses are likely to have the same behavior. Limiting DAG width is
92 // the safe approach and will be especially important with global DAGs.
94 // MaxParallelChains default is arbitrarily high to avoid affecting
95 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st
96 // sequence over this should have been converted to llvm.memcpy by the
97 // frontend. It easy to induce this behavior with .ll code such as:
98 // %buffer = alloca [4096 x i8]
99 // %data = load [4096 x i8]* %argPtr
100 // store [4096 x i8] %data, [4096 x i8]* %buffer
101 static const unsigned MaxParallelChains = 64;
103 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
104 const SDValue *Parts, unsigned NumParts,
105 MVT PartVT, EVT ValueVT, const Value *V);
107 /// getCopyFromParts - Create a value that contains the specified legal parts
108 /// combined into the value they represent. If the parts combine to a type
109 /// larger then ValueVT then AssertOp can be used to specify whether the extra
110 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
111 /// (ISD::AssertSext).
112 static SDValue getCopyFromParts(SelectionDAG &DAG, SDLoc DL,
113 const SDValue *Parts,
114 unsigned NumParts, MVT PartVT, EVT ValueVT,
116 ISD::NodeType AssertOp = ISD::DELETED_NODE) {
117 if (ValueVT.isVector())
118 return getCopyFromPartsVector(DAG, DL, Parts, NumParts,
121 assert(NumParts > 0 && "No parts to assemble!");
122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
123 SDValue Val = Parts[0];
126 // Assemble the value from multiple parts.
127 if (ValueVT.isInteger()) {
128 unsigned PartBits = PartVT.getSizeInBits();
129 unsigned ValueBits = ValueVT.getSizeInBits();
131 // Assemble the power of 2 part.
132 unsigned RoundParts = NumParts & (NumParts - 1) ?
133 1 << Log2_32(NumParts) : NumParts;
134 unsigned RoundBits = PartBits * RoundParts;
135 EVT RoundVT = RoundBits == ValueBits ?
136 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
139 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2);
141 if (RoundParts > 2) {
142 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2,
144 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2,
145 RoundParts / 2, PartVT, HalfVT, V);
147 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]);
148 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]);
151 if (DAG.getDataLayout().isBigEndian())
154 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi);
156 if (RoundParts < NumParts) {
157 // Assemble the trailing non-power-of-2 part.
158 unsigned OddParts = NumParts - RoundParts;
159 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits);
160 Hi = getCopyFromParts(DAG, DL,
161 Parts + RoundParts, OddParts, PartVT, OddVT, V);
163 // Combine the round and odd parts.
165 if (DAG.getDataLayout().isBigEndian())
167 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
168 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi);
170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi,
171 DAG.getConstant(Lo.getValueType().getSizeInBits(), DL,
172 TLI.getPointerTy(DAG.getDataLayout())));
173 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo);
174 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi);
176 } else if (PartVT.isFloatingPoint()) {
177 // FP split into multiple FP parts (for ppcf128)
178 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
181 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]);
182 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]);
183 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout()))
185 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi);
187 // FP split into integer parts (soft fp)
188 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
189 !PartVT.isVector() && "Unexpected split");
190 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
191 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V);
195 // There is now one part, held in Val. Correct it to match ValueVT.
196 EVT PartEVT = Val.getValueType();
198 if (PartEVT == ValueVT)
201 if (PartEVT.isInteger() && ValueVT.isFloatingPoint() &&
202 ValueVT.bitsLT(PartEVT)) {
203 // For an FP value in an integer part, we need to truncate to the right
205 PartEVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
206 Val = DAG.getNode(ISD::TRUNCATE, DL, PartEVT, Val);
209 if (PartEVT.isInteger() && ValueVT.isInteger()) {
210 if (ValueVT.bitsLT(PartEVT)) {
211 // For a truncate, see if we have any information to
212 // indicate whether the truncated bits will always be
213 // zero or sign-extension.
214 if (AssertOp != ISD::DELETED_NODE)
215 Val = DAG.getNode(AssertOp, DL, PartEVT, Val,
216 DAG.getValueType(ValueVT));
217 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
219 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val);
222 if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
223 // FP_ROUND's are always exact here.
224 if (ValueVT.bitsLT(Val.getValueType()))
226 ISD::FP_ROUND, DL, ValueVT, Val,
227 DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
229 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
232 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits())
233 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
235 llvm_unreachable("Unknown mismatch!");
238 static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V,
239 const Twine &ErrMsg) {
240 const Instruction *I = dyn_cast_or_null<Instruction>(V);
242 return Ctx.emitError(ErrMsg);
244 const char *AsmError = ", possible invalid constraint for vector type";
245 if (const CallInst *CI = dyn_cast<CallInst>(I))
246 if (isa<InlineAsm>(CI->getCalledValue()))
247 return Ctx.emitError(I, ErrMsg + AsmError);
249 return Ctx.emitError(I, ErrMsg);
252 /// getCopyFromPartsVector - Create a value that contains the specified legal
253 /// parts combined into the value they represent. If the parts combine to a
254 /// type larger then ValueVT then AssertOp can be used to specify whether the
255 /// extra bits are known to be zero (ISD::AssertZext) or sign extended from
256 /// ValueVT (ISD::AssertSext).
257 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, SDLoc DL,
258 const SDValue *Parts, unsigned NumParts,
259 MVT PartVT, EVT ValueVT, const Value *V) {
260 assert(ValueVT.isVector() && "Not a vector value");
261 assert(NumParts > 0 && "No parts to assemble!");
262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
263 SDValue Val = Parts[0];
265 // Handle a multi-element vector.
269 unsigned NumIntermediates;
271 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT,
272 NumIntermediates, RegisterVT);
273 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
274 NumParts = NumRegs; // Silence a compiler warning.
275 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
276 assert(RegisterVT.getSizeInBits() ==
277 Parts[0].getSimpleValueType().getSizeInBits() &&
278 "Part type sizes don't match!");
280 // Assemble the parts into intermediate operands.
281 SmallVector<SDValue, 8> Ops(NumIntermediates);
282 if (NumIntermediates == NumParts) {
283 // If the register was not expanded, truncate or copy the value,
285 for (unsigned i = 0; i != NumParts; ++i)
286 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1,
287 PartVT, IntermediateVT, V);
288 } else if (NumParts > 0) {
289 // If the intermediate type was expanded, build the intermediate
290 // operands from the parts.
291 assert(NumParts % NumIntermediates == 0 &&
292 "Must expand into a divisible number of parts!");
293 unsigned Factor = NumParts / NumIntermediates;
294 for (unsigned i = 0; i != NumIntermediates; ++i)
295 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor,
296 PartVT, IntermediateVT, V);
299 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the
300 // intermediate operands.
301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS
306 // There is now one part, held in Val. Correct it to match ValueVT.
307 EVT PartEVT = Val.getValueType();
309 if (PartEVT == ValueVT)
312 if (PartEVT.isVector()) {
313 // If the element type of the source/dest vectors are the same, but the
314 // parts vector has more elements than the value vector, then we have a
315 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the
317 if (PartEVT.getVectorElementType() == ValueVT.getVectorElementType()) {
318 assert(PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements() &&
319 "Cannot narrow, it would be a lossy transformation");
321 ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val,
322 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
325 // Vector/Vector bitcast.
326 if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
327 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
329 assert(PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements() &&
330 "Cannot handle this kind of promotion");
331 // Promoted vector extract
332 return DAG.getAnyExtOrTrunc(Val, DL, ValueVT);
336 // Trivial bitcast if the types are the same size and the destination
337 // vector type is legal.
338 if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
339 TLI.isTypeLegal(ValueVT))
340 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
342 // Handle cases such as i8 -> <1 x i1>
343 if (ValueVT.getVectorNumElements() != 1) {
344 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
345 "non-trivial scalar-to-vector conversion");
346 return DAG.getUNDEF(ValueVT);
349 if (ValueVT.getVectorNumElements() == 1 &&
350 ValueVT.getVectorElementType() != PartEVT)
351 Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
353 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
356 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc dl,
357 SDValue Val, SDValue *Parts, unsigned NumParts,
358 MVT PartVT, const Value *V);
360 /// getCopyToParts - Create a series of nodes that contain the specified value
361 /// split into legal parts. If the parts contain more bits than Val, then, for
362 /// integers, ExtendKind can be used to specify how to generate the extra bits.
363 static void getCopyToParts(SelectionDAG &DAG, SDLoc DL,
364 SDValue Val, SDValue *Parts, unsigned NumParts,
365 MVT PartVT, const Value *V,
366 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
367 EVT ValueVT = Val.getValueType();
369 // Handle the vector case separately.
370 if (ValueVT.isVector())
371 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT, V);
373 unsigned PartBits = PartVT.getSizeInBits();
374 unsigned OrigNumParts = NumParts;
375 assert(DAG.getTargetLoweringInfo().isTypeLegal(PartVT) &&
376 "Copying to an illegal type!");
381 assert(!ValueVT.isVector() && "Vector case handled elsewhere");
382 EVT PartEVT = PartVT;
383 if (PartEVT == ValueVT) {
384 assert(NumParts == 1 && "No-op copy with multiple parts!");
389 if (NumParts * PartBits > ValueVT.getSizeInBits()) {
390 // If the parts cover more bits than the value has, promote the value.
391 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
392 assert(NumParts == 1 && "Do not know what to promote to!");
393 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val);
395 if (ValueVT.isFloatingPoint()) {
396 // FP values need to be bitcast, then extended if they are being put
397 // into a larger container.
398 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits());
399 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
401 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
402 ValueVT.isInteger() &&
403 "Unknown mismatch!");
404 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
405 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val);
406 if (PartVT == MVT::x86mmx)
407 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
409 } else if (PartBits == ValueVT.getSizeInBits()) {
410 // Different types of the same size.
411 assert(NumParts == 1 && PartEVT != ValueVT);
412 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
413 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
414 // If the parts cover less bits than value has, truncate the value.
415 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) &&
416 ValueVT.isInteger() &&
417 "Unknown mismatch!");
418 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
419 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
420 if (PartVT == MVT::x86mmx)
421 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
424 // The value may have changed - recompute ValueVT.
425 ValueVT = Val.getValueType();
426 assert(NumParts * PartBits == ValueVT.getSizeInBits() &&
427 "Failed to tile the value with PartVT!");
430 if (PartEVT != ValueVT)
431 diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
432 "scalar-to-vector conversion failed");
438 // Expand the value into multiple parts.
439 if (NumParts & (NumParts - 1)) {
440 // The number of parts is not a power of 2. Split off and copy the tail.
441 assert(PartVT.isInteger() && ValueVT.isInteger() &&
442 "Do not know what to expand to!");
443 unsigned RoundParts = 1 << Log2_32(NumParts);
444 unsigned RoundBits = RoundParts * PartBits;
445 unsigned OddParts = NumParts - RoundParts;
446 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
447 DAG.getIntPtrConstant(RoundBits, DL));
448 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V);
450 if (DAG.getDataLayout().isBigEndian())
451 // The odd parts were reversed by getCopyToParts - unreverse them.
452 std::reverse(Parts + RoundParts, Parts + NumParts);
454 NumParts = RoundParts;
455 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits);
456 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val);
459 // The number of parts is a power of 2. Repeatedly bisect the value using
461 Parts[0] = DAG.getNode(ISD::BITCAST, DL,
462 EVT::getIntegerVT(*DAG.getContext(),
463 ValueVT.getSizeInBits()),
466 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
467 for (unsigned i = 0; i < NumParts; i += StepSize) {
468 unsigned ThisBits = StepSize * PartBits / 2;
469 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits);
470 SDValue &Part0 = Parts[i];
471 SDValue &Part1 = Parts[i+StepSize/2];
473 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
474 ThisVT, Part0, DAG.getIntPtrConstant(1, DL));
475 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL,
476 ThisVT, Part0, DAG.getIntPtrConstant(0, DL));
478 if (ThisBits == PartBits && ThisVT != PartVT) {
479 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0);
480 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1);
485 if (DAG.getDataLayout().isBigEndian())
486 std::reverse(Parts, Parts + OrigNumParts);
490 /// getCopyToPartsVector - Create a series of nodes that contain the specified
491 /// value split into legal parts.
492 static void getCopyToPartsVector(SelectionDAG &DAG, SDLoc DL,
493 SDValue Val, SDValue *Parts, unsigned NumParts,
494 MVT PartVT, const Value *V) {
495 EVT ValueVT = Val.getValueType();
496 assert(ValueVT.isVector() && "Not a vector");
497 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
500 EVT PartEVT = PartVT;
501 if (PartEVT == ValueVT) {
503 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) {
504 // Bitconvert vector->vector case.
505 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
506 } else if (PartVT.isVector() &&
507 PartEVT.getVectorElementType() == ValueVT.getVectorElementType() &&
508 PartEVT.getVectorNumElements() > ValueVT.getVectorNumElements()) {
509 EVT ElementVT = PartVT.getVectorElementType();
510 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in
512 SmallVector<SDValue, 16> Ops;
513 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i)
514 Ops.push_back(DAG.getNode(
515 ISD::EXTRACT_VECTOR_ELT, DL, ElementVT, Val,
516 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout()))));
518 for (unsigned i = ValueVT.getVectorNumElements(),
519 e = PartVT.getVectorNumElements(); i != e; ++i)
520 Ops.push_back(DAG.getUNDEF(ElementVT));
522 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, Ops);
524 // FIXME: Use CONCAT for 2x -> 4x.
526 //SDValue UndefElts = DAG.getUNDEF(VectorTy);
527 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts);
528 } else if (PartVT.isVector() &&
529 PartEVT.getVectorElementType().bitsGE(
530 ValueVT.getVectorElementType()) &&
531 PartEVT.getVectorNumElements() == ValueVT.getVectorNumElements()) {
533 // Promoted vector extract
534 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
536 // Vector -> scalar conversion.
537 assert(ValueVT.getVectorNumElements() == 1 &&
538 "Only trivial vector-to-scalar conversions should get here!");
540 ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
541 DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
543 Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
550 // Handle a multi-element vector.
553 unsigned NumIntermediates;
554 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT,
556 NumIntermediates, RegisterVT);
557 unsigned NumElements = ValueVT.getVectorNumElements();
559 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!");
560 NumParts = NumRegs; // Silence a compiler warning.
561 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
563 // Split the vector into intermediate operands.
564 SmallVector<SDValue, 8> Ops(NumIntermediates);
565 for (unsigned i = 0; i != NumIntermediates; ++i) {
566 if (IntermediateVT.isVector())
568 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val,
569 DAG.getConstant(i * (NumElements / NumIntermediates), DL,
570 TLI.getVectorIdxTy(DAG.getDataLayout())));
572 Ops[i] = DAG.getNode(
573 ISD::EXTRACT_VECTOR_ELT, DL, IntermediateVT, Val,
574 DAG.getConstant(i, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
577 // Split the intermediate operands into legal parts.
578 if (NumParts == NumIntermediates) {
579 // If the register was not expanded, promote or copy the value,
581 for (unsigned i = 0; i != NumParts; ++i)
582 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT, V);
583 } else if (NumParts > 0) {
584 // If the intermediate type was expanded, split each the value into
586 assert(NumIntermediates != 0 && "division by zero");
587 assert(NumParts % NumIntermediates == 0 &&
588 "Must expand into a divisible number of parts!");
589 unsigned Factor = NumParts / NumIntermediates;
590 for (unsigned i = 0; i != NumIntermediates; ++i)
591 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT, V);
595 RegsForValue::RegsForValue() {}
597 RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
599 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
601 RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
602 const DataLayout &DL, unsigned Reg, Type *Ty) {
603 ComputeValueVTs(TLI, DL, Ty, ValueVTs);
605 for (EVT ValueVT : ValueVTs) {
606 unsigned NumRegs = TLI.getNumRegisters(Context, ValueVT);
607 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
608 for (unsigned i = 0; i != NumRegs; ++i)
609 Regs.push_back(Reg + i);
610 RegVTs.push_back(RegisterVT);
615 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from
616 /// this value and returns the result as a ValueVT value. This uses
617 /// Chain/Flag as the input and updates them for the output Chain/Flag.
618 /// If the Flag pointer is NULL, no flag is used.
619 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
620 FunctionLoweringInfo &FuncInfo,
622 SDValue &Chain, SDValue *Flag,
623 const Value *V) const {
624 // A Value with type {} or [0 x %t] needs no registers.
625 if (ValueVTs.empty())
628 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
630 // Assemble the legal parts into the final values.
631 SmallVector<SDValue, 4> Values(ValueVTs.size());
632 SmallVector<SDValue, 8> Parts;
633 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
634 // Copy the legal parts from the registers.
635 EVT ValueVT = ValueVTs[Value];
636 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
637 MVT RegisterVT = RegVTs[Value];
639 Parts.resize(NumRegs);
640 for (unsigned i = 0; i != NumRegs; ++i) {
643 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
645 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
646 *Flag = P.getValue(2);
649 Chain = P.getValue(1);
652 // If the source register was virtual and if we know something about it,
653 // add an assert node.
654 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
655 !RegisterVT.isInteger() || RegisterVT.isVector())
658 const FunctionLoweringInfo::LiveOutInfo *LOI =
659 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]);
663 unsigned RegSize = RegisterVT.getSizeInBits();
664 unsigned NumSignBits = LOI->NumSignBits;
665 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes();
667 if (NumZeroBits == RegSize) {
668 // The current value is a zero.
669 // Explicitly express that as it would be easier for
670 // optimizations to kick in.
671 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
675 // FIXME: We capture more information than the dag can represent. For
676 // now, just use the tightest assertzext/assertsext possible.
678 EVT FromVT(MVT::Other);
679 if (NumSignBits == RegSize)
680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
681 else if (NumZeroBits >= RegSize-1)
682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
683 else if (NumSignBits > RegSize-8)
684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
685 else if (NumZeroBits >= RegSize-8)
686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
687 else if (NumSignBits > RegSize-16)
688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
689 else if (NumZeroBits >= RegSize-16)
690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
691 else if (NumSignBits > RegSize-32)
692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
693 else if (NumZeroBits >= RegSize-32)
694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
698 // Add an assertion node.
699 assert(FromVT != MVT::Other);
700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
701 RegisterVT, P, DAG.getValueType(FromVT));
704 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
705 NumRegs, RegisterVT, ValueVT, V);
710 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
713 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the
714 /// specified value into the registers specified by this object. This uses
715 /// Chain/Flag as the input and updates them for the output Chain/Flag.
716 /// If the Flag pointer is NULL, no flag is used.
717 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, SDLoc dl,
718 SDValue &Chain, SDValue *Flag, const Value *V,
719 ISD::NodeType PreferredExtendType) const {
720 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
721 ISD::NodeType ExtendKind = PreferredExtendType;
723 // Get the list of the values's legal parts.
724 unsigned NumRegs = Regs.size();
725 SmallVector<SDValue, 8> Parts(NumRegs);
726 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
727 EVT ValueVT = ValueVTs[Value];
728 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT);
729 MVT RegisterVT = RegVTs[Value];
731 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
732 ExtendKind = ISD::ZERO_EXTEND;
734 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
735 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
739 // Copy the parts into the registers.
740 SmallVector<SDValue, 8> Chains(NumRegs);
741 for (unsigned i = 0; i != NumRegs; ++i) {
744 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]);
746 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag);
747 *Flag = Part.getValue(1);
750 Chains[i] = Part.getValue(0);
753 if (NumRegs == 1 || Flag)
754 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is
755 // flagged to it. That is the CopyToReg nodes and the user are considered
756 // a single scheduling unit. If we create a TokenFactor and return it as
757 // chain, then the TokenFactor is both a predecessor (operand) of the
758 // user as well as a successor (the TF operands are flagged to the user).
759 // c1, f1 = CopyToReg
760 // c2, f2 = CopyToReg
761 // c3 = TokenFactor c1, c2
764 Chain = Chains[NumRegs-1];
766 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
769 /// AddInlineAsmOperands - Add this value to the specified inlineasm node
770 /// operand list. This adds the code marker and includes the number of
771 /// values added into it.
772 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,
773 unsigned MatchingIdx, SDLoc dl,
775 std::vector<SDValue> &Ops) const {
776 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
778 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size());
780 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx);
781 else if (!Regs.empty() &&
782 TargetRegisterInfo::isVirtualRegister(Regs.front())) {
783 // Put the register class of the virtual registers in the flag word. That
784 // way, later passes can recompute register class constraints for inline
785 // assembly as well as normal instructions.
786 // Don't do this for tied operands that can use the regclass information
788 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
790 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID());
793 SDValue Res = DAG.getTargetConstant(Flag, dl, MVT::i32);
796 unsigned SP = TLI.getStackPointerRegisterToSaveRestore();
797 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
798 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]);
799 MVT RegisterVT = RegVTs[Value];
800 for (unsigned i = 0; i != NumRegs; ++i) {
801 assert(Reg < Regs.size() && "Mismatch in # registers expected");
802 unsigned TheReg = Regs[Reg++];
803 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
805 if (TheReg == SP && Code == InlineAsm::Kind_Clobber) {
806 // If we clobbered the stack pointer, MFI should know about it.
807 assert(DAG.getMachineFunction().getFrameInfo()->
808 hasOpaqueSPAdjustment());
814 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa,
815 const TargetLibraryInfo *li) {
819 DL = &DAG.getDataLayout();
820 Context = DAG.getContext();
821 LPadToCallSiteMap.clear();
824 /// clear - Clear out the current SelectionDAG and the associated
825 /// state and prepare this SelectionDAGBuilder object to be used
826 /// for a new block. This doesn't clear out information about
827 /// additional blocks that are needed to complete switch lowering
828 /// or PHI node updating; that information is cleared out as it is
830 void SelectionDAGBuilder::clear() {
832 UnusedArgNodeMap.clear();
833 PendingLoads.clear();
834 PendingExports.clear();
837 SDNodeOrder = LowestSDNodeOrder;
838 StatepointLowering.clear();
841 /// clearDanglingDebugInfo - Clear the dangling debug information
842 /// map. This function is separated from the clear so that debug
843 /// information that is dangling in a basic block can be properly
844 /// resolved in a different basic block. This allows the
845 /// SelectionDAG to resolve dangling debug information attached
847 void SelectionDAGBuilder::clearDanglingDebugInfo() {
848 DanglingDebugInfoMap.clear();
851 /// getRoot - Return the current virtual root of the Selection DAG,
852 /// flushing any PendingLoad items. This must be done before emitting
853 /// a store or any other node that may need to be ordered after any
854 /// prior load instructions.
856 SDValue SelectionDAGBuilder::getRoot() {
857 if (PendingLoads.empty())
858 return DAG.getRoot();
860 if (PendingLoads.size() == 1) {
861 SDValue Root = PendingLoads[0];
863 PendingLoads.clear();
867 // Otherwise, we have to make a token factor node.
868 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
870 PendingLoads.clear();
875 /// getControlRoot - Similar to getRoot, but instead of flushing all the
876 /// PendingLoad items, flush all the PendingExports items. It is necessary
877 /// to do this before emitting a terminator instruction.
879 SDValue SelectionDAGBuilder::getControlRoot() {
880 SDValue Root = DAG.getRoot();
882 if (PendingExports.empty())
885 // Turn all of the CopyToReg chains into one factored node.
886 if (Root.getOpcode() != ISD::EntryToken) {
887 unsigned i = 0, e = PendingExports.size();
888 for (; i != e; ++i) {
889 assert(PendingExports[i].getNode()->getNumOperands() > 1);
890 if (PendingExports[i].getNode()->getOperand(0) == Root)
891 break; // Don't add the root if we already indirectly depend on it.
895 PendingExports.push_back(Root);
898 Root = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other,
900 PendingExports.clear();
905 void SelectionDAGBuilder::visit(const Instruction &I) {
906 // Set up outgoing PHI node register values before emitting the terminator.
907 if (isa<TerminatorInst>(&I))
908 HandlePHINodesInSuccessorBlocks(I.getParent());
914 visit(I.getOpcode(), I);
916 if (!isa<TerminatorInst>(&I) && !HasTailCall &&
917 !isStatepoint(&I)) // statepoints handle their exports internally
918 CopyToExportRegsIfNeeded(&I);
923 void SelectionDAGBuilder::visitPHI(const PHINode &) {
924 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!");
927 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
928 // Note: this doesn't use InstVisitor, because it has to work with
929 // ConstantExpr's in addition to instructions.
931 default: llvm_unreachable("Unknown instruction type encountered!");
932 // Build the switch statement using the Instruction.def file.
933 #define HANDLE_INST(NUM, OPCODE, CLASS) \
934 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
935 #include "llvm/IR/Instruction.def"
939 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
940 // generate the debug data structures now that we've seen its definition.
941 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V,
943 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V];
945 const DbgValueInst *DI = DDI.getDI();
946 DebugLoc dl = DDI.getdl();
947 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
948 DILocalVariable *Variable = DI->getVariable();
949 DIExpression *Expr = DI->getExpression();
950 assert(Variable->isValidLocationForIntrinsic(dl) &&
951 "Expected inlined-at fields to agree");
952 uint64_t Offset = DI->getOffset();
953 // A dbg.value for an alloca is always indirect.
954 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
957 if (!EmitFuncArgumentDbgValue(V, Variable, Expr, dl, Offset, IsIndirect,
959 SDV = DAG.getDbgValue(Variable, Expr, Val.getNode(), Val.getResNo(),
960 IsIndirect, Offset, dl, DbgSDNodeOrder);
961 DAG.AddDbgValue(SDV, Val.getNode(), false);
964 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
965 DanglingDebugInfoMap[V] = DanglingDebugInfo();
969 /// getCopyFromRegs - If there was virtual register allocated for the value V
970 /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.
971 SDValue SelectionDAGBuilder::getCopyFromRegs(const Value *V, Type *Ty) {
972 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V);
975 if (It != FuncInfo.ValueMap.end()) {
976 unsigned InReg = It->second;
977 RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
978 DAG.getDataLayout(), InReg, Ty);
979 SDValue Chain = DAG.getEntryNode();
980 Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
981 resolveDanglingDebugInfo(V, Result);
987 /// getValue - Return an SDValue for the given Value.
988 SDValue SelectionDAGBuilder::getValue(const Value *V) {
989 // If we already have an SDValue for this value, use it. It's important
990 // to do this first, so that we don't create a CopyFromReg if we already
991 // have a regular SDValue.
992 SDValue &N = NodeMap[V];
993 if (N.getNode()) return N;
995 // If there's a virtual register allocated and initialized for this
997 SDValue copyFromReg = getCopyFromRegs(V, V->getType());
998 if (copyFromReg.getNode()) {
1002 // Otherwise create a new SDValue and remember it.
1003 SDValue Val = getValueImpl(V);
1005 resolveDanglingDebugInfo(V, Val);
1009 // Return true if SDValue exists for the given Value
1010 bool SelectionDAGBuilder::findValue(const Value *V) const {
1011 return (NodeMap.find(V) != NodeMap.end()) ||
1012 (FuncInfo.ValueMap.find(V) != FuncInfo.ValueMap.end());
1015 /// getNonRegisterValue - Return an SDValue for the given Value, but
1016 /// don't look in FuncInfo.ValueMap for a virtual register.
1017 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) {
1018 // If we already have an SDValue for this value, use it.
1019 SDValue &N = NodeMap[V];
1021 if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
1022 // Remove the debug location from the node as the node is about to be used
1023 // in a location which may differ from the original debug location. This
1024 // is relevant to Constant and ConstantFP nodes because they can appear
1025 // as constant expressions inside PHI nodes.
1026 N->setDebugLoc(DebugLoc());
1031 // Otherwise create a new SDValue and remember it.
1032 SDValue Val = getValueImpl(V);
1034 resolveDanglingDebugInfo(V, Val);
1038 /// getValueImpl - Helper function for getValue and getNonRegisterValue.
1039 /// Create an SDValue for the given value.
1040 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
1041 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1043 if (const Constant *C = dyn_cast<Constant>(V)) {
1044 EVT VT = TLI.getValueType(DAG.getDataLayout(), V->getType(), true);
1046 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C))
1047 return DAG.getConstant(*CI, getCurSDLoc(), VT);
1049 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
1050 return DAG.getGlobalAddress(GV, getCurSDLoc(), VT);
1052 if (isa<ConstantPointerNull>(C)) {
1053 unsigned AS = V->getType()->getPointerAddressSpace();
1054 return DAG.getConstant(0, getCurSDLoc(),
1055 TLI.getPointerTy(DAG.getDataLayout(), AS));
1058 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
1059 return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
1061 if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
1062 return DAG.getUNDEF(VT);
1064 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
1065 visit(CE->getOpcode(), *CE);
1066 SDValue N1 = NodeMap[V];
1067 assert(N1.getNode() && "visit didn't populate the NodeMap!");
1071 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) {
1072 SmallVector<SDValue, 4> Constants;
1073 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end();
1075 SDNode *Val = getValue(*OI).getNode();
1076 // If the operand is an empty aggregate, there are no values.
1078 // Add each leaf value from the operand to the Constants list
1079 // to form a flattened list of all the values.
1080 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1081 Constants.push_back(SDValue(Val, i));
1084 return DAG.getMergeValues(Constants, getCurSDLoc());
1087 if (const ConstantDataSequential *CDS =
1088 dyn_cast<ConstantDataSequential>(C)) {
1089 SmallVector<SDValue, 4> Ops;
1090 for (unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1091 SDNode *Val = getValue(CDS->getElementAsConstant(i)).getNode();
1092 // Add each leaf value from the operand to the Constants list
1093 // to form a flattened list of all the values.
1094 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i)
1095 Ops.push_back(SDValue(Val, i));
1098 if (isa<ArrayType>(CDS->getType()))
1099 return DAG.getMergeValues(Ops, getCurSDLoc());
1100 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(),
1104 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) {
1105 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
1106 "Unknown struct or array constant!");
1108 SmallVector<EVT, 4> ValueVTs;
1109 ComputeValueVTs(TLI, DAG.getDataLayout(), C->getType(), ValueVTs);
1110 unsigned NumElts = ValueVTs.size();
1112 return SDValue(); // empty struct
1113 SmallVector<SDValue, 4> Constants(NumElts);
1114 for (unsigned i = 0; i != NumElts; ++i) {
1115 EVT EltVT = ValueVTs[i];
1116 if (isa<UndefValue>(C))
1117 Constants[i] = DAG.getUNDEF(EltVT);
1118 else if (EltVT.isFloatingPoint())
1119 Constants[i] = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1121 Constants[i] = DAG.getConstant(0, getCurSDLoc(), EltVT);
1124 return DAG.getMergeValues(Constants, getCurSDLoc());
1127 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C))
1128 return DAG.getBlockAddress(BA, VT);
1130 VectorType *VecTy = cast<VectorType>(V->getType());
1131 unsigned NumElements = VecTy->getNumElements();
1133 // Now that we know the number and type of the elements, get that number of
1134 // elements into the Ops array based on what kind of constant it is.
1135 SmallVector<SDValue, 16> Ops;
1136 if (const ConstantVector *CV = dyn_cast<ConstantVector>(C)) {
1137 for (unsigned i = 0; i != NumElements; ++i)
1138 Ops.push_back(getValue(CV->getOperand(i)));
1140 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
1142 TLI.getValueType(DAG.getDataLayout(), VecTy->getElementType());
1145 if (EltVT.isFloatingPoint())
1146 Op = DAG.getConstantFP(0, getCurSDLoc(), EltVT);
1148 Op = DAG.getConstant(0, getCurSDLoc(), EltVT);
1149 Ops.assign(NumElements, Op);
1152 // Create a BUILD_VECTOR node.
1153 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurSDLoc(), VT, Ops);
1156 // If this is a static alloca, generate it as the frameindex instead of
1158 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1159 DenseMap<const AllocaInst*, int>::iterator SI =
1160 FuncInfo.StaticAllocaMap.find(AI);
1161 if (SI != FuncInfo.StaticAllocaMap.end())
1162 return DAG.getFrameIndex(SI->second,
1163 TLI.getPointerTy(DAG.getDataLayout()));
1166 // If this is an instruction which fast-isel has deferred, select it now.
1167 if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
1168 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
1169 RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
1171 SDValue Chain = DAG.getEntryNode();
1172 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
1175 llvm_unreachable("Can't get register for value!");
1178 void SelectionDAGBuilder::visitCatchPad(const CatchPadInst &I) {
1179 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1180 bool IsMSVCCXX = Pers == EHPersonality::MSVC_CXX;
1181 bool IsCoreCLR = Pers == EHPersonality::CoreCLR;
1182 MachineBasicBlock *CatchPadMBB = FuncInfo.MBB;
1183 // In MSVC C++ and CoreCLR, catchblocks are funclets and need prologues.
1184 if (IsMSVCCXX || IsCoreCLR)
1185 CatchPadMBB->setIsEHFuncletEntry();
1187 MachineBasicBlock *NormalDestMBB = FuncInfo.MBBMap[I.getNormalDest()];
1189 // Update machine-CFG edge.
1190 FuncInfo.MBB->addSuccessor(NormalDestMBB);
1193 DAG.getNode(ISD::CATCHPAD, getCurSDLoc(), MVT::Other, getControlRoot());
1195 // If this is not a fall-through branch or optimizations are switched off,
1197 if (NormalDestMBB != NextBlock(CatchPadMBB) ||
1198 TM.getOptLevel() == CodeGenOpt::None)
1199 Chain = DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other, Chain,
1200 DAG.getBasicBlock(NormalDestMBB));
1204 void SelectionDAGBuilder::visitCatchRet(const CatchReturnInst &I) {
1205 // Update machine-CFG edge.
1206 MachineBasicBlock *TargetMBB = FuncInfo.MBBMap[I.getSuccessor()];
1207 FuncInfo.MBB->addSuccessor(TargetMBB);
1209 auto Pers = classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1210 bool IsSEH = isAsynchronousEHPersonality(Pers);
1212 // If this is not a fall-through branch or optimizations are switched off,
1214 if (TargetMBB != NextBlock(FuncInfo.MBB) ||
1215 TM.getOptLevel() == CodeGenOpt::None)
1216 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
1217 getControlRoot(), DAG.getBasicBlock(TargetMBB)));
1221 // Figure out the funclet membership for the catchret's successor.
1222 // This will be used by the FuncletLayout pass to determine how to order the
1224 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
1225 const BasicBlock *SuccessorColor = EHInfo->CatchRetSuccessorColorMap[&I];
1226 assert(SuccessorColor && "No parent funclet for catchret!");
1227 MachineBasicBlock *SuccessorColorMBB = FuncInfo.MBBMap[SuccessorColor];
1228 assert(SuccessorColorMBB && "No MBB for SuccessorColor!");
1230 // Create the terminator node.
1231 SDValue Ret = DAG.getNode(ISD::CATCHRET, getCurSDLoc(), MVT::Other,
1232 getControlRoot(), DAG.getBasicBlock(TargetMBB),
1233 DAG.getBasicBlock(SuccessorColorMBB));
1237 void SelectionDAGBuilder::visitCatchEndPad(const CatchEndPadInst &I) {
1238 llvm_unreachable("should never codegen catchendpads");
1241 void SelectionDAGBuilder::visitCleanupPad(const CleanupPadInst &CPI) {
1242 // Don't emit any special code for the cleanuppad instruction. It just marks
1243 // the start of a funclet.
1244 FuncInfo.MBB->setIsEHFuncletEntry();
1245 FuncInfo.MBB->setIsCleanupFuncletEntry();
1248 /// When an invoke or a cleanupret unwinds to the next EH pad, there are
1249 /// many places it could ultimately go. In the IR, we have a single unwind
1250 /// destination, but in the machine CFG, we enumerate all the possible blocks.
1251 /// This function skips over imaginary basic blocks that hold catchpad,
1252 /// terminatepad, or catchendpad instructions, and finds all the "real" machine
1253 /// basic block destinations. As those destinations may not be successors of
1254 /// EHPadBB, here we also calculate the edge weight to those destinations. The
1255 /// passed-in Weight is the edge weight to EHPadBB.
1256 static void findUnwindDestinations(
1257 FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, uint32_t Weight,
1258 SmallVectorImpl<std::pair<MachineBasicBlock *, uint32_t>> &UnwindDests) {
1259 EHPersonality Personality =
1260 classifyEHPersonality(FuncInfo.Fn->getPersonalityFn());
1261 bool IsMSVCCXX = Personality == EHPersonality::MSVC_CXX;
1262 bool IsCoreCLR = Personality == EHPersonality::CoreCLR;
1265 const Instruction *Pad = EHPadBB->getFirstNonPHI();
1266 BasicBlock *NewEHPadBB = nullptr;
1267 if (isa<LandingPadInst>(Pad)) {
1268 // Stop on landingpads. They are not funclets.
1269 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1271 } else if (isa<CleanupPadInst>(Pad)) {
1272 // Stop on cleanup pads. Cleanups are always funclet entries for all known
1274 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1275 UnwindDests.back().first->setIsEHFuncletEntry();
1277 } else if (const auto *CPI = dyn_cast<CatchPadInst>(Pad)) {
1278 // Add the catchpad handler to the possible destinations.
1279 UnwindDests.emplace_back(FuncInfo.MBBMap[EHPadBB], Weight);
1280 // In MSVC C++, catchblocks are funclets and need prologues.
1281 if (IsMSVCCXX || IsCoreCLR)
1282 UnwindDests.back().first->setIsEHFuncletEntry();
1283 NewEHPadBB = CPI->getUnwindDest();
1284 } else if (const auto *CEPI = dyn_cast<CatchEndPadInst>(Pad))
1285 NewEHPadBB = CEPI->getUnwindDest();
1286 else if (const auto *CEPI = dyn_cast<CleanupEndPadInst>(Pad))
1287 NewEHPadBB = CEPI->getUnwindDest();
1291 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1292 if (BPI && NewEHPadBB) {
1293 // When BPI is available, the calculated weight cannot be zero as zero
1294 // will be turned to a default weight in MachineBlockFrequencyInfo.
1295 Weight = std::max<uint32_t>(
1296 BPI->getEdgeProbability(EHPadBB, NewEHPadBB).scale(Weight), 1);
1298 EHPadBB = NewEHPadBB;
1302 void SelectionDAGBuilder::visitCleanupRet(const CleanupReturnInst &I) {
1303 // Update successor info.
1304 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
1305 auto UnwindDest = I.getUnwindDest();
1306 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1307 uint32_t UnwindDestWeight =
1308 BPI ? BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(), UnwindDest) : 0;
1309 findUnwindDestinations(FuncInfo, UnwindDest, UnwindDestWeight, UnwindDests);
1310 for (auto &UnwindDest : UnwindDests) {
1311 UnwindDest.first->setIsEHPad();
1312 addSuccessorWithWeight(FuncInfo.MBB, UnwindDest.first, UnwindDest.second);
1315 // Create the terminator node.
1317 DAG.getNode(ISD::CLEANUPRET, getCurSDLoc(), MVT::Other, getControlRoot());
1321 void SelectionDAGBuilder::visitCleanupEndPad(const CleanupEndPadInst &I) {
1322 report_fatal_error("visitCleanupEndPad not yet implemented!");
1325 void SelectionDAGBuilder::visitTerminatePad(const TerminatePadInst &TPI) {
1326 report_fatal_error("visitTerminatePad not yet implemented!");
1329 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
1330 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1331 auto &DL = DAG.getDataLayout();
1332 SDValue Chain = getControlRoot();
1333 SmallVector<ISD::OutputArg, 8> Outs;
1334 SmallVector<SDValue, 8> OutVals;
1336 if (!FuncInfo.CanLowerReturn) {
1337 unsigned DemoteReg = FuncInfo.DemoteRegister;
1338 const Function *F = I.getParent()->getParent();
1340 // Emit a store of the return value through the virtual register.
1341 // Leave Outs empty so that LowerReturn won't try to load return
1342 // registers the usual way.
1343 SmallVector<EVT, 1> PtrValueVTs;
1344 ComputeValueVTs(TLI, DL, PointerType::getUnqual(F->getReturnType()),
1347 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]);
1348 SDValue RetOp = getValue(I.getOperand(0));
1350 SmallVector<EVT, 4> ValueVTs;
1351 SmallVector<uint64_t, 4> Offsets;
1352 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs, &Offsets);
1353 unsigned NumValues = ValueVTs.size();
1355 SmallVector<SDValue, 4> Chains(NumValues);
1356 for (unsigned i = 0; i != NumValues; ++i) {
1357 SDValue Add = DAG.getNode(ISD::ADD, getCurSDLoc(),
1358 RetPtr.getValueType(), RetPtr,
1359 DAG.getIntPtrConstant(Offsets[i],
1362 DAG.getStore(Chain, getCurSDLoc(),
1363 SDValue(RetOp.getNode(), RetOp.getResNo() + i),
1364 // FIXME: better loc info would be nice.
1365 Add, MachinePointerInfo(), false, false, 0);
1368 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
1369 MVT::Other, Chains);
1370 } else if (I.getNumOperands() != 0) {
1371 SmallVector<EVT, 4> ValueVTs;
1372 ComputeValueVTs(TLI, DL, I.getOperand(0)->getType(), ValueVTs);
1373 unsigned NumValues = ValueVTs.size();
1375 SDValue RetOp = getValue(I.getOperand(0));
1377 const Function *F = I.getParent()->getParent();
1379 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1380 if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1382 ExtendKind = ISD::SIGN_EXTEND;
1383 else if (F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1385 ExtendKind = ISD::ZERO_EXTEND;
1387 LLVMContext &Context = F->getContext();
1388 bool RetInReg = F->getAttributes().hasAttribute(AttributeSet::ReturnIndex,
1391 for (unsigned j = 0; j != NumValues; ++j) {
1392 EVT VT = ValueVTs[j];
1394 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger())
1395 VT = TLI.getTypeForExtArgOrReturn(Context, VT, ExtendKind);
1397 unsigned NumParts = TLI.getNumRegisters(Context, VT);
1398 MVT PartVT = TLI.getRegisterType(Context, VT);
1399 SmallVector<SDValue, 4> Parts(NumParts);
1400 getCopyToParts(DAG, getCurSDLoc(),
1401 SDValue(RetOp.getNode(), RetOp.getResNo() + j),
1402 &Parts[0], NumParts, PartVT, &I, ExtendKind);
1404 // 'inreg' on function refers to return value
1405 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1409 // Propagate extension type if any
1410 if (ExtendKind == ISD::SIGN_EXTEND)
1412 else if (ExtendKind == ISD::ZERO_EXTEND)
1415 for (unsigned i = 0; i < NumParts; ++i) {
1416 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(),
1417 VT, /*isfixed=*/true, 0, 0));
1418 OutVals.push_back(Parts[i]);
1424 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1425 CallingConv::ID CallConv =
1426 DAG.getMachineFunction().getFunction()->getCallingConv();
1427 Chain = DAG.getTargetLoweringInfo().LowerReturn(
1428 Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
1430 // Verify that the target's LowerReturn behaved as expected.
1431 assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
1432 "LowerReturn didn't return a valid chain!");
1434 // Update the DAG with the new chain value resulting from return lowering.
1438 /// CopyToExportRegsIfNeeded - If the given value has virtual registers
1439 /// created for it, emit nodes to copy the value into the virtual
1441 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) {
1443 if (V->getType()->isEmptyTy())
1446 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
1447 if (VMI != FuncInfo.ValueMap.end()) {
1448 assert(!V->use_empty() && "Unused value assigned virtual registers!");
1449 CopyValueToVirtualRegister(V, VMI->second);
1453 /// ExportFromCurrentBlock - If this condition isn't known to be exported from
1454 /// the current basic block, add it to ValueMap now so that we'll get a
1456 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) {
1457 // No need to export constants.
1458 if (!isa<Instruction>(V) && !isa<Argument>(V)) return;
1460 // Already exported?
1461 if (FuncInfo.isExportedInst(V)) return;
1463 unsigned Reg = FuncInfo.InitializeRegForValue(V);
1464 CopyValueToVirtualRegister(V, Reg);
1467 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V,
1468 const BasicBlock *FromBB) {
1469 // The operands of the setcc have to be in this block. We don't know
1470 // how to export them from some other block.
1471 if (const Instruction *VI = dyn_cast<Instruction>(V)) {
1472 // Can export from current BB.
1473 if (VI->getParent() == FromBB)
1476 // Is already exported, noop.
1477 return FuncInfo.isExportedInst(V);
1480 // If this is an argument, we can export it if the BB is the entry block or
1481 // if it is already exported.
1482 if (isa<Argument>(V)) {
1483 if (FromBB == &FromBB->getParent()->getEntryBlock())
1486 // Otherwise, can only export this if it is already exported.
1487 return FuncInfo.isExportedInst(V);
1490 // Otherwise, constants can always be exported.
1494 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks.
1495 uint32_t SelectionDAGBuilder::getEdgeWeight(const MachineBasicBlock *Src,
1496 const MachineBasicBlock *Dst) const {
1497 BranchProbabilityInfo *BPI = FuncInfo.BPI;
1500 const BasicBlock *SrcBB = Src->getBasicBlock();
1501 const BasicBlock *DstBB = Dst->getBasicBlock();
1502 return BPI->getEdgeWeight(SrcBB, DstBB);
1505 void SelectionDAGBuilder::
1506 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
1507 uint32_t Weight /* = 0 */) {
1509 Src->addSuccessorWithoutWeight(Dst);
1512 Weight = getEdgeWeight(Src, Dst);
1513 Src->addSuccessor(Dst, Weight);
1518 static bool InBlock(const Value *V, const BasicBlock *BB) {
1519 if (const Instruction *I = dyn_cast<Instruction>(V))
1520 return I->getParent() == BB;
1524 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
1525 /// This function emits a branch and is used at the leaves of an OR or an
1526 /// AND operator tree.
1529 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond,
1530 MachineBasicBlock *TBB,
1531 MachineBasicBlock *FBB,
1532 MachineBasicBlock *CurBB,
1533 MachineBasicBlock *SwitchBB,
1536 const BasicBlock *BB = CurBB->getBasicBlock();
1538 // If the leaf of the tree is a comparison, merge the condition into
1540 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) {
1541 // The operands of the cmp have to be in this block. We don't know
1542 // how to export them from some other block. If this is the first block
1543 // of the sequence, no exporting is needed.
1544 if (CurBB == SwitchBB ||
1545 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) &&
1546 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) {
1547 ISD::CondCode Condition;
1548 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) {
1549 Condition = getICmpCondCode(IC->getPredicate());
1551 const FCmpInst *FC = cast<FCmpInst>(Cond);
1552 Condition = getFCmpCondCode(FC->getPredicate());
1553 if (TM.Options.NoNaNsFPMath)
1554 Condition = getFCmpCodeWithoutNaN(Condition);
1557 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1), nullptr,
1558 TBB, FBB, CurBB, TWeight, FWeight);
1559 SwitchCases.push_back(CB);
1564 // Create a CaseBlock record representing this branch.
1565 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()),
1566 nullptr, TBB, FBB, CurBB, TWeight, FWeight);
1567 SwitchCases.push_back(CB);
1570 /// Scale down both weights to fit into uint32_t.
1571 static void ScaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
1572 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
1573 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
1574 NewTrue = NewTrue / Scale;
1575 NewFalse = NewFalse / Scale;
1578 /// FindMergedConditions - If Cond is an expression like
1579 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
1580 MachineBasicBlock *TBB,
1581 MachineBasicBlock *FBB,
1582 MachineBasicBlock *CurBB,
1583 MachineBasicBlock *SwitchBB,
1584 Instruction::BinaryOps Opc,
1587 // If this node is not part of the or/and tree, emit it as a branch.
1588 const Instruction *BOp = dyn_cast<Instruction>(Cond);
1589 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) ||
1590 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() ||
1591 BOp->getParent() != CurBB->getBasicBlock() ||
1592 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) ||
1593 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) {
1594 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB,
1599 // Create TmpBB after CurBB.
1600 MachineFunction::iterator BBI(CurBB);
1601 MachineFunction &MF = DAG.getMachineFunction();
1602 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock());
1603 CurBB->getParent()->insert(++BBI, TmpBB);
1605 if (Opc == Instruction::Or) {
1606 // Codegen X | Y as:
1615 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1616 // The requirement is that
1617 // TrueProb for BB1 + (FalseProb for BB1 * TrueProb for TmpBB)
1618 // = TrueProb for original BB.
1619 // Assuming the original weights are A and B, one choice is to set BB1's
1620 // weights to A and A+2B, and set TmpBB's weights to A and 2B. This choice
1622 // TrueProb for BB1 == FalseProb for BB1 * TrueProb for TmpBB.
1623 // Another choice is to assume TrueProb for BB1 equals to TrueProb for
1624 // TmpBB, but the math is more complicated.
1626 uint64_t NewTrueWeight = TWeight;
1627 uint64_t NewFalseWeight = (uint64_t)TWeight + 2 * (uint64_t)FWeight;
1628 ScaleWeights(NewTrueWeight, NewFalseWeight);
1629 // Emit the LHS condition.
1630 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc,
1631 NewTrueWeight, NewFalseWeight);
1633 NewTrueWeight = TWeight;
1634 NewFalseWeight = 2 * (uint64_t)FWeight;
1635 ScaleWeights(NewTrueWeight, NewFalseWeight);
1636 // Emit the RHS condition into TmpBB.
1637 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1638 NewTrueWeight, NewFalseWeight);
1640 assert(Opc == Instruction::And && "Unknown merge op!");
1641 // Codegen X & Y as:
1649 // This requires creation of TmpBB after CurBB.
1651 // We have flexibility in setting Prob for BB1 and Prob for TmpBB.
1652 // The requirement is that
1653 // FalseProb for BB1 + (TrueProb for BB1 * FalseProb for TmpBB)
1654 // = FalseProb for original BB.
1655 // Assuming the original weights are A and B, one choice is to set BB1's
1656 // weights to 2A+B and B, and set TmpBB's weights to 2A and B. This choice
1658 // FalseProb for BB1 == TrueProb for BB1 * FalseProb for TmpBB.
1660 uint64_t NewTrueWeight = 2 * (uint64_t)TWeight + (uint64_t)FWeight;
1661 uint64_t NewFalseWeight = FWeight;
1662 ScaleWeights(NewTrueWeight, NewFalseWeight);
1663 // Emit the LHS condition.
1664 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc,
1665 NewTrueWeight, NewFalseWeight);
1667 NewTrueWeight = 2 * (uint64_t)TWeight;
1668 NewFalseWeight = FWeight;
1669 ScaleWeights(NewTrueWeight, NewFalseWeight);
1670 // Emit the RHS condition into TmpBB.
1671 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc,
1672 NewTrueWeight, NewFalseWeight);
1676 /// If the set of cases should be emitted as a series of branches, return true.
1677 /// If we should emit this as a bunch of and/or'd together conditions, return
1680 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
1681 if (Cases.size() != 2) return true;
1683 // If this is two comparisons of the same values or'd or and'd together, they
1684 // will get folded into a single comparison, so don't emit two blocks.
1685 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
1686 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
1687 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
1688 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
1692 // Handle: (X != null) | (Y != null) --> (X|Y) != 0
1693 // Handle: (X == null) & (Y == null) --> (X|Y) == 0
1694 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
1695 Cases[0].CC == Cases[1].CC &&
1696 isa<Constant>(Cases[0].CmpRHS) &&
1697 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
1698 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
1700 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
1707 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1708 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1710 // Update machine-CFG edges.
1711 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
1713 if (I.isUnconditional()) {
1714 // Update machine-CFG edges.
1715 BrMBB->addSuccessor(Succ0MBB);
1717 // If this is not a fall-through branch or optimizations are switched off,
1719 if (Succ0MBB != NextBlock(BrMBB) || TM.getOptLevel() == CodeGenOpt::None)
1720 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
1721 MVT::Other, getControlRoot(),
1722 DAG.getBasicBlock(Succ0MBB)));
1727 // If this condition is one of the special cases we handle, do special stuff
1729 const Value *CondVal = I.getCondition();
1730 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
1732 // If this is a series of conditions that are or'd or and'd together, emit
1733 // this as a sequence of branches instead of setcc's with and/or operations.
1734 // As long as jumps are not expensive, this should improve performance.
1735 // For example, instead of something like:
1748 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) {
1749 Instruction::BinaryOps Opcode = BOp->getOpcode();
1750 if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
1751 !I.getMetadata(LLVMContext::MD_unpredictable) &&
1752 (Opcode == Instruction::And || Opcode == Instruction::Or)) {
1753 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
1754 Opcode, getEdgeWeight(BrMBB, Succ0MBB),
1755 getEdgeWeight(BrMBB, Succ1MBB));
1756 // If the compares in later blocks need to use values not currently
1757 // exported from this block, export them now. This block should always
1758 // be the first entry.
1759 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!");
1761 // Allow some cases to be rejected.
1762 if (ShouldEmitAsBranches(SwitchCases)) {
1763 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) {
1764 ExportFromCurrentBlock(SwitchCases[i].CmpLHS);
1765 ExportFromCurrentBlock(SwitchCases[i].CmpRHS);
1768 // Emit the branch for this block.
1769 visitSwitchCase(SwitchCases[0], BrMBB);
1770 SwitchCases.erase(SwitchCases.begin());
1774 // Okay, we decided not to do this, remove any inserted MBB's and clear
1776 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i)
1777 FuncInfo.MF->erase(SwitchCases[i].ThisBB);
1779 SwitchCases.clear();
1783 // Create a CaseBlock record representing this branch.
1784 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()),
1785 nullptr, Succ0MBB, Succ1MBB, BrMBB);
1787 // Use visitSwitchCase to actually insert the fast branch sequence for this
1789 visitSwitchCase(CB, BrMBB);
1792 /// visitSwitchCase - Emits the necessary code to represent a single node in
1793 /// the binary search tree resulting from lowering a switch instruction.
1794 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB,
1795 MachineBasicBlock *SwitchBB) {
1797 SDValue CondLHS = getValue(CB.CmpLHS);
1798 SDLoc dl = getCurSDLoc();
1800 // Build the setcc now.
1802 // Fold "(X == true)" to X and "(X == false)" to !X to
1803 // handle common cases produced by branch lowering.
1804 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) &&
1805 CB.CC == ISD::SETEQ)
1807 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) &&
1808 CB.CC == ISD::SETEQ) {
1809 SDValue True = DAG.getConstant(1, dl, CondLHS.getValueType());
1810 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
1812 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1814 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
1816 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
1817 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
1819 SDValue CmpOp = getValue(CB.CmpMHS);
1820 EVT VT = CmpOp.getValueType();
1822 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
1823 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, dl, VT),
1826 SDValue SUB = DAG.getNode(ISD::SUB, dl,
1827 VT, CmpOp, DAG.getConstant(Low, dl, VT));
1828 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1829 DAG.getConstant(High-Low, dl, VT), ISD::SETULE);
1833 // Update successor info
1834 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight);
1835 // TrueBB and FalseBB are always different unless the incoming IR is
1836 // degenerate. This only happens when running llc on weird IR.
1837 if (CB.TrueBB != CB.FalseBB)
1838 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight);
1840 // If the lhs block is the next block, invert the condition so that we can
1841 // fall through to the lhs instead of the rhs block.
1842 if (CB.TrueBB == NextBlock(SwitchBB)) {
1843 std::swap(CB.TrueBB, CB.FalseBB);
1844 SDValue True = DAG.getConstant(1, dl, Cond.getValueType());
1845 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
1848 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1849 MVT::Other, getControlRoot(), Cond,
1850 DAG.getBasicBlock(CB.TrueBB));
1852 // Insert the false branch. Do this even if it's a fall through branch,
1853 // this makes it easier to do DAG optimizations which require inverting
1854 // the branch condition.
1855 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1856 DAG.getBasicBlock(CB.FalseBB));
1858 DAG.setRoot(BrCond);
1861 /// visitJumpTable - Emit JumpTable node in the current MBB
1862 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) {
1863 // Emit the code for the jump table
1864 assert(JT.Reg != -1U && "Should lower JT Header first!");
1865 EVT PTy = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1866 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurSDLoc(),
1868 SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
1869 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurSDLoc(),
1870 MVT::Other, Index.getValue(1),
1872 DAG.setRoot(BrJumpTable);
1875 /// visitJumpTableHeader - This function emits necessary code to produce index
1876 /// in the JumpTable from switch case.
1877 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT,
1878 JumpTableHeader &JTH,
1879 MachineBasicBlock *SwitchBB) {
1880 SDLoc dl = getCurSDLoc();
1882 // Subtract the lowest switch case value from the value being switched on and
1883 // conditional branch to default mbb if the result is greater than the
1884 // difference between smallest and largest cases.
1885 SDValue SwitchOp = getValue(JTH.SValue);
1886 EVT VT = SwitchOp.getValueType();
1887 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
1888 DAG.getConstant(JTH.First, dl, VT));
1890 // The SDNode we just created, which holds the value being switched on minus
1891 // the smallest case value, needs to be copied to a virtual register so it
1892 // can be used as an index into the jump table in a subsequent basic block.
1893 // This value may be smaller or larger than the target's pointer type, and
1894 // therefore require extension or truncating.
1895 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1896 SwitchOp = DAG.getZExtOrTrunc(Sub, dl, TLI.getPointerTy(DAG.getDataLayout()));
1898 unsigned JumpTableReg =
1899 FuncInfo.CreateReg(TLI.getPointerTy(DAG.getDataLayout()));
1900 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl,
1901 JumpTableReg, SwitchOp);
1902 JT.Reg = JumpTableReg;
1904 // Emit the range check for the jump table, and branch to the default block
1905 // for the switch statement if the value being switched on exceeds the largest
1906 // case in the switch.
1907 SDValue CMP = DAG.getSetCC(
1908 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
1909 Sub.getValueType()),
1910 Sub, DAG.getConstant(JTH.Last - JTH.First, dl, VT), ISD::SETUGT);
1912 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1913 MVT::Other, CopyTo, CMP,
1914 DAG.getBasicBlock(JT.Default));
1916 // Avoid emitting unnecessary branches to the next block.
1917 if (JT.MBB != NextBlock(SwitchBB))
1918 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
1919 DAG.getBasicBlock(JT.MBB));
1921 DAG.setRoot(BrCond);
1924 /// Codegen a new tail for a stack protector check ParentMBB which has had its
1925 /// tail spliced into a stack protector check success bb.
1927 /// For a high level explanation of how this fits into the stack protector
1928 /// generation see the comment on the declaration of class
1929 /// StackProtectorDescriptor.
1930 void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
1931 MachineBasicBlock *ParentBB) {
1933 // First create the loads to the guard/stack slot for the comparison.
1934 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1935 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
1937 MachineFrameInfo *MFI = ParentBB->getParent()->getFrameInfo();
1938 int FI = MFI->getStackProtectorIndex();
1940 const Value *IRGuard = SPD.getGuard();
1941 SDValue GuardPtr = getValue(IRGuard);
1942 SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
1944 unsigned Align = DL->getPrefTypeAlignment(IRGuard->getType());
1947 SDLoc dl = getCurSDLoc();
1949 // If GuardReg is set and useLoadStackGuardNode returns true, retrieve the
1950 // guard value from the virtual register holding the value. Otherwise, emit a
1951 // volatile load to retrieve the stack guard value.
1952 unsigned GuardReg = SPD.getGuardReg();
1954 if (GuardReg && TLI.useLoadStackGuardNode())
1955 Guard = DAG.getCopyFromReg(DAG.getEntryNode(), dl, GuardReg,
1958 Guard = DAG.getLoad(PtrTy, dl, DAG.getEntryNode(),
1959 GuardPtr, MachinePointerInfo(IRGuard, 0),
1960 true, false, false, Align);
1962 SDValue StackSlot = DAG.getLoad(
1963 PtrTy, dl, DAG.getEntryNode(), StackSlotPtr,
1964 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), true,
1965 false, false, Align);
1967 // Perform the comparison via a subtract/getsetcc.
1968 EVT VT = Guard.getValueType();
1969 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Guard, StackSlot);
1971 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(DAG.getDataLayout(),
1973 Sub.getValueType()),
1974 Sub, DAG.getConstant(0, dl, VT), ISD::SETNE);
1976 // If the sub is not 0, then we know the guard/stackslot do not equal, so
1977 // branch to failure MBB.
1978 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
1979 MVT::Other, StackSlot.getOperand(0),
1980 Cmp, DAG.getBasicBlock(SPD.getFailureMBB()));
1981 // Otherwise branch to success MBB.
1982 SDValue Br = DAG.getNode(ISD::BR, dl,
1984 DAG.getBasicBlock(SPD.getSuccessMBB()));
1989 /// Codegen the failure basic block for a stack protector check.
1991 /// A failure stack protector machine basic block consists simply of a call to
1992 /// __stack_chk_fail().
1994 /// For a high level explanation of how this fits into the stack protector
1995 /// generation see the comment on the declaration of class
1996 /// StackProtectorDescriptor.
1998 SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
1999 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2001 TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
2002 None, false, getCurSDLoc(), false, false).second;
2006 /// visitBitTestHeader - This function emits necessary code to produce value
2007 /// suitable for "bit tests"
2008 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B,
2009 MachineBasicBlock *SwitchBB) {
2010 SDLoc dl = getCurSDLoc();
2012 // Subtract the minimum value
2013 SDValue SwitchOp = getValue(B.SValue);
2014 EVT VT = SwitchOp.getValueType();
2015 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, SwitchOp,
2016 DAG.getConstant(B.First, dl, VT));
2019 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2020 SDValue RangeCmp = DAG.getSetCC(
2021 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
2022 Sub.getValueType()),
2023 Sub, DAG.getConstant(B.Range, dl, VT), ISD::SETUGT);
2025 // Determine the type of the test operands.
2026 bool UsePtrType = false;
2027 if (!TLI.isTypeLegal(VT))
2030 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i)
2031 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) {
2032 // Switch table case range are encoded into series of masks.
2033 // Just use pointer type, it's guaranteed to fit.
2039 VT = TLI.getPointerTy(DAG.getDataLayout());
2040 Sub = DAG.getZExtOrTrunc(Sub, dl, VT);
2043 B.RegVT = VT.getSimpleVT();
2044 B.Reg = FuncInfo.CreateReg(B.RegVT);
2045 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), dl, B.Reg, Sub);
2047 MachineBasicBlock* MBB = B.Cases[0].ThisBB;
2049 addSuccessorWithWeight(SwitchBB, B.Default, B.DefaultWeight);
2050 addSuccessorWithWeight(SwitchBB, MBB, B.Weight);
2052 SDValue BrRange = DAG.getNode(ISD::BRCOND, dl,
2053 MVT::Other, CopyTo, RangeCmp,
2054 DAG.getBasicBlock(B.Default));
2056 // Avoid emitting unnecessary branches to the next block.
2057 if (MBB != NextBlock(SwitchBB))
2058 BrRange = DAG.getNode(ISD::BR, dl, MVT::Other, BrRange,
2059 DAG.getBasicBlock(MBB));
2061 DAG.setRoot(BrRange);
2064 /// visitBitTestCase - this function produces one "bit test"
2065 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB,
2066 MachineBasicBlock* NextMBB,
2067 uint32_t BranchWeightToNext,
2070 MachineBasicBlock *SwitchBB) {
2071 SDLoc dl = getCurSDLoc();
2073 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), dl, Reg, VT);
2075 unsigned PopCount = countPopulation(B.Mask);
2076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2077 if (PopCount == 1) {
2078 // Testing for a single bit; just compare the shift count with what it
2079 // would need to be to shift a 1 bit in that position.
2081 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2082 ShiftOp, DAG.getConstant(countTrailingZeros(B.Mask), dl, VT),
2084 } else if (PopCount == BB.Range) {
2085 // There is only one zero bit in the range, test for it directly.
2087 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2088 ShiftOp, DAG.getConstant(countTrailingOnes(B.Mask), dl, VT),
2091 // Make desired shift
2092 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT,
2093 DAG.getConstant(1, dl, VT), ShiftOp);
2095 // Emit bit tests and jumps
2096 SDValue AndOp = DAG.getNode(ISD::AND, dl,
2097 VT, SwitchVal, DAG.getConstant(B.Mask, dl, VT));
2099 dl, TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT),
2100 AndOp, DAG.getConstant(0, dl, VT), ISD::SETNE);
2103 // The branch weight from SwitchBB to B.TargetBB is B.ExtraWeight.
2104 addSuccessorWithWeight(SwitchBB, B.TargetBB, B.ExtraWeight);
2105 // The branch weight from SwitchBB to NextMBB is BranchWeightToNext.
2106 addSuccessorWithWeight(SwitchBB, NextMBB, BranchWeightToNext);
2108 SDValue BrAnd = DAG.getNode(ISD::BRCOND, dl,
2109 MVT::Other, getControlRoot(),
2110 Cmp, DAG.getBasicBlock(B.TargetBB));
2112 // Avoid emitting unnecessary branches to the next block.
2113 if (NextMBB != NextBlock(SwitchBB))
2114 BrAnd = DAG.getNode(ISD::BR, dl, MVT::Other, BrAnd,
2115 DAG.getBasicBlock(NextMBB));
2120 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
2121 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
2123 // Retrieve successors. Look through artificial IR level blocks like catchpads
2124 // and catchendpads for successors.
2125 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
2126 const BasicBlock *EHPadBB = I.getSuccessor(1);
2128 const Value *Callee(I.getCalledValue());
2129 const Function *Fn = dyn_cast<Function>(Callee);
2130 if (isa<InlineAsm>(Callee))
2132 else if (Fn && Fn->isIntrinsic()) {
2133 switch (Fn->getIntrinsicID()) {
2135 llvm_unreachable("Cannot invoke this intrinsic");
2136 case Intrinsic::donothing:
2137 // Ignore invokes to @llvm.donothing: jump directly to the next BB.
2139 case Intrinsic::experimental_patchpoint_void:
2140 case Intrinsic::experimental_patchpoint_i64:
2141 visitPatchpoint(&I, EHPadBB);
2143 case Intrinsic::experimental_gc_statepoint:
2144 LowerStatepoint(ImmutableStatepoint(&I), EHPadBB);
2148 LowerCallTo(&I, getValue(Callee), false, EHPadBB);
2150 // If the value of the invoke is used outside of its defining block, make it
2151 // available as a virtual register.
2152 // We already took care of the exported value for the statepoint instruction
2153 // during call to the LowerStatepoint.
2154 if (!isStatepoint(I)) {
2155 CopyToExportRegsIfNeeded(&I);
2158 SmallVector<std::pair<MachineBasicBlock *, uint32_t>, 1> UnwindDests;
2159 BranchProbabilityInfo *BPI = FuncInfo.BPI;
2160 uint32_t EHPadBBWeight =
2161 BPI ? BPI->getEdgeWeight(InvokeMBB->getBasicBlock(), EHPadBB) : 0;
2162 findUnwindDestinations(FuncInfo, EHPadBB, EHPadBBWeight, UnwindDests);
2164 // Update successor info.
2165 addSuccessorWithWeight(InvokeMBB, Return);
2166 for (auto &UnwindDest : UnwindDests) {
2167 UnwindDest.first->setIsEHPad();
2168 addSuccessorWithWeight(InvokeMBB, UnwindDest.first, UnwindDest.second);
2171 // Drop into normal successor.
2172 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(),
2173 MVT::Other, getControlRoot(),
2174 DAG.getBasicBlock(Return)));
2177 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) {
2178 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!");
2181 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) {
2182 assert(FuncInfo.MBB->isEHPad() &&
2183 "Call to landingpad not in landing pad!");
2185 MachineBasicBlock *MBB = FuncInfo.MBB;
2186 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
2187 AddLandingPadInfo(LP, MMI, MBB);
2189 // If there aren't registers to copy the values into (e.g., during SjLj
2190 // exceptions), then don't bother to create these DAG nodes.
2191 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2192 const Constant *PersonalityFn = FuncInfo.Fn->getPersonalityFn();
2193 if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
2194 TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
2197 SmallVector<EVT, 2> ValueVTs;
2198 SDLoc dl = getCurSDLoc();
2199 ComputeValueVTs(TLI, DAG.getDataLayout(), LP.getType(), ValueVTs);
2200 assert(ValueVTs.size() == 2 && "Only two-valued landingpads are supported");
2202 // Get the two live-in registers as SDValues. The physregs have already been
2203 // copied into virtual registers.
2205 if (FuncInfo.ExceptionPointerVirtReg) {
2206 Ops[0] = DAG.getZExtOrTrunc(
2207 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2208 FuncInfo.ExceptionPointerVirtReg,
2209 TLI.getPointerTy(DAG.getDataLayout())),
2212 Ops[0] = DAG.getConstant(0, dl, TLI.getPointerTy(DAG.getDataLayout()));
2214 Ops[1] = DAG.getZExtOrTrunc(
2215 DAG.getCopyFromReg(DAG.getEntryNode(), dl,
2216 FuncInfo.ExceptionSelectorVirtReg,
2217 TLI.getPointerTy(DAG.getDataLayout())),
2221 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl,
2222 DAG.getVTList(ValueVTs), Ops);
2226 void SelectionDAGBuilder::sortAndRangeify(CaseClusterVector &Clusters) {
2228 for (const CaseCluster &CC : Clusters)
2229 assert(CC.Low == CC.High && "Input clusters must be single-case");
2232 std::sort(Clusters.begin(), Clusters.end(),
2233 [](const CaseCluster &a, const CaseCluster &b) {
2234 return a.Low->getValue().slt(b.Low->getValue());
2237 // Merge adjacent clusters with the same destination.
2238 const unsigned N = Clusters.size();
2239 unsigned DstIndex = 0;
2240 for (unsigned SrcIndex = 0; SrcIndex < N; ++SrcIndex) {
2241 CaseCluster &CC = Clusters[SrcIndex];
2242 const ConstantInt *CaseVal = CC.Low;
2243 MachineBasicBlock *Succ = CC.MBB;
2245 if (DstIndex != 0 && Clusters[DstIndex - 1].MBB == Succ &&
2246 (CaseVal->getValue() - Clusters[DstIndex - 1].High->getValue()) == 1) {
2247 // If this case has the same successor and is a neighbour, merge it into
2248 // the previous cluster.
2249 Clusters[DstIndex - 1].High = CaseVal;
2250 Clusters[DstIndex - 1].Weight += CC.Weight;
2251 assert(Clusters[DstIndex - 1].Weight >= CC.Weight && "Weight overflow!");
2253 std::memmove(&Clusters[DstIndex++], &Clusters[SrcIndex],
2254 sizeof(Clusters[SrcIndex]));
2257 Clusters.resize(DstIndex);
2260 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First,
2261 MachineBasicBlock *Last) {
2263 for (unsigned i = 0, e = JTCases.size(); i != e; ++i)
2264 if (JTCases[i].first.HeaderBB == First)
2265 JTCases[i].first.HeaderBB = Last;
2267 // Update BitTestCases.
2268 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i)
2269 if (BitTestCases[i].Parent == First)
2270 BitTestCases[i].Parent = Last;
2273 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2274 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2276 // Update machine-CFG edges with unique successors.
2277 SmallSet<BasicBlock*, 32> Done;
2278 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) {
2279 BasicBlock *BB = I.getSuccessor(i);
2280 bool Inserted = Done.insert(BB).second;
2284 MachineBasicBlock *Succ = FuncInfo.MBBMap[BB];
2285 addSuccessorWithWeight(IndirectBrMBB, Succ);
2288 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurSDLoc(),
2289 MVT::Other, getControlRoot(),
2290 getValue(I.getAddress())));
2293 void SelectionDAGBuilder::visitUnreachable(const UnreachableInst &I) {
2294 if (DAG.getTarget().Options.TrapUnreachable)
2296 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
2299 void SelectionDAGBuilder::visitFSub(const User &I) {
2300 // -0.0 - X --> fneg
2301 Type *Ty = I.getType();
2302 if (isa<Constant>(I.getOperand(0)) &&
2303 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) {
2304 SDValue Op2 = getValue(I.getOperand(1));
2305 setValue(&I, DAG.getNode(ISD::FNEG, getCurSDLoc(),
2306 Op2.getValueType(), Op2));
2310 visitBinary(I, ISD::FSUB);
2313 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) {
2314 SDValue Op1 = getValue(I.getOperand(0));
2315 SDValue Op2 = getValue(I.getOperand(1));
2322 if (const OverflowingBinaryOperator *OFBinOp =
2323 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2324 nuw = OFBinOp->hasNoUnsignedWrap();
2325 nsw = OFBinOp->hasNoSignedWrap();
2327 if (const PossiblyExactOperator *ExactOp =
2328 dyn_cast<const PossiblyExactOperator>(&I))
2329 exact = ExactOp->isExact();
2330 if (const FPMathOperator *FPOp = dyn_cast<const FPMathOperator>(&I))
2331 FMF = FPOp->getFastMathFlags();
2334 Flags.setExact(exact);
2335 Flags.setNoSignedWrap(nsw);
2336 Flags.setNoUnsignedWrap(nuw);
2337 if (EnableFMFInDAG) {
2338 Flags.setAllowReciprocal(FMF.allowReciprocal());
2339 Flags.setNoInfs(FMF.noInfs());
2340 Flags.setNoNaNs(FMF.noNaNs());
2341 Flags.setNoSignedZeros(FMF.noSignedZeros());
2342 Flags.setUnsafeAlgebra(FMF.unsafeAlgebra());
2344 SDValue BinNodeValue = DAG.getNode(OpCode, getCurSDLoc(), Op1.getValueType(),
2346 setValue(&I, BinNodeValue);
2349 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) {
2350 SDValue Op1 = getValue(I.getOperand(0));
2351 SDValue Op2 = getValue(I.getOperand(1));
2353 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy(
2354 Op2.getValueType(), DAG.getDataLayout());
2356 // Coerce the shift amount to the right type if we can.
2357 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) {
2358 unsigned ShiftSize = ShiftTy.getSizeInBits();
2359 unsigned Op2Size = Op2.getValueType().getSizeInBits();
2360 SDLoc DL = getCurSDLoc();
2362 // If the operand is smaller than the shift count type, promote it.
2363 if (ShiftSize > Op2Size)
2364 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2);
2366 // If the operand is larger than the shift count type but the shift
2367 // count type has enough bits to represent any shift value, truncate
2368 // it now. This is a common case and it exposes the truncate to
2369 // optimization early.
2370 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits()))
2371 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2);
2372 // Otherwise we'll need to temporarily settle for some other convenient
2373 // type. Type legalization will make adjustments once the shiftee is split.
2375 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32);
2382 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) {
2384 if (const OverflowingBinaryOperator *OFBinOp =
2385 dyn_cast<const OverflowingBinaryOperator>(&I)) {
2386 nuw = OFBinOp->hasNoUnsignedWrap();
2387 nsw = OFBinOp->hasNoSignedWrap();
2389 if (const PossiblyExactOperator *ExactOp =
2390 dyn_cast<const PossiblyExactOperator>(&I))
2391 exact = ExactOp->isExact();
2394 Flags.setExact(exact);
2395 Flags.setNoSignedWrap(nsw);
2396 Flags.setNoUnsignedWrap(nuw);
2397 SDValue Res = DAG.getNode(Opcode, getCurSDLoc(), Op1.getValueType(), Op1, Op2,
2402 void SelectionDAGBuilder::visitSDiv(const User &I) {
2403 SDValue Op1 = getValue(I.getOperand(0));
2404 SDValue Op2 = getValue(I.getOperand(1));
2407 Flags.setExact(isa<PossiblyExactOperator>(&I) &&
2408 cast<PossiblyExactOperator>(&I)->isExact());
2409 setValue(&I, DAG.getNode(ISD::SDIV, getCurSDLoc(), Op1.getValueType(), Op1,
2413 void SelectionDAGBuilder::visitICmp(const User &I) {
2414 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE;
2415 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I))
2416 predicate = IC->getPredicate();
2417 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I))
2418 predicate = ICmpInst::Predicate(IC->getPredicate());
2419 SDValue Op1 = getValue(I.getOperand(0));
2420 SDValue Op2 = getValue(I.getOperand(1));
2421 ISD::CondCode Opcode = getICmpCondCode(predicate);
2423 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2425 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Opcode));
2428 void SelectionDAGBuilder::visitFCmp(const User &I) {
2429 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE;
2430 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I))
2431 predicate = FC->getPredicate();
2432 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I))
2433 predicate = FCmpInst::Predicate(FC->getPredicate());
2434 SDValue Op1 = getValue(I.getOperand(0));
2435 SDValue Op2 = getValue(I.getOperand(1));
2436 ISD::CondCode Condition = getFCmpCondCode(predicate);
2438 // FIXME: Fcmp instructions have fast-math-flags in IR, so we should use them.
2439 // FIXME: We should propagate the fast-math-flags to the DAG node itself for
2440 // further optimization, but currently FMF is only applicable to binary nodes.
2441 if (TM.Options.NoNaNsFPMath)
2442 Condition = getFCmpCodeWithoutNaN(Condition);
2443 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2445 setValue(&I, DAG.getSetCC(getCurSDLoc(), DestVT, Op1, Op2, Condition));
2448 void SelectionDAGBuilder::visitSelect(const User &I) {
2449 SmallVector<EVT, 4> ValueVTs;
2450 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(), I.getType(),
2452 unsigned NumValues = ValueVTs.size();
2453 if (NumValues == 0) return;
2455 SmallVector<SDValue, 4> Values(NumValues);
2456 SDValue Cond = getValue(I.getOperand(0));
2457 SDValue LHSVal = getValue(I.getOperand(1));
2458 SDValue RHSVal = getValue(I.getOperand(2));
2459 auto BaseOps = {Cond};
2460 ISD::NodeType OpCode = Cond.getValueType().isVector() ?
2461 ISD::VSELECT : ISD::SELECT;
2463 // Min/max matching is only viable if all output VTs are the same.
2464 if (std::equal(ValueVTs.begin(), ValueVTs.end(), ValueVTs.begin())) {
2465 EVT VT = ValueVTs[0];
2466 LLVMContext &Ctx = *DAG.getContext();
2467 auto &TLI = DAG.getTargetLoweringInfo();
2468 while (TLI.getTypeAction(Ctx, VT) == TargetLoweringBase::TypeSplitVector)
2469 VT = TLI.getTypeToTransformTo(Ctx, VT);
2472 auto SPR = matchSelectPattern(const_cast<User*>(&I), LHS, RHS);
2473 ISD::NodeType Opc = ISD::DELETED_NODE;
2474 switch (SPR.Flavor) {
2475 case SPF_UMAX: Opc = ISD::UMAX; break;
2476 case SPF_UMIN: Opc = ISD::UMIN; break;
2477 case SPF_SMAX: Opc = ISD::SMAX; break;
2478 case SPF_SMIN: Opc = ISD::SMIN; break;
2480 switch (SPR.NaNBehavior) {
2481 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2482 case SPNB_RETURNS_NAN: Opc = ISD::FMINNAN; break;
2483 case SPNB_RETURNS_OTHER: Opc = ISD::FMINNUM; break;
2484 case SPNB_RETURNS_ANY:
2485 Opc = TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) ? ISD::FMINNUM
2491 switch (SPR.NaNBehavior) {
2492 case SPNB_NA: llvm_unreachable("No NaN behavior for FP op?");
2493 case SPNB_RETURNS_NAN: Opc = ISD::FMAXNAN; break;
2494 case SPNB_RETURNS_OTHER: Opc = ISD::FMAXNUM; break;
2495 case SPNB_RETURNS_ANY:
2496 Opc = TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) ? ISD::FMAXNUM
2504 if (Opc != ISD::DELETED_NODE && TLI.isOperationLegalOrCustom(Opc, VT) &&
2505 // If the underlying comparison instruction is used by any other instruction,
2506 // the consumed instructions won't be destroyed, so it is not profitable
2507 // to convert to a min/max.
2508 cast<SelectInst>(&I)->getCondition()->hasOneUse()) {
2510 LHSVal = getValue(LHS);
2511 RHSVal = getValue(RHS);
2516 for (unsigned i = 0; i != NumValues; ++i) {
2517 SmallVector<SDValue, 3> Ops(BaseOps.begin(), BaseOps.end());
2518 Ops.push_back(SDValue(LHSVal.getNode(), LHSVal.getResNo() + i));
2519 Ops.push_back(SDValue(RHSVal.getNode(), RHSVal.getResNo() + i));
2520 Values[i] = DAG.getNode(OpCode, getCurSDLoc(),
2521 LHSVal.getNode()->getValueType(LHSVal.getResNo()+i),
2525 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2526 DAG.getVTList(ValueVTs), Values));
2529 void SelectionDAGBuilder::visitTrunc(const User &I) {
2530 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
2531 SDValue N = getValue(I.getOperand(0));
2532 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2534 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), DestVT, N));
2537 void SelectionDAGBuilder::visitZExt(const User &I) {
2538 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2539 // ZExt also can't be a cast to bool for same reason. So, nothing much to do
2540 SDValue N = getValue(I.getOperand(0));
2541 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2543 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurSDLoc(), DestVT, N));
2546 void SelectionDAGBuilder::visitSExt(const User &I) {
2547 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
2548 // SExt also can't be a cast to bool for same reason. So, nothing much to do
2549 SDValue N = getValue(I.getOperand(0));
2550 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2552 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurSDLoc(), DestVT, N));
2555 void SelectionDAGBuilder::visitFPTrunc(const User &I) {
2556 // FPTrunc is never a no-op cast, no need to check
2557 SDValue N = getValue(I.getOperand(0));
2558 SDLoc dl = getCurSDLoc();
2559 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2560 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2561 setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
2562 DAG.getTargetConstant(
2563 0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
2566 void SelectionDAGBuilder::visitFPExt(const User &I) {
2567 // FPExt is never a no-op cast, no need to check
2568 SDValue N = getValue(I.getOperand(0));
2569 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2571 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurSDLoc(), DestVT, N));
2574 void SelectionDAGBuilder::visitFPToUI(const User &I) {
2575 // FPToUI is never a no-op cast, no need to check
2576 SDValue N = getValue(I.getOperand(0));
2577 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2579 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurSDLoc(), DestVT, N));
2582 void SelectionDAGBuilder::visitFPToSI(const User &I) {
2583 // FPToSI is never a no-op cast, no need to check
2584 SDValue N = getValue(I.getOperand(0));
2585 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2587 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurSDLoc(), DestVT, N));
2590 void SelectionDAGBuilder::visitUIToFP(const User &I) {
2591 // UIToFP is never a no-op cast, no need to check
2592 SDValue N = getValue(I.getOperand(0));
2593 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2595 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
2598 void SelectionDAGBuilder::visitSIToFP(const User &I) {
2599 // SIToFP is never a no-op cast, no need to check
2600 SDValue N = getValue(I.getOperand(0));
2601 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2603 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurSDLoc(), DestVT, N));
2606 void SelectionDAGBuilder::visitPtrToInt(const User &I) {
2607 // What to do depends on the size of the integer and the size of the pointer.
2608 // We can either truncate, zero extend, or no-op, accordingly.
2609 SDValue N = getValue(I.getOperand(0));
2610 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2612 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2615 void SelectionDAGBuilder::visitIntToPtr(const User &I) {
2616 // What to do depends on the size of the integer and the size of the pointer.
2617 // We can either truncate, zero extend, or no-op, accordingly.
2618 SDValue N = getValue(I.getOperand(0));
2619 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2621 setValue(&I, DAG.getZExtOrTrunc(N, getCurSDLoc(), DestVT));
2624 void SelectionDAGBuilder::visitBitCast(const User &I) {
2625 SDValue N = getValue(I.getOperand(0));
2626 SDLoc dl = getCurSDLoc();
2627 EVT DestVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
2630 // BitCast assures us that source and destination are the same size so this is
2631 // either a BITCAST or a no-op.
2632 if (DestVT != N.getValueType())
2633 setValue(&I, DAG.getNode(ISD::BITCAST, dl,
2634 DestVT, N)); // convert types.
2635 // Check if the original LLVM IR Operand was a ConstantInt, because getValue()
2636 // might fold any kind of constant expression to an integer constant and that
2637 // is not what we are looking for. Only regcognize a bitcast of a genuine
2638 // constant integer as an opaque constant.
2639 else if(ConstantInt *C = dyn_cast<ConstantInt>(I.getOperand(0)))
2640 setValue(&I, DAG.getConstant(C->getValue(), dl, DestVT, /*isTarget=*/false,
2643 setValue(&I, N); // noop cast.
2646 void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
2647 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2648 const Value *SV = I.getOperand(0);
2649 SDValue N = getValue(SV);
2650 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2652 unsigned SrcAS = SV->getType()->getPointerAddressSpace();
2653 unsigned DestAS = I.getType()->getPointerAddressSpace();
2655 if (!TLI.isNoopAddrSpaceCast(SrcAS, DestAS))
2656 N = DAG.getAddrSpaceCast(getCurSDLoc(), DestVT, N, SrcAS, DestAS);
2661 void SelectionDAGBuilder::visitInsertElement(const User &I) {
2662 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2663 SDValue InVec = getValue(I.getOperand(0));
2664 SDValue InVal = getValue(I.getOperand(1));
2665 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(2)), getCurSDLoc(),
2666 TLI.getVectorIdxTy(DAG.getDataLayout()));
2667 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurSDLoc(),
2668 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2669 InVec, InVal, InIdx));
2672 void SelectionDAGBuilder::visitExtractElement(const User &I) {
2673 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2674 SDValue InVec = getValue(I.getOperand(0));
2675 SDValue InIdx = DAG.getSExtOrTrunc(getValue(I.getOperand(1)), getCurSDLoc(),
2676 TLI.getVectorIdxTy(DAG.getDataLayout()));
2677 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurSDLoc(),
2678 TLI.getValueType(DAG.getDataLayout(), I.getType()),
2682 // Utility for visitShuffleVector - Return true if every element in Mask,
2683 // beginning from position Pos and ending in Pos+Size, falls within the
2684 // specified sequential range [L, L+Pos). or is undef.
2685 static bool isSequentialInRange(const SmallVectorImpl<int> &Mask,
2686 unsigned Pos, unsigned Size, int Low) {
2687 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
2688 if (Mask[i] >= 0 && Mask[i] != Low)
2693 void SelectionDAGBuilder::visitShuffleVector(const User &I) {
2694 SDValue Src1 = getValue(I.getOperand(0));
2695 SDValue Src2 = getValue(I.getOperand(1));
2697 SmallVector<int, 8> Mask;
2698 ShuffleVectorInst::getShuffleMask(cast<Constant>(I.getOperand(2)), Mask);
2699 unsigned MaskNumElts = Mask.size();
2701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2702 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
2703 EVT SrcVT = Src1.getValueType();
2704 unsigned SrcNumElts = SrcVT.getVectorNumElements();
2706 if (SrcNumElts == MaskNumElts) {
2707 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2712 // Normalize the shuffle vector since mask and vector length don't match.
2713 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) {
2714 // Mask is longer than the source vectors and is a multiple of the source
2715 // vectors. We can use concatenate vector to make the mask and vectors
2717 if (SrcNumElts*2 == MaskNumElts) {
2718 // First check for Src1 in low and Src2 in high
2719 if (isSequentialInRange(Mask, 0, SrcNumElts, 0) &&
2720 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, SrcNumElts)) {
2721 // The shuffle is concatenating two vectors together.
2722 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2726 // Then check for Src2 in low and Src1 in high
2727 if (isSequentialInRange(Mask, 0, SrcNumElts, SrcNumElts) &&
2728 isSequentialInRange(Mask, SrcNumElts, SrcNumElts, 0)) {
2729 // The shuffle is concatenating two vectors together.
2730 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(),
2736 // Pad both vectors with undefs to make them the same length as the mask.
2737 unsigned NumConcat = MaskNumElts / SrcNumElts;
2738 bool Src1U = Src1.getOpcode() == ISD::UNDEF;
2739 bool Src2U = Src2.getOpcode() == ISD::UNDEF;
2740 SDValue UndefVal = DAG.getUNDEF(SrcVT);
2742 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal);
2743 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal);
2747 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2748 getCurSDLoc(), VT, MOps1);
2749 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS,
2750 getCurSDLoc(), VT, MOps2);
2752 // Readjust mask for new input vector length.
2753 SmallVector<int, 8> MappedOps;
2754 for (unsigned i = 0; i != MaskNumElts; ++i) {
2756 if (Idx >= (int)SrcNumElts)
2757 Idx -= SrcNumElts - MaskNumElts;
2758 MappedOps.push_back(Idx);
2761 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2766 if (SrcNumElts > MaskNumElts) {
2767 // Analyze the access pattern of the vector to see if we can extract
2768 // two subvectors and do the shuffle. The analysis is done by calculating
2769 // the range of elements the mask access on both vectors.
2770 int MinRange[2] = { static_cast<int>(SrcNumElts),
2771 static_cast<int>(SrcNumElts)};
2772 int MaxRange[2] = {-1, -1};
2774 for (unsigned i = 0; i != MaskNumElts; ++i) {
2780 if (Idx >= (int)SrcNumElts) {
2784 if (Idx > MaxRange[Input])
2785 MaxRange[Input] = Idx;
2786 if (Idx < MinRange[Input])
2787 MinRange[Input] = Idx;
2790 // Check if the access is smaller than the vector size and can we find
2791 // a reasonable extract index.
2792 int RangeUse[2] = { -1, -1 }; // 0 = Unused, 1 = Extract, -1 = Can not
2794 int StartIdx[2]; // StartIdx to extract from
2795 for (unsigned Input = 0; Input < 2; ++Input) {
2796 if (MinRange[Input] >= (int)SrcNumElts && MaxRange[Input] < 0) {
2797 RangeUse[Input] = 0; // Unused
2798 StartIdx[Input] = 0;
2802 // Find a good start index that is a multiple of the mask length. Then
2803 // see if the rest of the elements are in range.
2804 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts;
2805 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts &&
2806 StartIdx[Input] + MaskNumElts <= SrcNumElts)
2807 RangeUse[Input] = 1; // Extract from a multiple of the mask length.
2810 if (RangeUse[0] == 0 && RangeUse[1] == 0) {
2811 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used.
2814 if (RangeUse[0] >= 0 && RangeUse[1] >= 0) {
2815 // Extract appropriate subvector and generate a vector shuffle
2816 for (unsigned Input = 0; Input < 2; ++Input) {
2817 SDValue &Src = Input == 0 ? Src1 : Src2;
2818 if (RangeUse[Input] == 0)
2819 Src = DAG.getUNDEF(VT);
2821 SDLoc dl = getCurSDLoc();
2823 ISD::EXTRACT_SUBVECTOR, dl, VT, Src,
2824 DAG.getConstant(StartIdx[Input], dl,
2825 TLI.getVectorIdxTy(DAG.getDataLayout())));
2829 // Calculate new mask.
2830 SmallVector<int, 8> MappedOps;
2831 for (unsigned i = 0; i != MaskNumElts; ++i) {
2834 if (Idx < (int)SrcNumElts)
2837 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
2839 MappedOps.push_back(Idx);
2842 setValue(&I, DAG.getVectorShuffle(VT, getCurSDLoc(), Src1, Src2,
2848 // We can't use either concat vectors or extract subvectors so fall back to
2849 // replacing the shuffle with extract and build vector.
2850 // to insert and build vector.
2851 EVT EltVT = VT.getVectorElementType();
2852 EVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout());
2853 SDLoc dl = getCurSDLoc();
2854 SmallVector<SDValue,8> Ops;
2855 for (unsigned i = 0; i != MaskNumElts; ++i) {
2860 Res = DAG.getUNDEF(EltVT);
2862 SDValue &Src = Idx < (int)SrcNumElts ? Src1 : Src2;
2863 if (Idx >= (int)SrcNumElts) Idx -= SrcNumElts;
2865 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2866 EltVT, Src, DAG.getConstant(Idx, dl, IdxVT));
2872 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops));
2875 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) {
2876 const Value *Op0 = I.getOperand(0);
2877 const Value *Op1 = I.getOperand(1);
2878 Type *AggTy = I.getType();
2879 Type *ValTy = Op1->getType();
2880 bool IntoUndef = isa<UndefValue>(Op0);
2881 bool FromUndef = isa<UndefValue>(Op1);
2883 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2885 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2886 SmallVector<EVT, 4> AggValueVTs;
2887 ComputeValueVTs(TLI, DAG.getDataLayout(), AggTy, AggValueVTs);
2888 SmallVector<EVT, 4> ValValueVTs;
2889 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2891 unsigned NumAggValues = AggValueVTs.size();
2892 unsigned NumValValues = ValValueVTs.size();
2893 SmallVector<SDValue, 4> Values(NumAggValues);
2895 // Ignore an insertvalue that produces an empty object
2896 if (!NumAggValues) {
2897 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2901 SDValue Agg = getValue(Op0);
2903 // Copy the beginning value(s) from the original aggregate.
2904 for (; i != LinearIndex; ++i)
2905 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2906 SDValue(Agg.getNode(), Agg.getResNo() + i);
2907 // Copy values from the inserted value(s).
2909 SDValue Val = getValue(Op1);
2910 for (; i != LinearIndex + NumValValues; ++i)
2911 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2912 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex);
2914 // Copy remaining value(s) from the original aggregate.
2915 for (; i != NumAggValues; ++i)
2916 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) :
2917 SDValue(Agg.getNode(), Agg.getResNo() + i);
2919 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2920 DAG.getVTList(AggValueVTs), Values));
2923 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) {
2924 const Value *Op0 = I.getOperand(0);
2925 Type *AggTy = Op0->getType();
2926 Type *ValTy = I.getType();
2927 bool OutOfUndef = isa<UndefValue>(Op0);
2929 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices());
2931 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2932 SmallVector<EVT, 4> ValValueVTs;
2933 ComputeValueVTs(TLI, DAG.getDataLayout(), ValTy, ValValueVTs);
2935 unsigned NumValValues = ValValueVTs.size();
2937 // Ignore a extractvalue that produces an empty object
2938 if (!NumValValues) {
2939 setValue(&I, DAG.getUNDEF(MVT(MVT::Other)));
2943 SmallVector<SDValue, 4> Values(NumValValues);
2945 SDValue Agg = getValue(Op0);
2946 // Copy out the selected value(s).
2947 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
2948 Values[i - LinearIndex] =
2950 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) :
2951 SDValue(Agg.getNode(), Agg.getResNo() + i);
2953 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
2954 DAG.getVTList(ValValueVTs), Values));
2957 void SelectionDAGBuilder::visitGetElementPtr(const User &I) {
2958 Value *Op0 = I.getOperand(0);
2959 // Note that the pointer operand may be a vector of pointers. Take the scalar
2960 // element which holds a pointer.
2961 Type *Ty = Op0->getType()->getScalarType();
2962 unsigned AS = Ty->getPointerAddressSpace();
2963 SDValue N = getValue(Op0);
2964 SDLoc dl = getCurSDLoc();
2966 // Normalize Vector GEP - all scalar operands should be converted to the
2968 unsigned VectorWidth = I.getType()->isVectorTy() ?
2969 cast<VectorType>(I.getType())->getVectorNumElements() : 0;
2971 if (VectorWidth && !N.getValueType().isVector()) {
2972 MVT VT = MVT::getVectorVT(N.getValueType().getSimpleVT(), VectorWidth);
2973 SmallVector<SDValue, 16> Ops(VectorWidth, N);
2974 N = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2976 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end();
2978 const Value *Idx = *OI;
2979 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
2980 unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
2983 uint64_t Offset = DL->getStructLayout(StTy)->getElementOffset(Field);
2984 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N,
2985 DAG.getConstant(Offset, dl, N.getValueType()));
2988 Ty = StTy->getElementType(Field);
2990 Ty = cast<SequentialType>(Ty)->getElementType();
2992 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout(), AS);
2993 unsigned PtrSize = PtrTy.getSizeInBits();
2994 APInt ElementSize(PtrSize, DL->getTypeAllocSize(Ty));
2996 // If this is a scalar constant or a splat vector of constants,
2997 // handle it quickly.
2998 const auto *CI = dyn_cast<ConstantInt>(Idx);
2999 if (!CI && isa<ConstantDataVector>(Idx) &&
3000 cast<ConstantDataVector>(Idx)->getSplatValue())
3001 CI = cast<ConstantInt>(cast<ConstantDataVector>(Idx)->getSplatValue());
3006 APInt Offs = ElementSize * CI->getValue().sextOrTrunc(PtrSize);
3007 SDValue OffsVal = VectorWidth ?
3008 DAG.getConstant(Offs, dl, MVT::getVectorVT(PtrTy, VectorWidth)) :
3009 DAG.getConstant(Offs, dl, PtrTy);
3010 N = DAG.getNode(ISD::ADD, dl, N.getValueType(), N, OffsVal);
3014 // N = N + Idx * ElementSize;
3015 SDValue IdxN = getValue(Idx);
3017 if (!IdxN.getValueType().isVector() && VectorWidth) {
3018 MVT VT = MVT::getVectorVT(IdxN.getValueType().getSimpleVT(), VectorWidth);
3019 SmallVector<SDValue, 16> Ops(VectorWidth, IdxN);
3020 IdxN = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3022 // If the index is smaller or larger than intptr_t, truncate or extend
3024 IdxN = DAG.getSExtOrTrunc(IdxN, dl, N.getValueType());
3026 // If this is a multiply by a power of two, turn it into a shl
3027 // immediately. This is a very common case.
3028 if (ElementSize != 1) {
3029 if (ElementSize.isPowerOf2()) {
3030 unsigned Amt = ElementSize.logBase2();
3031 IdxN = DAG.getNode(ISD::SHL, dl,
3032 N.getValueType(), IdxN,
3033 DAG.getConstant(Amt, dl, IdxN.getValueType()));
3035 SDValue Scale = DAG.getConstant(ElementSize, dl, IdxN.getValueType());
3036 IdxN = DAG.getNode(ISD::MUL, dl,
3037 N.getValueType(), IdxN, Scale);
3041 N = DAG.getNode(ISD::ADD, dl,
3042 N.getValueType(), N, IdxN);
3049 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) {
3050 // If this is a fixed sized alloca in the entry block of the function,
3051 // allocate it statically on the stack.
3052 if (FuncInfo.StaticAllocaMap.count(&I))
3053 return; // getValue will auto-populate this.
3055 SDLoc dl = getCurSDLoc();
3056 Type *Ty = I.getAllocatedType();
3057 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3058 auto &DL = DAG.getDataLayout();
3059 uint64_t TySize = DL.getTypeAllocSize(Ty);
3061 std::max((unsigned)DL.getPrefTypeAlignment(Ty), I.getAlignment());
3063 SDValue AllocSize = getValue(I.getArraySize());
3065 EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
3066 if (AllocSize.getValueType() != IntPtr)
3067 AllocSize = DAG.getZExtOrTrunc(AllocSize, dl, IntPtr);
3069 AllocSize = DAG.getNode(ISD::MUL, dl, IntPtr,
3071 DAG.getConstant(TySize, dl, IntPtr));
3073 // Handle alignment. If the requested alignment is less than or equal to
3074 // the stack alignment, ignore it. If the size is greater than or equal to
3075 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node.
3076 unsigned StackAlign =
3077 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
3078 if (Align <= StackAlign)
3081 // Round the size of the allocation up to the stack alignment size
3082 // by add SA-1 to the size.
3083 AllocSize = DAG.getNode(ISD::ADD, dl,
3084 AllocSize.getValueType(), AllocSize,
3085 DAG.getIntPtrConstant(StackAlign - 1, dl));
3087 // Mask out the low bits for alignment purposes.
3088 AllocSize = DAG.getNode(ISD::AND, dl,
3089 AllocSize.getValueType(), AllocSize,
3090 DAG.getIntPtrConstant(~(uint64_t)(StackAlign - 1),
3093 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align, dl) };
3094 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
3095 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, dl, VTs, Ops);
3097 DAG.setRoot(DSA.getValue(1));
3099 assert(FuncInfo.MF->getFrameInfo()->hasVarSizedObjects());
3102 void SelectionDAGBuilder::visitLoad(const LoadInst &I) {
3104 return visitAtomicLoad(I);
3106 const Value *SV = I.getOperand(0);
3107 SDValue Ptr = getValue(SV);
3109 Type *Ty = I.getType();
3111 bool isVolatile = I.isVolatile();
3112 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3114 // The IR notion of invariant_load only guarantees that all *non-faulting*
3115 // invariant loads result in the same value. The MI notion of invariant load
3116 // guarantees that the load can be legally moved to any location within its
3117 // containing function. The MI notion of invariant_load is stronger than the
3118 // IR notion of invariant_load -- an MI invariant_load is an IR invariant_load
3119 // with a guarantee that the location being loaded from is dereferenceable
3120 // throughout the function's lifetime.
3122 bool isInvariant = I.getMetadata(LLVMContext::MD_invariant_load) != nullptr &&
3123 isDereferenceablePointer(SV, DAG.getDataLayout());
3124 unsigned Alignment = I.getAlignment();
3127 I.getAAMetadata(AAInfo);
3128 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3130 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3131 SmallVector<EVT, 4> ValueVTs;
3132 SmallVector<uint64_t, 4> Offsets;
3133 ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &Offsets);
3134 unsigned NumValues = ValueVTs.size();
3139 bool ConstantMemory = false;
3140 if (isVolatile || NumValues > MaxParallelChains)
3141 // Serialize volatile loads with other side effects.
3143 else if (AA->pointsToConstantMemory(MemoryLocation(
3144 SV, DAG.getDataLayout().getTypeStoreSize(Ty), AAInfo))) {
3145 // Do not serialize (non-volatile) loads of constant memory with anything.
3146 Root = DAG.getEntryNode();
3147 ConstantMemory = true;
3149 // Do not serialize non-volatile loads against each other.
3150 Root = DAG.getRoot();
3153 SDLoc dl = getCurSDLoc();
3156 Root = TLI.prepareVolatileOrAtomicLoad(Root, dl, DAG);
3158 SmallVector<SDValue, 4> Values(NumValues);
3159 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3160 EVT PtrVT = Ptr.getValueType();
3161 unsigned ChainI = 0;
3162 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3163 // Serializing loads here may result in excessive register pressure, and
3164 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling
3165 // could recover a bit by hoisting nodes upward in the chain by recognizing
3166 // they are side-effect free or do not alias. The optimizer should really
3167 // avoid this case by converting large object/array copies to llvm.memcpy
3168 // (MaxParallelChains should always remain as failsafe).
3169 if (ChainI == MaxParallelChains) {
3170 assert(PendingLoads.empty() && "PendingLoads must be serialized first");
3171 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3172 makeArrayRef(Chains.data(), ChainI));
3176 SDValue A = DAG.getNode(ISD::ADD, dl,
3178 DAG.getConstant(Offsets[i], dl, PtrVT));
3179 SDValue L = DAG.getLoad(ValueVTs[i], dl, Root,
3180 A, MachinePointerInfo(SV, Offsets[i]), isVolatile,
3181 isNonTemporal, isInvariant, Alignment, AAInfo,
3185 Chains[ChainI] = L.getValue(1);
3188 if (!ConstantMemory) {
3189 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3190 makeArrayRef(Chains.data(), ChainI));
3194 PendingLoads.push_back(Chain);
3197 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl,
3198 DAG.getVTList(ValueVTs), Values));
3201 void SelectionDAGBuilder::visitStore(const StoreInst &I) {
3203 return visitAtomicStore(I);
3205 const Value *SrcV = I.getOperand(0);
3206 const Value *PtrV = I.getOperand(1);
3208 SmallVector<EVT, 4> ValueVTs;
3209 SmallVector<uint64_t, 4> Offsets;
3210 ComputeValueVTs(DAG.getTargetLoweringInfo(), DAG.getDataLayout(),
3211 SrcV->getType(), ValueVTs, &Offsets);
3212 unsigned NumValues = ValueVTs.size();
3216 // Get the lowered operands. Note that we do this after
3217 // checking if NumResults is zero, because with zero results
3218 // the operands won't have values in the map.
3219 SDValue Src = getValue(SrcV);
3220 SDValue Ptr = getValue(PtrV);
3222 SDValue Root = getRoot();
3223 SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
3224 EVT PtrVT = Ptr.getValueType();
3225 bool isVolatile = I.isVolatile();
3226 bool isNonTemporal = I.getMetadata(LLVMContext::MD_nontemporal) != nullptr;
3227 unsigned Alignment = I.getAlignment();
3228 SDLoc dl = getCurSDLoc();
3231 I.getAAMetadata(AAInfo);
3233 unsigned ChainI = 0;
3234 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) {
3235 // See visitLoad comments.
3236 if (ChainI == MaxParallelChains) {
3237 SDValue Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3238 makeArrayRef(Chains.data(), ChainI));
3242 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr,
3243 DAG.getConstant(Offsets[i], dl, PtrVT));
3244 SDValue St = DAG.getStore(Root, dl,
3245 SDValue(Src.getNode(), Src.getResNo() + i),
3246 Add, MachinePointerInfo(PtrV, Offsets[i]),
3247 isVolatile, isNonTemporal, Alignment, AAInfo);
3248 Chains[ChainI] = St;
3251 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3252 makeArrayRef(Chains.data(), ChainI));
3253 DAG.setRoot(StoreNode);
3256 void SelectionDAGBuilder::visitMaskedStore(const CallInst &I) {
3257 SDLoc sdl = getCurSDLoc();
3259 // llvm.masked.store.*(Src0, Ptr, alignment, Mask)
3260 Value *PtrOperand = I.getArgOperand(1);
3261 SDValue Ptr = getValue(PtrOperand);
3262 SDValue Src0 = getValue(I.getArgOperand(0));
3263 SDValue Mask = getValue(I.getArgOperand(3));
3264 EVT VT = Src0.getValueType();
3265 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3267 Alignment = DAG.getEVTAlignment(VT);
3270 I.getAAMetadata(AAInfo);
3272 MachineMemOperand *MMO =
3273 DAG.getMachineFunction().
3274 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3275 MachineMemOperand::MOStore, VT.getStoreSize(),
3277 SDValue StoreNode = DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Mask, VT,
3279 DAG.setRoot(StoreNode);
3280 setValue(&I, StoreNode);
3283 // Get a uniform base for the Gather/Scatter intrinsic.
3284 // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
3285 // We try to represent it as a base pointer + vector of indices.
3286 // Usually, the vector of pointers comes from a 'getelementptr' instruction.
3287 // The first operand of the GEP may be a single pointer or a vector of pointers
3289 // %gep.ptr = getelementptr i32, <8 x i32*> %vptr, <8 x i32> %ind
3291 // %gep.ptr = getelementptr i32, i32* %ptr, <8 x i32> %ind
3292 // %res = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %gep.ptr, ..
3294 // When the first GEP operand is a single pointer - it is the uniform base we
3295 // are looking for. If first operand of the GEP is a splat vector - we
3296 // extract the spalt value and use it as a uniform base.
3297 // In all other cases the function returns 'false'.
3299 static bool getUniformBase(Value *& Ptr, SDValue& Base, SDValue& Index,
3300 SelectionDAGBuilder* SDB) {
3302 SelectionDAG& DAG = SDB->DAG;
3303 LLVMContext &Context = *DAG.getContext();
3305 assert(Ptr->getType()->isVectorTy() && "Uexpected pointer type");
3306 GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(Ptr);
3307 if (!GEP || GEP->getNumOperands() > 2)
3310 Value *GEPPtr = GEP->getPointerOperand();
3311 if (!GEPPtr->getType()->isVectorTy())
3313 else if (!(Ptr = getSplatValue(GEPPtr)))
3316 Value *IndexVal = GEP->getOperand(1);
3318 // The operands of the GEP may be defined in another basic block.
3319 // In this case we'll not find nodes for the operands.
3320 if (!SDB->findValue(Ptr) || !SDB->findValue(IndexVal))
3323 Base = SDB->getValue(Ptr);
3324 Index = SDB->getValue(IndexVal);
3326 // Suppress sign extension.
3327 if (SExtInst* Sext = dyn_cast<SExtInst>(IndexVal)) {
3328 if (SDB->findValue(Sext->getOperand(0))) {
3329 IndexVal = Sext->getOperand(0);
3330 Index = SDB->getValue(IndexVal);
3333 if (!Index.getValueType().isVector()) {
3334 unsigned GEPWidth = GEP->getType()->getVectorNumElements();
3335 EVT VT = EVT::getVectorVT(Context, Index.getValueType(), GEPWidth);
3336 SmallVector<SDValue, 16> Ops(GEPWidth, Index);
3337 Index = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Index), VT, Ops);
3342 void SelectionDAGBuilder::visitMaskedScatter(const CallInst &I) {
3343 SDLoc sdl = getCurSDLoc();
3345 // llvm.masked.scatter.*(Src0, Ptrs, alignemt, Mask)
3346 Value *Ptr = I.getArgOperand(1);
3347 SDValue Src0 = getValue(I.getArgOperand(0));
3348 SDValue Mask = getValue(I.getArgOperand(3));
3349 EVT VT = Src0.getValueType();
3350 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(2)))->getZExtValue();
3352 Alignment = DAG.getEVTAlignment(VT);
3353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3356 I.getAAMetadata(AAInfo);
3360 Value *BasePtr = Ptr;
3361 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3363 Value *MemOpBasePtr = UniformBase ? BasePtr : nullptr;
3364 MachineMemOperand *MMO = DAG.getMachineFunction().
3365 getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
3366 MachineMemOperand::MOStore, VT.getStoreSize(),
3369 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3370 Index = getValue(Ptr);
3372 SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index };
3373 SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
3375 DAG.setRoot(Scatter);
3376 setValue(&I, Scatter);
3379 void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I) {
3380 SDLoc sdl = getCurSDLoc();
3382 // @llvm.masked.load.*(Ptr, alignment, Mask, Src0)
3383 Value *PtrOperand = I.getArgOperand(0);
3384 SDValue Ptr = getValue(PtrOperand);
3385 SDValue Src0 = getValue(I.getArgOperand(3));
3386 SDValue Mask = getValue(I.getArgOperand(2));
3388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3389 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3390 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3392 Alignment = DAG.getEVTAlignment(VT);
3395 I.getAAMetadata(AAInfo);
3396 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3398 SDValue InChain = DAG.getRoot();
3399 if (AA->pointsToConstantMemory(MemoryLocation(
3400 PtrOperand, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3402 // Do not serialize (non-volatile) loads of constant memory with anything.
3403 InChain = DAG.getEntryNode();
3406 MachineMemOperand *MMO =
3407 DAG.getMachineFunction().
3408 getMachineMemOperand(MachinePointerInfo(PtrOperand),
3409 MachineMemOperand::MOLoad, VT.getStoreSize(),
3410 Alignment, AAInfo, Ranges);
3412 SDValue Load = DAG.getMaskedLoad(VT, sdl, InChain, Ptr, Mask, Src0, VT, MMO,
3414 SDValue OutChain = Load.getValue(1);
3415 DAG.setRoot(OutChain);
3419 void SelectionDAGBuilder::visitMaskedGather(const CallInst &I) {
3420 SDLoc sdl = getCurSDLoc();
3422 // @llvm.masked.gather.*(Ptrs, alignment, Mask, Src0)
3423 Value *Ptr = I.getArgOperand(0);
3424 SDValue Src0 = getValue(I.getArgOperand(3));
3425 SDValue Mask = getValue(I.getArgOperand(2));
3427 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3428 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3429 unsigned Alignment = (cast<ConstantInt>(I.getArgOperand(1)))->getZExtValue();
3431 Alignment = DAG.getEVTAlignment(VT);
3434 I.getAAMetadata(AAInfo);
3435 const MDNode *Ranges = I.getMetadata(LLVMContext::MD_range);
3437 SDValue Root = DAG.getRoot();
3440 Value *BasePtr = Ptr;
3441 bool UniformBase = getUniformBase(BasePtr, Base, Index, this);
3442 bool ConstantMemory = false;
3444 AA->pointsToConstantMemory(MemoryLocation(
3445 BasePtr, DAG.getDataLayout().getTypeStoreSize(I.getType()),
3447 // Do not serialize (non-volatile) loads of constant memory with anything.
3448 Root = DAG.getEntryNode();
3449 ConstantMemory = true;
3452 MachineMemOperand *MMO =
3453 DAG.getMachineFunction().
3454 getMachineMemOperand(MachinePointerInfo(UniformBase ? BasePtr : nullptr),
3455 MachineMemOperand::MOLoad, VT.getStoreSize(),
3456 Alignment, AAInfo, Ranges);
3459 Base = DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
3460 Index = getValue(Ptr);
3462 SDValue Ops[] = { Root, Src0, Mask, Base, Index };
3463 SDValue Gather = DAG.getMaskedGather(DAG.getVTList(VT, MVT::Other), VT, sdl,
3466 SDValue OutChain = Gather.getValue(1);
3467 if (!ConstantMemory)
3468 PendingLoads.push_back(OutChain);
3469 setValue(&I, Gather);
3472 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) {
3473 SDLoc dl = getCurSDLoc();
3474 AtomicOrdering SuccessOrder = I.getSuccessOrdering();
3475 AtomicOrdering FailureOrder = I.getFailureOrdering();
3476 SynchronizationScope Scope = I.getSynchScope();
3478 SDValue InChain = getRoot();
3480 MVT MemVT = getValue(I.getCompareOperand()).getSimpleValueType();
3481 SDVTList VTs = DAG.getVTList(MemVT, MVT::i1, MVT::Other);
3482 SDValue L = DAG.getAtomicCmpSwap(
3483 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl, MemVT, VTs, InChain,
3484 getValue(I.getPointerOperand()), getValue(I.getCompareOperand()),
3485 getValue(I.getNewValOperand()), MachinePointerInfo(I.getPointerOperand()),
3486 /*Alignment=*/ 0, SuccessOrder, FailureOrder, Scope);
3488 SDValue OutChain = L.getValue(2);
3491 DAG.setRoot(OutChain);
3494 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) {
3495 SDLoc dl = getCurSDLoc();
3497 switch (I.getOperation()) {
3498 default: llvm_unreachable("Unknown atomicrmw operation");
3499 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break;
3500 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break;
3501 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break;
3502 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break;
3503 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break;
3504 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break;
3505 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break;
3506 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break;
3507 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break;
3508 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break;
3509 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break;
3511 AtomicOrdering Order = I.getOrdering();
3512 SynchronizationScope Scope = I.getSynchScope();
3514 SDValue InChain = getRoot();
3517 DAG.getAtomic(NT, dl,
3518 getValue(I.getValOperand()).getSimpleValueType(),
3520 getValue(I.getPointerOperand()),
3521 getValue(I.getValOperand()),
3522 I.getPointerOperand(),
3523 /* Alignment=*/ 0, Order, Scope);
3525 SDValue OutChain = L.getValue(1);
3528 DAG.setRoot(OutChain);
3531 void SelectionDAGBuilder::visitFence(const FenceInst &I) {
3532 SDLoc dl = getCurSDLoc();
3533 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3536 Ops[1] = DAG.getConstant(I.getOrdering(), dl,
3537 TLI.getPointerTy(DAG.getDataLayout()));
3538 Ops[2] = DAG.getConstant(I.getSynchScope(), dl,
3539 TLI.getPointerTy(DAG.getDataLayout()));
3540 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops));
3543 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) {
3544 SDLoc dl = getCurSDLoc();
3545 AtomicOrdering Order = I.getOrdering();
3546 SynchronizationScope Scope = I.getSynchScope();
3548 SDValue InChain = getRoot();
3550 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3551 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
3553 if (I.getAlignment() < VT.getSizeInBits() / 8)
3554 report_fatal_error("Cannot generate unaligned atomic load");
3556 MachineMemOperand *MMO =
3557 DAG.getMachineFunction().
3558 getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
3559 MachineMemOperand::MOVolatile |
3560 MachineMemOperand::MOLoad,
3562 I.getAlignment() ? I.getAlignment() :
3563 DAG.getEVTAlignment(VT));
3565 InChain = TLI.prepareVolatileOrAtomicLoad(InChain, dl, DAG);
3567 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain,
3568 getValue(I.getPointerOperand()), MMO,
3571 SDValue OutChain = L.getValue(1);
3574 DAG.setRoot(OutChain);
3577 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) {
3578 SDLoc dl = getCurSDLoc();
3580 AtomicOrdering Order = I.getOrdering();
3581 SynchronizationScope Scope = I.getSynchScope();
3583 SDValue InChain = getRoot();
3585 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3587 TLI.getValueType(DAG.getDataLayout(), I.getValueOperand()->getType());
3589 if (I.getAlignment() < VT.getSizeInBits() / 8)
3590 report_fatal_error("Cannot generate unaligned atomic store");
3593 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT,
3595 getValue(I.getPointerOperand()),
3596 getValue(I.getValueOperand()),
3597 I.getPointerOperand(), I.getAlignment(),
3600 DAG.setRoot(OutChain);
3603 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
3605 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
3606 unsigned Intrinsic) {
3607 bool HasChain = !I.doesNotAccessMemory();
3608 bool OnlyLoad = HasChain && I.onlyReadsMemory();
3610 // Build the operand list.
3611 SmallVector<SDValue, 8> Ops;
3612 if (HasChain) { // If this intrinsic has side-effects, chainify it.
3614 // We don't need to serialize loads against other loads.
3615 Ops.push_back(DAG.getRoot());
3617 Ops.push_back(getRoot());
3621 // Info is set by getTgtMemInstrinsic
3622 TargetLowering::IntrinsicInfo Info;
3623 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3624 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic);
3626 // Add the intrinsic ID as an integer operand if it's not a target intrinsic.
3627 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID ||
3628 Info.opc == ISD::INTRINSIC_W_CHAIN)
3629 Ops.push_back(DAG.getTargetConstant(Intrinsic, getCurSDLoc(),
3630 TLI.getPointerTy(DAG.getDataLayout())));
3632 // Add all operands of the call to the operand list.
3633 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
3634 SDValue Op = getValue(I.getArgOperand(i));
3638 SmallVector<EVT, 4> ValueVTs;
3639 ComputeValueVTs(TLI, DAG.getDataLayout(), I.getType(), ValueVTs);
3642 ValueVTs.push_back(MVT::Other);
3644 SDVTList VTs = DAG.getVTList(ValueVTs);
3648 if (IsTgtIntrinsic) {
3649 // This is target intrinsic that touches memory
3650 Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
3651 VTs, Ops, Info.memVT,
3652 MachinePointerInfo(Info.ptrVal, Info.offset),
3653 Info.align, Info.vol,
3654 Info.readMem, Info.writeMem, Info.size);
3655 } else if (!HasChain) {
3656 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
3657 } else if (!I.getType()->isVoidTy()) {
3658 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurSDLoc(), VTs, Ops);
3660 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurSDLoc(), VTs, Ops);
3664 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1);
3666 PendingLoads.push_back(Chain);
3671 if (!I.getType()->isVoidTy()) {
3672 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
3673 EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
3674 Result = DAG.getNode(ISD::BITCAST, getCurSDLoc(), VT, Result);
3677 setValue(&I, Result);
3681 /// GetSignificand - Get the significand and build it into a floating-point
3682 /// number with exponent of 1:
3684 /// Op = (Op & 0x007fffff) | 0x3f800000;
3686 /// where Op is the hexadecimal representation of floating point value.
3688 GetSignificand(SelectionDAG &DAG, SDValue Op, SDLoc dl) {
3689 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3690 DAG.getConstant(0x007fffff, dl, MVT::i32));
3691 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
3692 DAG.getConstant(0x3f800000, dl, MVT::i32));
3693 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2);
3696 /// GetExponent - Get the exponent:
3698 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127);
3700 /// where Op is the hexadecimal representation of floating point value.
3702 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
3704 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
3705 DAG.getConstant(0x7f800000, dl, MVT::i32));
3706 SDValue t1 = DAG.getNode(
3707 ISD::SRL, dl, MVT::i32, t0,
3708 DAG.getConstant(23, dl, TLI.getPointerTy(DAG.getDataLayout())));
3709 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
3710 DAG.getConstant(127, dl, MVT::i32));
3711 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
3714 /// getF32Constant - Get 32-bit floating point constant.
3716 getF32Constant(SelectionDAG &DAG, unsigned Flt, SDLoc dl) {
3717 return DAG.getConstantFP(APFloat(APFloat::IEEEsingle, APInt(32, Flt)), dl,
3721 static SDValue getLimitedPrecisionExp2(SDValue t0, SDLoc dl,
3722 SelectionDAG &DAG) {
3723 // TODO: What fast-math-flags should be set on the floating-point nodes?
3725 // IntegerPartOfX = ((int32_t)(t0);
3726 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
3728 // FractionalPartOfX = t0 - (float)IntegerPartOfX;
3729 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
3730 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
3732 // IntegerPartOfX <<= 23;
3733 IntegerPartOfX = DAG.getNode(
3734 ISD::SHL, dl, MVT::i32, IntegerPartOfX,
3735 DAG.getConstant(23, dl, DAG.getTargetLoweringInfo().getPointerTy(
3736 DAG.getDataLayout())));
3738 SDValue TwoToFractionalPartOfX;
3739 if (LimitFloatPrecision <= 6) {
3740 // For floating-point precision of 6:
3742 // TwoToFractionalPartOfX =
3744 // (0.735607626f + 0.252464424f * x) * x;
3746 // error 0.0144103317, which is 6 bits
3747 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3748 getF32Constant(DAG, 0x3e814304, dl));
3749 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3750 getF32Constant(DAG, 0x3f3c50c8, dl));
3751 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3752 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3753 getF32Constant(DAG, 0x3f7f5e7e, dl));
3754 } else if (LimitFloatPrecision <= 12) {
3755 // For floating-point precision of 12:
3757 // TwoToFractionalPartOfX =
3760 // (0.224338339f + 0.792043434e-1f * x) * x) * x;
3762 // error 0.000107046256, which is 13 to 14 bits
3763 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3764 getF32Constant(DAG, 0x3da235e3, dl));
3765 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3766 getF32Constant(DAG, 0x3e65b8f3, dl));
3767 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3768 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3769 getF32Constant(DAG, 0x3f324b07, dl));
3770 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3771 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3772 getF32Constant(DAG, 0x3f7ff8fd, dl));
3773 } else { // LimitFloatPrecision <= 18
3774 // For floating-point precision of 18:
3776 // TwoToFractionalPartOfX =
3780 // (0.554906021e-1f +
3781 // (0.961591928e-2f +
3782 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
3783 // error 2.47208000*10^(-7), which is better than 18 bits
3784 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3785 getF32Constant(DAG, 0x3924b03e, dl));
3786 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
3787 getF32Constant(DAG, 0x3ab24b87, dl));
3788 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3789 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3790 getF32Constant(DAG, 0x3c1d8c17, dl));
3791 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3792 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
3793 getF32Constant(DAG, 0x3d634a1d, dl));
3794 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3795 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3796 getF32Constant(DAG, 0x3e75fe14, dl));
3797 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3798 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
3799 getF32Constant(DAG, 0x3f317234, dl));
3800 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
3801 TwoToFractionalPartOfX = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
3802 getF32Constant(DAG, 0x3f800000, dl));
3805 // Add the exponent into the result in integer domain.
3806 SDValue t13 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, TwoToFractionalPartOfX);
3807 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3808 DAG.getNode(ISD::ADD, dl, MVT::i32, t13, IntegerPartOfX));
3811 /// expandExp - Lower an exp intrinsic. Handles the special sequences for
3812 /// limited-precision mode.
3813 static SDValue expandExp(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3814 const TargetLowering &TLI) {
3815 if (Op.getValueType() == MVT::f32 &&
3816 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3818 // Put the exponent in the right bit position for later addition to the
3821 // #define LOG2OFe 1.4426950f
3822 // t0 = Op * LOG2OFe
3824 // TODO: What fast-math-flags should be set here?
3825 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
3826 getF32Constant(DAG, 0x3fb8aa3b, dl));
3827 return getLimitedPrecisionExp2(t0, dl, DAG);
3830 // No special expansion.
3831 return DAG.getNode(ISD::FEXP, dl, Op.getValueType(), Op);
3834 /// expandLog - Lower a log intrinsic. Handles the special sequences for
3835 /// limited-precision mode.
3836 static SDValue expandLog(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3837 const TargetLowering &TLI) {
3839 // TODO: What fast-math-flags should be set on the floating-point nodes?
3841 if (Op.getValueType() == MVT::f32 &&
3842 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3843 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3845 // Scale the exponent by log(2) [0.69314718f].
3846 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
3847 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
3848 getF32Constant(DAG, 0x3f317218, dl));
3850 // Get the significand and build it into a floating-point number with
3852 SDValue X = GetSignificand(DAG, Op1, dl);
3854 SDValue LogOfMantissa;
3855 if (LimitFloatPrecision <= 6) {
3856 // For floating-point precision of 6:
3860 // (1.4034025f - 0.23903021f * x) * x;
3862 // error 0.0034276066, which is better than 8 bits
3863 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3864 getF32Constant(DAG, 0xbe74c456, dl));
3865 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3866 getF32Constant(DAG, 0x3fb3a2b1, dl));
3867 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3868 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3869 getF32Constant(DAG, 0x3f949a29, dl));
3870 } else if (LimitFloatPrecision <= 12) {
3871 // For floating-point precision of 12:
3877 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
3879 // error 0.000061011436, which is 14 bits
3880 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3881 getF32Constant(DAG, 0xbd67b6d6, dl));
3882 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3883 getF32Constant(DAG, 0x3ee4f4b8, dl));
3884 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3885 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3886 getF32Constant(DAG, 0x3fbc278b, dl));
3887 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3888 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3889 getF32Constant(DAG, 0x40348e95, dl));
3890 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3891 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3892 getF32Constant(DAG, 0x3fdef31a, dl));
3893 } else { // LimitFloatPrecision <= 18
3894 // For floating-point precision of 18:
3902 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
3904 // error 0.0000023660568, which is better than 18 bits
3905 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3906 getF32Constant(DAG, 0xbc91e5ac, dl));
3907 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3908 getF32Constant(DAG, 0x3e4350aa, dl));
3909 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3910 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3911 getF32Constant(DAG, 0x3f60d3e3, dl));
3912 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3913 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3914 getF32Constant(DAG, 0x4011cdf0, dl));
3915 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3916 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3917 getF32Constant(DAG, 0x406cfd1c, dl));
3918 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
3919 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
3920 getF32Constant(DAG, 0x408797cb, dl));
3921 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
3922 LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
3923 getF32Constant(DAG, 0x4006dcab, dl));
3926 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, LogOfMantissa);
3929 // No special expansion.
3930 return DAG.getNode(ISD::FLOG, dl, Op.getValueType(), Op);
3933 /// expandLog2 - Lower a log2 intrinsic. Handles the special sequences for
3934 /// limited-precision mode.
3935 static SDValue expandLog2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
3936 const TargetLowering &TLI) {
3938 // TODO: What fast-math-flags should be set on the floating-point nodes?
3940 if (Op.getValueType() == MVT::f32 &&
3941 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
3942 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3944 // Get the exponent.
3945 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
3947 // Get the significand and build it into a floating-point number with
3949 SDValue X = GetSignificand(DAG, Op1, dl);
3951 // Different possible minimax approximations of significand in
3952 // floating-point for various degrees of accuracy over [1,2].
3953 SDValue Log2ofMantissa;
3954 if (LimitFloatPrecision <= 6) {
3955 // For floating-point precision of 6:
3957 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
3959 // error 0.0049451742, which is more than 7 bits
3960 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3961 getF32Constant(DAG, 0xbeb08fe0, dl));
3962 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3963 getF32Constant(DAG, 0x40019463, dl));
3964 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3965 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3966 getF32Constant(DAG, 0x3fd6633d, dl));
3967 } else if (LimitFloatPrecision <= 12) {
3968 // For floating-point precision of 12:
3974 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
3976 // error 0.0000876136000, which is better than 13 bits
3977 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
3978 getF32Constant(DAG, 0xbda7262e, dl));
3979 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
3980 getF32Constant(DAG, 0x3f25280b, dl));
3981 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
3982 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
3983 getF32Constant(DAG, 0x4007b923, dl));
3984 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
3985 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
3986 getF32Constant(DAG, 0x40823e2f, dl));
3987 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
3988 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
3989 getF32Constant(DAG, 0x4020d29c, dl));
3990 } else { // LimitFloatPrecision <= 18
3991 // For floating-point precision of 18:
4000 // 0.25691327e-1f * x) * x) * x) * x) * x) * x;
4002 // error 0.0000018516, which is better than 18 bits
4003 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4004 getF32Constant(DAG, 0xbcd2769e, dl));
4005 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4006 getF32Constant(DAG, 0x3e8ce0b9, dl));
4007 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4008 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4009 getF32Constant(DAG, 0x3fa22ae7, dl));
4010 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4011 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
4012 getF32Constant(DAG, 0x40525723, dl));
4013 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4014 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
4015 getF32Constant(DAG, 0x40aaf200, dl));
4016 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4017 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
4018 getF32Constant(DAG, 0x40c39dad, dl));
4019 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
4020 Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
4021 getF32Constant(DAG, 0x4042902c, dl));
4024 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
4027 // No special expansion.
4028 return DAG.getNode(ISD::FLOG2, dl, Op.getValueType(), Op);
4031 /// expandLog10 - Lower a log10 intrinsic. Handles the special sequences for
4032 /// limited-precision mode.
4033 static SDValue expandLog10(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4034 const TargetLowering &TLI) {
4036 // TODO: What fast-math-flags should be set on the floating-point nodes?
4038 if (Op.getValueType() == MVT::f32 &&
4039 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4040 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
4042 // Scale the exponent by log10(2) [0.30102999f].
4043 SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
4044 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
4045 getF32Constant(DAG, 0x3e9a209a, dl));
4047 // Get the significand and build it into a floating-point number with
4049 SDValue X = GetSignificand(DAG, Op1, dl);
4051 SDValue Log10ofMantissa;
4052 if (LimitFloatPrecision <= 6) {
4053 // For floating-point precision of 6:
4055 // Log10ofMantissa =
4057 // (0.60948995f - 0.10380950f * x) * x;
4059 // error 0.0014886165, which is 6 bits
4060 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4061 getF32Constant(DAG, 0xbdd49a13, dl));
4062 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
4063 getF32Constant(DAG, 0x3f1c0789, dl));
4064 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4065 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
4066 getF32Constant(DAG, 0x3f011300, dl));
4067 } else if (LimitFloatPrecision <= 12) {
4068 // For floating-point precision of 12:
4070 // Log10ofMantissa =
4073 // (-0.31664806f + 0.47637168e-1f * x) * x) * x;
4075 // error 0.00019228036, which is better than 12 bits
4076 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4077 getF32Constant(DAG, 0x3d431f31, dl));
4078 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4079 getF32Constant(DAG, 0x3ea21fb2, dl));
4080 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4081 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4082 getF32Constant(DAG, 0x3f6ae232, dl));
4083 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4084 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4085 getF32Constant(DAG, 0x3f25f7c3, dl));
4086 } else { // LimitFloatPrecision <= 18
4087 // For floating-point precision of 18:
4089 // Log10ofMantissa =
4094 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
4096 // error 0.0000037995730, which is better than 18 bits
4097 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
4098 getF32Constant(DAG, 0x3c5d51ce, dl));
4099 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
4100 getF32Constant(DAG, 0x3e00685a, dl));
4101 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
4102 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
4103 getF32Constant(DAG, 0x3efb6798, dl));
4104 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
4105 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
4106 getF32Constant(DAG, 0x3f88d192, dl));
4107 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
4108 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
4109 getF32Constant(DAG, 0x3fc4316c, dl));
4110 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
4111 Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
4112 getF32Constant(DAG, 0x3f57ce70, dl));
4115 return DAG.getNode(ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
4118 // No special expansion.
4119 return DAG.getNode(ISD::FLOG10, dl, Op.getValueType(), Op);
4122 /// expandExp2 - Lower an exp2 intrinsic. Handles the special sequences for
4123 /// limited-precision mode.
4124 static SDValue expandExp2(SDLoc dl, SDValue Op, SelectionDAG &DAG,
4125 const TargetLowering &TLI) {
4126 if (Op.getValueType() == MVT::f32 &&
4127 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18)
4128 return getLimitedPrecisionExp2(Op, dl, DAG);
4130 // No special expansion.
4131 return DAG.getNode(ISD::FEXP2, dl, Op.getValueType(), Op);
4134 /// visitPow - Lower a pow intrinsic. Handles the special sequences for
4135 /// limited-precision mode with x == 10.0f.
4136 static SDValue expandPow(SDLoc dl, SDValue LHS, SDValue RHS,
4137 SelectionDAG &DAG, const TargetLowering &TLI) {
4138 bool IsExp10 = false;
4139 if (LHS.getValueType() == MVT::f32 && RHS.getValueType() == MVT::f32 &&
4140 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
4141 if (ConstantFPSDNode *LHSC = dyn_cast<ConstantFPSDNode>(LHS)) {
4143 IsExp10 = LHSC->isExactlyValue(Ten);
4147 // TODO: What fast-math-flags should be set on the FMUL node?
4149 // Put the exponent in the right bit position for later addition to the
4152 // #define LOG2OF10 3.3219281f
4153 // t0 = Op * LOG2OF10;
4154 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, RHS,
4155 getF32Constant(DAG, 0x40549a78, dl));
4156 return getLimitedPrecisionExp2(t0, dl, DAG);
4159 // No special expansion.
4160 return DAG.getNode(ISD::FPOW, dl, LHS.getValueType(), LHS, RHS);
4164 /// ExpandPowI - Expand a llvm.powi intrinsic.
4165 static SDValue ExpandPowI(SDLoc DL, SDValue LHS, SDValue RHS,
4166 SelectionDAG &DAG) {
4167 // If RHS is a constant, we can expand this out to a multiplication tree,
4168 // otherwise we end up lowering to a call to __powidf2 (for example). When
4169 // optimizing for size, we only want to do this if the expansion would produce
4170 // a small number of multiplies, otherwise we do the full expansion.
4171 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4172 // Get the exponent as a positive value.
4173 unsigned Val = RHSC->getSExtValue();
4174 if ((int)Val < 0) Val = -Val;
4176 // powi(x, 0) -> 1.0
4178 return DAG.getConstantFP(1.0, DL, LHS.getValueType());
4180 const Function *F = DAG.getMachineFunction().getFunction();
4181 if (!F->optForSize() ||
4182 // If optimizing for size, don't insert too many multiplies.
4183 // This inserts up to 5 multiplies.
4184 countPopulation(Val) + Log2_32(Val) < 7) {
4185 // We use the simple binary decomposition method to generate the multiply
4186 // sequence. There are more optimal ways to do this (for example,
4187 // powi(x,15) generates one more multiply than it should), but this has
4188 // the benefit of being both really simple and much better than a libcall.
4189 SDValue Res; // Logically starts equal to 1.0
4190 SDValue CurSquare = LHS;
4191 // TODO: Intrinsics should have fast-math-flags that propagate to these
4196 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare);
4198 Res = CurSquare; // 1.0*CurSquare.
4201 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(),
4202 CurSquare, CurSquare);
4206 // If the original was negative, invert the result, producing 1/(x*x*x).
4207 if (RHSC->getSExtValue() < 0)
4208 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(),
4209 DAG.getConstantFP(1.0, DL, LHS.getValueType()), Res);
4214 // Otherwise, expand to a libcall.
4215 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS);
4218 // getUnderlyingArgReg - Find underlying register used for a truncated or
4219 // bitcasted argument.
4220 static unsigned getUnderlyingArgReg(const SDValue &N) {
4221 switch (N.getOpcode()) {
4222 case ISD::CopyFromReg:
4223 return cast<RegisterSDNode>(N.getOperand(1))->getReg();
4225 case ISD::AssertZext:
4226 case ISD::AssertSext:
4228 return getUnderlyingArgReg(N.getOperand(0));
4234 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function
4235 /// argument, create the corresponding DBG_VALUE machine instruction for it now.
4236 /// At the end of instruction selection, they will be inserted to the entry BB.
4237 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
4238 const Value *V, DILocalVariable *Variable, DIExpression *Expr,
4239 DILocation *DL, int64_t Offset, bool IsIndirect, const SDValue &N) {
4240 const Argument *Arg = dyn_cast<Argument>(V);
4244 MachineFunction &MF = DAG.getMachineFunction();
4245 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
4247 // Ignore inlined function arguments here.
4249 // FIXME: Should we be checking DL->inlinedAt() to determine this?
4250 if (!Variable->getScope()->getSubprogram()->describes(MF.getFunction()))
4253 Optional<MachineOperand> Op;
4254 // Some arguments' frame index is recorded during argument lowering.
4255 if (int FI = FuncInfo.getArgumentFrameIndex(Arg))
4256 Op = MachineOperand::CreateFI(FI);
4258 if (!Op && N.getNode()) {
4259 unsigned Reg = getUnderlyingArgReg(N);
4260 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) {
4261 MachineRegisterInfo &RegInfo = MF.getRegInfo();
4262 unsigned PR = RegInfo.getLiveInPhysReg(Reg);
4267 Op = MachineOperand::CreateReg(Reg, false);
4271 // Check if ValueMap has reg number.
4272 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V);
4273 if (VMI != FuncInfo.ValueMap.end())
4274 Op = MachineOperand::CreateReg(VMI->second, false);
4277 if (!Op && N.getNode())
4278 // Check if frame index is available.
4279 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode()))
4280 if (FrameIndexSDNode *FINode =
4281 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
4282 Op = MachineOperand::CreateFI(FINode->getIndex());
4287 assert(Variable->isValidLocationForIntrinsic(DL) &&
4288 "Expected inlined-at fields to agree");
4290 FuncInfo.ArgDbgValues.push_back(
4291 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
4292 Op->getReg(), Offset, Variable, Expr));
4294 FuncInfo.ArgDbgValues.push_back(
4295 BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE))
4298 .addMetadata(Variable)
4299 .addMetadata(Expr));
4304 // VisualStudio defines setjmp as _setjmp
4305 #if defined(_MSC_VER) && defined(setjmp) && \
4306 !defined(setjmp_undefined_for_msvc)
4307 # pragma push_macro("setjmp")
4309 # define setjmp_undefined_for_msvc
4312 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If
4313 /// we want to emit this as a call to a named external function, return the name
4314 /// otherwise lower it and return null.
4316 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
4317 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4318 SDLoc sdl = getCurSDLoc();
4319 DebugLoc dl = getCurDebugLoc();
4322 switch (Intrinsic) {
4324 // By default, turn this into a target intrinsic node.
4325 visitTargetIntrinsic(I, Intrinsic);
4327 case Intrinsic::vastart: visitVAStart(I); return nullptr;
4328 case Intrinsic::vaend: visitVAEnd(I); return nullptr;
4329 case Intrinsic::vacopy: visitVACopy(I); return nullptr;
4330 case Intrinsic::returnaddress:
4331 setValue(&I, DAG.getNode(ISD::RETURNADDR, sdl,
4332 TLI.getPointerTy(DAG.getDataLayout()),
4333 getValue(I.getArgOperand(0))));
4335 case Intrinsic::frameaddress:
4336 setValue(&I, DAG.getNode(ISD::FRAMEADDR, sdl,
4337 TLI.getPointerTy(DAG.getDataLayout()),
4338 getValue(I.getArgOperand(0))));
4340 case Intrinsic::read_register: {
4341 Value *Reg = I.getArgOperand(0);
4342 SDValue Chain = getRoot();
4344 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4345 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4346 Res = DAG.getNode(ISD::READ_REGISTER, sdl,
4347 DAG.getVTList(VT, MVT::Other), Chain, RegName);
4349 DAG.setRoot(Res.getValue(1));
4352 case Intrinsic::write_register: {
4353 Value *Reg = I.getArgOperand(0);
4354 Value *RegValue = I.getArgOperand(1);
4355 SDValue Chain = getRoot();
4357 DAG.getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
4358 DAG.setRoot(DAG.getNode(ISD::WRITE_REGISTER, sdl, MVT::Other, Chain,
4359 RegName, getValue(RegValue)));
4362 case Intrinsic::setjmp:
4363 return &"_setjmp"[!TLI.usesUnderscoreSetJmp()];
4364 case Intrinsic::longjmp:
4365 return &"_longjmp"[!TLI.usesUnderscoreLongJmp()];
4366 case Intrinsic::memcpy: {
4367 // FIXME: this definition of "user defined address space" is x86-specific
4368 // Assert for address < 256 since we support only user defined address
4370 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4372 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4374 "Unknown address space");
4375 SDValue Op1 = getValue(I.getArgOperand(0));
4376 SDValue Op2 = getValue(I.getArgOperand(1));
4377 SDValue Op3 = getValue(I.getArgOperand(2));
4378 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4380 Align = 1; // @llvm.memcpy defines 0 and 1 to both mean no alignment.
4381 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4382 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4383 SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4385 MachinePointerInfo(I.getArgOperand(0)),
4386 MachinePointerInfo(I.getArgOperand(1)));
4387 updateDAGForMaybeTailCall(MC);
4390 case Intrinsic::memset: {
4391 // FIXME: this definition of "user defined address space" is x86-specific
4392 // Assert for address < 256 since we support only user defined address
4394 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4396 "Unknown address space");
4397 SDValue Op1 = getValue(I.getArgOperand(0));
4398 SDValue Op2 = getValue(I.getArgOperand(1));
4399 SDValue Op3 = getValue(I.getArgOperand(2));
4400 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4402 Align = 1; // @llvm.memset defines 0 and 1 to both mean no alignment.
4403 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4404 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4405 SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4406 isTC, MachinePointerInfo(I.getArgOperand(0)));
4407 updateDAGForMaybeTailCall(MS);
4410 case Intrinsic::memmove: {
4411 // FIXME: this definition of "user defined address space" is x86-specific
4412 // Assert for address < 256 since we support only user defined address
4414 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace()
4416 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace()
4418 "Unknown address space");
4419 SDValue Op1 = getValue(I.getArgOperand(0));
4420 SDValue Op2 = getValue(I.getArgOperand(1));
4421 SDValue Op3 = getValue(I.getArgOperand(2));
4422 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue();
4424 Align = 1; // @llvm.memmove defines 0 and 1 to both mean no alignment.
4425 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue();
4426 bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
4427 SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
4428 isTC, MachinePointerInfo(I.getArgOperand(0)),
4429 MachinePointerInfo(I.getArgOperand(1)));
4430 updateDAGForMaybeTailCall(MM);
4433 case Intrinsic::dbg_declare: {
4434 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I);
4435 DILocalVariable *Variable = DI.getVariable();
4436 DIExpression *Expression = DI.getExpression();
4437 const Value *Address = DI.getAddress();
4438 assert(Variable && "Missing variable");
4440 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4444 // Check if address has undef value.
4445 if (isa<UndefValue>(Address) ||
4446 (Address->use_empty() && !isa<Argument>(Address))) {
4447 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4451 SDValue &N = NodeMap[Address];
4452 if (!N.getNode() && isa<Argument>(Address))
4453 // Check unused arguments map.
4454 N = UnusedArgNodeMap[Address];
4457 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
4458 Address = BCI->getOperand(0);
4459 // Parameters are handled specially.
4460 bool isParameter = Variable->isParameter() || isa<Argument>(Address);
4462 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
4464 if (isParameter && !AI) {
4465 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode());
4467 // Byval parameter. We have a frame index at this point.
4468 SDV = DAG.getFrameIndexDbgValue(
4469 Variable, Expression, FINode->getIndex(), 0, dl, SDNodeOrder);
4471 // Address is an argument, so try to emit its dbg value using
4472 // virtual register info from the FuncInfo.ValueMap.
4473 EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4478 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4479 true, 0, dl, SDNodeOrder);
4481 DAG.AddDbgValue(SDV, N.getNode(), isParameter);
4483 // If Address is an argument then try to emit its dbg value using
4484 // virtual register info from the FuncInfo.ValueMap.
4485 if (!EmitFuncArgumentDbgValue(Address, Variable, Expression, dl, 0, false,
4487 // If variable is pinned by a alloca in dominating bb then
4488 // use StaticAllocaMap.
4489 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
4490 if (AI->getParent() != DI.getParent()) {
4491 DenseMap<const AllocaInst*, int>::iterator SI =
4492 FuncInfo.StaticAllocaMap.find(AI);
4493 if (SI != FuncInfo.StaticAllocaMap.end()) {
4494 SDV = DAG.getFrameIndexDbgValue(Variable, Expression, SI->second,
4495 0, dl, SDNodeOrder);
4496 DAG.AddDbgValue(SDV, nullptr, false);
4501 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4506 case Intrinsic::dbg_value: {
4507 const DbgValueInst &DI = cast<DbgValueInst>(I);
4508 assert(DI.getVariable() && "Missing variable");
4510 DILocalVariable *Variable = DI.getVariable();
4511 DIExpression *Expression = DI.getExpression();
4512 uint64_t Offset = DI.getOffset();
4513 const Value *V = DI.getValue();
4518 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
4519 SDV = DAG.getConstantDbgValue(Variable, Expression, V, Offset, dl,
4521 DAG.AddDbgValue(SDV, nullptr, false);
4523 // Do not use getValue() in here; we don't want to generate code at
4524 // this point if it hasn't been done yet.
4525 SDValue N = NodeMap[V];
4526 if (!N.getNode() && isa<Argument>(V))
4527 // Check unused arguments map.
4528 N = UnusedArgNodeMap[V];
4530 // A dbg.value for an alloca is always indirect.
4531 bool IsIndirect = isa<AllocaInst>(V) || Offset != 0;
4532 if (!EmitFuncArgumentDbgValue(V, Variable, Expression, dl, Offset,
4534 SDV = DAG.getDbgValue(Variable, Expression, N.getNode(), N.getResNo(),
4535 IsIndirect, Offset, dl, SDNodeOrder);
4536 DAG.AddDbgValue(SDV, N.getNode(), false);
4538 } else if (!V->use_empty() ) {
4539 // Do not call getValue(V) yet, as we don't want to generate code.
4540 // Remember it for later.
4541 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder);
4542 DanglingDebugInfoMap[V] = DDI;
4544 // We may expand this to cover more cases. One case where we have no
4545 // data available is an unreferenced parameter.
4546 DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
4550 // Build a debug info table entry.
4551 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V))
4552 V = BCI->getOperand(0);
4553 const AllocaInst *AI = dyn_cast<AllocaInst>(V);
4554 // Don't handle byval struct arguments or VLAs, for example.
4556 DEBUG(dbgs() << "Dropping debug location info for:\n " << DI << "\n");
4557 DEBUG(dbgs() << " Last seen at:\n " << *V << "\n");
4560 DenseMap<const AllocaInst*, int>::iterator SI =
4561 FuncInfo.StaticAllocaMap.find(AI);
4562 if (SI == FuncInfo.StaticAllocaMap.end())
4563 return nullptr; // VLAs.
4567 case Intrinsic::eh_typeid_for: {
4568 // Find the type id for the given typeinfo.
4569 GlobalValue *GV = ExtractTypeInfo(I.getArgOperand(0));
4570 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV);
4571 Res = DAG.getConstant(TypeID, sdl, MVT::i32);
4576 case Intrinsic::eh_return_i32:
4577 case Intrinsic::eh_return_i64:
4578 DAG.getMachineFunction().getMMI().setCallsEHReturn(true);
4579 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, sdl,
4582 getValue(I.getArgOperand(0)),
4583 getValue(I.getArgOperand(1))));
4585 case Intrinsic::eh_unwind_init:
4586 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true);
4588 case Intrinsic::eh_dwarf_cfa: {
4589 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), sdl,
4590 TLI.getPointerTy(DAG.getDataLayout()));
4591 SDValue Offset = DAG.getNode(ISD::ADD, sdl,
4592 CfaArg.getValueType(),
4593 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, sdl,
4594 CfaArg.getValueType()),
4596 SDValue FA = DAG.getNode(
4597 ISD::FRAMEADDR, sdl, TLI.getPointerTy(DAG.getDataLayout()),
4598 DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
4599 setValue(&I, DAG.getNode(ISD::ADD, sdl, FA.getValueType(),
4603 case Intrinsic::eh_sjlj_callsite: {
4604 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
4605 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0));
4606 assert(CI && "Non-constant call site value in eh.sjlj.callsite!");
4607 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!");
4609 MMI.setCurrentCallSite(CI->getZExtValue());
4612 case Intrinsic::eh_sjlj_functioncontext: {
4613 // Get and store the index of the function context.
4614 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4616 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts());
4617 int FI = FuncInfo.StaticAllocaMap[FnCtx];
4618 MFI->setFunctionContextIndex(FI);
4621 case Intrinsic::eh_sjlj_setjmp: {
4624 Ops[1] = getValue(I.getArgOperand(0));
4625 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, sdl,
4626 DAG.getVTList(MVT::i32, MVT::Other), Ops);
4627 setValue(&I, Op.getValue(0));
4628 DAG.setRoot(Op.getValue(1));
4631 case Intrinsic::eh_sjlj_longjmp: {
4632 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, sdl, MVT::Other,
4633 getRoot(), getValue(I.getArgOperand(0))));
4636 case Intrinsic::eh_sjlj_setup_dispatch: {
4637 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_SETUP_DISPATCH, sdl, MVT::Other,
4642 case Intrinsic::masked_gather:
4643 visitMaskedGather(I);
4645 case Intrinsic::masked_load:
4648 case Intrinsic::masked_scatter:
4649 visitMaskedScatter(I);
4651 case Intrinsic::masked_store:
4652 visitMaskedStore(I);
4654 case Intrinsic::x86_mmx_pslli_w:
4655 case Intrinsic::x86_mmx_pslli_d:
4656 case Intrinsic::x86_mmx_pslli_q:
4657 case Intrinsic::x86_mmx_psrli_w:
4658 case Intrinsic::x86_mmx_psrli_d:
4659 case Intrinsic::x86_mmx_psrli_q:
4660 case Intrinsic::x86_mmx_psrai_w:
4661 case Intrinsic::x86_mmx_psrai_d: {
4662 SDValue ShAmt = getValue(I.getArgOperand(1));
4663 if (isa<ConstantSDNode>(ShAmt)) {
4664 visitTargetIntrinsic(I, Intrinsic);
4667 unsigned NewIntrinsic = 0;
4668 EVT ShAmtVT = MVT::v2i32;
4669 switch (Intrinsic) {
4670 case Intrinsic::x86_mmx_pslli_w:
4671 NewIntrinsic = Intrinsic::x86_mmx_psll_w;
4673 case Intrinsic::x86_mmx_pslli_d:
4674 NewIntrinsic = Intrinsic::x86_mmx_psll_d;
4676 case Intrinsic::x86_mmx_pslli_q:
4677 NewIntrinsic = Intrinsic::x86_mmx_psll_q;
4679 case Intrinsic::x86_mmx_psrli_w:
4680 NewIntrinsic = Intrinsic::x86_mmx_psrl_w;
4682 case Intrinsic::x86_mmx_psrli_d:
4683 NewIntrinsic = Intrinsic::x86_mmx_psrl_d;
4685 case Intrinsic::x86_mmx_psrli_q:
4686 NewIntrinsic = Intrinsic::x86_mmx_psrl_q;
4688 case Intrinsic::x86_mmx_psrai_w:
4689 NewIntrinsic = Intrinsic::x86_mmx_psra_w;
4691 case Intrinsic::x86_mmx_psrai_d:
4692 NewIntrinsic = Intrinsic::x86_mmx_psra_d;
4694 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4697 // The vector shift intrinsics with scalars uses 32b shift amounts but
4698 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
4700 // We must do this early because v2i32 is not a legal type.
4703 ShOps[1] = DAG.getConstant(0, sdl, MVT::i32);
4704 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, sdl, ShAmtVT, ShOps);
4705 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4706 ShAmt = DAG.getNode(ISD::BITCAST, sdl, DestVT, ShAmt);
4707 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, sdl, DestVT,
4708 DAG.getConstant(NewIntrinsic, sdl, MVT::i32),
4709 getValue(I.getArgOperand(0)), ShAmt);
4713 case Intrinsic::convertff:
4714 case Intrinsic::convertfsi:
4715 case Intrinsic::convertfui:
4716 case Intrinsic::convertsif:
4717 case Intrinsic::convertuif:
4718 case Intrinsic::convertss:
4719 case Intrinsic::convertsu:
4720 case Intrinsic::convertus:
4721 case Intrinsic::convertuu: {
4722 ISD::CvtCode Code = ISD::CVT_INVALID;
4723 switch (Intrinsic) {
4724 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4725 case Intrinsic::convertff: Code = ISD::CVT_FF; break;
4726 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break;
4727 case Intrinsic::convertfui: Code = ISD::CVT_FU; break;
4728 case Intrinsic::convertsif: Code = ISD::CVT_SF; break;
4729 case Intrinsic::convertuif: Code = ISD::CVT_UF; break;
4730 case Intrinsic::convertss: Code = ISD::CVT_SS; break;
4731 case Intrinsic::convertsu: Code = ISD::CVT_SU; break;
4732 case Intrinsic::convertus: Code = ISD::CVT_US; break;
4733 case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
4735 EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4736 const Value *Op1 = I.getArgOperand(0);
4737 Res = DAG.getConvertRndSat(DestVT, sdl, getValue(Op1),
4738 DAG.getValueType(DestVT),
4739 DAG.getValueType(getValue(Op1).getValueType()),
4740 getValue(I.getArgOperand(1)),
4741 getValue(I.getArgOperand(2)),
4746 case Intrinsic::powi:
4747 setValue(&I, ExpandPowI(sdl, getValue(I.getArgOperand(0)),
4748 getValue(I.getArgOperand(1)), DAG));
4750 case Intrinsic::log:
4751 setValue(&I, expandLog(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4753 case Intrinsic::log2:
4754 setValue(&I, expandLog2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4756 case Intrinsic::log10:
4757 setValue(&I, expandLog10(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4759 case Intrinsic::exp:
4760 setValue(&I, expandExp(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4762 case Intrinsic::exp2:
4763 setValue(&I, expandExp2(sdl, getValue(I.getArgOperand(0)), DAG, TLI));
4765 case Intrinsic::pow:
4766 setValue(&I, expandPow(sdl, getValue(I.getArgOperand(0)),
4767 getValue(I.getArgOperand(1)), DAG, TLI));
4769 case Intrinsic::sqrt:
4770 case Intrinsic::fabs:
4771 case Intrinsic::sin:
4772 case Intrinsic::cos:
4773 case Intrinsic::floor:
4774 case Intrinsic::ceil:
4775 case Intrinsic::trunc:
4776 case Intrinsic::rint:
4777 case Intrinsic::nearbyint:
4778 case Intrinsic::round: {
4780 switch (Intrinsic) {
4781 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
4782 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
4783 case Intrinsic::fabs: Opcode = ISD::FABS; break;
4784 case Intrinsic::sin: Opcode = ISD::FSIN; break;
4785 case Intrinsic::cos: Opcode = ISD::FCOS; break;
4786 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
4787 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
4788 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
4789 case Intrinsic::rint: Opcode = ISD::FRINT; break;
4790 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
4791 case Intrinsic::round: Opcode = ISD::FROUND; break;
4794 setValue(&I, DAG.getNode(Opcode, sdl,
4795 getValue(I.getArgOperand(0)).getValueType(),
4796 getValue(I.getArgOperand(0))));
4799 case Intrinsic::minnum:
4800 setValue(&I, DAG.getNode(ISD::FMINNUM, sdl,
4801 getValue(I.getArgOperand(0)).getValueType(),
4802 getValue(I.getArgOperand(0)),
4803 getValue(I.getArgOperand(1))));
4805 case Intrinsic::maxnum:
4806 setValue(&I, DAG.getNode(ISD::FMAXNUM, sdl,
4807 getValue(I.getArgOperand(0)).getValueType(),
4808 getValue(I.getArgOperand(0)),
4809 getValue(I.getArgOperand(1))));
4811 case Intrinsic::copysign:
4812 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, sdl,
4813 getValue(I.getArgOperand(0)).getValueType(),
4814 getValue(I.getArgOperand(0)),
4815 getValue(I.getArgOperand(1))));
4817 case Intrinsic::fma:
4818 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4819 getValue(I.getArgOperand(0)).getValueType(),
4820 getValue(I.getArgOperand(0)),
4821 getValue(I.getArgOperand(1)),
4822 getValue(I.getArgOperand(2))));
4824 case Intrinsic::fmuladd: {
4825 EVT VT = TLI.getValueType(DAG.getDataLayout(), I.getType());
4826 if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
4827 TLI.isFMAFasterThanFMulAndFAdd(VT)) {
4828 setValue(&I, DAG.getNode(ISD::FMA, sdl,
4829 getValue(I.getArgOperand(0)).getValueType(),
4830 getValue(I.getArgOperand(0)),
4831 getValue(I.getArgOperand(1)),
4832 getValue(I.getArgOperand(2))));
4834 // TODO: Intrinsic calls should have fast-math-flags.
4835 SDValue Mul = DAG.getNode(ISD::FMUL, sdl,
4836 getValue(I.getArgOperand(0)).getValueType(),
4837 getValue(I.getArgOperand(0)),
4838 getValue(I.getArgOperand(1)));
4839 SDValue Add = DAG.getNode(ISD::FADD, sdl,
4840 getValue(I.getArgOperand(0)).getValueType(),
4842 getValue(I.getArgOperand(2)));
4847 case Intrinsic::convert_to_fp16:
4848 setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
4849 DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
4850 getValue(I.getArgOperand(0)),
4851 DAG.getTargetConstant(0, sdl,
4854 case Intrinsic::convert_from_fp16:
4855 setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
4856 TLI.getValueType(DAG.getDataLayout(), I.getType()),
4857 DAG.getNode(ISD::BITCAST, sdl, MVT::f16,
4858 getValue(I.getArgOperand(0)))));
4860 case Intrinsic::pcmarker: {
4861 SDValue Tmp = getValue(I.getArgOperand(0));
4862 DAG.setRoot(DAG.getNode(ISD::PCMARKER, sdl, MVT::Other, getRoot(), Tmp));
4865 case Intrinsic::readcyclecounter: {
4866 SDValue Op = getRoot();
4867 Res = DAG.getNode(ISD::READCYCLECOUNTER, sdl,
4868 DAG.getVTList(MVT::i64, MVT::Other), Op);
4870 DAG.setRoot(Res.getValue(1));
4873 case Intrinsic::bitreverse:
4874 setValue(&I, DAG.getNode(ISD::BITREVERSE, sdl,
4875 getValue(I.getArgOperand(0)).getValueType(),
4876 getValue(I.getArgOperand(0))));
4878 case Intrinsic::bswap:
4879 setValue(&I, DAG.getNode(ISD::BSWAP, sdl,
4880 getValue(I.getArgOperand(0)).getValueType(),
4881 getValue(I.getArgOperand(0))));
4883 case Intrinsic::uabsdiff:
4884 setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,
4885 getValue(I.getArgOperand(0)).getValueType(),
4886 getValue(I.getArgOperand(0)),
4887 getValue(I.getArgOperand(1))));
4889 case Intrinsic::sabsdiff:
4890 setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,
4891 getValue(I.getArgOperand(0)).getValueType(),
4892 getValue(I.getArgOperand(0)),
4893 getValue(I.getArgOperand(1))));
4895 case Intrinsic::cttz: {
4896 SDValue Arg = getValue(I.getArgOperand(0));
4897 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4898 EVT Ty = Arg.getValueType();
4899 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTTZ : ISD::CTTZ_ZERO_UNDEF,
4903 case Intrinsic::ctlz: {
4904 SDValue Arg = getValue(I.getArgOperand(0));
4905 ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));
4906 EVT Ty = Arg.getValueType();
4907 setValue(&I, DAG.getNode(CI->isZero() ? ISD::CTLZ : ISD::CTLZ_ZERO_UNDEF,
4911 case Intrinsic::ctpop: {
4912 SDValue Arg = getValue(I.getArgOperand(0));
4913 EVT Ty = Arg.getValueType();
4914 setValue(&I, DAG.getNode(ISD::CTPOP, sdl, Ty, Arg));
4917 case Intrinsic::stacksave: {
4918 SDValue Op = getRoot();
4920 ISD::STACKSAVE, sdl,
4921 DAG.getVTList(TLI.getPointerTy(DAG.getDataLayout()), MVT::Other), Op);
4923 DAG.setRoot(Res.getValue(1));
4926 case Intrinsic::stackrestore: {
4927 Res = getValue(I.getArgOperand(0));
4928 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, sdl, MVT::Other, getRoot(), Res));
4931 case Intrinsic::stackprotector: {
4932 // Emit code into the DAG to store the stack guard onto the stack.
4933 MachineFunction &MF = DAG.getMachineFunction();
4934 MachineFrameInfo *MFI = MF.getFrameInfo();
4935 EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
4936 SDValue Src, Chain = getRoot();
4937 const Value *Ptr = cast<LoadInst>(I.getArgOperand(0))->getPointerOperand();
4938 const GlobalVariable *GV = dyn_cast<GlobalVariable>(Ptr);
4940 // See if Ptr is a bitcast. If it is, look through it and see if we can get
4941 // global variable __stack_chk_guard.
4943 if (const Operator *BC = dyn_cast<Operator>(Ptr))
4944 if (BC->getOpcode() == Instruction::BitCast)
4945 GV = dyn_cast<GlobalVariable>(BC->getOperand(0));
4947 if (GV && TLI.useLoadStackGuardNode()) {
4948 // Emit a LOAD_STACK_GUARD node.
4949 MachineSDNode *Node = DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD,
4951 MachinePointerInfo MPInfo(GV);
4952 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
4953 unsigned Flags = MachineMemOperand::MOLoad |
4954 MachineMemOperand::MOInvariant;
4955 *MemRefs = MF.getMachineMemOperand(MPInfo, Flags,
4956 PtrTy.getSizeInBits() / 8,
4957 DAG.getEVTAlignment(PtrTy));
4958 Node->setMemRefs(MemRefs, MemRefs + 1);
4960 // Copy the guard value to a virtual register so that it can be
4961 // retrieved in the epilogue.
4962 Src = SDValue(Node, 0);
4963 const TargetRegisterClass *RC =
4964 TLI.getRegClassFor(Src.getSimpleValueType());
4965 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
4967 SPDescriptor.setGuardReg(Reg);
4968 Chain = DAG.getCopyToReg(Chain, sdl, Reg, Src);
4970 Src = getValue(I.getArgOperand(0)); // The guard's value.
4973 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1));
4975 int FI = FuncInfo.StaticAllocaMap[Slot];
4976 MFI->setStackProtectorIndex(FI);
4978 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4980 // Store the stack protector onto the stack.
4981 Res = DAG.getStore(Chain, sdl, Src, FIN, MachinePointerInfo::getFixedStack(
4982 DAG.getMachineFunction(), FI),
4988 case Intrinsic::objectsize: {
4989 // If we don't know by now, we're never going to know.
4990 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1));
4992 assert(CI && "Non-constant type in __builtin_object_size?");
4994 SDValue Arg = getValue(I.getCalledValue());
4995 EVT Ty = Arg.getValueType();
4998 Res = DAG.getConstant(-1ULL, sdl, Ty);
5000 Res = DAG.getConstant(0, sdl, Ty);
5005 case Intrinsic::annotation:
5006 case Intrinsic::ptr_annotation:
5007 // Drop the intrinsic, but forward the value
5008 setValue(&I, getValue(I.getOperand(0)));
5010 case Intrinsic::assume:
5011 case Intrinsic::var_annotation:
5012 // Discard annotate attributes and assumptions
5015 case Intrinsic::init_trampoline: {
5016 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts());
5020 Ops[1] = getValue(I.getArgOperand(0));
5021 Ops[2] = getValue(I.getArgOperand(1));
5022 Ops[3] = getValue(I.getArgOperand(2));
5023 Ops[4] = DAG.getSrcValue(I.getArgOperand(0));
5024 Ops[5] = DAG.getSrcValue(F);
5026 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, sdl, MVT::Other, Ops);
5031 case Intrinsic::adjust_trampoline: {
5032 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, sdl,
5033 TLI.getPointerTy(DAG.getDataLayout()),
5034 getValue(I.getArgOperand(0))));
5037 case Intrinsic::gcroot:
5039 const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
5040 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1));
5042 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode());
5043 GFI->addStackRoot(FI->getIndex(), TypeMap);
5046 case Intrinsic::gcread:
5047 case Intrinsic::gcwrite:
5048 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!");
5049 case Intrinsic::flt_rounds:
5050 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, sdl, MVT::i32));
5053 case Intrinsic::expect: {
5054 // Just replace __builtin_expect(exp, c) with EXP.
5055 setValue(&I, getValue(I.getArgOperand(0)));
5059 case Intrinsic::debugtrap:
5060 case Intrinsic::trap: {
5061 StringRef TrapFuncName =
5063 .getAttribute(AttributeSet::FunctionIndex, "trap-func-name")
5064 .getValueAsString();
5065 if (TrapFuncName.empty()) {
5066 ISD::NodeType Op = (Intrinsic == Intrinsic::trap) ?
5067 ISD::TRAP : ISD::DEBUGTRAP;
5068 DAG.setRoot(DAG.getNode(Op, sdl,MVT::Other, getRoot()));
5071 TargetLowering::ArgListTy Args;
5073 TargetLowering::CallLoweringInfo CLI(DAG);
5074 CLI.setDebugLoc(sdl).setChain(getRoot()).setCallee(
5075 CallingConv::C, I.getType(),
5076 DAG.getExternalSymbol(TrapFuncName.data(),
5077 TLI.getPointerTy(DAG.getDataLayout())),
5078 std::move(Args), 0);
5080 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5081 DAG.setRoot(Result.second);
5085 case Intrinsic::uadd_with_overflow:
5086 case Intrinsic::sadd_with_overflow:
5087 case Intrinsic::usub_with_overflow:
5088 case Intrinsic::ssub_with_overflow:
5089 case Intrinsic::umul_with_overflow:
5090 case Intrinsic::smul_with_overflow: {
5092 switch (Intrinsic) {
5093 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
5094 case Intrinsic::uadd_with_overflow: Op = ISD::UADDO; break;
5095 case Intrinsic::sadd_with_overflow: Op = ISD::SADDO; break;
5096 case Intrinsic::usub_with_overflow: Op = ISD::USUBO; break;
5097 case Intrinsic::ssub_with_overflow: Op = ISD::SSUBO; break;
5098 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break;
5099 case Intrinsic::smul_with_overflow: Op = ISD::SMULO; break;
5101 SDValue Op1 = getValue(I.getArgOperand(0));
5102 SDValue Op2 = getValue(I.getArgOperand(1));
5104 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5105 setValue(&I, DAG.getNode(Op, sdl, VTs, Op1, Op2));
5108 case Intrinsic::prefetch: {
5110 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5112 Ops[1] = getValue(I.getArgOperand(0));
5113 Ops[2] = getValue(I.getArgOperand(1));
5114 Ops[3] = getValue(I.getArgOperand(2));
5115 Ops[4] = getValue(I.getArgOperand(3));
5116 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, sdl,
5117 DAG.getVTList(MVT::Other), Ops,
5118 EVT::getIntegerVT(*Context, 8),
5119 MachinePointerInfo(I.getArgOperand(0)),
5121 false, /* volatile */
5123 rw==1)); /* write */
5126 case Intrinsic::lifetime_start:
5127 case Intrinsic::lifetime_end: {
5128 bool IsStart = (Intrinsic == Intrinsic::lifetime_start);
5129 // Stack coloring is not enabled in O0, discard region information.
5130 if (TM.getOptLevel() == CodeGenOpt::None)
5133 SmallVector<Value *, 4> Allocas;
5134 GetUnderlyingObjects(I.getArgOperand(1), Allocas, *DL);
5136 for (SmallVectorImpl<Value*>::iterator Object = Allocas.begin(),
5137 E = Allocas.end(); Object != E; ++Object) {
5138 AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(*Object);
5140 // Could not find an Alloca.
5141 if (!LifetimeObject)
5144 // First check that the Alloca is static, otherwise it won't have a
5145 // valid frame index.
5146 auto SI = FuncInfo.StaticAllocaMap.find(LifetimeObject);
5147 if (SI == FuncInfo.StaticAllocaMap.end())
5150 int FI = SI->second;
5155 DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()), true);
5156 unsigned Opcode = (IsStart ? ISD::LIFETIME_START : ISD::LIFETIME_END);
5158 Res = DAG.getNode(Opcode, sdl, MVT::Other, Ops);
5163 case Intrinsic::invariant_start:
5164 // Discard region information.
5165 setValue(&I, DAG.getUNDEF(TLI.getPointerTy(DAG.getDataLayout())));
5167 case Intrinsic::invariant_end:
5168 // Discard region information.
5170 case Intrinsic::stackprotectorcheck: {
5171 // Do not actually emit anything for this basic block. Instead we initialize
5172 // the stack protector descriptor and export the guard variable so we can
5173 // access it in FinishBasicBlock.
5174 const BasicBlock *BB = I.getParent();
5175 SPDescriptor.initialize(BB, FuncInfo.MBBMap[BB], I);
5176 ExportFromCurrentBlock(SPDescriptor.getGuard());
5178 // Flush our exports since we are going to process a terminator.
5179 (void)getControlRoot();
5182 case Intrinsic::clear_cache:
5183 return TLI.getClearCacheBuiltinName();
5184 case Intrinsic::donothing:
5187 case Intrinsic::experimental_stackmap: {
5191 case Intrinsic::experimental_patchpoint_void:
5192 case Intrinsic::experimental_patchpoint_i64: {
5193 visitPatchpoint(&I);
5196 case Intrinsic::experimental_gc_statepoint: {
5200 case Intrinsic::experimental_gc_result_int:
5201 case Intrinsic::experimental_gc_result_float:
5202 case Intrinsic::experimental_gc_result_ptr:
5203 case Intrinsic::experimental_gc_result: {
5207 case Intrinsic::experimental_gc_relocate: {
5211 case Intrinsic::instrprof_increment:
5212 llvm_unreachable("instrprof failed to lower an increment");
5214 case Intrinsic::localescape: {
5215 MachineFunction &MF = DAG.getMachineFunction();
5216 const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
5218 // Directly emit some LOCAL_ESCAPE machine instrs. Label assignment emission
5219 // is the same on all targets.
5220 for (unsigned Idx = 0, E = I.getNumArgOperands(); Idx < E; ++Idx) {
5221 Value *Arg = I.getArgOperand(Idx)->stripPointerCasts();
5222 if (isa<ConstantPointerNull>(Arg))
5223 continue; // Skip null pointers. They represent a hole in index space.
5224 AllocaInst *Slot = cast<AllocaInst>(Arg);
5225 assert(FuncInfo.StaticAllocaMap.count(Slot) &&
5226 "can only escape static allocas");
5227 int FI = FuncInfo.StaticAllocaMap[Slot];
5228 MCSymbol *FrameAllocSym =
5229 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5230 GlobalValue::getRealLinkageName(MF.getName()), Idx);
5231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, dl,
5232 TII->get(TargetOpcode::LOCAL_ESCAPE))
5233 .addSym(FrameAllocSym)
5240 case Intrinsic::localrecover: {
5241 // i8* @llvm.localrecover(i8* %fn, i8* %fp, i32 %idx)
5242 MachineFunction &MF = DAG.getMachineFunction();
5243 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout(), 0);
5245 // Get the symbol that defines the frame offset.
5246 auto *Fn = cast<Function>(I.getArgOperand(0)->stripPointerCasts());
5247 auto *Idx = cast<ConstantInt>(I.getArgOperand(2));
5248 unsigned IdxVal = unsigned(Idx->getLimitedValue(INT_MAX));
5249 MCSymbol *FrameAllocSym =
5250 MF.getMMI().getContext().getOrCreateFrameAllocSymbol(
5251 GlobalValue::getRealLinkageName(Fn->getName()), IdxVal);
5253 // Create a MCSymbol for the label to avoid any target lowering
5254 // that would make this PC relative.
5255 SDValue OffsetSym = DAG.getMCSymbol(FrameAllocSym, PtrVT);
5257 DAG.getNode(ISD::LOCAL_RECOVER, sdl, PtrVT, OffsetSym);
5259 // Add the offset to the FP.
5260 Value *FP = I.getArgOperand(1);
5261 SDValue FPVal = getValue(FP);
5262 SDValue Add = DAG.getNode(ISD::ADD, sdl, PtrVT, FPVal, OffsetVal);
5268 case Intrinsic::eh_exceptionpointer:
5269 case Intrinsic::eh_exceptioncode: {
5270 // Get the exception pointer vreg, copy from it, and resize it to fit.
5271 const auto *CPI = cast<CatchPadInst>(I.getArgOperand(0));
5272 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
5273 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
5274 unsigned VReg = FuncInfo.getCatchPadExceptionPointerVReg(CPI, PtrRC);
5276 DAG.getCopyFromReg(DAG.getEntryNode(), getCurSDLoc(), VReg, PtrVT);
5277 if (Intrinsic == Intrinsic::eh_exceptioncode)
5278 N = DAG.getZExtOrTrunc(N, getCurSDLoc(), MVT::i32);
5285 std::pair<SDValue, SDValue>
5286 SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
5287 const BasicBlock *EHPadBB) {
5288 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5289 MCSymbol *BeginLabel = nullptr;
5292 // Insert a label before the invoke call to mark the try range. This can be
5293 // used to detect deletion of the invoke via the MachineModuleInfo.
5294 BeginLabel = MMI.getContext().createTempSymbol();
5296 // For SjLj, keep track of which landing pads go with which invokes
5297 // so as to maintain the ordering of pads in the LSDA.
5298 unsigned CallSiteIndex = MMI.getCurrentCallSite();
5299 if (CallSiteIndex) {
5300 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex);
5301 LPadToCallSiteMap[FuncInfo.MBBMap[EHPadBB]].push_back(CallSiteIndex);
5303 // Now that the call site is handled, stop tracking it.
5304 MMI.setCurrentCallSite(0);
5307 // Both PendingLoads and PendingExports must be flushed here;
5308 // this call might not return.
5310 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getControlRoot(), BeginLabel));
5312 CLI.setChain(getRoot());
5314 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5315 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
5317 assert((CLI.IsTailCall || Result.second.getNode()) &&
5318 "Non-null chain expected with non-tail call!");
5319 assert((Result.second.getNode() || !Result.first.getNode()) &&
5320 "Null value expected with tail call!");
5322 if (!Result.second.getNode()) {
5323 // As a special case, a null chain means that a tail call has been emitted
5324 // and the DAG root is already updated.
5327 // Since there's no actual continuation from this block, nothing can be
5328 // relying on us setting vregs for them.
5329 PendingExports.clear();
5331 DAG.setRoot(Result.second);
5335 // Insert a label at the end of the invoke call to mark the try range. This
5336 // can be used to detect deletion of the invoke via the MachineModuleInfo.
5337 MCSymbol *EndLabel = MMI.getContext().createTempSymbol();
5338 DAG.setRoot(DAG.getEHLabel(getCurSDLoc(), getRoot(), EndLabel));
5340 // Inform MachineModuleInfo of range.
5341 if (MMI.hasEHFunclets()) {
5342 WinEHFuncInfo *EHInfo = DAG.getMachineFunction().getWinEHFuncInfo();
5343 EHInfo->addIPToStateRange(EHPadBB, BeginLabel, EndLabel);
5345 MMI.addInvoke(FuncInfo.MBBMap[EHPadBB], BeginLabel, EndLabel);
5352 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
5354 const BasicBlock *EHPadBB) {
5355 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
5356 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
5357 Type *RetTy = FTy->getReturnType();
5359 TargetLowering::ArgListTy Args;
5360 TargetLowering::ArgListEntry Entry;
5361 Args.reserve(CS.arg_size());
5363 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
5365 const Value *V = *i;
5368 if (V->getType()->isEmptyTy())
5371 SDValue ArgNode = getValue(V);
5372 Entry.Node = ArgNode; Entry.Ty = V->getType();
5374 // Skip the first return-type Attribute to get to params.
5375 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
5376 Args.push_back(Entry);
5378 // If we have an explicit sret argument that is an Instruction, (i.e., it
5379 // might point to function-local memory), we can't meaningfully tail-call.
5380 if (Entry.isSRet && isa<Instruction>(V))
5384 // Check if target-independent constraints permit a tail call here.
5385 // Target-dependent constraints are checked within TLI->LowerCallTo.
5386 if (isTailCall && !isInTailCallPosition(CS, DAG.getTarget()))
5389 TargetLowering::CallLoweringInfo CLI(DAG);
5390 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
5391 .setCallee(RetTy, FTy, Callee, std::move(Args), CS)
5392 .setTailCall(isTailCall);
5393 std::pair<SDValue, SDValue> Result = lowerInvokable(CLI, EHPadBB);
5395 if (Result.first.getNode())
5396 setValue(CS.getInstruction(), Result.first);
5399 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the
5400 /// value is equal or not-equal to zero.
5401 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) {
5402 for (const User *U : V->users()) {
5403 if (const ICmpInst *IC = dyn_cast<ICmpInst>(U))
5404 if (IC->isEquality())
5405 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1)))
5406 if (C->isNullValue())
5408 // Unknown instruction.
5414 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT,
5416 SelectionDAGBuilder &Builder) {
5418 // Check to see if this load can be trivially constant folded, e.g. if the
5419 // input is from a string literal.
5420 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
5421 // Cast pointer to the type we really want to load.
5422 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput),
5423 PointerType::getUnqual(LoadTy));
5425 if (const Constant *LoadCst = ConstantFoldLoadFromConstPtr(
5426 const_cast<Constant *>(LoadInput), *Builder.DL))
5427 return Builder.getValue(LoadCst);
5430 // Otherwise, we have to emit the load. If the pointer is to unfoldable but
5431 // still constant memory, the input chain can be the entry node.
5433 bool ConstantMemory = false;
5435 // Do not serialize (non-volatile) loads of constant memory with anything.
5436 if (Builder.AA->pointsToConstantMemory(PtrVal)) {
5437 Root = Builder.DAG.getEntryNode();
5438 ConstantMemory = true;
5440 // Do not serialize non-volatile loads against each other.
5441 Root = Builder.DAG.getRoot();
5444 SDValue Ptr = Builder.getValue(PtrVal);
5445 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurSDLoc(), Root,
5446 Ptr, MachinePointerInfo(PtrVal),
5448 false /*nontemporal*/,
5449 false /*isinvariant*/, 1 /* align=1 */);
5451 if (!ConstantMemory)
5452 Builder.PendingLoads.push_back(LoadVal.getValue(1));
5456 /// processIntegerCallValue - Record the value for an instruction that
5457 /// produces an integer result, converting the type where necessary.
5458 void SelectionDAGBuilder::processIntegerCallValue(const Instruction &I,
5461 EVT VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5464 Value = DAG.getSExtOrTrunc(Value, getCurSDLoc(), VT);
5466 Value = DAG.getZExtOrTrunc(Value, getCurSDLoc(), VT);
5467 setValue(&I, Value);
5470 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form.
5471 /// If so, return true and lower it, otherwise return false and it will be
5472 /// lowered like a normal call.
5473 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) {
5474 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t)
5475 if (I.getNumArgOperands() != 3)
5478 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1);
5479 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() ||
5480 !I.getArgOperand(2)->getType()->isIntegerTy() ||
5481 !I.getType()->isIntegerTy())
5484 const Value *Size = I.getArgOperand(2);
5485 const ConstantInt *CSize = dyn_cast<ConstantInt>(Size);
5486 if (CSize && CSize->getZExtValue() == 0) {
5487 EVT CallVT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(),
5489 setValue(&I, DAG.getConstant(0, getCurSDLoc(), CallVT));
5493 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5494 std::pair<SDValue, SDValue> Res =
5495 TSI.EmitTargetCodeForMemcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5496 getValue(LHS), getValue(RHS), getValue(Size),
5497 MachinePointerInfo(LHS),
5498 MachinePointerInfo(RHS));
5499 if (Res.first.getNode()) {
5500 processIntegerCallValue(I, Res.first, true);
5501 PendingLoads.push_back(Res.second);
5505 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0
5506 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0
5507 if (CSize && IsOnlyUsedInZeroEqualityComparison(&I)) {
5508 bool ActuallyDoIt = true;
5511 switch (CSize->getZExtValue()) {
5513 LoadVT = MVT::Other;
5515 ActuallyDoIt = false;
5519 LoadTy = Type::getInt16Ty(CSize->getContext());
5523 LoadTy = Type::getInt32Ty(CSize->getContext());
5527 LoadTy = Type::getInt64Ty(CSize->getContext());
5531 LoadVT = MVT::v4i32;
5532 LoadTy = Type::getInt32Ty(CSize->getContext());
5533 LoadTy = VectorType::get(LoadTy, 4);
5538 // This turns into unaligned loads. We only do this if the target natively
5539 // supports the MVT we'll be loading or if it is small enough (<= 4) that
5540 // we'll only produce a small number of byte loads.
5542 // Require that we can find a legal MVT, and only do this if the target
5543 // supports unaligned loads of that type. Expanding into byte loads would
5545 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5546 if (ActuallyDoIt && CSize->getZExtValue() > 4) {
5547 unsigned DstAS = LHS->getType()->getPointerAddressSpace();
5548 unsigned SrcAS = RHS->getType()->getPointerAddressSpace();
5549 // TODO: Handle 5 byte compare as 4-byte + 1 byte.
5550 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads.
5551 // TODO: Check alignment of src and dest ptrs.
5552 if (!TLI.isTypeLegal(LoadVT) ||
5553 !TLI.allowsMisalignedMemoryAccesses(LoadVT, SrcAS) ||
5554 !TLI.allowsMisalignedMemoryAccesses(LoadVT, DstAS))
5555 ActuallyDoIt = false;
5559 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this);
5560 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this);
5562 SDValue Res = DAG.getSetCC(getCurSDLoc(), MVT::i1, LHSVal, RHSVal,
5564 processIntegerCallValue(I, Res, false);
5573 /// visitMemChrCall -- See if we can lower a memchr call into an optimized
5574 /// form. If so, return true and lower it, otherwise return false and it
5575 /// will be lowered like a normal call.
5576 bool SelectionDAGBuilder::visitMemChrCall(const CallInst &I) {
5577 // Verify that the prototype makes sense. void *memchr(void *, int, size_t)
5578 if (I.getNumArgOperands() != 3)
5581 const Value *Src = I.getArgOperand(0);
5582 const Value *Char = I.getArgOperand(1);
5583 const Value *Length = I.getArgOperand(2);
5584 if (!Src->getType()->isPointerTy() ||
5585 !Char->getType()->isIntegerTy() ||
5586 !Length->getType()->isIntegerTy() ||
5587 !I.getType()->isPointerTy())
5590 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5591 std::pair<SDValue, SDValue> Res =
5592 TSI.EmitTargetCodeForMemchr(DAG, getCurSDLoc(), DAG.getRoot(),
5593 getValue(Src), getValue(Char), getValue(Length),
5594 MachinePointerInfo(Src));
5595 if (Res.first.getNode()) {
5596 setValue(&I, Res.first);
5597 PendingLoads.push_back(Res.second);
5604 /// visitStrCpyCall -- See if we can lower a strcpy or stpcpy call into an
5605 /// optimized form. If so, return true and lower it, otherwise return false
5606 /// and it will be lowered like a normal call.
5607 bool SelectionDAGBuilder::visitStrCpyCall(const CallInst &I, bool isStpcpy) {
5608 // Verify that the prototype makes sense. char *strcpy(char *, char *)
5609 if (I.getNumArgOperands() != 2)
5612 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5613 if (!Arg0->getType()->isPointerTy() ||
5614 !Arg1->getType()->isPointerTy() ||
5615 !I.getType()->isPointerTy())
5618 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5619 std::pair<SDValue, SDValue> Res =
5620 TSI.EmitTargetCodeForStrcpy(DAG, getCurSDLoc(), getRoot(),
5621 getValue(Arg0), getValue(Arg1),
5622 MachinePointerInfo(Arg0),
5623 MachinePointerInfo(Arg1), isStpcpy);
5624 if (Res.first.getNode()) {
5625 setValue(&I, Res.first);
5626 DAG.setRoot(Res.second);
5633 /// visitStrCmpCall - See if we can lower a call to strcmp in an optimized form.
5634 /// If so, return true and lower it, otherwise return false and it will be
5635 /// lowered like a normal call.
5636 bool SelectionDAGBuilder::visitStrCmpCall(const CallInst &I) {
5637 // Verify that the prototype makes sense. int strcmp(void*,void*)
5638 if (I.getNumArgOperands() != 2)
5641 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5642 if (!Arg0->getType()->isPointerTy() ||
5643 !Arg1->getType()->isPointerTy() ||
5644 !I.getType()->isIntegerTy())
5647 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5648 std::pair<SDValue, SDValue> Res =
5649 TSI.EmitTargetCodeForStrcmp(DAG, getCurSDLoc(), DAG.getRoot(),
5650 getValue(Arg0), getValue(Arg1),
5651 MachinePointerInfo(Arg0),
5652 MachinePointerInfo(Arg1));
5653 if (Res.first.getNode()) {
5654 processIntegerCallValue(I, Res.first, true);
5655 PendingLoads.push_back(Res.second);
5662 /// visitStrLenCall -- See if we can lower a strlen call into an optimized
5663 /// form. If so, return true and lower it, otherwise return false and it
5664 /// will be lowered like a normal call.
5665 bool SelectionDAGBuilder::visitStrLenCall(const CallInst &I) {
5666 // Verify that the prototype makes sense. size_t strlen(char *)
5667 if (I.getNumArgOperands() != 1)
5670 const Value *Arg0 = I.getArgOperand(0);
5671 if (!Arg0->getType()->isPointerTy() || !I.getType()->isIntegerTy())
5674 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5675 std::pair<SDValue, SDValue> Res =
5676 TSI.EmitTargetCodeForStrlen(DAG, getCurSDLoc(), DAG.getRoot(),
5677 getValue(Arg0), MachinePointerInfo(Arg0));
5678 if (Res.first.getNode()) {
5679 processIntegerCallValue(I, Res.first, false);
5680 PendingLoads.push_back(Res.second);
5687 /// visitStrNLenCall -- See if we can lower a strnlen call into an optimized
5688 /// form. If so, return true and lower it, otherwise return false and it
5689 /// will be lowered like a normal call.
5690 bool SelectionDAGBuilder::visitStrNLenCall(const CallInst &I) {
5691 // Verify that the prototype makes sense. size_t strnlen(char *, size_t)
5692 if (I.getNumArgOperands() != 2)
5695 const Value *Arg0 = I.getArgOperand(0), *Arg1 = I.getArgOperand(1);
5696 if (!Arg0->getType()->isPointerTy() ||
5697 !Arg1->getType()->isIntegerTy() ||
5698 !I.getType()->isIntegerTy())
5701 const TargetSelectionDAGInfo &TSI = DAG.getSelectionDAGInfo();
5702 std::pair<SDValue, SDValue> Res =
5703 TSI.EmitTargetCodeForStrnlen(DAG, getCurSDLoc(), DAG.getRoot(),
5704 getValue(Arg0), getValue(Arg1),
5705 MachinePointerInfo(Arg0));
5706 if (Res.first.getNode()) {
5707 processIntegerCallValue(I, Res.first, false);
5708 PendingLoads.push_back(Res.second);
5715 /// visitUnaryFloatCall - If a call instruction is a unary floating-point
5716 /// operation (as expected), translate it to an SDNode with the specified opcode
5717 /// and return true.
5718 bool SelectionDAGBuilder::visitUnaryFloatCall(const CallInst &I,
5720 // Sanity check that it really is a unary floating-point call.
5721 if (I.getNumArgOperands() != 1 ||
5722 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5723 I.getType() != I.getArgOperand(0)->getType() ||
5724 !I.onlyReadsMemory())
5727 SDValue Tmp = getValue(I.getArgOperand(0));
5728 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), Tmp.getValueType(), Tmp));
5732 /// visitBinaryFloatCall - If a call instruction is a binary floating-point
5733 /// operation (as expected), translate it to an SDNode with the specified opcode
5734 /// and return true.
5735 bool SelectionDAGBuilder::visitBinaryFloatCall(const CallInst &I,
5737 // Sanity check that it really is a binary floating-point call.
5738 if (I.getNumArgOperands() != 2 ||
5739 !I.getArgOperand(0)->getType()->isFloatingPointTy() ||
5740 I.getType() != I.getArgOperand(0)->getType() ||
5741 I.getType() != I.getArgOperand(1)->getType() ||
5742 !I.onlyReadsMemory())
5745 SDValue Tmp0 = getValue(I.getArgOperand(0));
5746 SDValue Tmp1 = getValue(I.getArgOperand(1));
5747 EVT VT = Tmp0.getValueType();
5748 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1));
5752 void SelectionDAGBuilder::visitCall(const CallInst &I) {
5753 // Handle inline assembly differently.
5754 if (isa<InlineAsm>(I.getCalledValue())) {
5759 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
5760 ComputeUsesVAFloatArgument(I, &MMI);
5762 const char *RenameFn = nullptr;
5763 if (Function *F = I.getCalledFunction()) {
5764 if (F->isDeclaration()) {
5765 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) {
5766 if (unsigned IID = II->getIntrinsicID(F)) {
5767 RenameFn = visitIntrinsicCall(I, IID);
5772 if (Intrinsic::ID IID = F->getIntrinsicID()) {
5773 RenameFn = visitIntrinsicCall(I, IID);
5779 // Check for well-known libc/libm calls. If the function is internal, it
5780 // can't be a library call.
5782 if (!F->hasLocalLinkage() && F->hasName() &&
5783 LibInfo->getLibFunc(F->getName(), Func) &&
5784 LibInfo->hasOptimizedCodeGen(Func)) {
5787 case LibFunc::copysign:
5788 case LibFunc::copysignf:
5789 case LibFunc::copysignl:
5790 if (I.getNumArgOperands() == 2 && // Basic sanity checks.
5791 I.getArgOperand(0)->getType()->isFloatingPointTy() &&
5792 I.getType() == I.getArgOperand(0)->getType() &&
5793 I.getType() == I.getArgOperand(1)->getType() &&
5794 I.onlyReadsMemory()) {
5795 SDValue LHS = getValue(I.getArgOperand(0));
5796 SDValue RHS = getValue(I.getArgOperand(1));
5797 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurSDLoc(),
5798 LHS.getValueType(), LHS, RHS));
5803 case LibFunc::fabsf:
5804 case LibFunc::fabsl:
5805 if (visitUnaryFloatCall(I, ISD::FABS))
5809 case LibFunc::fminf:
5810 case LibFunc::fminl:
5811 if (visitBinaryFloatCall(I, ISD::FMINNUM))
5815 case LibFunc::fmaxf:
5816 case LibFunc::fmaxl:
5817 if (visitBinaryFloatCall(I, ISD::FMAXNUM))
5823 if (visitUnaryFloatCall(I, ISD::FSIN))
5829 if (visitUnaryFloatCall(I, ISD::FCOS))
5833 case LibFunc::sqrtf:
5834 case LibFunc::sqrtl:
5835 case LibFunc::sqrt_finite:
5836 case LibFunc::sqrtf_finite:
5837 case LibFunc::sqrtl_finite:
5838 if (visitUnaryFloatCall(I, ISD::FSQRT))
5841 case LibFunc::floor:
5842 case LibFunc::floorf:
5843 case LibFunc::floorl:
5844 if (visitUnaryFloatCall(I, ISD::FFLOOR))
5847 case LibFunc::nearbyint:
5848 case LibFunc::nearbyintf:
5849 case LibFunc::nearbyintl:
5850 if (visitUnaryFloatCall(I, ISD::FNEARBYINT))
5854 case LibFunc::ceilf:
5855 case LibFunc::ceill:
5856 if (visitUnaryFloatCall(I, ISD::FCEIL))
5860 case LibFunc::rintf:
5861 case LibFunc::rintl:
5862 if (visitUnaryFloatCall(I, ISD::FRINT))
5865 case LibFunc::round:
5866 case LibFunc::roundf:
5867 case LibFunc::roundl:
5868 if (visitUnaryFloatCall(I, ISD::FROUND))
5871 case LibFunc::trunc:
5872 case LibFunc::truncf:
5873 case LibFunc::truncl:
5874 if (visitUnaryFloatCall(I, ISD::FTRUNC))
5878 case LibFunc::log2f:
5879 case LibFunc::log2l:
5880 if (visitUnaryFloatCall(I, ISD::FLOG2))
5884 case LibFunc::exp2f:
5885 case LibFunc::exp2l:
5886 if (visitUnaryFloatCall(I, ISD::FEXP2))
5889 case LibFunc::memcmp:
5890 if (visitMemCmpCall(I))
5893 case LibFunc::memchr:
5894 if (visitMemChrCall(I))
5897 case LibFunc::strcpy:
5898 if (visitStrCpyCall(I, false))
5901 case LibFunc::stpcpy:
5902 if (visitStrCpyCall(I, true))
5905 case LibFunc::strcmp:
5906 if (visitStrCmpCall(I))
5909 case LibFunc::strlen:
5910 if (visitStrLenCall(I))
5913 case LibFunc::strnlen:
5914 if (visitStrNLenCall(I))
5923 Callee = getValue(I.getCalledValue());
5925 Callee = DAG.getExternalSymbol(
5927 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()));
5929 // Check if we can potentially perform a tail call. More detailed checking is
5930 // be done within LowerCallTo, after more information about the call is known.
5931 LowerCallTo(&I, Callee, I.isTailCall());
5936 /// AsmOperandInfo - This contains information for each constraint that we are
5938 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo {
5940 /// CallOperand - If this is the result output operand or a clobber
5941 /// this is null, otherwise it is the incoming operand to the CallInst.
5942 /// This gets modified as the asm is processed.
5943 SDValue CallOperand;
5945 /// AssignedRegs - If this is a register or register class operand, this
5946 /// contains the set of register corresponding to the operand.
5947 RegsForValue AssignedRegs;
5949 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info)
5950 : TargetLowering::AsmOperandInfo(info), CallOperand(nullptr,0) {
5953 /// getCallOperandValEVT - Return the EVT of the Value* that this operand
5954 /// corresponds to. If there is no Value* for this operand, it returns
5956 EVT getCallOperandValEVT(LLVMContext &Context, const TargetLowering &TLI,
5957 const DataLayout &DL) const {
5958 if (!CallOperandVal) return MVT::Other;
5960 if (isa<BasicBlock>(CallOperandVal))
5961 return TLI.getPointerTy(DL);
5963 llvm::Type *OpTy = CallOperandVal->getType();
5965 // FIXME: code duplicated from TargetLowering::ParseConstraints().
5966 // If this is an indirect operand, the operand is a pointer to the
5969 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy);
5971 report_fatal_error("Indirect operand for inline asm not a pointer!");
5972 OpTy = PtrTy->getElementType();
5975 // Look for vector wrapped in a struct. e.g. { <16 x i8> }.
5976 if (StructType *STy = dyn_cast<StructType>(OpTy))
5977 if (STy->getNumElements() == 1)
5978 OpTy = STy->getElementType(0);
5980 // If OpTy is not a single value, it may be a struct/union that we
5981 // can tile with integers.
5982 if (!OpTy->isSingleValueType() && OpTy->isSized()) {
5983 unsigned BitSize = DL.getTypeSizeInBits(OpTy);
5992 OpTy = IntegerType::get(Context, BitSize);
5997 return TLI.getValueType(DL, OpTy, true);
6001 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector;
6003 } // end anonymous namespace
6005 /// GetRegistersForValue - Assign registers (virtual or physical) for the
6006 /// specified operand. We prefer to assign virtual registers, to allow the
6007 /// register allocator to handle the assignment process. However, if the asm
6008 /// uses features that we can't model on machineinstrs, we have SDISel do the
6009 /// allocation. This produces generally horrible, but correct, code.
6011 /// OpInfo describes the operand.
6013 static void GetRegistersForValue(SelectionDAG &DAG,
6014 const TargetLowering &TLI,
6016 SDISelAsmOperandInfo &OpInfo) {
6017 LLVMContext &Context = *DAG.getContext();
6019 MachineFunction &MF = DAG.getMachineFunction();
6020 SmallVector<unsigned, 4> Regs;
6022 // If this is a constraint for a single physreg, or a constraint for a
6023 // register class, find it.
6024 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
6025 TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
6026 OpInfo.ConstraintCode,
6027 OpInfo.ConstraintVT);
6029 unsigned NumRegs = 1;
6030 if (OpInfo.ConstraintVT != MVT::Other) {
6031 // If this is a FP input in an integer register (or visa versa) insert a bit
6032 // cast of the input value. More generally, handle any case where the input
6033 // value disagrees with the register class we plan to stick this in.
6034 if (OpInfo.Type == InlineAsm::isInput &&
6035 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
6036 // Try to convert to the first EVT that the reg class contains. If the
6037 // types are identical size, use a bitcast to convert (e.g. two differing
6039 MVT RegVT = *PhysReg.second->vt_begin();
6040 if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
6041 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6042 RegVT, OpInfo.CallOperand);
6043 OpInfo.ConstraintVT = RegVT;
6044 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
6045 // If the input is a FP value and we want it in FP registers, do a
6046 // bitcast to the corresponding integer type. This turns an f64 value
6047 // into i64, which can be passed with two i32 values on a 32-bit
6049 RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
6050 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
6051 RegVT, OpInfo.CallOperand);
6052 OpInfo.ConstraintVT = RegVT;
6056 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT);
6060 EVT ValueVT = OpInfo.ConstraintVT;
6062 // If this is a constraint for a specific physical register, like {r17},
6064 if (unsigned AssignedReg = PhysReg.first) {
6065 const TargetRegisterClass *RC = PhysReg.second;
6066 if (OpInfo.ConstraintVT == MVT::Other)
6067 ValueVT = *RC->vt_begin();
6069 // Get the actual register value type. This is important, because the user
6070 // may have asked for (e.g.) the AX register in i32 type. We need to
6071 // remember that AX is actually i16 to get the right extension.
6072 RegVT = *RC->vt_begin();
6074 // This is a explicit reference to a physical register.
6075 Regs.push_back(AssignedReg);
6077 // If this is an expanded reference, add the rest of the regs to Regs.
6079 TargetRegisterClass::iterator I = RC->begin();
6080 for (; *I != AssignedReg; ++I)
6081 assert(I != RC->end() && "Didn't find reg!");
6083 // Already added the first reg.
6085 for (; NumRegs; --NumRegs, ++I) {
6086 assert(I != RC->end() && "Ran out of registers to allocate!");
6091 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6095 // Otherwise, if this was a reference to an LLVM register class, create vregs
6096 // for this reference.
6097 if (const TargetRegisterClass *RC = PhysReg.second) {
6098 RegVT = *RC->vt_begin();
6099 if (OpInfo.ConstraintVT == MVT::Other)
6102 // Create the appropriate number of virtual registers.
6103 MachineRegisterInfo &RegInfo = MF.getRegInfo();
6104 for (; NumRegs; --NumRegs)
6105 Regs.push_back(RegInfo.createVirtualRegister(RC));
6107 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
6111 // Otherwise, we couldn't allocate enough registers for this.
6114 /// visitInlineAsm - Handle a call to an InlineAsm object.
6116 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
6117 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue());
6119 /// ConstraintOperands - Information about all of the constraints.
6120 SDISelAsmOperandInfoVector ConstraintOperands;
6122 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6123 TargetLowering::AsmOperandInfoVector TargetConstraints = TLI.ParseConstraints(
6124 DAG.getDataLayout(), DAG.getSubtarget().getRegisterInfo(), CS);
6126 bool hasMemory = false;
6128 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
6129 unsigned ResNo = 0; // ResNo - The result number of the next output.
6130 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6131 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i]));
6132 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
6134 MVT OpVT = MVT::Other;
6136 // Compute the value type for each operand.
6137 switch (OpInfo.Type) {
6138 case InlineAsm::isOutput:
6139 // Indirect outputs just consume an argument.
6140 if (OpInfo.isIndirect) {
6141 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6145 // The return value of the call is this value. As such, there is no
6146 // corresponding argument.
6147 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6148 if (StructType *STy = dyn_cast<StructType>(CS.getType())) {
6149 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(),
6150 STy->getElementType(ResNo));
6152 assert(ResNo == 0 && "Asm only has one result!");
6153 OpVT = TLI.getSimpleValueType(DAG.getDataLayout(), CS.getType());
6157 case InlineAsm::isInput:
6158 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++));
6160 case InlineAsm::isClobber:
6165 // If this is an input or an indirect output, process the call argument.
6166 // BasicBlocks are labels, currently appearing only in asm's.
6167 if (OpInfo.CallOperandVal) {
6168 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) {
6169 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]);
6171 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
6174 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
6175 DAG.getDataLayout()).getSimpleVT();
6178 OpInfo.ConstraintVT = OpVT;
6180 // Indirect operand accesses access memory.
6181 if (OpInfo.isIndirect)
6184 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) {
6185 TargetLowering::ConstraintType
6186 CType = TLI.getConstraintType(OpInfo.Codes[j]);
6187 if (CType == TargetLowering::C_Memory) {
6195 SDValue Chain, Flag;
6197 // We won't need to flush pending loads if this asm doesn't touch
6198 // memory and is nonvolatile.
6199 if (hasMemory || IA->hasSideEffects())
6202 Chain = DAG.getRoot();
6204 // Second pass over the constraints: compute which constraint option to use
6205 // and assign registers to constraints that want a specific physreg.
6206 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6207 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6209 // If this is an output operand with a matching input operand, look up the
6210 // matching input. If their types mismatch, e.g. one is an integer, the
6211 // other is floating point, or their sizes are different, flag it as an
6213 if (OpInfo.hasMatchingInput()) {
6214 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
6216 if (OpInfo.ConstraintVT != Input.ConstraintVT) {
6217 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
6218 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
6219 TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
6220 OpInfo.ConstraintVT);
6221 std::pair<unsigned, const TargetRegisterClass *> InputRC =
6222 TLI.getRegForInlineAsmConstraint(TRI, Input.ConstraintCode,
6223 Input.ConstraintVT);
6224 if ((OpInfo.ConstraintVT.isInteger() !=
6225 Input.ConstraintVT.isInteger()) ||
6226 (MatchRC.second != InputRC.second)) {
6227 report_fatal_error("Unsupported asm: input constraint"
6228 " with a matching output constraint of"
6229 " incompatible type!");
6231 Input.ConstraintVT = OpInfo.ConstraintVT;
6235 // Compute the constraint code and ConstraintType to use.
6236 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG);
6238 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6239 OpInfo.Type == InlineAsm::isClobber)
6242 // If this is a memory input, and if the operand is not indirect, do what we
6243 // need to to provide an address for the memory input.
6244 if (OpInfo.ConstraintType == TargetLowering::C_Memory &&
6245 !OpInfo.isIndirect) {
6246 assert((OpInfo.isMultipleAlternative ||
6247 (OpInfo.Type == InlineAsm::isInput)) &&
6248 "Can only indirectify direct input operands!");
6250 // Memory operands really want the address of the value. If we don't have
6251 // an indirect input, put it in the constpool if we can, otherwise spill
6252 // it to a stack slot.
6253 // TODO: This isn't quite right. We need to handle these according to
6254 // the addressing mode that the constraint wants. Also, this may take
6255 // an additional register for the computation and we don't want that
6258 // If the operand is a float, integer, or vector constant, spill to a
6259 // constant pool entry to get its address.
6260 const Value *OpVal = OpInfo.CallOperandVal;
6261 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
6262 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
6263 OpInfo.CallOperand = DAG.getConstantPool(
6264 cast<Constant>(OpVal), TLI.getPointerTy(DAG.getDataLayout()));
6266 // Otherwise, create a stack slot and emit a store to it before the
6268 Type *Ty = OpVal->getType();
6269 auto &DL = DAG.getDataLayout();
6270 uint64_t TySize = DL.getTypeAllocSize(Ty);
6271 unsigned Align = DL.getPrefTypeAlignment(Ty);
6272 MachineFunction &MF = DAG.getMachineFunction();
6273 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
6275 DAG.getFrameIndex(SSFI, TLI.getPointerTy(DAG.getDataLayout()));
6276 Chain = DAG.getStore(
6277 Chain, getCurSDLoc(), OpInfo.CallOperand, StackSlot,
6278 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
6280 OpInfo.CallOperand = StackSlot;
6283 // There is no longer a Value* corresponding to this operand.
6284 OpInfo.CallOperandVal = nullptr;
6286 // It is now an indirect operand.
6287 OpInfo.isIndirect = true;
6290 // If this constraint is for a specific register, allocate it before
6292 if (OpInfo.ConstraintType == TargetLowering::C_Register)
6293 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6296 // Second pass - Loop over all of the operands, assigning virtual or physregs
6297 // to register class operands.
6298 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6299 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6301 // C_Register operands have already been allocated, Other/Memory don't need
6303 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass)
6304 GetRegistersForValue(DAG, TLI, getCurSDLoc(), OpInfo);
6307 // AsmNodeOperands - The operands for the ISD::INLINEASM node.
6308 std::vector<SDValue> AsmNodeOperands;
6309 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
6310 AsmNodeOperands.push_back(DAG.getTargetExternalSymbol(
6311 IA->getAsmString().c_str(), TLI.getPointerTy(DAG.getDataLayout())));
6313 // If we have a !srcloc metadata node associated with it, we want to attach
6314 // this to the ultimately generated inline asm machineinstr. To do this, we
6315 // pass in the third operand as this (potentially null) inline asm MDNode.
6316 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc");
6317 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc));
6319 // Remember the HasSideEffect, AlignStack, AsmDialect, MayLoad and MayStore
6320 // bits as operand 3.
6321 unsigned ExtraInfo = 0;
6322 if (IA->hasSideEffects())
6323 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
6324 if (IA->isAlignStack())
6325 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
6326 // Set the asm dialect.
6327 ExtraInfo |= IA->getDialect() * InlineAsm::Extra_AsmDialect;
6329 // Determine if this InlineAsm MayLoad or MayStore based on the constraints.
6330 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) {
6331 TargetLowering::AsmOperandInfo &OpInfo = TargetConstraints[i];
6333 // Compute the constraint code and ConstraintType to use.
6334 TLI.ComputeConstraintToUse(OpInfo, SDValue());
6336 // Ideally, we would only check against memory constraints. However, the
6337 // meaning of an other constraint can be target-specific and we can't easily
6338 // reason about it. Therefore, be conservative and set MayLoad/MayStore
6339 // for other constriants as well.
6340 if (OpInfo.ConstraintType == TargetLowering::C_Memory ||
6341 OpInfo.ConstraintType == TargetLowering::C_Other) {
6342 if (OpInfo.Type == InlineAsm::isInput)
6343 ExtraInfo |= InlineAsm::Extra_MayLoad;
6344 else if (OpInfo.Type == InlineAsm::isOutput)
6345 ExtraInfo |= InlineAsm::Extra_MayStore;
6346 else if (OpInfo.Type == InlineAsm::isClobber)
6347 ExtraInfo |= (InlineAsm::Extra_MayLoad | InlineAsm::Extra_MayStore);
6351 AsmNodeOperands.push_back(DAG.getTargetConstant(
6352 ExtraInfo, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6354 // Loop over all of the inputs, copying the operand values into the
6355 // appropriate registers and processing the output regs.
6356 RegsForValue RetValRegs;
6358 // IndirectStoresToEmit - The set of stores to emit after the inline asm node.
6359 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit;
6361 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) {
6362 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i];
6364 switch (OpInfo.Type) {
6365 case InlineAsm::isOutput: {
6366 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass &&
6367 OpInfo.ConstraintType != TargetLowering::C_Register) {
6368 // Memory output, or 'other' output (e.g. 'X' constraint).
6369 assert(OpInfo.isIndirect && "Memory output must be indirect operand");
6371 unsigned ConstraintID =
6372 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6373 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6374 "Failed to convert memory constraint code to constraint id.");
6376 // Add information to the INLINEASM node to know about this output.
6377 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6378 OpFlags = InlineAsm::getFlagWordForMem(OpFlags, ConstraintID);
6379 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, getCurSDLoc(),
6381 AsmNodeOperands.push_back(OpInfo.CallOperand);
6385 // Otherwise, this is a register or register class output.
6387 // Copy the output from the appropriate register. Find a register that
6389 if (OpInfo.AssignedRegs.Regs.empty()) {
6390 LLVMContext &Ctx = *DAG.getContext();
6391 Ctx.emitError(CS.getInstruction(),
6392 "couldn't allocate output register for constraint '" +
6393 Twine(OpInfo.ConstraintCode) + "'");
6397 // If this is an indirect operand, store through the pointer after the
6399 if (OpInfo.isIndirect) {
6400 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs,
6401 OpInfo.CallOperandVal));
6403 // This is the result value of the call.
6404 assert(!CS.getType()->isVoidTy() && "Bad inline asm!");
6405 // Concatenate this output onto the outputs list.
6406 RetValRegs.append(OpInfo.AssignedRegs);
6409 // Add information to the INLINEASM node to know that this register is
6412 .AddInlineAsmOperands(OpInfo.isEarlyClobber
6413 ? InlineAsm::Kind_RegDefEarlyClobber
6414 : InlineAsm::Kind_RegDef,
6415 false, 0, getCurSDLoc(), DAG, AsmNodeOperands);
6418 case InlineAsm::isInput: {
6419 SDValue InOperandVal = OpInfo.CallOperand;
6421 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint?
6422 // If this is required to match an output register we have already set,
6423 // just use its register.
6424 unsigned OperandNo = OpInfo.getMatchedOperand();
6426 // Scan until we find the definition we already emitted of this operand.
6427 // When we find it, create a RegsForValue operand.
6428 unsigned CurOp = InlineAsm::Op_FirstOperand;
6429 for (; OperandNo; --OperandNo) {
6430 // Advance to the next operand.
6432 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6433 assert((InlineAsm::isRegDefKind(OpFlag) ||
6434 InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
6435 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?");
6436 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1;
6440 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
6441 if (InlineAsm::isRegDefKind(OpFlag) ||
6442 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
6443 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
6444 if (OpInfo.isIndirect) {
6445 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c
6446 LLVMContext &Ctx = *DAG.getContext();
6447 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:"
6448 " don't know how to handle tied "
6449 "indirect register inputs");
6453 RegsForValue MatchedRegs;
6454 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
6455 MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();
6456 MatchedRegs.RegVTs.push_back(RegVT);
6457 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
6458 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
6460 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))
6461 MatchedRegs.Regs.push_back(RegInfo.createVirtualRegister(RC));
6463 LLVMContext &Ctx = *DAG.getContext();
6464 Ctx.emitError(CS.getInstruction(),
6465 "inline asm error: This value"
6466 " type register class is not natively supported!");
6470 SDLoc dl = getCurSDLoc();
6471 // Use the produced MatchedRegs object to
6472 MatchedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6473 Chain, &Flag, CS.getInstruction());
6474 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse,
6475 true, OpInfo.getMatchedOperand(), dl,
6476 DAG, AsmNodeOperands);
6480 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!");
6481 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 &&
6482 "Unexpected number of operands");
6483 // Add information to the INLINEASM node to know about this input.
6484 // See InlineAsm.h isUseOperandTiedToDef.
6485 OpFlag = InlineAsm::convertMemFlagWordToMatchingFlagWord(OpFlag);
6486 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag,
6487 OpInfo.getMatchedOperand());
6488 AsmNodeOperands.push_back(DAG.getTargetConstant(
6489 OpFlag, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6490 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
6494 // Treat indirect 'X' constraint as memory.
6495 if (OpInfo.ConstraintType == TargetLowering::C_Other &&
6497 OpInfo.ConstraintType = TargetLowering::C_Memory;
6499 if (OpInfo.ConstraintType == TargetLowering::C_Other) {
6500 std::vector<SDValue> Ops;
6501 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode,
6504 LLVMContext &Ctx = *DAG.getContext();
6505 Ctx.emitError(CS.getInstruction(),
6506 "invalid operand for inline asm constraint '" +
6507 Twine(OpInfo.ConstraintCode) + "'");
6511 // Add information to the INLINEASM node to know about this input.
6512 unsigned ResOpType =
6513 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size());
6514 AsmNodeOperands.push_back(DAG.getTargetConstant(
6515 ResOpType, getCurSDLoc(), TLI.getPointerTy(DAG.getDataLayout())));
6516 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end());
6520 if (OpInfo.ConstraintType == TargetLowering::C_Memory) {
6521 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!");
6522 assert(InOperandVal.getValueType() ==
6523 TLI.getPointerTy(DAG.getDataLayout()) &&
6524 "Memory operands expect pointer values");
6526 unsigned ConstraintID =
6527 TLI.getInlineAsmMemConstraint(OpInfo.ConstraintCode);
6528 assert(ConstraintID != InlineAsm::Constraint_Unknown &&
6529 "Failed to convert memory constraint code to constraint id.");
6531 // Add information to the INLINEASM node to know about this input.
6532 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1);
6533 ResOpType = InlineAsm::getFlagWordForMem(ResOpType, ConstraintID);
6534 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType,
6537 AsmNodeOperands.push_back(InOperandVal);
6541 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass ||
6542 OpInfo.ConstraintType == TargetLowering::C_Register) &&
6543 "Unknown constraint type!");
6545 // TODO: Support this.
6546 if (OpInfo.isIndirect) {
6547 LLVMContext &Ctx = *DAG.getContext();
6548 Ctx.emitError(CS.getInstruction(),
6549 "Don't know how to handle indirect register inputs yet "
6550 "for constraint '" +
6551 Twine(OpInfo.ConstraintCode) + "'");
6555 // Copy the input into the appropriate registers.
6556 if (OpInfo.AssignedRegs.Regs.empty()) {
6557 LLVMContext &Ctx = *DAG.getContext();
6558 Ctx.emitError(CS.getInstruction(),
6559 "couldn't allocate input reg for constraint '" +
6560 Twine(OpInfo.ConstraintCode) + "'");
6564 SDLoc dl = getCurSDLoc();
6566 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, dl,
6567 Chain, &Flag, CS.getInstruction());
6569 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0,
6570 dl, DAG, AsmNodeOperands);
6573 case InlineAsm::isClobber: {
6574 // Add the clobbered value to the operand list, so that the register
6575 // allocator is aware that the physreg got clobbered.
6576 if (!OpInfo.AssignedRegs.Regs.empty())
6577 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber,
6578 false, 0, getCurSDLoc(), DAG,
6585 // Finish up input operands. Set the input chain and add the flag last.
6586 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
6587 if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
6589 Chain = DAG.getNode(ISD::INLINEASM, getCurSDLoc(),
6590 DAG.getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
6591 Flag = Chain.getValue(1);
6593 // If this asm returns a register value, copy the result from that register
6594 // and set it as the value of the call.
6595 if (!RetValRegs.Regs.empty()) {
6596 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6597 Chain, &Flag, CS.getInstruction());
6599 // FIXME: Why don't we do this for inline asms with MRVs?
6600 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
6601 EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
6603 // If any of the results of the inline asm is a vector, it may have the
6604 // wrong width/num elts. This can happen for register classes that can
6605 // contain multiple different value types. The preg or vreg allocated may
6606 // not have the same VT as was expected. Convert it to the right type
6607 // with bit_convert.
6608 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) {
6609 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
6612 } else if (ResultType != Val.getValueType() &&
6613 ResultType.isInteger() && Val.getValueType().isInteger()) {
6614 // If a result value was tied to an input value, the computed result may
6615 // have a wider width than the expected result. Extract the relevant
6617 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
6620 assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
6623 setValue(CS.getInstruction(), Val);
6624 // Don't need to use this as a chain in this case.
6625 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
6629 std::vector<std::pair<SDValue, const Value *> > StoresToEmit;
6631 // Process indirect outputs, first output all of the flagged copies out of
6633 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) {
6634 RegsForValue &OutRegs = IndirectStoresToEmit[i].first;
6635 const Value *Ptr = IndirectStoresToEmit[i].second;
6636 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
6638 StoresToEmit.push_back(std::make_pair(OutVal, Ptr));
6641 // Emit the non-flagged stores from the physregs.
6642 SmallVector<SDValue, 8> OutChains;
6643 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) {
6644 SDValue Val = DAG.getStore(Chain, getCurSDLoc(),
6645 StoresToEmit[i].first,
6646 getValue(StoresToEmit[i].second),
6647 MachinePointerInfo(StoresToEmit[i].second),
6649 OutChains.push_back(Val);
6652 if (!OutChains.empty())
6653 Chain = DAG.getNode(ISD::TokenFactor, getCurSDLoc(), MVT::Other, OutChains);
6658 void SelectionDAGBuilder::visitVAStart(const CallInst &I) {
6659 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurSDLoc(),
6660 MVT::Other, getRoot(),
6661 getValue(I.getArgOperand(0)),
6662 DAG.getSrcValue(I.getArgOperand(0))));
6665 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) {
6666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6667 const DataLayout &DL = DAG.getDataLayout();
6668 SDValue V = DAG.getVAArg(TLI.getValueType(DAG.getDataLayout(), I.getType()),
6669 getCurSDLoc(), getRoot(), getValue(I.getOperand(0)),
6670 DAG.getSrcValue(I.getOperand(0)),
6671 DL.getABITypeAlignment(I.getType()));
6673 DAG.setRoot(V.getValue(1));
6676 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) {
6677 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurSDLoc(),
6678 MVT::Other, getRoot(),
6679 getValue(I.getArgOperand(0)),
6680 DAG.getSrcValue(I.getArgOperand(0))));
6683 void SelectionDAGBuilder::visitVACopy(const CallInst &I) {
6684 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurSDLoc(),
6685 MVT::Other, getRoot(),
6686 getValue(I.getArgOperand(0)),
6687 getValue(I.getArgOperand(1)),
6688 DAG.getSrcValue(I.getArgOperand(0)),
6689 DAG.getSrcValue(I.getArgOperand(1))));
6692 /// \brief Lower an argument list according to the target calling convention.
6694 /// \return A tuple of <return-value, token-chain>
6696 /// This is a helper for lowering intrinsics that follow a target calling
6697 /// convention or require stack pointer adjustment. Only a subset of the
6698 /// intrinsic's operands need to participate in the calling convention.
6699 std::pair<SDValue, SDValue> SelectionDAGBuilder::lowerCallOperands(
6700 ImmutableCallSite CS, unsigned ArgIdx, unsigned NumArgs, SDValue Callee,
6701 Type *ReturnTy, const BasicBlock *EHPadBB, bool IsPatchPoint) {
6702 TargetLowering::ArgListTy Args;
6703 Args.reserve(NumArgs);
6705 // Populate the argument list.
6706 // Attributes for args start at offset 1, after the return attribute.
6707 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
6708 ArgI != ArgE; ++ArgI) {
6709 const Value *V = CS->getOperand(ArgI);
6711 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
6713 TargetLowering::ArgListEntry Entry;
6714 Entry.Node = getValue(V);
6715 Entry.Ty = V->getType();
6716 Entry.setAttributes(&CS, AttrI);
6717 Args.push_back(Entry);
6720 TargetLowering::CallLoweringInfo CLI(DAG);
6721 CLI.setDebugLoc(getCurSDLoc()).setChain(getRoot())
6722 .setCallee(CS.getCallingConv(), ReturnTy, Callee, std::move(Args), NumArgs)
6723 .setDiscardResult(CS->use_empty()).setIsPatchPoint(IsPatchPoint);
6725 return lowerInvokable(CLI, EHPadBB);
6728 /// \brief Add a stack map intrinsic call's live variable operands to a stackmap
6729 /// or patchpoint target node's operand list.
6731 /// Constants are converted to TargetConstants purely as an optimization to
6732 /// avoid constant materialization and register allocation.
6734 /// FrameIndex operands are converted to TargetFrameIndex so that ISEL does not
6735 /// generate addess computation nodes, and so ExpandISelPseudo can convert the
6736 /// TargetFrameIndex into a DirectMemRefOp StackMap location. This avoids
6737 /// address materialization and register allocation, but may also be required
6738 /// for correctness. If a StackMap (or PatchPoint) intrinsic directly uses an
6739 /// alloca in the entry block, then the runtime may assume that the alloca's
6740 /// StackMap location can be read immediately after compilation and that the
6741 /// location is valid at any point during execution (this is similar to the
6742 /// assumption made by the llvm.gcroot intrinsic). If the alloca's location were
6743 /// only available in a register, then the runtime would need to trap when
6744 /// execution reaches the StackMap in order to read the alloca's location.
6745 static void addStackMapLiveVars(ImmutableCallSite CS, unsigned StartIdx,
6746 SDLoc DL, SmallVectorImpl<SDValue> &Ops,
6747 SelectionDAGBuilder &Builder) {
6748 for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
6749 SDValue OpVal = Builder.getValue(CS.getArgument(i));
6750 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
6752 Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
6754 Builder.DAG.getTargetConstant(C->getSExtValue(), DL, MVT::i64));
6755 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(OpVal)) {
6756 const TargetLowering &TLI = Builder.DAG.getTargetLoweringInfo();
6757 Ops.push_back(Builder.DAG.getTargetFrameIndex(
6758 FI->getIndex(), TLI.getPointerTy(Builder.DAG.getDataLayout())));
6760 Ops.push_back(OpVal);
6764 /// \brief Lower llvm.experimental.stackmap directly to its target opcode.
6765 void SelectionDAGBuilder::visitStackmap(const CallInst &CI) {
6766 // void @llvm.experimental.stackmap(i32 <id>, i32 <numShadowBytes>,
6767 // [live variables...])
6769 assert(CI.getType()->isVoidTy() && "Stackmap cannot return a value.");
6771 SDValue Chain, InFlag, Callee, NullPtr;
6772 SmallVector<SDValue, 32> Ops;
6774 SDLoc DL = getCurSDLoc();
6775 Callee = getValue(CI.getCalledValue());
6776 NullPtr = DAG.getIntPtrConstant(0, DL, true);
6778 // The stackmap intrinsic only records the live variables (the arguemnts
6779 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
6780 // intrinsic, this won't be lowered to a function call. This means we don't
6781 // have to worry about calling conventions and target specific lowering code.
6782 // Instead we perform the call lowering right here.
6784 // chain, flag = CALLSEQ_START(chain, 0)
6785 // chain, flag = STACKMAP(id, nbytes, ..., chain, flag)
6786 // chain, flag = CALLSEQ_END(chain, 0, 0, flag)
6788 Chain = DAG.getCALLSEQ_START(getRoot(), NullPtr, DL);
6789 InFlag = Chain.getValue(1);
6791 // Add the <id> and <numBytes> constants.
6792 SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
6793 Ops.push_back(DAG.getTargetConstant(
6794 cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
6795 SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
6796 Ops.push_back(DAG.getTargetConstant(
6797 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
6800 // Push live variables for the stack map.
6801 addStackMapLiveVars(&CI, 2, DL, Ops, *this);
6803 // We are not pushing any register mask info here on the operands list,
6804 // because the stackmap doesn't clobber anything.
6806 // Push the chain and the glue flag.
6807 Ops.push_back(Chain);
6808 Ops.push_back(InFlag);
6810 // Create the STACKMAP node.
6811 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6812 SDNode *SM = DAG.getMachineNode(TargetOpcode::STACKMAP, DL, NodeTys, Ops);
6813 Chain = SDValue(SM, 0);
6814 InFlag = Chain.getValue(1);
6816 Chain = DAG.getCALLSEQ_END(Chain, NullPtr, NullPtr, InFlag, DL);
6818 // Stackmaps don't generate values, so nothing goes into the NodeMap.
6820 // Set the root to the target-lowered call chain.
6823 // Inform the Frame Information that we have a stackmap in this function.
6824 FuncInfo.MF->getFrameInfo()->setHasStackMap();
6827 /// \brief Lower llvm.experimental.patchpoint directly to its target opcode.
6828 void SelectionDAGBuilder::visitPatchpoint(ImmutableCallSite CS,
6829 const BasicBlock *EHPadBB) {
6830 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
6835 // [live variables...])
6837 CallingConv::ID CC = CS.getCallingConv();
6838 bool IsAnyRegCC = CC == CallingConv::AnyReg;
6839 bool HasDef = !CS->getType()->isVoidTy();
6840 SDLoc dl = getCurSDLoc();
6841 SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
6843 // Handle immediate and symbolic callees.
6844 if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
6845 Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
6847 else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
6848 Callee = DAG.getTargetGlobalAddress(SymbolicCallee->getGlobal(),
6849 SDLoc(SymbolicCallee),
6850 SymbolicCallee->getValueType(0));
6852 // Get the real number of arguments participating in the call <numArgs>
6853 SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
6854 unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
6856 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
6857 // Intrinsics include all meta-operands up to but not including CC.
6858 unsigned NumMetaOpers = PatchPointOpers::CCPos;
6859 assert(CS.arg_size() >= NumMetaOpers + NumArgs &&
6860 "Not enough arguments provided to the patchpoint intrinsic");
6862 // For AnyRegCC the arguments are lowered later on manually.
6863 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
6865 IsAnyRegCC ? Type::getVoidTy(*DAG.getContext()) : CS->getType();
6866 std::pair<SDValue, SDValue> Result = lowerCallOperands(
6867 CS, NumMetaOpers, NumCallArgs, Callee, ReturnTy, EHPadBB, true);
6869 SDNode *CallEnd = Result.second.getNode();
6870 if (HasDef && (CallEnd->getOpcode() == ISD::CopyFromReg))
6871 CallEnd = CallEnd->getOperand(0).getNode();
6873 /// Get a call instruction from the call sequence chain.
6874 /// Tail calls are not allowed.
6875 assert(CallEnd->getOpcode() == ISD::CALLSEQ_END &&
6876 "Expected a callseq node.");
6877 SDNode *Call = CallEnd->getOperand(0).getNode();
6878 bool HasGlue = Call->getGluedNode();
6880 // Replace the target specific call node with the patchable intrinsic.
6881 SmallVector<SDValue, 8> Ops;
6883 // Add the <id> and <numBytes> constants.
6884 SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
6885 Ops.push_back(DAG.getTargetConstant(
6886 cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
6887 SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
6888 Ops.push_back(DAG.getTargetConstant(
6889 cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
6893 Ops.push_back(Callee);
6895 // Adjust <numArgs> to account for any arguments that have been passed on the
6897 // Call Node: Chain, Target, {Args}, RegMask, [Glue]
6898 unsigned NumCallRegArgs = Call->getNumOperands() - (HasGlue ? 4 : 3);
6899 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
6900 Ops.push_back(DAG.getTargetConstant(NumCallRegArgs, dl, MVT::i32));
6902 // Add the calling convention
6903 Ops.push_back(DAG.getTargetConstant((unsigned)CC, dl, MVT::i32));
6905 // Add the arguments we omitted previously. The register allocator should
6906 // place these in any free register.
6908 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i)
6909 Ops.push_back(getValue(CS.getArgument(i)));
6911 // Push the arguments from the call instruction up to the register mask.
6912 SDNode::op_iterator e = HasGlue ? Call->op_end()-2 : Call->op_end()-1;
6913 Ops.append(Call->op_begin() + 2, e);
6915 // Push live variables for the stack map.
6916 addStackMapLiveVars(CS, NumMetaOpers + NumArgs, dl, Ops, *this);
6918 // Push the register mask info.
6920 Ops.push_back(*(Call->op_end()-2));
6922 Ops.push_back(*(Call->op_end()-1));
6924 // Push the chain (this is originally the first operand of the call, but
6925 // becomes now the last or second to last operand).
6926 Ops.push_back(*(Call->op_begin()));
6928 // Push the glue flag (last operand).
6930 Ops.push_back(*(Call->op_end()-1));
6933 if (IsAnyRegCC && HasDef) {
6934 // Create the return types based on the intrinsic definition
6935 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6936 SmallVector<EVT, 3> ValueVTs;
6937 ComputeValueVTs(TLI, DAG.getDataLayout(), CS->getType(), ValueVTs);
6938 assert(ValueVTs.size() == 1 && "Expected only one return value type.");
6940 // There is always a chain and a glue type at the end
6941 ValueVTs.push_back(MVT::Other);
6942 ValueVTs.push_back(MVT::Glue);
6943 NodeTys = DAG.getVTList(ValueVTs);
6945 NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
6947 // Replace the target specific call node with a PATCHPOINT node.
6948 MachineSDNode *MN = DAG.getMachineNode(TargetOpcode::PATCHPOINT,
6951 // Update the NodeMap.
6954 setValue(CS.getInstruction(), SDValue(MN, 0));
6956 setValue(CS.getInstruction(), Result.first);
6959 // Fixup the consumers of the intrinsic. The chain and glue may be used in the
6960 // call sequence. Furthermore the location of the chain and glue can change
6961 // when the AnyReg calling convention is used and the intrinsic returns a
6963 if (IsAnyRegCC && HasDef) {
6964 SDValue From[] = {SDValue(Call, 0), SDValue(Call, 1)};
6965 SDValue To[] = {SDValue(MN, 1), SDValue(MN, 2)};
6966 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
6968 DAG.ReplaceAllUsesWith(Call, MN);
6969 DAG.DeleteNode(Call);
6971 // Inform the Frame Information that we have a patchpoint in this function.
6972 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
6975 /// Returns an AttributeSet representing the attributes applied to the return
6976 /// value of the given call.
6977 static AttributeSet getReturnAttrs(TargetLowering::CallLoweringInfo &CLI) {
6978 SmallVector<Attribute::AttrKind, 2> Attrs;
6980 Attrs.push_back(Attribute::SExt);
6982 Attrs.push_back(Attribute::ZExt);
6984 Attrs.push_back(Attribute::InReg);
6986 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
6990 /// TargetLowering::LowerCallTo - This is the default LowerCallTo
6991 /// implementation, which just calls LowerCall.
6992 /// FIXME: When all targets are
6993 /// migrated to using LowerCall, this hook should be integrated into SDISel.
6994 std::pair<SDValue, SDValue>
6995 TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
6996 // Handle the incoming return values from the call.
6998 Type *OrigRetTy = CLI.RetTy;
6999 SmallVector<EVT, 4> RetTys;
7000 SmallVector<uint64_t, 4> Offsets;
7001 auto &DL = CLI.DAG.getDataLayout();
7002 ComputeValueVTs(*this, DL, CLI.RetTy, RetTys, &Offsets);
7004 SmallVector<ISD::OutputArg, 4> Outs;
7005 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, *this, DL);
7007 bool CanLowerReturn =
7008 this->CanLowerReturn(CLI.CallConv, CLI.DAG.getMachineFunction(),
7009 CLI.IsVarArg, Outs, CLI.RetTy->getContext());
7011 SDValue DemoteStackSlot;
7012 int DemoteStackIdx = -100;
7013 if (!CanLowerReturn) {
7014 // FIXME: equivalent assert?
7015 // assert(!CS.hasInAllocaArgument() &&
7016 // "sret demotion is incompatible with inalloca");
7017 uint64_t TySize = DL.getTypeAllocSize(CLI.RetTy);
7018 unsigned Align = DL.getPrefTypeAlignment(CLI.RetTy);
7019 MachineFunction &MF = CLI.DAG.getMachineFunction();
7020 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false);
7021 Type *StackSlotPtrType = PointerType::getUnqual(CLI.RetTy);
7023 DemoteStackSlot = CLI.DAG.getFrameIndex(DemoteStackIdx, getPointerTy(DL));
7025 Entry.Node = DemoteStackSlot;
7026 Entry.Ty = StackSlotPtrType;
7027 Entry.isSExt = false;
7028 Entry.isZExt = false;
7029 Entry.isInReg = false;
7030 Entry.isSRet = true;
7031 Entry.isNest = false;
7032 Entry.isByVal = false;
7033 Entry.isReturned = false;
7034 Entry.Alignment = Align;
7035 CLI.getArgs().insert(CLI.getArgs().begin(), Entry);
7036 CLI.RetTy = Type::getVoidTy(CLI.RetTy->getContext());
7038 // sret demotion isn't compatible with tail-calls, since the sret argument
7039 // points into the callers stack frame.
7040 CLI.IsTailCall = false;
7042 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7044 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7045 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7046 for (unsigned i = 0; i != NumRegs; ++i) {
7047 ISD::InputArg MyFlags;
7048 MyFlags.VT = RegisterVT;
7050 MyFlags.Used = CLI.IsReturnValueUsed;
7052 MyFlags.Flags.setSExt();
7054 MyFlags.Flags.setZExt();
7056 MyFlags.Flags.setInReg();
7057 CLI.Ins.push_back(MyFlags);
7062 // Handle all of the outgoing arguments.
7064 CLI.OutVals.clear();
7065 ArgListTy &Args = CLI.getArgs();
7066 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
7067 SmallVector<EVT, 4> ValueVTs;
7068 ComputeValueVTs(*this, DL, Args[i].Ty, ValueVTs);
7069 Type *FinalType = Args[i].Ty;
7070 if (Args[i].isByVal)
7071 FinalType = cast<PointerType>(Args[i].Ty)->getElementType();
7072 bool NeedsRegBlock = functionArgumentNeedsConsecutiveRegisters(
7073 FinalType, CLI.CallConv, CLI.IsVarArg);
7074 for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues;
7076 EVT VT = ValueVTs[Value];
7077 Type *ArgTy = VT.getTypeForEVT(CLI.RetTy->getContext());
7078 SDValue Op = SDValue(Args[i].Node.getNode(),
7079 Args[i].Node.getResNo() + Value);
7080 ISD::ArgFlagsTy Flags;
7081 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7087 if (Args[i].isInReg)
7091 if (Args[i].isByVal)
7093 if (Args[i].isInAlloca) {
7094 Flags.setInAlloca();
7095 // Set the byval flag for CCAssignFn callbacks that don't know about
7096 // inalloca. This way we can know how many bytes we should've allocated
7097 // and how many bytes a callee cleanup function will pop. If we port
7098 // inalloca to more targets, we'll have to add custom inalloca handling
7099 // in the various CC lowering callbacks.
7102 if (Args[i].isByVal || Args[i].isInAlloca) {
7103 PointerType *Ty = cast<PointerType>(Args[i].Ty);
7104 Type *ElementTy = Ty->getElementType();
7105 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7106 // For ByVal, alignment should come from FE. BE will guess if this
7107 // info is not there but there are cases it cannot get right.
7108 unsigned FrameAlign;
7109 if (Args[i].Alignment)
7110 FrameAlign = Args[i].Alignment;
7112 FrameAlign = getByValTypeAlignment(ElementTy, DL);
7113 Flags.setByValAlign(FrameAlign);
7118 Flags.setInConsecutiveRegs();
7119 Flags.setOrigAlign(OriginalAlignment);
7121 MVT PartVT = getRegisterType(CLI.RetTy->getContext(), VT);
7122 unsigned NumParts = getNumRegisters(CLI.RetTy->getContext(), VT);
7123 SmallVector<SDValue, 4> Parts(NumParts);
7124 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
7127 ExtendKind = ISD::SIGN_EXTEND;
7128 else if (Args[i].isZExt)
7129 ExtendKind = ISD::ZERO_EXTEND;
7131 // Conservatively only handle 'returned' on non-vectors for now
7132 if (Args[i].isReturned && !Op.getValueType().isVector()) {
7133 assert(CLI.RetTy == Args[i].Ty && RetTys.size() == NumValues &&
7134 "unexpected use of 'returned'");
7135 // Before passing 'returned' to the target lowering code, ensure that
7136 // either the register MVT and the actual EVT are the same size or that
7137 // the return value and argument are extended in the same way; in these
7138 // cases it's safe to pass the argument register value unchanged as the
7139 // return register value (although it's at the target's option whether
7141 // TODO: allow code generation to take advantage of partially preserved
7142 // registers rather than clobbering the entire register when the
7143 // parameter extension method is not compatible with the return
7145 if ((NumParts * PartVT.getSizeInBits() == VT.getSizeInBits()) ||
7146 (ExtendKind != ISD::ANY_EXTEND &&
7147 CLI.RetSExt == Args[i].isSExt && CLI.RetZExt == Args[i].isZExt))
7148 Flags.setReturned();
7151 getCopyToParts(CLI.DAG, CLI.DL, Op, &Parts[0], NumParts, PartVT,
7152 CLI.CS ? CLI.CS->getInstruction() : nullptr, ExtendKind);
7154 for (unsigned j = 0; j != NumParts; ++j) {
7155 // if it isn't first piece, alignment must be 1
7156 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), VT,
7157 i < CLI.NumFixedArgs,
7158 i, j*Parts[j].getValueType().getStoreSize());
7159 if (NumParts > 1 && j == 0)
7160 MyFlags.Flags.setSplit();
7162 MyFlags.Flags.setOrigAlign(1);
7164 CLI.Outs.push_back(MyFlags);
7165 CLI.OutVals.push_back(Parts[j]);
7168 if (NeedsRegBlock && Value == NumValues - 1)
7169 CLI.Outs[CLI.Outs.size() - 1].Flags.setInConsecutiveRegsLast();
7173 SmallVector<SDValue, 4> InVals;
7174 CLI.Chain = LowerCall(CLI, InVals);
7176 // Verify that the target's LowerCall behaved as expected.
7177 assert(CLI.Chain.getNode() && CLI.Chain.getValueType() == MVT::Other &&
7178 "LowerCall didn't return a valid chain!");
7179 assert((!CLI.IsTailCall || InVals.empty()) &&
7180 "LowerCall emitted a return value for a tail call!");
7181 assert((CLI.IsTailCall || InVals.size() == CLI.Ins.size()) &&
7182 "LowerCall didn't emit the correct number of values!");
7184 // For a tail call, the return value is merely live-out and there aren't
7185 // any nodes in the DAG representing it. Return a special value to
7186 // indicate that a tail call has been emitted and no more Instructions
7187 // should be processed in the current block.
7188 if (CLI.IsTailCall) {
7189 CLI.DAG.setRoot(CLI.Chain);
7190 return std::make_pair(SDValue(), SDValue());
7193 DEBUG(for (unsigned i = 0, e = CLI.Ins.size(); i != e; ++i) {
7194 assert(InVals[i].getNode() &&
7195 "LowerCall emitted a null value!");
7196 assert(EVT(CLI.Ins[i].VT) == InVals[i].getValueType() &&
7197 "LowerCall emitted a value with the wrong type!");
7200 SmallVector<SDValue, 4> ReturnValues;
7201 if (!CanLowerReturn) {
7202 // The instruction result is the result of loading from the
7203 // hidden sret parameter.
7204 SmallVector<EVT, 1> PVTs;
7205 Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);
7207 ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
7208 assert(PVTs.size() == 1 && "Pointers should fit in one register");
7209 EVT PtrVT = PVTs[0];
7211 unsigned NumValues = RetTys.size();
7212 ReturnValues.resize(NumValues);
7213 SmallVector<SDValue, 4> Chains(NumValues);
7215 for (unsigned i = 0; i < NumValues; ++i) {
7216 SDValue Add = CLI.DAG.getNode(ISD::ADD, CLI.DL, PtrVT, DemoteStackSlot,
7217 CLI.DAG.getConstant(Offsets[i], CLI.DL,
7219 SDValue L = CLI.DAG.getLoad(
7220 RetTys[i], CLI.DL, CLI.Chain, Add,
7221 MachinePointerInfo::getFixedStack(CLI.DAG.getMachineFunction(),
7222 DemoteStackIdx, Offsets[i]),
7223 false, false, false, 1);
7224 ReturnValues[i] = L;
7225 Chains[i] = L.getValue(1);
7228 CLI.Chain = CLI.DAG.getNode(ISD::TokenFactor, CLI.DL, MVT::Other, Chains);
7230 // Collect the legal value parts into potentially illegal values
7231 // that correspond to the original function's return values.
7232 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7234 AssertOp = ISD::AssertSext;
7235 else if (CLI.RetZExt)
7236 AssertOp = ISD::AssertZext;
7237 unsigned CurReg = 0;
7238 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
7240 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7241 unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), VT);
7243 ReturnValues.push_back(getCopyFromParts(CLI.DAG, CLI.DL, &InVals[CurReg],
7244 NumRegs, RegisterVT, VT, nullptr,
7249 // For a function returning void, there is no return value. We can't create
7250 // such a node, so we just return a null return value in that case. In
7251 // that case, nothing will actually look at the value.
7252 if (ReturnValues.empty())
7253 return std::make_pair(SDValue(), CLI.Chain);
7256 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL,
7257 CLI.DAG.getVTList(RetTys), ReturnValues);
7258 return std::make_pair(Res, CLI.Chain);
7261 void TargetLowering::LowerOperationWrapper(SDNode *N,
7262 SmallVectorImpl<SDValue> &Results,
7263 SelectionDAG &DAG) const {
7264 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
7266 Results.push_back(Res);
7269 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7270 llvm_unreachable("LowerOperation not implemented for this target!");
7274 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) {
7275 SDValue Op = getNonRegisterValue(V);
7276 assert((Op.getOpcode() != ISD::CopyFromReg ||
7277 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) &&
7278 "Copy from a reg to the same reg!");
7279 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg");
7281 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7282 RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
7284 SDValue Chain = DAG.getEntryNode();
7286 ISD::NodeType ExtendType = (FuncInfo.PreferredExtendType.find(V) ==
7287 FuncInfo.PreferredExtendType.end())
7289 : FuncInfo.PreferredExtendType[V];
7290 RFV.getCopyToRegs(Op, DAG, getCurSDLoc(), Chain, nullptr, V, ExtendType);
7291 PendingExports.push_back(Chain);
7294 #include "llvm/CodeGen/SelectionDAGISel.h"
7296 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the
7297 /// entry block, return true. This includes arguments used by switches, since
7298 /// the switch may expand into multiple basic blocks.
7299 static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel) {
7300 // With FastISel active, we may be splitting blocks, so force creation
7301 // of virtual registers for all non-dead arguments.
7303 return A->use_empty();
7305 const BasicBlock &Entry = A->getParent()->front();
7306 for (const User *U : A->users())
7307 if (cast<Instruction>(U)->getParent() != &Entry || isa<SwitchInst>(U))
7308 return false; // Use not in entry block.
7313 void SelectionDAGISel::LowerArguments(const Function &F) {
7314 SelectionDAG &DAG = SDB->DAG;
7315 SDLoc dl = SDB->getCurSDLoc();
7316 const DataLayout &DL = DAG.getDataLayout();
7317 SmallVector<ISD::InputArg, 16> Ins;
7319 if (!FuncInfo->CanLowerReturn) {
7320 // Put in an sret pointer parameter before all the other parameters.
7321 SmallVector<EVT, 1> ValueVTs;
7322 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7323 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7325 // NOTE: Assuming that a pointer will never break down to more than one VT
7327 ISD::ArgFlagsTy Flags;
7329 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7330 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7331 ISD::InputArg::NoArgIndex, 0);
7332 Ins.push_back(RetArg);
7335 // Set up the incoming argument description vector.
7337 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end();
7338 I != E; ++I, ++Idx) {
7339 SmallVector<EVT, 4> ValueVTs;
7340 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7341 bool isArgValueUsed = !I->use_empty();
7342 unsigned PartBase = 0;
7343 Type *FinalType = I->getType();
7344 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7345 FinalType = cast<PointerType>(FinalType)->getElementType();
7346 bool NeedsRegBlock = TLI->functionArgumentNeedsConsecutiveRegisters(
7347 FinalType, F.getCallingConv(), F.isVarArg());
7348 for (unsigned Value = 0, NumValues = ValueVTs.size();
7349 Value != NumValues; ++Value) {
7350 EVT VT = ValueVTs[Value];
7351 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
7352 ISD::ArgFlagsTy Flags;
7353 unsigned OriginalAlignment = DL.getABITypeAlignment(ArgTy);
7355 if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7357 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7359 if (F.getAttributes().hasAttribute(Idx, Attribute::InReg))
7361 if (F.getAttributes().hasAttribute(Idx, Attribute::StructRet))
7363 if (F.getAttributes().hasAttribute(Idx, Attribute::ByVal))
7365 if (F.getAttributes().hasAttribute(Idx, Attribute::InAlloca)) {
7366 Flags.setInAlloca();
7367 // Set the byval flag for CCAssignFn callbacks that don't know about
7368 // inalloca. This way we can know how many bytes we should've allocated
7369 // and how many bytes a callee cleanup function will pop. If we port
7370 // inalloca to more targets, we'll have to add custom inalloca handling
7371 // in the various CC lowering callbacks.
7374 if (Flags.isByVal() || Flags.isInAlloca()) {
7375 PointerType *Ty = cast<PointerType>(I->getType());
7376 Type *ElementTy = Ty->getElementType();
7377 Flags.setByValSize(DL.getTypeAllocSize(ElementTy));
7378 // For ByVal, alignment should be passed from FE. BE will guess if
7379 // this info is not there but there are cases it cannot get right.
7380 unsigned FrameAlign;
7381 if (F.getParamAlignment(Idx))
7382 FrameAlign = F.getParamAlignment(Idx);
7384 FrameAlign = TLI->getByValTypeAlignment(ElementTy, DL);
7385 Flags.setByValAlign(FrameAlign);
7387 if (F.getAttributes().hasAttribute(Idx, Attribute::Nest))
7390 Flags.setInConsecutiveRegs();
7391 Flags.setOrigAlign(OriginalAlignment);
7393 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7394 unsigned NumRegs = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7395 for (unsigned i = 0; i != NumRegs; ++i) {
7396 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7397 Idx-1, PartBase+i*RegisterVT.getStoreSize());
7398 if (NumRegs > 1 && i == 0)
7399 MyFlags.Flags.setSplit();
7400 // if it isn't first piece, alignment must be 1
7402 MyFlags.Flags.setOrigAlign(1);
7403 Ins.push_back(MyFlags);
7405 if (NeedsRegBlock && Value == NumValues - 1)
7406 Ins[Ins.size() - 1].Flags.setInConsecutiveRegsLast();
7407 PartBase += VT.getStoreSize();
7411 // Call the target to set up the argument values.
7412 SmallVector<SDValue, 8> InVals;
7413 SDValue NewRoot = TLI->LowerFormalArguments(
7414 DAG.getRoot(), F.getCallingConv(), F.isVarArg(), Ins, dl, DAG, InVals);
7416 // Verify that the target's LowerFormalArguments behaved as expected.
7417 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
7418 "LowerFormalArguments didn't return a valid chain!");
7419 assert(InVals.size() == Ins.size() &&
7420 "LowerFormalArguments didn't emit the correct number of values!");
7422 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
7423 assert(InVals[i].getNode() &&
7424 "LowerFormalArguments emitted a null value!");
7425 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
7426 "LowerFormalArguments emitted a value with the wrong type!");
7430 // Update the DAG with the new chain value resulting from argument lowering.
7431 DAG.setRoot(NewRoot);
7433 // Set up the argument values.
7436 if (!FuncInfo->CanLowerReturn) {
7437 // Create a virtual register for the sret pointer, and put in a copy
7438 // from the sret argument into it.
7439 SmallVector<EVT, 1> ValueVTs;
7440 ComputeValueVTs(*TLI, DAG.getDataLayout(),
7441 PointerType::getUnqual(F.getReturnType()), ValueVTs);
7442 MVT VT = ValueVTs[0].getSimpleVT();
7443 MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7444 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7445 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1,
7446 RegVT, VT, nullptr, AssertOp);
7448 MachineFunction& MF = SDB->DAG.getMachineFunction();
7449 MachineRegisterInfo& RegInfo = MF.getRegInfo();
7450 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));
7451 FuncInfo->DemoteRegister = SRetReg;
7453 SDB->DAG.getCopyToReg(NewRoot, SDB->getCurSDLoc(), SRetReg, ArgValue);
7454 DAG.setRoot(NewRoot);
7456 // i indexes lowered arguments. Bump it past the hidden sret argument.
7457 // Idx indexes LLVM arguments. Don't touch it.
7461 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
7463 SmallVector<SDValue, 4> ArgValues;
7464 SmallVector<EVT, 4> ValueVTs;
7465 ComputeValueVTs(*TLI, DAG.getDataLayout(), I->getType(), ValueVTs);
7466 unsigned NumValues = ValueVTs.size();
7468 // If this argument is unused then remember its value. It is used to generate
7469 // debugging information.
7470 if (I->use_empty() && NumValues) {
7471 SDB->setUnusedArgValue(&*I, InVals[i]);
7473 // Also remember any frame index for use in FastISel.
7474 if (FrameIndexSDNode *FI =
7475 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
7476 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7479 for (unsigned Val = 0; Val != NumValues; ++Val) {
7480 EVT VT = ValueVTs[Val];
7481 MVT PartVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7482 unsigned NumParts = TLI->getNumRegisters(*CurDAG->getContext(), VT);
7484 if (!I->use_empty()) {
7485 ISD::NodeType AssertOp = ISD::DELETED_NODE;
7486 if (F.getAttributes().hasAttribute(Idx, Attribute::SExt))
7487 AssertOp = ISD::AssertSext;
7488 else if (F.getAttributes().hasAttribute(Idx, Attribute::ZExt))
7489 AssertOp = ISD::AssertZext;
7491 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i],
7492 NumParts, PartVT, VT,
7493 nullptr, AssertOp));
7499 // We don't need to do anything else for unused arguments.
7500 if (ArgValues.empty())
7503 // Note down frame index.
7504 if (FrameIndexSDNode *FI =
7505 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
7506 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7508 SDValue Res = DAG.getMergeValues(makeArrayRef(ArgValues.data(), NumValues),
7509 SDB->getCurSDLoc());
7511 SDB->setValue(&*I, Res);
7512 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) {
7513 if (LoadSDNode *LNode =
7514 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode()))
7515 if (FrameIndexSDNode *FI =
7516 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
7517 FuncInfo->setArgumentFrameIndex(&*I, FI->getIndex());
7520 // If this argument is live outside of the entry block, insert a copy from
7521 // wherever we got it to the vreg that other BB's will reference it as.
7522 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) {
7523 // If we can, though, try to skip creating an unnecessary vreg.
7524 // FIXME: This isn't very clean... it would be nice to make this more
7525 // general. It's also subtly incompatible with the hacks FastISel
7527 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg();
7528 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
7529 FuncInfo->ValueMap[&*I] = Reg;
7533 if (!isOnlyUsedInEntryBlock(&*I, TM.Options.EnableFastISel)) {
7534 FuncInfo->InitializeRegForValue(&*I);
7535 SDB->CopyToExportRegsIfNeeded(&*I);
7539 assert(i == InVals.size() && "Argument register count mismatch!");
7541 // Finally, if the target has anything special to do, allow it to do so.
7542 EmitFunctionEntryCode();
7545 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
7546 /// ensure constants are generated when needed. Remember the virtual registers
7547 /// that need to be added to the Machine PHI nodes as input. We cannot just
7548 /// directly add them, because expansion might result in multiple MBB's for one
7549 /// BB. As such, the start of the BB might correspond to a different MBB than
7553 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
7554 const TerminatorInst *TI = LLVMBB->getTerminator();
7556 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
7558 // Check PHI nodes in successors that expect a value to be available from this
7560 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
7561 const BasicBlock *SuccBB = TI->getSuccessor(succ);
7562 if (!isa<PHINode>(SuccBB->begin())) continue;
7563 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
7565 // If this terminator has multiple identical successors (common for
7566 // switches), only handle each succ once.
7567 if (!SuccsHandled.insert(SuccMBB).second)
7570 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
7572 // At this point we know that there is a 1-1 correspondence between LLVM PHI
7573 // nodes and Machine PHI nodes, but the incoming operands have not been
7575 for (BasicBlock::const_iterator I = SuccBB->begin();
7576 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
7577 // Ignore dead phi's.
7578 if (PN->use_empty()) continue;
7581 if (PN->getType()->isEmptyTy())
7585 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
7587 if (const Constant *C = dyn_cast<Constant>(PHIOp)) {
7588 unsigned &RegOut = ConstantsOut[C];
7590 RegOut = FuncInfo.CreateRegs(C->getType());
7591 CopyValueToVirtualRegister(C, RegOut);
7595 DenseMap<const Value *, unsigned>::iterator I =
7596 FuncInfo.ValueMap.find(PHIOp);
7597 if (I != FuncInfo.ValueMap.end())
7600 assert(isa<AllocaInst>(PHIOp) &&
7601 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) &&
7602 "Didn't codegen value into a register!??");
7603 Reg = FuncInfo.CreateRegs(PHIOp->getType());
7604 CopyValueToVirtualRegister(PHIOp, Reg);
7608 // Remember that this register needs to added to the machine PHI node as
7609 // the input for this MBB.
7610 SmallVector<EVT, 4> ValueVTs;
7611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7612 ComputeValueVTs(TLI, DAG.getDataLayout(), PN->getType(), ValueVTs);
7613 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
7614 EVT VT = ValueVTs[vti];
7615 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT);
7616 for (unsigned i = 0, e = NumRegisters; i != e; ++i)
7617 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
7618 Reg += NumRegisters;
7623 ConstantsOut.clear();
7626 /// Add a successor MBB to ParentMBB< creating a new MachineBB for BB if SuccMBB
7629 SelectionDAGBuilder::StackProtectorDescriptor::
7630 AddSuccessorMBB(const BasicBlock *BB,
7631 MachineBasicBlock *ParentMBB,
7633 MachineBasicBlock *SuccMBB) {
7634 // If SuccBB has not been created yet, create it.
7636 MachineFunction *MF = ParentMBB->getParent();
7637 MachineFunction::iterator BBI(ParentMBB);
7638 SuccMBB = MF->CreateMachineBasicBlock(BB);
7639 MF->insert(++BBI, SuccMBB);
7641 // Add it as a successor of ParentMBB.
7642 ParentMBB->addSuccessor(
7643 SuccMBB, BranchProbabilityInfo::getBranchWeightStackProtector(IsLikely));
7647 MachineBasicBlock *SelectionDAGBuilder::NextBlock(MachineBasicBlock *MBB) {
7648 MachineFunction::iterator I(MBB);
7649 if (++I == FuncInfo.MF->end())
7654 /// During lowering new call nodes can be created (such as memset, etc.).
7655 /// Those will become new roots of the current DAG, but complications arise
7656 /// when they are tail calls. In such cases, the call lowering will update
7657 /// the root, but the builder still needs to know that a tail call has been
7658 /// lowered in order to avoid generating an additional return.
7659 void SelectionDAGBuilder::updateDAGForMaybeTailCall(SDValue MaybeTC) {
7660 // If the node is null, we do have a tail call.
7661 if (MaybeTC.getNode() != nullptr)
7662 DAG.setRoot(MaybeTC);
7667 bool SelectionDAGBuilder::isDense(const CaseClusterVector &Clusters,
7668 unsigned *TotalCases, unsigned First,
7670 assert(Last >= First);
7671 assert(TotalCases[Last] >= TotalCases[First]);
7673 APInt LowCase = Clusters[First].Low->getValue();
7674 APInt HighCase = Clusters[Last].High->getValue();
7675 assert(LowCase.getBitWidth() == HighCase.getBitWidth());
7677 // FIXME: A range of consecutive cases has 100% density, but only requires one
7678 // comparison to lower. We should discriminate against such consecutive ranges
7681 uint64_t Diff = (HighCase - LowCase).getLimitedValue((UINT64_MAX - 1) / 100);
7682 uint64_t Range = Diff + 1;
7685 TotalCases[Last] - (First == 0 ? 0 : TotalCases[First - 1]);
7687 assert(NumCases < UINT64_MAX / 100);
7688 assert(Range >= NumCases);
7690 return NumCases * 100 >= Range * MinJumpTableDensity;
7693 static inline bool areJTsAllowed(const TargetLowering &TLI) {
7694 return TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
7695 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
7698 bool SelectionDAGBuilder::buildJumpTable(CaseClusterVector &Clusters,
7699 unsigned First, unsigned Last,
7700 const SwitchInst *SI,
7701 MachineBasicBlock *DefaultMBB,
7702 CaseCluster &JTCluster) {
7703 assert(First <= Last);
7705 uint32_t Weight = 0;
7706 unsigned NumCmps = 0;
7707 std::vector<MachineBasicBlock*> Table;
7708 DenseMap<MachineBasicBlock*, uint32_t> JTWeights;
7709 for (unsigned I = First; I <= Last; ++I) {
7710 assert(Clusters[I].Kind == CC_Range);
7711 Weight += Clusters[I].Weight;
7712 assert(Weight >= Clusters[I].Weight && "Weight overflow!");
7713 APInt Low = Clusters[I].Low->getValue();
7714 APInt High = Clusters[I].High->getValue();
7715 NumCmps += (Low == High) ? 1 : 2;
7717 // Fill the gap between this and the previous cluster.
7718 APInt PreviousHigh = Clusters[I - 1].High->getValue();
7719 assert(PreviousHigh.slt(Low));
7720 uint64_t Gap = (Low - PreviousHigh).getLimitedValue() - 1;
7721 for (uint64_t J = 0; J < Gap; J++)
7722 Table.push_back(DefaultMBB);
7724 uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
7725 for (uint64_t J = 0; J < ClusterSize; ++J)
7726 Table.push_back(Clusters[I].MBB);
7727 JTWeights[Clusters[I].MBB] += Clusters[I].Weight;
7730 unsigned NumDests = JTWeights.size();
7731 if (isSuitableForBitTests(NumDests, NumCmps,
7732 Clusters[First].Low->getValue(),
7733 Clusters[Last].High->getValue())) {
7734 // Clusters[First..Last] should be lowered as bit tests instead.
7738 // Create the MBB that will load from and jump through the table.
7739 // Note: We create it here, but it's not inserted into the function yet.
7740 MachineFunction *CurMF = FuncInfo.MF;
7741 MachineBasicBlock *JumpTableMBB =
7742 CurMF->CreateMachineBasicBlock(SI->getParent());
7744 // Add successors. Note: use table order for determinism.
7745 SmallPtrSet<MachineBasicBlock *, 8> Done;
7746 for (MachineBasicBlock *Succ : Table) {
7747 if (Done.count(Succ))
7749 addSuccessorWithWeight(JumpTableMBB, Succ, JTWeights[Succ]);
7753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7754 unsigned JTI = CurMF->getOrCreateJumpTableInfo(TLI.getJumpTableEncoding())
7755 ->createJumpTableIndex(Table);
7757 // Set up the jump table info.
7758 JumpTable JT(-1U, JTI, JumpTableMBB, nullptr);
7759 JumpTableHeader JTH(Clusters[First].Low->getValue(),
7760 Clusters[Last].High->getValue(), SI->getCondition(),
7762 JTCases.emplace_back(std::move(JTH), std::move(JT));
7764 JTCluster = CaseCluster::jumpTable(Clusters[First].Low, Clusters[Last].High,
7765 JTCases.size() - 1, Weight);
7769 void SelectionDAGBuilder::findJumpTables(CaseClusterVector &Clusters,
7770 const SwitchInst *SI,
7771 MachineBasicBlock *DefaultMBB) {
7773 // Clusters must be non-empty, sorted, and only contain Range clusters.
7774 assert(!Clusters.empty());
7775 for (CaseCluster &C : Clusters)
7776 assert(C.Kind == CC_Range);
7777 for (unsigned i = 1, e = Clusters.size(); i < e; ++i)
7778 assert(Clusters[i - 1].High->getValue().slt(Clusters[i].Low->getValue()));
7781 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7782 if (!areJTsAllowed(TLI))
7785 const int64_t N = Clusters.size();
7786 const unsigned MinJumpTableSize = TLI.getMinimumJumpTableEntries();
7788 // TotalCases[i]: Total nbr of cases in Clusters[0..i].
7789 SmallVector<unsigned, 8> TotalCases(N);
7791 for (unsigned i = 0; i < N; ++i) {
7792 APInt Hi = Clusters[i].High->getValue();
7793 APInt Lo = Clusters[i].Low->getValue();
7794 TotalCases[i] = (Hi - Lo).getLimitedValue() + 1;
7796 TotalCases[i] += TotalCases[i - 1];
7799 if (N >= MinJumpTableSize && isDense(Clusters, &TotalCases[0], 0, N - 1)) {
7800 // Cheap case: the whole range might be suitable for jump table.
7801 CaseCluster JTCluster;
7802 if (buildJumpTable(Clusters, 0, N - 1, SI, DefaultMBB, JTCluster)) {
7803 Clusters[0] = JTCluster;
7809 // The algorithm below is not suitable for -O0.
7810 if (TM.getOptLevel() == CodeGenOpt::None)
7813 // Split Clusters into minimum number of dense partitions. The algorithm uses
7814 // the same idea as Kannan & Proebsting "Correction to 'Producing Good Code
7815 // for the Case Statement'" (1994), but builds the MinPartitions array in
7816 // reverse order to make it easier to reconstruct the partitions in ascending
7817 // order. In the choice between two optimal partitionings, it picks the one
7818 // which yields more jump tables.
7820 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
7821 SmallVector<unsigned, 8> MinPartitions(N);
7822 // LastElement[i] is the last element of the partition starting at i.
7823 SmallVector<unsigned, 8> LastElement(N);
7824 // NumTables[i]: nbr of >= MinJumpTableSize partitions from Clusters[i..N-1].
7825 SmallVector<unsigned, 8> NumTables(N);
7827 // Base case: There is only one way to partition Clusters[N-1].
7828 MinPartitions[N - 1] = 1;
7829 LastElement[N - 1] = N - 1;
7830 assert(MinJumpTableSize > 1);
7831 NumTables[N - 1] = 0;
7833 // Note: loop indexes are signed to avoid underflow.
7834 for (int64_t i = N - 2; i >= 0; i--) {
7835 // Find optimal partitioning of Clusters[i..N-1].
7836 // Baseline: Put Clusters[i] into a partition on its own.
7837 MinPartitions[i] = MinPartitions[i + 1] + 1;
7839 NumTables[i] = NumTables[i + 1];
7841 // Search for a solution that results in fewer partitions.
7842 for (int64_t j = N - 1; j > i; j--) {
7843 // Try building a partition from Clusters[i..j].
7844 if (isDense(Clusters, &TotalCases[0], i, j)) {
7845 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
7846 bool IsTable = j - i + 1 >= MinJumpTableSize;
7847 unsigned Tables = IsTable + (j == N - 1 ? 0 : NumTables[j + 1]);
7849 // If this j leads to fewer partitions, or same number of partitions
7850 // with more lookup tables, it is a better partitioning.
7851 if (NumPartitions < MinPartitions[i] ||
7852 (NumPartitions == MinPartitions[i] && Tables > NumTables[i])) {
7853 MinPartitions[i] = NumPartitions;
7855 NumTables[i] = Tables;
7861 // Iterate over the partitions, replacing some with jump tables in-place.
7862 unsigned DstIndex = 0;
7863 for (unsigned First = 0, Last; First < N; First = Last + 1) {
7864 Last = LastElement[First];
7865 assert(Last >= First);
7866 assert(DstIndex <= First);
7867 unsigned NumClusters = Last - First + 1;
7869 CaseCluster JTCluster;
7870 if (NumClusters >= MinJumpTableSize &&
7871 buildJumpTable(Clusters, First, Last, SI, DefaultMBB, JTCluster)) {
7872 Clusters[DstIndex++] = JTCluster;
7874 for (unsigned I = First; I <= Last; ++I)
7875 std::memmove(&Clusters[DstIndex++], &Clusters[I], sizeof(Clusters[I]));
7878 Clusters.resize(DstIndex);
7881 bool SelectionDAGBuilder::rangeFitsInWord(const APInt &Low, const APInt &High) {
7882 // FIXME: Using the pointer type doesn't seem ideal.
7883 uint64_t BW = DAG.getDataLayout().getPointerSizeInBits();
7884 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
7888 bool SelectionDAGBuilder::isSuitableForBitTests(unsigned NumDests,
7891 const APInt &High) {
7892 // FIXME: I don't think NumCmps is the correct metric: a single case and a
7893 // range of cases both require only one branch to lower. Just looking at the
7894 // number of clusters and destinations should be enough to decide whether to
7897 // To lower a range with bit tests, the range must fit the bitwidth of a
7899 if (!rangeFitsInWord(Low, High))
7902 // Decide whether it's profitable to lower this range with bit tests. Each
7903 // destination requires a bit test and branch, and there is an overall range
7904 // check branch. For a small number of clusters, separate comparisons might be
7905 // cheaper, and for many destinations, splitting the range might be better.
7906 return (NumDests == 1 && NumCmps >= 3) ||
7907 (NumDests == 2 && NumCmps >= 5) ||
7908 (NumDests == 3 && NumCmps >= 6);
7911 bool SelectionDAGBuilder::buildBitTests(CaseClusterVector &Clusters,
7912 unsigned First, unsigned Last,
7913 const SwitchInst *SI,
7914 CaseCluster &BTCluster) {
7915 assert(First <= Last);
7919 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
7920 unsigned NumCmps = 0;
7921 for (int64_t I = First; I <= Last; ++I) {
7922 assert(Clusters[I].Kind == CC_Range);
7923 Dests.set(Clusters[I].MBB->getNumber());
7924 NumCmps += (Clusters[I].Low == Clusters[I].High) ? 1 : 2;
7926 unsigned NumDests = Dests.count();
7928 APInt Low = Clusters[First].Low->getValue();
7929 APInt High = Clusters[Last].High->getValue();
7930 assert(Low.slt(High));
7932 if (!isSuitableForBitTests(NumDests, NumCmps, Low, High))
7938 const int BitWidth = DAG.getTargetLoweringInfo()
7939 .getPointerTy(DAG.getDataLayout())
7941 assert(rangeFitsInWord(Low, High) && "Case range must fit in bit mask!");
7943 // Check if the clusters cover a contiguous range such that no value in the
7944 // range will jump to the default statement.
7945 bool ContiguousRange = true;
7946 for (int64_t I = First + 1; I <= Last; ++I) {
7947 if (Clusters[I].Low->getValue() != Clusters[I - 1].High->getValue() + 1) {
7948 ContiguousRange = false;
7953 if (Low.isStrictlyPositive() && High.slt(BitWidth)) {
7954 // Optimize the case where all the case values fit in a word without having
7955 // to subtract minValue. In this case, we can optimize away the subtraction.
7956 LowBound = APInt::getNullValue(Low.getBitWidth());
7958 ContiguousRange = false;
7961 CmpRange = High - Low;
7965 uint32_t TotalWeight = 0;
7966 for (unsigned i = First; i <= Last; ++i) {
7967 // Find the CaseBits for this destination.
7969 for (j = 0; j < CBV.size(); ++j)
7970 if (CBV[j].BB == Clusters[i].MBB)
7972 if (j == CBV.size())
7973 CBV.push_back(CaseBits(0, Clusters[i].MBB, 0, 0));
7974 CaseBits *CB = &CBV[j];
7976 // Update Mask, Bits and ExtraWeight.
7977 uint64_t Lo = (Clusters[i].Low->getValue() - LowBound).getZExtValue();
7978 uint64_t Hi = (Clusters[i].High->getValue() - LowBound).getZExtValue();
7979 assert(Hi >= Lo && Hi < 64 && "Invalid bit case!");
7980 CB->Mask |= (-1ULL >> (63 - (Hi - Lo))) << Lo;
7981 CB->Bits += Hi - Lo + 1;
7982 CB->ExtraWeight += Clusters[i].Weight;
7983 TotalWeight += Clusters[i].Weight;
7984 assert(TotalWeight >= Clusters[i].Weight && "Weight overflow!");
7988 std::sort(CBV.begin(), CBV.end(), [](const CaseBits &a, const CaseBits &b) {
7989 // Sort by weight first, number of bits second.
7990 if (a.ExtraWeight != b.ExtraWeight)
7991 return a.ExtraWeight > b.ExtraWeight;
7992 return a.Bits > b.Bits;
7995 for (auto &CB : CBV) {
7996 MachineBasicBlock *BitTestBB =
7997 FuncInfo.MF->CreateMachineBasicBlock(SI->getParent());
7998 BTI.push_back(BitTestCase(CB.Mask, BitTestBB, CB.BB, CB.ExtraWeight));
8000 BitTestCases.emplace_back(std::move(LowBound), std::move(CmpRange),
8001 SI->getCondition(), -1U, MVT::Other, false,
8002 ContiguousRange, nullptr, nullptr, std::move(BTI),
8005 BTCluster = CaseCluster::bitTests(Clusters[First].Low, Clusters[Last].High,
8006 BitTestCases.size() - 1, TotalWeight);
8010 void SelectionDAGBuilder::findBitTestClusters(CaseClusterVector &Clusters,
8011 const SwitchInst *SI) {
8012 // Partition Clusters into as few subsets as possible, where each subset has a
8013 // range that fits in a machine word and has <= 3 unique destinations.
8016 // Clusters must be sorted and contain Range or JumpTable clusters.
8017 assert(!Clusters.empty());
8018 assert(Clusters[0].Kind == CC_Range || Clusters[0].Kind == CC_JumpTable);
8019 for (const CaseCluster &C : Clusters)
8020 assert(C.Kind == CC_Range || C.Kind == CC_JumpTable);
8021 for (unsigned i = 1; i < Clusters.size(); ++i)
8022 assert(Clusters[i-1].High->getValue().slt(Clusters[i].Low->getValue()));
8025 // The algorithm below is not suitable for -O0.
8026 if (TM.getOptLevel() == CodeGenOpt::None)
8029 // If target does not have legal shift left, do not emit bit tests at all.
8030 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8031 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
8032 if (!TLI.isOperationLegal(ISD::SHL, PTy))
8035 int BitWidth = PTy.getSizeInBits();
8036 const int64_t N = Clusters.size();
8038 // MinPartitions[i] is the minimum nbr of partitions of Clusters[i..N-1].
8039 SmallVector<unsigned, 8> MinPartitions(N);
8040 // LastElement[i] is the last element of the partition starting at i.
8041 SmallVector<unsigned, 8> LastElement(N);
8043 // FIXME: This might not be the best algorithm for finding bit test clusters.
8045 // Base case: There is only one way to partition Clusters[N-1].
8046 MinPartitions[N - 1] = 1;
8047 LastElement[N - 1] = N - 1;
8049 // Note: loop indexes are signed to avoid underflow.
8050 for (int64_t i = N - 2; i >= 0; --i) {
8051 // Find optimal partitioning of Clusters[i..N-1].
8052 // Baseline: Put Clusters[i] into a partition on its own.
8053 MinPartitions[i] = MinPartitions[i + 1] + 1;
8056 // Search for a solution that results in fewer partitions.
8057 // Note: the search is limited by BitWidth, reducing time complexity.
8058 for (int64_t j = std::min(N - 1, i + BitWidth - 1); j > i; --j) {
8059 // Try building a partition from Clusters[i..j].
8062 if (!rangeFitsInWord(Clusters[i].Low->getValue(),
8063 Clusters[j].High->getValue()))
8066 // Check nbr of destinations and cluster types.
8067 // FIXME: This works, but doesn't seem very efficient.
8068 bool RangesOnly = true;
8069 BitVector Dests(FuncInfo.MF->getNumBlockIDs());
8070 for (int64_t k = i; k <= j; k++) {
8071 if (Clusters[k].Kind != CC_Range) {
8075 Dests.set(Clusters[k].MBB->getNumber());
8077 if (!RangesOnly || Dests.count() > 3)
8080 // Check if it's a better partition.
8081 unsigned NumPartitions = 1 + (j == N - 1 ? 0 : MinPartitions[j + 1]);
8082 if (NumPartitions < MinPartitions[i]) {
8083 // Found a better partition.
8084 MinPartitions[i] = NumPartitions;
8090 // Iterate over the partitions, replacing with bit-test clusters in-place.
8091 unsigned DstIndex = 0;
8092 for (unsigned First = 0, Last; First < N; First = Last + 1) {
8093 Last = LastElement[First];
8094 assert(First <= Last);
8095 assert(DstIndex <= First);
8097 CaseCluster BitTestCluster;
8098 if (buildBitTests(Clusters, First, Last, SI, BitTestCluster)) {
8099 Clusters[DstIndex++] = BitTestCluster;
8101 size_t NumClusters = Last - First + 1;
8102 std::memmove(&Clusters[DstIndex], &Clusters[First],
8103 sizeof(Clusters[0]) * NumClusters);
8104 DstIndex += NumClusters;
8107 Clusters.resize(DstIndex);
8110 void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond,
8111 MachineBasicBlock *SwitchMBB,
8112 MachineBasicBlock *DefaultMBB) {
8113 MachineFunction *CurMF = FuncInfo.MF;
8114 MachineBasicBlock *NextMBB = nullptr;
8115 MachineFunction::iterator BBI(W.MBB);
8116 if (++BBI != FuncInfo.MF->end())
8119 unsigned Size = W.LastCluster - W.FirstCluster + 1;
8121 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8123 if (Size == 2 && W.MBB == SwitchMBB) {
8124 // If any two of the cases has the same destination, and if one value
8125 // is the same as the other, but has one bit unset that the other has set,
8126 // use bit manipulation to do two compares at once. For example:
8127 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)"
8128 // TODO: This could be extended to merge any 2 cases in switches with 3
8130 // TODO: Handle cases where W.CaseBB != SwitchBB.
8131 CaseCluster &Small = *W.FirstCluster;
8132 CaseCluster &Big = *W.LastCluster;
8134 if (Small.Low == Small.High && Big.Low == Big.High &&
8135 Small.MBB == Big.MBB) {
8136 const APInt &SmallValue = Small.Low->getValue();
8137 const APInt &BigValue = Big.Low->getValue();
8139 // Check that there is only one bit different.
8140 APInt CommonBit = BigValue ^ SmallValue;
8141 if (CommonBit.isPowerOf2()) {
8142 SDValue CondLHS = getValue(Cond);
8143 EVT VT = CondLHS.getValueType();
8144 SDLoc DL = getCurSDLoc();
8146 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS,
8147 DAG.getConstant(CommonBit, DL, VT));
8148 SDValue Cond = DAG.getSetCC(
8149 DL, MVT::i1, Or, DAG.getConstant(BigValue | SmallValue, DL, VT),
8152 // Update successor info.
8153 // Both Small and Big will jump to Small.BB, so we sum up the weights.
8154 addSuccessorWithWeight(SwitchMBB, Small.MBB, Small.Weight + Big.Weight);
8155 addSuccessorWithWeight(
8156 SwitchMBB, DefaultMBB,
8157 // The default destination is the first successor in IR.
8158 BPI ? BPI->getEdgeWeight(SwitchMBB->getBasicBlock(), (unsigned)0)
8161 // Insert the true branch.
8163 DAG.getNode(ISD::BRCOND, DL, MVT::Other, getControlRoot(), Cond,
8164 DAG.getBasicBlock(Small.MBB));
8165 // Insert the false branch.
8166 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond,
8167 DAG.getBasicBlock(DefaultMBB));
8169 DAG.setRoot(BrCond);
8175 if (TM.getOptLevel() != CodeGenOpt::None) {
8176 // Order cases by weight so the most likely case will be checked first.
8177 std::sort(W.FirstCluster, W.LastCluster + 1,
8178 [](const CaseCluster &a, const CaseCluster &b) {
8179 return a.Weight > b.Weight;
8182 // Rearrange the case blocks so that the last one falls through if possible
8183 // without without changing the order of weights.
8184 for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster; ) {
8186 if (I->Weight > W.LastCluster->Weight)
8188 if (I->Kind == CC_Range && I->MBB == NextMBB) {
8189 std::swap(*I, *W.LastCluster);
8195 // Compute total weight.
8196 uint32_t DefaultWeight = W.DefaultWeight;
8197 uint32_t UnhandledWeights = DefaultWeight;
8198 for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I) {
8199 UnhandledWeights += I->Weight;
8200 assert(UnhandledWeights >= I->Weight && "Weight overflow!");
8203 MachineBasicBlock *CurMBB = W.MBB;
8204 for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
8205 MachineBasicBlock *Fallthrough;
8206 if (I == W.LastCluster) {
8207 // For the last cluster, fall through to the default destination.
8208 Fallthrough = DefaultMBB;
8210 Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
8211 CurMF->insert(BBI, Fallthrough);
8212 // Put Cond in a virtual register to make it available from the new blocks.
8213 ExportFromCurrentBlock(Cond);
8215 UnhandledWeights -= I->Weight;
8218 case CC_JumpTable: {
8219 // FIXME: Optimize away range check based on pivot comparisons.
8220 JumpTableHeader *JTH = &JTCases[I->JTCasesIndex].first;
8221 JumpTable *JT = &JTCases[I->JTCasesIndex].second;
8223 // The jump block hasn't been inserted yet; insert it here.
8224 MachineBasicBlock *JumpMBB = JT->MBB;
8225 CurMF->insert(BBI, JumpMBB);
8227 uint32_t JumpWeight = I->Weight;
8228 uint32_t FallthroughWeight = UnhandledWeights;
8230 // If the default statement is a target of the jump table, we evenly
8231 // distribute the default weight to successors of CurMBB. Also update
8232 // the weight on the edge from JumpMBB to Fallthrough.
8233 for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
8234 SE = JumpMBB->succ_end();
8236 if (*SI == DefaultMBB) {
8237 JumpWeight += DefaultWeight / 2;
8238 FallthroughWeight -= DefaultWeight / 2;
8239 JumpMBB->setSuccWeight(SI, DefaultWeight / 2);
8244 addSuccessorWithWeight(CurMBB, Fallthrough, FallthroughWeight);
8245 addSuccessorWithWeight(CurMBB, JumpMBB, JumpWeight);
8247 // The jump table header will be inserted in our current block, do the
8248 // range check, and fall through to our fallthrough block.
8249 JTH->HeaderBB = CurMBB;
8250 JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
8252 // If we're in the right place, emit the jump table header right now.
8253 if (CurMBB == SwitchMBB) {
8254 visitJumpTableHeader(*JT, *JTH, SwitchMBB);
8255 JTH->Emitted = true;
8260 // FIXME: Optimize away range check based on pivot comparisons.
8261 BitTestBlock *BTB = &BitTestCases[I->BTCasesIndex];
8263 // The bit test blocks haven't been inserted yet; insert them here.
8264 for (BitTestCase &BTC : BTB->Cases)
8265 CurMF->insert(BBI, BTC.ThisBB);
8267 // Fill in fields of the BitTestBlock.
8268 BTB->Parent = CurMBB;
8269 BTB->Default = Fallthrough;
8271 BTB->DefaultWeight = UnhandledWeights;
8272 // If the cases in bit test don't form a contiguous range, we evenly
8273 // distribute the weight on the edge to Fallthrough to two successors
8275 if (!BTB->ContiguousRange) {
8276 BTB->Weight += DefaultWeight / 2;
8277 BTB->DefaultWeight -= DefaultWeight / 2;
8280 // If we're in the right place, emit the bit test header right now.
8281 if (CurMBB == SwitchMBB) {
8282 visitBitTestHeader(*BTB, SwitchMBB);
8283 BTB->Emitted = true;
8288 const Value *RHS, *LHS, *MHS;
8290 if (I->Low == I->High) {
8291 // Check Cond == I->Low.
8297 // Check I->Low <= Cond <= I->High.
8304 // The false weight is the sum of all unhandled cases.
8305 CaseBlock CB(CC, LHS, RHS, MHS, I->MBB, Fallthrough, CurMBB, I->Weight,
8308 if (CurMBB == SwitchMBB)
8309 visitSwitchCase(CB, SwitchMBB);
8311 SwitchCases.push_back(CB);
8316 CurMBB = Fallthrough;
8320 unsigned SelectionDAGBuilder::caseClusterRank(const CaseCluster &CC,
8321 CaseClusterIt First,
8322 CaseClusterIt Last) {
8323 return std::count_if(First, Last + 1, [&](const CaseCluster &X) {
8324 if (X.Weight != CC.Weight)
8325 return X.Weight > CC.Weight;
8327 // Ties are broken by comparing the case value.
8328 return X.Low->getValue().slt(CC.Low->getValue());
8332 void SelectionDAGBuilder::splitWorkItem(SwitchWorkList &WorkList,
8333 const SwitchWorkListItem &W,
8335 MachineBasicBlock *SwitchMBB) {
8336 assert(W.FirstCluster->Low->getValue().slt(W.LastCluster->Low->getValue()) &&
8337 "Clusters not sorted?");
8339 assert(W.LastCluster - W.FirstCluster + 1 >= 2 && "Too small to split!");
8341 // Balance the tree based on branch weights to create a near-optimal (in terms
8342 // of search time given key frequency) binary search tree. See e.g. Kurt
8343 // Mehlhorn "Nearly Optimal Binary Search Trees" (1975).
8344 CaseClusterIt LastLeft = W.FirstCluster;
8345 CaseClusterIt FirstRight = W.LastCluster;
8346 uint32_t LeftWeight = LastLeft->Weight + W.DefaultWeight / 2;
8347 uint32_t RightWeight = FirstRight->Weight + W.DefaultWeight / 2;
8349 // Move LastLeft and FirstRight towards each other from opposite directions to
8350 // find a partitioning of the clusters which balances the weight on both
8351 // sides. If LeftWeight and RightWeight are equal, alternate which side is
8352 // taken to ensure 0-weight nodes are distributed evenly.
8354 while (LastLeft + 1 < FirstRight) {
8355 if (LeftWeight < RightWeight || (LeftWeight == RightWeight && (I & 1)))
8356 LeftWeight += (++LastLeft)->Weight;
8358 RightWeight += (--FirstRight)->Weight;
8363 // Our binary search tree differs from a typical BST in that ours can have up
8364 // to three values in each leaf. The pivot selection above doesn't take that
8365 // into account, which means the tree might require more nodes and be less
8366 // efficient. We compensate for this here.
8368 unsigned NumLeft = LastLeft - W.FirstCluster + 1;
8369 unsigned NumRight = W.LastCluster - FirstRight + 1;
8371 if (std::min(NumLeft, NumRight) < 3 && std::max(NumLeft, NumRight) > 3) {
8372 // If one side has less than 3 clusters, and the other has more than 3,
8373 // consider taking a cluster from the other side.
8375 if (NumLeft < NumRight) {
8376 // Consider moving the first cluster on the right to the left side.
8377 CaseCluster &CC = *FirstRight;
8378 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8379 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8380 if (LeftSideRank <= RightSideRank) {
8381 // Moving the cluster to the left does not demote it.
8387 assert(NumRight < NumLeft);
8388 // Consider moving the last element on the left to the right side.
8389 CaseCluster &CC = *LastLeft;
8390 unsigned LeftSideRank = caseClusterRank(CC, W.FirstCluster, LastLeft);
8391 unsigned RightSideRank = caseClusterRank(CC, FirstRight, W.LastCluster);
8392 if (RightSideRank <= LeftSideRank) {
8393 // Moving the cluster to the right does not demot it.
8403 assert(LastLeft + 1 == FirstRight);
8404 assert(LastLeft >= W.FirstCluster);
8405 assert(FirstRight <= W.LastCluster);
8407 // Use the first element on the right as pivot since we will make less-than
8408 // comparisons against it.
8409 CaseClusterIt PivotCluster = FirstRight;
8410 assert(PivotCluster > W.FirstCluster);
8411 assert(PivotCluster <= W.LastCluster);
8413 CaseClusterIt FirstLeft = W.FirstCluster;
8414 CaseClusterIt LastRight = W.LastCluster;
8416 const ConstantInt *Pivot = PivotCluster->Low;
8418 // New blocks will be inserted immediately after the current one.
8419 MachineFunction::iterator BBI(W.MBB);
8422 // We will branch to the LHS if Value < Pivot. If LHS is a single cluster,
8423 // we can branch to its destination directly if it's squeezed exactly in
8424 // between the known lower bound and Pivot - 1.
8425 MachineBasicBlock *LeftMBB;
8426 if (FirstLeft == LastLeft && FirstLeft->Kind == CC_Range &&
8427 FirstLeft->Low == W.GE &&
8428 (FirstLeft->High->getValue() + 1LL) == Pivot->getValue()) {
8429 LeftMBB = FirstLeft->MBB;
8431 LeftMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8432 FuncInfo.MF->insert(BBI, LeftMBB);
8434 {LeftMBB, FirstLeft, LastLeft, W.GE, Pivot, W.DefaultWeight / 2});
8435 // Put Cond in a virtual register to make it available from the new blocks.
8436 ExportFromCurrentBlock(Cond);
8439 // Similarly, we will branch to the RHS if Value >= Pivot. If RHS is a
8440 // single cluster, RHS.Low == Pivot, and we can branch to its destination
8441 // directly if RHS.High equals the current upper bound.
8442 MachineBasicBlock *RightMBB;
8443 if (FirstRight == LastRight && FirstRight->Kind == CC_Range &&
8444 W.LT && (FirstRight->High->getValue() + 1ULL) == W.LT->getValue()) {
8445 RightMBB = FirstRight->MBB;
8447 RightMBB = FuncInfo.MF->CreateMachineBasicBlock(W.MBB->getBasicBlock());
8448 FuncInfo.MF->insert(BBI, RightMBB);
8450 {RightMBB, FirstRight, LastRight, Pivot, W.LT, W.DefaultWeight / 2});
8451 // Put Cond in a virtual register to make it available from the new blocks.
8452 ExportFromCurrentBlock(Cond);
8455 // Create the CaseBlock record that will be used to lower the branch.
8456 CaseBlock CB(ISD::SETLT, Cond, Pivot, nullptr, LeftMBB, RightMBB, W.MBB,
8457 LeftWeight, RightWeight);
8459 if (W.MBB == SwitchMBB)
8460 visitSwitchCase(CB, SwitchMBB);
8462 SwitchCases.push_back(CB);
8465 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
8466 // Extract cases from the switch.
8467 BranchProbabilityInfo *BPI = FuncInfo.BPI;
8468 CaseClusterVector Clusters;
8469 Clusters.reserve(SI.getNumCases());
8470 for (auto I : SI.cases()) {
8471 MachineBasicBlock *Succ = FuncInfo.MBBMap[I.getCaseSuccessor()];
8472 const ConstantInt *CaseVal = I.getCaseValue();
8474 BPI ? BPI->getEdgeWeight(SI.getParent(), I.getSuccessorIndex()) : 0;
8475 Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Weight));
8478 MachineBasicBlock *DefaultMBB = FuncInfo.MBBMap[SI.getDefaultDest()];
8480 // Cluster adjacent cases with the same destination. We do this at all
8481 // optimization levels because it's cheap to do and will make codegen faster
8482 // if there are many clusters.
8483 sortAndRangeify(Clusters);
8485 if (TM.getOptLevel() != CodeGenOpt::None) {
8486 // Replace an unreachable default with the most popular destination.
8487 // FIXME: Exploit unreachable default more aggressively.
8488 bool UnreachableDefault =
8489 isa<UnreachableInst>(SI.getDefaultDest()->getFirstNonPHIOrDbg());
8490 if (UnreachableDefault && !Clusters.empty()) {
8491 DenseMap<const BasicBlock *, unsigned> Popularity;
8492 unsigned MaxPop = 0;
8493 const BasicBlock *MaxBB = nullptr;
8494 for (auto I : SI.cases()) {
8495 const BasicBlock *BB = I.getCaseSuccessor();
8496 if (++Popularity[BB] > MaxPop) {
8497 MaxPop = Popularity[BB];
8502 assert(MaxPop > 0 && MaxBB);
8503 DefaultMBB = FuncInfo.MBBMap[MaxBB];
8505 // Remove cases that were pointing to the destination that is now the
8507 CaseClusterVector New;
8508 New.reserve(Clusters.size());
8509 for (CaseCluster &CC : Clusters) {
8510 if (CC.MBB != DefaultMBB)
8513 Clusters = std::move(New);
8517 // If there is only the default destination, jump there directly.
8518 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
8519 if (Clusters.empty()) {
8520 SwitchMBB->addSuccessor(DefaultMBB);
8521 if (DefaultMBB != NextBlock(SwitchMBB)) {
8522 DAG.setRoot(DAG.getNode(ISD::BR, getCurSDLoc(), MVT::Other,
8523 getControlRoot(), DAG.getBasicBlock(DefaultMBB)));
8528 findJumpTables(Clusters, &SI, DefaultMBB);
8529 findBitTestClusters(Clusters, &SI);
8532 dbgs() << "Case clusters: ";
8533 for (const CaseCluster &C : Clusters) {
8534 if (C.Kind == CC_JumpTable) dbgs() << "JT:";
8535 if (C.Kind == CC_BitTests) dbgs() << "BT:";
8537 C.Low->getValue().print(dbgs(), true);
8538 if (C.Low != C.High) {
8540 C.High->getValue().print(dbgs(), true);
8547 assert(!Clusters.empty());
8548 SwitchWorkList WorkList;
8549 CaseClusterIt First = Clusters.begin();
8550 CaseClusterIt Last = Clusters.end() - 1;
8551 uint32_t DefaultWeight = getEdgeWeight(SwitchMBB, DefaultMBB);
8552 WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultWeight});
8554 while (!WorkList.empty()) {
8555 SwitchWorkListItem W = WorkList.back();
8556 WorkList.pop_back();
8557 unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
8559 if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None) {
8560 // For optimized builds, lower large range as a balanced binary tree.
8561 splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
8565 lowerWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB);