1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in two vectors of half the size. For example, implementing
19 // <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "legalize-types"
31 //===----------------------------------------------------------------------===//
32 // Result Vector Scalarization: <1 x ty> -> ty.
33 //===----------------------------------------------------------------------===//
35 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Scalarize node result " << ResNo << ": ";
39 SDValue R = SDValue();
41 switch (N->getOpcode()) {
44 dbgs() << "ScalarizeVectorResult #" << ResNo << ": ";
48 report_fatal_error("Do not know how to scalarize the result of this "
51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break;
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break;
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
61 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
62 case ISD::SIGN_EXTEND_INREG: R = ScalarizeVecRes_InregOp(N); break;
63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break;
64 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
65 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
67 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
68 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
72 case ISD::CTLZ_ZERO_UNDEF:
75 case ISD::CTTZ_ZERO_UNDEF:
95 case ISD::SIGN_EXTEND:
99 case ISD::ZERO_EXTEND:
100 R = ScalarizeVecRes_UnaryOp(N);
126 R = ScalarizeVecRes_BinOp(N);
129 R = ScalarizeVecRes_TernaryOp(N);
133 // If R is null, the sub-method took care of registering the result.
135 SetScalarizedVector(SDValue(N, ResNo), R);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
139 SDValue LHS = GetScalarizedVector(N->getOperand(0));
140 SDValue RHS = GetScalarizedVector(N->getOperand(1));
141 return DAG.getNode(N->getOpcode(), SDLoc(N),
142 LHS.getValueType(), LHS, RHS);
145 SDValue DAGTypeLegalizer::ScalarizeVecRes_TernaryOp(SDNode *N) {
146 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
147 SDValue Op1 = GetScalarizedVector(N->getOperand(1));
148 SDValue Op2 = GetScalarizedVector(N->getOperand(2));
149 return DAG.getNode(N->getOpcode(), SDLoc(N),
150 Op0.getValueType(), Op0, Op1, Op2);
153 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
155 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
156 return GetScalarizedVector(Op);
159 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
160 EVT NewVT = N->getValueType(0).getVectorElementType();
161 return DAG.getNode(ISD::BITCAST, SDLoc(N),
162 NewVT, N->getOperand(0));
165 SDValue DAGTypeLegalizer::ScalarizeVecRes_BUILD_VECTOR(SDNode *N) {
166 EVT EltVT = N->getValueType(0).getVectorElementType();
167 SDValue InOp = N->getOperand(0);
168 // The BUILD_VECTOR operands may be of wider element types and
169 // we may need to truncate them back to the requested return type.
170 if (EltVT.isInteger())
171 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
175 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
176 EVT NewVT = N->getValueType(0).getVectorElementType();
177 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
178 return DAG.getConvertRndSat(NewVT, SDLoc(N),
179 Op0, DAG.getValueType(NewVT),
180 DAG.getValueType(Op0.getValueType()),
183 cast<CvtRndSatSDNode>(N)->getCvtCode());
186 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
187 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
188 N->getValueType(0).getVectorElementType(),
189 N->getOperand(0), N->getOperand(1));
192 SDValue DAGTypeLegalizer::ScalarizeVecRes_FP_ROUND(SDNode *N) {
193 EVT NewVT = N->getValueType(0).getVectorElementType();
194 SDValue Op = GetScalarizedVector(N->getOperand(0));
195 return DAG.getNode(ISD::FP_ROUND, SDLoc(N),
196 NewVT, Op, N->getOperand(1));
199 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
200 SDValue Op = GetScalarizedVector(N->getOperand(0));
201 return DAG.getNode(ISD::FPOWI, SDLoc(N),
202 Op.getValueType(), Op, N->getOperand(1));
205 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
206 // The value to insert may have a wider type than the vector element type,
207 // so be sure to truncate it to the element type if necessary.
208 SDValue Op = N->getOperand(1);
209 EVT EltVT = N->getValueType(0).getVectorElementType();
210 if (Op.getValueType() != EltVT)
211 // FIXME: Can this happen for floating point types?
212 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, Op);
216 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
217 assert(N->isUnindexed() && "Indexed vector load?");
219 SDValue Result = DAG.getLoad(ISD::UNINDEXED,
220 N->getExtensionType(),
221 N->getValueType(0).getVectorElementType(),
223 N->getChain(), N->getBasePtr(),
224 DAG.getUNDEF(N->getBasePtr().getValueType()),
226 N->getMemoryVT().getVectorElementType(),
227 N->isVolatile(), N->isNonTemporal(),
228 N->isInvariant(), N->getOriginalAlignment(),
231 // Legalized the chain result - switch anything that used the old chain to
233 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
237 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
238 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
239 EVT DestVT = N->getValueType(0).getVectorElementType();
240 SDValue Op = N->getOperand(0);
241 EVT OpVT = Op.getValueType();
243 // The result needs scalarizing, but it's not a given that the source does.
244 // This is a workaround for targets where it's impossible to scalarize the
245 // result of a conversion, because the source type is legal.
246 // For instance, this happens on AArch64: v1i1 is illegal but v1i{8,16,32}
247 // are widened to v8i8, v4i16, and v2i32, which is legal, because v1i64 is
248 // legal and was not scalarized.
249 // See the similar logic in ScalarizeVecRes_VSETCC
250 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
251 Op = GetScalarizedVector(Op);
253 EVT VT = OpVT.getVectorElementType();
254 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op,
255 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
257 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
260 SDValue DAGTypeLegalizer::ScalarizeVecRes_InregOp(SDNode *N) {
261 EVT EltVT = N->getValueType(0).getVectorElementType();
262 EVT ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT().getVectorElementType();
263 SDValue LHS = GetScalarizedVector(N->getOperand(0));
264 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
265 LHS, DAG.getValueType(ExtVT));
268 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
269 // If the operand is wider than the vector element type then it is implicitly
270 // truncated. Make that explicit here.
271 EVT EltVT = N->getValueType(0).getVectorElementType();
272 SDValue InOp = N->getOperand(0);
273 if (InOp.getValueType() != EltVT)
274 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), EltVT, InOp);
278 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
279 SDValue Cond = GetScalarizedVector(N->getOperand(0));
280 SDValue LHS = GetScalarizedVector(N->getOperand(1));
281 TargetLowering::BooleanContent ScalarBool =
282 TLI.getBooleanContents(false, false);
283 TargetLowering::BooleanContent VecBool = TLI.getBooleanContents(true, false);
285 // If integer and float booleans have different contents then we can't
286 // reliably optimize in all cases. There is a full explanation for this in
287 // DAGCombiner::visitSELECT() where the same issue affects folding
288 // (select C, 0, 1) to (xor C, 1).
289 if (TLI.getBooleanContents(false, false) !=
290 TLI.getBooleanContents(false, true)) {
291 // At least try the common case where the boolean is generated by a
293 if (Cond->getOpcode() == ISD::SETCC) {
294 EVT OpVT = Cond->getOperand(0)->getValueType(0);
295 ScalarBool = TLI.getBooleanContents(OpVT.getScalarType());
296 VecBool = TLI.getBooleanContents(OpVT);
298 ScalarBool = TargetLowering::UndefinedBooleanContent;
301 if (ScalarBool != VecBool) {
302 EVT CondVT = Cond.getValueType();
303 switch (ScalarBool) {
304 case TargetLowering::UndefinedBooleanContent:
306 case TargetLowering::ZeroOrOneBooleanContent:
307 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
308 VecBool == TargetLowering::ZeroOrNegativeOneBooleanContent);
309 // Vector read from all ones, scalar expects a single 1 so mask.
310 Cond = DAG.getNode(ISD::AND, SDLoc(N), CondVT,
311 Cond, DAG.getConstant(1, SDLoc(N), CondVT));
313 case TargetLowering::ZeroOrNegativeOneBooleanContent:
314 assert(VecBool == TargetLowering::UndefinedBooleanContent ||
315 VecBool == TargetLowering::ZeroOrOneBooleanContent);
316 // Vector reads from a one, scalar from all ones so sign extend.
317 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), CondVT,
318 Cond, DAG.getValueType(MVT::i1));
323 return DAG.getSelect(SDLoc(N),
324 LHS.getValueType(), Cond, LHS,
325 GetScalarizedVector(N->getOperand(2)));
328 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
329 SDValue LHS = GetScalarizedVector(N->getOperand(1));
330 return DAG.getSelect(SDLoc(N),
331 LHS.getValueType(), N->getOperand(0), LHS,
332 GetScalarizedVector(N->getOperand(2)));
335 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
336 SDValue LHS = GetScalarizedVector(N->getOperand(2));
337 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), LHS.getValueType(),
338 N->getOperand(0), N->getOperand(1),
339 LHS, GetScalarizedVector(N->getOperand(3)),
343 SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) {
344 assert(N->getValueType(0).isVector() ==
345 N->getOperand(0).getValueType().isVector() &&
346 "Scalar/Vector type mismatch");
348 if (N->getValueType(0).isVector()) return ScalarizeVecRes_VSETCC(N);
350 SDValue LHS = GetScalarizedVector(N->getOperand(0));
351 SDValue RHS = GetScalarizedVector(N->getOperand(1));
354 // Turn it into a scalar SETCC.
355 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
358 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
359 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
362 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
363 // Figure out if the scalar is the LHS or RHS and return it.
364 SDValue Arg = N->getOperand(2).getOperand(0);
365 if (Arg.getOpcode() == ISD::UNDEF)
366 return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
367 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
368 return GetScalarizedVector(N->getOperand(Op));
371 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
372 assert(N->getValueType(0).isVector() &&
373 N->getOperand(0).getValueType().isVector() &&
374 "Operand types must be vectors");
375 SDValue LHS = N->getOperand(0);
376 SDValue RHS = N->getOperand(1);
377 EVT OpVT = LHS.getValueType();
378 EVT NVT = N->getValueType(0).getVectorElementType();
381 // The result needs scalarizing, but it's not a given that the source does.
382 if (getTypeAction(OpVT) == TargetLowering::TypeScalarizeVector) {
383 LHS = GetScalarizedVector(LHS);
384 RHS = GetScalarizedVector(RHS);
386 EVT VT = OpVT.getVectorElementType();
387 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS,
388 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
389 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS,
390 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
393 // Turn it into a scalar SETCC.
394 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
396 // Vectors may have a different boolean contents to scalars. Promote the
397 // value appropriately.
398 ISD::NodeType ExtendCode =
399 TargetLowering::getExtendForContent(TLI.getBooleanContents(OpVT));
400 return DAG.getNode(ExtendCode, DL, NVT, Res);
404 //===----------------------------------------------------------------------===//
405 // Operand Vector Scalarization <1 x ty> -> ty.
406 //===----------------------------------------------------------------------===//
408 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
409 DEBUG(dbgs() << "Scalarize node operand " << OpNo << ": ";
412 SDValue Res = SDValue();
414 if (!Res.getNode()) {
415 switch (N->getOpcode()) {
418 dbgs() << "ScalarizeVectorOperand Op #" << OpNo << ": ";
422 llvm_unreachable("Do not know how to scalarize this operator's operand!");
424 Res = ScalarizeVecOp_BITCAST(N);
426 case ISD::ANY_EXTEND:
427 case ISD::ZERO_EXTEND:
428 case ISD::SIGN_EXTEND:
430 case ISD::FP_TO_SINT:
431 case ISD::FP_TO_UINT:
432 case ISD::SINT_TO_FP:
433 case ISD::UINT_TO_FP:
434 Res = ScalarizeVecOp_UnaryOp(N);
436 case ISD::CONCAT_VECTORS:
437 Res = ScalarizeVecOp_CONCAT_VECTORS(N);
439 case ISD::EXTRACT_VECTOR_ELT:
440 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N);
443 Res = ScalarizeVecOp_VSELECT(N);
446 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo);
449 Res = ScalarizeVecOp_FP_ROUND(N, OpNo);
454 // If the result is null, the sub-method took care of registering results etc.
455 if (!Res.getNode()) return false;
457 // If the result is N, the sub-method updated N in place. Tell the legalizer
459 if (Res.getNode() == N)
462 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
463 "Invalid operand expansion");
465 ReplaceValueWith(SDValue(N, 0), Res);
469 /// ScalarizeVecOp_BITCAST - If the value to convert is a vector that needs
470 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
471 SDValue DAGTypeLegalizer::ScalarizeVecOp_BITCAST(SDNode *N) {
472 SDValue Elt = GetScalarizedVector(N->getOperand(0));
473 return DAG.getNode(ISD::BITCAST, SDLoc(N),
474 N->getValueType(0), Elt);
477 /// ScalarizeVecOp_UnaryOp - If the input is a vector that needs to be
478 /// scalarized, it must be <1 x ty>. Do the operation on the element instead.
479 SDValue DAGTypeLegalizer::ScalarizeVecOp_UnaryOp(SDNode *N) {
480 assert(N->getValueType(0).getVectorNumElements() == 1 &&
481 "Unexpected vector type!");
482 SDValue Elt = GetScalarizedVector(N->getOperand(0));
483 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N),
484 N->getValueType(0).getScalarType(), Elt);
485 // Revectorize the result so the types line up with what the uses of this
486 // expression expect.
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op);
490 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
491 /// use a BUILD_VECTOR instead.
492 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
493 SmallVector<SDValue, 8> Ops(N->getNumOperands());
494 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
495 Ops[i] = GetScalarizedVector(N->getOperand(i));
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops);
499 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
500 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
502 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
503 SDValue Res = GetScalarizedVector(N->getOperand(0));
504 if (Res.getValueType() != N->getValueType(0))
505 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
511 /// ScalarizeVecOp_VSELECT - If the input condition is a vector that needs to be
512 /// scalarized, it must be <1 x i1>, so just convert to a normal ISD::SELECT
513 /// (still with vector output type since that was acceptable if we got here).
514 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {
515 SDValue ScalarCond = GetScalarizedVector(N->getOperand(0));
516 EVT VT = N->getValueType(0);
518 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
522 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
523 /// scalarized, it must be <1 x ty>. Just store the element.
524 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
525 assert(N->isUnindexed() && "Indexed store of one-element vector?");
526 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
529 if (N->isTruncatingStore())
530 return DAG.getTruncStore(N->getChain(), dl,
531 GetScalarizedVector(N->getOperand(1)),
532 N->getBasePtr(), N->getPointerInfo(),
533 N->getMemoryVT().getVectorElementType(),
534 N->isVolatile(), N->isNonTemporal(),
535 N->getAlignment(), N->getAAInfo());
537 return DAG.getStore(N->getChain(), dl, GetScalarizedVector(N->getOperand(1)),
538 N->getBasePtr(), N->getPointerInfo(),
539 N->isVolatile(), N->isNonTemporal(),
540 N->getOriginalAlignment(), N->getAAInfo());
543 /// ScalarizeVecOp_FP_ROUND - If the value to round is a vector that needs
544 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
545 SDValue DAGTypeLegalizer::ScalarizeVecOp_FP_ROUND(SDNode *N, unsigned OpNo) {
546 SDValue Elt = GetScalarizedVector(N->getOperand(0));
547 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N),
548 N->getValueType(0).getVectorElementType(), Elt,
550 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Res);
553 //===----------------------------------------------------------------------===//
554 // Result Vector Splitting
555 //===----------------------------------------------------------------------===//
557 /// SplitVectorResult - This method is called when the specified result of the
558 /// specified node is found to need vector splitting. At this point, the node
559 /// may also have invalid operands or may have other results that need
560 /// legalization, we just know that (at least) one result needs vector
562 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
563 DEBUG(dbgs() << "Split node result: ";
568 // See if the target wants to custom expand this node.
569 if (CustomLowerNode(N, N->getValueType(ResNo), true))
572 switch (N->getOpcode()) {
575 dbgs() << "SplitVectorResult #" << ResNo << ": ";
579 report_fatal_error("Do not know how to split the result of this "
582 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
584 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
585 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
586 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
587 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break;
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
589 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
590 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
591 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
592 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
593 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
594 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
595 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
596 case ISD::SIGN_EXTEND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
598 SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);
601 SplitVecRes_MLOAD(cast<MaskedLoadSDNode>(N), Lo, Hi);
604 SplitVecRes_MGATHER(cast<MaskedGatherSDNode>(N), Lo, Hi);
607 SplitVecRes_SETCC(N, Lo, Hi);
609 case ISD::VECTOR_SHUFFLE:
610 SplitVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N), Lo, Hi);
614 case ISD::CONVERT_RNDSAT:
617 case ISD::CTLZ_ZERO_UNDEF:
618 case ISD::CTTZ_ZERO_UNDEF:
629 case ISD::FNEARBYINT:
633 case ISD::FP_TO_SINT:
634 case ISD::FP_TO_UINT:
640 case ISD::SINT_TO_FP:
642 case ISD::UINT_TO_FP:
643 SplitVecRes_UnaryOp(N, Lo, Hi);
646 case ISD::ANY_EXTEND:
647 case ISD::SIGN_EXTEND:
648 case ISD::ZERO_EXTEND:
649 SplitVecRes_ExtendOp(N, Lo, Hi);
678 SplitVecRes_BinOp(N, Lo, Hi);
681 SplitVecRes_TernaryOp(N, Lo, Hi);
685 // If Lo/Hi is null, the sub-method took care of registering results etc.
687 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
690 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
692 SDValue LHSLo, LHSHi;
693 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
694 SDValue RHSLo, RHSHi;
695 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
698 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo, RHSLo);
699 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi, RHSHi);
702 void DAGTypeLegalizer::SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo,
704 SDValue Op0Lo, Op0Hi;
705 GetSplitVector(N->getOperand(0), Op0Lo, Op0Hi);
706 SDValue Op1Lo, Op1Hi;
707 GetSplitVector(N->getOperand(1), Op1Lo, Op1Hi);
708 SDValue Op2Lo, Op2Hi;
709 GetSplitVector(N->getOperand(2), Op2Lo, Op2Hi);
712 Lo = DAG.getNode(N->getOpcode(), dl, Op0Lo.getValueType(),
713 Op0Lo, Op1Lo, Op2Lo);
714 Hi = DAG.getNode(N->getOpcode(), dl, Op0Hi.getValueType(),
715 Op0Hi, Op1Hi, Op2Hi);
718 void DAGTypeLegalizer::SplitVecRes_BITCAST(SDNode *N, SDValue &Lo,
720 // We know the result is a vector. The input may be either a vector or a
723 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
726 SDValue InOp = N->getOperand(0);
727 EVT InVT = InOp.getValueType();
729 // Handle some special cases efficiently.
730 switch (getTypeAction(InVT)) {
731 case TargetLowering::TypeLegal:
732 case TargetLowering::TypePromoteInteger:
733 case TargetLowering::TypePromoteFloat:
734 case TargetLowering::TypeSoftenFloat:
735 case TargetLowering::TypeScalarizeVector:
736 case TargetLowering::TypeWidenVector:
738 case TargetLowering::TypeExpandInteger:
739 case TargetLowering::TypeExpandFloat:
740 // A scalar to vector conversion, where the scalar needs expansion.
741 // If the vector is being split in two then we can just convert the
744 GetExpandedOp(InOp, Lo, Hi);
745 if (TLI.isBigEndian())
747 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
748 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
752 case TargetLowering::TypeSplitVector:
753 // If the input is a vector that needs to be split, convert each split
754 // piece of the input now.
755 GetSplitVector(InOp, Lo, Hi);
756 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
757 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
761 // In the general case, convert the input to an integer and split it by hand.
762 EVT LoIntVT = EVT::getIntegerVT(*DAG.getContext(), LoVT.getSizeInBits());
763 EVT HiIntVT = EVT::getIntegerVT(*DAG.getContext(), HiVT.getSizeInBits());
764 if (TLI.isBigEndian())
765 std::swap(LoIntVT, HiIntVT);
767 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
769 if (TLI.isBigEndian())
771 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo);
772 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi);
775 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
779 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
780 unsigned LoNumElts = LoVT.getVectorNumElements();
781 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
782 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps);
784 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
785 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps);
788 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
790 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
792 unsigned NumSubvectors = N->getNumOperands() / 2;
793 if (NumSubvectors == 1) {
794 Lo = N->getOperand(0);
795 Hi = N->getOperand(1);
800 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
802 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
803 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps);
805 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
806 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps);
809 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
811 SDValue Vec = N->getOperand(0);
812 SDValue Idx = N->getOperand(1);
816 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
818 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
819 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
820 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
821 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
822 TLI.getVectorIdxTy()));
825 void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
827 SDValue Vec = N->getOperand(0);
828 SDValue SubVec = N->getOperand(1);
829 SDValue Idx = N->getOperand(2);
831 GetSplitVector(Vec, Lo, Hi);
833 // Spill the vector to the stack.
834 EVT VecVT = Vec.getValueType();
835 EVT SubVecVT = VecVT.getVectorElementType();
836 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
837 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
838 MachinePointerInfo(), false, false, 0);
840 // Store the new subvector into the specified index.
841 SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
842 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
843 unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
844 Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
847 // Load the Lo part from the stack slot.
848 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
849 false, false, false, 0);
851 // Increment the pointer to the other part.
852 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
854 DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
855 DAG.getConstant(IncrementSize, dl, StackPtr.getValueType()));
857 // Load the Hi part from the stack slot.
858 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
859 false, false, false, MinAlign(Alignment, IncrementSize));
862 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
865 GetSplitVector(N->getOperand(0), Lo, Hi);
866 Lo = DAG.getNode(ISD::FPOWI, dl, Lo.getValueType(), Lo, N->getOperand(1));
867 Hi = DAG.getNode(ISD::FPOWI, dl, Hi.getValueType(), Hi, N->getOperand(1));
870 void DAGTypeLegalizer::SplitVecRes_InregOp(SDNode *N, SDValue &Lo,
872 SDValue LHSLo, LHSHi;
873 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
877 std::tie(LoVT, HiVT) =
878 DAG.GetSplitDestVTs(cast<VTSDNode>(N->getOperand(1))->getVT());
880 Lo = DAG.getNode(N->getOpcode(), dl, LHSLo.getValueType(), LHSLo,
881 DAG.getValueType(LoVT));
882 Hi = DAG.getNode(N->getOpcode(), dl, LHSHi.getValueType(), LHSHi,
883 DAG.getValueType(HiVT));
886 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
888 SDValue Vec = N->getOperand(0);
889 SDValue Elt = N->getOperand(1);
890 SDValue Idx = N->getOperand(2);
892 GetSplitVector(Vec, Lo, Hi);
894 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
895 unsigned IdxVal = CIdx->getZExtValue();
896 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
897 if (IdxVal < LoNumElts)
898 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
899 Lo.getValueType(), Lo, Elt, Idx);
901 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, Hi.getValueType(), Hi, Elt,
902 DAG.getConstant(IdxVal - LoNumElts, dl,
903 TLI.getVectorIdxTy()));
907 // See if the target wants to custom expand this node.
908 if (CustomLowerNode(N, N->getValueType(0), true))
911 // Spill the vector to the stack.
912 EVT VecVT = Vec.getValueType();
913 EVT EltVT = VecVT.getVectorElementType();
914 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
915 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
916 MachinePointerInfo(), false, false, 0);
918 // Store the new element. This may be larger than the vector element type,
919 // so use a truncating store.
920 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
921 Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
923 TLI.getDataLayout()->getPrefTypeAlignment(VecType);
924 Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, MachinePointerInfo(), EltVT,
927 // Load the Lo part from the stack slot.
928 Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
929 false, false, false, 0);
931 // Increment the pointer to the other part.
932 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
933 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
934 DAG.getConstant(IncrementSize, dl,
935 StackPtr.getValueType()));
937 // Load the Hi part from the stack slot.
938 Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
939 false, false, false, MinAlign(Alignment, IncrementSize));
942 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
946 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
947 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
948 Hi = DAG.getUNDEF(HiVT);
951 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
953 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
956 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(LD->getValueType(0));
958 ISD::LoadExtType ExtType = LD->getExtensionType();
959 SDValue Ch = LD->getChain();
960 SDValue Ptr = LD->getBasePtr();
961 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
962 EVT MemoryVT = LD->getMemoryVT();
963 unsigned Alignment = LD->getOriginalAlignment();
964 bool isVolatile = LD->isVolatile();
965 bool isNonTemporal = LD->isNonTemporal();
966 bool isInvariant = LD->isInvariant();
967 AAMDNodes AAInfo = LD->getAAInfo();
969 EVT LoMemVT, HiMemVT;
970 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
972 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
973 LD->getPointerInfo(), LoMemVT, isVolatile, isNonTemporal,
974 isInvariant, Alignment, AAInfo);
976 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
977 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
978 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
979 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
980 LD->getPointerInfo().getWithOffset(IncrementSize),
981 HiMemVT, isVolatile, isNonTemporal, isInvariant, Alignment,
984 // Build a factor node to remember that this load is independent of the
986 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
989 // Legalized the chain result - switch anything that used the old chain to
991 ReplaceValueWith(SDValue(LD, 1), Ch);
994 void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
995 SDValue &Lo, SDValue &Hi) {
998 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
1000 SDValue Ch = MLD->getChain();
1001 SDValue Ptr = MLD->getBasePtr();
1002 SDValue Mask = MLD->getMask();
1003 unsigned Alignment = MLD->getOriginalAlignment();
1004 ISD::LoadExtType ExtType = MLD->getExtensionType();
1006 // if Alignment is equal to the vector size,
1007 // take the half of it for the second part
1008 unsigned SecondHalfAlignment =
1009 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
1010 Alignment/2 : Alignment;
1012 SDValue MaskLo, MaskHi;
1013 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1015 EVT MemoryVT = MLD->getMemoryVT();
1016 EVT LoMemVT, HiMemVT;
1017 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1019 SDValue Src0 = MLD->getSrc0();
1020 SDValue Src0Lo, Src0Hi;
1021 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, dl);
1023 MachineMemOperand *MMO = DAG.getMachineFunction().
1024 getMachineMemOperand(MLD->getPointerInfo(),
1025 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1026 Alignment, MLD->getAAInfo(), MLD->getRanges());
1028 Lo = DAG.getMaskedLoad(LoVT, dl, Ch, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
1031 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1032 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1033 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1035 MMO = DAG.getMachineFunction().
1036 getMachineMemOperand(MLD->getPointerInfo(),
1037 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1038 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
1040 Hi = DAG.getMaskedLoad(HiVT, dl, Ch, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
1044 // Build a factor node to remember that this load is independent of the
1046 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1049 // Legalized the chain result - switch anything that used the old chain to
1051 ReplaceValueWith(SDValue(MLD, 1), Ch);
1055 void DAGTypeLegalizer::SplitVecRes_MGATHER(MaskedGatherSDNode *MGT,
1056 SDValue &Lo, SDValue &Hi) {
1059 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1061 SDValue Ch = MGT->getChain();
1062 SDValue Ptr = MGT->getBasePtr();
1063 SDValue Mask = MGT->getMask();
1064 unsigned Alignment = MGT->getOriginalAlignment();
1066 SDValue MaskLo, MaskHi;
1067 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1069 EVT MemoryVT = MGT->getMemoryVT();
1070 EVT LoMemVT, HiMemVT;
1071 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1073 SDValue Src0Lo, Src0Hi;
1074 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1076 SDValue IndexHi, IndexLo;
1077 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MGT->getIndex(), dl);
1079 MachineMemOperand *MMO = DAG.getMachineFunction().
1080 getMachineMemOperand(MGT->getPointerInfo(),
1081 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1082 Alignment, MGT->getAAInfo(), MGT->getRanges());
1084 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1085 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl, OpsLo,
1088 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1089 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl, OpsHi,
1092 // Build a factor node to remember that this load is independent of the
1094 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1097 // Legalized the chain result - switch anything that used the old chain to
1099 ReplaceValueWith(SDValue(MGT, 1), Ch);
1103 void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
1104 assert(N->getValueType(0).isVector() &&
1105 N->getOperand(0).getValueType().isVector() &&
1106 "Operand types must be vectors");
1110 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1113 SDValue LL, LH, RL, RH;
1114 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
1115 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
1117 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
1118 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
1121 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
1123 // Get the dest types - they may not match the input types, e.g. int_to_fp.
1126 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
1128 // If the input also splits, handle it directly for a compile time speedup.
1129 // Otherwise split it by hand.
1130 EVT InVT = N->getOperand(0).getValueType();
1131 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector)
1132 GetSplitVector(N->getOperand(0), Lo, Hi);
1134 std::tie(Lo, Hi) = DAG.SplitVectorOperand(N, 0);
1136 if (N->getOpcode() == ISD::FP_ROUND) {
1137 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo, N->getOperand(1));
1138 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi, N->getOperand(1));
1139 } else if (N->getOpcode() == ISD::CONVERT_RNDSAT) {
1140 SDValue DTyOpLo = DAG.getValueType(LoVT);
1141 SDValue DTyOpHi = DAG.getValueType(HiVT);
1142 SDValue STyOpLo = DAG.getValueType(Lo.getValueType());
1143 SDValue STyOpHi = DAG.getValueType(Hi.getValueType());
1144 SDValue RndOp = N->getOperand(3);
1145 SDValue SatOp = N->getOperand(4);
1146 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1147 Lo = DAG.getConvertRndSat(LoVT, dl, Lo, DTyOpLo, STyOpLo, RndOp, SatOp,
1149 Hi = DAG.getConvertRndSat(HiVT, dl, Hi, DTyOpHi, STyOpHi, RndOp, SatOp,
1152 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1153 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1157 void DAGTypeLegalizer::SplitVecRes_ExtendOp(SDNode *N, SDValue &Lo,
1160 EVT SrcVT = N->getOperand(0).getValueType();
1161 EVT DestVT = N->getValueType(0);
1163 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(DestVT);
1165 // We can do better than a generic split operation if the extend is doing
1166 // more than just doubling the width of the elements and the following are
1168 // - The number of vector elements is even,
1169 // - the source type is legal,
1170 // - the type of a split source is illegal,
1171 // - the type of an extended (by doubling element size) source is legal, and
1172 // - the type of that extended source when split is legal.
1174 // This won't necessarily completely legalize the operation, but it will
1175 // more effectively move in the right direction and prevent falling down
1176 // to scalarization in many cases due to the input vector being split too
1178 unsigned NumElements = SrcVT.getVectorNumElements();
1179 if ((NumElements & 1) == 0 &&
1180 SrcVT.getSizeInBits() * 2 < DestVT.getSizeInBits()) {
1181 LLVMContext &Ctx = *DAG.getContext();
1182 EVT NewSrcVT = EVT::getVectorVT(
1183 Ctx, EVT::getIntegerVT(
1184 Ctx, SrcVT.getVectorElementType().getSizeInBits() * 2),
1187 EVT::getVectorVT(Ctx, SrcVT.getVectorElementType(), NumElements / 2);
1188 EVT SplitLoVT, SplitHiVT;
1189 std::tie(SplitLoVT, SplitHiVT) = DAG.GetSplitDestVTs(NewSrcVT);
1190 if (TLI.isTypeLegal(SrcVT) && !TLI.isTypeLegal(SplitSrcVT) &&
1191 TLI.isTypeLegal(NewSrcVT) && TLI.isTypeLegal(SplitLoVT)) {
1192 DEBUG(dbgs() << "Split vector extend via incremental extend:";
1193 N->dump(&DAG); dbgs() << "\n");
1194 // Extend the source vector by one step.
1196 DAG.getNode(N->getOpcode(), dl, NewSrcVT, N->getOperand(0));
1197 // Get the low and high halves of the new, extended one step, vector.
1198 std::tie(Lo, Hi) = DAG.SplitVector(NewSrc, dl);
1199 // Extend those vector halves the rest of the way.
1200 Lo = DAG.getNode(N->getOpcode(), dl, LoVT, Lo);
1201 Hi = DAG.getNode(N->getOpcode(), dl, HiVT, Hi);
1205 // Fall back to the generic unary operator splitting otherwise.
1206 SplitVecRes_UnaryOp(N, Lo, Hi);
1209 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N,
1210 SDValue &Lo, SDValue &Hi) {
1211 // The low and high parts of the original input give four input vectors.
1214 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
1215 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
1216 EVT NewVT = Inputs[0].getValueType();
1217 unsigned NewElts = NewVT.getVectorNumElements();
1219 // If Lo or Hi uses elements from at most two of the four input vectors, then
1220 // express it as a vector shuffle of those two inputs. Otherwise extract the
1221 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
1222 SmallVector<int, 16> Ops;
1223 for (unsigned High = 0; High < 2; ++High) {
1224 SDValue &Output = High ? Hi : Lo;
1226 // Build a shuffle mask for the output, discovering on the fly which
1227 // input vectors to use as shuffle operands (recorded in InputUsed).
1228 // If building a suitable shuffle vector proves too hard, then bail
1229 // out with useBuildVector set.
1230 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
1231 unsigned FirstMaskIdx = High * NewElts;
1232 bool useBuildVector = false;
1233 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1234 // The mask element. This indexes into the input.
1235 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1237 // The input vector this mask element indexes into.
1238 unsigned Input = (unsigned)Idx / NewElts;
1240 if (Input >= array_lengthof(Inputs)) {
1241 // The mask element does not index into any input vector.
1246 // Turn the index into an offset from the start of the input vector.
1247 Idx -= Input * NewElts;
1249 // Find or create a shuffle vector operand to hold this input.
1251 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
1252 if (InputUsed[OpNo] == Input) {
1253 // This input vector is already an operand.
1255 } else if (InputUsed[OpNo] == -1U) {
1256 // Create a new operand for this input vector.
1257 InputUsed[OpNo] = Input;
1262 if (OpNo >= array_lengthof(InputUsed)) {
1263 // More than two input vectors used! Give up on trying to create a
1264 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
1265 useBuildVector = true;
1269 // Add the mask index for the new shuffle vector.
1270 Ops.push_back(Idx + OpNo * NewElts);
1273 if (useBuildVector) {
1274 EVT EltVT = NewVT.getVectorElementType();
1275 SmallVector<SDValue, 16> SVOps;
1277 // Extract the input elements by hand.
1278 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
1279 // The mask element. This indexes into the input.
1280 int Idx = N->getMaskElt(FirstMaskIdx + MaskOffset);
1282 // The input vector this mask element indexes into.
1283 unsigned Input = (unsigned)Idx / NewElts;
1285 if (Input >= array_lengthof(Inputs)) {
1286 // The mask element is "undef" or indexes off the end of the input.
1287 SVOps.push_back(DAG.getUNDEF(EltVT));
1291 // Turn the index into an offset from the start of the input vector.
1292 Idx -= Input * NewElts;
1294 // Extract the vector element by hand.
1295 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
1297 DAG.getConstant(Idx, dl,
1298 TLI.getVectorIdxTy())));
1301 // Construct the Lo/Hi output using a BUILD_VECTOR.
1302 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps);
1303 } else if (InputUsed[0] == -1U) {
1304 // No input vectors were used! The result is undefined.
1305 Output = DAG.getUNDEF(NewVT);
1307 SDValue Op0 = Inputs[InputUsed[0]];
1308 // If only one input was used, use an undefined vector for the other.
1309 SDValue Op1 = InputUsed[1] == -1U ?
1310 DAG.getUNDEF(NewVT) : Inputs[InputUsed[1]];
1311 // At least one input vector was used. Create a new shuffle vector.
1312 Output = DAG.getVectorShuffle(NewVT, dl, Op0, Op1, &Ops[0]);
1320 //===----------------------------------------------------------------------===//
1321 // Operand Vector Splitting
1322 //===----------------------------------------------------------------------===//
1324 /// SplitVectorOperand - This method is called when the specified operand of the
1325 /// specified node is found to need vector splitting. At this point, all of the
1326 /// result types of the node are known to be legal, but other operands of the
1327 /// node may need legalization as well as the specified one.
1328 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
1329 DEBUG(dbgs() << "Split node operand: ";
1332 SDValue Res = SDValue();
1334 // See if the target wants to custom split this node.
1335 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1338 if (!Res.getNode()) {
1339 switch (N->getOpcode()) {
1342 dbgs() << "SplitVectorOperand Op #" << OpNo << ": ";
1346 report_fatal_error("Do not know how to split this operator's "
1349 case ISD::SETCC: Res = SplitVecOp_VSETCC(N); break;
1350 case ISD::BITCAST: Res = SplitVecOp_BITCAST(N); break;
1351 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
1352 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
1353 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break;
1355 Res = SplitVecOp_TruncateHelper(N);
1357 case ISD::FP_ROUND: Res = SplitVecOp_FP_ROUND(N); break;
1359 Res = SplitVecOp_STORE(cast<StoreSDNode>(N), OpNo);
1362 Res = SplitVecOp_MSTORE(cast<MaskedStoreSDNode>(N), OpNo);
1365 Res = SplitVecOp_MSCATTER(cast<MaskedScatterSDNode>(N), OpNo);
1368 Res = SplitVecOp_MGATHER(cast<MaskedGatherSDNode>(N), OpNo);
1371 Res = SplitVecOp_VSELECT(N, OpNo);
1373 case ISD::FP_TO_SINT:
1374 case ISD::FP_TO_UINT:
1375 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1376 Res = SplitVecOp_TruncateHelper(N);
1378 Res = SplitVecOp_UnaryOp(N);
1380 case ISD::SINT_TO_FP:
1381 case ISD::UINT_TO_FP:
1382 if (N->getValueType(0).bitsLT(N->getOperand(0)->getValueType(0)))
1383 Res = SplitVecOp_TruncateHelper(N);
1385 Res = SplitVecOp_UnaryOp(N);
1390 case ISD::FP_EXTEND:
1391 case ISD::SIGN_EXTEND:
1392 case ISD::ZERO_EXTEND:
1393 case ISD::ANY_EXTEND:
1395 Res = SplitVecOp_UnaryOp(N);
1400 // If the result is null, the sub-method took care of registering results etc.
1401 if (!Res.getNode()) return false;
1403 // If the result is N, the sub-method updated N in place. Tell the legalizer
1405 if (Res.getNode() == N)
1408 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1409 "Invalid operand expansion");
1411 ReplaceValueWith(SDValue(N, 0), Res);
1415 SDValue DAGTypeLegalizer::SplitVecOp_VSELECT(SDNode *N, unsigned OpNo) {
1416 // The only possibility for an illegal operand is the mask, since result type
1417 // legalization would have handled this node already otherwise.
1418 assert(OpNo == 0 && "Illegal operand must be mask");
1420 SDValue Mask = N->getOperand(0);
1421 SDValue Src0 = N->getOperand(1);
1422 SDValue Src1 = N->getOperand(2);
1423 EVT Src0VT = Src0.getValueType();
1425 assert(Mask.getValueType().isVector() && "VSELECT without a vector mask?");
1428 GetSplitVector(N->getOperand(0), Lo, Hi);
1429 assert(Lo.getValueType() == Hi.getValueType() &&
1430 "Lo and Hi have differing types");
1433 std::tie(LoOpVT, HiOpVT) = DAG.GetSplitDestVTs(Src0VT);
1434 assert(LoOpVT == HiOpVT && "Asymmetric vector split?");
1436 SDValue LoOp0, HiOp0, LoOp1, HiOp1, LoMask, HiMask;
1437 std::tie(LoOp0, HiOp0) = DAG.SplitVector(Src0, DL);
1438 std::tie(LoOp1, HiOp1) = DAG.SplitVector(Src1, DL);
1439 std::tie(LoMask, HiMask) = DAG.SplitVector(Mask, DL);
1442 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1);
1444 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1);
1446 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect);
1449 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
1450 // The result has a legal vector type, but the input needs splitting.
1451 EVT ResVT = N->getValueType(0);
1454 GetSplitVector(N->getOperand(0), Lo, Hi);
1455 EVT InVT = Lo.getValueType();
1457 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1458 InVT.getVectorNumElements());
1460 Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
1461 Hi = DAG.getNode(N->getOpcode(), dl, OutVT, Hi);
1463 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
1466 SDValue DAGTypeLegalizer::SplitVecOp_BITCAST(SDNode *N) {
1467 // For example, i64 = BITCAST v4i16 on alpha. Typically the vector will
1468 // end up being split all the way down to individual components. Convert the
1469 // split pieces into integers and reassemble.
1471 GetSplitVector(N->getOperand(0), Lo, Hi);
1472 Lo = BitConvertToInteger(Lo);
1473 Hi = BitConvertToInteger(Hi);
1475 if (TLI.isBigEndian())
1478 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0),
1479 JoinIntegers(Lo, Hi));
1482 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
1483 // We know that the extracted result type is legal.
1484 EVT SubVT = N->getValueType(0);
1485 SDValue Idx = N->getOperand(1);
1488 GetSplitVector(N->getOperand(0), Lo, Hi);
1490 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1491 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1493 if (IdxVal < LoElts) {
1494 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1495 "Extracted subvector crosses vector split!");
1496 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Lo, Idx);
1498 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi,
1499 DAG.getConstant(IdxVal - LoElts, dl,
1500 Idx.getValueType()));
1504 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
1505 SDValue Vec = N->getOperand(0);
1506 SDValue Idx = N->getOperand(1);
1507 EVT VecVT = Vec.getValueType();
1509 if (isa<ConstantSDNode>(Idx)) {
1510 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1511 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1514 GetSplitVector(Vec, Lo, Hi);
1516 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
1518 if (IdxVal < LoElts)
1519 return SDValue(DAG.UpdateNodeOperands(N, Lo, Idx), 0);
1520 return SDValue(DAG.UpdateNodeOperands(N, Hi,
1521 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
1522 Idx.getValueType())), 0);
1525 // See if the target wants to custom expand this node.
1526 if (CustomLowerNode(N, N->getValueType(0), true))
1529 // Store the vector to the stack.
1530 EVT EltVT = VecVT.getVectorElementType();
1532 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
1533 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1534 MachinePointerInfo(), false, false, 0);
1536 // Load back the required element.
1537 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
1538 return DAG.getExtLoad(ISD::EXTLOAD, dl, N->getValueType(0), Store, StackPtr,
1539 MachinePointerInfo(), EltVT, false, false, false, 0);
1542 SDValue DAGTypeLegalizer::SplitVecOp_MGATHER(MaskedGatherSDNode *MGT,
1546 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MGT->getValueType(0));
1548 SDValue Ch = MGT->getChain();
1549 SDValue Ptr = MGT->getBasePtr();
1550 SDValue Index = MGT->getIndex();
1551 SDValue Mask = MGT->getMask();
1552 unsigned Alignment = MGT->getOriginalAlignment();
1554 SDValue MaskLo, MaskHi;
1555 std::tie(MaskLo, MaskHi) = DAG.SplitVector(Mask, dl);
1557 EVT MemoryVT = MGT->getMemoryVT();
1558 EVT LoMemVT, HiMemVT;
1559 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1561 SDValue Src0Lo, Src0Hi;
1562 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(MGT->getValue(), dl);
1564 SDValue IndexHi, IndexLo;
1565 if (Index.getNode())
1566 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, dl);
1568 IndexLo = IndexHi = Index;
1570 MachineMemOperand *MMO = DAG.getMachineFunction().
1571 getMachineMemOperand(MGT->getPointerInfo(),
1572 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
1573 Alignment, MGT->getAAInfo(), MGT->getRanges());
1575 SDValue OpsLo[] = {Ch, Src0Lo, MaskLo, Ptr, IndexLo};
1576 SDValue Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, dl,
1579 MMO = DAG.getMachineFunction().
1580 getMachineMemOperand(MGT->getPointerInfo(),
1581 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
1582 Alignment, MGT->getAAInfo(),
1585 SDValue OpsHi[] = {Ch, Src0Hi, MaskHi, Ptr, IndexHi};
1586 SDValue Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, dl,
1589 // Build a factor node to remember that this load is independent of the
1591 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1594 // Legalized the chain result - switch anything that used the old chain to
1596 ReplaceValueWith(SDValue(MGT, 1), Ch);
1598 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo,
1600 ReplaceValueWith(SDValue(MGT, 0), Res);
1604 SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
1606 SDValue Ch = N->getChain();
1607 SDValue Ptr = N->getBasePtr();
1608 SDValue Mask = N->getMask();
1609 SDValue Data = N->getValue();
1610 EVT MemoryVT = N->getMemoryVT();
1611 unsigned Alignment = N->getOriginalAlignment();
1614 EVT LoMemVT, HiMemVT;
1615 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1617 SDValue DataLo, DataHi;
1618 GetSplitVector(Data, DataLo, DataHi);
1619 SDValue MaskLo, MaskHi;
1620 GetSplitVector(Mask, MaskLo, MaskHi);
1622 // if Alignment is equal to the vector size,
1623 // take the half of it for the second part
1624 unsigned SecondHalfAlignment =
1625 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
1626 Alignment/2 : Alignment;
1629 MachineMemOperand *MMO = DAG.getMachineFunction().
1630 getMachineMemOperand(N->getPointerInfo(),
1631 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1632 Alignment, N->getAAInfo(), N->getRanges());
1634 Lo = DAG.getMaskedStore(Ch, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
1635 N->isTruncatingStore());
1637 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1638 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1639 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1641 MMO = DAG.getMachineFunction().
1642 getMachineMemOperand(N->getPointerInfo(),
1643 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1644 SecondHalfAlignment, N->getAAInfo(), N->getRanges());
1646 Hi = DAG.getMaskedStore(Ch, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
1647 N->isTruncatingStore());
1649 // Build a factor node to remember that this store is independent of the
1651 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1654 SDValue DAGTypeLegalizer::SplitVecOp_MSCATTER(MaskedScatterSDNode *N,
1656 SDValue Ch = N->getChain();
1657 SDValue Ptr = N->getBasePtr();
1658 SDValue Mask = N->getMask();
1659 SDValue Index = N->getIndex();
1660 SDValue Data = N->getValue();
1661 EVT MemoryVT = N->getMemoryVT();
1662 unsigned Alignment = N->getOriginalAlignment();
1665 EVT LoMemVT, HiMemVT;
1666 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1668 SDValue DataLo, DataHi;
1669 GetSplitVector(Data, DataLo, DataHi);
1670 SDValue MaskLo, MaskHi;
1671 GetSplitVector(Mask, MaskLo, MaskHi);
1673 SDValue PtrLo, PtrHi;
1674 if (Ptr.getValueType().isVector()) // gather form vector of pointers
1675 std::tie(PtrLo, PtrHi) = DAG.SplitVector(Ptr, DL);
1677 PtrLo = PtrHi = Ptr;
1679 SDValue IndexHi, IndexLo;
1680 if (Index.getNode())
1681 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
1683 IndexLo = IndexHi = Index;
1686 MachineMemOperand *MMO = DAG.getMachineFunction().
1687 getMachineMemOperand(N->getPointerInfo(),
1688 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
1689 Alignment, N->getAAInfo(), N->getRanges());
1691 SDValue OpsLo[] = {Ch, DataLo, MaskLo, PtrLo, IndexLo};
1692 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
1695 MMO = DAG.getMachineFunction().
1696 getMachineMemOperand(N->getPointerInfo(),
1697 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
1698 Alignment, N->getAAInfo(), N->getRanges());
1700 SDValue OpsHi[] = {Ch, DataHi, MaskHi, PtrHi, IndexHi};
1701 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
1704 // Build a factor node to remember that this store is independent of the
1706 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1709 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
1710 assert(N->isUnindexed() && "Indexed store of vector?");
1711 assert(OpNo == 1 && "Can only split the stored value");
1714 bool isTruncating = N->isTruncatingStore();
1715 SDValue Ch = N->getChain();
1716 SDValue Ptr = N->getBasePtr();
1717 EVT MemoryVT = N->getMemoryVT();
1718 unsigned Alignment = N->getOriginalAlignment();
1719 bool isVol = N->isVolatile();
1720 bool isNT = N->isNonTemporal();
1721 AAMDNodes AAInfo = N->getAAInfo();
1723 GetSplitVector(N->getOperand(1), Lo, Hi);
1725 EVT LoMemVT, HiMemVT;
1726 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
1728 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
1731 Lo = DAG.getTruncStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1732 LoMemVT, isVol, isNT, Alignment, AAInfo);
1734 Lo = DAG.getStore(Ch, DL, Lo, Ptr, N->getPointerInfo(),
1735 isVol, isNT, Alignment, AAInfo);
1737 // Increment the pointer to the other half.
1738 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
1739 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
1742 Hi = DAG.getTruncStore(Ch, DL, Hi, Ptr,
1743 N->getPointerInfo().getWithOffset(IncrementSize),
1744 HiMemVT, isVol, isNT, Alignment, AAInfo);
1746 Hi = DAG.getStore(Ch, DL, Hi, Ptr,
1747 N->getPointerInfo().getWithOffset(IncrementSize),
1748 isVol, isNT, Alignment, AAInfo);
1750 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
1753 SDValue DAGTypeLegalizer::SplitVecOp_CONCAT_VECTORS(SDNode *N) {
1756 // The input operands all must have the same type, and we know the result
1757 // type is valid. Convert this to a buildvector which extracts all the
1759 // TODO: If the input elements are power-two vectors, we could convert this to
1760 // a new CONCAT_VECTORS node with elements that are half-wide.
1761 SmallVector<SDValue, 32> Elts;
1762 EVT EltVT = N->getValueType(0).getVectorElementType();
1763 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) {
1764 SDValue Op = N->getOperand(op);
1765 for (unsigned i = 0, e = Op.getValueType().getVectorNumElements();
1767 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT,
1768 Op, DAG.getConstant(i, DL, TLI.getVectorIdxTy())));
1773 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts);
1776 SDValue DAGTypeLegalizer::SplitVecOp_TruncateHelper(SDNode *N) {
1777 // The result type is legal, but the input type is illegal. If splitting
1778 // ends up with the result type of each half still being legal, just
1779 // do that. If, however, that would result in an illegal result type,
1780 // we can try to get more clever with power-two vectors. Specifically,
1781 // split the input type, but also widen the result element size, then
1782 // concatenate the halves and truncate again. For example, consider a target
1783 // where v8i8 is legal and v8i32 is not (ARM, which doesn't have 256-bit
1784 // vectors). To perform a "%res = v8i8 trunc v8i32 %in" we do:
1785 // %inlo = v4i32 extract_subvector %in, 0
1786 // %inhi = v4i32 extract_subvector %in, 4
1787 // %lo16 = v4i16 trunc v4i32 %inlo
1788 // %hi16 = v4i16 trunc v4i32 %inhi
1789 // %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16
1790 // %res = v8i8 trunc v8i16 %in16
1792 // Without this transform, the original truncate would end up being
1793 // scalarized, which is pretty much always a last resort.
1794 SDValue InVec = N->getOperand(0);
1795 EVT InVT = InVec->getValueType(0);
1796 EVT OutVT = N->getValueType(0);
1797 unsigned NumElements = OutVT.getVectorNumElements();
1798 bool IsFloat = OutVT.isFloatingPoint();
1800 // Widening should have already made sure this is a power-two vector
1801 // if we're trying to split it at all. assert() that's true, just in case.
1802 assert(!(NumElements & 1) && "Splitting vector, but not in half!");
1804 unsigned InElementSize = InVT.getVectorElementType().getSizeInBits();
1805 unsigned OutElementSize = OutVT.getVectorElementType().getSizeInBits();
1807 // If the input elements are only 1/2 the width of the result elements,
1808 // just use the normal splitting. Our trick only work if there's room
1809 // to split more than once.
1810 if (InElementSize <= OutElementSize * 2)
1811 return SplitVecOp_UnaryOp(N);
1814 // Extract the halves of the input via extract_subvector.
1815 SDValue InLoVec, InHiVec;
1816 std::tie(InLoVec, InHiVec) = DAG.SplitVector(InVec, DL);
1817 // Truncate them to 1/2 the element size.
1818 EVT HalfElementVT = IsFloat ?
1819 EVT::getFloatingPointVT(InElementSize/2) :
1820 EVT::getIntegerVT(*DAG.getContext(), InElementSize/2);
1821 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT,
1823 SDValue HalfLo = DAG.getNode(N->getOpcode(), DL, HalfVT, InLoVec);
1824 SDValue HalfHi = DAG.getNode(N->getOpcode(), DL, HalfVT, InHiVec);
1825 // Concatenate them to get the full intermediate truncation result.
1826 EVT InterVT = EVT::getVectorVT(*DAG.getContext(), HalfElementVT, NumElements);
1827 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo,
1829 // Now finish up by truncating all the way down to the original result
1830 // type. This should normally be something that ends up being legal directly,
1831 // but in theory if a target has very wide vectors and an annoyingly
1832 // restricted set of legal types, this split can chain to build things up.
1834 DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
1835 DAG.getTargetConstant(0, DL, TLI.getPointerTy())) :
1836 DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
1839 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
1840 assert(N->getValueType(0).isVector() &&
1841 N->getOperand(0).getValueType().isVector() &&
1842 "Operand types must be vectors");
1843 // The result has a legal vector type, but the input needs splitting.
1844 SDValue Lo0, Hi0, Lo1, Hi1, LoRes, HiRes;
1846 GetSplitVector(N->getOperand(0), Lo0, Hi0);
1847 GetSplitVector(N->getOperand(1), Lo1, Hi1);
1848 unsigned PartElements = Lo0.getValueType().getVectorNumElements();
1849 EVT PartResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, PartElements);
1850 EVT WideResVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1, 2*PartElements);
1852 LoRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Lo0, Lo1, N->getOperand(2));
1853 HiRes = DAG.getNode(ISD::SETCC, DL, PartResVT, Hi0, Hi1, N->getOperand(2));
1854 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes);
1855 return PromoteTargetBoolean(Con, N->getValueType(0));
1859 SDValue DAGTypeLegalizer::SplitVecOp_FP_ROUND(SDNode *N) {
1860 // The result has a legal vector type, but the input needs splitting.
1861 EVT ResVT = N->getValueType(0);
1864 GetSplitVector(N->getOperand(0), Lo, Hi);
1865 EVT InVT = Lo.getValueType();
1867 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), ResVT.getVectorElementType(),
1868 InVT.getVectorNumElements());
1870 Lo = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Lo, N->getOperand(1));
1871 Hi = DAG.getNode(ISD::FP_ROUND, DL, OutVT, Hi, N->getOperand(1));
1873 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi);
1878 //===----------------------------------------------------------------------===//
1879 // Result Vector Widening
1880 //===----------------------------------------------------------------------===//
1882 void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
1883 DEBUG(dbgs() << "Widen node result " << ResNo << ": ";
1887 // See if the target wants to custom widen this node.
1888 if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
1891 SDValue Res = SDValue();
1892 switch (N->getOpcode()) {
1895 dbgs() << "WidenVectorResult #" << ResNo << ": ";
1899 llvm_unreachable("Do not know how to widen the result of this operator!");
1901 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break;
1902 case ISD::BITCAST: Res = WidenVecRes_BITCAST(N); break;
1903 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
1904 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
1905 case ISD::CONVERT_RNDSAT: Res = WidenVecRes_CONVERT_RNDSAT(N); break;
1906 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
1907 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
1908 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
1909 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
1910 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
1911 case ISD::SIGN_EXTEND_INREG: Res = WidenVecRes_InregOp(N); break;
1913 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
1914 case ISD::SELECT_CC: Res = WidenVecRes_SELECT_CC(N); break;
1915 case ISD::SETCC: Res = WidenVecRes_SETCC(N); break;
1916 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
1917 case ISD::VECTOR_SHUFFLE:
1918 Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));
1921 Res = WidenVecRes_MLOAD(cast<MaskedLoadSDNode>(N));
1934 Res = WidenVecRes_Binary(N);
1938 case ISD::FCOPYSIGN:
1948 Res = WidenVecRes_BinaryCanTrap(N);
1952 Res = WidenVecRes_POWI(N);
1958 Res = WidenVecRes_Shift(N);
1961 case ISD::ANY_EXTEND:
1962 case ISD::FP_EXTEND:
1964 case ISD::FP_TO_SINT:
1965 case ISD::FP_TO_UINT:
1966 case ISD::SIGN_EXTEND:
1967 case ISD::SINT_TO_FP:
1969 case ISD::UINT_TO_FP:
1970 case ISD::ZERO_EXTEND:
1971 Res = WidenVecRes_Convert(N);
1987 case ISD::FNEARBYINT:
1994 Res = WidenVecRes_Unary(N);
1997 Res = WidenVecRes_Ternary(N);
2001 // If Res is null, the sub-method took care of registering the result.
2003 SetWidenedVector(SDValue(N, ResNo), Res);
2006 SDValue DAGTypeLegalizer::WidenVecRes_Ternary(SDNode *N) {
2007 // Ternary op widening.
2009 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2010 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2011 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2012 SDValue InOp3 = GetWidenedVector(N->getOperand(2));
2013 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, InOp3);
2016 SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
2017 // Binary op widening.
2019 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2020 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2021 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2022 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
2025 SDValue DAGTypeLegalizer::WidenVecRes_BinaryCanTrap(SDNode *N) {
2026 // Binary op widening for operations that can trap.
2027 unsigned Opcode = N->getOpcode();
2029 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2030 EVT WidenEltVT = WidenVT.getVectorElementType();
2032 unsigned NumElts = VT.getVectorNumElements();
2033 while (!TLI.isTypeLegal(VT) && NumElts != 1) {
2034 NumElts = NumElts / 2;
2035 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2038 if (NumElts != 1 && !TLI.canOpTrap(N->getOpcode(), VT)) {
2039 // Operation doesn't trap so just widen as normal.
2040 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2041 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2042 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2);
2045 // No legal vector version so unroll the vector operation and then widen.
2047 return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements());
2049 // Since the operation can trap, apply operation on the original vector.
2051 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2052 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2053 unsigned CurNumElts = N->getValueType(0).getVectorNumElements();
2055 SmallVector<SDValue, 16> ConcatOps(CurNumElts);
2056 unsigned ConcatEnd = 0; // Current ConcatOps index.
2057 int Idx = 0; // Current Idx into input vectors.
2059 // NumElts := greatest legal vector size (at most WidenVT)
2060 // while (orig. vector has unhandled elements) {
2061 // take munches of size NumElts from the beginning and add to ConcatOps
2062 // NumElts := next smaller supported vector size or 1
2064 while (CurNumElts != 0) {
2065 while (CurNumElts >= NumElts) {
2066 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp1,
2067 DAG.getConstant(Idx, dl,
2068 TLI.getVectorIdxTy()));
2069 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, InOp2,
2070 DAG.getConstant(Idx, dl,
2071 TLI.getVectorIdxTy()));
2072 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, VT, EOp1, EOp2);
2074 CurNumElts -= NumElts;
2077 NumElts = NumElts / 2;
2078 VT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NumElts);
2079 } while (!TLI.isTypeLegal(VT) && NumElts != 1);
2082 for (unsigned i = 0; i != CurNumElts; ++i, ++Idx) {
2083 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
2085 DAG.getConstant(Idx, dl,
2086 TLI.getVectorIdxTy()));
2087 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, WidenEltVT,
2089 DAG.getConstant(Idx, dl,
2090 TLI.getVectorIdxTy()));
2091 ConcatOps[ConcatEnd++] = DAG.getNode(Opcode, dl, WidenEltVT,
2098 // Check to see if we have a single operation with the widen type.
2099 if (ConcatEnd == 1) {
2100 VT = ConcatOps[0].getValueType();
2102 return ConcatOps[0];
2105 // while (Some element of ConcatOps is not of type MaxVT) {
2106 // From the end of ConcatOps, collect elements of the same type and put
2107 // them into an op of the next larger supported type
2109 while (ConcatOps[ConcatEnd-1].getValueType() != MaxVT) {
2110 Idx = ConcatEnd - 1;
2111 VT = ConcatOps[Idx--].getValueType();
2112 while (Idx >= 0 && ConcatOps[Idx].getValueType() == VT)
2115 int NextSize = VT.isVector() ? VT.getVectorNumElements() : 1;
2119 NextVT = EVT::getVectorVT(*DAG.getContext(), WidenEltVT, NextSize);
2120 } while (!TLI.isTypeLegal(NextVT));
2122 if (!VT.isVector()) {
2123 // Scalar type, create an INSERT_VECTOR_ELEMENT of type NextVT
2124 SDValue VecOp = DAG.getUNDEF(NextVT);
2125 unsigned NumToInsert = ConcatEnd - Idx - 1;
2126 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
2127 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NextVT, VecOp,
2129 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
2131 ConcatOps[Idx+1] = VecOp;
2132 ConcatEnd = Idx + 2;
2134 // Vector type, create a CONCAT_VECTORS of type NextVT
2135 SDValue undefVec = DAG.getUNDEF(VT);
2136 unsigned OpsToConcat = NextSize/VT.getVectorNumElements();
2137 SmallVector<SDValue, 16> SubConcatOps(OpsToConcat);
2138 unsigned RealVals = ConcatEnd - Idx - 1;
2139 unsigned SubConcatEnd = 0;
2140 unsigned SubConcatIdx = Idx + 1;
2141 while (SubConcatEnd < RealVals)
2142 SubConcatOps[SubConcatEnd++] = ConcatOps[++Idx];
2143 while (SubConcatEnd < OpsToConcat)
2144 SubConcatOps[SubConcatEnd++] = undefVec;
2145 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl,
2146 NextVT, SubConcatOps);
2147 ConcatEnd = SubConcatIdx + 1;
2151 // Check to see if we have a single operation with the widen type.
2152 if (ConcatEnd == 1) {
2153 VT = ConcatOps[0].getValueType();
2155 return ConcatOps[0];
2158 // add undefs of size MaxVT until ConcatOps grows to length of WidenVT
2159 unsigned NumOps = WidenVT.getVectorNumElements()/MaxVT.getVectorNumElements();
2160 if (NumOps != ConcatEnd ) {
2161 SDValue UndefVal = DAG.getUNDEF(MaxVT);
2162 for (unsigned j = ConcatEnd; j < NumOps; ++j)
2163 ConcatOps[j] = UndefVal;
2165 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
2166 makeArrayRef(ConcatOps.data(), NumOps));
2169 SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) {
2170 SDValue InOp = N->getOperand(0);
2173 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2174 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2176 EVT InVT = InOp.getValueType();
2177 EVT InEltVT = InVT.getVectorElementType();
2178 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2180 unsigned Opcode = N->getOpcode();
2181 unsigned InVTNumElts = InVT.getVectorNumElements();
2183 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2184 InOp = GetWidenedVector(N->getOperand(0));
2185 InVT = InOp.getValueType();
2186 InVTNumElts = InVT.getVectorNumElements();
2187 if (InVTNumElts == WidenNumElts) {
2188 if (N->getNumOperands() == 1)
2189 return DAG.getNode(Opcode, DL, WidenVT, InOp);
2190 return DAG.getNode(Opcode, DL, WidenVT, InOp, N->getOperand(1));
2194 if (TLI.isTypeLegal(InWidenVT)) {
2195 // Because the result and the input are different vector types, widening
2196 // the result could create a legal type but widening the input might make
2197 // it an illegal type that might lead to repeatedly splitting the input
2198 // and then widening it. To avoid this, we widen the input only if
2199 // it results in a legal type.
2200 if (WidenNumElts % InVTNumElts == 0) {
2201 // Widen the input and call convert on the widened input vector.
2202 unsigned NumConcat = WidenNumElts/InVTNumElts;
2203 SmallVector<SDValue, 16> Ops(NumConcat);
2205 SDValue UndefVal = DAG.getUNDEF(InVT);
2206 for (unsigned i = 1; i != NumConcat; ++i)
2208 SDValue InVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InWidenVT, Ops);
2209 if (N->getNumOperands() == 1)
2210 return DAG.getNode(Opcode, DL, WidenVT, InVec);
2211 return DAG.getNode(Opcode, DL, WidenVT, InVec, N->getOperand(1));
2214 if (InVTNumElts % WidenNumElts == 0) {
2215 SDValue InVal = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InWidenVT, InOp,
2216 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2217 // Extract the input and convert the shorten input vector.
2218 if (N->getNumOperands() == 1)
2219 return DAG.getNode(Opcode, DL, WidenVT, InVal);
2220 return DAG.getNode(Opcode, DL, WidenVT, InVal, N->getOperand(1));
2224 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2225 SmallVector<SDValue, 16> Ops(WidenNumElts);
2226 EVT EltVT = WidenVT.getVectorElementType();
2227 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2229 for (i=0; i < MinElts; ++i) {
2230 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, InEltVT, InOp,
2231 DAG.getConstant(i, DL, TLI.getVectorIdxTy()));
2232 if (N->getNumOperands() == 1)
2233 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val);
2235 Ops[i] = DAG.getNode(Opcode, DL, EltVT, Val, N->getOperand(1));
2238 SDValue UndefVal = DAG.getUNDEF(EltVT);
2239 for (; i < WidenNumElts; ++i)
2242 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops);
2245 SDValue DAGTypeLegalizer::WidenVecRes_POWI(SDNode *N) {
2246 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2247 SDValue InOp = GetWidenedVector(N->getOperand(0));
2248 SDValue ShOp = N->getOperand(1);
2249 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2252 SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
2253 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2254 SDValue InOp = GetWidenedVector(N->getOperand(0));
2255 SDValue ShOp = N->getOperand(1);
2257 EVT ShVT = ShOp.getValueType();
2258 if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) {
2259 ShOp = GetWidenedVector(ShOp);
2260 ShVT = ShOp.getValueType();
2262 EVT ShWidenVT = EVT::getVectorVT(*DAG.getContext(),
2263 ShVT.getVectorElementType(),
2264 WidenVT.getVectorNumElements());
2265 if (ShVT != ShWidenVT)
2266 ShOp = ModifyToType(ShOp, ShWidenVT);
2268 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp, ShOp);
2271 SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
2272 // Unary op widening.
2273 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2274 SDValue InOp = GetWidenedVector(N->getOperand(0));
2275 return DAG.getNode(N->getOpcode(), SDLoc(N), WidenVT, InOp);
2278 SDValue DAGTypeLegalizer::WidenVecRes_InregOp(SDNode *N) {
2279 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2280 EVT ExtVT = EVT::getVectorVT(*DAG.getContext(),
2281 cast<VTSDNode>(N->getOperand(1))->getVT()
2282 .getVectorElementType(),
2283 WidenVT.getVectorNumElements());
2284 SDValue WidenLHS = GetWidenedVector(N->getOperand(0));
2285 return DAG.getNode(N->getOpcode(), SDLoc(N),
2286 WidenVT, WidenLHS, DAG.getValueType(ExtVT));
2289 SDValue DAGTypeLegalizer::WidenVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo) {
2290 SDValue WidenVec = DisintegrateMERGE_VALUES(N, ResNo);
2291 return GetWidenedVector(WidenVec);
2294 SDValue DAGTypeLegalizer::WidenVecRes_BITCAST(SDNode *N) {
2295 SDValue InOp = N->getOperand(0);
2296 EVT InVT = InOp.getValueType();
2297 EVT VT = N->getValueType(0);
2298 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2301 switch (getTypeAction(InVT)) {
2302 case TargetLowering::TypeLegal:
2304 case TargetLowering::TypePromoteInteger:
2305 // If the incoming type is a vector that is being promoted, then
2306 // we know that the elements are arranged differently and that we
2307 // must perform the conversion using a stack slot.
2308 if (InVT.isVector())
2311 // If the InOp is promoted to the same size, convert it. Otherwise,
2312 // fall out of the switch and widen the promoted input.
2313 InOp = GetPromotedInteger(InOp);
2314 InVT = InOp.getValueType();
2315 if (WidenVT.bitsEq(InVT))
2316 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2318 case TargetLowering::TypeSoftenFloat:
2319 case TargetLowering::TypePromoteFloat:
2320 case TargetLowering::TypeExpandInteger:
2321 case TargetLowering::TypeExpandFloat:
2322 case TargetLowering::TypeScalarizeVector:
2323 case TargetLowering::TypeSplitVector:
2325 case TargetLowering::TypeWidenVector:
2326 // If the InOp is widened to the same size, convert it. Otherwise, fall
2327 // out of the switch and widen the widened input.
2328 InOp = GetWidenedVector(InOp);
2329 InVT = InOp.getValueType();
2330 if (WidenVT.bitsEq(InVT))
2331 // The input widens to the same size. Convert to the widen value.
2332 return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp);
2336 unsigned WidenSize = WidenVT.getSizeInBits();
2337 unsigned InSize = InVT.getSizeInBits();
2338 // x86mmx is not an acceptable vector element type, so don't try.
2339 if (WidenSize % InSize == 0 && InVT != MVT::x86mmx) {
2340 // Determine new input vector type. The new input vector type will use
2341 // the same element type (if its a vector) or use the input type as a
2342 // vector. It is the same size as the type to widen to.
2344 unsigned NewNumElts = WidenSize / InSize;
2345 if (InVT.isVector()) {
2346 EVT InEltVT = InVT.getVectorElementType();
2347 NewInVT = EVT::getVectorVT(*DAG.getContext(), InEltVT,
2348 WidenSize / InEltVT.getSizeInBits());
2350 NewInVT = EVT::getVectorVT(*DAG.getContext(), InVT, NewNumElts);
2353 if (TLI.isTypeLegal(NewInVT)) {
2354 // Because the result and the input are different vector types, widening
2355 // the result could create a legal type but widening the input might make
2356 // it an illegal type that might lead to repeatedly splitting the input
2357 // and then widening it. To avoid this, we widen the input only if
2358 // it results in a legal type.
2359 SmallVector<SDValue, 16> Ops(NewNumElts);
2360 SDValue UndefVal = DAG.getUNDEF(InVT);
2362 for (unsigned i = 1; i < NewNumElts; ++i)
2366 if (InVT.isVector())
2367 NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
2369 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, Ops);
2370 return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
2374 return CreateStackStoreLoad(InOp, WidenVT);
2377 SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
2379 // Build a vector with undefined for the new nodes.
2380 EVT VT = N->getValueType(0);
2382 // Integer BUILD_VECTOR operands may be larger than the node's vector element
2383 // type. The UNDEFs need to have the same type as the existing operands.
2384 EVT EltVT = N->getOperand(0).getValueType();
2385 unsigned NumElts = VT.getVectorNumElements();
2387 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2388 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2390 SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
2391 assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
2392 NewOps.append(WidenNumElts - NumElts, DAG.getUNDEF(EltVT));
2394 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, NewOps);
2397 SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
2398 EVT InVT = N->getOperand(0).getValueType();
2399 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2401 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2402 unsigned NumInElts = InVT.getVectorNumElements();
2403 unsigned NumOperands = N->getNumOperands();
2405 bool InputWidened = false; // Indicates we need to widen the input.
2406 if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) {
2407 if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) {
2408 // Add undef vectors to widen to correct length.
2409 unsigned NumConcat = WidenVT.getVectorNumElements() /
2410 InVT.getVectorNumElements();
2411 SDValue UndefVal = DAG.getUNDEF(InVT);
2412 SmallVector<SDValue, 16> Ops(NumConcat);
2413 for (unsigned i=0; i < NumOperands; ++i)
2414 Ops[i] = N->getOperand(i);
2415 for (unsigned i = NumOperands; i != NumConcat; ++i)
2417 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, Ops);
2420 InputWidened = true;
2421 if (WidenVT == TLI.getTypeToTransformTo(*DAG.getContext(), InVT)) {
2422 // The inputs and the result are widen to the same value.
2424 for (i=1; i < NumOperands; ++i)
2425 if (N->getOperand(i).getOpcode() != ISD::UNDEF)
2428 if (i == NumOperands)
2429 // Everything but the first operand is an UNDEF so just return the
2430 // widened first operand.
2431 return GetWidenedVector(N->getOperand(0));
2433 if (NumOperands == 2) {
2434 // Replace concat of two operands with a shuffle.
2435 SmallVector<int, 16> MaskOps(WidenNumElts, -1);
2436 for (unsigned i = 0; i < NumInElts; ++i) {
2438 MaskOps[i + NumInElts] = i + WidenNumElts;
2440 return DAG.getVectorShuffle(WidenVT, dl,
2441 GetWidenedVector(N->getOperand(0)),
2442 GetWidenedVector(N->getOperand(1)),
2448 // Fall back to use extracts and build vector.
2449 EVT EltVT = WidenVT.getVectorElementType();
2450 SmallVector<SDValue, 16> Ops(WidenNumElts);
2452 for (unsigned i=0; i < NumOperands; ++i) {
2453 SDValue InOp = N->getOperand(i);
2455 InOp = GetWidenedVector(InOp);
2456 for (unsigned j=0; j < NumInElts; ++j)
2457 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2458 DAG.getConstant(j, dl, TLI.getVectorIdxTy()));
2460 SDValue UndefVal = DAG.getUNDEF(EltVT);
2461 for (; Idx < WidenNumElts; ++Idx)
2462 Ops[Idx] = UndefVal;
2463 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2466 SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) {
2468 SDValue InOp = N->getOperand(0);
2469 SDValue RndOp = N->getOperand(3);
2470 SDValue SatOp = N->getOperand(4);
2472 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2473 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2475 EVT InVT = InOp.getValueType();
2476 EVT InEltVT = InVT.getVectorElementType();
2477 EVT InWidenVT = EVT::getVectorVT(*DAG.getContext(), InEltVT, WidenNumElts);
2479 SDValue DTyOp = DAG.getValueType(WidenVT);
2480 SDValue STyOp = DAG.getValueType(InWidenVT);
2481 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
2483 unsigned InVTNumElts = InVT.getVectorNumElements();
2484 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) {
2485 InOp = GetWidenedVector(InOp);
2486 InVT = InOp.getValueType();
2487 InVTNumElts = InVT.getVectorNumElements();
2488 if (InVTNumElts == WidenNumElts)
2489 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2493 if (TLI.isTypeLegal(InWidenVT)) {
2494 // Because the result and the input are different vector types, widening
2495 // the result could create a legal type but widening the input might make
2496 // it an illegal type that might lead to repeatedly splitting the input
2497 // and then widening it. To avoid this, we widen the input only if
2498 // it results in a legal type.
2499 if (WidenNumElts % InVTNumElts == 0) {
2500 // Widen the input and call convert on the widened input vector.
2501 unsigned NumConcat = WidenNumElts/InVTNumElts;
2502 SmallVector<SDValue, 16> Ops(NumConcat);
2504 SDValue UndefVal = DAG.getUNDEF(InVT);
2505 for (unsigned i = 1; i != NumConcat; ++i)
2508 InOp = DAG.getNode(ISD::CONCAT_VECTORS, dl, InWidenVT, Ops);
2509 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2513 if (InVTNumElts % WidenNumElts == 0) {
2514 // Extract the input and convert the shorten input vector.
2515 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InWidenVT, InOp,
2516 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
2517 return DAG.getConvertRndSat(WidenVT, dl, InOp, DTyOp, STyOp, RndOp,
2522 // Otherwise unroll into some nasty scalar code and rebuild the vector.
2523 SmallVector<SDValue, 16> Ops(WidenNumElts);
2524 EVT EltVT = WidenVT.getVectorElementType();
2525 DTyOp = DAG.getValueType(EltVT);
2526 STyOp = DAG.getValueType(InEltVT);
2528 unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
2530 for (i=0; i < MinElts; ++i) {
2531 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2532 DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
2533 Ops[i] = DAG.getConvertRndSat(WidenVT, dl, ExtVal, DTyOp, STyOp, RndOp,
2537 SDValue UndefVal = DAG.getUNDEF(EltVT);
2538 for (; i < WidenNumElts; ++i)
2541 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2544 SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
2545 EVT VT = N->getValueType(0);
2546 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2547 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2548 SDValue InOp = N->getOperand(0);
2549 SDValue Idx = N->getOperand(1);
2552 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2553 InOp = GetWidenedVector(InOp);
2555 EVT InVT = InOp.getValueType();
2557 // Check if we can just return the input vector after widening.
2558 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2559 if (IdxVal == 0 && InVT == WidenVT)
2562 // Check if we can extract from the vector.
2563 unsigned InNumElts = InVT.getVectorNumElements();
2564 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2565 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, InOp, Idx);
2567 // We could try widening the input to the right length but for now, extract
2568 // the original elements, fill the rest with undefs and build a vector.
2569 SmallVector<SDValue, 16> Ops(WidenNumElts);
2570 EVT EltVT = VT.getVectorElementType();
2571 unsigned NumElts = VT.getVectorNumElements();
2573 for (i=0; i < NumElts; ++i)
2574 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2575 DAG.getConstant(IdxVal + i, dl, TLI.getVectorIdxTy()));
2577 SDValue UndefVal = DAG.getUNDEF(EltVT);
2578 for (; i < WidenNumElts; ++i)
2580 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
2583 SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) {
2584 SDValue InOp = GetWidenedVector(N->getOperand(0));
2585 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N),
2586 InOp.getValueType(), InOp,
2587 N->getOperand(1), N->getOperand(2));
2590 SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
2591 LoadSDNode *LD = cast<LoadSDNode>(N);
2592 ISD::LoadExtType ExtType = LD->getExtensionType();
2595 SmallVector<SDValue, 16> LdChain; // Chain for the series of load
2596 if (ExtType != ISD::NON_EXTLOAD)
2597 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2599 Result = GenWidenVectorLoads(LdChain, LD);
2601 // If we generate a single load, we can use that for the chain. Otherwise,
2602 // build a factor node to remember the multiple loads are independent and
2605 if (LdChain.size() == 1)
2606 NewChain = LdChain[0];
2608 NewChain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other, LdChain);
2610 // Modified the chain - switch anything that used the old chain to use
2612 ReplaceValueWith(SDValue(N, 1), NewChain);
2617 SDValue DAGTypeLegalizer::WidenVecRes_MLOAD(MaskedLoadSDNode *N) {
2619 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),N->getValueType(0));
2620 SDValue Mask = N->getMask();
2621 EVT MaskVT = Mask.getValueType();
2622 SDValue Src0 = GetWidenedVector(N->getSrc0());
2623 ISD::LoadExtType ExtType = N->getExtensionType();
2626 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
2627 Mask = GetWidenedVector(Mask);
2629 EVT BoolVT = getSetCCResultType(WidenVT);
2631 // We can't use ModifyToType() because we should fill the mask with
2633 unsigned WidenNumElts = BoolVT.getVectorNumElements();
2634 unsigned MaskNumElts = MaskVT.getVectorNumElements();
2636 unsigned NumConcat = WidenNumElts / MaskNumElts;
2637 SmallVector<SDValue, 16> Ops(NumConcat);
2638 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
2640 for (unsigned i = 1; i != NumConcat; ++i)
2643 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
2646 SDValue Res = DAG.getMaskedLoad(WidenVT, dl, N->getChain(), N->getBasePtr(),
2647 Mask, Src0, N->getMemoryVT(),
2648 N->getMemOperand(), ExtType);
2649 // Legalized the chain result - switch anything that used the old chain to
2651 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
2655 SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
2656 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2657 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N),
2658 WidenVT, N->getOperand(0));
2661 SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
2662 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2663 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2665 SDValue Cond1 = N->getOperand(0);
2666 EVT CondVT = Cond1.getValueType();
2667 if (CondVT.isVector()) {
2668 EVT CondEltVT = CondVT.getVectorElementType();
2669 EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(),
2670 CondEltVT, WidenNumElts);
2671 if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector)
2672 Cond1 = GetWidenedVector(Cond1);
2674 // If we have to split the condition there is no point in widening the
2675 // select. This would result in an cycle of widening the select ->
2676 // widening the condition operand -> splitting the condition operand ->
2677 // splitting the select -> widening the select. Instead split this select
2678 // further and widen the resulting type.
2679 if (getTypeAction(CondVT) == TargetLowering::TypeSplitVector) {
2680 SDValue SplitSelect = SplitVecOp_VSELECT(N, 0);
2681 SDValue Res = ModifyToType(SplitSelect, WidenVT);
2685 if (Cond1.getValueType() != CondWidenVT)
2686 Cond1 = ModifyToType(Cond1, CondWidenVT);
2689 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
2690 SDValue InOp2 = GetWidenedVector(N->getOperand(2));
2691 assert(InOp1.getValueType() == WidenVT && InOp2.getValueType() == WidenVT);
2692 return DAG.getNode(N->getOpcode(), SDLoc(N),
2693 WidenVT, Cond1, InOp1, InOp2);
2696 SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) {
2697 SDValue InOp1 = GetWidenedVector(N->getOperand(2));
2698 SDValue InOp2 = GetWidenedVector(N->getOperand(3));
2699 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
2700 InOp1.getValueType(), N->getOperand(0),
2701 N->getOperand(1), InOp1, InOp2, N->getOperand(4));
2704 SDValue DAGTypeLegalizer::WidenVecRes_SETCC(SDNode *N) {
2705 assert(N->getValueType(0).isVector() ==
2706 N->getOperand(0).getValueType().isVector() &&
2707 "Scalar/Vector type mismatch");
2708 if (N->getValueType(0).isVector()) return WidenVecRes_VSETCC(N);
2710 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2711 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2712 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2713 return DAG.getNode(ISD::SETCC, SDLoc(N), WidenVT,
2714 InOp1, InOp2, N->getOperand(2));
2717 SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
2718 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2719 return DAG.getUNDEF(WidenVT);
2722 SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
2723 EVT VT = N->getValueType(0);
2726 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2727 unsigned NumElts = VT.getVectorNumElements();
2728 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2730 SDValue InOp1 = GetWidenedVector(N->getOperand(0));
2731 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2733 // Adjust mask based on new input vector length.
2734 SmallVector<int, 16> NewMask;
2735 for (unsigned i = 0; i != NumElts; ++i) {
2736 int Idx = N->getMaskElt(i);
2737 if (Idx < (int)NumElts)
2738 NewMask.push_back(Idx);
2740 NewMask.push_back(Idx - NumElts + WidenNumElts);
2742 for (unsigned i = NumElts; i != WidenNumElts; ++i)
2743 NewMask.push_back(-1);
2744 return DAG.getVectorShuffle(WidenVT, dl, InOp1, InOp2, &NewMask[0]);
2747 SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
2748 assert(N->getValueType(0).isVector() &&
2749 N->getOperand(0).getValueType().isVector() &&
2750 "Operands must be vectors");
2751 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2752 unsigned WidenNumElts = WidenVT.getVectorNumElements();
2754 SDValue InOp1 = N->getOperand(0);
2755 EVT InVT = InOp1.getValueType();
2756 assert(InVT.isVector() && "can not widen non-vector type");
2757 EVT WidenInVT = EVT::getVectorVT(*DAG.getContext(),
2758 InVT.getVectorElementType(), WidenNumElts);
2760 // The input and output types often differ here, and it could be that while
2761 // we'd prefer to widen the result type, the input operands have been split.
2762 // In this case, we also need to split the result of this node as well.
2763 if (getTypeAction(InVT) == TargetLowering::TypeSplitVector) {
2764 SDValue SplitVSetCC = SplitVecOp_VSETCC(N);
2765 SDValue Res = ModifyToType(SplitVSetCC, WidenVT);
2769 InOp1 = GetWidenedVector(InOp1);
2770 SDValue InOp2 = GetWidenedVector(N->getOperand(1));
2772 // Assume that the input and output will be widen appropriately. If not,
2773 // we will have to unroll it at some point.
2774 assert(InOp1.getValueType() == WidenInVT &&
2775 InOp2.getValueType() == WidenInVT &&
2776 "Input not widened to expected type!");
2778 return DAG.getNode(ISD::SETCC, SDLoc(N),
2779 WidenVT, InOp1, InOp2, N->getOperand(2));
2783 //===----------------------------------------------------------------------===//
2784 // Widen Vector Operand
2785 //===----------------------------------------------------------------------===//
2786 bool DAGTypeLegalizer::WidenVectorOperand(SDNode *N, unsigned OpNo) {
2787 DEBUG(dbgs() << "Widen node operand " << OpNo << ": ";
2790 SDValue Res = SDValue();
2792 // See if the target wants to custom widen this node.
2793 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2796 switch (N->getOpcode()) {
2799 dbgs() << "WidenVectorOperand op #" << OpNo << ": ";
2803 llvm_unreachable("Do not know how to widen this operator's operand!");
2805 case ISD::BITCAST: Res = WidenVecOp_BITCAST(N); break;
2806 case ISD::CONCAT_VECTORS: Res = WidenVecOp_CONCAT_VECTORS(N); break;
2807 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecOp_EXTRACT_SUBVECTOR(N); break;
2808 case ISD::EXTRACT_VECTOR_ELT: Res = WidenVecOp_EXTRACT_VECTOR_ELT(N); break;
2809 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
2810 case ISD::MSTORE: Res = WidenVecOp_MSTORE(N, OpNo); break;
2811 case ISD::SETCC: Res = WidenVecOp_SETCC(N); break;
2813 case ISD::ANY_EXTEND:
2814 case ISD::SIGN_EXTEND:
2815 case ISD::ZERO_EXTEND:
2816 Res = WidenVecOp_EXTEND(N);
2819 case ISD::FP_EXTEND:
2820 case ISD::FP_TO_SINT:
2821 case ISD::FP_TO_UINT:
2822 case ISD::SINT_TO_FP:
2823 case ISD::UINT_TO_FP:
2825 Res = WidenVecOp_Convert(N);
2829 // If Res is null, the sub-method took care of registering the result.
2830 if (!Res.getNode()) return false;
2832 // If the result is N, the sub-method updated N in place. Tell the legalizer
2834 if (Res.getNode() == N)
2838 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2839 "Invalid operand expansion");
2841 ReplaceValueWith(SDValue(N, 0), Res);
2845 SDValue DAGTypeLegalizer::WidenVecOp_EXTEND(SDNode *N) {
2847 EVT VT = N->getValueType(0);
2849 SDValue InOp = N->getOperand(0);
2850 // If some legalization strategy other than widening is used on the operand,
2851 // we can't safely assume that just extending the low lanes is the correct
2853 if (getTypeAction(InOp.getValueType()) != TargetLowering::TypeWidenVector)
2854 return WidenVecOp_Convert(N);
2855 InOp = GetWidenedVector(InOp);
2856 assert(VT.getVectorNumElements() <
2857 InOp.getValueType().getVectorNumElements() &&
2858 "Input wasn't widened!");
2860 // We may need to further widen the operand until it has the same total
2861 // vector size as the result.
2862 EVT InVT = InOp.getValueType();
2863 if (InVT.getSizeInBits() != VT.getSizeInBits()) {
2864 EVT InEltVT = InVT.getVectorElementType();
2865 for (int i = MVT::FIRST_VECTOR_VALUETYPE, e = MVT::LAST_VECTOR_VALUETYPE; i < e; ++i) {
2866 EVT FixedVT = (MVT::SimpleValueType)i;
2867 EVT FixedEltVT = FixedVT.getVectorElementType();
2868 if (TLI.isTypeLegal(FixedVT) &&
2869 FixedVT.getSizeInBits() == VT.getSizeInBits() &&
2870 FixedEltVT == InEltVT) {
2871 assert(FixedVT.getVectorNumElements() >= VT.getVectorNumElements() &&
2872 "Not enough elements in the fixed type for the operand!");
2873 assert(FixedVT.getVectorNumElements() != InVT.getVectorNumElements() &&
2874 "We can't have the same type as we started with!");
2875 if (FixedVT.getVectorNumElements() > InVT.getVectorNumElements())
2876 InOp = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, FixedVT,
2877 DAG.getUNDEF(FixedVT), InOp,
2878 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2880 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, FixedVT, InOp,
2881 DAG.getConstant(0, DL, TLI.getVectorIdxTy()));
2885 InVT = InOp.getValueType();
2886 if (InVT.getSizeInBits() != VT.getSizeInBits())
2887 // We couldn't find a legal vector type that was a widening of the input
2888 // and could be extended in-register to the result type, so we have to
2890 return WidenVecOp_Convert(N);
2893 // Use special DAG nodes to represent the operation of extending the
2895 switch (N->getOpcode()) {
2897 llvm_unreachable("Extend legalization on on extend operation!");
2898 case ISD::ANY_EXTEND:
2899 return DAG.getAnyExtendVectorInReg(InOp, DL, VT);
2900 case ISD::SIGN_EXTEND:
2901 return DAG.getSignExtendVectorInReg(InOp, DL, VT);
2902 case ISD::ZERO_EXTEND:
2903 return DAG.getZeroExtendVectorInReg(InOp, DL, VT);
2907 SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) {
2908 // Since the result is legal and the input is illegal, it is unlikely
2909 // that we can fix the input to a legal type so unroll the convert
2910 // into some scalar code and create a nasty build vector.
2911 EVT VT = N->getValueType(0);
2912 EVT EltVT = VT.getVectorElementType();
2914 unsigned NumElts = VT.getVectorNumElements();
2915 SDValue InOp = N->getOperand(0);
2916 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2917 InOp = GetWidenedVector(InOp);
2918 EVT InVT = InOp.getValueType();
2919 EVT InEltVT = InVT.getVectorElementType();
2921 unsigned Opcode = N->getOpcode();
2922 SmallVector<SDValue, 16> Ops(NumElts);
2923 for (unsigned i=0; i < NumElts; ++i)
2924 Ops[i] = DAG.getNode(Opcode, dl, EltVT,
2925 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, InEltVT, InOp,
2926 DAG.getConstant(i, dl,
2927 TLI.getVectorIdxTy())));
2929 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2932 SDValue DAGTypeLegalizer::WidenVecOp_BITCAST(SDNode *N) {
2933 EVT VT = N->getValueType(0);
2934 SDValue InOp = GetWidenedVector(N->getOperand(0));
2935 EVT InWidenVT = InOp.getValueType();
2938 // Check if we can convert between two legal vector types and extract.
2939 unsigned InWidenSize = InWidenVT.getSizeInBits();
2940 unsigned Size = VT.getSizeInBits();
2941 // x86mmx is not an acceptable vector element type, so don't try.
2942 if (InWidenSize % Size == 0 && !VT.isVector() && VT != MVT::x86mmx) {
2943 unsigned NewNumElts = InWidenSize / Size;
2944 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), VT, NewNumElts);
2945 if (TLI.isTypeLegal(NewVT)) {
2946 SDValue BitOp = DAG.getNode(ISD::BITCAST, dl, NewVT, InOp);
2947 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
2948 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
2952 return CreateStackStoreLoad(InOp, VT);
2955 SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) {
2956 // If the input vector is not legal, it is likely that we will not find a
2957 // legal vector of the same size. Replace the concatenate vector with a
2958 // nasty build vector.
2959 EVT VT = N->getValueType(0);
2960 EVT EltVT = VT.getVectorElementType();
2962 unsigned NumElts = VT.getVectorNumElements();
2963 SmallVector<SDValue, 16> Ops(NumElts);
2965 EVT InVT = N->getOperand(0).getValueType();
2966 unsigned NumInElts = InVT.getVectorNumElements();
2969 unsigned NumOperands = N->getNumOperands();
2970 for (unsigned i=0; i < NumOperands; ++i) {
2971 SDValue InOp = N->getOperand(i);
2972 if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector)
2973 InOp = GetWidenedVector(InOp);
2974 for (unsigned j=0; j < NumInElts; ++j)
2975 Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
2976 DAG.getConstant(j, dl, TLI.getVectorIdxTy()));
2978 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
2981 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
2982 SDValue InOp = GetWidenedVector(N->getOperand(0));
2983 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N),
2984 N->getValueType(0), InOp, N->getOperand(1));
2987 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2988 SDValue InOp = GetWidenedVector(N->getOperand(0));
2989 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N),
2990 N->getValueType(0), InOp, N->getOperand(1));
2993 SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) {
2994 // We have to widen the value but we want only to store the original
2996 StoreSDNode *ST = cast<StoreSDNode>(N);
2998 SmallVector<SDValue, 16> StChain;
2999 if (ST->isTruncatingStore())
3000 GenWidenVectorTruncStores(StChain, ST);
3002 GenWidenVectorStores(StChain, ST);
3004 if (StChain.size() == 1)
3007 return DAG.getNode(ISD::TokenFactor, SDLoc(ST), MVT::Other, StChain);
3010 SDValue DAGTypeLegalizer::WidenVecOp_MSTORE(SDNode *N, unsigned OpNo) {
3011 MaskedStoreSDNode *MST = cast<MaskedStoreSDNode>(N);
3012 SDValue Mask = MST->getMask();
3013 EVT MaskVT = Mask.getValueType();
3014 SDValue StVal = MST->getValue();
3016 SDValue WideVal = GetWidenedVector(StVal);
3019 if (OpNo == 2 || getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
3020 Mask = GetWidenedVector(Mask);
3022 // The mask should be widened as well
3023 EVT BoolVT = getSetCCResultType(WideVal.getValueType());
3024 // We can't use ModifyToType() because we should fill the mask with
3026 unsigned WidenNumElts = BoolVT.getVectorNumElements();
3027 unsigned MaskNumElts = MaskVT.getVectorNumElements();
3029 unsigned NumConcat = WidenNumElts / MaskNumElts;
3030 SmallVector<SDValue, 16> Ops(NumConcat);
3031 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
3033 for (unsigned i = 1; i != NumConcat; ++i)
3036 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
3038 assert(Mask.getValueType().getVectorNumElements() ==
3039 WideVal.getValueType().getVectorNumElements() &&
3040 "Mask and data vectors should have the same number of elements");
3041 return DAG.getMaskedStore(MST->getChain(), dl, WideVal, MST->getBasePtr(),
3042 Mask, MST->getMemoryVT(), MST->getMemOperand(),
3046 SDValue DAGTypeLegalizer::WidenVecOp_SETCC(SDNode *N) {
3047 SDValue InOp0 = GetWidenedVector(N->getOperand(0));
3048 SDValue InOp1 = GetWidenedVector(N->getOperand(1));
3051 // WARNING: In this code we widen the compare instruction with garbage.
3052 // This garbage may contain denormal floats which may be slow. Is this a real
3053 // concern ? Should we zero the unused lanes if this is a float compare ?
3055 // Get a new SETCC node to compare the newly widened operands.
3056 // Only some of the compared elements are legal.
3057 EVT SVT = TLI.getSetCCResultType(*DAG.getContext(), InOp0.getValueType());
3058 SDValue WideSETCC = DAG.getNode(ISD::SETCC, SDLoc(N),
3059 SVT, InOp0, InOp1, N->getOperand(2));
3061 // Extract the needed results from the result vector.
3062 EVT ResVT = EVT::getVectorVT(*DAG.getContext(),
3063 SVT.getVectorElementType(),
3064 N->getValueType(0).getVectorNumElements());
3065 SDValue CC = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl,
3067 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3069 return PromoteTargetBoolean(CC, N->getValueType(0));
3073 //===----------------------------------------------------------------------===//
3074 // Vector Widening Utilities
3075 //===----------------------------------------------------------------------===//
3077 // Utility function to find the type to chop up a widen vector for load/store
3078 // TLI: Target lowering used to determine legal types.
3079 // Width: Width left need to load/store.
3080 // WidenVT: The widen vector type to load to/store from
3081 // Align: If 0, don't allow use of a wider type
3082 // WidenEx: If Align is not 0, the amount additional we can load/store from.
3084 static EVT FindMemType(SelectionDAG& DAG, const TargetLowering &TLI,
3085 unsigned Width, EVT WidenVT,
3086 unsigned Align = 0, unsigned WidenEx = 0) {
3087 EVT WidenEltVT = WidenVT.getVectorElementType();
3088 unsigned WidenWidth = WidenVT.getSizeInBits();
3089 unsigned WidenEltWidth = WidenEltVT.getSizeInBits();
3090 unsigned AlignInBits = Align*8;
3092 // If we have one element to load/store, return it.
3093 EVT RetVT = WidenEltVT;
3094 if (Width == WidenEltWidth)
3097 // See if there is larger legal integer than the element type to load/store
3099 for (VT = (unsigned)MVT::LAST_INTEGER_VALUETYPE;
3100 VT >= (unsigned)MVT::FIRST_INTEGER_VALUETYPE; --VT) {
3101 EVT MemVT((MVT::SimpleValueType) VT);
3102 unsigned MemVTWidth = MemVT.getSizeInBits();
3103 if (MemVT.getSizeInBits() <= WidenEltWidth)
3105 auto Action = TLI.getTypeAction(*DAG.getContext(), MemVT);
3106 if ((Action == TargetLowering::TypeLegal ||
3107 Action == TargetLowering::TypePromoteInteger) &&
3108 (WidenWidth % MemVTWidth) == 0 &&
3109 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3110 (MemVTWidth <= Width ||
3111 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3117 // See if there is a larger vector type to load/store that has the same vector
3118 // element type and is evenly divisible with the WidenVT.
3119 for (VT = (unsigned)MVT::LAST_VECTOR_VALUETYPE;
3120 VT >= (unsigned)MVT::FIRST_VECTOR_VALUETYPE; --VT) {
3121 EVT MemVT = (MVT::SimpleValueType) VT;
3122 unsigned MemVTWidth = MemVT.getSizeInBits();
3123 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() &&
3124 (WidenWidth % MemVTWidth) == 0 &&
3125 isPowerOf2_32(WidenWidth / MemVTWidth) &&
3126 (MemVTWidth <= Width ||
3127 (Align!=0 && MemVTWidth<=AlignInBits && MemVTWidth<=Width+WidenEx))) {
3128 if (RetVT.getSizeInBits() < MemVTWidth || MemVT == WidenVT)
3136 // Builds a vector type from scalar loads
3137 // VecTy: Resulting Vector type
3138 // LDOps: Load operators to build a vector type
3139 // [Start,End) the list of loads to use.
3140 static SDValue BuildVectorFromScalar(SelectionDAG& DAG, EVT VecTy,
3141 SmallVectorImpl<SDValue> &LdOps,
3142 unsigned Start, unsigned End) {
3143 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3144 SDLoc dl(LdOps[Start]);
3145 EVT LdTy = LdOps[Start].getValueType();
3146 unsigned Width = VecTy.getSizeInBits();
3147 unsigned NumElts = Width / LdTy.getSizeInBits();
3148 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), LdTy, NumElts);
3151 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT,LdOps[Start]);
3153 for (unsigned i = Start + 1; i != End; ++i) {
3154 EVT NewLdTy = LdOps[i].getValueType();
3155 if (NewLdTy != LdTy) {
3156 NumElts = Width / NewLdTy.getSizeInBits();
3157 NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewLdTy, NumElts);
3158 VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, VecOp);
3159 // Readjust position and vector position based on new load type
3160 Idx = Idx * LdTy.getSizeInBits() / NewLdTy.getSizeInBits();
3163 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVecVT, VecOp, LdOps[i],
3164 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy()));
3166 return DAG.getNode(ISD::BITCAST, dl, VecTy, VecOp);
3169 SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
3171 // The strategy assumes that we can efficiently load powers of two widths.
3172 // The routines chops the vector into the largest vector loads with the same
3173 // element type or scalar loads and then recombines it to the widen vector
3175 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3176 unsigned WidenWidth = WidenVT.getSizeInBits();
3177 EVT LdVT = LD->getMemoryVT();
3179 assert(LdVT.isVector() && WidenVT.isVector());
3180 assert(LdVT.getVectorElementType() == WidenVT.getVectorElementType());
3183 SDValue Chain = LD->getChain();
3184 SDValue BasePtr = LD->getBasePtr();
3185 unsigned Align = LD->getAlignment();
3186 bool isVolatile = LD->isVolatile();
3187 bool isNonTemporal = LD->isNonTemporal();
3188 bool isInvariant = LD->isInvariant();
3189 AAMDNodes AAInfo = LD->getAAInfo();
3191 int LdWidth = LdVT.getSizeInBits();
3192 int WidthDiff = WidenWidth - LdWidth; // Difference
3193 unsigned LdAlign = (isVolatile) ? 0 : Align; // Allow wider loads
3195 // Find the vector type that can load from.
3196 EVT NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3197 int NewVTWidth = NewVT.getSizeInBits();
3198 SDValue LdOp = DAG.getLoad(NewVT, dl, Chain, BasePtr, LD->getPointerInfo(),
3199 isVolatile, isNonTemporal, isInvariant, Align,
3201 LdChain.push_back(LdOp.getValue(1));
3203 // Check if we can load the element with one instruction
3204 if (LdWidth <= NewVTWidth) {
3205 if (!NewVT.isVector()) {
3206 unsigned NumElts = WidenWidth / NewVTWidth;
3207 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3208 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
3209 return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
3211 if (NewVT == WidenVT)
3214 assert(WidenWidth % NewVTWidth == 0);
3215 unsigned NumConcat = WidenWidth / NewVTWidth;
3216 SmallVector<SDValue, 16> ConcatOps(NumConcat);
3217 SDValue UndefVal = DAG.getUNDEF(NewVT);
3218 ConcatOps[0] = LdOp;
3219 for (unsigned i = 1; i != NumConcat; ++i)
3220 ConcatOps[i] = UndefVal;
3221 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, ConcatOps);
3224 // Load vector by using multiple loads from largest vector to scalar
3225 SmallVector<SDValue, 16> LdOps;
3226 LdOps.push_back(LdOp);
3228 LdWidth -= NewVTWidth;
3229 unsigned Offset = 0;
3231 while (LdWidth > 0) {
3232 unsigned Increment = NewVTWidth / 8;
3233 Offset += Increment;
3234 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3235 DAG.getConstant(Increment, dl, BasePtr.getValueType()));
3238 if (LdWidth < NewVTWidth) {
3239 // Our current type we are using is too large, find a better size
3240 NewVT = FindMemType(DAG, TLI, LdWidth, WidenVT, LdAlign, WidthDiff);
3241 NewVTWidth = NewVT.getSizeInBits();
3242 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3243 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3244 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3246 LdChain.push_back(L.getValue(1));
3247 if (L->getValueType(0).isVector()) {
3248 SmallVector<SDValue, 16> Loads;
3250 unsigned size = L->getValueSizeInBits(0);
3251 while (size < LdOp->getValueSizeInBits(0)) {
3252 Loads.push_back(DAG.getUNDEF(L->getValueType(0)));
3253 size += L->getValueSizeInBits(0);
3255 L = DAG.getNode(ISD::CONCAT_VECTORS, dl, LdOp->getValueType(0), Loads);
3258 L = DAG.getLoad(NewVT, dl, Chain, BasePtr,
3259 LD->getPointerInfo().getWithOffset(Offset), isVolatile,
3260 isNonTemporal, isInvariant, MinAlign(Align, Increment),
3262 LdChain.push_back(L.getValue(1));
3268 LdWidth -= NewVTWidth;
3271 // Build the vector from the loads operations
3272 unsigned End = LdOps.size();
3273 if (!LdOps[0].getValueType().isVector())
3274 // All the loads are scalar loads.
3275 return BuildVectorFromScalar(DAG, WidenVT, LdOps, 0, End);
3277 // If the load contains vectors, build the vector using concat vector.
3278 // All of the vectors used to loads are power of 2 and the scalars load
3279 // can be combined to make a power of 2 vector.
3280 SmallVector<SDValue, 16> ConcatOps(End);
3283 EVT LdTy = LdOps[i].getValueType();
3284 // First combine the scalar loads to a vector
3285 if (!LdTy.isVector()) {
3286 for (--i; i >= 0; --i) {
3287 LdTy = LdOps[i].getValueType();
3288 if (LdTy.isVector())
3291 ConcatOps[--Idx] = BuildVectorFromScalar(DAG, LdTy, LdOps, i+1, End);
3293 ConcatOps[--Idx] = LdOps[i];
3294 for (--i; i >= 0; --i) {
3295 EVT NewLdTy = LdOps[i].getValueType();
3296 if (NewLdTy != LdTy) {
3297 // Create a larger vector
3298 ConcatOps[End-1] = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewLdTy,
3299 makeArrayRef(&ConcatOps[Idx], End - Idx));
3303 ConcatOps[--Idx] = LdOps[i];
3306 if (WidenWidth == LdTy.getSizeInBits()*(End - Idx))
3307 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
3308 makeArrayRef(&ConcatOps[Idx], End - Idx));
3310 // We need to fill the rest with undefs to build the vector
3311 unsigned NumOps = WidenWidth / LdTy.getSizeInBits();
3312 SmallVector<SDValue, 16> WidenOps(NumOps);
3313 SDValue UndefVal = DAG.getUNDEF(LdTy);
3316 for (; i != End-Idx; ++i)
3317 WidenOps[i] = ConcatOps[Idx+i];
3318 for (; i != NumOps; ++i)
3319 WidenOps[i] = UndefVal;
3321 return DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT, WidenOps);
3325 DAGTypeLegalizer::GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain,
3327 ISD::LoadExtType ExtType) {
3328 // For extension loads, it may not be more efficient to chop up the vector
3329 // and then extended it. Instead, we unroll the load and build a new vector.
3330 EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(),LD->getValueType(0));
3331 EVT LdVT = LD->getMemoryVT();
3333 assert(LdVT.isVector() && WidenVT.isVector());
3336 SDValue Chain = LD->getChain();
3337 SDValue BasePtr = LD->getBasePtr();
3338 unsigned Align = LD->getAlignment();
3339 bool isVolatile = LD->isVolatile();
3340 bool isNonTemporal = LD->isNonTemporal();
3341 bool isInvariant = LD->isInvariant();
3342 AAMDNodes AAInfo = LD->getAAInfo();
3344 EVT EltVT = WidenVT.getVectorElementType();
3345 EVT LdEltVT = LdVT.getVectorElementType();
3346 unsigned NumElts = LdVT.getVectorNumElements();
3348 // Load each element and widen
3349 unsigned WidenNumElts = WidenVT.getVectorNumElements();
3350 SmallVector<SDValue, 16> Ops(WidenNumElts);
3351 unsigned Increment = LdEltVT.getSizeInBits() / 8;
3352 Ops[0] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, BasePtr,
3353 LD->getPointerInfo(),
3354 LdEltVT, isVolatile, isNonTemporal, isInvariant,
3356 LdChain.push_back(Ops[0].getValue(1));
3357 unsigned i = 0, Offset = Increment;
3358 for (i=1; i < NumElts; ++i, Offset += Increment) {
3359 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3361 DAG.getConstant(Offset, dl,
3362 BasePtr.getValueType()));
3363 Ops[i] = DAG.getExtLoad(ExtType, dl, EltVT, Chain, NewBasePtr,
3364 LD->getPointerInfo().getWithOffset(Offset), LdEltVT,
3365 isVolatile, isNonTemporal, isInvariant, Align,
3367 LdChain.push_back(Ops[i].getValue(1));
3370 // Fill the rest with undefs
3371 SDValue UndefVal = DAG.getUNDEF(EltVT);
3372 for (; i != WidenNumElts; ++i)
3375 return DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT, Ops);
3379 void DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
3381 // The strategy assumes that we can efficiently store powers of two widths.
3382 // The routines chops the vector into the largest vector stores with the same
3383 // element type or scalar stores.
3384 SDValue Chain = ST->getChain();
3385 SDValue BasePtr = ST->getBasePtr();
3386 unsigned Align = ST->getAlignment();
3387 bool isVolatile = ST->isVolatile();
3388 bool isNonTemporal = ST->isNonTemporal();
3389 AAMDNodes AAInfo = ST->getAAInfo();
3390 SDValue ValOp = GetWidenedVector(ST->getValue());
3393 EVT StVT = ST->getMemoryVT();
3394 unsigned StWidth = StVT.getSizeInBits();
3395 EVT ValVT = ValOp.getValueType();
3396 unsigned ValWidth = ValVT.getSizeInBits();
3397 EVT ValEltVT = ValVT.getVectorElementType();
3398 unsigned ValEltWidth = ValEltVT.getSizeInBits();
3399 assert(StVT.getVectorElementType() == ValEltVT);
3401 int Idx = 0; // current index to store
3402 unsigned Offset = 0; // offset from base to store
3403 while (StWidth != 0) {
3404 // Find the largest vector type we can store with
3405 EVT NewVT = FindMemType(DAG, TLI, StWidth, ValVT);
3406 unsigned NewVTWidth = NewVT.getSizeInBits();
3407 unsigned Increment = NewVTWidth / 8;
3408 if (NewVT.isVector()) {
3409 unsigned NumVTElts = NewVT.getVectorNumElements();
3411 SDValue EOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT, ValOp,
3412 DAG.getConstant(Idx, dl,
3413 TLI.getVectorIdxTy()));
3414 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3415 ST->getPointerInfo().getWithOffset(Offset),
3416 isVolatile, isNonTemporal,
3417 MinAlign(Align, Offset), AAInfo));
3418 StWidth -= NewVTWidth;
3419 Offset += Increment;
3421 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3422 DAG.getConstant(Increment, dl,
3423 BasePtr.getValueType()));
3424 } while (StWidth != 0 && StWidth >= NewVTWidth);
3426 // Cast the vector to the scalar type we can store
3427 unsigned NumElts = ValWidth / NewVTWidth;
3428 EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
3429 SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
3430 // Readjust index position based on new vector type
3431 Idx = Idx * ValEltWidth / NewVTWidth;
3433 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
3434 DAG.getConstant(Idx++, dl, TLI.getVectorIdxTy()));
3435 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr,
3436 ST->getPointerInfo().getWithOffset(Offset),
3437 isVolatile, isNonTemporal,
3438 MinAlign(Align, Offset), AAInfo));
3439 StWidth -= NewVTWidth;
3440 Offset += Increment;
3441 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
3442 DAG.getConstant(Increment, dl,
3443 BasePtr.getValueType()));
3444 } while (StWidth != 0 && StWidth >= NewVTWidth);
3445 // Restore index back to be relative to the original widen element type
3446 Idx = Idx * NewVTWidth / ValEltWidth;
3452 DAGTypeLegalizer::GenWidenVectorTruncStores(SmallVectorImpl<SDValue> &StChain,
3454 // For extension loads, it may not be more efficient to truncate the vector
3455 // and then store it. Instead, we extract each element and then store it.
3456 SDValue Chain = ST->getChain();
3457 SDValue BasePtr = ST->getBasePtr();
3458 unsigned Align = ST->getAlignment();
3459 bool isVolatile = ST->isVolatile();
3460 bool isNonTemporal = ST->isNonTemporal();
3461 AAMDNodes AAInfo = ST->getAAInfo();
3462 SDValue ValOp = GetWidenedVector(ST->getValue());
3465 EVT StVT = ST->getMemoryVT();
3466 EVT ValVT = ValOp.getValueType();
3468 // It must be true that we the widen vector type is bigger than where
3469 // we need to store.
3470 assert(StVT.isVector() && ValOp.getValueType().isVector());
3471 assert(StVT.bitsLT(ValOp.getValueType()));
3473 // For truncating stores, we can not play the tricks of chopping legal
3474 // vector types and bit cast it to the right type. Instead, we unroll
3476 EVT StEltVT = StVT.getVectorElementType();
3477 EVT ValEltVT = ValVT.getVectorElementType();
3478 unsigned Increment = ValEltVT.getSizeInBits() / 8;
3479 unsigned NumElts = StVT.getVectorNumElements();
3480 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3481 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3482 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, BasePtr,
3483 ST->getPointerInfo(), StEltVT,
3484 isVolatile, isNonTemporal, Align,
3486 unsigned Offset = Increment;
3487 for (unsigned i=1; i < NumElts; ++i, Offset += Increment) {
3488 SDValue NewBasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(),
3490 DAG.getConstant(Offset, dl,
3491 BasePtr.getValueType()));
3492 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
3493 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3494 StChain.push_back(DAG.getTruncStore(Chain, dl, EOp, NewBasePtr,
3495 ST->getPointerInfo().getWithOffset(Offset),
3496 StEltVT, isVolatile, isNonTemporal,
3497 MinAlign(Align, Offset), AAInfo));
3501 /// Modifies a vector input (widen or narrows) to a vector of NVT. The
3502 /// input vector must have the same element type as NVT.
3503 SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
3504 // Note that InOp might have been widened so it might already have
3505 // the right width or it might need be narrowed.
3506 EVT InVT = InOp.getValueType();
3507 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
3508 "input and widen element type must match");
3511 // Check if InOp already has the right width.
3515 unsigned InNumElts = InVT.getVectorNumElements();
3516 unsigned WidenNumElts = NVT.getVectorNumElements();
3517 if (WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0) {
3518 unsigned NumConcat = WidenNumElts / InNumElts;
3519 SmallVector<SDValue, 16> Ops(NumConcat);
3520 SDValue UndefVal = DAG.getUNDEF(InVT);
3522 for (unsigned i = 1; i != NumConcat; ++i)
3525 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, Ops);
3528 if (WidenNumElts < InNumElts && InNumElts % WidenNumElts)
3529 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp,
3530 DAG.getConstant(0, dl, TLI.getVectorIdxTy()));
3532 // Fall back to extract and build.
3533 SmallVector<SDValue, 16> Ops(WidenNumElts);
3534 EVT EltVT = NVT.getVectorElementType();
3535 unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
3537 for (Idx = 0; Idx < MinNumElts; ++Idx)
3538 Ops[Idx] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp,
3539 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
3541 SDValue UndefVal = DAG.getUNDEF(EltVT);
3542 for ( ; Idx < WidenNumElts; ++Idx)
3543 Ops[Idx] = UndefVal;
3544 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);