1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file performs vector type splitting and scalarization for LegalizeTypes.
11 // Scalarization is the act of changing a computation in an illegal one-element
12 // vector type to be a computation in its scalar element type. For example,
13 // implementing <1 x f32> arithmetic in a scalar f32 register. This is needed
14 // as a base case when scalarizing vector arithmetic like <4 x f32>, which
15 // eventually decomposes to scalars if the target doesn't support v4f32 or v2f32
17 // Splitting is the act of changing a computation in an invalid vector type to
18 // be a computation in multiple vectors of a smaller type. For example,
19 // implementing <128 x f32> operations in terms of two <64 x f32> operations.
21 //===----------------------------------------------------------------------===//
23 #include "LegalizeTypes.h"
24 #include "llvm/Target/TargetData.h"
27 //===----------------------------------------------------------------------===//
28 // Result Vector Scalarization: <1 x ty> -> ty.
29 //===----------------------------------------------------------------------===//
31 void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
32 DEBUG(cerr << "Scalarize node result " << ResNo << ": "; N->dump(&DAG);
34 SDValue R = SDValue();
36 switch (N->getOpcode()) {
39 cerr << "ScalarizeVectorResult #" << ResNo << ": ";
40 N->dump(&DAG); cerr << "\n";
42 assert(0 && "Do not know how to scalarize the result of this operator!");
45 case ISD::BIT_CONVERT: R = ScalarizeVecRes_BIT_CONVERT(N); break;
46 case ISD::BUILD_VECTOR: R = N->getOperand(0); break;
47 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break;
48 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
49 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
50 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
51 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break;
52 case ISD::SCALAR_TO_VECTOR: R = ScalarizeVecRes_SCALAR_TO_VECTOR(N); break;
53 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
54 case ISD::SELECT_CC: R = ScalarizeVecRes_SELECT_CC(N); break;
55 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
56 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
57 case ISD::VSETCC: R = ScalarizeVecRes_VSETCC(N); break;
76 case ISD::UINT_TO_FP: R = ScalarizeVecRes_UnaryOp(N); break;
93 case ISD::XOR: R = ScalarizeVecRes_BinOp(N); break;
96 // If R is null, the sub-method took care of registering the result.
98 SetScalarizedVector(SDValue(N, ResNo), R);
101 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
102 SDValue LHS = GetScalarizedVector(N->getOperand(0));
103 SDValue RHS = GetScalarizedVector(N->getOperand(1));
104 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
107 SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
108 MVT NewVT = N->getValueType(0).getVectorElementType();
109 return DAG.getNode(ISD::BIT_CONVERT, NewVT, N->getOperand(0));
112 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
113 MVT NewVT = N->getValueType(0).getVectorElementType();
114 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
115 return DAG.getConvertRndSat(NewVT, Op0, DAG.getValueType(NewVT),
116 DAG.getValueType(Op0.getValueType()),
119 cast<CvtRndSatSDNode>(N)->getCvtCode());
122 SDValue DAGTypeLegalizer::ScalarizeVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
123 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
124 N->getValueType(0).getVectorElementType(),
125 N->getOperand(0), N->getOperand(1));
128 SDValue DAGTypeLegalizer::ScalarizeVecRes_FPOWI(SDNode *N) {
129 SDValue Op = GetScalarizedVector(N->getOperand(0));
130 return DAG.getNode(ISD::FPOWI, Op.getValueType(), Op, N->getOperand(1));
133 SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) {
134 // The value to insert may have a wider type than the vector element type,
135 // so be sure to truncate it to the element type if necessary.
136 SDValue Op = N->getOperand(1);
137 MVT EltVT = N->getValueType(0).getVectorElementType();
138 if (Op.getValueType() != EltVT)
139 // FIXME: Can this happen for floating point types?
140 Op = DAG.getNode(ISD::TRUNCATE, EltVT, Op);
144 SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) {
145 assert(N->isUnindexed() && "Indexed vector load?");
147 SDValue Result = DAG.getLoad(ISD::UNINDEXED, N->getExtensionType(),
148 N->getValueType(0).getVectorElementType(),
149 N->getChain(), N->getBasePtr(),
150 DAG.getNode(ISD::UNDEF,
151 N->getBasePtr().getValueType()),
152 N->getSrcValue(), N->getSrcValueOffset(),
153 N->getMemoryVT().getVectorElementType(),
154 N->isVolatile(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Result.getValue(1));
162 SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
163 // Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
164 MVT DestVT = N->getValueType(0).getVectorElementType();
165 SDValue Op = GetScalarizedVector(N->getOperand(0));
166 return DAG.getNode(N->getOpcode(), DestVT, Op);
169 SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
170 return N->getOperand(0);
173 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT(SDNode *N) {
174 SDValue LHS = GetScalarizedVector(N->getOperand(1));
175 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0), LHS,
176 GetScalarizedVector(N->getOperand(2)));
179 SDValue DAGTypeLegalizer::ScalarizeVecRes_SELECT_CC(SDNode *N) {
180 SDValue LHS = GetScalarizedVector(N->getOperand(2));
181 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(),
182 N->getOperand(0), N->getOperand(1),
183 LHS, GetScalarizedVector(N->getOperand(3)),
187 SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
188 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
191 SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) {
192 // Figure out if the scalar is the LHS or RHS and return it.
193 SDValue Arg = N->getOperand(2).getOperand(0);
194 if (Arg.getOpcode() == ISD::UNDEF)
195 return DAG.getNode(ISD::UNDEF, N->getValueType(0).getVectorElementType());
196 unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
197 return GetScalarizedVector(N->getOperand(Op));
200 SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
201 SDValue LHS = GetScalarizedVector(N->getOperand(0));
202 SDValue RHS = GetScalarizedVector(N->getOperand(1));
203 MVT NVT = N->getValueType(0).getVectorElementType();
204 MVT SVT = TLI.getSetCCResultType(LHS);
206 // Turn it into a scalar SETCC.
207 SDValue Res = DAG.getNode(ISD::SETCC, SVT, LHS, RHS, N->getOperand(2));
209 // VSETCC always returns a sign-extended value, while SETCC may not. The
210 // SETCC result type may not match the vector element type. Correct these.
211 if (NVT.bitsLE(SVT)) {
212 // The SETCC result type is bigger than the vector element type.
213 // Ensure the SETCC result is sign-extended.
214 if (TLI.getBooleanContents() !=
215 TargetLowering::ZeroOrNegativeOneBooleanContent)
216 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, SVT, Res,
217 DAG.getValueType(MVT::i1));
218 // Truncate to the final type.
219 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
221 // The SETCC result type is smaller than the vector element type.
222 // If the SetCC result is not sign-extended, chop it down to MVT::i1.
223 if (TLI.getBooleanContents() !=
224 TargetLowering::ZeroOrNegativeOneBooleanContent)
225 Res = DAG.getNode(ISD::TRUNCATE, MVT::i1, Res);
226 // Sign extend to the final type.
227 return DAG.getNode(ISD::SIGN_EXTEND, NVT, Res);
232 //===----------------------------------------------------------------------===//
233 // Operand Vector Scalarization <1 x ty> -> ty.
234 //===----------------------------------------------------------------------===//
236 bool DAGTypeLegalizer::ScalarizeVectorOperand(SDNode *N, unsigned OpNo) {
237 DEBUG(cerr << "Scalarize node operand " << OpNo << ": "; N->dump(&DAG);
239 SDValue Res = SDValue();
241 if (Res.getNode() == 0) {
242 switch (N->getOpcode()) {
245 cerr << "ScalarizeVectorOperand Op #" << OpNo << ": ";
246 N->dump(&DAG); cerr << "\n";
248 assert(0 && "Do not know how to scalarize this operator's operand!");
251 case ISD::BIT_CONVERT:
252 Res = ScalarizeVecOp_BIT_CONVERT(N); break;
254 case ISD::CONCAT_VECTORS:
255 Res = ScalarizeVecOp_CONCAT_VECTORS(N); break;
257 case ISD::EXTRACT_VECTOR_ELT:
258 Res = ScalarizeVecOp_EXTRACT_VECTOR_ELT(N); break;
261 Res = ScalarizeVecOp_STORE(cast<StoreSDNode>(N), OpNo); break;
265 // If the result is null, the sub-method took care of registering results etc.
266 if (!Res.getNode()) return false;
268 // If the result is N, the sub-method updated N in place. Tell the legalizer
270 if (Res.getNode() == N)
273 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
274 "Invalid operand expansion");
276 ReplaceValueWith(SDValue(N, 0), Res);
280 /// ScalarizeVecOp_BIT_CONVERT - If the value to convert is a vector that needs
281 /// to be scalarized, it must be <1 x ty>. Convert the element instead.
282 SDValue DAGTypeLegalizer::ScalarizeVecOp_BIT_CONVERT(SDNode *N) {
283 SDValue Elt = GetScalarizedVector(N->getOperand(0));
284 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Elt);
287 /// ScalarizeVecOp_CONCAT_VECTORS - The vectors to concatenate have length one -
288 /// use a BUILD_VECTOR instead.
289 SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
290 SmallVector<SDValue, 8> Ops(N->getNumOperands());
291 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
292 Ops[i] = GetScalarizedVector(N->getOperand(i));
293 return DAG.getNode(ISD::BUILD_VECTOR, N->getValueType(0),
294 &Ops[0], Ops.size());
297 /// ScalarizeVecOp_EXTRACT_VECTOR_ELT - If the input is a vector that needs to
298 /// be scalarized, it must be <1 x ty>, so just return the element, ignoring the
300 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
301 return GetScalarizedVector(N->getOperand(0));
304 /// ScalarizeVecOp_STORE - If the value to store is a vector that needs to be
305 /// scalarized, it must be <1 x ty>. Just store the element.
306 SDValue DAGTypeLegalizer::ScalarizeVecOp_STORE(StoreSDNode *N, unsigned OpNo){
307 assert(N->isUnindexed() && "Indexed store of one-element vector?");
308 assert(OpNo == 1 && "Do not know how to scalarize this operand!");
310 if (N->isTruncatingStore())
311 return DAG.getTruncStore(N->getChain(),
312 GetScalarizedVector(N->getOperand(1)),
314 N->getSrcValue(), N->getSrcValueOffset(),
315 N->getMemoryVT().getVectorElementType(),
316 N->isVolatile(), N->getAlignment());
318 return DAG.getStore(N->getChain(), GetScalarizedVector(N->getOperand(1)),
319 N->getBasePtr(), N->getSrcValue(), N->getSrcValueOffset(),
320 N->isVolatile(), N->getAlignment());
324 //===----------------------------------------------------------------------===//
325 // Result Vector Splitting
326 //===----------------------------------------------------------------------===//
328 /// SplitVectorResult - This method is called when the specified result of the
329 /// specified node is found to need vector splitting. At this point, the node
330 /// may also have invalid operands or may have other results that need
331 /// legalization, we just know that (at least) one result needs vector
333 void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
334 DEBUG(cerr << "Split node result: "; N->dump(&DAG); cerr << "\n");
337 switch (N->getOpcode()) {
340 cerr << "SplitVectorResult #" << ResNo << ": ";
341 N->dump(&DAG); cerr << "\n";
343 assert(0 && "Do not know how to split the result of this operator!");
346 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
347 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
348 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
349 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
351 case ISD::BIT_CONVERT: SplitVecRes_BIT_CONVERT(N, Lo, Hi); break;
352 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
353 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
354 case ISD::CONVERT_RNDSAT: SplitVecRes_CONVERT_RNDSAT(N, Lo, Hi); break;
355 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
356 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
357 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
358 case ISD::SCALAR_TO_VECTOR: SplitVecRes_SCALAR_TO_VECTOR(N, Lo, Hi); break;
359 case ISD::LOAD: SplitVecRes_LOAD(cast<LoadSDNode>(N), Lo, Hi);break;
360 case ISD::VECTOR_SHUFFLE: SplitVecRes_VECTOR_SHUFFLE(N, Lo, Hi); break;
361 case ISD::VSETCC: SplitVecRes_VSETCC(N, Lo, Hi); break;
375 case ISD::FNEARBYINT:
376 case ISD::FP_TO_SINT:
377 case ISD::FP_TO_UINT:
378 case ISD::SINT_TO_FP:
380 case ISD::UINT_TO_FP: SplitVecRes_UnaryOp(N, Lo, Hi); break;
397 case ISD::FREM: SplitVecRes_BinOp(N, Lo, Hi); break;
400 // If Lo/Hi is null, the sub-method took care of registering results etc.
402 SetSplitVector(SDValue(N, ResNo), Lo, Hi);
405 void DAGTypeLegalizer::SplitVecRes_BinOp(SDNode *N, SDValue &Lo,
407 SDValue LHSLo, LHSHi;
408 GetSplitVector(N->getOperand(0), LHSLo, LHSHi);
409 SDValue RHSLo, RHSHi;
410 GetSplitVector(N->getOperand(1), RHSLo, RHSHi);
412 Lo = DAG.getNode(N->getOpcode(), LHSLo.getValueType(), LHSLo, RHSLo);
413 Hi = DAG.getNode(N->getOpcode(), LHSHi.getValueType(), LHSHi, RHSHi);
416 void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
418 // We know the result is a vector. The input may be either a vector or a
421 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
423 SDValue InOp = N->getOperand(0);
424 MVT InVT = InOp.getValueType();
426 // Handle some special cases efficiently.
427 switch (getTypeAction(InVT)) {
429 assert(false && "Unknown type action!");
433 case ScalarizeVector:
437 // A scalar to vector conversion, where the scalar needs expansion.
438 // If the vector is being split in two then we can just convert the
441 GetExpandedOp(InOp, Lo, Hi);
442 if (TLI.isBigEndian())
444 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
445 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
450 // If the input is a vector that needs to be split, convert each split
451 // piece of the input now.
452 GetSplitVector(InOp, Lo, Hi);
453 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
454 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
458 // In the general case, convert the input to an integer and split it by hand.
459 MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
460 MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
461 if (TLI.isBigEndian())
462 std::swap(LoIntVT, HiIntVT);
464 SplitInteger(BitConvertToInteger(InOp), LoIntVT, HiIntVT, Lo, Hi);
466 if (TLI.isBigEndian())
468 Lo = DAG.getNode(ISD::BIT_CONVERT, LoVT, Lo);
469 Hi = DAG.getNode(ISD::BIT_CONVERT, HiVT, Hi);
472 void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
475 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
476 unsigned LoNumElts = LoVT.getVectorNumElements();
477 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+LoNumElts);
478 Lo = DAG.getNode(ISD::BUILD_VECTOR, LoVT, &LoOps[0], LoOps.size());
480 SmallVector<SDValue, 8> HiOps(N->op_begin()+LoNumElts, N->op_end());
481 Hi = DAG.getNode(ISD::BUILD_VECTOR, HiVT, &HiOps[0], HiOps.size());
484 void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo,
486 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS");
487 unsigned NumSubvectors = N->getNumOperands() / 2;
488 if (NumSubvectors == 1) {
489 Lo = N->getOperand(0);
490 Hi = N->getOperand(1);
495 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
497 SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
498 Lo = DAG.getNode(ISD::CONCAT_VECTORS, LoVT, &LoOps[0], LoOps.size());
500 SmallVector<SDValue, 8> HiOps(N->op_begin()+NumSubvectors, N->op_end());
501 Hi = DAG.getNode(ISD::CONCAT_VECTORS, HiVT, &HiOps[0], HiOps.size());
504 void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
507 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
509 GetSplitVector(N->getOperand(0), VLo, VHi);
510 SDValue DTyOpLo = DAG.getValueType(LoVT);
511 SDValue DTyOpHi = DAG.getValueType(HiVT);
512 SDValue STyOpLo = DAG.getValueType(VLo.getValueType());
513 SDValue STyOpHi = DAG.getValueType(VHi.getValueType());
515 SDValue RndOp = N->getOperand(3);
516 SDValue SatOp = N->getOperand(4);
517 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
519 Lo = DAG.getConvertRndSat(LoVT, VLo, DTyOpLo, STyOpLo, RndOp, SatOp, CvtCode);
520 Hi = DAG.getConvertRndSat(HiVT, VHi, DTyOpHi, STyOpHi, RndOp, SatOp, CvtCode);
523 void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
525 SDValue Vec = N->getOperand(0);
526 SDValue Idx = N->getOperand(1);
527 MVT IdxVT = Idx.getValueType();
530 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
531 // The indices are not guaranteed to be a multiple of the new vector
532 // size unless the original vector type was split in two.
533 assert(LoVT == HiVT && "Non power-of-two vectors not supported!");
535 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, LoVT, Vec, Idx);
536 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
537 DAG.getConstant(LoVT.getVectorNumElements(), IdxVT));
538 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, HiVT, Vec, Idx);
541 void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
543 GetSplitVector(N->getOperand(0), Lo, Hi);
544 Lo = DAG.getNode(ISD::FPOWI, Lo.getValueType(), Lo, N->getOperand(1));
545 Hi = DAG.getNode(ISD::FPOWI, Hi.getValueType(), Hi, N->getOperand(1));
548 void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
550 SDValue Vec = N->getOperand(0);
551 SDValue Elt = N->getOperand(1);
552 SDValue Idx = N->getOperand(2);
553 GetSplitVector(Vec, Lo, Hi);
555 if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
556 unsigned IdxVal = CIdx->getZExtValue();
557 unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
558 if (IdxVal < LoNumElts)
559 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, Lo.getValueType(), Lo, Elt, Idx);
561 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, Hi.getValueType(), Hi, Elt,
562 DAG.getIntPtrConstant(IdxVal - LoNumElts));
566 // Spill the vector to the stack.
567 MVT VecVT = Vec.getValueType();
568 MVT EltVT = VecVT.getVectorElementType();
569 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
570 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
572 // Store the new element. This may be larger than the vector element type,
573 // so use a truncating store.
574 SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
576 TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
577 Store = DAG.getTruncStore(Store, Elt, EltPtr, NULL, 0, EltVT);
579 // Load the Lo part from the stack slot.
580 Lo = DAG.getLoad(Lo.getValueType(), Store, StackPtr, NULL, 0);
582 // Increment the pointer to the other part.
583 unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
584 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
585 DAG.getIntPtrConstant(IncrementSize));
587 // Load the Hi part from the stack slot.
588 Hi = DAG.getLoad(Hi.getValueType(), Store, StackPtr, NULL, 0, false,
589 MinAlign(Alignment, IncrementSize));
592 void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
595 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
596 Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, LoVT, N->getOperand(0));
597 Hi = DAG.getNode(ISD::UNDEF, HiVT);
600 void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
602 assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
604 GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
606 ISD::LoadExtType ExtType = LD->getExtensionType();
607 SDValue Ch = LD->getChain();
608 SDValue Ptr = LD->getBasePtr();
609 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
610 const Value *SV = LD->getSrcValue();
611 int SVOffset = LD->getSrcValueOffset();
612 MVT MemoryVT = LD->getMemoryVT();
613 unsigned Alignment = LD->getAlignment();
614 bool isVolatile = LD->isVolatile();
616 MVT LoMemVT, HiMemVT;
617 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
619 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, Ch, Ptr, Offset,
620 SV, SVOffset, LoMemVT, isVolatile, Alignment);
622 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
623 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
624 DAG.getIntPtrConstant(IncrementSize));
625 SVOffset += IncrementSize;
626 Alignment = MinAlign(Alignment, IncrementSize);
627 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, Ch, Ptr, Offset,
628 SV, SVOffset, HiMemVT, isVolatile, Alignment);
630 // Build a factor node to remember that this load is independent of the
632 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
635 // Legalized the chain result - switch anything that used the old chain to
637 ReplaceValueWith(SDValue(LD, 1), Ch);
640 void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
642 // Get the dest types - they may not match the input types, e.g. int_to_fp.
644 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
647 MVT InVT = N->getOperand(0).getValueType();
648 switch (getTypeAction(InVT)) {
649 default: assert(0 && "Unexpected type action!");
651 assert(LoVT == HiVT && "Legal non-power-of-two vector type?");
652 MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
653 LoVT.getVectorNumElements());
654 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
655 DAG.getIntPtrConstant(0));
656 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, InNVT, N->getOperand(0),
657 DAG.getIntPtrConstant(InNVT.getVectorNumElements()));
661 GetSplitVector(N->getOperand(0), Lo, Hi);
665 Lo = DAG.getNode(N->getOpcode(), LoVT, Lo);
666 Hi = DAG.getNode(N->getOpcode(), HiVT, Hi);
669 void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(SDNode *N, SDValue &Lo,
671 // The low and high parts of the original input give four input vectors.
673 GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
674 GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
675 MVT NewVT = Inputs[0].getValueType();
676 unsigned NewElts = NewVT.getVectorNumElements();
677 assert(NewVT == Inputs[1].getValueType() &&
678 "Non power-of-two vectors not supported!");
680 // If Lo or Hi uses elements from at most two of the four input vectors, then
681 // express it as a vector shuffle of those two inputs. Otherwise extract the
682 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR.
683 SDValue Mask = N->getOperand(2);
684 MVT IdxVT = Mask.getValueType().getVectorElementType();
685 SmallVector<SDValue, 16> Ops;
686 Ops.reserve(NewElts);
687 for (unsigned High = 0; High < 2; ++High) {
688 SDValue &Output = High ? Hi : Lo;
690 // Build a shuffle mask for the output, discovering on the fly which
691 // input vectors to use as shuffle operands (recorded in InputUsed).
692 // If building a suitable shuffle vector proves too hard, then bail
693 // out with useBuildVector set.
694 unsigned InputUsed[2] = { -1U, -1U }; // Not yet discovered.
695 unsigned FirstMaskIdx = High * NewElts;
696 bool useBuildVector = false;
697 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
698 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
700 // The mask element. This indexes into the input.
701 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
702 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
704 // The input vector this mask element indexes into.
705 unsigned Input = Idx / NewElts;
707 if (Input >= array_lengthof(Inputs)) {
708 // The mask element does not index into any input vector.
709 Ops.push_back(DAG.getNode(ISD::UNDEF, IdxVT));
713 // Turn the index into an offset from the start of the input vector.
714 Idx -= Input * NewElts;
716 // Find or create a shuffle vector operand to hold this input.
718 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
719 if (InputUsed[OpNo] == Input) {
720 // This input vector is already an operand.
722 } else if (InputUsed[OpNo] == -1U) {
723 // Create a new operand for this input vector.
724 InputUsed[OpNo] = Input;
729 if (OpNo >= array_lengthof(InputUsed)) {
730 // More than two input vectors used! Give up on trying to create a
731 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
732 useBuildVector = true;
736 // Add the mask index for the new shuffle vector.
737 Ops.push_back(DAG.getConstant(Idx + OpNo * NewElts, IdxVT));
740 if (useBuildVector) {
741 MVT EltVT = NewVT.getVectorElementType();
744 // Extract the input elements by hand.
745 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) {
746 SDValue Arg = Mask.getOperand(FirstMaskIdx + MaskOffset);
748 // The mask element. This indexes into the input.
749 unsigned Idx = Arg.getOpcode() == ISD::UNDEF ?
750 -1U : cast<ConstantSDNode>(Arg)->getZExtValue();
752 // The input vector this mask element indexes into.
753 unsigned Input = Idx / NewElts;
755 if (Input >= array_lengthof(Inputs)) {
756 // The mask element is "undef" or indexes off the end of the input.
757 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
761 // Turn the index into an offset from the start of the input vector.
762 Idx -= Input * NewElts;
764 // Extract the vector element by hand.
765 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT,
766 Inputs[Input], DAG.getIntPtrConstant(Idx)));
769 // Construct the Lo/Hi output using a BUILD_VECTOR.
770 Output = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &Ops[0], Ops.size());
771 } else if (InputUsed[0] == -1U) {
772 // No input vectors were used! The result is undefined.
773 Output = DAG.getNode(ISD::UNDEF, NewVT);
775 // At least one input vector was used. Create a new shuffle vector.
776 SDValue NewMask = DAG.getNode(ISD::BUILD_VECTOR,
777 MVT::getVectorVT(IdxVT, Ops.size()),
778 &Ops[0], Ops.size());
779 SDValue Op0 = Inputs[InputUsed[0]];
780 // If only one input was used, use an undefined vector for the other.
781 SDValue Op1 = InputUsed[1] == -1U ?
782 DAG.getNode(ISD::UNDEF, NewVT) : Inputs[InputUsed[1]];
783 Output = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, Op0, Op1, NewMask);
790 void DAGTypeLegalizer::SplitVecRes_VSETCC(SDNode *N, SDValue &Lo,
793 GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
795 SDValue LL, LH, RL, RH;
796 GetSplitVector(N->getOperand(0), LL, LH);
797 GetSplitVector(N->getOperand(1), RL, RH);
799 Lo = DAG.getNode(ISD::VSETCC, LoVT, LL, RL, N->getOperand(2));
800 Hi = DAG.getNode(ISD::VSETCC, HiVT, LH, RH, N->getOperand(2));
804 //===----------------------------------------------------------------------===//
805 // Operand Vector Splitting
806 //===----------------------------------------------------------------------===//
808 /// SplitVectorOperand - This method is called when the specified operand of the
809 /// specified node is found to need vector splitting. At this point, all of the
810 /// result types of the node are known to be legal, but other operands of the
811 /// node may need legalization as well as the specified one.
812 bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) {
813 DEBUG(cerr << "Split node operand: "; N->dump(&DAG); cerr << "\n");
814 SDValue Res = SDValue();
816 if (Res.getNode() == 0) {
817 switch (N->getOpcode()) {
820 cerr << "SplitVectorOperand Op #" << OpNo << ": ";
821 N->dump(&DAG); cerr << "\n";
823 assert(0 && "Do not know how to split this operator's operand!");
826 case ISD::BIT_CONVERT: Res = SplitVecOp_BIT_CONVERT(N); break;
827 case ISD::EXTRACT_SUBVECTOR: Res = SplitVecOp_EXTRACT_SUBVECTOR(N); break;
828 case ISD::EXTRACT_VECTOR_ELT:Res = SplitVecOp_EXTRACT_VECTOR_ELT(N); break;
829 case ISD::STORE: Res = SplitVecOp_STORE(cast<StoreSDNode>(N),
831 case ISD::VECTOR_SHUFFLE: Res = SplitVecOp_VECTOR_SHUFFLE(N, OpNo);break;
836 case ISD::FP_TO_SINT:
837 case ISD::FP_TO_UINT:
838 case ISD::SINT_TO_FP:
840 case ISD::UINT_TO_FP: Res = SplitVecOp_UnaryOp(N); break;
844 // If the result is null, the sub-method took care of registering results etc.
845 if (!Res.getNode()) return false;
847 // If the result is N, the sub-method updated N in place. Tell the legalizer
849 if (Res.getNode() == N)
852 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
853 "Invalid operand expansion");
855 ReplaceValueWith(SDValue(N, 0), Res);
859 SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
860 // The result has a legal vector type, but the input needs splitting.
861 MVT ResVT = N->getValueType(0);
863 GetSplitVector(N->getOperand(0), Lo, Hi);
864 assert(Lo.getValueType() == Hi.getValueType() &&
865 "Returns legal non-power-of-two vector type?");
866 MVT InVT = Lo.getValueType();
868 MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
869 InVT.getVectorNumElements());
871 Lo = DAG.getNode(N->getOpcode(), OutVT, Lo);
872 Hi = DAG.getNode(N->getOpcode(), OutVT, Hi);
874 return DAG.getNode(ISD::CONCAT_VECTORS, ResVT, Lo, Hi);
877 SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) {
878 // For example, i64 = BIT_CONVERT v4i16 on alpha. Typically the vector will
879 // end up being split all the way down to individual components. Convert the
880 // split pieces into integers and reassemble.
882 GetSplitVector(N->getOperand(0), Lo, Hi);
883 Lo = BitConvertToInteger(Lo);
884 Hi = BitConvertToInteger(Hi);
886 if (TLI.isBigEndian())
889 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0),
890 JoinIntegers(Lo, Hi));
893 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
894 // We know that the extracted result type is legal. For now, assume the index
896 MVT SubVT = N->getValueType(0);
897 SDValue Idx = N->getOperand(1);
899 GetSplitVector(N->getOperand(0), Lo, Hi);
901 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
902 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
904 if (IdxVal < LoElts) {
905 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
906 "Extracted subvector crosses vector split!");
907 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Lo, Idx);
909 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SubVT, Hi,
910 DAG.getConstant(IdxVal - LoElts, Idx.getValueType()));
914 SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
915 SDValue Vec = N->getOperand(0);
916 SDValue Idx = N->getOperand(1);
917 MVT VecVT = Vec.getValueType();
919 if (isa<ConstantSDNode>(Idx)) {
920 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
921 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
924 GetSplitVector(Vec, Lo, Hi);
926 uint64_t LoElts = Lo.getValueType().getVectorNumElements();
929 return DAG.UpdateNodeOperands(SDValue(N, 0), Lo, Idx);
931 return DAG.UpdateNodeOperands(SDValue(N, 0), Hi,
932 DAG.getConstant(IdxVal - LoElts,
933 Idx.getValueType()));
936 // Store the vector to the stack.
937 MVT EltVT = VecVT.getVectorElementType();
938 SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
939 SDValue Store = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
941 // Load back the required element.
942 StackPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
943 return DAG.getLoad(EltVT, Store, StackPtr, NULL, 0);
946 SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) {
947 assert(N->isUnindexed() && "Indexed store of vector?");
948 assert(OpNo == 1 && "Can only split the stored value");
950 bool isTruncating = N->isTruncatingStore();
951 SDValue Ch = N->getChain();
952 SDValue Ptr = N->getBasePtr();
953 int SVOffset = N->getSrcValueOffset();
954 MVT MemoryVT = N->getMemoryVT();
955 unsigned Alignment = N->getAlignment();
956 bool isVol = N->isVolatile();
958 GetSplitVector(N->getOperand(1), Lo, Hi);
960 MVT LoMemVT, HiMemVT;
961 GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
963 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
966 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
967 LoMemVT, isVol, Alignment);
969 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
972 // Increment the pointer to the other half.
973 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
974 DAG.getIntPtrConstant(IncrementSize));
977 Hi = DAG.getTruncStore(Ch, Hi, Ptr,
978 N->getSrcValue(), SVOffset+IncrementSize,
980 isVol, MinAlign(Alignment, IncrementSize));
982 Hi = DAG.getStore(Ch, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
983 isVol, MinAlign(Alignment, IncrementSize));
985 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
988 SDValue DAGTypeLegalizer::SplitVecOp_VECTOR_SHUFFLE(SDNode *N, unsigned OpNo) {
989 assert(OpNo == 2 && "Shuffle source type differs from result type?");
990 SDValue Mask = N->getOperand(2);
991 unsigned MaskLength = Mask.getValueType().getVectorNumElements();
992 unsigned LargestMaskEntryPlusOne = 2 * MaskLength;
993 unsigned MinimumBitWidth = Log2_32_Ceil(LargestMaskEntryPlusOne);
995 // Look for a legal vector type to place the mask values in.
996 // Note that there may not be *any* legal vector-of-integer
997 // type for which the element type is legal!
998 for (MVT::SimpleValueType EltVT = MVT::FIRST_INTEGER_VALUETYPE;
999 EltVT <= MVT::LAST_INTEGER_VALUETYPE;
1000 // Integer values types are consecutively numbered. Exploit this.
1001 EltVT = MVT::SimpleValueType(EltVT + 1)) {
1003 // Is the element type big enough to hold the values?
1004 if (MVT(EltVT).getSizeInBits() < MinimumBitWidth)
1008 // Is the vector type legal?
1009 MVT VecVT = MVT::getVectorVT(EltVT, MaskLength);
1010 if (!isTypeLegal(VecVT))
1014 // If the element type is not legal, find a larger legal type to use for
1015 // the BUILD_VECTOR operands. This is an ugly hack, but seems to work!
1016 // FIXME: The real solution is to change VECTOR_SHUFFLE into a variadic
1017 // node where the shuffle mask is a list of integer operands, #2 .. #2+n.
1018 for (MVT::SimpleValueType OpVT = EltVT; OpVT <= MVT::LAST_INTEGER_VALUETYPE;
1019 // Integer values types are consecutively numbered. Exploit this.
1020 OpVT = MVT::SimpleValueType(OpVT + 1)) {
1021 if (!isTypeLegal(OpVT))
1024 // Success! Rebuild the vector using the legal types.
1025 SmallVector<SDValue, 16> Ops(MaskLength);
1026 for (unsigned i = 0; i < MaskLength; ++i) {
1027 SDValue Arg = Mask.getOperand(i);
1028 if (Arg.getOpcode() == ISD::UNDEF) {
1029 Ops[i] = DAG.getNode(ISD::UNDEF, OpVT);
1031 uint64_t Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1032 Ops[i] = DAG.getConstant(Idx, OpVT);
1035 return DAG.UpdateNodeOperands(SDValue(N,0),
1036 N->getOperand(0), N->getOperand(1),
1037 DAG.getNode(ISD::BUILD_VECTOR,
1038 VecVT, &Ops[0], Ops.size()));
1041 // Continuing is pointless - failure is certain.
1044 assert(false && "Failed to find an appropriate mask type!");
1045 return SDValue(N, 0);