1 //===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::LegalizeVectors method.
12 // The vector legalizer looks for vector operations which might need to be
13 // scalarized and legalizes them. This is a separate step from Legalize because
14 // scalarizing can introduce illegal types. For example, suppose we have an
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
17 // operation, which introduces nodes with the illegal type i64 which must be
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
19 // the operation must be unrolled, which introduces nodes with the illegal
20 // type i8 which must be promoted.
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
23 // or operations that happen to take a vector which are custom-lowered;
24 // the legalization for such operations never produces nodes
25 // with illegal types, so it's okay to put off legalizing them until
26 // SelectionDAG::Legalize runs.
28 //===----------------------------------------------------------------------===//
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/Target/TargetLowering.h"
35 class VectorLegalizer {
37 const TargetLowering &TLI;
38 bool Changed; // Keep track of whether anything changed
40 /// For nodes that are of legal width, and that have more than one use, this
41 /// map indicates what regularized operand to use. This allows us to avoid
42 /// legalizing the same thing more than once.
43 SmallDenseMap<SDValue, SDValue, 64> LegalizedNodes;
45 /// \brief Adds a node to the translation cache.
46 void AddLegalizedOperand(SDValue From, SDValue To) {
47 LegalizedNodes.insert(std::make_pair(From, To));
48 // If someone requests legalization of the new node, return itself.
50 LegalizedNodes.insert(std::make_pair(To, To));
53 /// \brief Legalizes the given node.
54 SDValue LegalizeOp(SDValue Op);
56 /// \brief Assuming the node is legal, "legalize" the results.
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
59 /// \brief Implements unrolling a VSETCC.
60 SDValue UnrollVSETCC(SDValue Op);
62 /// \brief Implement expand-based legalization of vector operations.
64 /// This is just a high-level routine to dispatch to specific code paths for
65 /// operations to legalize them.
66 SDValue Expand(SDValue Op);
68 /// \brief Implements expansion for FNEG; falls back to UnrollVectorOp if
71 /// Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if
72 /// SINT_TO_FLOAT and SHR on vectors isn't legal.
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
75 /// \brief Implement expansion for SIGN_EXTEND_INREG using SRL and SRA.
76 SDValue ExpandSEXTINREG(SDValue Op);
78 /// \brief Implement expansion for ANY_EXTEND_VECTOR_INREG.
80 /// Shuffles the low lanes of the operand into place and bitcasts to the proper
81 /// type. The contents of the bits in the extended part of each element are
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
85 /// \brief Implement expansion for SIGN_EXTEND_VECTOR_INREG.
87 /// Shuffles the low lanes of the operand into place, bitcasts to the proper
88 /// type, then shifts left and arithmetic shifts right to introduce a sign
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
92 /// \brief Implement expansion for ZERO_EXTEND_VECTOR_INREG.
94 /// Shuffles the low lanes of the operand into place and blends zeros into
95 /// the remaining lanes, finally bitcasting to the proper type.
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
98 /// \brief Expand bswap of vectors into a shuffle if legal.
99 SDValue ExpandBSWAP(SDValue Op);
101 /// \brief Implement vselect in terms of XOR, AND, OR when blend is not
102 /// supported by the target.
103 SDValue ExpandVSELECT(SDValue Op);
104 SDValue ExpandSELECT(SDValue Op);
105 SDValue ExpandLoad(SDValue Op);
106 SDValue ExpandStore(SDValue Op);
107 SDValue ExpandFNEG(SDValue Op);
108 SDValue ExpandABSDIFF(SDValue Op);
110 /// \brief Implements vector promotion.
112 /// This is essentially just bitcasting the operands to a different type and
113 /// bitcasting the result back to the original type.
114 SDValue Promote(SDValue Op);
116 /// \brief Implements [SU]INT_TO_FP vector promotion.
118 /// This is a [zs]ext of the input operand to the next size up.
119 SDValue PromoteINT_TO_FP(SDValue Op);
121 /// \brief Implements FP_TO_[SU]INT vector promotion of the result type.
123 /// It is promoted to the next size up integer type. The result is then
124 /// truncated back to the original type.
125 SDValue PromoteFP_TO_INT(SDValue Op, bool isSigned);
128 /// \brief Begin legalizer the vector operations in the DAG.
130 VectorLegalizer(SelectionDAG& dag) :
131 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {}
134 bool VectorLegalizer::Run() {
135 // Before we start legalizing vector nodes, check if there are any vectors.
136 bool HasVectors = false;
137 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
138 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I) {
139 // Check if the values of the nodes contain vectors. We don't need to check
140 // the operands because we are going to check their values at some point.
141 for (SDNode::value_iterator J = I->value_begin(), E = I->value_end();
143 HasVectors |= J->isVector();
145 // If we found a vector node we can start the legalization.
150 // If this basic block has no vectors then no need to legalize vectors.
154 // The legalize process is inherently a bottom-up recursive process (users
155 // legalize their uses before themselves). Given infinite stack space, we
156 // could just start legalizing on the root and traverse the whole graph. In
157 // practice however, this causes us to run out of stack space on large basic
158 // blocks. To avoid this problem, compute an ordering of the nodes where each
159 // node is only legalized after all of its operands are legalized.
160 DAG.AssignTopologicalOrder();
161 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
162 E = std::prev(DAG.allnodes_end()); I != std::next(E); ++I)
163 LegalizeOp(SDValue(&*I, 0));
165 // Finally, it's possible the root changed. Get the new root.
166 SDValue OldRoot = DAG.getRoot();
167 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
168 DAG.setRoot(LegalizedNodes[OldRoot]);
170 LegalizedNodes.clear();
172 // Remove dead nodes now.
173 DAG.RemoveDeadNodes();
178 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) {
179 // Generic legalization: just pass the operand through.
180 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i)
181 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
182 return Result.getValue(Op.getResNo());
185 SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
186 // Note that LegalizeOp may be reentered even from single-use nodes, which
187 // means that we always must cache transformed nodes.
188 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
189 if (I != LegalizedNodes.end()) return I->second;
191 SDNode* Node = Op.getNode();
193 // Legalize the operands
194 SmallVector<SDValue, 8> Ops;
195 for (const SDValue &Op : Node->op_values())
196 Ops.push_back(LegalizeOp(Op));
198 SDValue Result = SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops), 0);
200 bool HasVectorValue = false;
201 if (Op.getOpcode() == ISD::LOAD) {
202 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
203 ISD::LoadExtType ExtType = LD->getExtensionType();
204 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
205 switch (TLI.getLoadExtAction(LD->getExtensionType(), LD->getValueType(0),
206 LD->getMemoryVT())) {
207 default: llvm_unreachable("This action is not supported yet!");
208 case TargetLowering::Legal:
209 return TranslateLegalizeResults(Op, Result);
210 case TargetLowering::Custom:
211 if (SDValue Lowered = TLI.LowerOperation(Result, DAG)) {
212 if (Lowered == Result)
213 return TranslateLegalizeResults(Op, Lowered);
215 if (Lowered->getNumValues() != Op->getNumValues()) {
216 // This expanded to something other than the load. Assume the
217 // lowering code took care of any chain values, and just handle the
219 assert(Result.getValue(1).use_empty() &&
220 "There are still live users of the old chain!");
221 return LegalizeOp(Lowered);
223 return TranslateLegalizeResults(Op, Lowered);
226 case TargetLowering::Expand:
228 return LegalizeOp(ExpandLoad(Op));
230 } else if (Op.getOpcode() == ISD::STORE) {
231 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
232 EVT StVT = ST->getMemoryVT();
233 MVT ValVT = ST->getValue().getSimpleValueType();
234 if (StVT.isVector() && ST->isTruncatingStore())
235 switch (TLI.getTruncStoreAction(ValVT, StVT.getSimpleVT())) {
236 default: llvm_unreachable("This action is not supported yet!");
237 case TargetLowering::Legal:
238 return TranslateLegalizeResults(Op, Result);
239 case TargetLowering::Custom: {
240 SDValue Lowered = TLI.LowerOperation(Result, DAG);
241 Changed = Lowered != Result;
242 return TranslateLegalizeResults(Op, Lowered);
244 case TargetLowering::Expand:
246 return LegalizeOp(ExpandStore(Op));
248 } else if (Op.getOpcode() == ISD::MSCATTER)
249 HasVectorValue = true;
251 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
254 HasVectorValue |= J->isVector();
256 return TranslateLegalizeResults(Op, Result);
259 switch (Op.getOpcode()) {
261 return TranslateLegalizeResults(Op, Result);
287 case ISD::CTLZ_ZERO_UNDEF:
288 case ISD::CTTZ_ZERO_UNDEF:
294 case ISD::ZERO_EXTEND:
295 case ISD::ANY_EXTEND:
297 case ISD::SIGN_EXTEND:
298 case ISD::FP_TO_SINT:
299 case ISD::FP_TO_UINT:
320 case ISD::FNEARBYINT:
326 case ISD::SIGN_EXTEND_INREG:
327 case ISD::ANY_EXTEND_VECTOR_INREG:
328 case ISD::SIGN_EXTEND_VECTOR_INREG:
329 case ISD::ZERO_EXTEND_VECTOR_INREG:
336 QueryType = Node->getValueType(0);
338 case ISD::FP_ROUND_INREG:
339 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT();
341 case ISD::SINT_TO_FP:
342 case ISD::UINT_TO_FP:
343 QueryType = Node->getOperand(0).getValueType();
346 QueryType = cast<MaskedScatterSDNode>(Node)->getValue().getValueType();
350 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
351 default: llvm_unreachable("This action is not supported yet!");
352 case TargetLowering::Promote:
353 Result = Promote(Op);
356 case TargetLowering::Legal:
358 case TargetLowering::Custom: {
359 SDValue Tmp1 = TLI.LowerOperation(Op, DAG);
360 if (Tmp1.getNode()) {
366 case TargetLowering::Expand:
370 // Make sure that the generated code is itself legal.
372 Result = LegalizeOp(Result);
376 // Note that LegalizeOp may be reentered even from single-use nodes, which
377 // means that we always must cache transformed nodes.
378 AddLegalizedOperand(Op, Result);
382 SDValue VectorLegalizer::Promote(SDValue Op) {
383 // For a few operations there is a specific concept for promotion based on
384 // the operand's type.
385 switch (Op.getOpcode()) {
386 case ISD::SINT_TO_FP:
387 case ISD::UINT_TO_FP:
388 // "Promote" the operation by extending the operand.
389 return PromoteINT_TO_FP(Op);
390 case ISD::FP_TO_UINT:
391 case ISD::FP_TO_SINT:
392 // Promote the operation by extending the operand.
393 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
396 // There are currently two cases of vector promotion:
397 // 1) Bitcasting a vector of integers to a different type to a vector of the
398 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
399 // 2) Extending a vector of floats to a vector of the same number of larger
400 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
401 MVT VT = Op.getSimpleValueType();
402 assert(Op.getNode()->getNumValues() == 1 &&
403 "Can't promote a vector with multiple results!");
404 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
406 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
408 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
409 if (Op.getOperand(j).getValueType().isVector())
412 .getVectorElementType()
413 .isFloatingPoint() &&
414 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint())
415 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
417 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
419 Operands[j] = Op.getOperand(j);
422 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
423 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) ||
424 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() &&
425 NVT.isVector() && NVT.getVectorElementType().isFloatingPoint()))
426 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
428 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
431 SDValue VectorLegalizer::PromoteINT_TO_FP(SDValue Op) {
432 // INT_TO_FP operations may require the input operand be promoted even
433 // when the type is otherwise legal.
434 EVT VT = Op.getOperand(0).getValueType();
435 assert(Op.getNode()->getNumValues() == 1 &&
436 "Can't promote a vector with multiple results!");
438 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
439 // by widening the vector w/ the same element width and twice the number
440 // of elements. We want the other way around, the same number of elements,
441 // each twice the width.
443 // Increase the bitwidth of the element to the next pow-of-two
444 // (which is greater than 8 bits).
446 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext());
447 assert(NVT.isSimple() && "Promoting to a non-simple vector type!");
449 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
451 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
453 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
454 if (Op.getOperand(j).getValueType().isVector())
455 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j));
457 Operands[j] = Op.getOperand(j);
460 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), Operands);
463 // For FP_TO_INT we promote the result type to a vector type with wider
464 // elements and then truncate the result. This is different from the default
465 // PromoteVector which uses bitcast to promote thus assumning that the
466 // promoted vector type has the same overall size.
467 SDValue VectorLegalizer::PromoteFP_TO_INT(SDValue Op, bool isSigned) {
468 assert(Op.getNode()->getNumValues() == 1 &&
469 "Can't promote a vector with multiple results!");
470 EVT VT = Op.getValueType();
475 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext());
476 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!");
477 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
478 NewOpc = ISD::FP_TO_SINT;
481 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
482 NewOpc = ISD::FP_TO_UINT;
488 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0));
489 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
493 SDValue VectorLegalizer::ExpandLoad(SDValue Op) {
495 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
496 SDValue Chain = LD->getChain();
497 SDValue BasePTR = LD->getBasePtr();
498 EVT SrcVT = LD->getMemoryVT();
499 ISD::LoadExtType ExtType = LD->getExtensionType();
501 SmallVector<SDValue, 8> Vals;
502 SmallVector<SDValue, 8> LoadChains;
503 unsigned NumElem = SrcVT.getVectorNumElements();
505 EVT SrcEltVT = SrcVT.getScalarType();
506 EVT DstEltVT = Op.getNode()->getValueType(0).getScalarType();
508 if (SrcVT.getVectorNumElements() > 1 && !SrcEltVT.isByteSized()) {
509 // When elements in a vector is not byte-addressable, we cannot directly
510 // load each element by advancing pointer, which could only address bytes.
511 // Instead, we load all significant words, mask bits off, and concatenate
512 // them to form each element. Finally, they are extended to destination
513 // scalar type to build the destination vector.
514 EVT WideVT = TLI.getPointerTy(DAG.getDataLayout());
516 assert(WideVT.isRound() &&
517 "Could not handle the sophisticated case when the widest integer is"
519 assert(WideVT.bitsGE(SrcEltVT) &&
520 "Type is not legalized?");
522 unsigned WideBytes = WideVT.getStoreSize();
524 unsigned RemainingBytes = SrcVT.getStoreSize();
525 SmallVector<SDValue, 8> LoadVals;
527 while (RemainingBytes > 0) {
529 unsigned LoadBytes = WideBytes;
531 if (RemainingBytes >= LoadBytes) {
532 ScalarLoad = DAG.getLoad(WideVT, dl, Chain, BasePTR,
533 LD->getPointerInfo().getWithOffset(Offset),
534 LD->isVolatile(), LD->isNonTemporal(),
536 MinAlign(LD->getAlignment(), Offset),
540 while (RemainingBytes < LoadBytes) {
541 LoadBytes >>= 1; // Reduce the load size by half.
542 LoadVT = EVT::getIntegerVT(*DAG.getContext(), LoadBytes << 3);
544 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
545 LD->getPointerInfo().getWithOffset(Offset),
546 LoadVT, LD->isVolatile(),
547 LD->isNonTemporal(), LD->isInvariant(),
548 MinAlign(LD->getAlignment(), Offset),
552 RemainingBytes -= LoadBytes;
554 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
555 DAG.getConstant(LoadBytes, dl,
556 BasePTR.getValueType()));
558 LoadVals.push_back(ScalarLoad.getValue(0));
559 LoadChains.push_back(ScalarLoad.getValue(1));
562 // Extract bits, pack and extend/trunc them into destination type.
563 unsigned SrcEltBits = SrcEltVT.getSizeInBits();
564 SDValue SrcEltBitMask = DAG.getConstant((1U << SrcEltBits) - 1, dl, WideVT);
566 unsigned BitOffset = 0;
567 unsigned WideIdx = 0;
568 unsigned WideBits = WideVT.getSizeInBits();
570 for (unsigned Idx = 0; Idx != NumElem; ++Idx) {
571 SDValue Lo, Hi, ShAmt;
573 if (BitOffset < WideBits) {
574 ShAmt = DAG.getConstant(
575 BitOffset, dl, TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
576 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
577 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
580 BitOffset += SrcEltBits;
581 if (BitOffset >= WideBits) {
583 BitOffset -= WideBits;
585 ShAmt = DAG.getConstant(
586 SrcEltBits - BitOffset, dl,
587 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
588 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
589 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
594 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
597 default: llvm_unreachable("Unknown extended-load op!");
599 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT);
602 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT);
606 DAG.getConstant(WideBits - SrcEltBits, dl,
607 TLI.getShiftAmountTy(WideVT, DAG.getDataLayout()));
608 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
609 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
610 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT);
616 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
618 for (unsigned Idx=0; Idx<NumElem; Idx++) {
619 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
620 Op.getNode()->getValueType(0).getScalarType(),
621 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride),
622 SrcVT.getScalarType(),
623 LD->isVolatile(), LD->isNonTemporal(), LD->isInvariant(),
624 MinAlign(LD->getAlignment(), Idx * Stride), LD->getAAInfo());
626 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
627 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
629 Vals.push_back(ScalarLoad.getValue(0));
630 LoadChains.push_back(ScalarLoad.getValue(1));
634 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
635 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
636 Op.getNode()->getValueType(0), Vals);
638 AddLegalizedOperand(Op.getValue(0), Value);
639 AddLegalizedOperand(Op.getValue(1), NewChain);
641 return (Op.getResNo() ? NewChain : Value);
644 SDValue VectorLegalizer::ExpandStore(SDValue Op) {
646 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode());
647 SDValue Chain = ST->getChain();
648 SDValue BasePTR = ST->getBasePtr();
649 SDValue Value = ST->getValue();
650 EVT StVT = ST->getMemoryVT();
652 unsigned Alignment = ST->getAlignment();
653 bool isVolatile = ST->isVolatile();
654 bool isNonTemporal = ST->isNonTemporal();
655 AAMDNodes AAInfo = ST->getAAInfo();
657 unsigned NumElem = StVT.getVectorNumElements();
658 // The type of the data we want to save
659 EVT RegVT = Value.getValueType();
660 EVT RegSclVT = RegVT.getScalarType();
661 // The type of data as saved in memory.
662 EVT MemSclVT = StVT.getScalarType();
664 // Cast floats into integers
665 unsigned ScalarSize = MemSclVT.getSizeInBits();
667 // Round odd types to the next pow of two.
668 if (!isPowerOf2_32(ScalarSize))
669 ScalarSize = NextPowerOf2(ScalarSize);
671 // Store Stride in bytes
672 unsigned Stride = ScalarSize/8;
673 // Extract each of the elements from the original vector
674 // and save them into memory individually.
675 SmallVector<SDValue, 8> Stores;
676 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
677 SDValue Ex = DAG.getNode(
678 ISD::EXTRACT_VECTOR_ELT, dl, RegSclVT, Value,
679 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
681 // This scalar TruncStore may be illegal, but we legalize it later.
682 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR,
683 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT,
684 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
687 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
688 DAG.getConstant(Stride, dl, BasePTR.getValueType()));
690 Stores.push_back(Store);
692 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
693 AddLegalizedOperand(Op, TF);
697 SDValue VectorLegalizer::Expand(SDValue Op) {
698 switch (Op->getOpcode()) {
699 case ISD::SIGN_EXTEND_INREG:
700 return ExpandSEXTINREG(Op);
701 case ISD::ANY_EXTEND_VECTOR_INREG:
702 return ExpandANY_EXTEND_VECTOR_INREG(Op);
703 case ISD::SIGN_EXTEND_VECTOR_INREG:
704 return ExpandSIGN_EXTEND_VECTOR_INREG(Op);
705 case ISD::ZERO_EXTEND_VECTOR_INREG:
706 return ExpandZERO_EXTEND_VECTOR_INREG(Op);
708 return ExpandBSWAP(Op);
710 return ExpandVSELECT(Op);
712 return ExpandSELECT(Op);
713 case ISD::UINT_TO_FP:
714 return ExpandUINT_TO_FLOAT(Op);
716 return ExpandFNEG(Op);
718 return UnrollVSETCC(Op);
721 return ExpandABSDIFF(Op);
723 return DAG.UnrollVectorOp(Op.getNode());
727 SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {
729 SDValue Op0 = Op.getOperand(0);
730 SDValue Op1 = Op.getOperand(1);
731 EVT VT = Op.getValueType();
733 // For unsigned intrinsic, promote the type to handle unsigned overflow.
734 bool isUabsdiff = (Op->getOpcode() == ISD::UABSDIFF);
736 VT = VT.widenIntegerVectorElementType(*DAG.getContext());
737 Op0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op0);
738 Op1 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op1);
742 Flags.setNoSignedWrap(!isUabsdiff);
743 SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, Op0, Op1, &Flags);
745 return DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Sub);
748 DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(DAG.getDataLayout(),
749 *DAG.getContext(), VT),
750 Sub, DAG.getConstant(0, dl, VT), DAG.getCondCode(ISD::SETGE));
751 SDValue Neg = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Sub, &Flags);
752 return DAG.getNode(ISD::VSELECT, dl, VT, Cmp, Sub, Neg);
755 SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {
756 // Lower a select instruction where the condition is a scalar and the
757 // operands are vectors. Lower this select to VSELECT and implement it
758 // using XOR AND OR. The selector bit is broadcasted.
759 EVT VT = Op.getValueType();
762 SDValue Mask = Op.getOperand(0);
763 SDValue Op1 = Op.getOperand(1);
764 SDValue Op2 = Op.getOperand(2);
766 assert(VT.isVector() && !Mask.getValueType().isVector()
767 && Op1.getValueType() == Op2.getValueType() && "Invalid type");
769 unsigned NumElem = VT.getVectorNumElements();
771 // If we can't even use the basic vector operations of
772 // AND,OR,XOR, we will have to scalarize the op.
773 // Notice that the operation may be 'promoted' which means that it is
774 // 'bitcasted' to another type which is handled.
775 // Also, we need to be able to construct a splat vector using BUILD_VECTOR.
776 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
777 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
778 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
779 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
780 return DAG.UnrollVectorOp(Op.getNode());
782 // Generate a mask operand.
783 EVT MaskTy = VT.changeVectorElementTypeToInteger();
785 // What is the size of each element in the vector mask.
786 EVT BitTy = MaskTy.getScalarType();
788 Mask = DAG.getSelect(DL, BitTy, Mask,
789 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL,
791 DAG.getConstant(0, DL, BitTy));
793 // Broadcast the mask so that the entire vector is all-one or all zero.
794 SmallVector<SDValue, 8> Ops(NumElem, Mask);
795 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
797 // Bitcast the operands to be the same type as the mask.
798 // This is needed when we select between FP types because
799 // the mask is a vector of integers.
800 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
801 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
803 SDValue AllOnes = DAG.getConstant(
804 APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy);
805 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
807 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
808 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
809 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
810 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
813 SDValue VectorLegalizer::ExpandSEXTINREG(SDValue Op) {
814 EVT VT = Op.getValueType();
816 // Make sure that the SRA and SHL instructions are available.
817 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
818 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
819 return DAG.UnrollVectorOp(Op.getNode());
822 EVT OrigTy = cast<VTSDNode>(Op->getOperand(1))->getVT();
824 unsigned BW = VT.getScalarType().getSizeInBits();
825 unsigned OrigBW = OrigTy.getScalarType().getSizeInBits();
826 SDValue ShiftSz = DAG.getConstant(BW - OrigBW, DL, VT);
828 Op = Op.getOperand(0);
829 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
830 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
833 // Generically expand a vector anyext in register to a shuffle of the relevant
834 // lanes into the appropriate locations, with other lanes left undef.
835 SDValue VectorLegalizer::ExpandANY_EXTEND_VECTOR_INREG(SDValue Op) {
837 EVT VT = Op.getValueType();
838 int NumElements = VT.getVectorNumElements();
839 SDValue Src = Op.getOperand(0);
840 EVT SrcVT = Src.getValueType();
841 int NumSrcElements = SrcVT.getVectorNumElements();
843 // Build a base mask of undef shuffles.
844 SmallVector<int, 16> ShuffleMask;
845 ShuffleMask.resize(NumSrcElements, -1);
847 // Place the extended lanes into the correct locations.
848 int ExtLaneScale = NumSrcElements / NumElements;
849 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
850 for (int i = 0; i < NumElements; ++i)
851 ShuffleMask[i * ExtLaneScale + EndianOffset] = i;
854 ISD::BITCAST, DL, VT,
855 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
858 SDValue VectorLegalizer::ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op) {
860 EVT VT = Op.getValueType();
861 SDValue Src = Op.getOperand(0);
862 EVT SrcVT = Src.getValueType();
864 // First build an any-extend node which can be legalized above when we
865 // recurse through it.
866 Op = DAG.getAnyExtendVectorInReg(Src, DL, VT);
868 // Now we need sign extend. Do this by shifting the elements. Even if these
869 // aren't legal operations, they have a better chance of being legalized
870 // without full scalarization than the sign extension does.
871 unsigned EltWidth = VT.getVectorElementType().getSizeInBits();
872 unsigned SrcEltWidth = SrcVT.getVectorElementType().getSizeInBits();
873 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
874 return DAG.getNode(ISD::SRA, DL, VT,
875 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
879 // Generically expand a vector zext in register to a shuffle of the relevant
880 // lanes into the appropriate locations, a blend of zero into the high bits,
881 // and a bitcast to the wider element type.
882 SDValue VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op) {
884 EVT VT = Op.getValueType();
885 int NumElements = VT.getVectorNumElements();
886 SDValue Src = Op.getOperand(0);
887 EVT SrcVT = Src.getValueType();
888 int NumSrcElements = SrcVT.getVectorNumElements();
890 // Build up a zero vector to blend into this one.
891 EVT SrcScalarVT = SrcVT.getScalarType();
892 SDValue ScalarZero = DAG.getTargetConstant(0, DL, SrcScalarVT);
893 SmallVector<SDValue, 4> BuildVectorOperands(NumSrcElements, ScalarZero);
894 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands);
896 // Shuffle the incoming lanes into the correct position, and pull all other
897 // lanes from the zero vector.
898 SmallVector<int, 16> ShuffleMask;
899 ShuffleMask.reserve(NumSrcElements);
900 for (int i = 0; i < NumSrcElements; ++i)
901 ShuffleMask.push_back(i);
903 int ExtLaneScale = NumSrcElements / NumElements;
904 int EndianOffset = DAG.getDataLayout().isBigEndian() ? ExtLaneScale - 1 : 0;
905 for (int i = 0; i < NumElements; ++i)
906 ShuffleMask[i * ExtLaneScale + EndianOffset] = NumSrcElements + i;
908 return DAG.getNode(ISD::BITCAST, DL, VT,
909 DAG.getVectorShuffle(SrcVT, DL, Zero, Src, ShuffleMask));
912 SDValue VectorLegalizer::ExpandBSWAP(SDValue Op) {
913 EVT VT = Op.getValueType();
915 // Generate a byte wise shuffle mask for the BSWAP.
916 SmallVector<int, 16> ShuffleMask;
917 int ScalarSizeInBytes = VT.getScalarSizeInBits() / 8;
918 for (int I = 0, E = VT.getVectorNumElements(); I != E; ++I)
919 for (int J = ScalarSizeInBytes - 1; J >= 0; --J)
920 ShuffleMask.push_back((I * ScalarSizeInBytes) + J);
922 EVT ByteVT = EVT::getVectorVT(*DAG.getContext(), MVT::i8, ShuffleMask.size());
924 // Only emit a shuffle if the mask is legal.
925 if (!TLI.isShuffleMaskLegal(ShuffleMask, ByteVT))
926 return DAG.UnrollVectorOp(Op.getNode());
929 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
930 Op = DAG.getVectorShuffle(ByteVT, DL, Op, DAG.getUNDEF(ByteVT),
932 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
935 SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) {
936 // Implement VSELECT in terms of XOR, AND, OR
937 // on platforms which do not support blend natively.
940 SDValue Mask = Op.getOperand(0);
941 SDValue Op1 = Op.getOperand(1);
942 SDValue Op2 = Op.getOperand(2);
944 EVT VT = Mask.getValueType();
946 // If we can't even use the basic vector operations of
947 // AND,OR,XOR, we will have to scalarize the op.
948 // Notice that the operation may be 'promoted' which means that it is
949 // 'bitcasted' to another type which is handled.
950 // This operation also isn't safe with AND, OR, XOR when the boolean
951 // type is 0/1 as we need an all ones vector constant to mask with.
952 // FIXME: Sign extend 1 to all ones if thats legal on the target.
953 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
954 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
955 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
956 TLI.getBooleanContents(Op1.getValueType()) !=
957 TargetLowering::ZeroOrNegativeOneBooleanContent)
958 return DAG.UnrollVectorOp(Op.getNode());
960 // If the mask and the type are different sizes, unroll the vector op. This
961 // can occur when getSetCCResultType returns something that is different in
962 // size from the operand types. For example, v4i8 = select v4i32, v4i8, v4i8.
963 if (VT.getSizeInBits() != Op1.getValueType().getSizeInBits())
964 return DAG.UnrollVectorOp(Op.getNode());
966 // Bitcast the operands to be the same type as the mask.
967 // This is needed when we select between FP types because
968 // the mask is a vector of integers.
969 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
970 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
972 SDValue AllOnes = DAG.getConstant(
973 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), DL, VT);
974 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
976 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
977 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
978 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
979 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
982 SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) {
983 EVT VT = Op.getOperand(0).getValueType();
986 // Make sure that the SINT_TO_FP and SRL instructions are available.
987 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
988 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
989 return DAG.UnrollVectorOp(Op.getNode());
991 EVT SVT = VT.getScalarType();
992 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) &&
993 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide");
995 unsigned BW = SVT.getSizeInBits();
996 SDValue HalfWord = DAG.getConstant(BW/2, DL, VT);
998 // Constants to clear the upper part of the word.
999 // Notice that we can also use SHL+SHR, but using a constant is slightly
1001 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF;
1002 SDValue HalfWordMask = DAG.getConstant(HWMask, DL, VT);
1004 // Two to the power of half-word-size.
1005 SDValue TWOHW = DAG.getConstantFP(1 << (BW/2), DL, Op.getValueType());
1007 // Clear upper part of LO, lower HI
1008 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1009 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1011 // Convert hi and lo to floats
1012 // Convert the hi part back to the upper values
1013 // TODO: Can any fast-math-flags be set on these nodes?
1014 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1015 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1016 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1018 // Add the two halves
1019 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1023 SDValue VectorLegalizer::ExpandFNEG(SDValue Op) {
1024 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1026 SDValue Zero = DAG.getConstantFP(-0.0, DL, Op.getValueType());
1027 // TODO: If FNEG had fast-math-flags, they'd get propagated to this FSUB.
1028 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1029 Zero, Op.getOperand(0));
1031 return DAG.UnrollVectorOp(Op.getNode());
1034 SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
1035 EVT VT = Op.getValueType();
1036 unsigned NumElems = VT.getVectorNumElements();
1037 EVT EltVT = VT.getVectorElementType();
1038 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
1039 EVT TmpEltVT = LHS.getValueType().getVectorElementType();
1041 SmallVector<SDValue, 8> Ops(NumElems);
1042 for (unsigned i = 0; i < NumElems; ++i) {
1043 SDValue LHSElem = DAG.getNode(
1044 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1045 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1046 SDValue RHSElem = DAG.getNode(
1047 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1048 DAG.getConstant(i, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
1049 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1050 TLI.getSetCCResultType(DAG.getDataLayout(),
1051 *DAG.getContext(), TmpEltVT),
1052 LHSElem, RHSElem, CC);
1053 Ops[i] = DAG.getSelect(dl, EltVT, Ops[i],
1054 DAG.getConstant(APInt::getAllOnesValue
1055 (EltVT.getSizeInBits()), dl, EltVT),
1056 DAG.getConstant(0, dl, EltVT));
1058 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
1063 bool SelectionDAG::LegalizeVectors() {
1064 return VectorLegalizer(*this).Run();