1 //===-- LegalizeTypesPromote.cpp - Promotion for LegalizeTypes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements promotion support for LegalizeTypes. Promotion is the
11 // act of changing a computation in an invalid type to be a computation in a
12 // larger type. For example, implementing i8 arithmetic in an i32 register (as
13 // is often needed on powerpc for example).
15 //===----------------------------------------------------------------------===//
17 #include "LegalizeTypes.h"
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 /// PromoteResult - This method is called when a result of a node is found to be
25 /// in need of promotion to a larger type. At this point, the node may also
26 /// have invalid operands or may have other results that need expansion, we just
27 /// know that (at least) one result needs promotion.
28 void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
29 DEBUG(cerr << "Promote node result: "; N->dump(&DAG); cerr << "\n");
30 SDOperand Result = SDOperand();
32 switch (N->getOpcode()) {
35 cerr << "PromoteResult #" << ResNo << ": ";
36 N->dump(&DAG); cerr << "\n";
38 assert(0 && "Do not know how to promote this operator!");
40 case ISD::UNDEF: Result = PromoteResult_UNDEF(N); break;
41 case ISD::Constant: Result = PromoteResult_Constant(N); break;
43 case ISD::TRUNCATE: Result = PromoteResult_TRUNCATE(N); break;
44 case ISD::SIGN_EXTEND:
45 case ISD::ZERO_EXTEND:
46 case ISD::ANY_EXTEND: Result = PromoteResult_INT_EXTEND(N); break;
47 case ISD::FP_ROUND: Result = PromoteResult_FP_ROUND(N); break;
49 case ISD::FP_TO_UINT: Result = PromoteResult_FP_TO_XINT(N); break;
50 case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
51 case ISD::LOAD: Result = PromoteResult_LOAD(cast<LoadSDNode>(N)); break;
52 case ISD::BUILD_PAIR: Result = PromoteResult_BUILD_PAIR(N); break;
53 case ISD::BIT_CONVERT: Result = PromoteResult_BIT_CONVERT(N); break;
60 case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
63 case ISD::SREM: Result = PromoteResult_SDIV(N); break;
66 case ISD::UREM: Result = PromoteResult_UDIV(N); break;
68 case ISD::SHL: Result = PromoteResult_SHL(N); break;
69 case ISD::SRA: Result = PromoteResult_SRA(N); break;
70 case ISD::SRL: Result = PromoteResult_SRL(N); break;
72 case ISD::SELECT: Result = PromoteResult_SELECT(N); break;
73 case ISD::SELECT_CC: Result = PromoteResult_SELECT_CC(N); break;
75 case ISD::CTLZ: Result = PromoteResult_CTLZ(N); break;
76 case ISD::CTPOP: Result = PromoteResult_CTPOP(N); break;
77 case ISD::CTTZ: Result = PromoteResult_CTTZ(N); break;
79 case ISD::EXTRACT_VECTOR_ELT:
80 Result = PromoteResult_EXTRACT_VECTOR_ELT(N);
84 // If Result is null, the sub-method took care of registering the result.
86 SetPromotedOp(SDOperand(N, ResNo), Result);
89 SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) {
90 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
93 SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
94 MVT::ValueType VT = N->getValueType(0);
95 // Zero extend things like i1, sign extend everything else. It shouldn't
96 // matter in theory which one we pick, but this tends to give better code?
97 unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
98 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
100 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
104 SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
107 switch (getTypeAction(N->getOperand(0).getValueType())) {
108 default: assert(0 && "Unknown type action!");
111 Res = N->getOperand(0);
114 Res = GetPromotedOp(N->getOperand(0));
118 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
119 assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) &&
120 "Truncation doesn't make sense!");
121 if (Res.getValueType() == NVT)
124 // Truncate to NVT instead of VT
125 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
128 SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
129 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
131 if (getTypeAction(N->getOperand(0).getValueType()) == Promote) {
132 SDOperand Res = GetPromotedOp(N->getOperand(0));
133 assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) &&
134 "Extension doesn't make sense!");
136 // If the result and operand types are the same after promotion, simplify
137 // to an in-register extension.
138 if (NVT == Res.getValueType()) {
139 // The high bits are not guaranteed to be anything. Insert an extend.
140 if (N->getOpcode() == ISD::SIGN_EXTEND)
141 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
142 DAG.getValueType(N->getOperand(0).getValueType()));
143 if (N->getOpcode() == ISD::ZERO_EXTEND)
144 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
145 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
150 // Otherwise, just extend the original operand all the way to the larger type.
151 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
154 SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
155 // NOTE: Assumes input is legal.
156 if (N->getConstantOperandVal(1) == 0)
157 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
158 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
159 // If the precision discard isn't needed, just return the operand unrounded.
160 return N->getOperand(0);
163 SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
164 SDOperand Op = N->getOperand(0);
165 // If the operand needed to be promoted, do so now.
166 if (getTypeAction(Op.getValueType()) == Promote)
167 // The input result is prerounded, so we don't have to do anything special.
168 Op = GetPromotedOp(Op);
170 unsigned NewOpc = N->getOpcode();
171 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
173 // If we're promoting a UINT to a larger size, check to see if the new node
174 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
175 // we can use that instead. This allows us to generate better code for
176 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
177 // legal, such as PowerPC.
178 if (N->getOpcode() == ISD::FP_TO_UINT) {
179 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
180 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
181 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
182 NewOpc = ISD::FP_TO_SINT;
185 return DAG.getNode(NewOpc, NVT, Op);
188 SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
189 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
190 && "SetCC type is not legal??");
191 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
192 N->getOperand(0), N->getOperand(1), N->getOperand(2));
195 SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
196 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
197 ISD::LoadExtType ExtType =
198 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
199 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
200 N->getSrcValue(), N->getSrcValueOffset(),
201 N->getMemoryVT(), N->isVolatile(),
204 // Legalized the chain result - switch anything that used the old chain to
206 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
210 SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) {
211 // The pair element type may be legal, or may not promote to the same type as
212 // the result, for example i16 = BUILD_PAIR (i8, i8) when i8 is legal but i16
213 // is not. Handle all cases.
214 MVT::ValueType LVT = N->getOperand(0).getValueType();
215 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
216 SDOperand Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
217 SDOperand Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, N->getOperand(1));
218 Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(MVT::getSizeInBits(LVT),
219 TLI.getShiftAmountTy()));
220 return DAG.getNode(ISD::OR, NVT, Lo, Hi);
223 SDOperand DAGTypeLegalizer::PromoteResult_BIT_CONVERT(SDNode *N) {
224 SDOperand InOp = N->getOperand(0);
225 MVT::ValueType InVT = InOp.getValueType();
226 MVT::ValueType NInVT = TLI.getTypeToTransformTo(InVT);
227 MVT::ValueType OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
229 switch (getTypeAction(InVT)) {
231 assert(false && "Unknown type action!");
236 if (MVT::getSizeInBits(OutVT) == MVT::getSizeInBits(NInVT))
237 // The input promotes to the same size. Convert the promoted value.
238 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedOp(InOp));
243 // Convert the element to an integer and promote it by hand.
244 InOp = DAG.getNode(ISD::BIT_CONVERT,
245 MVT::getIntegerType(MVT::getSizeInBits(InVT)),
246 GetScalarizedOp(InOp));
247 InOp = DAG.getNode(ISD::ANY_EXTEND,
248 MVT::getIntegerType(MVT::getSizeInBits(OutVT)), InOp);
249 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
251 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
252 // pieces of the input into integers and reassemble in the final type.
254 GetSplitOp(N->getOperand(0), Lo, Hi);
256 unsigned LoBits = MVT::getSizeInBits(Lo.getValueType());
257 Lo = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(LoBits), Lo);
259 unsigned HiBits = MVT::getSizeInBits(Hi.getValueType());
260 Hi = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(HiBits), Hi);
262 if (TLI.isBigEndian())
265 MVT::ValueType TargetTy = MVT::getIntegerType(MVT::getSizeInBits(OutVT));
266 Hi = DAG.getNode(ISD::ANY_EXTEND, TargetTy, Hi);
267 Hi = DAG.getNode(ISD::SHL, TargetTy, Hi,
268 DAG.getConstant(MVT::getSizeInBits(Lo.getValueType()),
269 TLI.getShiftAmountTy()));
270 Lo = DAG.getNode(ISD::ZERO_EXTEND, TargetTy, Lo);
272 return DAG.getNode(ISD::BIT_CONVERT, OutVT,
273 DAG.getNode(ISD::OR, TargetTy, Lo, Hi));
276 // Otherwise, lower the bit-convert to a store/load from the stack, then
278 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
279 return PromoteResult_LOAD(cast<LoadSDNode>(Op.Val));
282 SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
283 // The input may have strange things in the top bits of the registers, but
284 // these operations don't care. They may have weird bits going out, but
285 // that too is okay if they are integer operations.
286 SDOperand LHS = GetPromotedOp(N->getOperand(0));
287 SDOperand RHS = GetPromotedOp(N->getOperand(1));
288 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
291 SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
292 // Sign extend the input.
293 SDOperand LHS = GetPromotedOp(N->getOperand(0));
294 SDOperand RHS = GetPromotedOp(N->getOperand(1));
295 MVT::ValueType VT = N->getValueType(0);
296 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
297 DAG.getValueType(VT));
298 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
299 DAG.getValueType(VT));
301 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
304 SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
305 // Zero extend the input.
306 SDOperand LHS = GetPromotedOp(N->getOperand(0));
307 SDOperand RHS = GetPromotedOp(N->getOperand(1));
308 MVT::ValueType VT = N->getValueType(0);
309 LHS = DAG.getZeroExtendInReg(LHS, VT);
310 RHS = DAG.getZeroExtendInReg(RHS, VT);
312 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
315 SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
316 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
317 GetPromotedOp(N->getOperand(0)), N->getOperand(1));
320 SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
321 // The input value must be properly sign extended.
322 MVT::ValueType VT = N->getValueType(0);
323 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
324 SDOperand Res = GetPromotedOp(N->getOperand(0));
325 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
326 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
329 SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
330 // The input value must be properly zero extended.
331 MVT::ValueType VT = N->getValueType(0);
332 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
333 SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
334 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
337 SDOperand DAGTypeLegalizer::PromoteResult_SELECT(SDNode *N) {
338 SDOperand LHS = GetPromotedOp(N->getOperand(1));
339 SDOperand RHS = GetPromotedOp(N->getOperand(2));
340 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
343 SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
344 SDOperand LHS = GetPromotedOp(N->getOperand(2));
345 SDOperand RHS = GetPromotedOp(N->getOperand(3));
346 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
347 N->getOperand(1), LHS, RHS, N->getOperand(4));
350 SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) {
351 SDOperand Op = GetPromotedOp(N->getOperand(0));
352 MVT::ValueType OVT = N->getValueType(0);
353 MVT::ValueType NVT = Op.getValueType();
354 // Zero extend to the promoted type and do the count there.
355 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
356 // Subtract off the extra leading bits in the bigger type.
357 return DAG.getNode(ISD::SUB, NVT, Op,
358 DAG.getConstant(MVT::getSizeInBits(NVT) -
359 MVT::getSizeInBits(OVT), NVT));
362 SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) {
363 SDOperand Op = GetPromotedOp(N->getOperand(0));
364 MVT::ValueType OVT = N->getValueType(0);
365 MVT::ValueType NVT = Op.getValueType();
366 // Zero extend to the promoted type and do the count there.
367 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
370 SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) {
371 SDOperand Op = GetPromotedOp(N->getOperand(0));
372 MVT::ValueType OVT = N->getValueType(0);
373 MVT::ValueType NVT = Op.getValueType();
374 // The count is the same in the promoted type except if the original
375 // value was zero. This can be handled by setting the bit just off
376 // the top of the original type.
377 Op = DAG.getNode(ISD::OR, NVT, Op,
378 // FIXME: Do this using an APINT constant.
379 DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT));
380 return DAG.getNode(ISD::CTTZ, NVT, Op);
383 SDOperand DAGTypeLegalizer::PromoteResult_EXTRACT_VECTOR_ELT(SDNode *N) {
384 MVT::ValueType OldVT = N->getValueType(0);
385 SDOperand OldVec = N->getOperand(0);
386 unsigned OldElts = MVT::getVectorNumElements(OldVec.getValueType());
389 assert(!isTypeLegal(OldVec.getValueType()) &&
390 "Legal one-element vector of a type needing promotion!");
391 // It is tempting to follow GetScalarizedOp by a call to GetPromotedOp,
392 // but this would be wrong because the scalarized value may not yet have
394 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
395 GetScalarizedOp(OldVec));
398 // Convert to a vector half as long with an element type of twice the width,
399 // for example <4 x i16> -> <2 x i32>.
400 assert(!(OldElts & 1) && "Odd length vectors not supported!");
401 MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
402 assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
404 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
405 MVT::getVectorType(NewVT, OldElts / 2),
408 // Extract the element at OldIdx / 2 from the new vector.
409 SDOperand OldIdx = N->getOperand(1);
410 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
411 DAG.getConstant(1, TLI.getShiftAmountTy()));
412 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
414 // Select the appropriate half of the element: Lo if OldIdx was even,
417 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
418 DAG.getConstant(MVT::getSizeInBits(OldVT),
419 TLI.getShiftAmountTy()));
420 if (TLI.isBigEndian())
423 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
424 DAG.getConstant(1, TLI.getShiftAmountTy()));
425 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
428 //===----------------------------------------------------------------------===//
430 //===----------------------------------------------------------------------===//
432 /// PromoteOperand - This method is called when the specified operand of the
433 /// specified node is found to need promotion. At this point, all of the result
434 /// types of the node are known to be legal, but other operands of the node may
435 /// need promotion or expansion as well as the specified one.
436 bool DAGTypeLegalizer::PromoteOperand(SDNode *N, unsigned OpNo) {
437 DEBUG(cerr << "Promote node operand: "; N->dump(&DAG); cerr << "\n");
439 switch (N->getOpcode()) {
442 cerr << "PromoteOperand Op #" << OpNo << ": ";
443 N->dump(&DAG); cerr << "\n";
445 assert(0 && "Do not know how to promote this operator's operand!");
448 case ISD::ANY_EXTEND: Res = PromoteOperand_ANY_EXTEND(N); break;
449 case ISD::ZERO_EXTEND: Res = PromoteOperand_ZERO_EXTEND(N); break;
450 case ISD::SIGN_EXTEND: Res = PromoteOperand_SIGN_EXTEND(N); break;
451 case ISD::TRUNCATE: Res = PromoteOperand_TRUNCATE(N); break;
452 case ISD::FP_EXTEND: Res = PromoteOperand_FP_EXTEND(N); break;
453 case ISD::FP_ROUND: Res = PromoteOperand_FP_ROUND(N); break;
454 case ISD::SINT_TO_FP:
455 case ISD::UINT_TO_FP: Res = PromoteOperand_INT_TO_FP(N); break;
456 case ISD::BUILD_PAIR: Res = PromoteOperand_BUILD_PAIR(N); break;
458 case ISD::SELECT: Res = PromoteOperand_SELECT(N, OpNo); break;
459 case ISD::BRCOND: Res = PromoteOperand_BRCOND(N, OpNo); break;
460 case ISD::BR_CC: Res = PromoteOperand_BR_CC(N, OpNo); break;
461 case ISD::SETCC: Res = PromoteOperand_SETCC(N, OpNo); break;
463 case ISD::STORE: Res = PromoteOperand_STORE(cast<StoreSDNode>(N),
467 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
469 case ISD::BUILD_VECTOR: Res = PromoteOperand_BUILD_VECTOR(N); break;
470 case ISD::INSERT_VECTOR_ELT:
471 Res = PromoteOperand_INSERT_VECTOR_ELT(N, OpNo);
474 case ISD::RET: Res = PromoteOperand_RET(N, OpNo); break;
476 case ISD::MEMBARRIER: Res = PromoteOperand_MEMBARRIER(N); break;
479 // If the result is null, the sub-method took care of registering results etc.
480 if (!Res.Val) return false;
481 // If the result is N, the sub-method updated N in place.
483 // Mark N as new and remark N and its operands. This allows us to correctly
484 // revisit N if it needs another step of promotion and allows us to visit
485 // any new operands to N.
490 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
491 "Invalid operand expansion");
493 ReplaceValueWith(SDOperand(N, 0), Res);
497 SDOperand DAGTypeLegalizer::PromoteOperand_ANY_EXTEND(SDNode *N) {
498 SDOperand Op = GetPromotedOp(N->getOperand(0));
499 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
502 SDOperand DAGTypeLegalizer::PromoteOperand_ZERO_EXTEND(SDNode *N) {
503 SDOperand Op = GetPromotedOp(N->getOperand(0));
504 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
505 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
508 SDOperand DAGTypeLegalizer::PromoteOperand_SIGN_EXTEND(SDNode *N) {
509 SDOperand Op = GetPromotedOp(N->getOperand(0));
510 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
511 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
512 Op, DAG.getValueType(N->getOperand(0).getValueType()));
515 SDOperand DAGTypeLegalizer::PromoteOperand_TRUNCATE(SDNode *N) {
516 SDOperand Op = GetPromotedOp(N->getOperand(0));
517 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
520 SDOperand DAGTypeLegalizer::PromoteOperand_FP_EXTEND(SDNode *N) {
521 SDOperand Op = GetPromotedOp(N->getOperand(0));
522 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
525 SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
526 SDOperand Op = GetPromotedOp(N->getOperand(0));
527 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
528 DAG.getIntPtrConstant(0));
531 SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
532 SDOperand In = GetPromotedOp(N->getOperand(0));
533 MVT::ValueType OpVT = N->getOperand(0).getValueType();
534 if (N->getOpcode() == ISD::UINT_TO_FP)
535 In = DAG.getZeroExtendInReg(In, OpVT);
537 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
538 In, DAG.getValueType(OpVT));
540 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
543 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) {
544 // Since the result type is legal, the operands must promote to it.
545 MVT::ValueType OVT = N->getOperand(0).getValueType();
546 SDOperand Lo = GetPromotedOp(N->getOperand(0));
547 SDOperand Hi = GetPromotedOp(N->getOperand(1));
548 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
550 Lo = DAG.getZeroExtendInReg(Lo, OVT);
551 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
552 DAG.getConstant(MVT::getSizeInBits(OVT),
553 TLI.getShiftAmountTy()));
554 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
557 SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
558 assert(OpNo == 0 && "Only know how to promote condition");
559 SDOperand Cond = GetPromotedOp(N->getOperand(0)); // Promote the condition.
561 // The top bits of the promoted condition are not necessarily zero, ensure
562 // that the value is properly zero extended.
563 unsigned BitWidth = Cond.getValueSizeInBits();
564 if (!DAG.MaskedValueIsZero(Cond,
565 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
566 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
568 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
569 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
573 SDOperand DAGTypeLegalizer::PromoteOperand_BRCOND(SDNode *N, unsigned OpNo) {
574 assert(OpNo == 1 && "only know how to promote condition");
575 SDOperand Cond = GetPromotedOp(N->getOperand(1)); // Promote the condition.
577 // The top bits of the promoted condition are not necessarily zero, ensure
578 // that the value is properly zero extended.
579 unsigned BitWidth = Cond.getValueSizeInBits();
580 if (!DAG.MaskedValueIsZero(Cond,
581 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
582 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
584 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
585 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
589 SDOperand DAGTypeLegalizer::PromoteOperand_BR_CC(SDNode *N, unsigned OpNo) {
590 assert(OpNo == 2 && "Don't know how to promote this operand");
592 SDOperand LHS = N->getOperand(2);
593 SDOperand RHS = N->getOperand(3);
594 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
596 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
598 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
599 N->getOperand(1), LHS, RHS, N->getOperand(4));
602 SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) {
603 assert(OpNo == 0 && "Don't know how to promote this operand");
605 SDOperand LHS = N->getOperand(0);
606 SDOperand RHS = N->getOperand(1);
607 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
609 // The CC (#2) is always legal.
610 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
613 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
614 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
615 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
616 ISD::CondCode CCCode) {
617 MVT::ValueType VT = NewLHS.getValueType();
619 // Get the promoted values.
620 NewLHS = GetPromotedOp(NewLHS);
621 NewRHS = GetPromotedOp(NewRHS);
623 // If this is an FP compare, the operands have already been extended.
624 if (!MVT::isInteger(NewLHS.getValueType()))
627 // Otherwise, we have to insert explicit sign or zero extends. Note
628 // that we could insert sign extends for ALL conditions, but zero extend
629 // is cheaper on many machines (an AND instead of two shifts), so prefer
632 default: assert(0 && "Unknown integer comparison!");
639 // ALL of these operations will work if we either sign or zero extend
640 // the operands (including the unsigned comparisons!). Zero extend is
641 // usually a simpler/cheaper operation, so prefer it.
642 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
643 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
649 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
650 DAG.getValueType(VT));
651 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
652 DAG.getValueType(VT));
657 SDOperand DAGTypeLegalizer::PromoteOperand_STORE(StoreSDNode *N, unsigned OpNo){
658 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
659 int SVOffset = N->getSrcValueOffset();
660 unsigned Alignment = N->getAlignment();
661 bool isVolatile = N->isVolatile();
663 SDOperand Val = GetPromotedOp(N->getValue()); // Get promoted value.
665 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
667 // Truncate the value and store the result.
668 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
669 SVOffset, N->getMemoryVT(),
670 isVolatile, Alignment);
673 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) {
674 // The vector type is legal but the element type is not. This implies
675 // that the vector is a power-of-two in length and that the element
676 // type does not have a strange size (eg: it is not i1).
677 MVT::ValueType VecVT = N->getValueType(0);
678 unsigned NumElts = MVT::getVectorNumElements(VecVT);
679 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
681 // Build a vector of half the length out of elements of twice the bitwidth.
682 // For example <4 x i16> -> <2 x i32>.
683 MVT::ValueType OldVT = N->getOperand(0).getValueType();
684 MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
685 assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
687 std::vector<SDOperand> NewElts;
688 NewElts.reserve(NumElts/2);
690 for (unsigned i = 0; i < NumElts; i += 2) {
691 // Combine two successive elements into one promoted element.
692 SDOperand Lo = N->getOperand(i);
693 SDOperand Hi = N->getOperand(i+1);
694 if (TLI.isBigEndian())
696 NewElts.push_back(DAG.getNode(ISD::BUILD_PAIR, NewVT, Lo, Hi));
699 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
700 MVT::getVectorType(NewVT, NewElts.size()),
701 &NewElts[0], NewElts.size());
703 // Convert the new vector to the old vector type.
704 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
707 SDOperand DAGTypeLegalizer::PromoteOperand_INSERT_VECTOR_ELT(SDNode *N,
710 // Promote the inserted value. This is valid because the type does not
711 // have to match the vector element type.
713 // Check that any extra bits introduced will be truncated away.
714 assert(MVT::getSizeInBits(N->getOperand(1).getValueType()) >=
715 MVT::getSizeInBits(MVT::getVectorElementType(N->getValueType(0))) &&
716 "Type of inserted value narrower than vector element type!");
717 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
718 GetPromotedOp(N->getOperand(1)),
722 assert(OpNo == 2 && "Different operand and result vector types?");
724 // Promote the index.
725 SDOperand Idx = N->getOperand(2);
726 Idx = DAG.getZeroExtendInReg(GetPromotedOp(Idx), Idx.getValueType());
727 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
728 N->getOperand(1), Idx);
731 SDOperand DAGTypeLegalizer::PromoteOperand_RET(SDNode *N, unsigned OpNo) {
732 assert(!(OpNo & 1) && "Return values should be legally typed!");
733 assert((N->getNumOperands() & 1) && "Wrong number of operands!");
735 // It's a flag. Promote all the flags in one hit, as an optimization.
736 SmallVector<SDOperand, 8> NewValues(N->getNumOperands());
737 NewValues[0] = N->getOperand(0); // The chain
738 for (unsigned i = 1, e = N->getNumOperands(); i < e; i += 2) {
740 NewValues[i] = N->getOperand(i);
743 SDOperand Flag = N->getOperand(i + 1);
744 if (getTypeAction(Flag.getValueType()) == Promote)
745 // The promoted value may have rubbish in the new bits, but that
746 // doesn't matter because those bits aren't queried anyway.
747 Flag = GetPromotedOp(Flag);
748 NewValues[i + 1] = Flag;
751 return DAG.UpdateNodeOperands(SDOperand (N, 0),
752 &NewValues[0], NewValues.size());
755 SDOperand DAGTypeLegalizer::PromoteOperand_MEMBARRIER(SDNode *N) {
757 NewOps[0] = N->getOperand(0);
758 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
759 SDOperand Flag = GetPromotedOp(N->getOperand(i));
760 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
762 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
763 array_lengthof(NewOps));