1 //===-- LegalizeTypesPromote.cpp - Promotion for LegalizeTypes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements promotion support for LegalizeTypes. Promotion is the
11 // act of changing a computation in an invalid type to be a computation in a
12 // larger type. For example, implementing i8 arithmetic in an i32 register (as
13 // is often needed on powerpc for example).
15 //===----------------------------------------------------------------------===//
17 #include "LegalizeTypes.h"
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 /// PromoteResult - This method is called when a result of a node is found to be
25 /// in need of promotion to a larger type. At this point, the node may also
26 /// have invalid operands or may have other results that need expansion, we just
27 /// know that (at least) one result needs promotion.
28 void DAGTypeLegalizer::PromoteResult(SDNode *N, unsigned ResNo) {
29 DEBUG(cerr << "Promote node result: "; N->dump(&DAG); cerr << "\n");
30 SDOperand Result = SDOperand();
32 switch (N->getOpcode()) {
35 cerr << "PromoteResult #" << ResNo << ": ";
36 N->dump(&DAG); cerr << "\n";
38 assert(0 && "Do not know how to promote this operator!");
40 case ISD::UNDEF: Result = PromoteResult_UNDEF(N); break;
41 case ISD::Constant: Result = PromoteResult_Constant(N); break;
43 case ISD::TRUNCATE: Result = PromoteResult_TRUNCATE(N); break;
44 case ISD::SIGN_EXTEND:
45 case ISD::ZERO_EXTEND:
46 case ISD::ANY_EXTEND: Result = PromoteResult_INT_EXTEND(N); break;
47 case ISD::FP_ROUND: Result = PromoteResult_FP_ROUND(N); break;
49 case ISD::FP_TO_UINT: Result = PromoteResult_FP_TO_XINT(N); break;
50 case ISD::SETCC: Result = PromoteResult_SETCC(N); break;
51 case ISD::LOAD: Result = PromoteResult_LOAD(cast<LoadSDNode>(N)); break;
52 case ISD::BUILD_PAIR: Result = PromoteResult_BUILD_PAIR(N); break;
59 case ISD::MUL: Result = PromoteResult_SimpleIntBinOp(N); break;
62 case ISD::SREM: Result = PromoteResult_SDIV(N); break;
65 case ISD::UREM: Result = PromoteResult_UDIV(N); break;
67 case ISD::SHL: Result = PromoteResult_SHL(N); break;
68 case ISD::SRA: Result = PromoteResult_SRA(N); break;
69 case ISD::SRL: Result = PromoteResult_SRL(N); break;
71 case ISD::SELECT: Result = PromoteResult_SELECT(N); break;
72 case ISD::SELECT_CC: Result = PromoteResult_SELECT_CC(N); break;
74 case ISD::CTLZ: Result = PromoteResult_CTLZ(N); break;
75 case ISD::CTPOP: Result = PromoteResult_CTPOP(N); break;
76 case ISD::CTTZ: Result = PromoteResult_CTTZ(N); break;
79 // If Result is null, the sub-method took care of registering the result.
81 SetPromotedOp(SDOperand(N, ResNo), Result);
84 SDOperand DAGTypeLegalizer::PromoteResult_UNDEF(SDNode *N) {
85 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
88 SDOperand DAGTypeLegalizer::PromoteResult_Constant(SDNode *N) {
89 MVT::ValueType VT = N->getValueType(0);
90 // Zero extend things like i1, sign extend everything else. It shouldn't
91 // matter in theory which one we pick, but this tends to give better code?
92 unsigned Opc = VT != MVT::i1 ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
93 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
95 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
99 SDOperand DAGTypeLegalizer::PromoteResult_TRUNCATE(SDNode *N) {
102 switch (getTypeAction(N->getOperand(0).getValueType())) {
103 default: assert(0 && "Unknown type action!");
106 Res = N->getOperand(0);
109 Res = GetPromotedOp(N->getOperand(0));
113 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
114 assert(MVT::getSizeInBits(Res.getValueType()) >= MVT::getSizeInBits(NVT) &&
115 "Truncation doesn't make sense!");
116 if (Res.getValueType() == NVT)
119 // Truncate to NVT instead of VT
120 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
123 SDOperand DAGTypeLegalizer::PromoteResult_INT_EXTEND(SDNode *N) {
124 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
126 if (getTypeAction(N->getOperand(0).getValueType()) == Promote) {
127 SDOperand Res = GetPromotedOp(N->getOperand(0));
128 assert(MVT::getSizeInBits(Res.getValueType()) <= MVT::getSizeInBits(NVT) &&
129 "Extension doesn't make sense!");
131 // If the result and operand types are the same after promotion, simplify
132 // to an in-register extension.
133 if (NVT == Res.getValueType()) {
134 // The high bits are not guaranteed to be anything. Insert an extend.
135 if (N->getOpcode() == ISD::SIGN_EXTEND)
136 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
137 DAG.getValueType(N->getOperand(0).getValueType()));
138 if (N->getOpcode() == ISD::ZERO_EXTEND)
139 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
140 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
145 // Otherwise, just extend the original operand all the way to the larger type.
146 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
149 SDOperand DAGTypeLegalizer::PromoteResult_FP_ROUND(SDNode *N) {
150 // NOTE: Assumes input is legal.
151 if (N->getConstantOperandVal(1) == 0)
152 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
153 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
154 // If the precision discard isn't needed, just return the operand unrounded.
155 return N->getOperand(0);
158 SDOperand DAGTypeLegalizer::PromoteResult_FP_TO_XINT(SDNode *N) {
159 SDOperand Op = N->getOperand(0);
160 // If the operand needed to be promoted, do so now.
161 if (getTypeAction(Op.getValueType()) == Promote)
162 // The input result is prerounded, so we don't have to do anything special.
163 Op = GetPromotedOp(Op);
165 unsigned NewOpc = N->getOpcode();
166 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
168 // If we're promoting a UINT to a larger size, check to see if the new node
169 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
170 // we can use that instead. This allows us to generate better code for
171 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
172 // legal, such as PowerPC.
173 if (N->getOpcode() == ISD::FP_TO_UINT) {
174 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
175 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
176 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
177 NewOpc = ISD::FP_TO_SINT;
180 return DAG.getNode(NewOpc, NVT, Op);
183 SDOperand DAGTypeLegalizer::PromoteResult_SETCC(SDNode *N) {
184 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
185 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), N->getOperand(0),
186 N->getOperand(1), N->getOperand(2));
189 SDOperand DAGTypeLegalizer::PromoteResult_LOAD(LoadSDNode *N) {
190 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
191 ISD::LoadExtType ExtType =
192 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
193 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
194 N->getSrcValue(), N->getSrcValueOffset(),
195 N->getMemoryVT(), N->isVolatile(),
198 // Legalized the chain result - switch anything that used the old chain to
200 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
204 SDOperand DAGTypeLegalizer::PromoteResult_BUILD_PAIR(SDNode *N) {
205 // The pair element type may be legal, or may not promote to the same type as
206 // the result, for example i16 = BUILD_PAIR (i8, i8) when i8 is legal but i16
207 // is not. Handle all cases.
208 MVT::ValueType LVT = N->getOperand(0).getValueType();
209 MVT::ValueType NVT = TLI.getTypeToTransformTo(N->getValueType(0));
210 SDOperand Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
211 SDOperand Hi = DAG.getNode(ISD::ANY_EXTEND, NVT, N->getOperand(1));
212 Hi = DAG.getNode(ISD::SHL, NVT, Hi, DAG.getConstant(MVT::getSizeInBits(LVT),
213 TLI.getShiftAmountTy()));
214 return DAG.getNode(ISD::OR, NVT, Lo, Hi);
217 SDOperand DAGTypeLegalizer::PromoteResult_SimpleIntBinOp(SDNode *N) {
218 // The input may have strange things in the top bits of the registers, but
219 // these operations don't care. They may have weird bits going out, but
220 // that too is okay if they are integer operations.
221 SDOperand LHS = GetPromotedOp(N->getOperand(0));
222 SDOperand RHS = GetPromotedOp(N->getOperand(1));
223 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
226 SDOperand DAGTypeLegalizer::PromoteResult_SDIV(SDNode *N) {
227 // Sign extend the input.
228 SDOperand LHS = GetPromotedOp(N->getOperand(0));
229 SDOperand RHS = GetPromotedOp(N->getOperand(1));
230 MVT::ValueType VT = N->getValueType(0);
231 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
232 DAG.getValueType(VT));
233 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
234 DAG.getValueType(VT));
236 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
239 SDOperand DAGTypeLegalizer::PromoteResult_UDIV(SDNode *N) {
240 // Zero extend the input.
241 SDOperand LHS = GetPromotedOp(N->getOperand(0));
242 SDOperand RHS = GetPromotedOp(N->getOperand(1));
243 MVT::ValueType VT = N->getValueType(0);
244 LHS = DAG.getZeroExtendInReg(LHS, VT);
245 RHS = DAG.getZeroExtendInReg(RHS, VT);
247 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
250 SDOperand DAGTypeLegalizer::PromoteResult_SHL(SDNode *N) {
251 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
252 GetPromotedOp(N->getOperand(0)), N->getOperand(1));
255 SDOperand DAGTypeLegalizer::PromoteResult_SRA(SDNode *N) {
256 // The input value must be properly sign extended.
257 MVT::ValueType VT = N->getValueType(0);
258 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
259 SDOperand Res = GetPromotedOp(N->getOperand(0));
260 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
261 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
264 SDOperand DAGTypeLegalizer::PromoteResult_SRL(SDNode *N) {
265 // The input value must be properly zero extended.
266 MVT::ValueType VT = N->getValueType(0);
267 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
268 SDOperand Res = GetPromotedZExtOp(N->getOperand(0));
269 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
272 SDOperand DAGTypeLegalizer::PromoteResult_SELECT(SDNode *N) {
273 SDOperand LHS = GetPromotedOp(N->getOperand(1));
274 SDOperand RHS = GetPromotedOp(N->getOperand(2));
275 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
278 SDOperand DAGTypeLegalizer::PromoteResult_SELECT_CC(SDNode *N) {
279 SDOperand LHS = GetPromotedOp(N->getOperand(2));
280 SDOperand RHS = GetPromotedOp(N->getOperand(3));
281 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
282 N->getOperand(1), LHS, RHS, N->getOperand(4));
285 SDOperand DAGTypeLegalizer::PromoteResult_CTLZ(SDNode *N) {
286 SDOperand Op = GetPromotedOp(N->getOperand(0));
287 MVT::ValueType OVT = N->getValueType(0);
288 MVT::ValueType NVT = Op.getValueType();
289 // Zero extend to the promoted type and do the count there.
290 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
291 // Subtract off the extra leading bits in the bigger type.
292 return DAG.getNode(ISD::SUB, NVT, Op,
293 DAG.getConstant(MVT::getSizeInBits(NVT) -
294 MVT::getSizeInBits(OVT), NVT));
297 SDOperand DAGTypeLegalizer::PromoteResult_CTPOP(SDNode *N) {
298 SDOperand Op = GetPromotedOp(N->getOperand(0));
299 MVT::ValueType OVT = N->getValueType(0);
300 MVT::ValueType NVT = Op.getValueType();
301 // Zero extend to the promoted type and do the count there.
302 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
305 SDOperand DAGTypeLegalizer::PromoteResult_CTTZ(SDNode *N) {
306 SDOperand Op = GetPromotedOp(N->getOperand(0));
307 MVT::ValueType OVT = N->getValueType(0);
308 MVT::ValueType NVT = Op.getValueType();
309 // The count is the same in the promoted type except if the original
310 // value was zero. This can be handled by setting the bit just off
311 // the top of the original type.
312 Op = DAG.getNode(ISD::OR, NVT, Op,
313 // FIXME: Do this using an APINT constant.
314 DAG.getConstant(1UL << MVT::getSizeInBits(OVT), NVT));
315 return DAG.getNode(ISD::CTTZ, NVT, Op);
318 //===----------------------------------------------------------------------===//
320 //===----------------------------------------------------------------------===//
322 /// PromoteOperand - This method is called when the specified operand of the
323 /// specified node is found to need promotion. At this point, all of the result
324 /// types of the node are known to be legal, but other operands of the node may
325 /// need promotion or expansion as well as the specified one.
326 bool DAGTypeLegalizer::PromoteOperand(SDNode *N, unsigned OpNo) {
327 DEBUG(cerr << "Promote node operand: "; N->dump(&DAG); cerr << "\n");
329 switch (N->getOpcode()) {
332 cerr << "PromoteOperand Op #" << OpNo << ": ";
333 N->dump(&DAG); cerr << "\n";
335 assert(0 && "Do not know how to promote this operator's operand!");
338 case ISD::ANY_EXTEND: Res = PromoteOperand_ANY_EXTEND(N); break;
339 case ISD::ZERO_EXTEND: Res = PromoteOperand_ZERO_EXTEND(N); break;
340 case ISD::SIGN_EXTEND: Res = PromoteOperand_SIGN_EXTEND(N); break;
341 case ISD::TRUNCATE: Res = PromoteOperand_TRUNCATE(N); break;
342 case ISD::FP_EXTEND: Res = PromoteOperand_FP_EXTEND(N); break;
343 case ISD::FP_ROUND: Res = PromoteOperand_FP_ROUND(N); break;
344 case ISD::SINT_TO_FP:
345 case ISD::UINT_TO_FP: Res = PromoteOperand_INT_TO_FP(N); break;
346 case ISD::BUILD_PAIR: Res = PromoteOperand_BUILD_PAIR(N); break;
348 case ISD::SELECT: Res = PromoteOperand_SELECT(N, OpNo); break;
349 case ISD::BRCOND: Res = PromoteOperand_BRCOND(N, OpNo); break;
350 case ISD::BR_CC: Res = PromoteOperand_BR_CC(N, OpNo); break;
351 case ISD::SETCC: Res = PromoteOperand_SETCC(N, OpNo); break;
353 case ISD::STORE: Res = PromoteOperand_STORE(cast<StoreSDNode>(N),
357 case ISD::MEMMOVE: Res = HandleMemIntrinsic(N); break;
359 case ISD::BUILD_VECTOR: Res = PromoteOperand_BUILD_VECTOR(N); break;
361 case ISD::RET: Res = PromoteOperand_RET(N, OpNo); break;
364 // If the result is null, the sub-method took care of registering results etc.
365 if (!Res.Val) return false;
366 // If the result is N, the sub-method updated N in place.
368 // Mark N as new and remark N and its operands. This allows us to correctly
369 // revisit N if it needs another step of promotion and allows us to visit
370 // any new operands to N.
371 N->setNodeId(NewNode);
376 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
377 "Invalid operand expansion");
379 ReplaceValueWith(SDOperand(N, 0), Res);
383 SDOperand DAGTypeLegalizer::PromoteOperand_ANY_EXTEND(SDNode *N) {
384 SDOperand Op = GetPromotedOp(N->getOperand(0));
385 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
388 SDOperand DAGTypeLegalizer::PromoteOperand_ZERO_EXTEND(SDNode *N) {
389 SDOperand Op = GetPromotedOp(N->getOperand(0));
390 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
391 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
394 SDOperand DAGTypeLegalizer::PromoteOperand_SIGN_EXTEND(SDNode *N) {
395 SDOperand Op = GetPromotedOp(N->getOperand(0));
396 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
398 Op, DAG.getValueType(N->getOperand(0).getValueType()));
401 SDOperand DAGTypeLegalizer::PromoteOperand_TRUNCATE(SDNode *N) {
402 SDOperand Op = GetPromotedOp(N->getOperand(0));
403 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
406 SDOperand DAGTypeLegalizer::PromoteOperand_FP_EXTEND(SDNode *N) {
407 SDOperand Op = GetPromotedOp(N->getOperand(0));
408 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
411 SDOperand DAGTypeLegalizer::PromoteOperand_FP_ROUND(SDNode *N) {
412 SDOperand Op = GetPromotedOp(N->getOperand(0));
413 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
414 DAG.getIntPtrConstant(0));
417 SDOperand DAGTypeLegalizer::PromoteOperand_INT_TO_FP(SDNode *N) {
418 SDOperand In = GetPromotedOp(N->getOperand(0));
419 MVT::ValueType OpVT = N->getOperand(0).getValueType();
420 if (N->getOpcode() == ISD::UINT_TO_FP)
421 In = DAG.getZeroExtendInReg(In, OpVT);
423 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
424 In, DAG.getValueType(OpVT));
426 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
429 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_PAIR(SDNode *N) {
430 // Since the result type is legal, the operands must promote to it.
431 MVT::ValueType OVT = N->getOperand(0).getValueType();
432 SDOperand Lo = GetPromotedOp(N->getOperand(0));
433 SDOperand Hi = GetPromotedOp(N->getOperand(1));
434 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
436 Lo = DAG.getZeroExtendInReg(Lo, OVT);
437 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
438 DAG.getConstant(MVT::getSizeInBits(OVT),
439 TLI.getShiftAmountTy()));
440 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
443 SDOperand DAGTypeLegalizer::PromoteOperand_SELECT(SDNode *N, unsigned OpNo) {
444 assert(OpNo == 0 && "Only know how to promote condition");
445 SDOperand Cond = GetPromotedOp(N->getOperand(0)); // Promote the condition.
447 // The top bits of the promoted condition are not necessarily zero, ensure
448 // that the value is properly zero extended.
449 unsigned BitWidth = Cond.getValueSizeInBits();
450 if (!DAG.MaskedValueIsZero(Cond,
451 APInt::getHighBitsSet(BitWidth, BitWidth-1))) {
452 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
453 MarkNewNodes(Cond.Val);
456 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
457 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
461 SDOperand DAGTypeLegalizer::PromoteOperand_BRCOND(SDNode *N, unsigned OpNo) {
462 assert(OpNo == 1 && "only know how to promote condition");
463 SDOperand Cond = GetPromotedOp(N->getOperand(1)); // Promote the condition.
465 // The top bits of the promoted condition are not necessarily zero, ensure
466 // that the value is properly zero extended.
467 unsigned BitWidth = Cond.getValueSizeInBits();
468 if (!DAG.MaskedValueIsZero(Cond,
469 APInt::getHighBitsSet(BitWidth, BitWidth-1))) {
470 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
471 MarkNewNodes(Cond.Val);
474 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
475 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
479 SDOperand DAGTypeLegalizer::PromoteOperand_BR_CC(SDNode *N, unsigned OpNo) {
480 assert(OpNo == 2 && "Don't know how to promote this operand");
482 SDOperand LHS = N->getOperand(2);
483 SDOperand RHS = N->getOperand(3);
484 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
486 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
488 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
489 N->getOperand(1), LHS, RHS, N->getOperand(4));
492 SDOperand DAGTypeLegalizer::PromoteOperand_SETCC(SDNode *N, unsigned OpNo) {
493 assert(OpNo == 0 && "Don't know how to promote this operand");
495 SDOperand LHS = N->getOperand(0);
496 SDOperand RHS = N->getOperand(1);
497 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
499 // The CC (#2) is always legal.
500 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
503 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
504 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
505 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
506 ISD::CondCode CCCode) {
507 MVT::ValueType VT = NewLHS.getValueType();
509 // Get the promoted values.
510 NewLHS = GetPromotedOp(NewLHS);
511 NewRHS = GetPromotedOp(NewRHS);
513 // If this is an FP compare, the operands have already been extended.
514 if (!MVT::isInteger(NewLHS.getValueType()))
517 // Otherwise, we have to insert explicit sign or zero extends. Note
518 // that we could insert sign extends for ALL conditions, but zero extend
519 // is cheaper on many machines (an AND instead of two shifts), so prefer
522 default: assert(0 && "Unknown integer comparison!");
529 // ALL of these operations will work if we either sign or zero extend
530 // the operands (including the unsigned comparisons!). Zero extend is
531 // usually a simpler/cheaper operation, so prefer it.
532 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
533 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
539 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
540 DAG.getValueType(VT));
541 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
542 DAG.getValueType(VT));
547 SDOperand DAGTypeLegalizer::PromoteOperand_STORE(StoreSDNode *N, unsigned OpNo){
548 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
549 int SVOffset = N->getSrcValueOffset();
550 unsigned Alignment = N->getAlignment();
551 bool isVolatile = N->isVolatile();
553 SDOperand Val = GetPromotedOp(N->getValue()); // Get promoted value.
555 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
557 // Truncate the value and store the result.
558 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
559 SVOffset, N->getMemoryVT(),
560 isVolatile, Alignment);
563 SDOperand DAGTypeLegalizer::PromoteOperand_BUILD_VECTOR(SDNode *N) {
564 // The vector type is legal but the element type is not. This implies
565 // that the vector is a power-of-two in length and that the element
566 // type does not have a strange size (eg: it is not i1).
567 MVT::ValueType VecVT = N->getValueType(0);
568 unsigned NumElts = MVT::getVectorNumElements(VecVT);
569 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
571 // Build a vector of half the length out of elements of twice the bitwidth.
572 // For example <4 x i16> -> <2 x i32>.
573 MVT::ValueType OldVT = N->getOperand(0).getValueType();
574 MVT::ValueType NewVT = MVT::getIntegerType(2 * MVT::getSizeInBits(OldVT));
575 assert(!MVT::isExtendedVT(OldVT) && !MVT::isExtendedVT(NewVT));
577 std::vector<SDOperand> NewElts;
578 NewElts.reserve(NumElts/2);
580 for (unsigned i = 0; i < NumElts; i += 2) {
581 // Combine two successive elements into one promoted element.
582 SDOperand Lo = N->getOperand(i);
583 SDOperand Hi = N->getOperand(i+1);
584 if (TLI.isBigEndian())
586 NewElts.push_back(DAG.getNode(ISD::BUILD_PAIR, NewVT, Lo, Hi));
589 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
590 MVT::getVectorType(NewVT, NewElts.size()),
591 &NewElts[0], NewElts.size());
593 // Convert the new vector to the old vector type.
594 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
597 SDOperand DAGTypeLegalizer::PromoteOperand_RET(SDNode *N, unsigned OpNo) {
598 assert(!(OpNo & 1) && "Return values should be legally typed!");
599 assert((N->getNumOperands() & 1) && "Wrong number of operands!");
601 // It's a flag. Promote all the flags in one hit, as an optimization.
602 SmallVector<SDOperand, 8> NewValues(N->getNumOperands());
603 NewValues[0] = N->getOperand(0); // The chain
604 for (unsigned i = 1, e = N->getNumOperands(); i < e; i += 2) {
606 NewValues[i] = N->getOperand(i);
609 SDOperand Flag = N->getOperand(i + 1);
610 if (getTypeAction(Flag.getValueType()) == Promote)
611 // The promoted value may have rubbish in the new bits, but that
612 // doesn't matter because those bits aren't queried anyway.
613 Flag = GetPromotedOp(Flag);
614 NewValues[i + 1] = Flag;
617 return DAG.UpdateNodeOperands(SDOperand (N, 0),
618 &NewValues[0], NewValues.size());