1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Result = SDValue();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
65 case ISD::EXTRACT_VECTOR_ELT:
66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
80 case ISD::SIGN_EXTEND:
81 case ISD::ZERO_EXTEND:
82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
101 // If Result is null, the sub-method took care of registering the result.
102 if (Result.getNode())
103 SetPromotedInteger(SDValue(N, ResNo), Result);
106 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
107 // Sign-extend the new bits, and continue the assertion.
108 MVT OldVT = N->getValueType(0);
109 SDValue Op = GetPromotedInteger(N->getOperand(0));
110 return DAG.getNode(ISD::AssertSext, Op.getValueType(),
111 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
112 DAG.getValueType(OldVT)), N->getOperand(1));
115 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
116 // Zero the new bits, and continue the assertion.
117 MVT OldVT = N->getValueType(0);
118 SDValue Op = GetPromotedInteger(N->getOperand(0));
119 return DAG.getNode(ISD::AssertZext, Op.getValueType(),
120 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
123 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
124 SDValue InOp = N->getOperand(0);
125 MVT InVT = InOp.getValueType();
126 MVT NInVT = TLI.getTypeToTransformTo(InVT);
127 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
129 switch (getTypeAction(InVT)) {
131 assert(false && "Unknown type action!");
136 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
137 // The input promotes to the same size. Convert the promoted value.
138 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
141 // Promote the integer operand by hand.
142 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
146 case ScalarizeVector:
147 // Convert the element to an integer and promote it by hand.
148 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
149 BitConvertToInteger(GetScalarizedVector(InOp)));
151 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
152 // pieces of the input into integers and reassemble in the final type.
154 GetSplitVector(N->getOperand(0), Lo, Hi);
155 Lo = BitConvertToInteger(Lo);
156 Hi = BitConvertToInteger(Hi);
158 if (TLI.isBigEndian())
161 InOp = DAG.getNode(ISD::ANY_EXTEND,
162 MVT::getIntegerVT(OutVT.getSizeInBits()),
163 JoinIntegers(Lo, Hi));
164 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
167 // Otherwise, lower the bit-convert to a store/load from the stack, then
169 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
170 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
173 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
174 SDValue Op = GetPromotedInteger(N->getOperand(0));
175 MVT OVT = N->getValueType(0);
176 MVT NVT = Op.getValueType();
178 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
179 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
180 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
183 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
184 // The pair element type may be legal, or may not promote to the same type as
185 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
186 return DAG.getNode(ISD::ANY_EXTEND,
187 TLI.getTypeToTransformTo(N->getValueType(0)),
188 JoinIntegers(N->getOperand(0), N->getOperand(1)));
191 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
192 MVT VT = N->getValueType(0);
193 // Zero extend things like i1, sign extend everything else. It shouldn't
194 // matter in theory which one we pick, but this tends to give better code?
195 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
196 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
198 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
202 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
203 SDValue Op = GetPromotedInteger(N->getOperand(0));
204 MVT OVT = N->getValueType(0);
205 MVT NVT = Op.getValueType();
206 // Zero extend to the promoted type and do the count there.
207 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
208 // Subtract off the extra leading bits in the bigger type.
209 return DAG.getNode(ISD::SUB, NVT, Op,
210 DAG.getConstant(NVT.getSizeInBits() -
211 OVT.getSizeInBits(), NVT));
214 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
215 SDValue Op = GetPromotedInteger(N->getOperand(0));
216 MVT OVT = N->getValueType(0);
217 MVT NVT = Op.getValueType();
218 // Zero extend to the promoted type and do the count there.
219 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
222 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
223 SDValue Op = GetPromotedInteger(N->getOperand(0));
224 MVT OVT = N->getValueType(0);
225 MVT NVT = Op.getValueType();
226 // The count is the same in the promoted type except if the original
227 // value was zero. This can be handled by setting the bit just off
228 // the top of the original type.
229 APInt TopBit(NVT.getSizeInBits(), 0);
230 TopBit.set(OVT.getSizeInBits());
231 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
232 return DAG.getNode(ISD::CTTZ, NVT, Op);
235 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
236 MVT OldVT = N->getValueType(0);
237 SDValue OldVec = N->getOperand(0);
238 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
241 assert(!isTypeLegal(OldVec.getValueType()) &&
242 "Legal one-element vector of a type needing promotion!");
243 // It is tempting to follow GetScalarizedVector by a call to
244 // GetPromotedInteger, but this would be wrong because the
245 // scalarized value may not yet have been processed.
246 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
247 GetScalarizedVector(OldVec));
250 // Convert to a vector half as long with an element type of twice the width,
251 // for example <4 x i16> -> <2 x i32>.
252 assert(!(OldElts & 1) && "Odd length vectors not supported!");
253 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
254 assert(OldVT.isSimple() && NewVT.isSimple());
256 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
257 MVT::getVectorVT(NewVT, OldElts / 2),
260 // Extract the element at OldIdx / 2 from the new vector.
261 SDValue OldIdx = N->getOperand(1);
262 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
263 DAG.getConstant(1, TLI.getShiftAmountTy()));
264 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
266 // Select the appropriate half of the element: Lo if OldIdx was even,
269 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
270 DAG.getConstant(OldVT.getSizeInBits(),
271 TLI.getShiftAmountTy()));
272 if (TLI.isBigEndian())
275 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
276 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
279 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
280 unsigned NewOpc = N->getOpcode();
281 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
283 // If we're promoting a UINT to a larger size, check to see if the new node
284 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
285 // we can use that instead. This allows us to generate better code for
286 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
287 // legal, such as PowerPC.
288 if (N->getOpcode() == ISD::FP_TO_UINT) {
289 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
290 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
291 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
292 NewOpc = ISD::FP_TO_SINT;
295 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
298 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
299 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
301 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
302 SDValue Res = GetPromotedInteger(N->getOperand(0));
303 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
304 "Extension doesn't make sense!");
306 // If the result and operand types are the same after promotion, simplify
307 // to an in-register extension.
308 if (NVT == Res.getValueType()) {
309 // The high bits are not guaranteed to be anything. Insert an extend.
310 if (N->getOpcode() == ISD::SIGN_EXTEND)
311 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
312 DAG.getValueType(N->getOperand(0).getValueType()));
313 if (N->getOpcode() == ISD::ZERO_EXTEND)
314 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
315 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
320 // Otherwise, just extend the original operand all the way to the larger type.
321 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
324 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
325 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
326 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
327 ISD::LoadExtType ExtType =
328 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
329 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
330 N->getSrcValue(), N->getSrcValueOffset(),
331 N->getMemoryVT(), N->isVolatile(),
334 // Legalized the chain result - switch anything that used the old chain to
336 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
340 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
341 // Sign extend the input.
342 SDValue LHS = GetPromotedInteger(N->getOperand(0));
343 SDValue RHS = GetPromotedInteger(N->getOperand(1));
344 MVT VT = N->getValueType(0);
345 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
346 DAG.getValueType(VT));
347 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
348 DAG.getValueType(VT));
350 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
353 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
354 SDValue LHS = GetPromotedInteger(N->getOperand(1));
355 SDValue RHS = GetPromotedInteger(N->getOperand(2));
356 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
359 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
360 SDValue LHS = GetPromotedInteger(N->getOperand(2));
361 SDValue RHS = GetPromotedInteger(N->getOperand(3));
362 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
363 N->getOperand(1), LHS, RHS, N->getOperand(4));
366 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
367 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
368 MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
369 assert(isTypeLegal(SVT) && "SetCC type not legal??");
370 assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
371 "Integer type overpromoted?");
372 return DAG.getNode(ISD::TRUNCATE, NVT,
373 DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
374 N->getOperand(1), N->getOperand(2)));
377 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
378 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
379 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
382 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
383 SDValue Op = GetPromotedInteger(N->getOperand(0));
384 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
388 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
389 // The input may have strange things in the top bits of the registers, but
390 // these operations don't care. They may have weird bits going out, but
391 // that too is okay if they are integer operations.
392 SDValue LHS = GetPromotedInteger(N->getOperand(0));
393 SDValue RHS = GetPromotedInteger(N->getOperand(1));
394 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
397 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
398 // The input value must be properly sign extended.
399 MVT VT = N->getValueType(0);
400 MVT NVT = TLI.getTypeToTransformTo(VT);
401 SDValue Res = GetPromotedInteger(N->getOperand(0));
402 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
403 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
406 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
407 // The input value must be properly zero extended.
408 MVT VT = N->getValueType(0);
409 MVT NVT = TLI.getTypeToTransformTo(VT);
410 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
411 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
414 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
417 switch (getTypeAction(N->getOperand(0).getValueType())) {
418 default: assert(0 && "Unknown type action!");
421 Res = N->getOperand(0);
424 Res = GetPromotedInteger(N->getOperand(0));
428 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
429 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
430 "Truncation doesn't make sense!");
431 if (Res.getValueType() == NVT)
434 // Truncate to NVT instead of VT
435 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
438 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
439 // Zero extend the input.
440 SDValue LHS = GetPromotedInteger(N->getOperand(0));
441 SDValue RHS = GetPromotedInteger(N->getOperand(1));
442 MVT VT = N->getValueType(0);
443 LHS = DAG.getZeroExtendInReg(LHS, VT);
444 RHS = DAG.getZeroExtendInReg(RHS, VT);
446 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
449 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
450 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
453 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
454 SDValue Chain = N->getOperand(0); // Get the chain.
455 SDValue Ptr = N->getOperand(1); // Get the pointer.
456 MVT VT = N->getValueType(0);
458 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
459 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
461 // Increment the arg pointer, VAList, to the next vaarg
462 // FIXME: should the ABI size be used for the increment? Think of
463 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
464 // integers of unusual size (such MVT::i1, which gives an increment
466 unsigned Increment = VT.getSizeInBits() / 8;
467 SDValue Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
468 DAG.getConstant(Increment, TLI.getPointerTy()));
470 // Store the incremented VAList to the pointer.
471 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
473 // Load the actual argument out of the arg pointer VAList.
474 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
475 VAList, NULL, 0, VT);
477 // Legalized the chain result - switch anything that used the old chain to
479 ReplaceValueWith(SDValue(N, 1), Tmp.getValue(1));
484 //===----------------------------------------------------------------------===//
485 // Integer Operand Promotion
486 //===----------------------------------------------------------------------===//
488 /// PromoteIntegerOperand - This method is called when the specified operand of
489 /// the specified node is found to need promotion. At this point, all of the
490 /// result types of the node are known to be legal, but other operands of the
491 /// node may need promotion or expansion as well as the specified one.
492 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
493 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
494 SDValue Res = SDValue();
496 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
497 == TargetLowering::Custom)
498 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
500 if (Res.getNode() == 0) {
501 switch (N->getOpcode()) {
504 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
505 N->dump(&DAG); cerr << "\n";
507 assert(0 && "Do not know how to promote this operator's operand!");
510 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
511 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
512 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
513 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
514 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
515 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
516 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
517 case ISD::INSERT_VECTOR_ELT:
518 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
519 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
520 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
521 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
522 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
523 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
524 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
526 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
527 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
529 case ISD::SINT_TO_FP:
530 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
534 // If the result is null, the sub-method took care of registering results etc.
535 if (!Res.getNode()) return false;
536 // If the result is N, the sub-method updated N in place.
537 if (Res.getNode() == N) {
538 // Mark N as new and remark N and its operands. This allows us to correctly
539 // revisit N if it needs another step of promotion and allows us to visit
540 // any new operands to N.
545 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
546 "Invalid operand expansion");
548 ReplaceValueWith(SDValue(N, 0), Res);
552 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
553 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
554 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
555 ISD::CondCode CCCode) {
556 MVT VT = NewLHS.getValueType();
558 // Get the promoted values.
559 NewLHS = GetPromotedInteger(NewLHS);
560 NewRHS = GetPromotedInteger(NewRHS);
562 // Otherwise, we have to insert explicit sign or zero extends. Note
563 // that we could insert sign extends for ALL conditions, but zero extend
564 // is cheaper on many machines (an AND instead of two shifts), so prefer
567 default: assert(0 && "Unknown integer comparison!");
574 // ALL of these operations will work if we either sign or zero extend
575 // the operands (including the unsigned comparisons!). Zero extend is
576 // usually a simpler/cheaper operation, so prefer it.
577 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
578 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
584 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
585 DAG.getValueType(VT));
586 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
587 DAG.getValueType(VT));
592 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
593 SDValue Op = GetPromotedInteger(N->getOperand(0));
594 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
597 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
598 assert(OpNo == 2 && "Don't know how to promote this operand!");
600 SDValue LHS = N->getOperand(2);
601 SDValue RHS = N->getOperand(3);
602 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
604 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
606 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
607 N->getOperand(1), LHS, RHS, N->getOperand(4));
610 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
611 assert(OpNo == 1 && "only know how to promote condition");
612 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
614 // The top bits of the promoted condition are not necessarily zero, ensure
615 // that the value is properly zero extended.
616 unsigned BitWidth = Cond.getValueSizeInBits();
617 if (!DAG.MaskedValueIsZero(Cond,
618 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
619 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
621 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
622 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
626 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
627 // Since the result type is legal, the operands must promote to it.
628 MVT OVT = N->getOperand(0).getValueType();
629 SDValue Lo = GetPromotedInteger(N->getOperand(0));
630 SDValue Hi = GetPromotedInteger(N->getOperand(1));
631 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
633 Lo = DAG.getZeroExtendInReg(Lo, OVT);
634 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
635 DAG.getConstant(OVT.getSizeInBits(),
636 TLI.getShiftAmountTy()));
637 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
640 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
641 // The vector type is legal but the element type is not. This implies
642 // that the vector is a power-of-two in length and that the element
643 // type does not have a strange size (eg: it is not i1).
644 MVT VecVT = N->getValueType(0);
645 unsigned NumElts = VecVT.getVectorNumElements();
646 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
648 // Build a vector of half the length out of elements of twice the bitwidth.
649 // For example <4 x i16> -> <2 x i32>.
650 MVT OldVT = N->getOperand(0).getValueType();
651 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
652 assert(OldVT.isSimple() && NewVT.isSimple());
654 std::vector<SDValue> NewElts;
655 NewElts.reserve(NumElts/2);
657 for (unsigned i = 0; i < NumElts; i += 2) {
658 // Combine two successive elements into one promoted element.
659 SDValue Lo = N->getOperand(i);
660 SDValue Hi = N->getOperand(i+1);
661 if (TLI.isBigEndian())
663 NewElts.push_back(JoinIntegers(Lo, Hi));
666 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
667 MVT::getVectorVT(NewVT, NewElts.size()),
668 &NewElts[0], NewElts.size());
670 // Convert the new vector to the old vector type.
671 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
674 SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
675 SDValue Op = GetPromotedInteger(N->getOperand(0));
676 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
679 SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
680 SDValue Op = GetPromotedInteger(N->getOperand(0));
681 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
682 DAG.getIntPtrConstant(0));
685 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
688 // Promote the inserted value. This is valid because the type does not
689 // have to match the vector element type.
691 // Check that any extra bits introduced will be truncated away.
692 assert(N->getOperand(1).getValueType().getSizeInBits() >=
693 N->getValueType(0).getVectorElementType().getSizeInBits() &&
694 "Type of inserted value narrower than vector element type!");
695 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
696 GetPromotedInteger(N->getOperand(1)),
700 assert(OpNo == 2 && "Different operand and result vector types?");
702 // Promote the index.
703 SDValue Idx = N->getOperand(2);
704 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
705 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
706 N->getOperand(1), Idx);
709 SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
710 SDValue In = GetPromotedInteger(N->getOperand(0));
711 MVT OpVT = N->getOperand(0).getValueType();
712 if (N->getOpcode() == ISD::UINT_TO_FP)
713 In = DAG.getZeroExtendInReg(In, OpVT);
715 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
716 In, DAG.getValueType(OpVT));
718 return DAG.UpdateNodeOperands(SDValue(N, 0), In);
721 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
723 NewOps[0] = N->getOperand(0);
724 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
725 SDValue Flag = GetPromotedInteger(N->getOperand(i));
726 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
728 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
729 array_lengthof(NewOps));
732 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
733 assert(OpNo == 0 && "Only know how to promote condition");
734 SDValue Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
736 // The top bits of the promoted condition are not necessarily zero, ensure
737 // that the value is properly zero extended.
738 unsigned BitWidth = Cond.getValueSizeInBits();
739 if (!DAG.MaskedValueIsZero(Cond,
740 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
741 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
743 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
744 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, N->getOperand(1),
748 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
749 assert(OpNo == 0 && "Don't know how to promote this operand!");
751 SDValue LHS = N->getOperand(0);
752 SDValue RHS = N->getOperand(1);
753 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
755 // The CC (#4) and the possible return values (#2 and #3) have legal types.
756 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
757 N->getOperand(3), N->getOperand(4));
760 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
761 assert(OpNo == 0 && "Don't know how to promote this operand!");
763 SDValue LHS = N->getOperand(0);
764 SDValue RHS = N->getOperand(1);
765 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
767 // The CC (#2) is always legal.
768 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
771 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
772 SDValue Op = GetPromotedInteger(N->getOperand(0));
773 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
774 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
775 Op, DAG.getValueType(N->getOperand(0).getValueType()));
778 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
779 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
780 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
781 int SVOffset = N->getSrcValueOffset();
782 unsigned Alignment = N->getAlignment();
783 bool isVolatile = N->isVolatile();
785 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
787 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
789 // Truncate the value and store the result.
790 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
791 SVOffset, N->getMemoryVT(),
792 isVolatile, Alignment);
795 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
796 SDValue Op = GetPromotedInteger(N->getOperand(0));
797 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
800 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
801 SDValue Op = GetPromotedInteger(N->getOperand(0));
802 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
803 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
807 //===----------------------------------------------------------------------===//
808 // Integer Result Expansion
809 //===----------------------------------------------------------------------===//
811 /// ExpandIntegerResult - This method is called when the specified result of the
812 /// specified node is found to need expansion. At this point, the node may also
813 /// have invalid operands or may have other results that need promotion, we just
814 /// know that (at least) one result needs expansion.
815 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
816 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
820 // See if the target wants to custom expand this node.
821 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
822 TargetLowering::Custom) {
823 // If the target wants to, allow it to lower this itself.
824 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
825 // Everything that once used N now uses P. We are guaranteed that the
826 // result value types of N and the result value types of P match.
827 ReplaceNodeWith(N, P);
832 switch (N->getOpcode()) {
835 cerr << "ExpandIntegerResult #" << ResNo << ": ";
836 N->dump(&DAG); cerr << "\n";
838 assert(0 && "Do not know how to expand the result of this operator!");
841 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
842 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
843 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
844 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
846 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
847 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
848 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
849 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
851 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
852 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
853 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
854 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
855 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
856 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
857 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
858 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
859 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
860 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
861 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
862 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
863 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
864 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
865 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
866 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
867 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
868 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
869 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
870 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
874 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
877 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
880 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
883 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
887 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
890 // If Lo/Hi is null, the sub-method took care of registering results etc.
892 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
895 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
896 /// and the shift amount is a constant 'Amt'. Expand the operation.
897 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
898 SDValue &Lo, SDValue &Hi) {
899 // Expand the incoming operand to be shifted, so that we have its parts
901 GetExpandedInteger(N->getOperand(0), InL, InH);
903 MVT NVT = InL.getValueType();
904 unsigned VTBits = N->getValueType(0).getSizeInBits();
905 unsigned NVTBits = NVT.getSizeInBits();
906 MVT ShTy = N->getOperand(1).getValueType();
908 if (N->getOpcode() == ISD::SHL) {
910 Lo = Hi = DAG.getConstant(0, NVT);
911 } else if (Amt > NVTBits) {
912 Lo = DAG.getConstant(0, NVT);
913 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
914 } else if (Amt == NVTBits) {
915 Lo = DAG.getConstant(0, NVT);
917 } else if (Amt == 1) {
918 // Emit this X << 1 as X+X.
919 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
920 SDValue LoOps[2] = { InL, InL };
921 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
922 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
923 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
925 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
926 Hi = DAG.getNode(ISD::OR, NVT,
927 DAG.getNode(ISD::SHL, NVT, InH,
928 DAG.getConstant(Amt, ShTy)),
929 DAG.getNode(ISD::SRL, NVT, InL,
930 DAG.getConstant(NVTBits-Amt, ShTy)));
935 if (N->getOpcode() == ISD::SRL) {
937 Lo = DAG.getConstant(0, NVT);
938 Hi = DAG.getConstant(0, NVT);
939 } else if (Amt > NVTBits) {
940 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
941 Hi = DAG.getConstant(0, NVT);
942 } else if (Amt == NVTBits) {
944 Hi = DAG.getConstant(0, NVT);
946 Lo = DAG.getNode(ISD::OR, NVT,
947 DAG.getNode(ISD::SRL, NVT, InL,
948 DAG.getConstant(Amt, ShTy)),
949 DAG.getNode(ISD::SHL, NVT, InH,
950 DAG.getConstant(NVTBits-Amt, ShTy)));
951 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
956 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
958 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
959 DAG.getConstant(NVTBits-1, ShTy));
960 } else if (Amt > NVTBits) {
961 Lo = DAG.getNode(ISD::SRA, NVT, InH,
962 DAG.getConstant(Amt-NVTBits, ShTy));
963 Hi = DAG.getNode(ISD::SRA, NVT, InH,
964 DAG.getConstant(NVTBits-1, ShTy));
965 } else if (Amt == NVTBits) {
967 Hi = DAG.getNode(ISD::SRA, NVT, InH,
968 DAG.getConstant(NVTBits-1, ShTy));
970 Lo = DAG.getNode(ISD::OR, NVT,
971 DAG.getNode(ISD::SRL, NVT, InL,
972 DAG.getConstant(Amt, ShTy)),
973 DAG.getNode(ISD::SHL, NVT, InH,
974 DAG.getConstant(NVTBits-Amt, ShTy)));
975 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
979 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
980 /// this shift based on knowledge of the high bit of the shift amount. If we
981 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
983 bool DAGTypeLegalizer::
984 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
985 SDValue Amt = N->getOperand(1);
986 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
987 MVT ShTy = Amt.getValueType();
988 unsigned ShBits = ShTy.getSizeInBits();
989 unsigned NVTBits = NVT.getSizeInBits();
990 assert(isPowerOf2_32(NVTBits) &&
991 "Expanded integer type size not a power of two!");
993 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
994 APInt KnownZero, KnownOne;
995 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
997 // If we don't know anything about the high bits, exit.
998 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1001 // Get the incoming operand to be shifted.
1003 GetExpandedInteger(N->getOperand(0), InL, InH);
1005 // If we know that any of the high bits of the shift amount are one, then we
1006 // can do this as a couple of simple shifts.
1007 if (KnownOne.intersects(HighBitMask)) {
1008 // Mask out the high bit, which we know is set.
1009 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1010 DAG.getConstant(~HighBitMask, ShTy));
1012 switch (N->getOpcode()) {
1013 default: assert(0 && "Unknown shift");
1015 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1016 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1019 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1020 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1023 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1024 DAG.getConstant(NVTBits-1, ShTy));
1025 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1030 // If we know that all of the high bits of the shift amount are zero, then we
1031 // can do this as a couple of simple shifts.
1032 if ((KnownZero & HighBitMask) == HighBitMask) {
1034 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1035 DAG.getConstant(NVTBits, ShTy),
1038 switch (N->getOpcode()) {
1039 default: assert(0 && "Unknown shift");
1040 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1042 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1045 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1046 Hi = DAG.getNode(ISD::OR, NVT,
1047 DAG.getNode(Op1, NVT, InH, Amt),
1048 DAG.getNode(Op2, NVT, InL, Amt2));
1055 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1056 SDValue &Lo, SDValue &Hi) {
1057 // Expand the subcomponents.
1058 SDValue LHSL, LHSH, RHSL, RHSH;
1059 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1060 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1061 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1062 SDValue LoOps[2] = { LHSL, RHSL };
1063 SDValue HiOps[3] = { LHSH, RHSH };
1065 if (N->getOpcode() == ISD::ADD) {
1066 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1067 HiOps[2] = Lo.getValue(1);
1068 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1070 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1071 HiOps[2] = Lo.getValue(1);
1072 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1076 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1077 SDValue &Lo, SDValue &Hi) {
1078 // Expand the subcomponents.
1079 SDValue LHSL, LHSH, RHSL, RHSH;
1080 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1081 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1082 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1083 SDValue LoOps[2] = { LHSL, RHSL };
1084 SDValue HiOps[3] = { LHSH, RHSH };
1086 if (N->getOpcode() == ISD::ADDC) {
1087 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1088 HiOps[2] = Lo.getValue(1);
1089 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1091 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1092 HiOps[2] = Lo.getValue(1);
1093 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1096 // Legalized the flag result - switch anything that used the old flag to
1098 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1101 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1102 SDValue &Lo, SDValue &Hi) {
1103 // Expand the subcomponents.
1104 SDValue LHSL, LHSH, RHSL, RHSH;
1105 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1106 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1107 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1108 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1109 SDValue HiOps[3] = { LHSH, RHSH };
1111 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1112 HiOps[2] = Lo.getValue(1);
1113 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1115 // Legalized the flag result - switch anything that used the old flag to
1117 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1120 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1121 SDValue &Lo, SDValue &Hi) {
1122 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1123 SDValue Op = N->getOperand(0);
1124 if (Op.getValueType().bitsLE(NVT)) {
1125 // The low part is any extension of the input (which degenerates to a copy).
1126 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1127 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1129 // For example, extension of an i48 to an i64. The operand type necessarily
1130 // promotes to the result type, so will end up being expanded too.
1131 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1132 "Only know how to promote this result!");
1133 SDValue Res = GetPromotedInteger(Op);
1134 assert(Res.getValueType() == N->getValueType(0) &&
1135 "Operand over promoted?");
1136 // Split the promoted operand. This will simplify when it is expanded.
1137 SplitInteger(Res, Lo, Hi);
1141 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1142 SDValue &Lo, SDValue &Hi) {
1143 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1144 MVT NVT = Lo.getValueType();
1145 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1146 unsigned NVTBits = NVT.getSizeInBits();
1147 unsigned EVTBits = EVT.getSizeInBits();
1149 if (NVTBits < EVTBits) {
1150 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1151 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1153 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1154 // The high part replicates the sign bit of Lo, make it explicit.
1155 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1156 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1160 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1161 SDValue &Lo, SDValue &Hi) {
1162 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1163 MVT NVT = Lo.getValueType();
1164 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1165 unsigned NVTBits = NVT.getSizeInBits();
1166 unsigned EVTBits = EVT.getSizeInBits();
1168 if (NVTBits < EVTBits) {
1169 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1170 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1172 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1173 // The high part must be zero, make it explicit.
1174 Hi = DAG.getConstant(0, NVT);
1178 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1179 SDValue &Lo, SDValue &Hi) {
1180 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1181 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1182 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1185 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1186 SDValue &Lo, SDValue &Hi) {
1187 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1188 unsigned NBitWidth = NVT.getSizeInBits();
1189 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1190 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1191 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1194 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1195 SDValue &Lo, SDValue &Hi) {
1196 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1197 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1198 MVT NVT = Lo.getValueType();
1200 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1201 DAG.getConstant(0, NVT), ISD::SETNE);
1203 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1204 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1206 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1207 DAG.getNode(ISD::ADD, NVT, LoLZ,
1208 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1209 Hi = DAG.getConstant(0, NVT);
1212 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1213 SDValue &Lo, SDValue &Hi) {
1214 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1215 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1216 MVT NVT = Lo.getValueType();
1217 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1218 DAG.getNode(ISD::CTPOP, NVT, Hi));
1219 Hi = DAG.getConstant(0, NVT);
1222 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1223 SDValue &Lo, SDValue &Hi) {
1224 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1225 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1226 MVT NVT = Lo.getValueType();
1228 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1229 DAG.getConstant(0, NVT), ISD::SETNE);
1231 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1232 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1234 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1235 DAG.getNode(ISD::ADD, NVT, HiLZ,
1236 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1237 Hi = DAG.getConstant(0, NVT);
1240 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1242 MVT VT = N->getValueType(0);
1243 SDValue Op = N->getOperand(0);
1244 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1245 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1246 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1249 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1251 MVT VT = N->getValueType(0);
1252 SDValue Op = N->getOperand(0);
1253 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1254 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1255 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1258 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1259 SDValue &Lo, SDValue &Hi) {
1260 if (ISD::isNormalLoad(N)) {
1261 ExpandRes_NormalLoad(N, Lo, Hi);
1265 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1267 MVT VT = N->getValueType(0);
1268 MVT NVT = TLI.getTypeToTransformTo(VT);
1269 SDValue Ch = N->getChain();
1270 SDValue Ptr = N->getBasePtr();
1271 ISD::LoadExtType ExtType = N->getExtensionType();
1272 int SVOffset = N->getSrcValueOffset();
1273 unsigned Alignment = N->getAlignment();
1274 bool isVolatile = N->isVolatile();
1276 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1278 if (N->getMemoryVT().bitsLE(NVT)) {
1279 MVT EVT = N->getMemoryVT();
1281 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1282 isVolatile, Alignment);
1284 // Remember the chain.
1285 Ch = Lo.getValue(1);
1287 if (ExtType == ISD::SEXTLOAD) {
1288 // The high part is obtained by SRA'ing all but one of the bits of the
1290 unsigned LoSize = Lo.getValueType().getSizeInBits();
1291 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1292 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1293 } else if (ExtType == ISD::ZEXTLOAD) {
1294 // The high part is just a zero.
1295 Hi = DAG.getConstant(0, NVT);
1297 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1298 // The high part is undefined.
1299 Hi = DAG.getNode(ISD::UNDEF, NVT);
1301 } else if (TLI.isLittleEndian()) {
1302 // Little-endian - low bits are at low addresses.
1303 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1304 isVolatile, Alignment);
1306 unsigned ExcessBits =
1307 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1308 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1310 // Increment the pointer to the other half.
1311 unsigned IncrementSize = NVT.getSizeInBits()/8;
1312 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1313 DAG.getIntPtrConstant(IncrementSize));
1314 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1315 SVOffset+IncrementSize, NEVT,
1316 isVolatile, MinAlign(Alignment, IncrementSize));
1318 // Build a factor node to remember that this load is independent of the
1320 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1323 // Big-endian - high bits are at low addresses. Favor aligned loads at
1324 // the cost of some bit-fiddling.
1325 MVT EVT = N->getMemoryVT();
1326 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1327 unsigned IncrementSize = NVT.getSizeInBits()/8;
1328 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1330 // Load both the high bits and maybe some of the low bits.
1331 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1332 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1333 isVolatile, Alignment);
1335 // Increment the pointer to the other half.
1336 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1337 DAG.getIntPtrConstant(IncrementSize));
1338 // Load the rest of the low bits.
1339 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1340 SVOffset+IncrementSize,
1341 MVT::getIntegerVT(ExcessBits),
1342 isVolatile, MinAlign(Alignment, IncrementSize));
1344 // Build a factor node to remember that this load is independent of the
1346 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1349 if (ExcessBits < NVT.getSizeInBits()) {
1350 // Transfer low bits from the bottom of Hi to the top of Lo.
1351 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1352 DAG.getNode(ISD::SHL, NVT, Hi,
1353 DAG.getConstant(ExcessBits,
1354 TLI.getShiftAmountTy())));
1355 // Move high bits to the right position in Hi.
1356 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1357 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1358 TLI.getShiftAmountTy()));
1362 // Legalized the chain result - switch anything that used the old chain to
1364 ReplaceValueWith(SDValue(N, 1), Ch);
1367 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1368 SDValue &Lo, SDValue &Hi) {
1369 SDValue LL, LH, RL, RH;
1370 GetExpandedInteger(N->getOperand(0), LL, LH);
1371 GetExpandedInteger(N->getOperand(1), RL, RH);
1372 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1373 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1376 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1377 SDValue &Lo, SDValue &Hi) {
1378 MVT VT = N->getValueType(0);
1379 MVT NVT = TLI.getTypeToTransformTo(VT);
1381 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1382 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1383 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1384 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1385 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1386 SDValue LL, LH, RL, RH;
1387 GetExpandedInteger(N->getOperand(0), LL, LH);
1388 GetExpandedInteger(N->getOperand(1), RL, RH);
1389 unsigned OuterBitSize = VT.getSizeInBits();
1390 unsigned InnerBitSize = NVT.getSizeInBits();
1391 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1392 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1394 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1395 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1396 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1397 // The inputs are both zero-extended.
1399 // We can emit a umul_lohi.
1400 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1401 Hi = SDValue(Lo.getNode(), 1);
1405 // We can emit a mulhu+mul.
1406 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1407 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1411 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1412 // The input values are both sign-extended.
1414 // We can emit a smul_lohi.
1415 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1416 Hi = SDValue(Lo.getNode(), 1);
1420 // We can emit a mulhs+mul.
1421 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1422 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1427 // Lo,Hi = umul LHS, RHS.
1428 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1429 DAG.getVTList(NVT, NVT), LL, RL);
1431 Hi = UMulLOHI.getValue(1);
1432 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1433 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1434 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1435 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1439 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1440 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1441 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1442 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1443 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1444 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1449 // If nothing else, we can make a libcall.
1450 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1452 LC = RTLIB::MUL_I32;
1453 else if (VT == MVT::i64)
1454 LC = RTLIB::MUL_I64;
1455 else if (VT == MVT::i128)
1456 LC = RTLIB::MUL_I128;
1457 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1459 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1460 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1463 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1464 SDValue &Lo, SDValue &Hi) {
1465 MVT VT = N->getValueType(0);
1467 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1469 LC = RTLIB::SDIV_I32;
1470 else if (VT == MVT::i64)
1471 LC = RTLIB::SDIV_I64;
1472 else if (VT == MVT::i128)
1473 LC = RTLIB::SDIV_I128;
1474 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1476 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1477 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1480 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1481 SDValue &Lo, SDValue &Hi) {
1482 MVT VT = N->getValueType(0);
1484 // If we can emit an efficient shift operation, do so now. Check to see if
1485 // the RHS is a constant.
1486 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1487 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1489 // If we can determine that the high bit of the shift is zero or one, even if
1490 // the low bits are variable, emit this shift in an optimized form.
1491 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1494 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1496 if (N->getOpcode() == ISD::SHL) {
1497 PartsOpc = ISD::SHL_PARTS;
1498 } else if (N->getOpcode() == ISD::SRL) {
1499 PartsOpc = ISD::SRL_PARTS;
1501 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1502 PartsOpc = ISD::SRA_PARTS;
1505 // Next check to see if the target supports this SHL_PARTS operation or if it
1506 // will custom expand it.
1507 MVT NVT = TLI.getTypeToTransformTo(VT);
1508 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1509 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1510 Action == TargetLowering::Custom) {
1511 // Expand the subcomponents.
1513 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1515 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1516 MVT VT = LHSL.getValueType();
1517 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1518 Hi = Lo.getValue(1);
1522 // Otherwise, emit a libcall.
1523 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1525 if (N->getOpcode() == ISD::SHL) {
1526 isSigned = false; /*sign irrelevant*/
1528 LC = RTLIB::SHL_I32;
1529 else if (VT == MVT::i64)
1530 LC = RTLIB::SHL_I64;
1531 else if (VT == MVT::i128)
1532 LC = RTLIB::SHL_I128;
1533 } else if (N->getOpcode() == ISD::SRL) {
1536 LC = RTLIB::SRL_I32;
1537 else if (VT == MVT::i64)
1538 LC = RTLIB::SRL_I64;
1539 else if (VT == MVT::i128)
1540 LC = RTLIB::SRL_I128;
1542 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1545 LC = RTLIB::SRA_I32;
1546 else if (VT == MVT::i64)
1547 LC = RTLIB::SRA_I64;
1548 else if (VT == MVT::i128)
1549 LC = RTLIB::SRA_I128;
1551 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1553 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1554 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1557 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1558 SDValue &Lo, SDValue &Hi) {
1559 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1560 SDValue Op = N->getOperand(0);
1561 if (Op.getValueType().bitsLE(NVT)) {
1562 // The low part is sign extension of the input (which degenerates to a copy).
1563 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1564 // The high part is obtained by SRA'ing all but one of the bits of low part.
1565 unsigned LoSize = NVT.getSizeInBits();
1566 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1567 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1569 // For example, extension of an i48 to an i64. The operand type necessarily
1570 // promotes to the result type, so will end up being expanded too.
1571 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1572 "Only know how to promote this result!");
1573 SDValue Res = GetPromotedInteger(Op);
1574 assert(Res.getValueType() == N->getValueType(0) &&
1575 "Operand over promoted?");
1576 // Split the promoted operand. This will simplify when it is expanded.
1577 SplitInteger(Res, Lo, Hi);
1578 unsigned ExcessBits =
1579 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1580 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1581 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1585 void DAGTypeLegalizer::
1586 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1587 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1588 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1590 if (EVT.bitsLE(Lo.getValueType())) {
1591 // sext_inreg the low part if needed.
1592 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1595 // The high part gets the sign extension from the lo-part. This handles
1596 // things like sextinreg V:i64 from i8.
1597 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1598 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1599 TLI.getShiftAmountTy()));
1601 // For example, extension of an i48 to an i64. Leave the low part alone,
1602 // sext_inreg the high part.
1603 unsigned ExcessBits =
1604 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1605 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1606 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1610 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1611 SDValue &Lo, SDValue &Hi) {
1612 MVT VT = N->getValueType(0);
1614 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1616 LC = RTLIB::SREM_I32;
1617 else if (VT == MVT::i64)
1618 LC = RTLIB::SREM_I64;
1619 else if (VT == MVT::i128)
1620 LC = RTLIB::SREM_I128;
1621 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1623 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1624 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1627 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1628 SDValue &Lo, SDValue &Hi) {
1629 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1630 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1631 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1632 DAG.getConstant(NVT.getSizeInBits(),
1633 TLI.getShiftAmountTy()));
1634 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1637 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1638 SDValue &Lo, SDValue &Hi) {
1639 MVT VT = N->getValueType(0);
1641 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1643 LC = RTLIB::UDIV_I32;
1644 else if (VT == MVT::i64)
1645 LC = RTLIB::UDIV_I64;
1646 else if (VT == MVT::i128)
1647 LC = RTLIB::UDIV_I128;
1648 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1650 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1651 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1654 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1655 SDValue &Lo, SDValue &Hi) {
1656 MVT VT = N->getValueType(0);
1658 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1660 LC = RTLIB::UREM_I32;
1661 else if (VT == MVT::i64)
1662 LC = RTLIB::UREM_I64;
1663 else if (VT == MVT::i128)
1664 LC = RTLIB::UREM_I128;
1665 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1667 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1668 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1671 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1672 SDValue &Lo, SDValue &Hi) {
1673 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1674 SDValue Op = N->getOperand(0);
1675 if (Op.getValueType().bitsLE(NVT)) {
1676 // The low part is zero extension of the input (which degenerates to a copy).
1677 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1678 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1680 // For example, extension of an i48 to an i64. The operand type necessarily
1681 // promotes to the result type, so will end up being expanded too.
1682 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1683 "Only know how to promote this result!");
1684 SDValue Res = GetPromotedInteger(Op);
1685 assert(Res.getValueType() == N->getValueType(0) &&
1686 "Operand over promoted?");
1687 // Split the promoted operand. This will simplify when it is expanded.
1688 SplitInteger(Res, Lo, Hi);
1689 unsigned ExcessBits =
1690 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1691 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1696 //===----------------------------------------------------------------------===//
1697 // Integer Operand Expansion
1698 //===----------------------------------------------------------------------===//
1700 /// ExpandIntegerOperand - This method is called when the specified operand of
1701 /// the specified node is found to need expansion. At this point, all of the
1702 /// result types of the node are known to be legal, but other operands of the
1703 /// node may need promotion or expansion as well as the specified one.
1704 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1705 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1706 SDValue Res = SDValue();
1708 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1709 == TargetLowering::Custom)
1710 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
1712 if (Res.getNode() == 0) {
1713 switch (N->getOpcode()) {
1716 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1717 N->dump(&DAG); cerr << "\n";
1719 assert(0 && "Do not know how to expand this operator's operand!");
1722 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1723 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1724 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1726 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1727 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1728 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1729 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1730 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1732 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1733 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1737 // If the result is null, the sub-method took care of registering results etc.
1738 if (!Res.getNode()) return false;
1739 // If the result is N, the sub-method updated N in place. Check to see if any
1740 // operands are new, and if so, mark them.
1741 if (Res.getNode() == N) {
1742 // Mark N as new and remark N and its operands. This allows us to correctly
1743 // revisit N if it needs another step of expansion and allows us to visit
1744 // any new operands to N.
1749 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1750 "Invalid operand expansion");
1752 ReplaceValueWith(SDValue(N, 0), Res);
1756 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1757 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1758 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1760 ISD::CondCode &CCCode) {
1761 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1762 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1763 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1765 MVT VT = NewLHS.getValueType();
1767 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1768 if (RHSLo == RHSHi) {
1769 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1770 if (RHSCST->isAllOnesValue()) {
1771 // Equality comparison to -1.
1772 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1779 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1780 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1781 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1782 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1786 // If this is a comparison of the sign bit, just look at the top part.
1788 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1789 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1790 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1796 // FIXME: This generated code sucks.
1797 ISD::CondCode LowCC;
1799 default: assert(0 && "Unknown integer setcc!");
1801 case ISD::SETULT: LowCC = ISD::SETULT; break;
1803 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1805 case ISD::SETULE: LowCC = ISD::SETULE; break;
1807 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1810 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1811 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1812 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1814 // NOTE: on targets without efficient SELECT of bools, we can always use
1815 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1816 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1818 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1819 false, DagCombineInfo);
1820 if (!Tmp1.getNode())
1821 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1822 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1823 CCCode, false, DagCombineInfo);
1824 if (!Tmp2.getNode())
1825 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1826 DAG.getCondCode(CCCode));
1828 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
1829 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
1830 if ((Tmp1C && Tmp1C->isNullValue()) ||
1831 (Tmp2C && Tmp2C->isNullValue() &&
1832 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1833 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1834 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1835 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1836 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1837 // low part is known false, returns high part.
1838 // For LE / GE, if high part is known false, ignore the low part.
1839 // For LT / GT, if high part is known true, ignore the low part.
1845 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1846 ISD::SETEQ, false, DagCombineInfo);
1847 if (!NewLHS.getNode())
1848 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1850 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1851 NewLHS, Tmp1, Tmp2);
1855 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1856 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1857 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1858 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1860 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1861 // against zero to select between true and false values.
1862 if (NewRHS.getNode() == 0) {
1863 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1864 CCCode = ISD::SETNE;
1867 // Update N to have the operands specified.
1868 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
1869 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1873 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1874 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1875 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1876 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1878 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1879 // against zero to select between true and false values.
1880 if (NewRHS.getNode() == 0) {
1881 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1882 CCCode = ISD::SETNE;
1885 // Update N to have the operands specified.
1886 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
1887 N->getOperand(2), N->getOperand(3),
1888 DAG.getCondCode(CCCode));
1891 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1892 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1893 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1894 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1896 // If ExpandSetCCOperands returned a scalar, use it.
1897 if (NewRHS.getNode() == 0) {
1898 assert(NewLHS.getValueType() == N->getValueType(0) &&
1899 "Unexpected setcc expansion!");
1903 // Otherwise, update N to have the operands specified.
1904 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
1905 DAG.getCondCode(CCCode));
1908 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
1909 SDValue Op = N->getOperand(0);
1910 MVT DstVT = N->getValueType(0);
1911 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
1912 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1913 "Don't know how to expand this SINT_TO_FP!");
1914 return MakeLibCall(LC, DstVT, &Op, 1, true);
1917 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
1918 if (ISD::isNormalStore(N))
1919 return ExpandOp_NormalStore(N, OpNo);
1921 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1922 assert(OpNo == 1 && "Can only expand the stored value so far");
1924 MVT VT = N->getOperand(1).getValueType();
1925 MVT NVT = TLI.getTypeToTransformTo(VT);
1926 SDValue Ch = N->getChain();
1927 SDValue Ptr = N->getBasePtr();
1928 int SVOffset = N->getSrcValueOffset();
1929 unsigned Alignment = N->getAlignment();
1930 bool isVolatile = N->isVolatile();
1933 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1935 if (N->getMemoryVT().bitsLE(NVT)) {
1936 GetExpandedInteger(N->getValue(), Lo, Hi);
1937 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1938 N->getMemoryVT(), isVolatile, Alignment);
1939 } else if (TLI.isLittleEndian()) {
1940 // Little-endian - low bits are at low addresses.
1941 GetExpandedInteger(N->getValue(), Lo, Hi);
1943 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1944 isVolatile, Alignment);
1946 unsigned ExcessBits =
1947 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1948 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1950 // Increment the pointer to the other half.
1951 unsigned IncrementSize = NVT.getSizeInBits()/8;
1952 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1953 DAG.getIntPtrConstant(IncrementSize));
1954 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1955 SVOffset+IncrementSize, NEVT,
1956 isVolatile, MinAlign(Alignment, IncrementSize));
1957 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1959 // Big-endian - high bits are at low addresses. Favor aligned stores at
1960 // the cost of some bit-fiddling.
1961 GetExpandedInteger(N->getValue(), Lo, Hi);
1963 MVT EVT = N->getMemoryVT();
1964 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1965 unsigned IncrementSize = NVT.getSizeInBits()/8;
1966 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1967 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
1969 if (ExcessBits < NVT.getSizeInBits()) {
1970 // Transfer high bits from the top of Lo to the bottom of Hi.
1971 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
1972 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1973 TLI.getShiftAmountTy()));
1974 Hi = DAG.getNode(ISD::OR, NVT, Hi,
1975 DAG.getNode(ISD::SRL, NVT, Lo,
1976 DAG.getConstant(ExcessBits,
1977 TLI.getShiftAmountTy())));
1980 // Store both the high bits and maybe some of the low bits.
1981 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1982 SVOffset, HiVT, isVolatile, Alignment);
1984 // Increment the pointer to the other half.
1985 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1986 DAG.getIntPtrConstant(IncrementSize));
1987 // Store the lowest ExcessBits bits in the second half.
1988 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
1989 SVOffset+IncrementSize,
1990 MVT::getIntegerVT(ExcessBits),
1991 isVolatile, MinAlign(Alignment, IncrementSize));
1992 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1996 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
1998 GetExpandedInteger(N->getOperand(0), InL, InH);
1999 // Just truncate the low part of the source.
2000 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2003 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2004 SDValue Op = N->getOperand(0);
2005 MVT SrcVT = Op.getValueType();
2006 MVT DstVT = N->getValueType(0);
2008 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2009 // Do a signed conversion then adjust the result.
2010 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2011 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2013 // The result of the signed conversion needs adjusting if the 'sign bit' of
2014 // the incoming integer was set. To handle this, we dynamically test to see
2015 // if it is set, and, if so, add a fudge factor.
2017 const uint64_t F32TwoE32 = 0x4F800000ULL;
2018 const uint64_t F32TwoE64 = 0x5F800000ULL;
2019 const uint64_t F32TwoE128 = 0x7F800000ULL;
2022 if (SrcVT == MVT::i32)
2023 FF = APInt(32, F32TwoE32);
2024 else if (SrcVT == MVT::i64)
2025 FF = APInt(32, F32TwoE64);
2026 else if (SrcVT == MVT::i128)
2027 FF = APInt(32, F32TwoE128);
2029 assert(false && "Unsupported UINT_TO_FP!");
2031 // Check whether the sign bit is set.
2033 GetExpandedInteger(Op, Lo, Hi);
2034 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2035 DAG.getConstant(0, Hi.getValueType()),
2038 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2039 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2040 TLI.getPointerTy());
2042 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2043 SDValue Zero = DAG.getIntPtrConstant(0);
2044 SDValue Four = DAG.getIntPtrConstant(4);
2045 if (TLI.isBigEndian()) std::swap(Zero, Four);
2046 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2048 unsigned Alignment =
2049 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2050 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2051 Alignment = std::min(Alignment, 4u);
2053 // Load the value out, extending it from f32 to the destination float type.
2054 // FIXME: Avoid the extend by constructing the right constant pool?
2055 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2056 FudgePtr, NULL, 0, MVT::f32,
2058 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2061 // Otherwise, use a libcall.
2062 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2063 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2064 "Don't know how to expand this UINT_TO_FP!");
2065 return MakeLibCall(LC, DstVT, &Op, 1, true);