1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Result = SDValue();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
65 case ISD::EXTRACT_VECTOR_ELT:
66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
80 case ISD::SIGN_EXTEND:
81 case ISD::ZERO_EXTEND:
82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
101 // If Result is null, the sub-method took care of registering the result.
102 if (Result.getNode())
103 SetPromotedInteger(SDValue(N, ResNo), Result);
106 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
107 // Sign-extend the new bits, and continue the assertion.
108 MVT OldVT = N->getValueType(0);
109 SDValue Op = GetPromotedInteger(N->getOperand(0));
110 return DAG.getNode(ISD::AssertSext, Op.getValueType(),
111 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
112 DAG.getValueType(OldVT)), N->getOperand(1));
115 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
116 // Zero the new bits, and continue the assertion.
117 MVT OldVT = N->getValueType(0);
118 SDValue Op = GetPromotedInteger(N->getOperand(0));
119 return DAG.getNode(ISD::AssertZext, Op.getValueType(),
120 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
123 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
124 SDValue InOp = N->getOperand(0);
125 MVT InVT = InOp.getValueType();
126 MVT NInVT = TLI.getTypeToTransformTo(InVT);
127 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
129 switch (getTypeAction(InVT)) {
131 assert(false && "Unknown type action!");
136 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
137 // The input promotes to the same size. Convert the promoted value.
138 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
141 // Promote the integer operand by hand.
142 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
146 case ScalarizeVector:
147 // Convert the element to an integer and promote it by hand.
148 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
149 BitConvertToInteger(GetScalarizedVector(InOp)));
151 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
152 // pieces of the input into integers and reassemble in the final type.
154 GetSplitVector(N->getOperand(0), Lo, Hi);
155 Lo = BitConvertToInteger(Lo);
156 Hi = BitConvertToInteger(Hi);
158 if (TLI.isBigEndian())
161 InOp = DAG.getNode(ISD::ANY_EXTEND,
162 MVT::getIntegerVT(OutVT.getSizeInBits()),
163 JoinIntegers(Lo, Hi));
164 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
167 // Otherwise, lower the bit-convert to a store/load from the stack, then
169 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
170 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
173 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
174 SDValue Op = GetPromotedInteger(N->getOperand(0));
175 MVT OVT = N->getValueType(0);
176 MVT NVT = Op.getValueType();
178 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
179 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
180 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
183 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
184 // The pair element type may be legal, or may not promote to the same type as
185 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
186 return DAG.getNode(ISD::ANY_EXTEND,
187 TLI.getTypeToTransformTo(N->getValueType(0)),
188 JoinIntegers(N->getOperand(0), N->getOperand(1)));
191 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
192 MVT VT = N->getValueType(0);
193 // Zero extend things like i1, sign extend everything else. It shouldn't
194 // matter in theory which one we pick, but this tends to give better code?
195 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
196 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
198 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
202 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
203 SDValue Op = GetPromotedInteger(N->getOperand(0));
204 MVT OVT = N->getValueType(0);
205 MVT NVT = Op.getValueType();
206 // Zero extend to the promoted type and do the count there.
207 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
208 // Subtract off the extra leading bits in the bigger type.
209 return DAG.getNode(ISD::SUB, NVT, Op,
210 DAG.getConstant(NVT.getSizeInBits() -
211 OVT.getSizeInBits(), NVT));
214 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
215 SDValue Op = GetPromotedInteger(N->getOperand(0));
216 MVT OVT = N->getValueType(0);
217 MVT NVT = Op.getValueType();
218 // Zero extend to the promoted type and do the count there.
219 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
222 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
223 SDValue Op = GetPromotedInteger(N->getOperand(0));
224 MVT OVT = N->getValueType(0);
225 MVT NVT = Op.getValueType();
226 // The count is the same in the promoted type except if the original
227 // value was zero. This can be handled by setting the bit just off
228 // the top of the original type.
229 APInt TopBit(NVT.getSizeInBits(), 0);
230 TopBit.set(OVT.getSizeInBits());
231 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
232 return DAG.getNode(ISD::CTTZ, NVT, Op);
235 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
236 MVT OldVT = N->getValueType(0);
237 SDValue OldVec = N->getOperand(0);
238 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
241 assert(!isTypeLegal(OldVec.getValueType()) &&
242 "Legal one-element vector of a type needing promotion!");
243 // It is tempting to follow GetScalarizedVector by a call to
244 // GetPromotedInteger, but this would be wrong because the
245 // scalarized value may not yet have been processed.
246 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
247 GetScalarizedVector(OldVec));
250 // Convert to a vector half as long with an element type of twice the width,
251 // for example <4 x i16> -> <2 x i32>.
252 assert(!(OldElts & 1) && "Odd length vectors not supported!");
253 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
254 assert(OldVT.isSimple() && NewVT.isSimple());
256 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
257 MVT::getVectorVT(NewVT, OldElts / 2),
260 // Extract the element at OldIdx / 2 from the new vector.
261 SDValue OldIdx = N->getOperand(1);
262 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
263 DAG.getConstant(1, TLI.getShiftAmountTy()));
264 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
266 // Select the appropriate half of the element: Lo if OldIdx was even,
269 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
270 DAG.getConstant(OldVT.getSizeInBits(),
271 TLI.getShiftAmountTy()));
272 if (TLI.isBigEndian())
275 SDValue Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
276 DAG.getConstant(1, TLI.getShiftAmountTy()));
277 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
280 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
281 unsigned NewOpc = N->getOpcode();
282 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
284 // If we're promoting a UINT to a larger size, check to see if the new node
285 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
286 // we can use that instead. This allows us to generate better code for
287 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
288 // legal, such as PowerPC.
289 if (N->getOpcode() == ISD::FP_TO_UINT) {
290 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
291 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
292 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
293 NewOpc = ISD::FP_TO_SINT;
296 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
299 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
300 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
302 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
303 SDValue Res = GetPromotedInteger(N->getOperand(0));
304 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
305 "Extension doesn't make sense!");
307 // If the result and operand types are the same after promotion, simplify
308 // to an in-register extension.
309 if (NVT == Res.getValueType()) {
310 // The high bits are not guaranteed to be anything. Insert an extend.
311 if (N->getOpcode() == ISD::SIGN_EXTEND)
312 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
313 DAG.getValueType(N->getOperand(0).getValueType()));
314 if (N->getOpcode() == ISD::ZERO_EXTEND)
315 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
316 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
321 // Otherwise, just extend the original operand all the way to the larger type.
322 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
325 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
326 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
327 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
328 ISD::LoadExtType ExtType =
329 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
330 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
331 N->getSrcValue(), N->getSrcValueOffset(),
332 N->getMemoryVT(), N->isVolatile(),
335 // Legalized the chain result - switch anything that used the old chain to
337 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
341 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
342 // Sign extend the input.
343 SDValue LHS = GetPromotedInteger(N->getOperand(0));
344 SDValue RHS = GetPromotedInteger(N->getOperand(1));
345 MVT VT = N->getValueType(0);
346 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
347 DAG.getValueType(VT));
348 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
349 DAG.getValueType(VT));
351 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
354 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
355 SDValue LHS = GetPromotedInteger(N->getOperand(1));
356 SDValue RHS = GetPromotedInteger(N->getOperand(2));
357 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
360 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
361 SDValue LHS = GetPromotedInteger(N->getOperand(2));
362 SDValue RHS = GetPromotedInteger(N->getOperand(3));
363 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
364 N->getOperand(1), LHS, RHS, N->getOperand(4));
367 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
368 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
369 MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
370 assert(isTypeLegal(SVT) && "SetCC type not legal??");
371 assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
372 "Integer type overpromoted?");
373 return DAG.getNode(ISD::TRUNCATE, NVT,
374 DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
375 N->getOperand(1), N->getOperand(2)));
378 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
379 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
380 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
383 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
384 SDValue Op = GetPromotedInteger(N->getOperand(0));
385 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
389 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
390 // The input may have strange things in the top bits of the registers, but
391 // these operations don't care. They may have weird bits going out, but
392 // that too is okay if they are integer operations.
393 SDValue LHS = GetPromotedInteger(N->getOperand(0));
394 SDValue RHS = GetPromotedInteger(N->getOperand(1));
395 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
398 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
399 // The input value must be properly sign extended.
400 MVT VT = N->getValueType(0);
401 MVT NVT = TLI.getTypeToTransformTo(VT);
402 SDValue Res = GetPromotedInteger(N->getOperand(0));
403 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
404 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
407 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
408 // The input value must be properly zero extended.
409 MVT VT = N->getValueType(0);
410 MVT NVT = TLI.getTypeToTransformTo(VT);
411 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
412 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
415 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
418 switch (getTypeAction(N->getOperand(0).getValueType())) {
419 default: assert(0 && "Unknown type action!");
422 Res = N->getOperand(0);
425 Res = GetPromotedInteger(N->getOperand(0));
429 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
430 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
431 "Truncation doesn't make sense!");
432 if (Res.getValueType() == NVT)
435 // Truncate to NVT instead of VT
436 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
439 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
440 // Zero extend the input.
441 SDValue LHS = GetPromotedInteger(N->getOperand(0));
442 SDValue RHS = GetPromotedInteger(N->getOperand(1));
443 MVT VT = N->getValueType(0);
444 LHS = DAG.getZeroExtendInReg(LHS, VT);
445 RHS = DAG.getZeroExtendInReg(RHS, VT);
447 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
450 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
451 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
454 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
455 SDValue Chain = N->getOperand(0); // Get the chain.
456 SDValue Ptr = N->getOperand(1); // Get the pointer.
457 MVT VT = N->getValueType(0);
459 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
460 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
462 // Increment the arg pointer, VAList, to the next vaarg
463 // FIXME: should the ABI size be used for the increment? Think of
464 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
465 // integers of unusual size (such MVT::i1, which gives an increment
467 unsigned Increment = VT.getSizeInBits() / 8;
468 SDValue Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
469 DAG.getConstant(Increment, TLI.getPointerTy()));
471 // Store the incremented VAList to the pointer.
472 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
474 // Load the actual argument out of the arg pointer VAList.
475 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
476 VAList, NULL, 0, VT);
478 // Legalized the chain result - switch anything that used the old chain to
480 ReplaceValueWith(SDValue(N, 1), Tmp.getValue(1));
485 //===----------------------------------------------------------------------===//
486 // Integer Operand Promotion
487 //===----------------------------------------------------------------------===//
489 /// PromoteIntegerOperand - This method is called when the specified operand of
490 /// the specified node is found to need promotion. At this point, all of the
491 /// result types of the node are known to be legal, but other operands of the
492 /// node may need promotion or expansion as well as the specified one.
493 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
494 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
495 SDValue Res = SDValue();
497 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
498 == TargetLowering::Custom)
499 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
501 if (Res.getNode() == 0) {
502 switch (N->getOpcode()) {
505 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
506 N->dump(&DAG); cerr << "\n";
508 assert(0 && "Do not know how to promote this operator's operand!");
511 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
512 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
513 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
514 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
515 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
516 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
517 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
518 case ISD::INSERT_VECTOR_ELT:
519 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
520 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
521 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
522 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
523 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
524 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
525 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
527 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
528 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
530 case ISD::SINT_TO_FP:
531 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
535 // If the result is null, the sub-method took care of registering results etc.
536 if (!Res.getNode()) return false;
537 // If the result is N, the sub-method updated N in place.
538 if (Res.getNode() == N) {
539 // Mark N as new and remark N and its operands. This allows us to correctly
540 // revisit N if it needs another step of promotion and allows us to visit
541 // any new operands to N.
546 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
547 "Invalid operand expansion");
549 ReplaceValueWith(SDValue(N, 0), Res);
553 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
554 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
555 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
556 ISD::CondCode CCCode) {
557 MVT VT = NewLHS.getValueType();
559 // Get the promoted values.
560 NewLHS = GetPromotedInteger(NewLHS);
561 NewRHS = GetPromotedInteger(NewRHS);
563 // Otherwise, we have to insert explicit sign or zero extends. Note
564 // that we could insert sign extends for ALL conditions, but zero extend
565 // is cheaper on many machines (an AND instead of two shifts), so prefer
568 default: assert(0 && "Unknown integer comparison!");
575 // ALL of these operations will work if we either sign or zero extend
576 // the operands (including the unsigned comparisons!). Zero extend is
577 // usually a simpler/cheaper operation, so prefer it.
578 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
579 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
585 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
586 DAG.getValueType(VT));
587 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
588 DAG.getValueType(VT));
593 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
594 SDValue Op = GetPromotedInteger(N->getOperand(0));
595 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
598 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
599 assert(OpNo == 2 && "Don't know how to promote this operand!");
601 SDValue LHS = N->getOperand(2);
602 SDValue RHS = N->getOperand(3);
603 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
605 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
607 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
608 N->getOperand(1), LHS, RHS, N->getOperand(4));
611 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
612 assert(OpNo == 1 && "only know how to promote condition");
613 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
615 // The top bits of the promoted condition are not necessarily zero, ensure
616 // that the value is properly zero extended.
617 unsigned BitWidth = Cond.getValueSizeInBits();
618 if (!DAG.MaskedValueIsZero(Cond,
619 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
620 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
622 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
623 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
627 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
628 // Since the result type is legal, the operands must promote to it.
629 MVT OVT = N->getOperand(0).getValueType();
630 SDValue Lo = GetPromotedInteger(N->getOperand(0));
631 SDValue Hi = GetPromotedInteger(N->getOperand(1));
632 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
634 Lo = DAG.getZeroExtendInReg(Lo, OVT);
635 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
636 DAG.getConstant(OVT.getSizeInBits(),
637 TLI.getShiftAmountTy()));
638 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
641 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
642 // The vector type is legal but the element type is not. This implies
643 // that the vector is a power-of-two in length and that the element
644 // type does not have a strange size (eg: it is not i1).
645 MVT VecVT = N->getValueType(0);
646 unsigned NumElts = VecVT.getVectorNumElements();
647 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
649 // Build a vector of half the length out of elements of twice the bitwidth.
650 // For example <4 x i16> -> <2 x i32>.
651 MVT OldVT = N->getOperand(0).getValueType();
652 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
653 assert(OldVT.isSimple() && NewVT.isSimple());
655 std::vector<SDValue> NewElts;
656 NewElts.reserve(NumElts/2);
658 for (unsigned i = 0; i < NumElts; i += 2) {
659 // Combine two successive elements into one promoted element.
660 SDValue Lo = N->getOperand(i);
661 SDValue Hi = N->getOperand(i+1);
662 if (TLI.isBigEndian())
664 NewElts.push_back(JoinIntegers(Lo, Hi));
667 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
668 MVT::getVectorVT(NewVT, NewElts.size()),
669 &NewElts[0], NewElts.size());
671 // Convert the new vector to the old vector type.
672 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
675 SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
676 SDValue Op = GetPromotedInteger(N->getOperand(0));
677 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
680 SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
681 SDValue Op = GetPromotedInteger(N->getOperand(0));
682 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
683 DAG.getIntPtrConstant(0));
686 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
689 // Promote the inserted value. This is valid because the type does not
690 // have to match the vector element type.
692 // Check that any extra bits introduced will be truncated away.
693 assert(N->getOperand(1).getValueType().getSizeInBits() >=
694 N->getValueType(0).getVectorElementType().getSizeInBits() &&
695 "Type of inserted value narrower than vector element type!");
696 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
697 GetPromotedInteger(N->getOperand(1)),
701 assert(OpNo == 2 && "Different operand and result vector types?");
703 // Promote the index.
704 SDValue Idx = N->getOperand(2);
705 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
706 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
707 N->getOperand(1), Idx);
710 SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
711 SDValue In = GetPromotedInteger(N->getOperand(0));
712 MVT OpVT = N->getOperand(0).getValueType();
713 if (N->getOpcode() == ISD::UINT_TO_FP)
714 In = DAG.getZeroExtendInReg(In, OpVT);
716 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
717 In, DAG.getValueType(OpVT));
719 return DAG.UpdateNodeOperands(SDValue(N, 0), In);
722 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
724 NewOps[0] = N->getOperand(0);
725 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
726 SDValue Flag = GetPromotedInteger(N->getOperand(i));
727 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
729 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
730 array_lengthof(NewOps));
733 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
734 assert(OpNo == 0 && "Only know how to promote condition");
735 SDValue Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
737 // The top bits of the promoted condition are not necessarily zero, ensure
738 // that the value is properly zero extended.
739 unsigned BitWidth = Cond.getValueSizeInBits();
740 if (!DAG.MaskedValueIsZero(Cond,
741 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
742 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
744 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
745 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, N->getOperand(1),
749 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
750 assert(OpNo == 0 && "Don't know how to promote this operand!");
752 SDValue LHS = N->getOperand(0);
753 SDValue RHS = N->getOperand(1);
754 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
756 // The CC (#4) and the possible return values (#2 and #3) have legal types.
757 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
758 N->getOperand(3), N->getOperand(4));
761 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
762 assert(OpNo == 0 && "Don't know how to promote this operand!");
764 SDValue LHS = N->getOperand(0);
765 SDValue RHS = N->getOperand(1);
766 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
768 // The CC (#2) is always legal.
769 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
772 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
773 SDValue Op = GetPromotedInteger(N->getOperand(0));
774 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
775 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
776 Op, DAG.getValueType(N->getOperand(0).getValueType()));
779 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
780 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
781 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
782 int SVOffset = N->getSrcValueOffset();
783 unsigned Alignment = N->getAlignment();
784 bool isVolatile = N->isVolatile();
786 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
788 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
790 // Truncate the value and store the result.
791 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
792 SVOffset, N->getMemoryVT(),
793 isVolatile, Alignment);
796 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
797 SDValue Op = GetPromotedInteger(N->getOperand(0));
798 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
801 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
802 SDValue Op = GetPromotedInteger(N->getOperand(0));
803 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
804 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
808 //===----------------------------------------------------------------------===//
809 // Integer Result Expansion
810 //===----------------------------------------------------------------------===//
812 /// ExpandIntegerResult - This method is called when the specified result of the
813 /// specified node is found to need expansion. At this point, the node may also
814 /// have invalid operands or may have other results that need promotion, we just
815 /// know that (at least) one result needs expansion.
816 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
817 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
821 // See if the target wants to custom expand this node.
822 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
823 TargetLowering::Custom) {
824 // If the target wants to, allow it to lower this itself.
825 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
826 // Everything that once used N now uses P. We are guaranteed that the
827 // result value types of N and the result value types of P match.
828 ReplaceNodeWith(N, P);
833 switch (N->getOpcode()) {
836 cerr << "ExpandIntegerResult #" << ResNo << ": ";
837 N->dump(&DAG); cerr << "\n";
839 assert(0 && "Do not know how to expand the result of this operator!");
842 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
843 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
844 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
845 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
847 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
848 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
849 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
850 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
852 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
853 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
854 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
855 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
856 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
857 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
858 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
859 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
860 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
861 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
862 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
863 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
864 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
865 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
866 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
867 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
868 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
869 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
870 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
871 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
875 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
878 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
881 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
884 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
888 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
891 // If Lo/Hi is null, the sub-method took care of registering results etc.
893 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
896 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
897 /// and the shift amount is a constant 'Amt'. Expand the operation.
898 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
899 SDValue &Lo, SDValue &Hi) {
900 // Expand the incoming operand to be shifted, so that we have its parts
902 GetExpandedInteger(N->getOperand(0), InL, InH);
904 MVT NVT = InL.getValueType();
905 unsigned VTBits = N->getValueType(0).getSizeInBits();
906 unsigned NVTBits = NVT.getSizeInBits();
907 MVT ShTy = N->getOperand(1).getValueType();
909 if (N->getOpcode() == ISD::SHL) {
911 Lo = Hi = DAG.getConstant(0, NVT);
912 } else if (Amt > NVTBits) {
913 Lo = DAG.getConstant(0, NVT);
914 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
915 } else if (Amt == NVTBits) {
916 Lo = DAG.getConstant(0, NVT);
918 } else if (Amt == 1) {
919 // Emit this X << 1 as X+X.
920 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
921 SDValue LoOps[2] = { InL, InL };
922 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
923 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
924 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
926 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
927 Hi = DAG.getNode(ISD::OR, NVT,
928 DAG.getNode(ISD::SHL, NVT, InH,
929 DAG.getConstant(Amt, ShTy)),
930 DAG.getNode(ISD::SRL, NVT, InL,
931 DAG.getConstant(NVTBits-Amt, ShTy)));
936 if (N->getOpcode() == ISD::SRL) {
938 Lo = DAG.getConstant(0, NVT);
939 Hi = DAG.getConstant(0, NVT);
940 } else if (Amt > NVTBits) {
941 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
942 Hi = DAG.getConstant(0, NVT);
943 } else if (Amt == NVTBits) {
945 Hi = DAG.getConstant(0, NVT);
947 Lo = DAG.getNode(ISD::OR, NVT,
948 DAG.getNode(ISD::SRL, NVT, InL,
949 DAG.getConstant(Amt, ShTy)),
950 DAG.getNode(ISD::SHL, NVT, InH,
951 DAG.getConstant(NVTBits-Amt, ShTy)));
952 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
957 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
959 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
960 DAG.getConstant(NVTBits-1, ShTy));
961 } else if (Amt > NVTBits) {
962 Lo = DAG.getNode(ISD::SRA, NVT, InH,
963 DAG.getConstant(Amt-NVTBits, ShTy));
964 Hi = DAG.getNode(ISD::SRA, NVT, InH,
965 DAG.getConstant(NVTBits-1, ShTy));
966 } else if (Amt == NVTBits) {
968 Hi = DAG.getNode(ISD::SRA, NVT, InH,
969 DAG.getConstant(NVTBits-1, ShTy));
971 Lo = DAG.getNode(ISD::OR, NVT,
972 DAG.getNode(ISD::SRL, NVT, InL,
973 DAG.getConstant(Amt, ShTy)),
974 DAG.getNode(ISD::SHL, NVT, InH,
975 DAG.getConstant(NVTBits-Amt, ShTy)));
976 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
980 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
981 /// this shift based on knowledge of the high bit of the shift amount. If we
982 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
984 bool DAGTypeLegalizer::
985 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
986 SDValue Amt = N->getOperand(1);
987 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
988 MVT ShTy = Amt.getValueType();
989 unsigned ShBits = ShTy.getSizeInBits();
990 unsigned NVTBits = NVT.getSizeInBits();
991 assert(isPowerOf2_32(NVTBits) &&
992 "Expanded integer type size not a power of two!");
994 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
995 APInt KnownZero, KnownOne;
996 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
998 // If we don't know anything about the high bits, exit.
999 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1002 // Get the incoming operand to be shifted.
1004 GetExpandedInteger(N->getOperand(0), InL, InH);
1006 // If we know that any of the high bits of the shift amount are one, then we
1007 // can do this as a couple of simple shifts.
1008 if (KnownOne.intersects(HighBitMask)) {
1009 // Mask out the high bit, which we know is set.
1010 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1011 DAG.getConstant(~HighBitMask, ShTy));
1013 switch (N->getOpcode()) {
1014 default: assert(0 && "Unknown shift");
1016 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1017 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1020 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1021 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1024 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1025 DAG.getConstant(NVTBits-1, ShTy));
1026 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1031 // If we know that all of the high bits of the shift amount are zero, then we
1032 // can do this as a couple of simple shifts.
1033 if ((KnownZero & HighBitMask) == HighBitMask) {
1035 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1036 DAG.getConstant(NVTBits, ShTy),
1039 switch (N->getOpcode()) {
1040 default: assert(0 && "Unknown shift");
1041 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1043 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1046 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1047 Hi = DAG.getNode(ISD::OR, NVT,
1048 DAG.getNode(Op1, NVT, InH, Amt),
1049 DAG.getNode(Op2, NVT, InL, Amt2));
1056 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1057 SDValue &Lo, SDValue &Hi) {
1058 // Expand the subcomponents.
1059 SDValue LHSL, LHSH, RHSL, RHSH;
1060 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1061 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1062 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1063 SDValue LoOps[2] = { LHSL, RHSL };
1064 SDValue HiOps[3] = { LHSH, RHSH };
1066 if (N->getOpcode() == ISD::ADD) {
1067 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1068 HiOps[2] = Lo.getValue(1);
1069 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1071 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1072 HiOps[2] = Lo.getValue(1);
1073 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1077 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1078 SDValue &Lo, SDValue &Hi) {
1079 // Expand the subcomponents.
1080 SDValue LHSL, LHSH, RHSL, RHSH;
1081 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1082 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1083 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1084 SDValue LoOps[2] = { LHSL, RHSL };
1085 SDValue HiOps[3] = { LHSH, RHSH };
1087 if (N->getOpcode() == ISD::ADDC) {
1088 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1089 HiOps[2] = Lo.getValue(1);
1090 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1092 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1093 HiOps[2] = Lo.getValue(1);
1094 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1097 // Legalized the flag result - switch anything that used the old flag to
1099 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1102 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1103 SDValue &Lo, SDValue &Hi) {
1104 // Expand the subcomponents.
1105 SDValue LHSL, LHSH, RHSL, RHSH;
1106 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1107 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1108 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1109 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1110 SDValue HiOps[3] = { LHSH, RHSH };
1112 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1113 HiOps[2] = Lo.getValue(1);
1114 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1116 // Legalized the flag result - switch anything that used the old flag to
1118 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1121 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1122 SDValue &Lo, SDValue &Hi) {
1123 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1124 SDValue Op = N->getOperand(0);
1125 if (Op.getValueType().bitsLE(NVT)) {
1126 // The low part is any extension of the input (which degenerates to a copy).
1127 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1128 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1130 // For example, extension of an i48 to an i64. The operand type necessarily
1131 // promotes to the result type, so will end up being expanded too.
1132 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1133 "Only know how to promote this result!");
1134 SDValue Res = GetPromotedInteger(Op);
1135 assert(Res.getValueType() == N->getValueType(0) &&
1136 "Operand over promoted?");
1137 // Split the promoted operand. This will simplify when it is expanded.
1138 SplitInteger(Res, Lo, Hi);
1142 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1143 SDValue &Lo, SDValue &Hi) {
1144 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1145 MVT NVT = Lo.getValueType();
1146 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1147 unsigned NVTBits = NVT.getSizeInBits();
1148 unsigned EVTBits = EVT.getSizeInBits();
1150 if (NVTBits < EVTBits) {
1151 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1152 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1154 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1155 // The high part replicates the sign bit of Lo, make it explicit.
1156 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1157 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1161 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1162 SDValue &Lo, SDValue &Hi) {
1163 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1164 MVT NVT = Lo.getValueType();
1165 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1166 unsigned NVTBits = NVT.getSizeInBits();
1167 unsigned EVTBits = EVT.getSizeInBits();
1169 if (NVTBits < EVTBits) {
1170 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1171 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1173 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1174 // The high part must be zero, make it explicit.
1175 Hi = DAG.getConstant(0, NVT);
1179 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1180 SDValue &Lo, SDValue &Hi) {
1181 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1182 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1183 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1186 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1187 SDValue &Lo, SDValue &Hi) {
1188 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1189 unsigned NBitWidth = NVT.getSizeInBits();
1190 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1191 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1192 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1195 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1196 SDValue &Lo, SDValue &Hi) {
1197 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1198 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1199 MVT NVT = Lo.getValueType();
1201 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1202 DAG.getConstant(0, NVT), ISD::SETNE);
1204 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1205 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1207 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1208 DAG.getNode(ISD::ADD, NVT, LoLZ,
1209 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1210 Hi = DAG.getConstant(0, NVT);
1213 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1214 SDValue &Lo, SDValue &Hi) {
1215 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1216 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1217 MVT NVT = Lo.getValueType();
1218 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1219 DAG.getNode(ISD::CTPOP, NVT, Hi));
1220 Hi = DAG.getConstant(0, NVT);
1223 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1224 SDValue &Lo, SDValue &Hi) {
1225 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1226 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1227 MVT NVT = Lo.getValueType();
1229 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1230 DAG.getConstant(0, NVT), ISD::SETNE);
1232 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1233 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1235 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1236 DAG.getNode(ISD::ADD, NVT, HiLZ,
1237 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1238 Hi = DAG.getConstant(0, NVT);
1241 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1243 MVT VT = N->getValueType(0);
1244 SDValue Op = N->getOperand(0);
1245 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1246 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1247 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1250 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1252 MVT VT = N->getValueType(0);
1253 SDValue Op = N->getOperand(0);
1254 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1255 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1256 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1259 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1260 SDValue &Lo, SDValue &Hi) {
1261 if (ISD::isNormalLoad(N)) {
1262 ExpandRes_NormalLoad(N, Lo, Hi);
1266 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1268 MVT VT = N->getValueType(0);
1269 MVT NVT = TLI.getTypeToTransformTo(VT);
1270 SDValue Ch = N->getChain();
1271 SDValue Ptr = N->getBasePtr();
1272 ISD::LoadExtType ExtType = N->getExtensionType();
1273 int SVOffset = N->getSrcValueOffset();
1274 unsigned Alignment = N->getAlignment();
1275 bool isVolatile = N->isVolatile();
1277 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1279 if (N->getMemoryVT().bitsLE(NVT)) {
1280 MVT EVT = N->getMemoryVT();
1282 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1283 isVolatile, Alignment);
1285 // Remember the chain.
1286 Ch = Lo.getValue(1);
1288 if (ExtType == ISD::SEXTLOAD) {
1289 // The high part is obtained by SRA'ing all but one of the bits of the
1291 unsigned LoSize = Lo.getValueType().getSizeInBits();
1292 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1293 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1294 } else if (ExtType == ISD::ZEXTLOAD) {
1295 // The high part is just a zero.
1296 Hi = DAG.getConstant(0, NVT);
1298 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1299 // The high part is undefined.
1300 Hi = DAG.getNode(ISD::UNDEF, NVT);
1302 } else if (TLI.isLittleEndian()) {
1303 // Little-endian - low bits are at low addresses.
1304 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1305 isVolatile, Alignment);
1307 unsigned ExcessBits =
1308 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1309 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1311 // Increment the pointer to the other half.
1312 unsigned IncrementSize = NVT.getSizeInBits()/8;
1313 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1314 DAG.getIntPtrConstant(IncrementSize));
1315 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1316 SVOffset+IncrementSize, NEVT,
1317 isVolatile, MinAlign(Alignment, IncrementSize));
1319 // Build a factor node to remember that this load is independent of the
1321 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1324 // Big-endian - high bits are at low addresses. Favor aligned loads at
1325 // the cost of some bit-fiddling.
1326 MVT EVT = N->getMemoryVT();
1327 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1328 unsigned IncrementSize = NVT.getSizeInBits()/8;
1329 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1331 // Load both the high bits and maybe some of the low bits.
1332 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1333 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1334 isVolatile, Alignment);
1336 // Increment the pointer to the other half.
1337 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1338 DAG.getIntPtrConstant(IncrementSize));
1339 // Load the rest of the low bits.
1340 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1341 SVOffset+IncrementSize,
1342 MVT::getIntegerVT(ExcessBits),
1343 isVolatile, MinAlign(Alignment, IncrementSize));
1345 // Build a factor node to remember that this load is independent of the
1347 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1350 if (ExcessBits < NVT.getSizeInBits()) {
1351 // Transfer low bits from the bottom of Hi to the top of Lo.
1352 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1353 DAG.getNode(ISD::SHL, NVT, Hi,
1354 DAG.getConstant(ExcessBits,
1355 TLI.getShiftAmountTy())));
1356 // Move high bits to the right position in Hi.
1357 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1358 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1359 TLI.getShiftAmountTy()));
1363 // Legalized the chain result - switch anything that used the old chain to
1365 ReplaceValueWith(SDValue(N, 1), Ch);
1368 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1369 SDValue &Lo, SDValue &Hi) {
1370 SDValue LL, LH, RL, RH;
1371 GetExpandedInteger(N->getOperand(0), LL, LH);
1372 GetExpandedInteger(N->getOperand(1), RL, RH);
1373 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1374 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1377 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1378 SDValue &Lo, SDValue &Hi) {
1379 MVT VT = N->getValueType(0);
1380 MVT NVT = TLI.getTypeToTransformTo(VT);
1382 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1383 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1384 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1385 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1386 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1387 SDValue LL, LH, RL, RH;
1388 GetExpandedInteger(N->getOperand(0), LL, LH);
1389 GetExpandedInteger(N->getOperand(1), RL, RH);
1390 unsigned OuterBitSize = VT.getSizeInBits();
1391 unsigned InnerBitSize = NVT.getSizeInBits();
1392 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1393 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1395 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1396 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1397 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1398 // The inputs are both zero-extended.
1400 // We can emit a umul_lohi.
1401 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1402 Hi = SDValue(Lo.getNode(), 1);
1406 // We can emit a mulhu+mul.
1407 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1408 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1412 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1413 // The input values are both sign-extended.
1415 // We can emit a smul_lohi.
1416 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1417 Hi = SDValue(Lo.getNode(), 1);
1421 // We can emit a mulhs+mul.
1422 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1423 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1428 // Lo,Hi = umul LHS, RHS.
1429 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1430 DAG.getVTList(NVT, NVT), LL, RL);
1432 Hi = UMulLOHI.getValue(1);
1433 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1434 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1435 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1436 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1440 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1441 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1442 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1443 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1444 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1445 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1450 // If nothing else, we can make a libcall.
1451 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1453 LC = RTLIB::MUL_I32;
1454 else if (VT == MVT::i64)
1455 LC = RTLIB::MUL_I64;
1456 else if (VT == MVT::i128)
1457 LC = RTLIB::MUL_I128;
1458 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1460 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1461 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1464 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1465 SDValue &Lo, SDValue &Hi) {
1466 MVT VT = N->getValueType(0);
1468 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1470 LC = RTLIB::SDIV_I32;
1471 else if (VT == MVT::i64)
1472 LC = RTLIB::SDIV_I64;
1473 else if (VT == MVT::i128)
1474 LC = RTLIB::SDIV_I128;
1475 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1477 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1478 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1481 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1482 SDValue &Lo, SDValue &Hi) {
1483 MVT VT = N->getValueType(0);
1485 // If we can emit an efficient shift operation, do so now. Check to see if
1486 // the RHS is a constant.
1487 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1488 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1490 // If we can determine that the high bit of the shift is zero or one, even if
1491 // the low bits are variable, emit this shift in an optimized form.
1492 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1495 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1497 if (N->getOpcode() == ISD::SHL) {
1498 PartsOpc = ISD::SHL_PARTS;
1499 } else if (N->getOpcode() == ISD::SRL) {
1500 PartsOpc = ISD::SRL_PARTS;
1502 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1503 PartsOpc = ISD::SRA_PARTS;
1506 // Next check to see if the target supports this SHL_PARTS operation or if it
1507 // will custom expand it.
1508 MVT NVT = TLI.getTypeToTransformTo(VT);
1509 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1510 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1511 Action == TargetLowering::Custom) {
1512 // Expand the subcomponents.
1514 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1516 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1517 MVT VT = LHSL.getValueType();
1518 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1519 Hi = Lo.getValue(1);
1523 // Otherwise, emit a libcall.
1524 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1526 if (N->getOpcode() == ISD::SHL) {
1527 isSigned = false; /*sign irrelevant*/
1529 LC = RTLIB::SHL_I32;
1530 else if (VT == MVT::i64)
1531 LC = RTLIB::SHL_I64;
1532 else if (VT == MVT::i128)
1533 LC = RTLIB::SHL_I128;
1534 } else if (N->getOpcode() == ISD::SRL) {
1537 LC = RTLIB::SRL_I32;
1538 else if (VT == MVT::i64)
1539 LC = RTLIB::SRL_I64;
1540 else if (VT == MVT::i128)
1541 LC = RTLIB::SRL_I128;
1543 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1546 LC = RTLIB::SRA_I32;
1547 else if (VT == MVT::i64)
1548 LC = RTLIB::SRA_I64;
1549 else if (VT == MVT::i128)
1550 LC = RTLIB::SRA_I128;
1552 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1554 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1555 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1558 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1559 SDValue &Lo, SDValue &Hi) {
1560 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1561 SDValue Op = N->getOperand(0);
1562 if (Op.getValueType().bitsLE(NVT)) {
1563 // The low part is sign extension of the input (which degenerates to a copy).
1564 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1565 // The high part is obtained by SRA'ing all but one of the bits of low part.
1566 unsigned LoSize = NVT.getSizeInBits();
1567 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1568 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1570 // For example, extension of an i48 to an i64. The operand type necessarily
1571 // promotes to the result type, so will end up being expanded too.
1572 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1573 "Only know how to promote this result!");
1574 SDValue Res = GetPromotedInteger(Op);
1575 assert(Res.getValueType() == N->getValueType(0) &&
1576 "Operand over promoted?");
1577 // Split the promoted operand. This will simplify when it is expanded.
1578 SplitInteger(Res, Lo, Hi);
1579 unsigned ExcessBits =
1580 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1581 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1582 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1586 void DAGTypeLegalizer::
1587 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1588 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1589 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1591 if (EVT.bitsLE(Lo.getValueType())) {
1592 // sext_inreg the low part if needed.
1593 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1596 // The high part gets the sign extension from the lo-part. This handles
1597 // things like sextinreg V:i64 from i8.
1598 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1599 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1600 TLI.getShiftAmountTy()));
1602 // For example, extension of an i48 to an i64. Leave the low part alone,
1603 // sext_inreg the high part.
1604 unsigned ExcessBits =
1605 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1606 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1607 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1611 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1612 SDValue &Lo, SDValue &Hi) {
1613 MVT VT = N->getValueType(0);
1615 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1617 LC = RTLIB::SREM_I32;
1618 else if (VT == MVT::i64)
1619 LC = RTLIB::SREM_I64;
1620 else if (VT == MVT::i128)
1621 LC = RTLIB::SREM_I128;
1622 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1624 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1625 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1628 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1629 SDValue &Lo, SDValue &Hi) {
1630 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1631 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1632 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1633 DAG.getConstant(NVT.getSizeInBits(),
1634 TLI.getShiftAmountTy()));
1635 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1638 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1639 SDValue &Lo, SDValue &Hi) {
1640 MVT VT = N->getValueType(0);
1642 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1644 LC = RTLIB::UDIV_I32;
1645 else if (VT == MVT::i64)
1646 LC = RTLIB::UDIV_I64;
1647 else if (VT == MVT::i128)
1648 LC = RTLIB::UDIV_I128;
1649 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1651 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1652 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1655 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1656 SDValue &Lo, SDValue &Hi) {
1657 MVT VT = N->getValueType(0);
1659 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1661 LC = RTLIB::UREM_I32;
1662 else if (VT == MVT::i64)
1663 LC = RTLIB::UREM_I64;
1664 else if (VT == MVT::i128)
1665 LC = RTLIB::UREM_I128;
1666 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1668 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1669 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1672 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1673 SDValue &Lo, SDValue &Hi) {
1674 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1675 SDValue Op = N->getOperand(0);
1676 if (Op.getValueType().bitsLE(NVT)) {
1677 // The low part is zero extension of the input (which degenerates to a copy).
1678 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1679 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1681 // For example, extension of an i48 to an i64. The operand type necessarily
1682 // promotes to the result type, so will end up being expanded too.
1683 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1684 "Only know how to promote this result!");
1685 SDValue Res = GetPromotedInteger(Op);
1686 assert(Res.getValueType() == N->getValueType(0) &&
1687 "Operand over promoted?");
1688 // Split the promoted operand. This will simplify when it is expanded.
1689 SplitInteger(Res, Lo, Hi);
1690 unsigned ExcessBits =
1691 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1692 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1697 //===----------------------------------------------------------------------===//
1698 // Integer Operand Expansion
1699 //===----------------------------------------------------------------------===//
1701 /// ExpandIntegerOperand - This method is called when the specified operand of
1702 /// the specified node is found to need expansion. At this point, all of the
1703 /// result types of the node are known to be legal, but other operands of the
1704 /// node may need promotion or expansion as well as the specified one.
1705 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1706 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1707 SDValue Res = SDValue();
1709 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1710 == TargetLowering::Custom)
1711 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
1713 if (Res.getNode() == 0) {
1714 switch (N->getOpcode()) {
1717 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1718 N->dump(&DAG); cerr << "\n";
1720 assert(0 && "Do not know how to expand this operator's operand!");
1723 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1724 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1725 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1727 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1728 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1729 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1730 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1731 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1733 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1734 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1738 // If the result is null, the sub-method took care of registering results etc.
1739 if (!Res.getNode()) return false;
1740 // If the result is N, the sub-method updated N in place. Check to see if any
1741 // operands are new, and if so, mark them.
1742 if (Res.getNode() == N) {
1743 // Mark N as new and remark N and its operands. This allows us to correctly
1744 // revisit N if it needs another step of expansion and allows us to visit
1745 // any new operands to N.
1750 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1751 "Invalid operand expansion");
1753 ReplaceValueWith(SDValue(N, 0), Res);
1757 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1758 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1759 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1761 ISD::CondCode &CCCode) {
1762 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1763 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1764 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1766 MVT VT = NewLHS.getValueType();
1768 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1769 if (RHSLo == RHSHi) {
1770 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1771 if (RHSCST->isAllOnesValue()) {
1772 // Equality comparison to -1.
1773 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1780 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1781 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1782 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1783 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1787 // If this is a comparison of the sign bit, just look at the top part.
1789 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1790 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1791 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1797 // FIXME: This generated code sucks.
1798 ISD::CondCode LowCC;
1800 default: assert(0 && "Unknown integer setcc!");
1802 case ISD::SETULT: LowCC = ISD::SETULT; break;
1804 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1806 case ISD::SETULE: LowCC = ISD::SETULE; break;
1808 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1811 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1812 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1813 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1815 // NOTE: on targets without efficient SELECT of bools, we can always use
1816 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1817 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1819 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1820 false, DagCombineInfo);
1821 if (!Tmp1.getNode())
1822 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1823 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1824 CCCode, false, DagCombineInfo);
1825 if (!Tmp2.getNode())
1826 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1827 DAG.getCondCode(CCCode));
1829 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
1830 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
1831 if ((Tmp1C && Tmp1C->isNullValue()) ||
1832 (Tmp2C && Tmp2C->isNullValue() &&
1833 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1834 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1835 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1836 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1837 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1838 // low part is known false, returns high part.
1839 // For LE / GE, if high part is known false, ignore the low part.
1840 // For LT / GT, if high part is known true, ignore the low part.
1846 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1847 ISD::SETEQ, false, DagCombineInfo);
1848 if (!NewLHS.getNode())
1849 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1851 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1852 NewLHS, Tmp1, Tmp2);
1856 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1857 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1858 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1859 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1861 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1862 // against zero to select between true and false values.
1863 if (NewRHS.getNode() == 0) {
1864 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1865 CCCode = ISD::SETNE;
1868 // Update N to have the operands specified.
1869 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
1870 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1874 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1875 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1876 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1877 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1879 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1880 // against zero to select between true and false values.
1881 if (NewRHS.getNode() == 0) {
1882 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1883 CCCode = ISD::SETNE;
1886 // Update N to have the operands specified.
1887 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
1888 N->getOperand(2), N->getOperand(3),
1889 DAG.getCondCode(CCCode));
1892 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1893 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1894 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1895 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1897 // If ExpandSetCCOperands returned a scalar, use it.
1898 if (NewRHS.getNode() == 0) {
1899 assert(NewLHS.getValueType() == N->getValueType(0) &&
1900 "Unexpected setcc expansion!");
1904 // Otherwise, update N to have the operands specified.
1905 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
1906 DAG.getCondCode(CCCode));
1909 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
1910 SDValue Op = N->getOperand(0);
1911 MVT DstVT = N->getValueType(0);
1912 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
1913 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1914 "Don't know how to expand this SINT_TO_FP!");
1915 return MakeLibCall(LC, DstVT, &Op, 1, true);
1918 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
1919 if (ISD::isNormalStore(N))
1920 return ExpandOp_NormalStore(N, OpNo);
1922 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1923 assert(OpNo == 1 && "Can only expand the stored value so far");
1925 MVT VT = N->getOperand(1).getValueType();
1926 MVT NVT = TLI.getTypeToTransformTo(VT);
1927 SDValue Ch = N->getChain();
1928 SDValue Ptr = N->getBasePtr();
1929 int SVOffset = N->getSrcValueOffset();
1930 unsigned Alignment = N->getAlignment();
1931 bool isVolatile = N->isVolatile();
1934 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1936 if (N->getMemoryVT().bitsLE(NVT)) {
1937 GetExpandedInteger(N->getValue(), Lo, Hi);
1938 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1939 N->getMemoryVT(), isVolatile, Alignment);
1940 } else if (TLI.isLittleEndian()) {
1941 // Little-endian - low bits are at low addresses.
1942 GetExpandedInteger(N->getValue(), Lo, Hi);
1944 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1945 isVolatile, Alignment);
1947 unsigned ExcessBits =
1948 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1949 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1951 // Increment the pointer to the other half.
1952 unsigned IncrementSize = NVT.getSizeInBits()/8;
1953 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1954 DAG.getIntPtrConstant(IncrementSize));
1955 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1956 SVOffset+IncrementSize, NEVT,
1957 isVolatile, MinAlign(Alignment, IncrementSize));
1958 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1960 // Big-endian - high bits are at low addresses. Favor aligned stores at
1961 // the cost of some bit-fiddling.
1962 GetExpandedInteger(N->getValue(), Lo, Hi);
1964 MVT EVT = N->getMemoryVT();
1965 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1966 unsigned IncrementSize = NVT.getSizeInBits()/8;
1967 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1968 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
1970 if (ExcessBits < NVT.getSizeInBits()) {
1971 // Transfer high bits from the top of Lo to the bottom of Hi.
1972 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
1973 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1974 TLI.getShiftAmountTy()));
1975 Hi = DAG.getNode(ISD::OR, NVT, Hi,
1976 DAG.getNode(ISD::SRL, NVT, Lo,
1977 DAG.getConstant(ExcessBits,
1978 TLI.getShiftAmountTy())));
1981 // Store both the high bits and maybe some of the low bits.
1982 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1983 SVOffset, HiVT, isVolatile, Alignment);
1985 // Increment the pointer to the other half.
1986 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1987 DAG.getIntPtrConstant(IncrementSize));
1988 // Store the lowest ExcessBits bits in the second half.
1989 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
1990 SVOffset+IncrementSize,
1991 MVT::getIntegerVT(ExcessBits),
1992 isVolatile, MinAlign(Alignment, IncrementSize));
1993 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1997 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
1999 GetExpandedInteger(N->getOperand(0), InL, InH);
2000 // Just truncate the low part of the source.
2001 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2004 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2005 SDValue Op = N->getOperand(0);
2006 MVT SrcVT = Op.getValueType();
2007 MVT DstVT = N->getValueType(0);
2009 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2010 // Do a signed conversion then adjust the result.
2011 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2012 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2014 // The result of the signed conversion needs adjusting if the 'sign bit' of
2015 // the incoming integer was set. To handle this, we dynamically test to see
2016 // if it is set, and, if so, add a fudge factor.
2018 const uint64_t F32TwoE32 = 0x4F800000ULL;
2019 const uint64_t F32TwoE64 = 0x5F800000ULL;
2020 const uint64_t F32TwoE128 = 0x7F800000ULL;
2023 if (SrcVT == MVT::i32)
2024 FF = APInt(32, F32TwoE32);
2025 else if (SrcVT == MVT::i64)
2026 FF = APInt(32, F32TwoE64);
2027 else if (SrcVT == MVT::i128)
2028 FF = APInt(32, F32TwoE128);
2030 assert(false && "Unsupported UINT_TO_FP!");
2032 // Check whether the sign bit is set.
2034 GetExpandedInteger(Op, Lo, Hi);
2035 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2036 DAG.getConstant(0, Hi.getValueType()),
2039 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2040 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2041 TLI.getPointerTy());
2043 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2044 SDValue Zero = DAG.getIntPtrConstant(0);
2045 SDValue Four = DAG.getIntPtrConstant(4);
2046 if (TLI.isBigEndian()) std::swap(Zero, Four);
2047 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2049 unsigned Alignment =
2050 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2051 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2052 Alignment = std::min(Alignment, 4u);
2054 // Load the value out, extending it from f32 to the destination float type.
2055 // FIXME: Avoid the extend by constructing the right constant pool?
2056 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2057 FudgePtr, NULL, 0, MVT::f32,
2059 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2062 // Otherwise, use a libcall.
2063 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2064 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2065 "Don't know how to expand this UINT_TO_FP!");
2066 return MakeLibCall(LC, DstVT, &Op, 1, true);