1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerResults(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 // Otherwise, lower the bit-convert to a store/load from the stack.
215 // Create the stack frame object. Make sure it is aligned for both
216 // the source and destination types.
217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
219 const Value *SV = PseudoSourceValue::getFixedStack(FI);
221 // Emit a store to the stack slot.
222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
224 // Result is an extending load from the stack slot.
225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT);
228 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
229 SDValue Op = GetPromotedInteger(N->getOperand(0));
230 MVT OVT = N->getValueType(0);
231 MVT NVT = Op.getValueType();
232 DebugLoc dl = N->getDebugLoc();
234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
236 DAG.getConstant(DiffBits, TLI.getPointerTy()));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
240 // The pair element type may be legal, or may not promote to the same type as
241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
243 TLI.getTypeToTransformTo(N->getValueType(0)),
244 JoinIntegers(N->getOperand(0), N->getOperand(1)));
247 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
248 MVT VT = N->getValueType(0);
249 // Zero extend things like i1, sign extend everything else. It shouldn't
250 // matter in theory which one we pick, but this tends to give better code?
251 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
252 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
254 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
258 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
259 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
260 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
261 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
262 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
263 "can only promote integers");
264 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
265 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
266 N->getOperand(1), N->getOperand(2),
267 N->getOperand(3), N->getOperand(4), CvtCode);
270 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
271 // Zero extend to the promoted type and do the count there.
272 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
273 MVT OVT = N->getValueType(0);
274 MVT NVT = Op.getValueType();
275 Op = DAG.getNode(ISD::CTLZ, NVT, Op);
276 // Subtract off the extra leading bits in the bigger type.
277 return DAG.getNode(ISD::SUB, N->getDebugLoc(), NVT, Op,
278 DAG.getConstant(NVT.getSizeInBits() -
279 OVT.getSizeInBits(), NVT));
282 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
283 // Zero extend to the promoted type and do the count there.
284 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
285 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
288 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
289 SDValue Op = GetPromotedInteger(N->getOperand(0));
290 MVT OVT = N->getValueType(0);
291 MVT NVT = Op.getValueType();
292 DebugLoc dl = N->getDebugLoc();
293 // The count is the same in the promoted type except if the original
294 // value was zero. This can be handled by setting the bit just off
295 // the top of the original type.
296 APInt TopBit(NVT.getSizeInBits(), 0);
297 TopBit.set(OVT.getSizeInBits());
298 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
299 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
302 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
303 MVT OldVT = N->getValueType(0);
304 SDValue OldVec = N->getOperand(0);
305 if (getTypeAction(OldVec.getValueType()) == WidenVector)
306 OldVec = GetWidenedVector(N->getOperand(0));
307 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
308 DebugLoc dl = N->getDebugLoc();
311 assert(!isTypeLegal(OldVec.getValueType()) &&
312 "Legal one-element vector of a type needing promotion!");
313 // It is tempting to follow GetScalarizedVector by a call to
314 // GetPromotedInteger, but this would be wrong because the
315 // scalarized value may not yet have been processed.
316 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
317 GetScalarizedVector(OldVec));
320 // Convert to a vector half as long with an element type of twice the width,
321 // for example <4 x i16> -> <2 x i32>.
322 assert(!(OldElts & 1) && "Odd length vectors not supported!");
323 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
324 assert(OldVT.isSimple() && NewVT.isSimple());
326 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
327 MVT::getVectorVT(NewVT, OldElts / 2),
330 // Extract the element at OldIdx / 2 from the new vector.
331 SDValue OldIdx = N->getOperand(1);
332 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
333 DAG.getConstant(1, TLI.getPointerTy()));
334 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
336 // Select the appropriate half of the element: Lo if OldIdx was even,
339 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
340 DAG.getConstant(OldVT.getSizeInBits(),
341 TLI.getPointerTy()));
342 if (TLI.isBigEndian())
345 // Extend to the promoted type.
346 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
347 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
348 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
351 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
352 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
353 unsigned NewOpc = N->getOpcode();
354 DebugLoc dl = N->getDebugLoc();
356 // If we're promoting a UINT to a larger size, check to see if the new node
357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
358 // we can use that instead. This allows us to generate better code for
359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
360 // legal, such as PowerPC.
361 if (N->getOpcode() == ISD::FP_TO_UINT &&
362 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
363 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
364 NewOpc = ISD::FP_TO_SINT;
366 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
368 // Assert that the converted value fits in the original type. If it doesn't
369 // (eg: because the value being converted is too big), then the result of the
370 // original operation was undefined anyway, so the assert is still correct.
371 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
372 ISD::AssertZext : ISD::AssertSext, dl,
373 NVT, Res, DAG.getValueType(N->getValueType(0)));
376 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
377 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
378 DebugLoc dl = N->getDebugLoc();
380 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
381 SDValue Res = GetPromotedInteger(N->getOperand(0));
382 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
384 // If the result and operand types are the same after promotion, simplify
385 // to an in-register extension.
386 if (NVT == Res.getValueType()) {
387 // The high bits are not guaranteed to be anything. Insert an extend.
388 if (N->getOpcode() == ISD::SIGN_EXTEND)
389 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
390 DAG.getValueType(N->getOperand(0).getValueType()));
391 if (N->getOpcode() == ISD::ZERO_EXTEND)
392 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
393 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
398 // Otherwise, just extend the original operand all the way to the larger type.
399 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
402 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
403 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
404 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
405 ISD::LoadExtType ExtType =
406 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
407 DebugLoc dl = N->getDebugLoc();
408 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
409 N->getSrcValue(), N->getSrcValueOffset(),
410 N->getMemoryVT(), N->isVolatile(),
413 // Legalized the chain result - switch anything that used the old chain to
415 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
419 /// Promote the overflow flag of an overflowing arithmetic node.
420 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
421 // Simply change the return type of the boolean result.
422 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
423 MVT ValueVTs[] = { N->getValueType(0), NVT };
424 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
425 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
426 DAG.getVTList(ValueVTs, 2), Ops, 2);
428 // Modified the sum result - switch anything that used the old sum to use
430 ReplaceValueWith(SDValue(N, 0), Res);
432 return SDValue(Res.getNode(), 1);
435 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
437 return PromoteIntRes_Overflow(N);
439 // The operation overflowed iff the result in the larger type is not the
440 // sign extension of its truncation to the original type.
441 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
442 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
443 MVT OVT = N->getOperand(0).getValueType();
444 MVT NVT = LHS.getValueType();
445 DebugLoc dl = N->getDebugLoc();
447 // Do the arithmetic in the larger type.
448 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
449 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
451 // Calculate the overflow flag: sign extend the arithmetic result from
452 // the original type.
453 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
454 DAG.getValueType(OVT));
455 // Overflowed if and only if this is not equal to Res.
456 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
458 // Use the calculated overflow everywhere.
459 ReplaceValueWith(SDValue(N, 1), Ofl);
464 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
465 // Sign extend the input.
466 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
467 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
468 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
469 LHS.getValueType(), LHS, RHS);
472 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
473 SDValue LHS = GetPromotedInteger(N->getOperand(1));
474 SDValue RHS = GetPromotedInteger(N->getOperand(2));
475 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
476 LHS.getValueType(), N->getOperand(0),LHS,RHS);
479 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
480 SDValue LHS = GetPromotedInteger(N->getOperand(2));
481 SDValue RHS = GetPromotedInteger(N->getOperand(3));
482 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
483 LHS.getValueType(), N->getOperand(0),
484 N->getOperand(1), LHS, RHS, N->getOperand(4));
487 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
488 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
489 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
490 DebugLoc dl = N->getDebugLoc();
492 // Get the SETCC result using the canonical SETCC type.
493 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
494 N->getOperand(1), N->getOperand(2));
496 // Convert to the expected type.
497 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
498 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
499 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
503 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
504 TLI.getTypeToTransformTo(N->getValueType(0)),
505 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
508 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
509 SDValue Op = GetPromotedInteger(N->getOperand(0));
510 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
511 Op.getValueType(), Op, N->getOperand(1));
514 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
515 // The input may have strange things in the top bits of the registers, but
516 // these operations don't care. They may have weird bits going out, but
517 // that too is okay if they are integer operations.
518 SDValue LHS = GetPromotedInteger(N->getOperand(0));
519 SDValue RHS = GetPromotedInteger(N->getOperand(1));
520 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
521 LHS.getValueType(), LHS, RHS);
524 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
525 // The input value must be properly sign extended.
526 SDValue Res = SExtPromotedInteger(N->getOperand(0));
527 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
528 Res.getValueType(), Res, N->getOperand(1));
531 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
532 // The input value must be properly zero extended.
533 MVT VT = N->getValueType(0);
534 MVT NVT = TLI.getTypeToTransformTo(VT);
535 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
536 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
539 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
540 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
543 switch (getTypeAction(N->getOperand(0).getValueType())) {
544 default: assert(0 && "Unknown type action!");
547 Res = N->getOperand(0);
550 Res = GetPromotedInteger(N->getOperand(0));
554 // Truncate to NVT instead of VT
555 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
558 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
560 return PromoteIntRes_Overflow(N);
562 // The operation overflowed iff the result in the larger type is not the
563 // zero extension of its truncation to the original type.
564 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
565 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
566 MVT OVT = N->getOperand(0).getValueType();
567 MVT NVT = LHS.getValueType();
568 DebugLoc dl = N->getDebugLoc();
570 // Do the arithmetic in the larger type.
571 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
572 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
574 // Calculate the overflow flag: zero extend the arithmetic result from
575 // the original type.
576 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
577 // Overflowed if and only if this is not equal to Res.
578 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
580 // Use the calculated overflow everywhere.
581 ReplaceValueWith(SDValue(N, 1), Ofl);
586 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
587 // Zero extend the input.
588 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
589 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
590 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
591 LHS.getValueType(), LHS, RHS);
594 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
595 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(),
596 TLI.getTypeToTransformTo(N->getValueType(0)));
599 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
600 SDValue Chain = N->getOperand(0); // Get the chain.
601 SDValue Ptr = N->getOperand(1); // Get the pointer.
602 MVT VT = N->getValueType(0);
603 DebugLoc dl = N->getDebugLoc();
605 MVT RegVT = TLI.getRegisterType(VT);
606 unsigned NumRegs = TLI.getNumRegisters(VT);
607 // The argument is passed as NumRegs registers of type RegVT.
609 SmallVector<SDValue, 8> Parts(NumRegs);
610 for (unsigned i = 0; i < NumRegs; ++i) {
611 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
612 Chain = Parts[i].getValue(1);
615 // Handle endianness of the load.
616 if (TLI.isBigEndian())
617 std::reverse(Parts.begin(), Parts.end());
619 // Assemble the parts in the promoted type.
620 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
621 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
622 for (unsigned i = 1; i < NumRegs; ++i) {
623 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
624 // Shift it to the right position and "or" it in.
625 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
626 DAG.getConstant(i * RegVT.getSizeInBits(),
627 TLI.getPointerTy()));
628 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
631 // Modified the chain result - switch anything that used the old chain to
633 ReplaceValueWith(SDValue(N, 1), Chain);
638 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
639 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
640 return PromoteIntRes_Overflow(N);
643 //===----------------------------------------------------------------------===//
644 // Integer Operand Promotion
645 //===----------------------------------------------------------------------===//
647 /// PromoteIntegerOperand - This method is called when the specified operand of
648 /// the specified node is found to need promotion. At this point, all of the
649 /// result types of the node are known to be legal, but other operands of the
650 /// node may need promotion or expansion as well as the specified one.
651 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
652 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
653 SDValue Res = SDValue();
655 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
658 switch (N->getOpcode()) {
661 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
662 N->dump(&DAG); cerr << "\n";
664 assert(0 && "Do not know how to promote this operator's operand!");
667 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
668 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
669 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
670 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
671 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
672 case ISD::CONVERT_RNDSAT:
673 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
674 case ISD::INSERT_VECTOR_ELT:
675 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
676 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
677 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
678 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
679 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
680 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
681 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
682 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
684 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
685 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
686 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
692 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
695 // If the result is null, the sub-method took care of registering results etc.
696 if (!Res.getNode()) return false;
698 // If the result is N, the sub-method updated N in place. Tell the legalizer
700 if (Res.getNode() == N)
703 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
704 "Invalid operand expansion");
706 ReplaceValueWith(SDValue(N, 0), Res);
710 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
711 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
712 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
713 ISD::CondCode CCCode) {
714 // We have to insert explicit sign or zero extends. Note that we could
715 // insert sign extends for ALL conditions, but zero extend is cheaper on
716 // many machines (an AND instead of two shifts), so prefer it.
718 default: assert(0 && "Unknown integer comparison!");
725 // ALL of these operations will work if we either sign or zero extend
726 // the operands (including the unsigned comparisons!). Zero extend is
727 // usually a simpler/cheaper operation, so prefer it.
728 NewLHS = ZExtPromotedInteger(NewLHS);
729 NewRHS = ZExtPromotedInteger(NewRHS);
735 NewLHS = SExtPromotedInteger(NewLHS);
736 NewRHS = SExtPromotedInteger(NewRHS);
741 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
742 SDValue Op = GetPromotedInteger(N->getOperand(0));
743 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
746 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
747 assert(OpNo == 2 && "Don't know how to promote this operand!");
749 SDValue LHS = N->getOperand(2);
750 SDValue RHS = N->getOperand(3);
751 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
753 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
755 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
756 N->getOperand(1), LHS, RHS, N->getOperand(4));
759 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
760 assert(OpNo == 1 && "only know how to promote condition");
762 // Promote all the way up to the canonical SetCC type.
763 MVT SVT = TLI.getSetCCResultType(MVT::Other);
764 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
766 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
767 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
771 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
772 // Since the result type is legal, the operands must promote to it.
773 MVT OVT = N->getOperand(0).getValueType();
774 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
775 SDValue Hi = GetPromotedInteger(N->getOperand(1));
776 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
777 DebugLoc dl = N->getDebugLoc();
779 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
780 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
781 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
784 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
785 // The vector type is legal but the element type is not. This implies
786 // that the vector is a power-of-two in length and that the element
787 // type does not have a strange size (eg: it is not i1).
788 MVT VecVT = N->getValueType(0);
789 unsigned NumElts = VecVT.getVectorNumElements();
790 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
791 DebugLoc dl = N->getDebugLoc();
793 // Build a vector of half the length out of elements of twice the bitwidth.
794 // For example <4 x i16> -> <2 x i32>.
795 MVT OldVT = N->getOperand(0).getValueType();
796 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
797 assert(OldVT.isSimple() && NewVT.isSimple());
799 std::vector<SDValue> NewElts;
800 NewElts.reserve(NumElts/2);
802 for (unsigned i = 0; i < NumElts; i += 2) {
803 // Combine two successive elements into one promoted element.
804 SDValue Lo = N->getOperand(i);
805 SDValue Hi = N->getOperand(i+1);
806 if (TLI.isBigEndian())
808 NewElts.push_back(JoinIntegers(Lo, Hi));
811 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
812 MVT::getVectorVT(NewVT, NewElts.size()),
813 &NewElts[0], NewElts.size());
815 // Convert the new vector to the old vector type.
816 return DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, NewVec);
819 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
820 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
821 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
822 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
823 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
824 "can only promote integer arguments");
825 SDValue InOp = GetPromotedInteger(N->getOperand(0));
826 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
827 N->getOperand(1), N->getOperand(2),
828 N->getOperand(3), N->getOperand(4), CvtCode);
831 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
834 // Promote the inserted value. This is valid because the type does not
835 // have to match the vector element type.
837 // Check that any extra bits introduced will be truncated away.
838 assert(N->getOperand(1).getValueType().getSizeInBits() >=
839 N->getValueType(0).getVectorElementType().getSizeInBits() &&
840 "Type of inserted value narrower than vector element type!");
841 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
842 GetPromotedInteger(N->getOperand(1)),
846 assert(OpNo == 2 && "Different operand and result vector types?");
848 // Promote the index.
849 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
850 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
851 N->getOperand(1), Idx);
854 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
856 DebugLoc dl = N->getDebugLoc();
857 NewOps[0] = N->getOperand(0);
858 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
859 SDValue Flag = GetPromotedInteger(N->getOperand(i));
860 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
862 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
863 array_lengthof(NewOps));
866 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
867 assert(OpNo == 0 && "Only know how to promote condition");
869 // Promote all the way up to the canonical SetCC type.
870 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
871 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
873 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
874 N->getOperand(1), N->getOperand(2));
877 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
878 assert(OpNo == 0 && "Don't know how to promote this operand!");
880 SDValue LHS = N->getOperand(0);
881 SDValue RHS = N->getOperand(1);
882 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
884 // The CC (#4) and the possible return values (#2 and #3) have legal types.
885 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
886 N->getOperand(3), N->getOperand(4));
889 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
890 assert(OpNo == 0 && "Don't know how to promote this operand!");
892 SDValue LHS = N->getOperand(0);
893 SDValue RHS = N->getOperand(1);
894 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
896 // The CC (#2) is always legal.
897 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
900 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
901 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
902 ZExtPromotedInteger(N->getOperand(1)));
905 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
906 SDValue Op = GetPromotedInteger(N->getOperand(0));
907 DebugLoc dl = N->getDebugLoc();
908 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
909 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
910 Op, DAG.getValueType(N->getOperand(0).getValueType()));
913 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
914 return DAG.UpdateNodeOperands(SDValue(N, 0),
915 SExtPromotedInteger(N->getOperand(0)));
918 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
919 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
920 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
921 int SVOffset = N->getSrcValueOffset();
922 unsigned Alignment = N->getAlignment();
923 bool isVolatile = N->isVolatile();
924 DebugLoc dl = N->getDebugLoc();
926 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
928 // Truncate the value and store the result.
929 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
930 SVOffset, N->getMemoryVT(),
931 isVolatile, Alignment);
934 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
935 SDValue Op = GetPromotedInteger(N->getOperand(0));
936 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
939 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
940 return DAG.UpdateNodeOperands(SDValue(N, 0),
941 ZExtPromotedInteger(N->getOperand(0)));
944 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
945 DebugLoc dl = N->getDebugLoc();
946 SDValue Op = GetPromotedInteger(N->getOperand(0));
947 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
948 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
952 //===----------------------------------------------------------------------===//
953 // Integer Result Expansion
954 //===----------------------------------------------------------------------===//
956 /// ExpandIntegerResult - This method is called when the specified result of the
957 /// specified node is found to need expansion. At this point, the node may also
958 /// have invalid operands or may have other results that need promotion, we just
959 /// know that (at least) one result needs expansion.
960 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
961 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
965 // See if the target wants to custom expand this node.
966 if (CustomLowerResults(N, N->getValueType(ResNo), true))
969 switch (N->getOpcode()) {
972 cerr << "ExpandIntegerResult #" << ResNo << ": ";
973 N->dump(&DAG); cerr << "\n";
975 assert(0 && "Do not know how to expand the result of this operator!");
978 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
979 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
980 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
981 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
983 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
984 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
985 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
986 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
987 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
989 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
990 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
991 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
992 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
993 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
994 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
995 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
996 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
997 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
998 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
999 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1000 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1001 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1002 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1003 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1004 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1005 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1006 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1007 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1008 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1012 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1015 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1018 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1021 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1025 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1028 // If Lo/Hi is null, the sub-method took care of registering results etc.
1030 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1033 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1034 /// and the shift amount is a constant 'Amt'. Expand the operation.
1035 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1036 SDValue &Lo, SDValue &Hi) {
1037 DebugLoc dl = N->getDebugLoc();
1038 // Expand the incoming operand to be shifted, so that we have its parts
1040 GetExpandedInteger(N->getOperand(0), InL, InH);
1042 MVT NVT = InL.getValueType();
1043 unsigned VTBits = N->getValueType(0).getSizeInBits();
1044 unsigned NVTBits = NVT.getSizeInBits();
1045 MVT ShTy = N->getOperand(1).getValueType();
1047 if (N->getOpcode() == ISD::SHL) {
1049 Lo = Hi = DAG.getConstant(0, NVT);
1050 } else if (Amt > NVTBits) {
1051 Lo = DAG.getConstant(0, NVT);
1052 Hi = DAG.getNode(ISD::SHL, dl,
1053 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1054 } else if (Amt == NVTBits) {
1055 Lo = DAG.getConstant(0, NVT);
1057 } else if (Amt == 1 &&
1058 TLI.isOperationLegalOrCustom(ISD::ADDC,
1059 TLI.getTypeToExpandTo(NVT))) {
1060 // Emit this X << 1 as X+X.
1061 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1062 SDValue LoOps[2] = { InL, InL };
1063 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1064 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1065 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1067 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1068 Hi = DAG.getNode(ISD::OR, dl, NVT,
1069 DAG.getNode(ISD::SHL, dl, NVT, InH,
1070 DAG.getConstant(Amt, ShTy)),
1071 DAG.getNode(ISD::SRL, dl, NVT, InL,
1072 DAG.getConstant(NVTBits-Amt, ShTy)));
1077 if (N->getOpcode() == ISD::SRL) {
1079 Lo = DAG.getConstant(0, NVT);
1080 Hi = DAG.getConstant(0, NVT);
1081 } else if (Amt > NVTBits) {
1082 Lo = DAG.getNode(ISD::SRL, dl,
1083 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1084 Hi = DAG.getConstant(0, NVT);
1085 } else if (Amt == NVTBits) {
1087 Hi = DAG.getConstant(0, NVT);
1089 Lo = DAG.getNode(ISD::OR, dl, NVT,
1090 DAG.getNode(ISD::SRL, dl, NVT, InL,
1091 DAG.getConstant(Amt, ShTy)),
1092 DAG.getNode(ISD::SHL, dl, NVT, InH,
1093 DAG.getConstant(NVTBits-Amt, ShTy)));
1094 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1099 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1101 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1102 DAG.getConstant(NVTBits-1, ShTy));
1103 } else if (Amt > NVTBits) {
1104 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1105 DAG.getConstant(Amt-NVTBits, ShTy));
1106 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1107 DAG.getConstant(NVTBits-1, ShTy));
1108 } else if (Amt == NVTBits) {
1110 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1111 DAG.getConstant(NVTBits-1, ShTy));
1113 Lo = DAG.getNode(ISD::OR, dl, NVT,
1114 DAG.getNode(ISD::SRL, dl, NVT, InL,
1115 DAG.getConstant(Amt, ShTy)),
1116 DAG.getNode(ISD::SHL, dl, NVT, InH,
1117 DAG.getConstant(NVTBits-Amt, ShTy)));
1118 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1122 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1123 /// this shift based on knowledge of the high bit of the shift amount. If we
1124 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1126 bool DAGTypeLegalizer::
1127 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1128 SDValue Amt = N->getOperand(1);
1129 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1130 MVT ShTy = Amt.getValueType();
1131 unsigned ShBits = ShTy.getSizeInBits();
1132 unsigned NVTBits = NVT.getSizeInBits();
1133 assert(isPowerOf2_32(NVTBits) &&
1134 "Expanded integer type size not a power of two!");
1135 DebugLoc dl = N->getDebugLoc();
1137 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1138 APInt KnownZero, KnownOne;
1139 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1141 // If we don't know anything about the high bits, exit.
1142 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1145 // Get the incoming operand to be shifted.
1147 GetExpandedInteger(N->getOperand(0), InL, InH);
1149 // If we know that any of the high bits of the shift amount are one, then we
1150 // can do this as a couple of simple shifts.
1151 if (KnownOne.intersects(HighBitMask)) {
1152 // Mask out the high bit, which we know is set.
1153 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1154 DAG.getConstant(~HighBitMask, ShTy));
1156 switch (N->getOpcode()) {
1157 default: assert(0 && "Unknown shift");
1159 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1160 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1163 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1164 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1167 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1168 DAG.getConstant(NVTBits-1, ShTy));
1169 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1175 // FIXME: This code is broken for shifts with a zero amount!
1176 // If we know that all of the high bits of the shift amount are zero, then we
1177 // can do this as a couple of simple shifts.
1178 if ((KnownZero & HighBitMask) == HighBitMask) {
1180 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1181 DAG.getConstant(NVTBits, ShTy),
1184 switch (N->getOpcode()) {
1185 default: assert(0 && "Unknown shift");
1186 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1188 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1191 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1192 Hi = DAG.getNode(ISD::OR, NVT,
1193 DAG.getNode(Op1, NVT, InH, Amt),
1194 DAG.getNode(Op2, NVT, InL, Amt2));
1202 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1203 SDValue &Lo, SDValue &Hi) {
1204 DebugLoc dl = N->getDebugLoc();
1205 // Expand the subcomponents.
1206 SDValue LHSL, LHSH, RHSL, RHSH;
1207 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1208 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1210 MVT NVT = LHSL.getValueType();
1211 SDValue LoOps[2] = { LHSL, RHSL };
1212 SDValue HiOps[3] = { LHSH, RHSH };
1214 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1215 // them. TODO: Teach operation legalization how to expand unsupported
1216 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1217 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1218 // generate a value of this type in the expanded code sequence.
1220 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1221 ISD::ADDC : ISD::SUBC,
1222 TLI.getTypeToExpandTo(NVT));
1225 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1226 if (N->getOpcode() == ISD::ADD) {
1227 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1228 HiOps[2] = Lo.getValue(1);
1229 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1231 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1232 HiOps[2] = Lo.getValue(1);
1233 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1236 if (N->getOpcode() == ISD::ADD) {
1237 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1238 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1239 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1241 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1242 DAG.getConstant(1, NVT),
1243 DAG.getConstant(0, NVT));
1244 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1246 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1247 DAG.getConstant(1, NVT), Carry1);
1248 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1250 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1251 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1253 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1254 LoOps[0], LoOps[1], ISD::SETULT);
1255 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1256 DAG.getConstant(1, NVT),
1257 DAG.getConstant(0, NVT));
1258 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1263 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1264 SDValue &Lo, SDValue &Hi) {
1265 // Expand the subcomponents.
1266 SDValue LHSL, LHSH, RHSL, RHSH;
1267 DebugLoc dl = N->getDebugLoc();
1268 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1269 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1270 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1271 SDValue LoOps[2] = { LHSL, RHSL };
1272 SDValue HiOps[3] = { LHSH, RHSH };
1274 if (N->getOpcode() == ISD::ADDC) {
1275 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1276 HiOps[2] = Lo.getValue(1);
1277 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1279 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1280 HiOps[2] = Lo.getValue(1);
1281 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1284 // Legalized the flag result - switch anything that used the old flag to
1286 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1289 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1290 SDValue &Lo, SDValue &Hi) {
1291 // Expand the subcomponents.
1292 SDValue LHSL, LHSH, RHSL, RHSH;
1293 DebugLoc dl = N->getDebugLoc();
1294 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1295 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1296 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1297 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1298 SDValue HiOps[3] = { LHSH, RHSH };
1300 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1301 HiOps[2] = Lo.getValue(1);
1302 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1304 // Legalized the flag result - switch anything that used the old flag to
1306 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1309 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1310 SDValue &Lo, SDValue &Hi) {
1311 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1312 DebugLoc dl = N->getDebugLoc();
1313 SDValue Op = N->getOperand(0);
1314 if (Op.getValueType().bitsLE(NVT)) {
1315 // The low part is any extension of the input (which degenerates to a copy).
1316 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1317 Hi = DAG.getNode(ISD::UNDEF, dl, NVT); // The high part is undefined.
1319 // For example, extension of an i48 to an i64. The operand type necessarily
1320 // promotes to the result type, so will end up being expanded too.
1321 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1322 "Only know how to promote this result!");
1323 SDValue Res = GetPromotedInteger(Op);
1324 assert(Res.getValueType() == N->getValueType(0) &&
1325 "Operand over promoted?");
1326 // Split the promoted operand. This will simplify when it is expanded.
1327 SplitInteger(Res, Lo, Hi);
1331 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1332 SDValue &Lo, SDValue &Hi) {
1333 DebugLoc dl = N->getDebugLoc();
1334 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1335 MVT NVT = Lo.getValueType();
1336 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1337 unsigned NVTBits = NVT.getSizeInBits();
1338 unsigned EVTBits = EVT.getSizeInBits();
1340 if (NVTBits < EVTBits) {
1341 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1342 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1344 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1345 // The high part replicates the sign bit of Lo, make it explicit.
1346 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1347 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1351 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1352 SDValue &Lo, SDValue &Hi) {
1353 DebugLoc dl = N->getDebugLoc();
1354 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1355 MVT NVT = Lo.getValueType();
1356 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1357 unsigned NVTBits = NVT.getSizeInBits();
1358 unsigned EVTBits = EVT.getSizeInBits();
1360 if (NVTBits < EVTBits) {
1361 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1362 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1364 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1365 // The high part must be zero, make it explicit.
1366 Hi = DAG.getConstant(0, NVT);
1370 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1371 SDValue &Lo, SDValue &Hi) {
1372 DebugLoc dl = N->getDebugLoc();
1373 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1374 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1375 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1378 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1379 SDValue &Lo, SDValue &Hi) {
1380 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1381 unsigned NBitWidth = NVT.getSizeInBits();
1382 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1383 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1384 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1387 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1388 SDValue &Lo, SDValue &Hi) {
1389 DebugLoc dl = N->getDebugLoc();
1390 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1391 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1392 MVT NVT = Lo.getValueType();
1394 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1395 DAG.getConstant(0, NVT), ISD::SETNE);
1397 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1398 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1400 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1401 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1402 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1403 Hi = DAG.getConstant(0, NVT);
1406 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1407 SDValue &Lo, SDValue &Hi) {
1408 DebugLoc dl = N->getDebugLoc();
1409 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1410 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1411 MVT NVT = Lo.getValueType();
1412 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1413 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1414 Hi = DAG.getConstant(0, NVT);
1417 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1418 SDValue &Lo, SDValue &Hi) {
1419 DebugLoc dl = N->getDebugLoc();
1420 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1421 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1422 MVT NVT = Lo.getValueType();
1424 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1425 DAG.getConstant(0, NVT), ISD::SETNE);
1427 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1428 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1430 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1431 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1432 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1433 Hi = DAG.getConstant(0, NVT);
1436 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1438 DebugLoc dl = N->getDebugLoc();
1439 MVT VT = N->getValueType(0);
1440 SDValue Op = N->getOperand(0);
1441 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1442 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1443 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1446 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1448 DebugLoc dl = N->getDebugLoc();
1449 MVT VT = N->getValueType(0);
1450 SDValue Op = N->getOperand(0);
1451 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1452 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1453 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1456 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1457 SDValue &Lo, SDValue &Hi) {
1458 if (ISD::isNormalLoad(N)) {
1459 ExpandRes_NormalLoad(N, Lo, Hi);
1463 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1465 MVT VT = N->getValueType(0);
1466 MVT NVT = TLI.getTypeToTransformTo(VT);
1467 SDValue Ch = N->getChain();
1468 SDValue Ptr = N->getBasePtr();
1469 ISD::LoadExtType ExtType = N->getExtensionType();
1470 int SVOffset = N->getSrcValueOffset();
1471 unsigned Alignment = N->getAlignment();
1472 bool isVolatile = N->isVolatile();
1473 DebugLoc dl = N->getDebugLoc();
1475 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1477 if (N->getMemoryVT().bitsLE(NVT)) {
1478 MVT EVT = N->getMemoryVT();
1480 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1481 EVT, isVolatile, Alignment);
1483 // Remember the chain.
1484 Ch = Lo.getValue(1);
1486 if (ExtType == ISD::SEXTLOAD) {
1487 // The high part is obtained by SRA'ing all but one of the bits of the
1489 unsigned LoSize = Lo.getValueType().getSizeInBits();
1490 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1491 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1492 } else if (ExtType == ISD::ZEXTLOAD) {
1493 // The high part is just a zero.
1494 Hi = DAG.getConstant(0, NVT);
1496 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1497 // The high part is undefined.
1498 Hi = DAG.getNode(ISD::UNDEF, dl, NVT);
1500 } else if (TLI.isLittleEndian()) {
1501 // Little-endian - low bits are at low addresses.
1502 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1503 isVolatile, Alignment);
1505 unsigned ExcessBits =
1506 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1507 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1509 // Increment the pointer to the other half.
1510 unsigned IncrementSize = NVT.getSizeInBits()/8;
1511 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1512 DAG.getIntPtrConstant(IncrementSize));
1513 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1514 SVOffset+IncrementSize, NEVT,
1515 isVolatile, MinAlign(Alignment, IncrementSize));
1517 // Build a factor node to remember that this load is independent of the
1519 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1522 // Big-endian - high bits are at low addresses. Favor aligned loads at
1523 // the cost of some bit-fiddling.
1524 MVT EVT = N->getMemoryVT();
1525 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1526 unsigned IncrementSize = NVT.getSizeInBits()/8;
1527 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1529 // Load both the high bits and maybe some of the low bits.
1530 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1531 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1532 isVolatile, Alignment);
1534 // Increment the pointer to the other half.
1535 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1536 DAG.getIntPtrConstant(IncrementSize));
1537 // Load the rest of the low bits.
1538 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1539 SVOffset+IncrementSize,
1540 MVT::getIntegerVT(ExcessBits),
1541 isVolatile, MinAlign(Alignment, IncrementSize));
1543 // Build a factor node to remember that this load is independent of the
1545 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1548 if (ExcessBits < NVT.getSizeInBits()) {
1549 // Transfer low bits from the bottom of Hi to the top of Lo.
1550 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1551 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1552 DAG.getConstant(ExcessBits,
1553 TLI.getPointerTy())));
1554 // Move high bits to the right position in Hi.
1555 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1557 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1558 TLI.getPointerTy()));
1562 // Legalized the chain result - switch anything that used the old chain to
1564 ReplaceValueWith(SDValue(N, 1), Ch);
1567 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1568 SDValue &Lo, SDValue &Hi) {
1569 DebugLoc dl = N->getDebugLoc();
1570 SDValue LL, LH, RL, RH;
1571 GetExpandedInteger(N->getOperand(0), LL, LH);
1572 GetExpandedInteger(N->getOperand(1), RL, RH);
1573 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1574 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1577 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1578 SDValue &Lo, SDValue &Hi) {
1579 MVT VT = N->getValueType(0);
1580 MVT NVT = TLI.getTypeToTransformTo(VT);
1581 DebugLoc dl = N->getDebugLoc();
1583 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1584 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1585 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1586 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1587 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1588 SDValue LL, LH, RL, RH;
1589 GetExpandedInteger(N->getOperand(0), LL, LH);
1590 GetExpandedInteger(N->getOperand(1), RL, RH);
1591 unsigned OuterBitSize = VT.getSizeInBits();
1592 unsigned InnerBitSize = NVT.getSizeInBits();
1593 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1594 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1596 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1597 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1598 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1599 // The inputs are both zero-extended.
1601 // We can emit a umul_lohi.
1602 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1603 Hi = SDValue(Lo.getNode(), 1);
1607 // We can emit a mulhu+mul.
1608 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1609 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1613 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1614 // The input values are both sign-extended.
1616 // We can emit a smul_lohi.
1617 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1618 Hi = SDValue(Lo.getNode(), 1);
1622 // We can emit a mulhs+mul.
1623 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1624 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1629 // Lo,Hi = umul LHS, RHS.
1630 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1631 DAG.getVTList(NVT, NVT), LL, RL);
1633 Hi = UMulLOHI.getValue(1);
1634 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1635 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1636 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1637 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1641 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1642 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1643 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1644 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1645 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1646 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1651 // If nothing else, we can make a libcall.
1652 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1654 LC = RTLIB::MUL_I16;
1655 else if (VT == MVT::i32)
1656 LC = RTLIB::MUL_I32;
1657 else if (VT == MVT::i64)
1658 LC = RTLIB::MUL_I64;
1659 else if (VT == MVT::i128)
1660 LC = RTLIB::MUL_I128;
1661 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1663 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1664 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1667 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1668 SDValue &Lo, SDValue &Hi) {
1669 MVT VT = N->getValueType(0);
1670 DebugLoc dl = N->getDebugLoc();
1672 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1674 LC = RTLIB::SDIV_I32;
1675 else if (VT == MVT::i64)
1676 LC = RTLIB::SDIV_I64;
1677 else if (VT == MVT::i128)
1678 LC = RTLIB::SDIV_I128;
1679 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1681 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1682 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1685 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1686 SDValue &Lo, SDValue &Hi) {
1687 MVT VT = N->getValueType(0);
1688 DebugLoc dl = N->getDebugLoc();
1690 // If we can emit an efficient shift operation, do so now. Check to see if
1691 // the RHS is a constant.
1692 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1693 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1695 // If we can determine that the high bit of the shift is zero or one, even if
1696 // the low bits are variable, emit this shift in an optimized form.
1697 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1700 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1702 if (N->getOpcode() == ISD::SHL) {
1703 PartsOpc = ISD::SHL_PARTS;
1704 } else if (N->getOpcode() == ISD::SRL) {
1705 PartsOpc = ISD::SRL_PARTS;
1707 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1708 PartsOpc = ISD::SRA_PARTS;
1711 // Next check to see if the target supports this SHL_PARTS operation or if it
1712 // will custom expand it.
1713 MVT NVT = TLI.getTypeToTransformTo(VT);
1714 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1715 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1716 Action == TargetLowering::Custom) {
1717 // Expand the subcomponents.
1719 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1721 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1722 MVT VT = LHSL.getValueType();
1723 Lo = DAG.getNode(PartsOpc, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1724 Hi = Lo.getValue(1);
1728 // Otherwise, emit a libcall.
1729 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1731 if (N->getOpcode() == ISD::SHL) {
1732 isSigned = false; /*sign irrelevant*/
1734 LC = RTLIB::SHL_I16;
1735 else if (VT == MVT::i32)
1736 LC = RTLIB::SHL_I32;
1737 else if (VT == MVT::i64)
1738 LC = RTLIB::SHL_I64;
1739 else if (VT == MVT::i128)
1740 LC = RTLIB::SHL_I128;
1741 } else if (N->getOpcode() == ISD::SRL) {
1744 LC = RTLIB::SRL_I16;
1745 else if (VT == MVT::i32)
1746 LC = RTLIB::SRL_I32;
1747 else if (VT == MVT::i64)
1748 LC = RTLIB::SRL_I64;
1749 else if (VT == MVT::i128)
1750 LC = RTLIB::SRL_I128;
1752 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1755 LC = RTLIB::SRA_I16;
1756 else if (VT == MVT::i32)
1757 LC = RTLIB::SRA_I32;
1758 else if (VT == MVT::i64)
1759 LC = RTLIB::SRA_I64;
1760 else if (VT == MVT::i128)
1761 LC = RTLIB::SRA_I128;
1763 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1765 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1766 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1769 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1770 SDValue &Lo, SDValue &Hi) {
1771 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1772 DebugLoc dl = N->getDebugLoc();
1773 SDValue Op = N->getOperand(0);
1774 if (Op.getValueType().bitsLE(NVT)) {
1775 // The low part is sign extension of the input (degenerates to a copy).
1776 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1777 // The high part is obtained by SRA'ing all but one of the bits of low part.
1778 unsigned LoSize = NVT.getSizeInBits();
1779 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1780 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1782 // For example, extension of an i48 to an i64. The operand type necessarily
1783 // promotes to the result type, so will end up being expanded too.
1784 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1785 "Only know how to promote this result!");
1786 SDValue Res = GetPromotedInteger(Op);
1787 assert(Res.getValueType() == N->getValueType(0) &&
1788 "Operand over promoted?");
1789 // Split the promoted operand. This will simplify when it is expanded.
1790 SplitInteger(Res, Lo, Hi);
1791 unsigned ExcessBits =
1792 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1793 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1794 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1798 void DAGTypeLegalizer::
1799 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1800 DebugLoc dl = N->getDebugLoc();
1801 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1802 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1804 if (EVT.bitsLE(Lo.getValueType())) {
1805 // sext_inreg the low part if needed.
1806 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1809 // The high part gets the sign extension from the lo-part. This handles
1810 // things like sextinreg V:i64 from i8.
1811 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1812 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1813 TLI.getPointerTy()));
1815 // For example, extension of an i48 to an i64. Leave the low part alone,
1816 // sext_inreg the high part.
1817 unsigned ExcessBits =
1818 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1819 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1820 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1824 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1825 SDValue &Lo, SDValue &Hi) {
1826 MVT VT = N->getValueType(0);
1827 DebugLoc dl = N->getDebugLoc();
1829 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1831 LC = RTLIB::SREM_I32;
1832 else if (VT == MVT::i64)
1833 LC = RTLIB::SREM_I64;
1834 else if (VT == MVT::i128)
1835 LC = RTLIB::SREM_I128;
1836 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1838 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1839 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1842 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1843 SDValue &Lo, SDValue &Hi) {
1844 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1845 DebugLoc dl = N->getDebugLoc();
1846 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1847 Hi = DAG.getNode(ISD::SRL, dl,
1848 N->getOperand(0).getValueType(), N->getOperand(0),
1849 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1850 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1853 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1854 SDValue &Lo, SDValue &Hi) {
1855 MVT VT = N->getValueType(0);
1856 DebugLoc dl = N->getDebugLoc();
1858 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1860 LC = RTLIB::UDIV_I32;
1861 else if (VT == MVT::i64)
1862 LC = RTLIB::UDIV_I64;
1863 else if (VT == MVT::i128)
1864 LC = RTLIB::UDIV_I128;
1865 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1867 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1868 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1871 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1872 SDValue &Lo, SDValue &Hi) {
1873 MVT VT = N->getValueType(0);
1874 DebugLoc dl = N->getDebugLoc();
1876 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1878 LC = RTLIB::UREM_I32;
1879 else if (VT == MVT::i64)
1880 LC = RTLIB::UREM_I64;
1881 else if (VT == MVT::i128)
1882 LC = RTLIB::UREM_I128;
1883 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1885 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1886 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1889 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1890 SDValue &Lo, SDValue &Hi) {
1891 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1892 DebugLoc dl = N->getDebugLoc();
1893 SDValue Op = N->getOperand(0);
1894 if (Op.getValueType().bitsLE(NVT)) {
1895 // The low part is zero extension of the input (degenerates to a copy).
1896 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1897 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1899 // For example, extension of an i48 to an i64. The operand type necessarily
1900 // promotes to the result type, so will end up being expanded too.
1901 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1902 "Only know how to promote this result!");
1903 SDValue Res = GetPromotedInteger(Op);
1904 assert(Res.getValueType() == N->getValueType(0) &&
1905 "Operand over promoted?");
1906 // Split the promoted operand. This will simplify when it is expanded.
1907 SplitInteger(Res, Lo, Hi);
1908 unsigned ExcessBits =
1909 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1910 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
1915 //===----------------------------------------------------------------------===//
1916 // Integer Operand Expansion
1917 //===----------------------------------------------------------------------===//
1919 /// ExpandIntegerOperand - This method is called when the specified operand of
1920 /// the specified node is found to need expansion. At this point, all of the
1921 /// result types of the node are known to be legal, but other operands of the
1922 /// node may need promotion or expansion as well as the specified one.
1923 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1924 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1925 SDValue Res = SDValue();
1927 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
1930 switch (N->getOpcode()) {
1933 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1934 N->dump(&DAG); cerr << "\n";
1936 assert(0 && "Do not know how to expand this operator's operand!");
1939 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1940 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1941 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1942 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1943 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1944 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1945 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1946 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1947 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1948 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
1949 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1950 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1956 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
1959 // If the result is null, the sub-method took care of registering results etc.
1960 if (!Res.getNode()) return false;
1962 // If the result is N, the sub-method updated N in place. Tell the legalizer
1964 if (Res.getNode() == N)
1967 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1968 "Invalid operand expansion");
1970 ReplaceValueWith(SDValue(N, 0), Res);
1974 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1975 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1976 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1978 ISD::CondCode &CCCode,
1980 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1981 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1982 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1984 MVT VT = NewLHS.getValueType();
1986 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1987 if (RHSLo == RHSHi) {
1988 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1989 if (RHSCST->isAllOnesValue()) {
1990 // Equality comparison to -1.
1991 NewLHS = DAG.getNode(ISD::AND, dl,
1992 LHSLo.getValueType(), LHSLo, LHSHi);
1999 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2000 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2001 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2002 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2006 // If this is a comparison of the sign bit, just look at the top part.
2008 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2009 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2010 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2016 // FIXME: This generated code sucks.
2017 ISD::CondCode LowCC;
2019 default: assert(0 && "Unknown integer setcc!");
2021 case ISD::SETULT: LowCC = ISD::SETULT; break;
2023 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2025 case ISD::SETULE: LowCC = ISD::SETULE; break;
2027 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2030 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2031 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2032 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2034 // NOTE: on targets without efficient SELECT of bools, we can always use
2035 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2036 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2038 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2039 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2040 if (!Tmp1.getNode())
2041 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2042 LHSLo, RHSLo, LowCC);
2043 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2044 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2045 if (!Tmp2.getNode())
2046 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2047 TLI.getSetCCResultType(LHSHi.getValueType()),
2048 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2050 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2051 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2052 if ((Tmp1C && Tmp1C->isNullValue()) ||
2053 (Tmp2C && Tmp2C->isNullValue() &&
2054 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2055 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2056 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2057 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2058 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2059 // low part is known false, returns high part.
2060 // For LE / GE, if high part is known false, ignore the low part.
2061 // For LT / GT, if high part is known true, ignore the low part.
2067 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2068 LHSHi, RHSHi, ISD::SETEQ, false,
2069 DagCombineInfo, dl);
2070 if (!NewLHS.getNode())
2071 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2072 LHSHi, RHSHi, ISD::SETEQ);
2073 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2074 NewLHS, Tmp1, Tmp2);
2078 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2079 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2080 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2081 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2083 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2084 // against zero to select between true and false values.
2085 if (NewRHS.getNode() == 0) {
2086 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2087 CCCode = ISD::SETNE;
2090 // Update N to have the operands specified.
2091 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2092 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2096 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2097 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2098 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2099 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2101 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2102 // against zero to select between true and false values.
2103 if (NewRHS.getNode() == 0) {
2104 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2105 CCCode = ISD::SETNE;
2108 // Update N to have the operands specified.
2109 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2110 N->getOperand(2), N->getOperand(3),
2111 DAG.getCondCode(CCCode));
2114 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2115 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2116 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2117 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2119 // If ExpandSetCCOperands returned a scalar, use it.
2120 if (NewRHS.getNode() == 0) {
2121 assert(NewLHS.getValueType() == N->getValueType(0) &&
2122 "Unexpected setcc expansion!");
2126 // Otherwise, update N to have the operands specified.
2127 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2128 DAG.getCondCode(CCCode));
2131 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2132 // The value being shifted is legal, but the shift amount is too big.
2133 // It follows that either the result of the shift is undefined, or the
2134 // upper half of the shift amount is zero. Just use the lower half.
2136 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2137 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2140 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2141 SDValue Op = N->getOperand(0);
2142 MVT DstVT = N->getValueType(0);
2143 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2144 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2145 "Don't know how to expand this SINT_TO_FP!");
2146 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2149 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2150 if (ISD::isNormalStore(N))
2151 return ExpandOp_NormalStore(N, OpNo);
2153 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2154 assert(OpNo == 1 && "Can only expand the stored value so far");
2156 MVT VT = N->getOperand(1).getValueType();
2157 MVT NVT = TLI.getTypeToTransformTo(VT);
2158 SDValue Ch = N->getChain();
2159 SDValue Ptr = N->getBasePtr();
2160 int SVOffset = N->getSrcValueOffset();
2161 unsigned Alignment = N->getAlignment();
2162 bool isVolatile = N->isVolatile();
2163 DebugLoc dl = N->getDebugLoc();
2166 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2168 if (N->getMemoryVT().bitsLE(NVT)) {
2169 GetExpandedInteger(N->getValue(), Lo, Hi);
2170 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2171 N->getMemoryVT(), isVolatile, Alignment);
2172 } else if (TLI.isLittleEndian()) {
2173 // Little-endian - low bits are at low addresses.
2174 GetExpandedInteger(N->getValue(), Lo, Hi);
2176 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2177 isVolatile, Alignment);
2179 unsigned ExcessBits =
2180 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2181 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2183 // Increment the pointer to the other half.
2184 unsigned IncrementSize = NVT.getSizeInBits()/8;
2185 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2186 DAG.getIntPtrConstant(IncrementSize));
2187 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2188 SVOffset+IncrementSize, NEVT,
2189 isVolatile, MinAlign(Alignment, IncrementSize));
2190 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2192 // Big-endian - high bits are at low addresses. Favor aligned stores at
2193 // the cost of some bit-fiddling.
2194 GetExpandedInteger(N->getValue(), Lo, Hi);
2196 MVT EVT = N->getMemoryVT();
2197 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2198 unsigned IncrementSize = NVT.getSizeInBits()/8;
2199 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2200 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2202 if (ExcessBits < NVT.getSizeInBits()) {
2203 // Transfer high bits from the top of Lo to the bottom of Hi.
2204 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2205 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2206 TLI.getPointerTy()));
2207 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2208 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2209 DAG.getConstant(ExcessBits,
2210 TLI.getPointerTy())));
2213 // Store both the high bits and maybe some of the low bits.
2214 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2215 SVOffset, HiVT, isVolatile, Alignment);
2217 // Increment the pointer to the other half.
2218 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2219 DAG.getIntPtrConstant(IncrementSize));
2220 // Store the lowest ExcessBits bits in the second half.
2221 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2222 SVOffset+IncrementSize,
2223 MVT::getIntegerVT(ExcessBits),
2224 isVolatile, MinAlign(Alignment, IncrementSize));
2225 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2229 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2231 GetExpandedInteger(N->getOperand(0), InL, InH);
2232 // Just truncate the low part of the source.
2233 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2236 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2237 SDValue Op = N->getOperand(0);
2238 MVT SrcVT = Op.getValueType();
2239 MVT DstVT = N->getValueType(0);
2240 DebugLoc dl = N->getDebugLoc();
2242 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2243 // Do a signed conversion then adjust the result.
2244 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2245 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2247 // The result of the signed conversion needs adjusting if the 'sign bit' of
2248 // the incoming integer was set. To handle this, we dynamically test to see
2249 // if it is set, and, if so, add a fudge factor.
2251 const uint64_t F32TwoE32 = 0x4F800000ULL;
2252 const uint64_t F32TwoE64 = 0x5F800000ULL;
2253 const uint64_t F32TwoE128 = 0x7F800000ULL;
2256 if (SrcVT == MVT::i32)
2257 FF = APInt(32, F32TwoE32);
2258 else if (SrcVT == MVT::i64)
2259 FF = APInt(32, F32TwoE64);
2260 else if (SrcVT == MVT::i128)
2261 FF = APInt(32, F32TwoE128);
2263 assert(false && "Unsupported UINT_TO_FP!");
2265 // Check whether the sign bit is set.
2267 GetExpandedInteger(Op, Lo, Hi);
2268 SDValue SignSet = DAG.getSetCC(dl,
2269 TLI.getSetCCResultType(Hi.getValueType()),
2270 Hi, DAG.getConstant(0, Hi.getValueType()),
2273 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2274 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2275 TLI.getPointerTy());
2277 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2278 SDValue Zero = DAG.getIntPtrConstant(0);
2279 SDValue Four = DAG.getIntPtrConstant(4);
2280 if (TLI.isBigEndian()) std::swap(Zero, Four);
2281 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2283 unsigned Alignment =
2284 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2285 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2286 Alignment = std::min(Alignment, 4u);
2288 // Load the value out, extending it from f32 to the destination float type.
2289 // FIXME: Avoid the extend by constructing the right constant pool?
2290 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2291 FudgePtr, NULL, 0, MVT::f32,
2293 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2296 // Otherwise, use a libcall.
2297 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2298 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2299 "Don't know how to expand this UINT_TO_FP!");
2300 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);