1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Res = SDValue();
36 // See if the target wants to custom expand this node.
37 if (CustomLowerResults(N, N->getValueType(ResNo), true))
40 switch (N->getOpcode()) {
43 cerr << "PromoteIntegerResult #" << ResNo << ": ";
44 N->dump(&DAG); cerr << "\n";
46 assert(0 && "Do not know how to promote this operator!");
48 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
49 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
50 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
51 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
52 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
53 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
54 case ISD::CONVERT_RNDSAT:
55 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
56 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
57 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
58 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
59 case ISD::EXTRACT_VECTOR_ELT:
60 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
61 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
62 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
63 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
64 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
65 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
66 case ISD::SIGN_EXTEND_INREG:
67 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
68 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
69 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
70 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
71 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
72 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
74 case ISD::SIGN_EXTEND:
75 case ISD::ZERO_EXTEND:
76 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
79 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
86 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
89 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
92 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
95 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
97 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
99 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
101 case ISD::ATOMIC_LOAD_ADD:
102 case ISD::ATOMIC_LOAD_SUB:
103 case ISD::ATOMIC_LOAD_AND:
104 case ISD::ATOMIC_LOAD_OR:
105 case ISD::ATOMIC_LOAD_XOR:
106 case ISD::ATOMIC_LOAD_NAND:
107 case ISD::ATOMIC_LOAD_MIN:
108 case ISD::ATOMIC_LOAD_MAX:
109 case ISD::ATOMIC_LOAD_UMIN:
110 case ISD::ATOMIC_LOAD_UMAX:
111 case ISD::ATOMIC_SWAP:
112 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
114 case ISD::ATOMIC_CMP_SWAP:
115 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
118 // If the result is null then the sub-method took care of registering it.
120 SetPromotedInteger(SDValue(N, ResNo), Res);
123 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
124 // Sign-extend the new bits, and continue the assertion.
125 SDValue Op = SExtPromotedInteger(N->getOperand(0));
126 return DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, N->getOperand(1));
129 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
130 // Zero the new bits, and continue the assertion.
131 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
132 return DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, N->getOperand(1));
135 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
136 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
137 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(),
138 N->getChain(), N->getBasePtr(),
139 Op2, N->getSrcValue(), N->getAlignment());
140 // Legalized the chain result - switch anything that used the old chain to
142 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
146 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
147 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
148 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
149 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getMemoryVT(),
150 N->getChain(), N->getBasePtr(),
151 Op2, Op3, N->getSrcValue(), N->getAlignment());
152 // Legalized the chain result - switch anything that used the old chain to
154 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
158 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
159 SDValue InOp = N->getOperand(0);
160 MVT InVT = InOp.getValueType();
161 MVT NInVT = TLI.getTypeToTransformTo(InVT);
162 MVT OutVT = N->getValueType(0);
163 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
165 switch (getTypeAction(InVT)) {
167 assert(false && "Unknown type action!");
172 if (NOutVT.bitsEq(NInVT))
173 // The input promotes to the same size. Convert the promoted value.
174 return DAG.getNode(ISD::BIT_CONVERT, NOutVT, GetPromotedInteger(InOp));
177 // Promote the integer operand by hand.
178 return DAG.getNode(ISD::ANY_EXTEND, NOutVT, GetSoftenedFloat(InOp));
182 case ScalarizeVector:
183 // Convert the element to an integer and promote it by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, NOutVT,
185 BitConvertToInteger(GetScalarizedVector(InOp)));
187 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
188 // pieces of the input into integers and reassemble in the final type.
190 GetSplitVector(N->getOperand(0), Lo, Hi);
191 Lo = BitConvertToInteger(Lo);
192 Hi = BitConvertToInteger(Hi);
194 if (TLI.isBigEndian())
197 InOp = DAG.getNode(ISD::ANY_EXTEND,
198 MVT::getIntegerVT(NOutVT.getSizeInBits()),
199 JoinIntegers(Lo, Hi));
200 return DAG.getNode(ISD::BIT_CONVERT, NOutVT, InOp);
203 if (OutVT.bitsEq(NInVT))
204 // The input is widened to the same size. Convert to the widened value.
205 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetWidenedVector(InOp));
208 // Otherwise, lower the bit-convert to a store/load from the stack.
209 // Create the stack frame object. Make sure it is aligned for both
210 // the source and destination types.
211 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
213 // Emit a store to the stack slot.
214 SDValue Store = DAG.getStore(DAG.getEntryNode(), InOp, FIPtr, NULL, 0);
216 // Result is an extending load from the stack slot.
217 return DAG.getExtLoad(ISD::EXTLOAD, NOutVT, Store, FIPtr, NULL, 0, OutVT);
220 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
221 SDValue Op = GetPromotedInteger(N->getOperand(0));
222 MVT OVT = N->getValueType(0);
223 MVT NVT = Op.getValueType();
225 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
226 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
227 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
230 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
231 // The pair element type may be legal, or may not promote to the same type as
232 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
233 return DAG.getNode(ISD::ANY_EXTEND,
234 TLI.getTypeToTransformTo(N->getValueType(0)),
235 JoinIntegers(N->getOperand(0), N->getOperand(1)));
238 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
239 MVT VT = N->getValueType(0);
240 // Zero extend things like i1, sign extend everything else. It shouldn't
241 // matter in theory which one we pick, but this tends to give better code?
242 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
243 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
245 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
249 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
250 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
251 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
252 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
253 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
254 "can only promote integers");
255 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
256 return DAG.getConvertRndSat(OutVT, N->getOperand(0),
257 N->getOperand(1), N->getOperand(2),
258 N->getOperand(3), N->getOperand(4), CvtCode);
261 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
262 // Zero extend to the promoted type and do the count there.
263 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
264 MVT OVT = N->getValueType(0);
265 MVT NVT = Op.getValueType();
266 Op = DAG.getNode(ISD::CTLZ, NVT, Op);
267 // Subtract off the extra leading bits in the bigger type.
268 return DAG.getNode(ISD::SUB, NVT, Op,
269 DAG.getConstant(NVT.getSizeInBits() -
270 OVT.getSizeInBits(), NVT));
273 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
274 // Zero extend to the promoted type and do the count there.
275 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
276 return DAG.getNode(ISD::CTPOP, Op.getValueType(), Op);
279 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
280 SDValue Op = GetPromotedInteger(N->getOperand(0));
281 MVT OVT = N->getValueType(0);
282 MVT NVT = Op.getValueType();
283 // The count is the same in the promoted type except if the original
284 // value was zero. This can be handled by setting the bit just off
285 // the top of the original type.
286 APInt TopBit(NVT.getSizeInBits(), 0);
287 TopBit.set(OVT.getSizeInBits());
288 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
289 return DAG.getNode(ISD::CTTZ, NVT, Op);
292 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
293 MVT OldVT = N->getValueType(0);
294 SDValue OldVec = N->getOperand(0);
295 if (getTypeAction(OldVec.getValueType()) == WidenVector)
296 OldVec = GetWidenedVector(N->getOperand(0));
297 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
300 assert(!isTypeLegal(OldVec.getValueType()) &&
301 "Legal one-element vector of a type needing promotion!");
302 // It is tempting to follow GetScalarizedVector by a call to
303 // GetPromotedInteger, but this would be wrong because the
304 // scalarized value may not yet have been processed.
305 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
306 GetScalarizedVector(OldVec));
309 // Convert to a vector half as long with an element type of twice the width,
310 // for example <4 x i16> -> <2 x i32>.
311 assert(!(OldElts & 1) && "Odd length vectors not supported!");
312 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
313 assert(OldVT.isSimple() && NewVT.isSimple());
315 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
316 MVT::getVectorVT(NewVT, OldElts / 2),
319 // Extract the element at OldIdx / 2 from the new vector.
320 SDValue OldIdx = N->getOperand(1);
321 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
322 DAG.getConstant(1, TLI.getShiftAmountTy()));
323 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
325 // Select the appropriate half of the element: Lo if OldIdx was even,
328 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
329 DAG.getConstant(OldVT.getSizeInBits(),
330 TLI.getShiftAmountTy()));
331 if (TLI.isBigEndian())
334 // Extend to the promoted type.
335 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
336 SDValue Res = DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
337 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), Res);
340 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
341 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
342 unsigned NewOpc = N->getOpcode();
344 // If we're promoting a UINT to a larger size, check to see if the new node
345 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
346 // we can use that instead. This allows us to generate better code for
347 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
348 // legal, such as PowerPC.
349 if (N->getOpcode() == ISD::FP_TO_UINT &&
350 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
351 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
352 NewOpc = ISD::FP_TO_SINT;
354 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0));
356 // Assert that the converted value fits in the original type. If it doesn't
357 // (eg: because the value being converted is too big), then the result of the
358 // original operation was undefined anyway, so the assert is still correct.
359 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
360 ISD::AssertZext : ISD::AssertSext,
361 NVT, Res, DAG.getValueType(N->getValueType(0)));
364 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
365 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
367 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
368 SDValue Res = GetPromotedInteger(N->getOperand(0));
369 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
371 // If the result and operand types are the same after promotion, simplify
372 // to an in-register extension.
373 if (NVT == Res.getValueType()) {
374 // The high bits are not guaranteed to be anything. Insert an extend.
375 if (N->getOpcode() == ISD::SIGN_EXTEND)
376 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
377 DAG.getValueType(N->getOperand(0).getValueType()));
378 if (N->getOpcode() == ISD::ZERO_EXTEND)
379 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
380 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
385 // Otherwise, just extend the original operand all the way to the larger type.
386 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
389 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
390 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
391 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
392 ISD::LoadExtType ExtType =
393 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
394 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
395 N->getSrcValue(), N->getSrcValueOffset(),
396 N->getMemoryVT(), N->isVolatile(),
399 // Legalized the chain result - switch anything that used the old chain to
401 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
405 /// Promote the overflow flag of an overflowing arithmetic node.
406 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
407 // Simply change the return type of the boolean result.
408 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
409 MVT ValueVTs[] = { N->getValueType(0), NVT };
410 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
411 SDValue Res = DAG.getNode(N->getOpcode(), DAG.getVTList(ValueVTs, 2), Ops, 2);
413 // Modified the sum result - switch anything that used the old sum to use
415 ReplaceValueWith(SDValue(N, 0), Res);
417 return SDValue(Res.getNode(), 1);
420 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
422 return PromoteIntRes_Overflow(N);
424 // The operation overflowed iff the result in the larger type is not the
425 // sign extension of its truncation to the original type.
426 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
427 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
428 MVT OVT = N->getOperand(0).getValueType();
429 MVT NVT = LHS.getValueType();
431 // Do the arithmetic in the larger type.
432 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
433 SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS);
435 // Calculate the overflow flag: sign extend the arithmetic result from
436 // the original type.
437 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
438 DAG.getValueType(OVT));
439 // Overflowed if and only if this is not equal to Res.
440 Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE);
442 // Use the calculated overflow everywhere.
443 ReplaceValueWith(SDValue(N, 1), Ofl);
448 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
449 // Sign extend the input.
450 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
451 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
452 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
455 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
456 SDValue LHS = GetPromotedInteger(N->getOperand(1));
457 SDValue RHS = GetPromotedInteger(N->getOperand(2));
458 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
461 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
462 SDValue LHS = GetPromotedInteger(N->getOperand(2));
463 SDValue RHS = GetPromotedInteger(N->getOperand(3));
464 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
465 N->getOperand(1), LHS, RHS, N->getOperand(4));
468 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
469 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
470 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
472 // Get the SETCC result using the canonical SETCC type.
473 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
474 N->getOperand(1), N->getOperand(2));
476 // Convert to the expected type.
477 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
478 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
479 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
482 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
483 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
484 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
487 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
488 SDValue Op = GetPromotedInteger(N->getOperand(0));
489 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
493 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
494 // The input may have strange things in the top bits of the registers, but
495 // these operations don't care. They may have weird bits going out, but
496 // that too is okay if they are integer operations.
497 SDValue LHS = GetPromotedInteger(N->getOperand(0));
498 SDValue RHS = GetPromotedInteger(N->getOperand(1));
499 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
503 // The input value must be properly sign extended.
504 SDValue Res = SExtPromotedInteger(N->getOperand(0));
505 return DAG.getNode(ISD::SRA, Res.getValueType(), Res, N->getOperand(1));
508 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
509 // The input value must be properly zero extended.
510 MVT VT = N->getValueType(0);
511 MVT NVT = TLI.getTypeToTransformTo(VT);
512 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
513 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
516 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
517 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
520 switch (getTypeAction(N->getOperand(0).getValueType())) {
521 default: assert(0 && "Unknown type action!");
524 Res = N->getOperand(0);
527 Res = GetPromotedInteger(N->getOperand(0));
531 // Truncate to NVT instead of VT
532 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
535 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
537 return PromoteIntRes_Overflow(N);
539 // The operation overflowed iff the result in the larger type is not the
540 // zero extension of its truncation to the original type.
541 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
542 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
543 MVT OVT = N->getOperand(0).getValueType();
544 MVT NVT = LHS.getValueType();
546 // Do the arithmetic in the larger type.
547 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
548 SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS);
550 // Calculate the overflow flag: zero extend the arithmetic result from
551 // the original type.
552 SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT);
553 // Overflowed if and only if this is not equal to Res.
554 Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE);
556 // Use the calculated overflow everywhere.
557 ReplaceValueWith(SDValue(N, 1), Ofl);
562 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
563 // Zero extend the input.
564 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
565 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
566 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
569 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
570 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
573 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
574 SDValue Chain = N->getOperand(0); // Get the chain.
575 SDValue Ptr = N->getOperand(1); // Get the pointer.
576 MVT VT = N->getValueType(0);
578 MVT RegVT = TLI.getRegisterType(VT);
579 unsigned NumRegs = TLI.getNumRegisters(VT);
580 // The argument is passed as NumRegs registers of type RegVT.
582 SmallVector<SDValue, 8> Parts(NumRegs);
583 for (unsigned i = 0; i < NumRegs; ++i) {
584 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2));
585 Chain = Parts[i].getValue(1);
588 // Handle endianness of the load.
589 if (TLI.isBigEndian())
590 std::reverse(Parts.begin(), Parts.end());
592 // Assemble the parts in the promoted type.
593 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
594 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]);
595 for (unsigned i = 1; i < NumRegs; ++i) {
596 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]);
597 // Shift it to the right position and "or" it in.
598 Part = DAG.getNode(ISD::SHL, NVT, Part,
599 DAG.getConstant(i * RegVT.getSizeInBits(),
600 TLI.getShiftAmountTy()));
601 Res = DAG.getNode(ISD::OR, NVT, Res, Part);
604 // Modified the chain result - switch anything that used the old chain to
606 ReplaceValueWith(SDValue(N, 1), Chain);
611 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
612 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
613 return PromoteIntRes_Overflow(N);
616 //===----------------------------------------------------------------------===//
617 // Integer Operand Promotion
618 //===----------------------------------------------------------------------===//
620 /// PromoteIntegerOperand - This method is called when the specified operand of
621 /// the specified node is found to need promotion. At this point, all of the
622 /// result types of the node are known to be legal, but other operands of the
623 /// node may need promotion or expansion as well as the specified one.
624 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
625 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
626 SDValue Res = SDValue();
628 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
631 switch (N->getOpcode()) {
634 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
635 N->dump(&DAG); cerr << "\n";
637 assert(0 && "Do not know how to promote this operator's operand!");
640 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
641 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
642 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
643 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
644 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
645 case ISD::CONVERT_RNDSAT:
646 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
647 case ISD::INSERT_VECTOR_ELT:
648 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
649 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
650 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
651 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
652 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
653 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
654 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
655 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
657 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
658 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
659 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
662 // If the result is null, the sub-method took care of registering results etc.
663 if (!Res.getNode()) return false;
665 // If the result is N, the sub-method updated N in place. Tell the legalizer
667 if (Res.getNode() == N)
670 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
671 "Invalid operand expansion");
673 ReplaceValueWith(SDValue(N, 0), Res);
677 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
678 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
679 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
680 ISD::CondCode CCCode) {
681 // We have to insert explicit sign or zero extends. Note that we could
682 // insert sign extends for ALL conditions, but zero extend is cheaper on
683 // many machines (an AND instead of two shifts), so prefer it.
685 default: assert(0 && "Unknown integer comparison!");
692 // ALL of these operations will work if we either sign or zero extend
693 // the operands (including the unsigned comparisons!). Zero extend is
694 // usually a simpler/cheaper operation, so prefer it.
695 NewLHS = ZExtPromotedInteger(NewLHS);
696 NewRHS = ZExtPromotedInteger(NewRHS);
702 NewLHS = SExtPromotedInteger(NewLHS);
703 NewRHS = SExtPromotedInteger(NewRHS);
708 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
709 SDValue Op = GetPromotedInteger(N->getOperand(0));
710 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
713 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
714 assert(OpNo == 2 && "Don't know how to promote this operand!");
716 SDValue LHS = N->getOperand(2);
717 SDValue RHS = N->getOperand(3);
718 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
720 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
722 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
723 N->getOperand(1), LHS, RHS, N->getOperand(4));
726 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
727 assert(OpNo == 1 && "only know how to promote condition");
729 // Promote all the way up to the canonical SetCC type.
730 MVT SVT = TLI.getSetCCResultType(MVT::Other);
731 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
733 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
734 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
738 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
739 // Since the result type is legal, the operands must promote to it.
740 MVT OVT = N->getOperand(0).getValueType();
741 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
742 SDValue Hi = GetPromotedInteger(N->getOperand(1));
743 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
745 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
746 DAG.getConstant(OVT.getSizeInBits(),
747 TLI.getShiftAmountTy()));
748 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
751 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
752 // The vector type is legal but the element type is not. This implies
753 // that the vector is a power-of-two in length and that the element
754 // type does not have a strange size (eg: it is not i1).
755 MVT VecVT = N->getValueType(0);
756 unsigned NumElts = VecVT.getVectorNumElements();
757 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
759 // Build a vector of half the length out of elements of twice the bitwidth.
760 // For example <4 x i16> -> <2 x i32>.
761 MVT OldVT = N->getOperand(0).getValueType();
762 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
763 assert(OldVT.isSimple() && NewVT.isSimple());
765 std::vector<SDValue> NewElts;
766 NewElts.reserve(NumElts/2);
768 for (unsigned i = 0; i < NumElts; i += 2) {
769 // Combine two successive elements into one promoted element.
770 SDValue Lo = N->getOperand(i);
771 SDValue Hi = N->getOperand(i+1);
772 if (TLI.isBigEndian())
774 NewElts.push_back(JoinIntegers(Lo, Hi));
777 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
778 MVT::getVectorVT(NewVT, NewElts.size()),
779 &NewElts[0], NewElts.size());
781 // Convert the new vector to the old vector type.
782 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
785 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
786 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
787 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
788 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
789 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
790 "can only promote integer arguments");
791 SDValue InOp = GetPromotedInteger(N->getOperand(0));
792 return DAG.getConvertRndSat(N->getValueType(0), InOp,
793 N->getOperand(1), N->getOperand(2),
794 N->getOperand(3), N->getOperand(4), CvtCode);
797 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
800 // Promote the inserted value. This is valid because the type does not
801 // have to match the vector element type.
803 // Check that any extra bits introduced will be truncated away.
804 assert(N->getOperand(1).getValueType().getSizeInBits() >=
805 N->getValueType(0).getVectorElementType().getSizeInBits() &&
806 "Type of inserted value narrower than vector element type!");
807 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
808 GetPromotedInteger(N->getOperand(1)),
812 assert(OpNo == 2 && "Different operand and result vector types?");
814 // Promote the index.
815 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
816 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
817 N->getOperand(1), Idx);
820 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
822 NewOps[0] = N->getOperand(0);
823 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
824 SDValue Flag = GetPromotedInteger(N->getOperand(i));
825 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
827 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
828 array_lengthof(NewOps));
831 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
832 assert(OpNo == 0 && "Only know how to promote condition");
834 // Promote all the way up to the canonical SetCC type.
835 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
836 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
838 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
839 N->getOperand(1), N->getOperand(2));
842 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
843 assert(OpNo == 0 && "Don't know how to promote this operand!");
845 SDValue LHS = N->getOperand(0);
846 SDValue RHS = N->getOperand(1);
847 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
849 // The CC (#4) and the possible return values (#2 and #3) have legal types.
850 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
851 N->getOperand(3), N->getOperand(4));
854 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
855 assert(OpNo == 0 && "Don't know how to promote this operand!");
857 SDValue LHS = N->getOperand(0);
858 SDValue RHS = N->getOperand(1);
859 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
861 // The CC (#2) is always legal.
862 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
865 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
866 SDValue Op = GetPromotedInteger(N->getOperand(0));
867 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
868 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
869 Op, DAG.getValueType(N->getOperand(0).getValueType()));
872 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
873 return DAG.UpdateNodeOperands(SDValue(N, 0),
874 SExtPromotedInteger(N->getOperand(0)));
877 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
878 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
879 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
880 int SVOffset = N->getSrcValueOffset();
881 unsigned Alignment = N->getAlignment();
882 bool isVolatile = N->isVolatile();
884 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
886 // Truncate the value and store the result.
887 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
888 SVOffset, N->getMemoryVT(),
889 isVolatile, Alignment);
892 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
893 SDValue Op = GetPromotedInteger(N->getOperand(0));
894 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
897 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
898 return DAG.UpdateNodeOperands(SDValue(N, 0),
899 ZExtPromotedInteger(N->getOperand(0)));
902 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
903 SDValue Op = GetPromotedInteger(N->getOperand(0));
904 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
905 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
909 //===----------------------------------------------------------------------===//
910 // Integer Result Expansion
911 //===----------------------------------------------------------------------===//
913 /// ExpandIntegerResult - This method is called when the specified result of the
914 /// specified node is found to need expansion. At this point, the node may also
915 /// have invalid operands or may have other results that need promotion, we just
916 /// know that (at least) one result needs expansion.
917 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
918 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
922 // See if the target wants to custom expand this node.
923 if (CustomLowerResults(N, N->getValueType(ResNo), true))
926 switch (N->getOpcode()) {
929 cerr << "ExpandIntegerResult #" << ResNo << ": ";
930 N->dump(&DAG); cerr << "\n";
932 assert(0 && "Do not know how to expand the result of this operator!");
935 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
936 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
937 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
938 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
940 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
941 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
942 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
943 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
944 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
946 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
947 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
948 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
949 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
950 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
951 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
952 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
953 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
954 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
955 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
956 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
957 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
958 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
959 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
960 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
961 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
962 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
963 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
964 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
965 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
969 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
972 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
975 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
978 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
982 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
985 // If Lo/Hi is null, the sub-method took care of registering results etc.
987 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
990 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
991 /// and the shift amount is a constant 'Amt'. Expand the operation.
992 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
993 SDValue &Lo, SDValue &Hi) {
994 // Expand the incoming operand to be shifted, so that we have its parts
996 GetExpandedInteger(N->getOperand(0), InL, InH);
998 MVT NVT = InL.getValueType();
999 unsigned VTBits = N->getValueType(0).getSizeInBits();
1000 unsigned NVTBits = NVT.getSizeInBits();
1001 MVT ShTy = N->getOperand(1).getValueType();
1003 if (N->getOpcode() == ISD::SHL) {
1005 Lo = Hi = DAG.getConstant(0, NVT);
1006 } else if (Amt > NVTBits) {
1007 Lo = DAG.getConstant(0, NVT);
1008 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1009 } else if (Amt == NVTBits) {
1010 Lo = DAG.getConstant(0, NVT);
1012 } else if (Amt == 1 &&
1013 TLI.isOperationLegalOrCustom(ISD::ADDC,
1014 TLI.getTypeToExpandTo(NVT))) {
1015 // Emit this X << 1 as X+X.
1016 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1017 SDValue LoOps[2] = { InL, InL };
1018 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1019 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1020 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1022 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1023 Hi = DAG.getNode(ISD::OR, NVT,
1024 DAG.getNode(ISD::SHL, NVT, InH,
1025 DAG.getConstant(Amt, ShTy)),
1026 DAG.getNode(ISD::SRL, NVT, InL,
1027 DAG.getConstant(NVTBits-Amt, ShTy)));
1032 if (N->getOpcode() == ISD::SRL) {
1034 Lo = DAG.getConstant(0, NVT);
1035 Hi = DAG.getConstant(0, NVT);
1036 } else if (Amt > NVTBits) {
1037 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1038 Hi = DAG.getConstant(0, NVT);
1039 } else if (Amt == NVTBits) {
1041 Hi = DAG.getConstant(0, NVT);
1043 Lo = DAG.getNode(ISD::OR, NVT,
1044 DAG.getNode(ISD::SRL, NVT, InL,
1045 DAG.getConstant(Amt, ShTy)),
1046 DAG.getNode(ISD::SHL, NVT, InH,
1047 DAG.getConstant(NVTBits-Amt, ShTy)));
1048 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1053 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1055 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1056 DAG.getConstant(NVTBits-1, ShTy));
1057 } else if (Amt > NVTBits) {
1058 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1059 DAG.getConstant(Amt-NVTBits, ShTy));
1060 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1061 DAG.getConstant(NVTBits-1, ShTy));
1062 } else if (Amt == NVTBits) {
1064 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1065 DAG.getConstant(NVTBits-1, ShTy));
1067 Lo = DAG.getNode(ISD::OR, NVT,
1068 DAG.getNode(ISD::SRL, NVT, InL,
1069 DAG.getConstant(Amt, ShTy)),
1070 DAG.getNode(ISD::SHL, NVT, InH,
1071 DAG.getConstant(NVTBits-Amt, ShTy)));
1072 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1076 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1077 /// this shift based on knowledge of the high bit of the shift amount. If we
1078 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1080 bool DAGTypeLegalizer::
1081 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1082 SDValue Amt = N->getOperand(1);
1083 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1084 MVT ShTy = Amt.getValueType();
1085 unsigned ShBits = ShTy.getSizeInBits();
1086 unsigned NVTBits = NVT.getSizeInBits();
1087 assert(isPowerOf2_32(NVTBits) &&
1088 "Expanded integer type size not a power of two!");
1090 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1091 APInt KnownZero, KnownOne;
1092 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1094 // If we don't know anything about the high bits, exit.
1095 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1098 // Get the incoming operand to be shifted.
1100 GetExpandedInteger(N->getOperand(0), InL, InH);
1102 // If we know that any of the high bits of the shift amount are one, then we
1103 // can do this as a couple of simple shifts.
1104 if (KnownOne.intersects(HighBitMask)) {
1105 // Mask out the high bit, which we know is set.
1106 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1107 DAG.getConstant(~HighBitMask, ShTy));
1109 switch (N->getOpcode()) {
1110 default: assert(0 && "Unknown shift");
1112 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1113 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1116 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1117 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1120 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1121 DAG.getConstant(NVTBits-1, ShTy));
1122 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1128 // FIXME: This code is broken for shifts with a zero amount!
1129 // If we know that all of the high bits of the shift amount are zero, then we
1130 // can do this as a couple of simple shifts.
1131 if ((KnownZero & HighBitMask) == HighBitMask) {
1133 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1134 DAG.getConstant(NVTBits, ShTy),
1137 switch (N->getOpcode()) {
1138 default: assert(0 && "Unknown shift");
1139 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1141 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1144 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1145 Hi = DAG.getNode(ISD::OR, NVT,
1146 DAG.getNode(Op1, NVT, InH, Amt),
1147 DAG.getNode(Op2, NVT, InL, Amt2));
1155 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1156 SDValue &Lo, SDValue &Hi) {
1157 // Expand the subcomponents.
1158 SDValue LHSL, LHSH, RHSL, RHSH;
1159 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1160 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1162 MVT NVT = LHSL.getValueType();
1163 SDValue LoOps[2] = { LHSL, RHSL };
1164 SDValue HiOps[3] = { LHSH, RHSH };
1166 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1167 // them. TODO: Teach operation legalization how to expand unsupported
1168 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1169 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1170 // generate a value of this type in the expanded code sequence.
1172 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1173 ISD::ADDC : ISD::SUBC,
1174 TLI.getTypeToExpandTo(NVT));
1177 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1178 if (N->getOpcode() == ISD::ADD) {
1179 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1180 HiOps[2] = Lo.getValue(1);
1181 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1183 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1184 HiOps[2] = Lo.getValue(1);
1185 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1188 if (N->getOpcode() == ISD::ADD) {
1189 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
1190 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
1191 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1193 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
1194 DAG.getConstant(1, NVT),
1195 DAG.getConstant(0, NVT));
1196 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1198 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
1199 DAG.getConstant(1, NVT), Carry1);
1200 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
1202 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
1203 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
1205 DAG.getSetCC(TLI.getSetCCResultType(LoOps[0].getValueType()),
1206 LoOps[0], LoOps[1], ISD::SETULT);
1207 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
1208 DAG.getConstant(1, NVT),
1209 DAG.getConstant(0, NVT));
1210 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
1215 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1216 SDValue &Lo, SDValue &Hi) {
1217 // Expand the subcomponents.
1218 SDValue LHSL, LHSH, RHSL, RHSH;
1219 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1220 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1221 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1222 SDValue LoOps[2] = { LHSL, RHSL };
1223 SDValue HiOps[3] = { LHSH, RHSH };
1225 if (N->getOpcode() == ISD::ADDC) {
1226 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1227 HiOps[2] = Lo.getValue(1);
1228 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1230 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1231 HiOps[2] = Lo.getValue(1);
1232 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1235 // Legalized the flag result - switch anything that used the old flag to
1237 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1240 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1241 SDValue &Lo, SDValue &Hi) {
1242 // Expand the subcomponents.
1243 SDValue LHSL, LHSH, RHSL, RHSH;
1244 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1245 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1246 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1247 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1248 SDValue HiOps[3] = { LHSH, RHSH };
1250 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1251 HiOps[2] = Lo.getValue(1);
1252 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1254 // Legalized the flag result - switch anything that used the old flag to
1256 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1259 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1260 SDValue &Lo, SDValue &Hi) {
1261 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1262 SDValue Op = N->getOperand(0);
1263 if (Op.getValueType().bitsLE(NVT)) {
1264 // The low part is any extension of the input (which degenerates to a copy).
1265 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1266 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1268 // For example, extension of an i48 to an i64. The operand type necessarily
1269 // promotes to the result type, so will end up being expanded too.
1270 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1271 "Only know how to promote this result!");
1272 SDValue Res = GetPromotedInteger(Op);
1273 assert(Res.getValueType() == N->getValueType(0) &&
1274 "Operand over promoted?");
1275 // Split the promoted operand. This will simplify when it is expanded.
1276 SplitInteger(Res, Lo, Hi);
1280 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1281 SDValue &Lo, SDValue &Hi) {
1282 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1283 MVT NVT = Lo.getValueType();
1284 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1285 unsigned NVTBits = NVT.getSizeInBits();
1286 unsigned EVTBits = EVT.getSizeInBits();
1288 if (NVTBits < EVTBits) {
1289 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1290 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1292 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1293 // The high part replicates the sign bit of Lo, make it explicit.
1294 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1295 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1299 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1300 SDValue &Lo, SDValue &Hi) {
1301 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1302 MVT NVT = Lo.getValueType();
1303 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1304 unsigned NVTBits = NVT.getSizeInBits();
1305 unsigned EVTBits = EVT.getSizeInBits();
1307 if (NVTBits < EVTBits) {
1308 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1309 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1311 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1312 // The high part must be zero, make it explicit.
1313 Hi = DAG.getConstant(0, NVT);
1317 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1318 SDValue &Lo, SDValue &Hi) {
1319 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1320 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1321 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1324 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1325 SDValue &Lo, SDValue &Hi) {
1326 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1327 unsigned NBitWidth = NVT.getSizeInBits();
1328 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1329 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1330 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1333 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1334 SDValue &Lo, SDValue &Hi) {
1335 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1336 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1337 MVT NVT = Lo.getValueType();
1339 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Hi,
1340 DAG.getConstant(0, NVT), ISD::SETNE);
1342 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1343 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1345 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1346 DAG.getNode(ISD::ADD, NVT, LoLZ,
1347 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1348 Hi = DAG.getConstant(0, NVT);
1351 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1352 SDValue &Lo, SDValue &Hi) {
1353 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1354 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1355 MVT NVT = Lo.getValueType();
1356 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1357 DAG.getNode(ISD::CTPOP, NVT, Hi));
1358 Hi = DAG.getConstant(0, NVT);
1361 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1362 SDValue &Lo, SDValue &Hi) {
1363 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1364 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1365 MVT NVT = Lo.getValueType();
1367 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(NVT), Lo,
1368 DAG.getConstant(0, NVT), ISD::SETNE);
1370 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1371 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1373 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1374 DAG.getNode(ISD::ADD, NVT, HiLZ,
1375 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1376 Hi = DAG.getConstant(0, NVT);
1379 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1381 DebugLoc dl = N->getDebugLoc();
1382 MVT VT = N->getValueType(0);
1383 SDValue Op = N->getOperand(0);
1384 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1385 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1386 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1389 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1391 DebugLoc dl = N->getDebugLoc();
1392 MVT VT = N->getValueType(0);
1393 SDValue Op = N->getOperand(0);
1394 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1395 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1396 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1399 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1400 SDValue &Lo, SDValue &Hi) {
1401 if (ISD::isNormalLoad(N)) {
1402 ExpandRes_NormalLoad(N, Lo, Hi);
1406 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1408 MVT VT = N->getValueType(0);
1409 MVT NVT = TLI.getTypeToTransformTo(VT);
1410 SDValue Ch = N->getChain();
1411 SDValue Ptr = N->getBasePtr();
1412 ISD::LoadExtType ExtType = N->getExtensionType();
1413 int SVOffset = N->getSrcValueOffset();
1414 unsigned Alignment = N->getAlignment();
1415 bool isVolatile = N->isVolatile();
1417 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1419 if (N->getMemoryVT().bitsLE(NVT)) {
1420 MVT EVT = N->getMemoryVT();
1422 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1423 isVolatile, Alignment);
1425 // Remember the chain.
1426 Ch = Lo.getValue(1);
1428 if (ExtType == ISD::SEXTLOAD) {
1429 // The high part is obtained by SRA'ing all but one of the bits of the
1431 unsigned LoSize = Lo.getValueType().getSizeInBits();
1432 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1433 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1434 } else if (ExtType == ISD::ZEXTLOAD) {
1435 // The high part is just a zero.
1436 Hi = DAG.getConstant(0, NVT);
1438 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1439 // The high part is undefined.
1440 Hi = DAG.getNode(ISD::UNDEF, NVT);
1442 } else if (TLI.isLittleEndian()) {
1443 // Little-endian - low bits are at low addresses.
1444 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1445 isVolatile, Alignment);
1447 unsigned ExcessBits =
1448 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1449 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1451 // Increment the pointer to the other half.
1452 unsigned IncrementSize = NVT.getSizeInBits()/8;
1453 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1454 DAG.getIntPtrConstant(IncrementSize));
1455 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1456 SVOffset+IncrementSize, NEVT,
1457 isVolatile, MinAlign(Alignment, IncrementSize));
1459 // Build a factor node to remember that this load is independent of the
1461 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1464 // Big-endian - high bits are at low addresses. Favor aligned loads at
1465 // the cost of some bit-fiddling.
1466 MVT EVT = N->getMemoryVT();
1467 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1468 unsigned IncrementSize = NVT.getSizeInBits()/8;
1469 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1471 // Load both the high bits and maybe some of the low bits.
1472 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1473 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1474 isVolatile, Alignment);
1476 // Increment the pointer to the other half.
1477 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1478 DAG.getIntPtrConstant(IncrementSize));
1479 // Load the rest of the low bits.
1480 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1481 SVOffset+IncrementSize,
1482 MVT::getIntegerVT(ExcessBits),
1483 isVolatile, MinAlign(Alignment, IncrementSize));
1485 // Build a factor node to remember that this load is independent of the
1487 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1490 if (ExcessBits < NVT.getSizeInBits()) {
1491 // Transfer low bits from the bottom of Hi to the top of Lo.
1492 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1493 DAG.getNode(ISD::SHL, NVT, Hi,
1494 DAG.getConstant(ExcessBits,
1495 TLI.getShiftAmountTy())));
1496 // Move high bits to the right position in Hi.
1497 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1498 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1499 TLI.getShiftAmountTy()));
1503 // Legalized the chain result - switch anything that used the old chain to
1505 ReplaceValueWith(SDValue(N, 1), Ch);
1508 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1509 SDValue &Lo, SDValue &Hi) {
1510 SDValue LL, LH, RL, RH;
1511 GetExpandedInteger(N->getOperand(0), LL, LH);
1512 GetExpandedInteger(N->getOperand(1), RL, RH);
1513 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1514 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1517 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1518 SDValue &Lo, SDValue &Hi) {
1519 MVT VT = N->getValueType(0);
1520 MVT NVT = TLI.getTypeToTransformTo(VT);
1521 DebugLoc dl = N->getDebugLoc();
1523 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1524 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1525 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1526 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1527 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1528 SDValue LL, LH, RL, RH;
1529 GetExpandedInteger(N->getOperand(0), LL, LH);
1530 GetExpandedInteger(N->getOperand(1), RL, RH);
1531 unsigned OuterBitSize = VT.getSizeInBits();
1532 unsigned InnerBitSize = NVT.getSizeInBits();
1533 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1534 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1536 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1537 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1538 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1539 // The inputs are both zero-extended.
1541 // We can emit a umul_lohi.
1542 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1543 Hi = SDValue(Lo.getNode(), 1);
1547 // We can emit a mulhu+mul.
1548 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1549 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1553 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1554 // The input values are both sign-extended.
1556 // We can emit a smul_lohi.
1557 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1558 Hi = SDValue(Lo.getNode(), 1);
1562 // We can emit a mulhs+mul.
1563 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1564 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1569 // Lo,Hi = umul LHS, RHS.
1570 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1571 DAG.getVTList(NVT, NVT), LL, RL);
1573 Hi = UMulLOHI.getValue(1);
1574 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1575 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1576 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1577 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1581 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1582 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1583 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1584 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1585 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1586 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1591 // If nothing else, we can make a libcall.
1592 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1594 LC = RTLIB::MUL_I16;
1595 else if (VT == MVT::i32)
1596 LC = RTLIB::MUL_I32;
1597 else if (VT == MVT::i64)
1598 LC = RTLIB::MUL_I64;
1599 else if (VT == MVT::i128)
1600 LC = RTLIB::MUL_I128;
1601 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1603 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1604 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1607 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1608 SDValue &Lo, SDValue &Hi) {
1609 MVT VT = N->getValueType(0);
1610 DebugLoc dl = N->getDebugLoc();
1612 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1614 LC = RTLIB::SDIV_I32;
1615 else if (VT == MVT::i64)
1616 LC = RTLIB::SDIV_I64;
1617 else if (VT == MVT::i128)
1618 LC = RTLIB::SDIV_I128;
1619 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1621 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1622 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1625 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1626 SDValue &Lo, SDValue &Hi) {
1627 MVT VT = N->getValueType(0);
1628 DebugLoc dl = N->getDebugLoc();
1630 // If we can emit an efficient shift operation, do so now. Check to see if
1631 // the RHS is a constant.
1632 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1633 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1635 // If we can determine that the high bit of the shift is zero or one, even if
1636 // the low bits are variable, emit this shift in an optimized form.
1637 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1640 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1642 if (N->getOpcode() == ISD::SHL) {
1643 PartsOpc = ISD::SHL_PARTS;
1644 } else if (N->getOpcode() == ISD::SRL) {
1645 PartsOpc = ISD::SRL_PARTS;
1647 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1648 PartsOpc = ISD::SRA_PARTS;
1651 // Next check to see if the target supports this SHL_PARTS operation or if it
1652 // will custom expand it.
1653 MVT NVT = TLI.getTypeToTransformTo(VT);
1654 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1655 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1656 Action == TargetLowering::Custom) {
1657 // Expand the subcomponents.
1659 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1661 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1662 MVT VT = LHSL.getValueType();
1663 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1664 Hi = Lo.getValue(1);
1668 // Otherwise, emit a libcall.
1669 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1671 if (N->getOpcode() == ISD::SHL) {
1672 isSigned = false; /*sign irrelevant*/
1674 LC = RTLIB::SHL_I16;
1675 else if (VT == MVT::i32)
1676 LC = RTLIB::SHL_I32;
1677 else if (VT == MVT::i64)
1678 LC = RTLIB::SHL_I64;
1679 else if (VT == MVT::i128)
1680 LC = RTLIB::SHL_I128;
1681 } else if (N->getOpcode() == ISD::SRL) {
1684 LC = RTLIB::SRL_I16;
1685 else if (VT == MVT::i32)
1686 LC = RTLIB::SRL_I32;
1687 else if (VT == MVT::i64)
1688 LC = RTLIB::SRL_I64;
1689 else if (VT == MVT::i128)
1690 LC = RTLIB::SRL_I128;
1692 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1695 LC = RTLIB::SRA_I16;
1696 else if (VT == MVT::i32)
1697 LC = RTLIB::SRA_I32;
1698 else if (VT == MVT::i64)
1699 LC = RTLIB::SRA_I64;
1700 else if (VT == MVT::i128)
1701 LC = RTLIB::SRA_I128;
1703 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1705 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1706 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1709 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1710 SDValue &Lo, SDValue &Hi) {
1711 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1712 SDValue Op = N->getOperand(0);
1713 if (Op.getValueType().bitsLE(NVT)) {
1714 // The low part is sign extension of the input (degenerates to a copy).
1715 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1716 // The high part is obtained by SRA'ing all but one of the bits of low part.
1717 unsigned LoSize = NVT.getSizeInBits();
1718 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1719 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1721 // For example, extension of an i48 to an i64. The operand type necessarily
1722 // promotes to the result type, so will end up being expanded too.
1723 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1724 "Only know how to promote this result!");
1725 SDValue Res = GetPromotedInteger(Op);
1726 assert(Res.getValueType() == N->getValueType(0) &&
1727 "Operand over promoted?");
1728 // Split the promoted operand. This will simplify when it is expanded.
1729 SplitInteger(Res, Lo, Hi);
1730 unsigned ExcessBits =
1731 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1732 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1733 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1737 void DAGTypeLegalizer::
1738 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1739 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1740 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1742 if (EVT.bitsLE(Lo.getValueType())) {
1743 // sext_inreg the low part if needed.
1744 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1747 // The high part gets the sign extension from the lo-part. This handles
1748 // things like sextinreg V:i64 from i8.
1749 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1750 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1751 TLI.getShiftAmountTy()));
1753 // For example, extension of an i48 to an i64. Leave the low part alone,
1754 // sext_inreg the high part.
1755 unsigned ExcessBits =
1756 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1757 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1758 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1762 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1763 SDValue &Lo, SDValue &Hi) {
1764 MVT VT = N->getValueType(0);
1765 DebugLoc dl = N->getDebugLoc();
1767 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1769 LC = RTLIB::SREM_I32;
1770 else if (VT == MVT::i64)
1771 LC = RTLIB::SREM_I64;
1772 else if (VT == MVT::i128)
1773 LC = RTLIB::SREM_I128;
1774 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1776 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1777 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1780 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1781 SDValue &Lo, SDValue &Hi) {
1782 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1783 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1784 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1785 DAG.getConstant(NVT.getSizeInBits(),
1786 TLI.getShiftAmountTy()));
1787 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1790 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1791 SDValue &Lo, SDValue &Hi) {
1792 MVT VT = N->getValueType(0);
1793 DebugLoc dl = N->getDebugLoc();
1795 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1797 LC = RTLIB::UDIV_I32;
1798 else if (VT == MVT::i64)
1799 LC = RTLIB::UDIV_I64;
1800 else if (VT == MVT::i128)
1801 LC = RTLIB::UDIV_I128;
1802 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1804 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1805 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1808 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1809 SDValue &Lo, SDValue &Hi) {
1810 MVT VT = N->getValueType(0);
1811 DebugLoc dl = N->getDebugLoc();
1813 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1815 LC = RTLIB::UREM_I32;
1816 else if (VT == MVT::i64)
1817 LC = RTLIB::UREM_I64;
1818 else if (VT == MVT::i128)
1819 LC = RTLIB::UREM_I128;
1820 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1822 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1823 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1826 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1827 SDValue &Lo, SDValue &Hi) {
1828 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1829 SDValue Op = N->getOperand(0);
1830 if (Op.getValueType().bitsLE(NVT)) {
1831 // The low part is zero extension of the input (degenerates to a copy).
1832 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1833 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1835 // For example, extension of an i48 to an i64. The operand type necessarily
1836 // promotes to the result type, so will end up being expanded too.
1837 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1838 "Only know how to promote this result!");
1839 SDValue Res = GetPromotedInteger(Op);
1840 assert(Res.getValueType() == N->getValueType(0) &&
1841 "Operand over promoted?");
1842 // Split the promoted operand. This will simplify when it is expanded.
1843 SplitInteger(Res, Lo, Hi);
1844 unsigned ExcessBits =
1845 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1846 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1851 //===----------------------------------------------------------------------===//
1852 // Integer Operand Expansion
1853 //===----------------------------------------------------------------------===//
1855 /// ExpandIntegerOperand - This method is called when the specified operand of
1856 /// the specified node is found to need expansion. At this point, all of the
1857 /// result types of the node are known to be legal, but other operands of the
1858 /// node may need promotion or expansion as well as the specified one.
1859 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1860 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1861 SDValue Res = SDValue();
1863 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
1866 switch (N->getOpcode()) {
1869 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1870 N->dump(&DAG); cerr << "\n";
1872 assert(0 && "Do not know how to expand this operator's operand!");
1875 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1876 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1877 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1878 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1879 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1881 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1882 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1883 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1884 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1885 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1887 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1888 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1891 // If the result is null, the sub-method took care of registering results etc.
1892 if (!Res.getNode()) return false;
1894 // If the result is N, the sub-method updated N in place. Tell the legalizer
1896 if (Res.getNode() == N)
1899 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1900 "Invalid operand expansion");
1902 ReplaceValueWith(SDValue(N, 0), Res);
1906 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1907 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1908 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1910 ISD::CondCode &CCCode,
1912 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1913 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1914 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1916 MVT VT = NewLHS.getValueType();
1918 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1919 if (RHSLo == RHSHi) {
1920 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1921 if (RHSCST->isAllOnesValue()) {
1922 // Equality comparison to -1.
1923 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1930 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1931 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1932 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1933 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1937 // If this is a comparison of the sign bit, just look at the top part.
1939 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1940 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1941 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1947 // FIXME: This generated code sucks.
1948 ISD::CondCode LowCC;
1950 default: assert(0 && "Unknown integer setcc!");
1952 case ISD::SETULT: LowCC = ISD::SETULT; break;
1954 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1956 case ISD::SETULE: LowCC = ISD::SETULE; break;
1958 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1961 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1962 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1963 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1965 // NOTE: on targets without efficient SELECT of bools, we can always use
1966 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1967 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1969 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
1970 LHSLo, RHSLo, LowCC, false, DagCombineInfo);
1971 if (!Tmp1.getNode())
1972 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
1973 LHSLo, RHSLo, LowCC);
1974 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
1975 LHSHi, RHSHi, CCCode, false, DagCombineInfo);
1976 if (!Tmp2.getNode())
1977 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi.getValueType()),
1978 LHSHi, RHSHi, DAG.getCondCode(CCCode));
1980 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
1981 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
1982 if ((Tmp1C && Tmp1C->isNullValue()) ||
1983 (Tmp2C && Tmp2C->isNullValue() &&
1984 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1985 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1986 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1987 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1988 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1989 // low part is known false, returns high part.
1990 // For LE / GE, if high part is known false, ignore the low part.
1991 // For LT / GT, if high part is known true, ignore the low part.
1997 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
1998 LHSHi, RHSHi, ISD::SETEQ, false, DagCombineInfo);
1999 if (!NewLHS.getNode())
2000 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2001 LHSHi, RHSHi, ISD::SETEQ);
2002 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2003 NewLHS, Tmp1, Tmp2);
2007 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2008 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2009 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2010 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2012 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2013 // against zero to select between true and false values.
2014 if (NewRHS.getNode() == 0) {
2015 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2016 CCCode = ISD::SETNE;
2019 // Update N to have the operands specified.
2020 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2021 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2025 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2026 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2027 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2028 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2030 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2031 // against zero to select between true and false values.
2032 if (NewRHS.getNode() == 0) {
2033 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2034 CCCode = ISD::SETNE;
2037 // Update N to have the operands specified.
2038 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2039 N->getOperand(2), N->getOperand(3),
2040 DAG.getCondCode(CCCode));
2043 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2044 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2045 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2046 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2048 // If ExpandSetCCOperands returned a scalar, use it.
2049 if (NewRHS.getNode() == 0) {
2050 assert(NewLHS.getValueType() == N->getValueType(0) &&
2051 "Unexpected setcc expansion!");
2055 // Otherwise, update N to have the operands specified.
2056 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2057 DAG.getCondCode(CCCode));
2060 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2061 SDValue Op = N->getOperand(0);
2062 MVT DstVT = N->getValueType(0);
2063 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2064 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2065 "Don't know how to expand this SINT_TO_FP!");
2066 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2069 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2070 if (ISD::isNormalStore(N))
2071 return ExpandOp_NormalStore(N, OpNo);
2073 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2074 assert(OpNo == 1 && "Can only expand the stored value so far");
2076 MVT VT = N->getOperand(1).getValueType();
2077 MVT NVT = TLI.getTypeToTransformTo(VT);
2078 SDValue Ch = N->getChain();
2079 SDValue Ptr = N->getBasePtr();
2080 int SVOffset = N->getSrcValueOffset();
2081 unsigned Alignment = N->getAlignment();
2082 bool isVolatile = N->isVolatile();
2085 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2087 if (N->getMemoryVT().bitsLE(NVT)) {
2088 GetExpandedInteger(N->getValue(), Lo, Hi);
2089 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2090 N->getMemoryVT(), isVolatile, Alignment);
2091 } else if (TLI.isLittleEndian()) {
2092 // Little-endian - low bits are at low addresses.
2093 GetExpandedInteger(N->getValue(), Lo, Hi);
2095 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2096 isVolatile, Alignment);
2098 unsigned ExcessBits =
2099 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2100 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2102 // Increment the pointer to the other half.
2103 unsigned IncrementSize = NVT.getSizeInBits()/8;
2104 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2105 DAG.getIntPtrConstant(IncrementSize));
2106 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2107 SVOffset+IncrementSize, NEVT,
2108 isVolatile, MinAlign(Alignment, IncrementSize));
2109 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2111 // Big-endian - high bits are at low addresses. Favor aligned stores at
2112 // the cost of some bit-fiddling.
2113 GetExpandedInteger(N->getValue(), Lo, Hi);
2115 MVT EVT = N->getMemoryVT();
2116 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2117 unsigned IncrementSize = NVT.getSizeInBits()/8;
2118 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2119 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2121 if (ExcessBits < NVT.getSizeInBits()) {
2122 // Transfer high bits from the top of Lo to the bottom of Hi.
2123 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2124 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2125 TLI.getShiftAmountTy()));
2126 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2127 DAG.getNode(ISD::SRL, NVT, Lo,
2128 DAG.getConstant(ExcessBits,
2129 TLI.getShiftAmountTy())));
2132 // Store both the high bits and maybe some of the low bits.
2133 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2134 SVOffset, HiVT, isVolatile, Alignment);
2136 // Increment the pointer to the other half.
2137 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2138 DAG.getIntPtrConstant(IncrementSize));
2139 // Store the lowest ExcessBits bits in the second half.
2140 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2141 SVOffset+IncrementSize,
2142 MVT::getIntegerVT(ExcessBits),
2143 isVolatile, MinAlign(Alignment, IncrementSize));
2144 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2148 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2150 GetExpandedInteger(N->getOperand(0), InL, InH);
2151 // Just truncate the low part of the source.
2152 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2155 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2156 SDValue Op = N->getOperand(0);
2157 MVT SrcVT = Op.getValueType();
2158 MVT DstVT = N->getValueType(0);
2159 DebugLoc dl = N->getDebugLoc();
2161 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2162 // Do a signed conversion then adjust the result.
2163 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2164 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2166 // The result of the signed conversion needs adjusting if the 'sign bit' of
2167 // the incoming integer was set. To handle this, we dynamically test to see
2168 // if it is set, and, if so, add a fudge factor.
2170 const uint64_t F32TwoE32 = 0x4F800000ULL;
2171 const uint64_t F32TwoE64 = 0x5F800000ULL;
2172 const uint64_t F32TwoE128 = 0x7F800000ULL;
2175 if (SrcVT == MVT::i32)
2176 FF = APInt(32, F32TwoE32);
2177 else if (SrcVT == MVT::i64)
2178 FF = APInt(32, F32TwoE64);
2179 else if (SrcVT == MVT::i128)
2180 FF = APInt(32, F32TwoE128);
2182 assert(false && "Unsupported UINT_TO_FP!");
2184 // Check whether the sign bit is set.
2186 GetExpandedInteger(Op, Lo, Hi);
2187 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi.getValueType()),
2188 Hi, DAG.getConstant(0, Hi.getValueType()),
2191 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2192 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2193 TLI.getPointerTy());
2195 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2196 SDValue Zero = DAG.getIntPtrConstant(0);
2197 SDValue Four = DAG.getIntPtrConstant(4);
2198 if (TLI.isBigEndian()) std::swap(Zero, Four);
2199 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2201 unsigned Alignment =
2202 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2203 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2204 Alignment = std::min(Alignment, 4u);
2206 // Load the value out, extending it from f32 to the destination float type.
2207 // FIXME: Avoid the extend by constructing the right constant pool?
2208 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2209 FudgePtr, NULL, 0, MVT::f32,
2211 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2214 // Otherwise, use a libcall.
2215 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2216 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2217 "Don't know how to expand this UINT_TO_FP!");
2218 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);