1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Result = SDValue();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
65 case ISD::EXTRACT_VECTOR_ELT:
66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
80 case ISD::SIGN_EXTEND:
81 case ISD::ZERO_EXTEND:
82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
100 case ISD::ATOMIC_LOAD_ADD_8:
101 case ISD::ATOMIC_LOAD_SUB_8:
102 case ISD::ATOMIC_LOAD_AND_8:
103 case ISD::ATOMIC_LOAD_OR_8:
104 case ISD::ATOMIC_LOAD_XOR_8:
105 case ISD::ATOMIC_LOAD_NAND_8:
106 case ISD::ATOMIC_LOAD_MIN_8:
107 case ISD::ATOMIC_LOAD_MAX_8:
108 case ISD::ATOMIC_LOAD_UMIN_8:
109 case ISD::ATOMIC_LOAD_UMAX_8:
110 case ISD::ATOMIC_SWAP_8:
111 case ISD::ATOMIC_LOAD_ADD_16:
112 case ISD::ATOMIC_LOAD_SUB_16:
113 case ISD::ATOMIC_LOAD_AND_16:
114 case ISD::ATOMIC_LOAD_OR_16:
115 case ISD::ATOMIC_LOAD_XOR_16:
116 case ISD::ATOMIC_LOAD_NAND_16:
117 case ISD::ATOMIC_LOAD_MIN_16:
118 case ISD::ATOMIC_LOAD_MAX_16:
119 case ISD::ATOMIC_LOAD_UMIN_16:
120 case ISD::ATOMIC_LOAD_UMAX_16:
121 case ISD::ATOMIC_SWAP_16:
122 case ISD::ATOMIC_LOAD_ADD_32:
123 case ISD::ATOMIC_LOAD_SUB_32:
124 case ISD::ATOMIC_LOAD_AND_32:
125 case ISD::ATOMIC_LOAD_OR_32:
126 case ISD::ATOMIC_LOAD_XOR_32:
127 case ISD::ATOMIC_LOAD_NAND_32:
128 case ISD::ATOMIC_LOAD_MIN_32:
129 case ISD::ATOMIC_LOAD_MAX_32:
130 case ISD::ATOMIC_LOAD_UMIN_32:
131 case ISD::ATOMIC_LOAD_UMAX_32:
132 case ISD::ATOMIC_SWAP_32:
133 case ISD::ATOMIC_LOAD_ADD_64:
134 case ISD::ATOMIC_LOAD_SUB_64:
135 case ISD::ATOMIC_LOAD_AND_64:
136 case ISD::ATOMIC_LOAD_OR_64:
137 case ISD::ATOMIC_LOAD_XOR_64:
138 case ISD::ATOMIC_LOAD_NAND_64:
139 case ISD::ATOMIC_LOAD_MIN_64:
140 case ISD::ATOMIC_LOAD_MAX_64:
141 case ISD::ATOMIC_LOAD_UMIN_64:
142 case ISD::ATOMIC_LOAD_UMAX_64:
143 case ISD::ATOMIC_SWAP_64:
144 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
146 case ISD::ATOMIC_CMP_SWAP_8:
147 case ISD::ATOMIC_CMP_SWAP_16:
148 case ISD::ATOMIC_CMP_SWAP_32:
149 case ISD::ATOMIC_CMP_SWAP_64:
150 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
153 // If Result is null, the sub-method took care of registering the result.
154 if (Result.getNode())
155 SetPromotedInteger(SDValue(N, ResNo), Result);
158 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
159 // Sign-extend the new bits, and continue the assertion.
160 MVT OldVT = N->getValueType(0);
161 SDValue Op = GetPromotedInteger(N->getOperand(0));
162 return DAG.getNode(ISD::AssertSext, Op.getValueType(),
163 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
164 DAG.getValueType(OldVT)), N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
168 // Zero the new bits, and continue the assertion.
169 MVT OldVT = N->getValueType(0);
170 SDValue Op = GetPromotedInteger(N->getOperand(0));
171 return DAG.getNode(ISD::AssertZext, Op.getValueType(),
172 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
175 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
176 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
177 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
178 Op2, N->getSrcValue(), N->getAlignment());
179 // Legalized the chain result - switch anything that used the old chain to
181 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
185 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
186 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
187 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
188 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
189 Op2, Op3, N->getSrcValue(), N->getAlignment());
190 // Legalized the chain result - switch anything that used the old chain to
192 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
196 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
197 SDValue InOp = N->getOperand(0);
198 MVT InVT = InOp.getValueType();
199 MVT NInVT = TLI.getTypeToTransformTo(InVT);
200 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
202 switch (getTypeAction(InVT)) {
204 assert(false && "Unknown type action!");
209 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
210 // The input promotes to the same size. Convert the promoted value.
211 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
214 // Promote the integer operand by hand.
215 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
219 case ScalarizeVector:
220 // Convert the element to an integer and promote it by hand.
221 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
222 BitConvertToInteger(GetScalarizedVector(InOp)));
224 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
225 // pieces of the input into integers and reassemble in the final type.
227 GetSplitVector(N->getOperand(0), Lo, Hi);
228 Lo = BitConvertToInteger(Lo);
229 Hi = BitConvertToInteger(Hi);
231 if (TLI.isBigEndian())
234 InOp = DAG.getNode(ISD::ANY_EXTEND,
235 MVT::getIntegerVT(OutVT.getSizeInBits()),
236 JoinIntegers(Lo, Hi));
237 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
240 // Otherwise, lower the bit-convert to a store/load from the stack, then
242 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
243 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
246 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
247 SDValue Op = GetPromotedInteger(N->getOperand(0));
248 MVT OVT = N->getValueType(0);
249 MVT NVT = Op.getValueType();
251 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
252 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
253 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
256 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
257 // The pair element type may be legal, or may not promote to the same type as
258 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
259 return DAG.getNode(ISD::ANY_EXTEND,
260 TLI.getTypeToTransformTo(N->getValueType(0)),
261 JoinIntegers(N->getOperand(0), N->getOperand(1)));
264 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
265 MVT VT = N->getValueType(0);
266 // Zero extend things like i1, sign extend everything else. It shouldn't
267 // matter in theory which one we pick, but this tends to give better code?
268 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
269 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
271 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
275 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
276 SDValue Op = GetPromotedInteger(N->getOperand(0));
277 MVT OVT = N->getValueType(0);
278 MVT NVT = Op.getValueType();
279 // Zero extend to the promoted type and do the count there.
280 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
281 // Subtract off the extra leading bits in the bigger type.
282 return DAG.getNode(ISD::SUB, NVT, Op,
283 DAG.getConstant(NVT.getSizeInBits() -
284 OVT.getSizeInBits(), NVT));
287 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
288 SDValue Op = GetPromotedInteger(N->getOperand(0));
289 MVT OVT = N->getValueType(0);
290 MVT NVT = Op.getValueType();
291 // Zero extend to the promoted type and do the count there.
292 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
295 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
296 SDValue Op = GetPromotedInteger(N->getOperand(0));
297 MVT OVT = N->getValueType(0);
298 MVT NVT = Op.getValueType();
299 // The count is the same in the promoted type except if the original
300 // value was zero. This can be handled by setting the bit just off
301 // the top of the original type.
302 APInt TopBit(NVT.getSizeInBits(), 0);
303 TopBit.set(OVT.getSizeInBits());
304 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
305 return DAG.getNode(ISD::CTTZ, NVT, Op);
308 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
309 MVT OldVT = N->getValueType(0);
310 SDValue OldVec = N->getOperand(0);
311 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getShiftAmountTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getShiftAmountTy()));
345 if (TLI.isBigEndian())
348 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
349 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
352 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
353 unsigned NewOpc = N->getOpcode();
354 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 // If we're promoting a UINT to a larger size, check to see if the new node
357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
358 // we can use that instead. This allows us to generate better code for
359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
360 // legal, such as PowerPC.
361 if (N->getOpcode() == ISD::FP_TO_UINT) {
362 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
363 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
364 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
365 NewOpc = ISD::FP_TO_SINT;
368 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
371 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
372 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
374 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
375 SDValue Res = GetPromotedInteger(N->getOperand(0));
376 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
377 "Extension doesn't make sense!");
379 // If the result and operand types are the same after promotion, simplify
380 // to an in-register extension.
381 if (NVT == Res.getValueType()) {
382 // The high bits are not guaranteed to be anything. Insert an extend.
383 if (N->getOpcode() == ISD::SIGN_EXTEND)
384 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
385 DAG.getValueType(N->getOperand(0).getValueType()));
386 if (N->getOpcode() == ISD::ZERO_EXTEND)
387 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
388 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
393 // Otherwise, just extend the original operand all the way to the larger type.
394 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
397 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
398 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
399 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
400 ISD::LoadExtType ExtType =
401 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
402 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
403 N->getSrcValue(), N->getSrcValueOffset(),
404 N->getMemoryVT(), N->isVolatile(),
407 // Legalized the chain result - switch anything that used the old chain to
409 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
413 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
414 // Sign extend the input.
415 SDValue LHS = GetPromotedInteger(N->getOperand(0));
416 SDValue RHS = GetPromotedInteger(N->getOperand(1));
417 MVT VT = N->getValueType(0);
418 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
419 DAG.getValueType(VT));
420 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
421 DAG.getValueType(VT));
423 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
426 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
427 SDValue LHS = GetPromotedInteger(N->getOperand(1));
428 SDValue RHS = GetPromotedInteger(N->getOperand(2));
429 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
432 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
433 SDValue LHS = GetPromotedInteger(N->getOperand(2));
434 SDValue RHS = GetPromotedInteger(N->getOperand(3));
435 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
436 N->getOperand(1), LHS, RHS, N->getOperand(4));
439 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
440 MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
441 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
443 // Get the SETCC result using the canonical SETCC type.
444 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
445 N->getOperand(1), N->getOperand(2));
447 // Convert to the expected type.
448 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
449 assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
450 "Integer type overpromoted?");
451 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
454 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
455 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
456 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
459 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
460 SDValue Op = GetPromotedInteger(N->getOperand(0));
461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
465 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
466 // The input may have strange things in the top bits of the registers, but
467 // these operations don't care. They may have weird bits going out, but
468 // that too is okay if they are integer operations.
469 SDValue LHS = GetPromotedInteger(N->getOperand(0));
470 SDValue RHS = GetPromotedInteger(N->getOperand(1));
471 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
474 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
475 // The input value must be properly sign extended.
476 MVT VT = N->getValueType(0);
477 MVT NVT = TLI.getTypeToTransformTo(VT);
478 SDValue Res = GetPromotedInteger(N->getOperand(0));
479 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
480 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
483 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
484 // The input value must be properly zero extended.
485 MVT VT = N->getValueType(0);
486 MVT NVT = TLI.getTypeToTransformTo(VT);
487 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
488 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
491 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
494 switch (getTypeAction(N->getOperand(0).getValueType())) {
495 default: assert(0 && "Unknown type action!");
498 Res = N->getOperand(0);
501 Res = GetPromotedInteger(N->getOperand(0));
505 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
506 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
507 "Truncation doesn't make sense!");
508 if (Res.getValueType() == NVT)
511 // Truncate to NVT instead of VT
512 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
515 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
516 // Zero extend the input.
517 SDValue LHS = GetPromotedInteger(N->getOperand(0));
518 SDValue RHS = GetPromotedInteger(N->getOperand(1));
519 MVT VT = N->getValueType(0);
520 LHS = DAG.getZeroExtendInReg(LHS, VT);
521 RHS = DAG.getZeroExtendInReg(RHS, VT);
523 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
526 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
527 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
530 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
531 SDValue Chain = N->getOperand(0); // Get the chain.
532 SDValue Ptr = N->getOperand(1); // Get the pointer.
533 MVT VT = N->getValueType(0);
535 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
536 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
538 // Increment the arg pointer, VAList, to the next vaarg
539 // FIXME: should the ABI size be used for the increment? Think of
540 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
541 // integers of unusual size (such MVT::i1, which gives an increment
543 unsigned Increment = VT.getSizeInBits() / 8;
544 SDValue Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
545 DAG.getIntPtrConstant(Increment));
547 // Store the incremented VAList to the pointer.
548 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
550 // Load the actual argument out of the arg pointer VAList.
551 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
552 VAList, NULL, 0, VT);
554 // Legalized the chain result - switch anything that used the old chain to
556 ReplaceValueWith(SDValue(N, 1), Tmp.getValue(1));
561 //===----------------------------------------------------------------------===//
562 // Integer Operand Promotion
563 //===----------------------------------------------------------------------===//
565 /// PromoteIntegerOperand - This method is called when the specified operand of
566 /// the specified node is found to need promotion. At this point, all of the
567 /// result types of the node are known to be legal, but other operands of the
568 /// node may need promotion or expansion as well as the specified one.
569 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
570 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
571 SDValue Res = SDValue();
573 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
574 == TargetLowering::Custom)
575 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
577 if (Res.getNode() == 0) {
578 switch (N->getOpcode()) {
581 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
582 N->dump(&DAG); cerr << "\n";
584 assert(0 && "Do not know how to promote this operator's operand!");
587 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
588 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
589 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
590 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
591 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
592 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
593 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
594 case ISD::INSERT_VECTOR_ELT:
595 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
596 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
597 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
598 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
599 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
600 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
601 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
603 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
604 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
606 case ISD::SINT_TO_FP:
607 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
611 // If the result is null, the sub-method took care of registering results etc.
612 if (!Res.getNode()) return false;
613 // If the result is N, the sub-method updated N in place.
614 if (Res.getNode() == N) {
615 // Mark N as new and remark N and its operands. This allows us to correctly
616 // revisit N if it needs another step of promotion and allows us to visit
617 // any new operands to N.
622 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
623 "Invalid operand expansion");
625 ReplaceValueWith(SDValue(N, 0), Res);
629 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
630 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
631 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
632 ISD::CondCode CCCode) {
633 MVT VT = NewLHS.getValueType();
635 // Get the promoted values.
636 NewLHS = GetPromotedInteger(NewLHS);
637 NewRHS = GetPromotedInteger(NewRHS);
639 // Otherwise, we have to insert explicit sign or zero extends. Note
640 // that we could insert sign extends for ALL conditions, but zero extend
641 // is cheaper on many machines (an AND instead of two shifts), so prefer
644 default: assert(0 && "Unknown integer comparison!");
651 // ALL of these operations will work if we either sign or zero extend
652 // the operands (including the unsigned comparisons!). Zero extend is
653 // usually a simpler/cheaper operation, so prefer it.
654 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
655 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
661 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
662 DAG.getValueType(VT));
663 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
664 DAG.getValueType(VT));
669 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
670 SDValue Op = GetPromotedInteger(N->getOperand(0));
671 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
674 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
675 assert(OpNo == 2 && "Don't know how to promote this operand!");
677 SDValue LHS = N->getOperand(2);
678 SDValue RHS = N->getOperand(3);
679 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
681 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
683 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
684 N->getOperand(1), LHS, RHS, N->getOperand(4));
687 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
688 assert(OpNo == 1 && "only know how to promote condition");
689 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
691 // The top bits of the promoted condition are not necessarily zero, ensure
692 // that the value is properly zero extended.
693 unsigned BitWidth = Cond.getValueSizeInBits();
694 if (!DAG.MaskedValueIsZero(Cond,
695 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
696 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
698 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
699 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
703 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
704 // Since the result type is legal, the operands must promote to it.
705 MVT OVT = N->getOperand(0).getValueType();
706 SDValue Lo = GetPromotedInteger(N->getOperand(0));
707 SDValue Hi = GetPromotedInteger(N->getOperand(1));
708 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
710 Lo = DAG.getZeroExtendInReg(Lo, OVT);
711 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
712 DAG.getConstant(OVT.getSizeInBits(),
713 TLI.getShiftAmountTy()));
714 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
717 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
718 // The vector type is legal but the element type is not. This implies
719 // that the vector is a power-of-two in length and that the element
720 // type does not have a strange size (eg: it is not i1).
721 MVT VecVT = N->getValueType(0);
722 unsigned NumElts = VecVT.getVectorNumElements();
723 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
725 // Build a vector of half the length out of elements of twice the bitwidth.
726 // For example <4 x i16> -> <2 x i32>.
727 MVT OldVT = N->getOperand(0).getValueType();
728 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
729 assert(OldVT.isSimple() && NewVT.isSimple());
731 std::vector<SDValue> NewElts;
732 NewElts.reserve(NumElts/2);
734 for (unsigned i = 0; i < NumElts; i += 2) {
735 // Combine two successive elements into one promoted element.
736 SDValue Lo = N->getOperand(i);
737 SDValue Hi = N->getOperand(i+1);
738 if (TLI.isBigEndian())
740 NewElts.push_back(JoinIntegers(Lo, Hi));
743 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
744 MVT::getVectorVT(NewVT, NewElts.size()),
745 &NewElts[0], NewElts.size());
747 // Convert the new vector to the old vector type.
748 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
751 SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
752 SDValue Op = GetPromotedInteger(N->getOperand(0));
753 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
756 SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
757 SDValue Op = GetPromotedInteger(N->getOperand(0));
758 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
759 DAG.getIntPtrConstant(0));
762 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
765 // Promote the inserted value. This is valid because the type does not
766 // have to match the vector element type.
768 // Check that any extra bits introduced will be truncated away.
769 assert(N->getOperand(1).getValueType().getSizeInBits() >=
770 N->getValueType(0).getVectorElementType().getSizeInBits() &&
771 "Type of inserted value narrower than vector element type!");
772 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
773 GetPromotedInteger(N->getOperand(1)),
777 assert(OpNo == 2 && "Different operand and result vector types?");
779 // Promote the index.
780 SDValue Idx = N->getOperand(2);
781 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
782 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
783 N->getOperand(1), Idx);
786 SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
787 SDValue In = GetPromotedInteger(N->getOperand(0));
788 MVT OpVT = N->getOperand(0).getValueType();
789 if (N->getOpcode() == ISD::UINT_TO_FP)
790 In = DAG.getZeroExtendInReg(In, OpVT);
792 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
793 In, DAG.getValueType(OpVT));
795 return DAG.UpdateNodeOperands(SDValue(N, 0), In);
798 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
800 NewOps[0] = N->getOperand(0);
801 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
802 SDValue Flag = GetPromotedInteger(N->getOperand(i));
803 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
805 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
806 array_lengthof(NewOps));
809 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
810 assert(OpNo == 0 && "Only know how to promote condition");
811 assert(N->getOperand(0).getValueType() == MVT::i1 &&
812 "SetCC type is not legal??");
813 SDValue Cond = GetPromotedInteger(N->getOperand(0));
815 // Promote all the way up to SVT, the canonical SetCC type.
816 MVT SVT = TLI.getSetCCResultType(Cond);
817 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
818 assert(Cond.getValueSizeInBits() <= SVT.getSizeInBits() &&
819 "Integer type overpromoted?");
821 // Make sure the extra bits conform to getSetCCResultContents. There are
822 // two sets of extra bits: those in Cond, which come from type promotion,
823 // and those we need to add to have the final type be SVT (for most targets
824 // this last set of bits is empty).
825 unsigned CondBits = Cond.getValueSizeInBits();
826 ISD::NodeType ExtendCode;
827 switch (TLI.getSetCCResultContents()) {
829 assert(false && "Unknown SetCCResultValue!");
830 case TargetLowering::UndefinedSetCCResult:
831 // Extend to SVT by adding rubbish.
832 ExtendCode = ISD::ANY_EXTEND;
834 case TargetLowering::ZeroOrOneSetCCResult:
835 ExtendCode = ISD::ZERO_EXTEND;
836 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
837 // All extra bits need to be cleared. Do this by zero extending the
838 // original MVT::i1 condition value all the way to SVT.
839 Cond = N->getOperand(0);
841 case TargetLowering::ZeroOrNegativeOneSetCCResult: {
842 ExtendCode = ISD::SIGN_EXTEND;
843 unsigned SignBits = DAG.ComputeNumSignBits(Cond);
844 if (SignBits != CondBits)
845 // All extra bits need to be sign extended. Do this by sign extending the
846 // original MVT::i1 condition value all the way to SVT.
847 Cond = N->getOperand(0);
851 Cond = DAG.getNode(ExtendCode, SVT, Cond);
853 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
854 N->getOperand(1), N->getOperand(2));
857 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
858 assert(OpNo == 0 && "Don't know how to promote this operand!");
860 SDValue LHS = N->getOperand(0);
861 SDValue RHS = N->getOperand(1);
862 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
864 // The CC (#4) and the possible return values (#2 and #3) have legal types.
865 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
866 N->getOperand(3), N->getOperand(4));
869 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
870 assert(OpNo == 0 && "Don't know how to promote this operand!");
872 SDValue LHS = N->getOperand(0);
873 SDValue RHS = N->getOperand(1);
874 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
876 // The CC (#2) is always legal.
877 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
880 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
881 SDValue Op = GetPromotedInteger(N->getOperand(0));
882 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
883 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
884 Op, DAG.getValueType(N->getOperand(0).getValueType()));
887 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
888 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
889 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
890 int SVOffset = N->getSrcValueOffset();
891 unsigned Alignment = N->getAlignment();
892 bool isVolatile = N->isVolatile();
894 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
896 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
898 // Truncate the value and store the result.
899 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
900 SVOffset, N->getMemoryVT(),
901 isVolatile, Alignment);
904 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
905 SDValue Op = GetPromotedInteger(N->getOperand(0));
906 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
909 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
910 SDValue Op = GetPromotedInteger(N->getOperand(0));
911 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
912 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
916 //===----------------------------------------------------------------------===//
917 // Integer Result Expansion
918 //===----------------------------------------------------------------------===//
920 /// ExpandIntegerResult - This method is called when the specified result of the
921 /// specified node is found to need expansion. At this point, the node may also
922 /// have invalid operands or may have other results that need promotion, we just
923 /// know that (at least) one result needs expansion.
924 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
925 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
929 // See if the target wants to custom expand this node.
930 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
931 TargetLowering::Custom) {
932 // If the target wants to, allow it to lower this itself.
933 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
934 // Everything that once used N now uses P. We are guaranteed that the
935 // result value types of N and the result value types of P match.
936 ReplaceNodeWith(N, P);
941 switch (N->getOpcode()) {
944 cerr << "ExpandIntegerResult #" << ResNo << ": ";
945 N->dump(&DAG); cerr << "\n";
947 assert(0 && "Do not know how to expand the result of this operator!");
950 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
951 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
952 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
953 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
955 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
956 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
957 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
958 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
960 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
961 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
962 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
963 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
964 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
965 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
966 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
967 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
968 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
969 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
970 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
971 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
972 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
973 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
974 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
975 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
976 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
977 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
978 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
979 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
983 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
986 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
989 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
992 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
996 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
999 // If Lo/Hi is null, the sub-method took care of registering results etc.
1001 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1004 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1005 /// and the shift amount is a constant 'Amt'. Expand the operation.
1006 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1007 SDValue &Lo, SDValue &Hi) {
1008 // Expand the incoming operand to be shifted, so that we have its parts
1010 GetExpandedInteger(N->getOperand(0), InL, InH);
1012 MVT NVT = InL.getValueType();
1013 unsigned VTBits = N->getValueType(0).getSizeInBits();
1014 unsigned NVTBits = NVT.getSizeInBits();
1015 MVT ShTy = N->getOperand(1).getValueType();
1017 if (N->getOpcode() == ISD::SHL) {
1019 Lo = Hi = DAG.getConstant(0, NVT);
1020 } else if (Amt > NVTBits) {
1021 Lo = DAG.getConstant(0, NVT);
1022 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1023 } else if (Amt == NVTBits) {
1024 Lo = DAG.getConstant(0, NVT);
1026 } else if (Amt == 1) {
1027 // Emit this X << 1 as X+X.
1028 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1029 SDValue LoOps[2] = { InL, InL };
1030 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1031 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1032 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1034 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1035 Hi = DAG.getNode(ISD::OR, NVT,
1036 DAG.getNode(ISD::SHL, NVT, InH,
1037 DAG.getConstant(Amt, ShTy)),
1038 DAG.getNode(ISD::SRL, NVT, InL,
1039 DAG.getConstant(NVTBits-Amt, ShTy)));
1044 if (N->getOpcode() == ISD::SRL) {
1046 Lo = DAG.getConstant(0, NVT);
1047 Hi = DAG.getConstant(0, NVT);
1048 } else if (Amt > NVTBits) {
1049 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1050 Hi = DAG.getConstant(0, NVT);
1051 } else if (Amt == NVTBits) {
1053 Hi = DAG.getConstant(0, NVT);
1055 Lo = DAG.getNode(ISD::OR, NVT,
1056 DAG.getNode(ISD::SRL, NVT, InL,
1057 DAG.getConstant(Amt, ShTy)),
1058 DAG.getNode(ISD::SHL, NVT, InH,
1059 DAG.getConstant(NVTBits-Amt, ShTy)));
1060 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1065 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1067 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1068 DAG.getConstant(NVTBits-1, ShTy));
1069 } else if (Amt > NVTBits) {
1070 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1071 DAG.getConstant(Amt-NVTBits, ShTy));
1072 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1073 DAG.getConstant(NVTBits-1, ShTy));
1074 } else if (Amt == NVTBits) {
1076 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1077 DAG.getConstant(NVTBits-1, ShTy));
1079 Lo = DAG.getNode(ISD::OR, NVT,
1080 DAG.getNode(ISD::SRL, NVT, InL,
1081 DAG.getConstant(Amt, ShTy)),
1082 DAG.getNode(ISD::SHL, NVT, InH,
1083 DAG.getConstant(NVTBits-Amt, ShTy)));
1084 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1088 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1089 /// this shift based on knowledge of the high bit of the shift amount. If we
1090 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1092 bool DAGTypeLegalizer::
1093 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1094 SDValue Amt = N->getOperand(1);
1095 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1096 MVT ShTy = Amt.getValueType();
1097 unsigned ShBits = ShTy.getSizeInBits();
1098 unsigned NVTBits = NVT.getSizeInBits();
1099 assert(isPowerOf2_32(NVTBits) &&
1100 "Expanded integer type size not a power of two!");
1102 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1103 APInt KnownZero, KnownOne;
1104 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1106 // If we don't know anything about the high bits, exit.
1107 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1110 // Get the incoming operand to be shifted.
1112 GetExpandedInteger(N->getOperand(0), InL, InH);
1114 // If we know that any of the high bits of the shift amount are one, then we
1115 // can do this as a couple of simple shifts.
1116 if (KnownOne.intersects(HighBitMask)) {
1117 // Mask out the high bit, which we know is set.
1118 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1119 DAG.getConstant(~HighBitMask, ShTy));
1121 switch (N->getOpcode()) {
1122 default: assert(0 && "Unknown shift");
1124 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1125 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1128 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1129 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1132 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1133 DAG.getConstant(NVTBits-1, ShTy));
1134 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1139 // If we know that all of the high bits of the shift amount are zero, then we
1140 // can do this as a couple of simple shifts.
1141 if ((KnownZero & HighBitMask) == HighBitMask) {
1143 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1144 DAG.getConstant(NVTBits, ShTy),
1147 switch (N->getOpcode()) {
1148 default: assert(0 && "Unknown shift");
1149 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1151 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1154 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1155 Hi = DAG.getNode(ISD::OR, NVT,
1156 DAG.getNode(Op1, NVT, InH, Amt),
1157 DAG.getNode(Op2, NVT, InL, Amt2));
1164 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1165 SDValue &Lo, SDValue &Hi) {
1166 // Expand the subcomponents.
1167 SDValue LHSL, LHSH, RHSL, RHSH;
1168 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1169 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1170 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1171 SDValue LoOps[2] = { LHSL, RHSL };
1172 SDValue HiOps[3] = { LHSH, RHSH };
1174 if (N->getOpcode() == ISD::ADD) {
1175 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1176 HiOps[2] = Lo.getValue(1);
1177 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1179 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1180 HiOps[2] = Lo.getValue(1);
1181 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1185 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1186 SDValue &Lo, SDValue &Hi) {
1187 // Expand the subcomponents.
1188 SDValue LHSL, LHSH, RHSL, RHSH;
1189 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1190 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1191 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1192 SDValue LoOps[2] = { LHSL, RHSL };
1193 SDValue HiOps[3] = { LHSH, RHSH };
1195 if (N->getOpcode() == ISD::ADDC) {
1196 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1197 HiOps[2] = Lo.getValue(1);
1198 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1200 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1201 HiOps[2] = Lo.getValue(1);
1202 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1205 // Legalized the flag result - switch anything that used the old flag to
1207 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1210 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1211 SDValue &Lo, SDValue &Hi) {
1212 // Expand the subcomponents.
1213 SDValue LHSL, LHSH, RHSL, RHSH;
1214 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1215 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1216 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1217 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1218 SDValue HiOps[3] = { LHSH, RHSH };
1220 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1221 HiOps[2] = Lo.getValue(1);
1222 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1224 // Legalized the flag result - switch anything that used the old flag to
1226 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1229 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1230 SDValue &Lo, SDValue &Hi) {
1231 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1232 SDValue Op = N->getOperand(0);
1233 if (Op.getValueType().bitsLE(NVT)) {
1234 // The low part is any extension of the input (which degenerates to a copy).
1235 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1236 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1238 // For example, extension of an i48 to an i64. The operand type necessarily
1239 // promotes to the result type, so will end up being expanded too.
1240 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1241 "Only know how to promote this result!");
1242 SDValue Res = GetPromotedInteger(Op);
1243 assert(Res.getValueType() == N->getValueType(0) &&
1244 "Operand over promoted?");
1245 // Split the promoted operand. This will simplify when it is expanded.
1246 SplitInteger(Res, Lo, Hi);
1250 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1251 SDValue &Lo, SDValue &Hi) {
1252 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1253 MVT NVT = Lo.getValueType();
1254 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1255 unsigned NVTBits = NVT.getSizeInBits();
1256 unsigned EVTBits = EVT.getSizeInBits();
1258 if (NVTBits < EVTBits) {
1259 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1260 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1262 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1263 // The high part replicates the sign bit of Lo, make it explicit.
1264 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1265 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1269 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1270 SDValue &Lo, SDValue &Hi) {
1271 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1272 MVT NVT = Lo.getValueType();
1273 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1274 unsigned NVTBits = NVT.getSizeInBits();
1275 unsigned EVTBits = EVT.getSizeInBits();
1277 if (NVTBits < EVTBits) {
1278 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1279 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1281 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1282 // The high part must be zero, make it explicit.
1283 Hi = DAG.getConstant(0, NVT);
1287 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1288 SDValue &Lo, SDValue &Hi) {
1289 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1290 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1291 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1294 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1295 SDValue &Lo, SDValue &Hi) {
1296 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1297 unsigned NBitWidth = NVT.getSizeInBits();
1298 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1299 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1300 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1303 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1304 SDValue &Lo, SDValue &Hi) {
1305 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1306 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1307 MVT NVT = Lo.getValueType();
1309 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1310 DAG.getConstant(0, NVT), ISD::SETNE);
1312 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1313 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1315 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1316 DAG.getNode(ISD::ADD, NVT, LoLZ,
1317 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1318 Hi = DAG.getConstant(0, NVT);
1321 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1322 SDValue &Lo, SDValue &Hi) {
1323 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1324 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1325 MVT NVT = Lo.getValueType();
1326 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1327 DAG.getNode(ISD::CTPOP, NVT, Hi));
1328 Hi = DAG.getConstant(0, NVT);
1331 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1332 SDValue &Lo, SDValue &Hi) {
1333 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1334 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1335 MVT NVT = Lo.getValueType();
1337 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1338 DAG.getConstant(0, NVT), ISD::SETNE);
1340 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1341 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1343 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1344 DAG.getNode(ISD::ADD, NVT, HiLZ,
1345 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1346 Hi = DAG.getConstant(0, NVT);
1349 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1351 MVT VT = N->getValueType(0);
1352 SDValue Op = N->getOperand(0);
1353 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1354 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1355 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1358 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1360 MVT VT = N->getValueType(0);
1361 SDValue Op = N->getOperand(0);
1362 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1363 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1364 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1367 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1368 SDValue &Lo, SDValue &Hi) {
1369 if (ISD::isNormalLoad(N)) {
1370 ExpandRes_NormalLoad(N, Lo, Hi);
1374 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1376 MVT VT = N->getValueType(0);
1377 MVT NVT = TLI.getTypeToTransformTo(VT);
1378 SDValue Ch = N->getChain();
1379 SDValue Ptr = N->getBasePtr();
1380 ISD::LoadExtType ExtType = N->getExtensionType();
1381 int SVOffset = N->getSrcValueOffset();
1382 unsigned Alignment = N->getAlignment();
1383 bool isVolatile = N->isVolatile();
1385 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1387 if (N->getMemoryVT().bitsLE(NVT)) {
1388 MVT EVT = N->getMemoryVT();
1390 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1391 isVolatile, Alignment);
1393 // Remember the chain.
1394 Ch = Lo.getValue(1);
1396 if (ExtType == ISD::SEXTLOAD) {
1397 // The high part is obtained by SRA'ing all but one of the bits of the
1399 unsigned LoSize = Lo.getValueType().getSizeInBits();
1400 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1401 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1402 } else if (ExtType == ISD::ZEXTLOAD) {
1403 // The high part is just a zero.
1404 Hi = DAG.getConstant(0, NVT);
1406 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1407 // The high part is undefined.
1408 Hi = DAG.getNode(ISD::UNDEF, NVT);
1410 } else if (TLI.isLittleEndian()) {
1411 // Little-endian - low bits are at low addresses.
1412 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1413 isVolatile, Alignment);
1415 unsigned ExcessBits =
1416 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1417 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1419 // Increment the pointer to the other half.
1420 unsigned IncrementSize = NVT.getSizeInBits()/8;
1421 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1422 DAG.getIntPtrConstant(IncrementSize));
1423 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1424 SVOffset+IncrementSize, NEVT,
1425 isVolatile, MinAlign(Alignment, IncrementSize));
1427 // Build a factor node to remember that this load is independent of the
1429 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1432 // Big-endian - high bits are at low addresses. Favor aligned loads at
1433 // the cost of some bit-fiddling.
1434 MVT EVT = N->getMemoryVT();
1435 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1436 unsigned IncrementSize = NVT.getSizeInBits()/8;
1437 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1439 // Load both the high bits and maybe some of the low bits.
1440 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1441 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1442 isVolatile, Alignment);
1444 // Increment the pointer to the other half.
1445 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1446 DAG.getIntPtrConstant(IncrementSize));
1447 // Load the rest of the low bits.
1448 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1449 SVOffset+IncrementSize,
1450 MVT::getIntegerVT(ExcessBits),
1451 isVolatile, MinAlign(Alignment, IncrementSize));
1453 // Build a factor node to remember that this load is independent of the
1455 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1458 if (ExcessBits < NVT.getSizeInBits()) {
1459 // Transfer low bits from the bottom of Hi to the top of Lo.
1460 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1461 DAG.getNode(ISD::SHL, NVT, Hi,
1462 DAG.getConstant(ExcessBits,
1463 TLI.getShiftAmountTy())));
1464 // Move high bits to the right position in Hi.
1465 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1466 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1467 TLI.getShiftAmountTy()));
1471 // Legalized the chain result - switch anything that used the old chain to
1473 ReplaceValueWith(SDValue(N, 1), Ch);
1476 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1477 SDValue &Lo, SDValue &Hi) {
1478 SDValue LL, LH, RL, RH;
1479 GetExpandedInteger(N->getOperand(0), LL, LH);
1480 GetExpandedInteger(N->getOperand(1), RL, RH);
1481 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1482 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1485 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1486 SDValue &Lo, SDValue &Hi) {
1487 MVT VT = N->getValueType(0);
1488 MVT NVT = TLI.getTypeToTransformTo(VT);
1490 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1491 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1492 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1493 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1494 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1495 SDValue LL, LH, RL, RH;
1496 GetExpandedInteger(N->getOperand(0), LL, LH);
1497 GetExpandedInteger(N->getOperand(1), RL, RH);
1498 unsigned OuterBitSize = VT.getSizeInBits();
1499 unsigned InnerBitSize = NVT.getSizeInBits();
1500 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1501 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1503 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1504 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1505 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1506 // The inputs are both zero-extended.
1508 // We can emit a umul_lohi.
1509 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1510 Hi = SDValue(Lo.getNode(), 1);
1514 // We can emit a mulhu+mul.
1515 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1516 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1520 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1521 // The input values are both sign-extended.
1523 // We can emit a smul_lohi.
1524 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1525 Hi = SDValue(Lo.getNode(), 1);
1529 // We can emit a mulhs+mul.
1530 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1531 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1536 // Lo,Hi = umul LHS, RHS.
1537 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1538 DAG.getVTList(NVT, NVT), LL, RL);
1540 Hi = UMulLOHI.getValue(1);
1541 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1542 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1543 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1544 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1548 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1549 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1550 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1551 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1552 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1553 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1558 // If nothing else, we can make a libcall.
1559 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1561 LC = RTLIB::MUL_I32;
1562 else if (VT == MVT::i64)
1563 LC = RTLIB::MUL_I64;
1564 else if (VT == MVT::i128)
1565 LC = RTLIB::MUL_I128;
1566 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1568 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1569 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1572 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1573 SDValue &Lo, SDValue &Hi) {
1574 MVT VT = N->getValueType(0);
1576 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1578 LC = RTLIB::SDIV_I32;
1579 else if (VT == MVT::i64)
1580 LC = RTLIB::SDIV_I64;
1581 else if (VT == MVT::i128)
1582 LC = RTLIB::SDIV_I128;
1583 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1585 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1586 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1589 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1590 SDValue &Lo, SDValue &Hi) {
1591 MVT VT = N->getValueType(0);
1593 // If we can emit an efficient shift operation, do so now. Check to see if
1594 // the RHS is a constant.
1595 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1596 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1598 // If we can determine that the high bit of the shift is zero or one, even if
1599 // the low bits are variable, emit this shift in an optimized form.
1600 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1603 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1605 if (N->getOpcode() == ISD::SHL) {
1606 PartsOpc = ISD::SHL_PARTS;
1607 } else if (N->getOpcode() == ISD::SRL) {
1608 PartsOpc = ISD::SRL_PARTS;
1610 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1611 PartsOpc = ISD::SRA_PARTS;
1614 // Next check to see if the target supports this SHL_PARTS operation or if it
1615 // will custom expand it.
1616 MVT NVT = TLI.getTypeToTransformTo(VT);
1617 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1618 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1619 Action == TargetLowering::Custom) {
1620 // Expand the subcomponents.
1622 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1624 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1625 MVT VT = LHSL.getValueType();
1626 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1627 Hi = Lo.getValue(1);
1631 // Otherwise, emit a libcall.
1632 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1634 if (N->getOpcode() == ISD::SHL) {
1635 isSigned = false; /*sign irrelevant*/
1637 LC = RTLIB::SHL_I32;
1638 else if (VT == MVT::i64)
1639 LC = RTLIB::SHL_I64;
1640 else if (VT == MVT::i128)
1641 LC = RTLIB::SHL_I128;
1642 } else if (N->getOpcode() == ISD::SRL) {
1645 LC = RTLIB::SRL_I32;
1646 else if (VT == MVT::i64)
1647 LC = RTLIB::SRL_I64;
1648 else if (VT == MVT::i128)
1649 LC = RTLIB::SRL_I128;
1651 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1654 LC = RTLIB::SRA_I32;
1655 else if (VT == MVT::i64)
1656 LC = RTLIB::SRA_I64;
1657 else if (VT == MVT::i128)
1658 LC = RTLIB::SRA_I128;
1660 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1662 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1663 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1666 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1667 SDValue &Lo, SDValue &Hi) {
1668 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1669 SDValue Op = N->getOperand(0);
1670 if (Op.getValueType().bitsLE(NVT)) {
1671 // The low part is sign extension of the input (which degenerates to a copy).
1672 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1673 // The high part is obtained by SRA'ing all but one of the bits of low part.
1674 unsigned LoSize = NVT.getSizeInBits();
1675 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1676 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1678 // For example, extension of an i48 to an i64. The operand type necessarily
1679 // promotes to the result type, so will end up being expanded too.
1680 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1681 "Only know how to promote this result!");
1682 SDValue Res = GetPromotedInteger(Op);
1683 assert(Res.getValueType() == N->getValueType(0) &&
1684 "Operand over promoted?");
1685 // Split the promoted operand. This will simplify when it is expanded.
1686 SplitInteger(Res, Lo, Hi);
1687 unsigned ExcessBits =
1688 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1689 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1690 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1694 void DAGTypeLegalizer::
1695 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1696 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1697 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1699 if (EVT.bitsLE(Lo.getValueType())) {
1700 // sext_inreg the low part if needed.
1701 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1704 // The high part gets the sign extension from the lo-part. This handles
1705 // things like sextinreg V:i64 from i8.
1706 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1707 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1708 TLI.getShiftAmountTy()));
1710 // For example, extension of an i48 to an i64. Leave the low part alone,
1711 // sext_inreg the high part.
1712 unsigned ExcessBits =
1713 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1714 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1715 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1719 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1720 SDValue &Lo, SDValue &Hi) {
1721 MVT VT = N->getValueType(0);
1723 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1725 LC = RTLIB::SREM_I32;
1726 else if (VT == MVT::i64)
1727 LC = RTLIB::SREM_I64;
1728 else if (VT == MVT::i128)
1729 LC = RTLIB::SREM_I128;
1730 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1732 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1733 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1736 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1737 SDValue &Lo, SDValue &Hi) {
1738 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1739 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1740 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1741 DAG.getConstant(NVT.getSizeInBits(),
1742 TLI.getShiftAmountTy()));
1743 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1746 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1747 SDValue &Lo, SDValue &Hi) {
1748 MVT VT = N->getValueType(0);
1750 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1752 LC = RTLIB::UDIV_I32;
1753 else if (VT == MVT::i64)
1754 LC = RTLIB::UDIV_I64;
1755 else if (VT == MVT::i128)
1756 LC = RTLIB::UDIV_I128;
1757 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1759 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1760 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1763 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1764 SDValue &Lo, SDValue &Hi) {
1765 MVT VT = N->getValueType(0);
1767 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1769 LC = RTLIB::UREM_I32;
1770 else if (VT == MVT::i64)
1771 LC = RTLIB::UREM_I64;
1772 else if (VT == MVT::i128)
1773 LC = RTLIB::UREM_I128;
1774 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1776 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1777 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1780 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1781 SDValue &Lo, SDValue &Hi) {
1782 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1783 SDValue Op = N->getOperand(0);
1784 if (Op.getValueType().bitsLE(NVT)) {
1785 // The low part is zero extension of the input (which degenerates to a copy).
1786 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1787 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1789 // For example, extension of an i48 to an i64. The operand type necessarily
1790 // promotes to the result type, so will end up being expanded too.
1791 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1792 "Only know how to promote this result!");
1793 SDValue Res = GetPromotedInteger(Op);
1794 assert(Res.getValueType() == N->getValueType(0) &&
1795 "Operand over promoted?");
1796 // Split the promoted operand. This will simplify when it is expanded.
1797 SplitInteger(Res, Lo, Hi);
1798 unsigned ExcessBits =
1799 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1800 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1805 //===----------------------------------------------------------------------===//
1806 // Integer Operand Expansion
1807 //===----------------------------------------------------------------------===//
1809 /// ExpandIntegerOperand - This method is called when the specified operand of
1810 /// the specified node is found to need expansion. At this point, all of the
1811 /// result types of the node are known to be legal, but other operands of the
1812 /// node may need promotion or expansion as well as the specified one.
1813 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1814 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1815 SDValue Res = SDValue();
1817 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1818 == TargetLowering::Custom)
1819 Res = TLI.LowerOperation(SDValue(N, OpNo), DAG);
1821 if (Res.getNode() == 0) {
1822 switch (N->getOpcode()) {
1825 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1826 N->dump(&DAG); cerr << "\n";
1828 assert(0 && "Do not know how to expand this operator's operand!");
1831 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1832 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1833 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1835 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1836 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1837 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1838 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1839 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1841 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1842 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1846 // If the result is null, the sub-method took care of registering results etc.
1847 if (!Res.getNode()) return false;
1848 // If the result is N, the sub-method updated N in place. Check to see if any
1849 // operands are new, and if so, mark them.
1850 if (Res.getNode() == N) {
1851 // Mark N as new and remark N and its operands. This allows us to correctly
1852 // revisit N if it needs another step of expansion and allows us to visit
1853 // any new operands to N.
1858 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1859 "Invalid operand expansion");
1861 ReplaceValueWith(SDValue(N, 0), Res);
1865 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1866 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1867 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1869 ISD::CondCode &CCCode) {
1870 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1871 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1872 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1874 MVT VT = NewLHS.getValueType();
1876 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1877 if (RHSLo == RHSHi) {
1878 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1879 if (RHSCST->isAllOnesValue()) {
1880 // Equality comparison to -1.
1881 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1888 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1889 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1890 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1891 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1895 // If this is a comparison of the sign bit, just look at the top part.
1897 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1898 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1899 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1905 // FIXME: This generated code sucks.
1906 ISD::CondCode LowCC;
1908 default: assert(0 && "Unknown integer setcc!");
1910 case ISD::SETULT: LowCC = ISD::SETULT; break;
1912 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1914 case ISD::SETULE: LowCC = ISD::SETULE; break;
1916 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1919 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1920 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1921 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1923 // NOTE: on targets without efficient SELECT of bools, we can always use
1924 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1925 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1927 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1928 false, DagCombineInfo);
1929 if (!Tmp1.getNode())
1930 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1931 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1932 CCCode, false, DagCombineInfo);
1933 if (!Tmp2.getNode())
1934 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1935 DAG.getCondCode(CCCode));
1937 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
1938 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
1939 if ((Tmp1C && Tmp1C->isNullValue()) ||
1940 (Tmp2C && Tmp2C->isNullValue() &&
1941 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1942 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1943 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1944 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1945 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1946 // low part is known false, returns high part.
1947 // For LE / GE, if high part is known false, ignore the low part.
1948 // For LT / GT, if high part is known true, ignore the low part.
1954 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1955 ISD::SETEQ, false, DagCombineInfo);
1956 if (!NewLHS.getNode())
1957 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1959 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1960 NewLHS, Tmp1, Tmp2);
1964 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1965 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1966 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1967 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1969 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1970 // against zero to select between true and false values.
1971 if (NewRHS.getNode() == 0) {
1972 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1973 CCCode = ISD::SETNE;
1976 // Update N to have the operands specified.
1977 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
1978 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1982 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1983 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1984 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1985 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1987 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1988 // against zero to select between true and false values.
1989 if (NewRHS.getNode() == 0) {
1990 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1991 CCCode = ISD::SETNE;
1994 // Update N to have the operands specified.
1995 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
1996 N->getOperand(2), N->getOperand(3),
1997 DAG.getCondCode(CCCode));
2000 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2001 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2002 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2003 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2005 // If ExpandSetCCOperands returned a scalar, use it.
2006 if (NewRHS.getNode() == 0) {
2007 assert(NewLHS.getValueType() == N->getValueType(0) &&
2008 "Unexpected setcc expansion!");
2012 // Otherwise, update N to have the operands specified.
2013 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2014 DAG.getCondCode(CCCode));
2017 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2018 SDValue Op = N->getOperand(0);
2019 MVT DstVT = N->getValueType(0);
2020 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2021 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2022 "Don't know how to expand this SINT_TO_FP!");
2023 return MakeLibCall(LC, DstVT, &Op, 1, true);
2026 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2027 if (ISD::isNormalStore(N))
2028 return ExpandOp_NormalStore(N, OpNo);
2030 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2031 assert(OpNo == 1 && "Can only expand the stored value so far");
2033 MVT VT = N->getOperand(1).getValueType();
2034 MVT NVT = TLI.getTypeToTransformTo(VT);
2035 SDValue Ch = N->getChain();
2036 SDValue Ptr = N->getBasePtr();
2037 int SVOffset = N->getSrcValueOffset();
2038 unsigned Alignment = N->getAlignment();
2039 bool isVolatile = N->isVolatile();
2042 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2044 if (N->getMemoryVT().bitsLE(NVT)) {
2045 GetExpandedInteger(N->getValue(), Lo, Hi);
2046 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2047 N->getMemoryVT(), isVolatile, Alignment);
2048 } else if (TLI.isLittleEndian()) {
2049 // Little-endian - low bits are at low addresses.
2050 GetExpandedInteger(N->getValue(), Lo, Hi);
2052 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2053 isVolatile, Alignment);
2055 unsigned ExcessBits =
2056 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2057 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2059 // Increment the pointer to the other half.
2060 unsigned IncrementSize = NVT.getSizeInBits()/8;
2061 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2062 DAG.getIntPtrConstant(IncrementSize));
2063 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2064 SVOffset+IncrementSize, NEVT,
2065 isVolatile, MinAlign(Alignment, IncrementSize));
2066 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2068 // Big-endian - high bits are at low addresses. Favor aligned stores at
2069 // the cost of some bit-fiddling.
2070 GetExpandedInteger(N->getValue(), Lo, Hi);
2072 MVT EVT = N->getMemoryVT();
2073 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2074 unsigned IncrementSize = NVT.getSizeInBits()/8;
2075 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2076 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2078 if (ExcessBits < NVT.getSizeInBits()) {
2079 // Transfer high bits from the top of Lo to the bottom of Hi.
2080 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2081 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2082 TLI.getShiftAmountTy()));
2083 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2084 DAG.getNode(ISD::SRL, NVT, Lo,
2085 DAG.getConstant(ExcessBits,
2086 TLI.getShiftAmountTy())));
2089 // Store both the high bits and maybe some of the low bits.
2090 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2091 SVOffset, HiVT, isVolatile, Alignment);
2093 // Increment the pointer to the other half.
2094 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2095 DAG.getIntPtrConstant(IncrementSize));
2096 // Store the lowest ExcessBits bits in the second half.
2097 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2098 SVOffset+IncrementSize,
2099 MVT::getIntegerVT(ExcessBits),
2100 isVolatile, MinAlign(Alignment, IncrementSize));
2101 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2105 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2107 GetExpandedInteger(N->getOperand(0), InL, InH);
2108 // Just truncate the low part of the source.
2109 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2112 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2113 SDValue Op = N->getOperand(0);
2114 MVT SrcVT = Op.getValueType();
2115 MVT DstVT = N->getValueType(0);
2117 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2118 // Do a signed conversion then adjust the result.
2119 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2120 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2122 // The result of the signed conversion needs adjusting if the 'sign bit' of
2123 // the incoming integer was set. To handle this, we dynamically test to see
2124 // if it is set, and, if so, add a fudge factor.
2126 const uint64_t F32TwoE32 = 0x4F800000ULL;
2127 const uint64_t F32TwoE64 = 0x5F800000ULL;
2128 const uint64_t F32TwoE128 = 0x7F800000ULL;
2131 if (SrcVT == MVT::i32)
2132 FF = APInt(32, F32TwoE32);
2133 else if (SrcVT == MVT::i64)
2134 FF = APInt(32, F32TwoE64);
2135 else if (SrcVT == MVT::i128)
2136 FF = APInt(32, F32TwoE128);
2138 assert(false && "Unsupported UINT_TO_FP!");
2140 // Check whether the sign bit is set.
2142 GetExpandedInteger(Op, Lo, Hi);
2143 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2144 DAG.getConstant(0, Hi.getValueType()),
2147 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2148 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2149 TLI.getPointerTy());
2151 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2152 SDValue Zero = DAG.getIntPtrConstant(0);
2153 SDValue Four = DAG.getIntPtrConstant(4);
2154 if (TLI.isBigEndian()) std::swap(Zero, Four);
2155 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2157 unsigned Alignment =
2158 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2159 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2160 Alignment = std::min(Alignment, 4u);
2162 // Load the value out, extending it from f32 to the destination float type.
2163 // FIXME: Avoid the extend by constructing the right constant pool?
2164 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2165 FudgePtr, NULL, 0, MVT::f32,
2167 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2170 // Otherwise, use a libcall.
2171 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2172 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2173 "Don't know how to expand this UINT_TO_FP!");
2174 return MakeLibCall(LC, DstVT, &Op, 1, true);