1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Result = SDValue();
36 // See if the target wants to custom expand this node.
37 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
38 TargetLowering::Custom) {
39 // If the target wants to, allow it to lower this itself.
40 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
41 // Everything that once used N now uses P. We are guaranteed that the
42 // result value types of N and the result value types of P match.
43 ReplaceNodeWith(N, P);
48 switch (N->getOpcode()) {
51 cerr << "PromoteIntegerResult #" << ResNo << ": ";
52 N->dump(&DAG); cerr << "\n";
54 assert(0 && "Do not know how to promote this operator!");
56 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
57 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
59 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
60 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
61 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
62 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
65 case ISD::EXTRACT_VECTOR_ELT:
66 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
67 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
68 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
69 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
80 case ISD::SIGN_EXTEND:
81 case ISD::ZERO_EXTEND:
82 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
85 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
92 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
95 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
98 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
100 case ISD::ATOMIC_LOAD_ADD_8:
101 case ISD::ATOMIC_LOAD_SUB_8:
102 case ISD::ATOMIC_LOAD_AND_8:
103 case ISD::ATOMIC_LOAD_OR_8:
104 case ISD::ATOMIC_LOAD_XOR_8:
105 case ISD::ATOMIC_LOAD_NAND_8:
106 case ISD::ATOMIC_LOAD_MIN_8:
107 case ISD::ATOMIC_LOAD_MAX_8:
108 case ISD::ATOMIC_LOAD_UMIN_8:
109 case ISD::ATOMIC_LOAD_UMAX_8:
110 case ISD::ATOMIC_SWAP_8:
111 case ISD::ATOMIC_LOAD_ADD_16:
112 case ISD::ATOMIC_LOAD_SUB_16:
113 case ISD::ATOMIC_LOAD_AND_16:
114 case ISD::ATOMIC_LOAD_OR_16:
115 case ISD::ATOMIC_LOAD_XOR_16:
116 case ISD::ATOMIC_LOAD_NAND_16:
117 case ISD::ATOMIC_LOAD_MIN_16:
118 case ISD::ATOMIC_LOAD_MAX_16:
119 case ISD::ATOMIC_LOAD_UMIN_16:
120 case ISD::ATOMIC_LOAD_UMAX_16:
121 case ISD::ATOMIC_SWAP_16:
122 case ISD::ATOMIC_LOAD_ADD_32:
123 case ISD::ATOMIC_LOAD_SUB_32:
124 case ISD::ATOMIC_LOAD_AND_32:
125 case ISD::ATOMIC_LOAD_OR_32:
126 case ISD::ATOMIC_LOAD_XOR_32:
127 case ISD::ATOMIC_LOAD_NAND_32:
128 case ISD::ATOMIC_LOAD_MIN_32:
129 case ISD::ATOMIC_LOAD_MAX_32:
130 case ISD::ATOMIC_LOAD_UMIN_32:
131 case ISD::ATOMIC_LOAD_UMAX_32:
132 case ISD::ATOMIC_SWAP_32:
133 case ISD::ATOMIC_LOAD_ADD_64:
134 case ISD::ATOMIC_LOAD_SUB_64:
135 case ISD::ATOMIC_LOAD_AND_64:
136 case ISD::ATOMIC_LOAD_OR_64:
137 case ISD::ATOMIC_LOAD_XOR_64:
138 case ISD::ATOMIC_LOAD_NAND_64:
139 case ISD::ATOMIC_LOAD_MIN_64:
140 case ISD::ATOMIC_LOAD_MAX_64:
141 case ISD::ATOMIC_LOAD_UMIN_64:
142 case ISD::ATOMIC_LOAD_UMAX_64:
143 case ISD::ATOMIC_SWAP_64:
144 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
146 case ISD::ATOMIC_CMP_SWAP_8:
147 case ISD::ATOMIC_CMP_SWAP_16:
148 case ISD::ATOMIC_CMP_SWAP_32:
149 case ISD::ATOMIC_CMP_SWAP_64:
150 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
153 // If Result is null, the sub-method took care of registering the result.
154 if (Result.getNode())
155 SetPromotedInteger(SDValue(N, ResNo), Result);
158 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
159 // Sign-extend the new bits, and continue the assertion.
160 MVT OldVT = N->getValueType(0);
161 SDValue Op = GetPromotedInteger(N->getOperand(0));
162 return DAG.getNode(ISD::AssertSext, Op.getValueType(),
163 DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
164 DAG.getValueType(OldVT)), N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
168 // Zero the new bits, and continue the assertion.
169 MVT OldVT = N->getValueType(0);
170 SDValue Op = GetPromotedInteger(N->getOperand(0));
171 return DAG.getNode(ISD::AssertZext, Op.getValueType(),
172 DAG.getZeroExtendInReg(Op, OldVT), N->getOperand(1));
175 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
176 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
177 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
178 Op2, N->getSrcValue(), N->getAlignment());
179 // Legalized the chain result - switch anything that used the old chain to
181 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
185 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
186 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
187 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
188 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
189 Op2, Op3, N->getSrcValue(), N->getAlignment());
190 // Legalized the chain result - switch anything that used the old chain to
192 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
196 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
197 SDValue InOp = N->getOperand(0);
198 MVT InVT = InOp.getValueType();
199 MVT NInVT = TLI.getTypeToTransformTo(InVT);
200 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
202 switch (getTypeAction(InVT)) {
204 assert(false && "Unknown type action!");
209 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
210 // The input promotes to the same size. Convert the promoted value.
211 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
214 // Promote the integer operand by hand.
215 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
219 case ScalarizeVector:
220 // Convert the element to an integer and promote it by hand.
221 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
222 BitConvertToInteger(GetScalarizedVector(InOp)));
224 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
225 // pieces of the input into integers and reassemble in the final type.
227 GetSplitVector(N->getOperand(0), Lo, Hi);
228 Lo = BitConvertToInteger(Lo);
229 Hi = BitConvertToInteger(Hi);
231 if (TLI.isBigEndian())
234 InOp = DAG.getNode(ISD::ANY_EXTEND,
235 MVT::getIntegerVT(OutVT.getSizeInBits()),
236 JoinIntegers(Lo, Hi));
237 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
240 // Otherwise, lower the bit-convert to a store/load from the stack, then
242 SDValue Op = CreateStackStoreLoad(InOp, N->getValueType(0));
243 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.getNode()));
246 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
247 SDValue Op = GetPromotedInteger(N->getOperand(0));
248 MVT OVT = N->getValueType(0);
249 MVT NVT = Op.getValueType();
251 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
252 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
253 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
256 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
257 // The pair element type may be legal, or may not promote to the same type as
258 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
259 return DAG.getNode(ISD::ANY_EXTEND,
260 TLI.getTypeToTransformTo(N->getValueType(0)),
261 JoinIntegers(N->getOperand(0), N->getOperand(1)));
264 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
265 MVT VT = N->getValueType(0);
266 // Zero extend things like i1, sign extend everything else. It shouldn't
267 // matter in theory which one we pick, but this tends to give better code?
268 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
269 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
271 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
275 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
276 SDValue Op = GetPromotedInteger(N->getOperand(0));
277 MVT OVT = N->getValueType(0);
278 MVT NVT = Op.getValueType();
279 // Zero extend to the promoted type and do the count there.
280 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
281 // Subtract off the extra leading bits in the bigger type.
282 return DAG.getNode(ISD::SUB, NVT, Op,
283 DAG.getConstant(NVT.getSizeInBits() -
284 OVT.getSizeInBits(), NVT));
287 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
288 SDValue Op = GetPromotedInteger(N->getOperand(0));
289 MVT OVT = N->getValueType(0);
290 MVT NVT = Op.getValueType();
291 // Zero extend to the promoted type and do the count there.
292 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
295 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
296 SDValue Op = GetPromotedInteger(N->getOperand(0));
297 MVT OVT = N->getValueType(0);
298 MVT NVT = Op.getValueType();
299 // The count is the same in the promoted type except if the original
300 // value was zero. This can be handled by setting the bit just off
301 // the top of the original type.
302 APInt TopBit(NVT.getSizeInBits(), 0);
303 TopBit.set(OVT.getSizeInBits());
304 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
305 return DAG.getNode(ISD::CTTZ, NVT, Op);
308 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
309 MVT OldVT = N->getValueType(0);
310 SDValue OldVec = N->getOperand(0);
311 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getShiftAmountTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getShiftAmountTy()));
345 if (TLI.isBigEndian())
348 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
349 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
352 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
353 unsigned NewOpc = N->getOpcode();
354 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 // If we're promoting a UINT to a larger size, check to see if the new node
357 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
358 // we can use that instead. This allows us to generate better code for
359 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
360 // legal, such as PowerPC.
361 if (N->getOpcode() == ISD::FP_TO_UINT) {
362 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
363 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
364 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
365 NewOpc = ISD::FP_TO_SINT;
368 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
371 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
372 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
374 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
375 SDValue Res = GetPromotedInteger(N->getOperand(0));
376 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
377 "Extension doesn't make sense!");
379 // If the result and operand types are the same after promotion, simplify
380 // to an in-register extension.
381 if (NVT == Res.getValueType()) {
382 // The high bits are not guaranteed to be anything. Insert an extend.
383 if (N->getOpcode() == ISD::SIGN_EXTEND)
384 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
385 DAG.getValueType(N->getOperand(0).getValueType()));
386 if (N->getOpcode() == ISD::ZERO_EXTEND)
387 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
388 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
393 // Otherwise, just extend the original operand all the way to the larger type.
394 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
397 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
398 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
399 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
400 ISD::LoadExtType ExtType =
401 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
402 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
403 N->getSrcValue(), N->getSrcValueOffset(),
404 N->getMemoryVT(), N->isVolatile(),
407 // Legalized the chain result - switch anything that used the old chain to
409 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
413 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
414 // Sign extend the input.
415 SDValue LHS = GetPromotedInteger(N->getOperand(0));
416 SDValue RHS = GetPromotedInteger(N->getOperand(1));
417 MVT VT = N->getValueType(0);
418 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
419 DAG.getValueType(VT));
420 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
421 DAG.getValueType(VT));
423 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
426 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
427 SDValue LHS = GetPromotedInteger(N->getOperand(1));
428 SDValue RHS = GetPromotedInteger(N->getOperand(2));
429 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
432 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
433 SDValue LHS = GetPromotedInteger(N->getOperand(2));
434 SDValue RHS = GetPromotedInteger(N->getOperand(3));
435 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
436 N->getOperand(1), LHS, RHS, N->getOperand(4));
439 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
440 MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
441 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
443 // Get the SETCC result using the canonical SETCC type.
444 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
445 N->getOperand(1), N->getOperand(2));
447 // Convert to the expected type.
448 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
449 assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
450 "Integer type overpromoted?");
451 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
454 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
455 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
456 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
459 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
460 SDValue Op = GetPromotedInteger(N->getOperand(0));
461 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
465 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
466 // The input may have strange things in the top bits of the registers, but
467 // these operations don't care. They may have weird bits going out, but
468 // that too is okay if they are integer operations.
469 SDValue LHS = GetPromotedInteger(N->getOperand(0));
470 SDValue RHS = GetPromotedInteger(N->getOperand(1));
471 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
474 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
475 // The input value must be properly sign extended.
476 MVT VT = N->getValueType(0);
477 MVT NVT = TLI.getTypeToTransformTo(VT);
478 SDValue Res = GetPromotedInteger(N->getOperand(0));
479 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
480 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
483 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
484 // The input value must be properly zero extended.
485 MVT VT = N->getValueType(0);
486 MVT NVT = TLI.getTypeToTransformTo(VT);
487 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
488 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
491 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
494 switch (getTypeAction(N->getOperand(0).getValueType())) {
495 default: assert(0 && "Unknown type action!");
498 Res = N->getOperand(0);
501 Res = GetPromotedInteger(N->getOperand(0));
505 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
506 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
507 "Truncation doesn't make sense!");
508 if (Res.getValueType() == NVT)
511 // Truncate to NVT instead of VT
512 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
515 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
516 // Zero extend the input.
517 SDValue LHS = GetPromotedInteger(N->getOperand(0));
518 SDValue RHS = GetPromotedInteger(N->getOperand(1));
519 MVT VT = N->getValueType(0);
520 LHS = DAG.getZeroExtendInReg(LHS, VT);
521 RHS = DAG.getZeroExtendInReg(RHS, VT);
523 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
526 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
527 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
530 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
531 SDValue Chain = N->getOperand(0); // Get the chain.
532 SDValue Ptr = N->getOperand(1); // Get the pointer.
533 MVT VT = N->getValueType(0);
535 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
536 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
538 // Increment the arg pointer, VAList, to the next vaarg
539 // FIXME: should the ABI size be used for the increment? Think of
540 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
541 // integers of unusual size (such MVT::i1, which gives an increment
543 unsigned Increment = VT.getSizeInBits() / 8;
544 SDValue Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
545 DAG.getIntPtrConstant(Increment));
547 // Store the incremented VAList to the pointer.
548 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
550 // Load the actual argument out of the arg pointer VAList.
551 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
552 VAList, NULL, 0, VT);
554 // Legalized the chain result - switch anything that used the old chain to
556 ReplaceValueWith(SDValue(N, 1), Tmp.getValue(1));
561 //===----------------------------------------------------------------------===//
562 // Integer Operand Promotion
563 //===----------------------------------------------------------------------===//
565 /// PromoteIntegerOperand - This method is called when the specified operand of
566 /// the specified node is found to need promotion. At this point, all of the
567 /// result types of the node are known to be legal, but other operands of the
568 /// node may need promotion or expansion as well as the specified one.
569 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
570 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
571 SDValue Res = SDValue();
573 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
574 == TargetLowering::Custom)
575 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
577 if (Res.getNode() == 0) {
578 switch (N->getOpcode()) {
581 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
582 N->dump(&DAG); cerr << "\n";
584 assert(0 && "Do not know how to promote this operator's operand!");
587 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
588 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
589 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
590 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
591 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
592 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
593 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
594 case ISD::INSERT_VECTOR_ELT:
595 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
596 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
597 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
598 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
599 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
600 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
601 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
603 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
604 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
606 case ISD::SINT_TO_FP:
607 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
611 // If the result is null, the sub-method took care of registering results etc.
612 if (!Res.getNode()) return false;
613 // If the result is N, the sub-method updated N in place.
614 if (Res.getNode() == N) {
615 // Mark N as new and remark N and its operands. This allows us to correctly
616 // revisit N if it needs another step of promotion and allows us to visit
617 // any new operands to N.
622 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
623 "Invalid operand expansion");
625 ReplaceValueWith(SDValue(N, 0), Res);
629 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
630 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
631 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
632 ISD::CondCode CCCode) {
633 MVT VT = NewLHS.getValueType();
635 // Get the promoted values.
636 NewLHS = GetPromotedInteger(NewLHS);
637 NewRHS = GetPromotedInteger(NewRHS);
639 // Otherwise, we have to insert explicit sign or zero extends. Note
640 // that we could insert sign extends for ALL conditions, but zero extend
641 // is cheaper on many machines (an AND instead of two shifts), so prefer
644 default: assert(0 && "Unknown integer comparison!");
651 // ALL of these operations will work if we either sign or zero extend
652 // the operands (including the unsigned comparisons!). Zero extend is
653 // usually a simpler/cheaper operation, so prefer it.
654 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
655 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
661 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
662 DAG.getValueType(VT));
663 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
664 DAG.getValueType(VT));
669 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
670 SDValue Op = GetPromotedInteger(N->getOperand(0));
671 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
674 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
675 assert(OpNo == 2 && "Don't know how to promote this operand!");
677 SDValue LHS = N->getOperand(2);
678 SDValue RHS = N->getOperand(3);
679 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
681 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
683 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
684 N->getOperand(1), LHS, RHS, N->getOperand(4));
687 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
688 assert(OpNo == 1 && "only know how to promote condition");
689 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
691 // The top bits of the promoted condition are not necessarily zero, ensure
692 // that the value is properly zero extended.
693 unsigned BitWidth = Cond.getValueSizeInBits();
694 if (!DAG.MaskedValueIsZero(Cond,
695 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
696 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
698 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
699 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
703 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
704 // Since the result type is legal, the operands must promote to it.
705 MVT OVT = N->getOperand(0).getValueType();
706 SDValue Lo = GetPromotedInteger(N->getOperand(0));
707 SDValue Hi = GetPromotedInteger(N->getOperand(1));
708 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
710 Lo = DAG.getZeroExtendInReg(Lo, OVT);
711 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
712 DAG.getConstant(OVT.getSizeInBits(),
713 TLI.getShiftAmountTy()));
714 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
717 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
718 // The vector type is legal but the element type is not. This implies
719 // that the vector is a power-of-two in length and that the element
720 // type does not have a strange size (eg: it is not i1).
721 MVT VecVT = N->getValueType(0);
722 unsigned NumElts = VecVT.getVectorNumElements();
723 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
725 // Build a vector of half the length out of elements of twice the bitwidth.
726 // For example <4 x i16> -> <2 x i32>.
727 MVT OldVT = N->getOperand(0).getValueType();
728 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
729 assert(OldVT.isSimple() && NewVT.isSimple());
731 std::vector<SDValue> NewElts;
732 NewElts.reserve(NumElts/2);
734 for (unsigned i = 0; i < NumElts; i += 2) {
735 // Combine two successive elements into one promoted element.
736 SDValue Lo = N->getOperand(i);
737 SDValue Hi = N->getOperand(i+1);
738 if (TLI.isBigEndian())
740 NewElts.push_back(JoinIntegers(Lo, Hi));
743 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
744 MVT::getVectorVT(NewVT, NewElts.size()),
745 &NewElts[0], NewElts.size());
747 // Convert the new vector to the old vector type.
748 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
751 SDValue DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
752 SDValue Op = GetPromotedInteger(N->getOperand(0));
753 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
756 SDValue DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
757 SDValue Op = GetPromotedInteger(N->getOperand(0));
758 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
759 DAG.getIntPtrConstant(0));
762 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
765 // Promote the inserted value. This is valid because the type does not
766 // have to match the vector element type.
768 // Check that any extra bits introduced will be truncated away.
769 assert(N->getOperand(1).getValueType().getSizeInBits() >=
770 N->getValueType(0).getVectorElementType().getSizeInBits() &&
771 "Type of inserted value narrower than vector element type!");
772 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
773 GetPromotedInteger(N->getOperand(1)),
777 assert(OpNo == 2 && "Different operand and result vector types?");
779 // Promote the index.
780 SDValue Idx = N->getOperand(2);
781 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
782 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
783 N->getOperand(1), Idx);
786 SDValue DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
787 SDValue In = GetPromotedInteger(N->getOperand(0));
788 MVT OpVT = N->getOperand(0).getValueType();
789 if (N->getOpcode() == ISD::UINT_TO_FP)
790 In = DAG.getZeroExtendInReg(In, OpVT);
792 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
793 In, DAG.getValueType(OpVT));
795 return DAG.UpdateNodeOperands(SDValue(N, 0), In);
798 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
800 NewOps[0] = N->getOperand(0);
801 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
802 SDValue Flag = GetPromotedInteger(N->getOperand(i));
803 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
805 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
806 array_lengthof(NewOps));
809 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
810 assert(OpNo == 0 && "Only know how to promote condition");
811 SDValue Cond = GetPromotedInteger(N->getOperand(0));
813 // Promote all the way up to SVT, the canonical SetCC type.
814 // FIXME: Not clear what value to pass to getSetCCResultType.
815 // [This only matters for CellSPU since all other targets
816 // ignore the argument.] We used to pass Cond, resulting in
817 // SVT = MVT::i8, but CellSPU has no select patterns for i8,
818 // causing an abort later. Passing the result type works
819 // around the problem.
820 MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
821 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
822 assert(Cond.getValueSizeInBits() <= SVT.getSizeInBits() &&
823 "Unexpected SetCC type!");
825 // Make sure the extra bits conform to getSetCCResultContents. There are
826 // two sets of extra bits: those in Cond, which come from type promotion,
827 // and those we need to add to have the final type be SVT (for most targets
828 // this last set of bits is empty).
829 unsigned CondBits = Cond.getValueSizeInBits();
830 ISD::NodeType ExtendCode;
831 switch (TLI.getSetCCResultContents()) {
833 assert(false && "Unknown SetCCResultValue!");
834 case TargetLowering::UndefinedSetCCResult:
835 // Extend to SVT by adding rubbish.
836 ExtendCode = ISD::ANY_EXTEND;
838 case TargetLowering::ZeroOrOneSetCCResult:
839 ExtendCode = ISD::ZERO_EXTEND;
840 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
841 // All extra bits need to be cleared. Do this by zero extending the
842 // original condition value all the way to SVT.
843 Cond = N->getOperand(0);
845 case TargetLowering::ZeroOrNegativeOneSetCCResult: {
846 ExtendCode = ISD::SIGN_EXTEND;
847 unsigned SignBits = DAG.ComputeNumSignBits(Cond);
848 if (SignBits != CondBits)
849 // All extra bits need to be sign extended. Do this by sign extending the
850 // original condition value all the way to SVT.
851 Cond = N->getOperand(0);
855 Cond = DAG.getNode(ExtendCode, SVT, Cond);
857 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
858 N->getOperand(1), N->getOperand(2));
861 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
862 assert(OpNo == 0 && "Don't know how to promote this operand!");
864 SDValue LHS = N->getOperand(0);
865 SDValue RHS = N->getOperand(1);
866 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
868 // The CC (#4) and the possible return values (#2 and #3) have legal types.
869 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
870 N->getOperand(3), N->getOperand(4));
873 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
874 assert(OpNo == 0 && "Don't know how to promote this operand!");
876 SDValue LHS = N->getOperand(0);
877 SDValue RHS = N->getOperand(1);
878 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
880 // The CC (#2) is always legal.
881 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
884 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
885 SDValue Op = GetPromotedInteger(N->getOperand(0));
886 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
887 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
888 Op, DAG.getValueType(N->getOperand(0).getValueType()));
891 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
892 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
893 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
894 int SVOffset = N->getSrcValueOffset();
895 unsigned Alignment = N->getAlignment();
896 bool isVolatile = N->isVolatile();
898 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
900 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
902 // Truncate the value and store the result.
903 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
904 SVOffset, N->getMemoryVT(),
905 isVolatile, Alignment);
908 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
909 SDValue Op = GetPromotedInteger(N->getOperand(0));
910 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
913 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
914 SDValue Op = GetPromotedInteger(N->getOperand(0));
915 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
916 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
920 //===----------------------------------------------------------------------===//
921 // Integer Result Expansion
922 //===----------------------------------------------------------------------===//
924 /// ExpandIntegerResult - This method is called when the specified result of the
925 /// specified node is found to need expansion. At this point, the node may also
926 /// have invalid operands or may have other results that need promotion, we just
927 /// know that (at least) one result needs expansion.
928 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
929 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
933 // See if the target wants to custom expand this node.
934 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(ResNo)) ==
935 TargetLowering::Custom) {
936 // If the target wants to, allow it to lower this itself.
937 if (SDNode *P = TLI.ReplaceNodeResults(N, DAG)) {
938 // Everything that once used N now uses P. We are guaranteed that the
939 // result value types of N and the result value types of P match.
940 ReplaceNodeWith(N, P);
945 switch (N->getOpcode()) {
948 cerr << "ExpandIntegerResult #" << ResNo << ": ";
949 N->dump(&DAG); cerr << "\n";
951 assert(0 && "Do not know how to expand the result of this operator!");
954 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
955 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
956 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
957 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
959 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
960 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
961 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
962 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
964 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
965 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
966 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
967 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
968 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
969 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
970 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
971 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
972 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
973 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
974 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
975 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
976 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
977 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
978 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
979 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
980 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
981 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
982 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
983 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
987 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
990 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
993 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
996 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1000 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1003 // If Lo/Hi is null, the sub-method took care of registering results etc.
1005 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1008 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1009 /// and the shift amount is a constant 'Amt'. Expand the operation.
1010 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1011 SDValue &Lo, SDValue &Hi) {
1012 // Expand the incoming operand to be shifted, so that we have its parts
1014 GetExpandedInteger(N->getOperand(0), InL, InH);
1016 MVT NVT = InL.getValueType();
1017 unsigned VTBits = N->getValueType(0).getSizeInBits();
1018 unsigned NVTBits = NVT.getSizeInBits();
1019 MVT ShTy = N->getOperand(1).getValueType();
1021 if (N->getOpcode() == ISD::SHL) {
1023 Lo = Hi = DAG.getConstant(0, NVT);
1024 } else if (Amt > NVTBits) {
1025 Lo = DAG.getConstant(0, NVT);
1026 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1027 } else if (Amt == NVTBits) {
1028 Lo = DAG.getConstant(0, NVT);
1030 } else if (Amt == 1) {
1031 // Emit this X << 1 as X+X.
1032 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1033 SDValue LoOps[2] = { InL, InL };
1034 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1035 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1036 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1038 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1039 Hi = DAG.getNode(ISD::OR, NVT,
1040 DAG.getNode(ISD::SHL, NVT, InH,
1041 DAG.getConstant(Amt, ShTy)),
1042 DAG.getNode(ISD::SRL, NVT, InL,
1043 DAG.getConstant(NVTBits-Amt, ShTy)));
1048 if (N->getOpcode() == ISD::SRL) {
1050 Lo = DAG.getConstant(0, NVT);
1051 Hi = DAG.getConstant(0, NVT);
1052 } else if (Amt > NVTBits) {
1053 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1054 Hi = DAG.getConstant(0, NVT);
1055 } else if (Amt == NVTBits) {
1057 Hi = DAG.getConstant(0, NVT);
1059 Lo = DAG.getNode(ISD::OR, NVT,
1060 DAG.getNode(ISD::SRL, NVT, InL,
1061 DAG.getConstant(Amt, ShTy)),
1062 DAG.getNode(ISD::SHL, NVT, InH,
1063 DAG.getConstant(NVTBits-Amt, ShTy)));
1064 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1069 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1071 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1072 DAG.getConstant(NVTBits-1, ShTy));
1073 } else if (Amt > NVTBits) {
1074 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1075 DAG.getConstant(Amt-NVTBits, ShTy));
1076 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1077 DAG.getConstant(NVTBits-1, ShTy));
1078 } else if (Amt == NVTBits) {
1080 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1081 DAG.getConstant(NVTBits-1, ShTy));
1083 Lo = DAG.getNode(ISD::OR, NVT,
1084 DAG.getNode(ISD::SRL, NVT, InL,
1085 DAG.getConstant(Amt, ShTy)),
1086 DAG.getNode(ISD::SHL, NVT, InH,
1087 DAG.getConstant(NVTBits-Amt, ShTy)));
1088 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1092 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1093 /// this shift based on knowledge of the high bit of the shift amount. If we
1094 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1096 bool DAGTypeLegalizer::
1097 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1098 SDValue Amt = N->getOperand(1);
1099 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1100 MVT ShTy = Amt.getValueType();
1101 unsigned ShBits = ShTy.getSizeInBits();
1102 unsigned NVTBits = NVT.getSizeInBits();
1103 assert(isPowerOf2_32(NVTBits) &&
1104 "Expanded integer type size not a power of two!");
1106 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1107 APInt KnownZero, KnownOne;
1108 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1110 // If we don't know anything about the high bits, exit.
1111 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1114 // Get the incoming operand to be shifted.
1116 GetExpandedInteger(N->getOperand(0), InL, InH);
1118 // If we know that any of the high bits of the shift amount are one, then we
1119 // can do this as a couple of simple shifts.
1120 if (KnownOne.intersects(HighBitMask)) {
1121 // Mask out the high bit, which we know is set.
1122 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1123 DAG.getConstant(~HighBitMask, ShTy));
1125 switch (N->getOpcode()) {
1126 default: assert(0 && "Unknown shift");
1128 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1129 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1132 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1133 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1136 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1137 DAG.getConstant(NVTBits-1, ShTy));
1138 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1143 // If we know that all of the high bits of the shift amount are zero, then we
1144 // can do this as a couple of simple shifts.
1145 if ((KnownZero & HighBitMask) == HighBitMask) {
1147 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1148 DAG.getConstant(NVTBits, ShTy),
1151 switch (N->getOpcode()) {
1152 default: assert(0 && "Unknown shift");
1153 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1155 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1158 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1159 Hi = DAG.getNode(ISD::OR, NVT,
1160 DAG.getNode(Op1, NVT, InH, Amt),
1161 DAG.getNode(Op2, NVT, InL, Amt2));
1168 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1169 SDValue &Lo, SDValue &Hi) {
1170 // Expand the subcomponents.
1171 SDValue LHSL, LHSH, RHSL, RHSH;
1172 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1173 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1175 MVT NVT = LHSL.getValueType();
1176 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1177 SDValue LoOps[2] = { LHSL, RHSL };
1178 SDValue HiOps[3] = { LHSH, RHSH };
1180 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1181 // them. TODO: Teach operation legalization how to expand unsupported
1182 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1183 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1184 // generate a value of this type in the expanded code sequence.
1186 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC,
1187 TLI.getTypeToExpandTo(NVT));
1190 if (N->getOpcode() == ISD::ADD) {
1191 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1192 HiOps[2] = Lo.getValue(1);
1193 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1195 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1196 HiOps[2] = Lo.getValue(1);
1197 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1200 if (N->getOpcode() == ISD::ADD) {
1201 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
1202 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
1203 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0],
1205 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
1206 DAG.getConstant(1, NVT),
1207 DAG.getConstant(0, NVT));
1208 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1],
1210 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
1211 DAG.getConstant(1, NVT), Carry1);
1212 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
1214 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
1215 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
1216 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
1217 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
1218 DAG.getConstant(1, NVT),
1219 DAG.getConstant(0, NVT));
1220 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
1225 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1226 SDValue &Lo, SDValue &Hi) {
1227 // Expand the subcomponents.
1228 SDValue LHSL, LHSH, RHSL, RHSH;
1229 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1230 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1231 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1232 SDValue LoOps[2] = { LHSL, RHSL };
1233 SDValue HiOps[3] = { LHSH, RHSH };
1235 if (N->getOpcode() == ISD::ADDC) {
1236 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1237 HiOps[2] = Lo.getValue(1);
1238 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1240 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1241 HiOps[2] = Lo.getValue(1);
1242 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1245 // Legalized the flag result - switch anything that used the old flag to
1247 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1250 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1251 SDValue &Lo, SDValue &Hi) {
1252 // Expand the subcomponents.
1253 SDValue LHSL, LHSH, RHSL, RHSH;
1254 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1255 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1256 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1257 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1258 SDValue HiOps[3] = { LHSH, RHSH };
1260 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1261 HiOps[2] = Lo.getValue(1);
1262 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1264 // Legalized the flag result - switch anything that used the old flag to
1266 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1269 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1270 SDValue &Lo, SDValue &Hi) {
1271 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1272 SDValue Op = N->getOperand(0);
1273 if (Op.getValueType().bitsLE(NVT)) {
1274 // The low part is any extension of the input (which degenerates to a copy).
1275 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1276 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1278 // For example, extension of an i48 to an i64. The operand type necessarily
1279 // promotes to the result type, so will end up being expanded too.
1280 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1281 "Only know how to promote this result!");
1282 SDValue Res = GetPromotedInteger(Op);
1283 assert(Res.getValueType() == N->getValueType(0) &&
1284 "Operand over promoted?");
1285 // Split the promoted operand. This will simplify when it is expanded.
1286 SplitInteger(Res, Lo, Hi);
1290 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1291 SDValue &Lo, SDValue &Hi) {
1292 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1293 MVT NVT = Lo.getValueType();
1294 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1295 unsigned NVTBits = NVT.getSizeInBits();
1296 unsigned EVTBits = EVT.getSizeInBits();
1298 if (NVTBits < EVTBits) {
1299 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1300 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1302 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1303 // The high part replicates the sign bit of Lo, make it explicit.
1304 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1305 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1309 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1310 SDValue &Lo, SDValue &Hi) {
1311 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1312 MVT NVT = Lo.getValueType();
1313 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1314 unsigned NVTBits = NVT.getSizeInBits();
1315 unsigned EVTBits = EVT.getSizeInBits();
1317 if (NVTBits < EVTBits) {
1318 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1319 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1321 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1322 // The high part must be zero, make it explicit.
1323 Hi = DAG.getConstant(0, NVT);
1327 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1328 SDValue &Lo, SDValue &Hi) {
1329 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1330 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1331 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1334 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1335 SDValue &Lo, SDValue &Hi) {
1336 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1337 unsigned NBitWidth = NVT.getSizeInBits();
1338 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1339 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1340 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1343 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1344 SDValue &Lo, SDValue &Hi) {
1345 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1346 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1347 MVT NVT = Lo.getValueType();
1349 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1350 DAG.getConstant(0, NVT), ISD::SETNE);
1352 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1353 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1355 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1356 DAG.getNode(ISD::ADD, NVT, LoLZ,
1357 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1358 Hi = DAG.getConstant(0, NVT);
1361 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1362 SDValue &Lo, SDValue &Hi) {
1363 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1364 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1365 MVT NVT = Lo.getValueType();
1366 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1367 DAG.getNode(ISD::CTPOP, NVT, Hi));
1368 Hi = DAG.getConstant(0, NVT);
1371 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1372 SDValue &Lo, SDValue &Hi) {
1373 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1374 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1375 MVT NVT = Lo.getValueType();
1377 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1378 DAG.getConstant(0, NVT), ISD::SETNE);
1380 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1381 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1383 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1384 DAG.getNode(ISD::ADD, NVT, HiLZ,
1385 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1386 Hi = DAG.getConstant(0, NVT);
1389 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1391 MVT VT = N->getValueType(0);
1392 SDValue Op = N->getOperand(0);
1393 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1394 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1395 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1398 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1400 MVT VT = N->getValueType(0);
1401 SDValue Op = N->getOperand(0);
1402 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1403 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1404 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1407 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1408 SDValue &Lo, SDValue &Hi) {
1409 if (ISD::isNormalLoad(N)) {
1410 ExpandRes_NormalLoad(N, Lo, Hi);
1414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1416 MVT VT = N->getValueType(0);
1417 MVT NVT = TLI.getTypeToTransformTo(VT);
1418 SDValue Ch = N->getChain();
1419 SDValue Ptr = N->getBasePtr();
1420 ISD::LoadExtType ExtType = N->getExtensionType();
1421 int SVOffset = N->getSrcValueOffset();
1422 unsigned Alignment = N->getAlignment();
1423 bool isVolatile = N->isVolatile();
1425 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1427 if (N->getMemoryVT().bitsLE(NVT)) {
1428 MVT EVT = N->getMemoryVT();
1430 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1431 isVolatile, Alignment);
1433 // Remember the chain.
1434 Ch = Lo.getValue(1);
1436 if (ExtType == ISD::SEXTLOAD) {
1437 // The high part is obtained by SRA'ing all but one of the bits of the
1439 unsigned LoSize = Lo.getValueType().getSizeInBits();
1440 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1441 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1442 } else if (ExtType == ISD::ZEXTLOAD) {
1443 // The high part is just a zero.
1444 Hi = DAG.getConstant(0, NVT);
1446 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1447 // The high part is undefined.
1448 Hi = DAG.getNode(ISD::UNDEF, NVT);
1450 } else if (TLI.isLittleEndian()) {
1451 // Little-endian - low bits are at low addresses.
1452 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1453 isVolatile, Alignment);
1455 unsigned ExcessBits =
1456 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1457 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1459 // Increment the pointer to the other half.
1460 unsigned IncrementSize = NVT.getSizeInBits()/8;
1461 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1462 DAG.getIntPtrConstant(IncrementSize));
1463 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1464 SVOffset+IncrementSize, NEVT,
1465 isVolatile, MinAlign(Alignment, IncrementSize));
1467 // Build a factor node to remember that this load is independent of the
1469 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1472 // Big-endian - high bits are at low addresses. Favor aligned loads at
1473 // the cost of some bit-fiddling.
1474 MVT EVT = N->getMemoryVT();
1475 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1476 unsigned IncrementSize = NVT.getSizeInBits()/8;
1477 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1479 // Load both the high bits and maybe some of the low bits.
1480 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1481 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1482 isVolatile, Alignment);
1484 // Increment the pointer to the other half.
1485 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1486 DAG.getIntPtrConstant(IncrementSize));
1487 // Load the rest of the low bits.
1488 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1489 SVOffset+IncrementSize,
1490 MVT::getIntegerVT(ExcessBits),
1491 isVolatile, MinAlign(Alignment, IncrementSize));
1493 // Build a factor node to remember that this load is independent of the
1495 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1498 if (ExcessBits < NVT.getSizeInBits()) {
1499 // Transfer low bits from the bottom of Hi to the top of Lo.
1500 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1501 DAG.getNode(ISD::SHL, NVT, Hi,
1502 DAG.getConstant(ExcessBits,
1503 TLI.getShiftAmountTy())));
1504 // Move high bits to the right position in Hi.
1505 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1506 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1507 TLI.getShiftAmountTy()));
1511 // Legalized the chain result - switch anything that used the old chain to
1513 ReplaceValueWith(SDValue(N, 1), Ch);
1516 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1517 SDValue &Lo, SDValue &Hi) {
1518 SDValue LL, LH, RL, RH;
1519 GetExpandedInteger(N->getOperand(0), LL, LH);
1520 GetExpandedInteger(N->getOperand(1), RL, RH);
1521 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1522 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1525 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1526 SDValue &Lo, SDValue &Hi) {
1527 MVT VT = N->getValueType(0);
1528 MVT NVT = TLI.getTypeToTransformTo(VT);
1530 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1531 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1532 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1533 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1534 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1535 SDValue LL, LH, RL, RH;
1536 GetExpandedInteger(N->getOperand(0), LL, LH);
1537 GetExpandedInteger(N->getOperand(1), RL, RH);
1538 unsigned OuterBitSize = VT.getSizeInBits();
1539 unsigned InnerBitSize = NVT.getSizeInBits();
1540 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1541 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1543 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1544 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1545 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1546 // The inputs are both zero-extended.
1548 // We can emit a umul_lohi.
1549 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1550 Hi = SDValue(Lo.getNode(), 1);
1554 // We can emit a mulhu+mul.
1555 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1556 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1560 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1561 // The input values are both sign-extended.
1563 // We can emit a smul_lohi.
1564 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1565 Hi = SDValue(Lo.getNode(), 1);
1569 // We can emit a mulhs+mul.
1570 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1571 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1576 // Lo,Hi = umul LHS, RHS.
1577 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1578 DAG.getVTList(NVT, NVT), LL, RL);
1580 Hi = UMulLOHI.getValue(1);
1581 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1582 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1583 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1584 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1588 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1589 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1590 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1591 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1592 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1593 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1598 // If nothing else, we can make a libcall.
1599 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1601 LC = RTLIB::MUL_I32;
1602 else if (VT == MVT::i64)
1603 LC = RTLIB::MUL_I64;
1604 else if (VT == MVT::i128)
1605 LC = RTLIB::MUL_I128;
1606 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1608 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1609 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1612 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1613 SDValue &Lo, SDValue &Hi) {
1614 MVT VT = N->getValueType(0);
1616 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1618 LC = RTLIB::SDIV_I32;
1619 else if (VT == MVT::i64)
1620 LC = RTLIB::SDIV_I64;
1621 else if (VT == MVT::i128)
1622 LC = RTLIB::SDIV_I128;
1623 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1625 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1626 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1629 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1630 SDValue &Lo, SDValue &Hi) {
1631 MVT VT = N->getValueType(0);
1633 // If we can emit an efficient shift operation, do so now. Check to see if
1634 // the RHS is a constant.
1635 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1636 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1638 // If we can determine that the high bit of the shift is zero or one, even if
1639 // the low bits are variable, emit this shift in an optimized form.
1640 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1643 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1645 if (N->getOpcode() == ISD::SHL) {
1646 PartsOpc = ISD::SHL_PARTS;
1647 } else if (N->getOpcode() == ISD::SRL) {
1648 PartsOpc = ISD::SRL_PARTS;
1650 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1651 PartsOpc = ISD::SRA_PARTS;
1654 // Next check to see if the target supports this SHL_PARTS operation or if it
1655 // will custom expand it.
1656 MVT NVT = TLI.getTypeToTransformTo(VT);
1657 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1658 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1659 Action == TargetLowering::Custom) {
1660 // Expand the subcomponents.
1662 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1664 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1665 MVT VT = LHSL.getValueType();
1666 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1667 Hi = Lo.getValue(1);
1671 // Otherwise, emit a libcall.
1672 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1674 if (N->getOpcode() == ISD::SHL) {
1675 isSigned = false; /*sign irrelevant*/
1677 LC = RTLIB::SHL_I32;
1678 else if (VT == MVT::i64)
1679 LC = RTLIB::SHL_I64;
1680 else if (VT == MVT::i128)
1681 LC = RTLIB::SHL_I128;
1682 } else if (N->getOpcode() == ISD::SRL) {
1685 LC = RTLIB::SRL_I32;
1686 else if (VT == MVT::i64)
1687 LC = RTLIB::SRL_I64;
1688 else if (VT == MVT::i128)
1689 LC = RTLIB::SRL_I128;
1691 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1694 LC = RTLIB::SRA_I32;
1695 else if (VT == MVT::i64)
1696 LC = RTLIB::SRA_I64;
1697 else if (VT == MVT::i128)
1698 LC = RTLIB::SRA_I128;
1700 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1702 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1703 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1706 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1707 SDValue &Lo, SDValue &Hi) {
1708 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1709 SDValue Op = N->getOperand(0);
1710 if (Op.getValueType().bitsLE(NVT)) {
1711 // The low part is sign extension of the input (degenerates to a copy).
1712 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1713 // The high part is obtained by SRA'ing all but one of the bits of low part.
1714 unsigned LoSize = NVT.getSizeInBits();
1715 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1716 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1718 // For example, extension of an i48 to an i64. The operand type necessarily
1719 // promotes to the result type, so will end up being expanded too.
1720 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1721 "Only know how to promote this result!");
1722 SDValue Res = GetPromotedInteger(Op);
1723 assert(Res.getValueType() == N->getValueType(0) &&
1724 "Operand over promoted?");
1725 // Split the promoted operand. This will simplify when it is expanded.
1726 SplitInteger(Res, Lo, Hi);
1727 unsigned ExcessBits =
1728 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1729 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1730 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1734 void DAGTypeLegalizer::
1735 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1736 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1737 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1739 if (EVT.bitsLE(Lo.getValueType())) {
1740 // sext_inreg the low part if needed.
1741 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1744 // The high part gets the sign extension from the lo-part. This handles
1745 // things like sextinreg V:i64 from i8.
1746 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1747 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1748 TLI.getShiftAmountTy()));
1750 // For example, extension of an i48 to an i64. Leave the low part alone,
1751 // sext_inreg the high part.
1752 unsigned ExcessBits =
1753 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1754 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1755 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1759 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1760 SDValue &Lo, SDValue &Hi) {
1761 MVT VT = N->getValueType(0);
1763 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1765 LC = RTLIB::SREM_I32;
1766 else if (VT == MVT::i64)
1767 LC = RTLIB::SREM_I64;
1768 else if (VT == MVT::i128)
1769 LC = RTLIB::SREM_I128;
1770 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1772 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1773 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1776 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1777 SDValue &Lo, SDValue &Hi) {
1778 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1779 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1780 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1781 DAG.getConstant(NVT.getSizeInBits(),
1782 TLI.getShiftAmountTy()));
1783 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1786 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1787 SDValue &Lo, SDValue &Hi) {
1788 MVT VT = N->getValueType(0);
1790 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1792 LC = RTLIB::UDIV_I32;
1793 else if (VT == MVT::i64)
1794 LC = RTLIB::UDIV_I64;
1795 else if (VT == MVT::i128)
1796 LC = RTLIB::UDIV_I128;
1797 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1799 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1800 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1803 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1804 SDValue &Lo, SDValue &Hi) {
1805 MVT VT = N->getValueType(0);
1807 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1809 LC = RTLIB::UREM_I32;
1810 else if (VT == MVT::i64)
1811 LC = RTLIB::UREM_I64;
1812 else if (VT == MVT::i128)
1813 LC = RTLIB::UREM_I128;
1814 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1816 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1817 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1820 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1821 SDValue &Lo, SDValue &Hi) {
1822 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1823 SDValue Op = N->getOperand(0);
1824 if (Op.getValueType().bitsLE(NVT)) {
1825 // The low part is zero extension of the input (degenerates to a copy).
1826 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1827 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1829 // For example, extension of an i48 to an i64. The operand type necessarily
1830 // promotes to the result type, so will end up being expanded too.
1831 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1832 "Only know how to promote this result!");
1833 SDValue Res = GetPromotedInteger(Op);
1834 assert(Res.getValueType() == N->getValueType(0) &&
1835 "Operand over promoted?");
1836 // Split the promoted operand. This will simplify when it is expanded.
1837 SplitInteger(Res, Lo, Hi);
1838 unsigned ExcessBits =
1839 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1840 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1845 //===----------------------------------------------------------------------===//
1846 // Integer Operand Expansion
1847 //===----------------------------------------------------------------------===//
1849 /// ExpandIntegerOperand - This method is called when the specified operand of
1850 /// the specified node is found to need expansion. At this point, all of the
1851 /// result types of the node are known to be legal, but other operands of the
1852 /// node may need promotion or expansion as well as the specified one.
1853 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1854 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1855 SDValue Res = SDValue();
1857 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1858 == TargetLowering::Custom)
1859 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
1861 if (Res.getNode() == 0) {
1862 switch (N->getOpcode()) {
1865 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1866 N->dump(&DAG); cerr << "\n";
1868 assert(0 && "Do not know how to expand this operator's operand!");
1871 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1872 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1873 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1875 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1876 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1877 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1878 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1879 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1881 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1882 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1886 // If the result is null, the sub-method took care of registering results etc.
1887 if (!Res.getNode()) return false;
1888 // If the result is N, the sub-method updated N in place. Check to see if any
1889 // operands are new, and if so, mark them.
1890 if (Res.getNode() == N) {
1891 // Mark N as new and remark N and its operands. This allows us to correctly
1892 // revisit N if it needs another step of expansion and allows us to visit
1893 // any new operands to N.
1898 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1899 "Invalid operand expansion");
1901 ReplaceValueWith(SDValue(N, 0), Res);
1905 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1906 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1907 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1909 ISD::CondCode &CCCode) {
1910 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1911 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1912 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1914 MVT VT = NewLHS.getValueType();
1916 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1917 if (RHSLo == RHSHi) {
1918 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1919 if (RHSCST->isAllOnesValue()) {
1920 // Equality comparison to -1.
1921 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1928 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1929 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1930 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1931 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1935 // If this is a comparison of the sign bit, just look at the top part.
1937 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1938 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1939 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1945 // FIXME: This generated code sucks.
1946 ISD::CondCode LowCC;
1948 default: assert(0 && "Unknown integer setcc!");
1950 case ISD::SETULT: LowCC = ISD::SETULT; break;
1952 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1954 case ISD::SETULE: LowCC = ISD::SETULE; break;
1956 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1959 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1960 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1961 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1963 // NOTE: on targets without efficient SELECT of bools, we can always use
1964 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1965 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1967 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1968 false, DagCombineInfo);
1969 if (!Tmp1.getNode())
1970 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1971 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1972 CCCode, false, DagCombineInfo);
1973 if (!Tmp2.getNode())
1974 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1975 DAG.getCondCode(CCCode));
1977 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
1978 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
1979 if ((Tmp1C && Tmp1C->isNullValue()) ||
1980 (Tmp2C && Tmp2C->isNullValue() &&
1981 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1982 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1983 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1984 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1985 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1986 // low part is known false, returns high part.
1987 // For LE / GE, if high part is known false, ignore the low part.
1988 // For LT / GT, if high part is known true, ignore the low part.
1994 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1995 ISD::SETEQ, false, DagCombineInfo);
1996 if (!NewLHS.getNode())
1997 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1999 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2000 NewLHS, Tmp1, Tmp2);
2004 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2005 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2006 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2007 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2009 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2010 // against zero to select between true and false values.
2011 if (NewRHS.getNode() == 0) {
2012 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2013 CCCode = ISD::SETNE;
2016 // Update N to have the operands specified.
2017 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2018 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2022 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2023 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2024 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2025 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2027 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2028 // against zero to select between true and false values.
2029 if (NewRHS.getNode() == 0) {
2030 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2031 CCCode = ISD::SETNE;
2034 // Update N to have the operands specified.
2035 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2036 N->getOperand(2), N->getOperand(3),
2037 DAG.getCondCode(CCCode));
2040 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2041 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2042 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2043 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2045 // If ExpandSetCCOperands returned a scalar, use it.
2046 if (NewRHS.getNode() == 0) {
2047 assert(NewLHS.getValueType() == N->getValueType(0) &&
2048 "Unexpected setcc expansion!");
2052 // Otherwise, update N to have the operands specified.
2053 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2054 DAG.getCondCode(CCCode));
2057 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2058 SDValue Op = N->getOperand(0);
2059 MVT DstVT = N->getValueType(0);
2060 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2061 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2062 "Don't know how to expand this SINT_TO_FP!");
2063 return MakeLibCall(LC, DstVT, &Op, 1, true);
2066 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2067 if (ISD::isNormalStore(N))
2068 return ExpandOp_NormalStore(N, OpNo);
2070 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2071 assert(OpNo == 1 && "Can only expand the stored value so far");
2073 MVT VT = N->getOperand(1).getValueType();
2074 MVT NVT = TLI.getTypeToTransformTo(VT);
2075 SDValue Ch = N->getChain();
2076 SDValue Ptr = N->getBasePtr();
2077 int SVOffset = N->getSrcValueOffset();
2078 unsigned Alignment = N->getAlignment();
2079 bool isVolatile = N->isVolatile();
2082 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2084 if (N->getMemoryVT().bitsLE(NVT)) {
2085 GetExpandedInteger(N->getValue(), Lo, Hi);
2086 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2087 N->getMemoryVT(), isVolatile, Alignment);
2088 } else if (TLI.isLittleEndian()) {
2089 // Little-endian - low bits are at low addresses.
2090 GetExpandedInteger(N->getValue(), Lo, Hi);
2092 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2093 isVolatile, Alignment);
2095 unsigned ExcessBits =
2096 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2097 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2099 // Increment the pointer to the other half.
2100 unsigned IncrementSize = NVT.getSizeInBits()/8;
2101 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2102 DAG.getIntPtrConstant(IncrementSize));
2103 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2104 SVOffset+IncrementSize, NEVT,
2105 isVolatile, MinAlign(Alignment, IncrementSize));
2106 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2108 // Big-endian - high bits are at low addresses. Favor aligned stores at
2109 // the cost of some bit-fiddling.
2110 GetExpandedInteger(N->getValue(), Lo, Hi);
2112 MVT EVT = N->getMemoryVT();
2113 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2114 unsigned IncrementSize = NVT.getSizeInBits()/8;
2115 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2116 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2118 if (ExcessBits < NVT.getSizeInBits()) {
2119 // Transfer high bits from the top of Lo to the bottom of Hi.
2120 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2121 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2122 TLI.getShiftAmountTy()));
2123 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2124 DAG.getNode(ISD::SRL, NVT, Lo,
2125 DAG.getConstant(ExcessBits,
2126 TLI.getShiftAmountTy())));
2129 // Store both the high bits and maybe some of the low bits.
2130 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2131 SVOffset, HiVT, isVolatile, Alignment);
2133 // Increment the pointer to the other half.
2134 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2135 DAG.getIntPtrConstant(IncrementSize));
2136 // Store the lowest ExcessBits bits in the second half.
2137 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2138 SVOffset+IncrementSize,
2139 MVT::getIntegerVT(ExcessBits),
2140 isVolatile, MinAlign(Alignment, IncrementSize));
2141 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2145 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2147 GetExpandedInteger(N->getOperand(0), InL, InH);
2148 // Just truncate the low part of the source.
2149 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2152 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2153 SDValue Op = N->getOperand(0);
2154 MVT SrcVT = Op.getValueType();
2155 MVT DstVT = N->getValueType(0);
2157 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2158 // Do a signed conversion then adjust the result.
2159 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2160 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2162 // The result of the signed conversion needs adjusting if the 'sign bit' of
2163 // the incoming integer was set. To handle this, we dynamically test to see
2164 // if it is set, and, if so, add a fudge factor.
2166 const uint64_t F32TwoE32 = 0x4F800000ULL;
2167 const uint64_t F32TwoE64 = 0x5F800000ULL;
2168 const uint64_t F32TwoE128 = 0x7F800000ULL;
2171 if (SrcVT == MVT::i32)
2172 FF = APInt(32, F32TwoE32);
2173 else if (SrcVT == MVT::i64)
2174 FF = APInt(32, F32TwoE64);
2175 else if (SrcVT == MVT::i128)
2176 FF = APInt(32, F32TwoE128);
2178 assert(false && "Unsupported UINT_TO_FP!");
2180 // Check whether the sign bit is set.
2182 GetExpandedInteger(Op, Lo, Hi);
2183 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2184 DAG.getConstant(0, Hi.getValueType()),
2187 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2188 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2189 TLI.getPointerTy());
2191 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2192 SDValue Zero = DAG.getIntPtrConstant(0);
2193 SDValue Four = DAG.getIntPtrConstant(4);
2194 if (TLI.isBigEndian()) std::swap(Zero, Four);
2195 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2197 unsigned Alignment =
2198 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2199 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2200 Alignment = std::min(Alignment, 4u);
2202 // Load the value out, extending it from f32 to the destination float type.
2203 // FIXME: Avoid the extend by constructing the right constant pool?
2204 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2205 FudgePtr, NULL, 0, MVT::f32,
2207 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2210 // Otherwise, use a libcall.
2211 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2212 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2213 "Don't know how to expand this UINT_TO_FP!");
2214 return MakeLibCall(LC, DstVT, &Op, 1, true);