1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerNode(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
215 CreateStackStoreLoad(InOp, OutVT));
218 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
219 SDValue Op = GetPromotedInteger(N->getOperand(0));
220 MVT OVT = N->getValueType(0);
221 MVT NVT = Op.getValueType();
222 DebugLoc dl = N->getDebugLoc();
224 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
225 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
226 DAG.getConstant(DiffBits, TLI.getPointerTy()));
229 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
230 // The pair element type may be legal, or may not promote to the same type as
231 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
232 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
233 TLI.getTypeToTransformTo(N->getValueType(0)),
234 JoinIntegers(N->getOperand(0), N->getOperand(1)));
237 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
238 MVT VT = N->getValueType(0);
239 // FIXME there is no actual debug info here
240 DebugLoc dl = N->getDebugLoc();
241 // Zero extend things like i1, sign extend everything else. It shouldn't
242 // matter in theory which one we pick, but this tends to give better code?
243 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
244 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
246 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
250 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
251 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
252 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
253 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
254 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
255 "can only promote integers");
256 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
257 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
258 N->getOperand(1), N->getOperand(2),
259 N->getOperand(3), N->getOperand(4), CvtCode);
262 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
263 // Zero extend to the promoted type and do the count there.
264 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
265 DebugLoc dl = N->getDebugLoc();
266 MVT OVT = N->getValueType(0);
267 MVT NVT = Op.getValueType();
268 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
269 // Subtract off the extra leading bits in the bigger type.
270 return DAG.getNode(ISD::SUB, dl, NVT, Op,
271 DAG.getConstant(NVT.getSizeInBits() -
272 OVT.getSizeInBits(), NVT));
275 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
276 // Zero extend to the promoted type and do the count there.
277 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
278 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
281 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
282 SDValue Op = GetPromotedInteger(N->getOperand(0));
283 MVT OVT = N->getValueType(0);
284 MVT NVT = Op.getValueType();
285 DebugLoc dl = N->getDebugLoc();
286 // The count is the same in the promoted type except if the original
287 // value was zero. This can be handled by setting the bit just off
288 // the top of the original type.
289 APInt TopBit(NVT.getSizeInBits(), 0);
290 TopBit.set(OVT.getSizeInBits());
291 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
292 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
295 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
296 DebugLoc dl = N->getDebugLoc();
297 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
298 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
302 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
303 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
304 unsigned NewOpc = N->getOpcode();
305 DebugLoc dl = N->getDebugLoc();
307 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
308 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
309 // and SINT conversions are Custom, there is no way to tell which is preferable.
310 // We choose SINT because that's the right thing on PPC.)
311 if (N->getOpcode() == ISD::FP_TO_UINT &&
312 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
313 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
314 NewOpc = ISD::FP_TO_SINT;
316 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
318 // Assert that the converted value fits in the original type. If it doesn't
319 // (eg: because the value being converted is too big), then the result of the
320 // original operation was undefined anyway, so the assert is still correct.
321 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
322 ISD::AssertZext : ISD::AssertSext, dl,
323 NVT, Res, DAG.getValueType(N->getValueType(0)));
326 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
327 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
328 DebugLoc dl = N->getDebugLoc();
330 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
331 SDValue Res = GetPromotedInteger(N->getOperand(0));
332 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
334 // If the result and operand types are the same after promotion, simplify
335 // to an in-register extension.
336 if (NVT == Res.getValueType()) {
337 // The high bits are not guaranteed to be anything. Insert an extend.
338 if (N->getOpcode() == ISD::SIGN_EXTEND)
339 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
340 DAG.getValueType(N->getOperand(0).getValueType()));
341 if (N->getOpcode() == ISD::ZERO_EXTEND)
342 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
343 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
348 // Otherwise, just extend the original operand all the way to the larger type.
349 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
352 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
353 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
354 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
355 ISD::LoadExtType ExtType =
356 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
357 DebugLoc dl = N->getDebugLoc();
358 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
359 N->getSrcValue(), N->getSrcValueOffset(),
360 N->getMemoryVT(), N->isVolatile(),
363 // Legalized the chain result - switch anything that used the old chain to
365 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
369 /// Promote the overflow flag of an overflowing arithmetic node.
370 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
371 // Simply change the return type of the boolean result.
372 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
373 MVT ValueVTs[] = { N->getValueType(0), NVT };
374 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
375 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
376 DAG.getVTList(ValueVTs, 2), Ops, 2);
378 // Modified the sum result - switch anything that used the old sum to use
380 ReplaceValueWith(SDValue(N, 0), Res);
382 return SDValue(Res.getNode(), 1);
385 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
387 return PromoteIntRes_Overflow(N);
389 // The operation overflowed iff the result in the larger type is not the
390 // sign extension of its truncation to the original type.
391 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
392 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
393 MVT OVT = N->getOperand(0).getValueType();
394 MVT NVT = LHS.getValueType();
395 DebugLoc dl = N->getDebugLoc();
397 // Do the arithmetic in the larger type.
398 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
399 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
401 // Calculate the overflow flag: sign extend the arithmetic result from
402 // the original type.
403 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
404 DAG.getValueType(OVT));
405 // Overflowed if and only if this is not equal to Res.
406 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
408 // Use the calculated overflow everywhere.
409 ReplaceValueWith(SDValue(N, 1), Ofl);
414 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
415 // Sign extend the input.
416 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
417 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
418 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
419 LHS.getValueType(), LHS, RHS);
422 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
423 SDValue LHS = GetPromotedInteger(N->getOperand(1));
424 SDValue RHS = GetPromotedInteger(N->getOperand(2));
425 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
426 LHS.getValueType(), N->getOperand(0),LHS,RHS);
429 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
430 SDValue LHS = GetPromotedInteger(N->getOperand(2));
431 SDValue RHS = GetPromotedInteger(N->getOperand(3));
432 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
433 LHS.getValueType(), N->getOperand(0),
434 N->getOperand(1), LHS, RHS, N->getOperand(4));
437 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
438 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
439 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
440 DebugLoc dl = N->getDebugLoc();
442 // Get the SETCC result using the canonical SETCC type.
443 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
444 N->getOperand(1), N->getOperand(2));
446 // Convert to the expected type.
447 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
448 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
449 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
452 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
453 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
454 TLI.getTypeToTransformTo(N->getValueType(0)),
455 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
458 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
459 SDValue Op = GetPromotedInteger(N->getOperand(0));
460 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
461 Op.getValueType(), Op, N->getOperand(1));
464 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
465 // The input may have strange things in the top bits of the registers, but
466 // these operations don't care. They may have weird bits going out, but
467 // that too is okay if they are integer operations.
468 SDValue LHS = GetPromotedInteger(N->getOperand(0));
469 SDValue RHS = GetPromotedInteger(N->getOperand(1));
470 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
471 LHS.getValueType(), LHS, RHS);
474 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
475 // The input value must be properly sign extended.
476 SDValue Res = SExtPromotedInteger(N->getOperand(0));
477 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
478 Res.getValueType(), Res, N->getOperand(1));
481 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
482 // The input value must be properly zero extended.
483 MVT VT = N->getValueType(0);
484 MVT NVT = TLI.getTypeToTransformTo(VT);
485 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
486 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
489 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
490 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
493 switch (getTypeAction(N->getOperand(0).getValueType())) {
494 default: assert(0 && "Unknown type action!");
497 Res = N->getOperand(0);
500 Res = GetPromotedInteger(N->getOperand(0));
504 // Truncate to NVT instead of VT
505 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
508 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
510 return PromoteIntRes_Overflow(N);
512 // The operation overflowed iff the result in the larger type is not the
513 // zero extension of its truncation to the original type.
514 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
515 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
516 MVT OVT = N->getOperand(0).getValueType();
517 MVT NVT = LHS.getValueType();
518 DebugLoc dl = N->getDebugLoc();
520 // Do the arithmetic in the larger type.
521 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
522 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
524 // Calculate the overflow flag: zero extend the arithmetic result from
525 // the original type.
526 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
527 // Overflowed if and only if this is not equal to Res.
528 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
530 // Use the calculated overflow everywhere.
531 ReplaceValueWith(SDValue(N, 1), Ofl);
536 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
537 // Zero extend the input.
538 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
539 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
540 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
541 LHS.getValueType(), LHS, RHS);
544 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
545 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
548 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
549 SDValue Chain = N->getOperand(0); // Get the chain.
550 SDValue Ptr = N->getOperand(1); // Get the pointer.
551 MVT VT = N->getValueType(0);
552 DebugLoc dl = N->getDebugLoc();
554 MVT RegVT = TLI.getRegisterType(VT);
555 unsigned NumRegs = TLI.getNumRegisters(VT);
556 // The argument is passed as NumRegs registers of type RegVT.
558 SmallVector<SDValue, 8> Parts(NumRegs);
559 for (unsigned i = 0; i < NumRegs; ++i) {
560 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
561 Chain = Parts[i].getValue(1);
564 // Handle endianness of the load.
565 if (TLI.isBigEndian())
566 std::reverse(Parts.begin(), Parts.end());
568 // Assemble the parts in the promoted type.
569 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
570 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
571 for (unsigned i = 1; i < NumRegs; ++i) {
572 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
573 // Shift it to the right position and "or" it in.
574 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
575 DAG.getConstant(i * RegVT.getSizeInBits(),
576 TLI.getPointerTy()));
577 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
580 // Modified the chain result - switch anything that used the old chain to
582 ReplaceValueWith(SDValue(N, 1), Chain);
587 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
588 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
589 return PromoteIntRes_Overflow(N);
592 //===----------------------------------------------------------------------===//
593 // Integer Operand Promotion
594 //===----------------------------------------------------------------------===//
596 /// PromoteIntegerOperand - This method is called when the specified operand of
597 /// the specified node is found to need promotion. At this point, all of the
598 /// result types of the node are known to be legal, but other operands of the
599 /// node may need promotion or expansion as well as the specified one.
600 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
601 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
602 SDValue Res = SDValue();
604 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
607 switch (N->getOpcode()) {
610 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
611 N->dump(&DAG); cerr << "\n";
613 assert(0 && "Do not know how to promote this operator's operand!");
616 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
617 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
618 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
619 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
620 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
621 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
622 case ISD::CONVERT_RNDSAT:
623 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
624 case ISD::INSERT_VECTOR_ELT:
625 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
626 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
627 case ISD::SCALAR_TO_VECTOR:
628 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
629 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
630 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
631 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
632 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
633 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
634 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
636 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
637 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
638 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
644 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
647 // If the result is null, the sub-method took care of registering results etc.
648 if (!Res.getNode()) return false;
650 // If the result is N, the sub-method updated N in place. Tell the legalizer
652 if (Res.getNode() == N)
655 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
656 "Invalid operand expansion");
658 ReplaceValueWith(SDValue(N, 0), Res);
662 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
663 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
664 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
665 ISD::CondCode CCCode) {
666 // We have to insert explicit sign or zero extends. Note that we could
667 // insert sign extends for ALL conditions, but zero extend is cheaper on
668 // many machines (an AND instead of two shifts), so prefer it.
670 default: assert(0 && "Unknown integer comparison!");
677 // ALL of these operations will work if we either sign or zero extend
678 // the operands (including the unsigned comparisons!). Zero extend is
679 // usually a simpler/cheaper operation, so prefer it.
680 NewLHS = ZExtPromotedInteger(NewLHS);
681 NewRHS = ZExtPromotedInteger(NewRHS);
687 NewLHS = SExtPromotedInteger(NewLHS);
688 NewRHS = SExtPromotedInteger(NewRHS);
693 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
694 SDValue Op = GetPromotedInteger(N->getOperand(0));
695 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
698 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
699 // This should only occur in unusual situations like bitcasting to an
700 // x86_fp80, so just turn it into a store+load
701 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
704 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
705 assert(OpNo == 2 && "Don't know how to promote this operand!");
707 SDValue LHS = N->getOperand(2);
708 SDValue RHS = N->getOperand(3);
709 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
711 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
713 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
714 N->getOperand(1), LHS, RHS, N->getOperand(4));
717 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
718 assert(OpNo == 1 && "only know how to promote condition");
720 // Promote all the way up to the canonical SetCC type.
721 MVT SVT = TLI.getSetCCResultType(MVT::Other);
722 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
724 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
725 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
729 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
730 // Since the result type is legal, the operands must promote to it.
731 MVT OVT = N->getOperand(0).getValueType();
732 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
733 SDValue Hi = GetPromotedInteger(N->getOperand(1));
734 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
735 DebugLoc dl = N->getDebugLoc();
737 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
738 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
739 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
742 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
743 // The vector type is legal but the element type is not. This implies
744 // that the vector is a power-of-two in length and that the element
745 // type does not have a strange size (eg: it is not i1).
746 MVT VecVT = N->getValueType(0);
747 unsigned NumElts = VecVT.getVectorNumElements();
748 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
750 // Promote the inserted value. The type does not need to match the
751 // vector element type. Check that any extra bits introduced will be
753 assert(N->getOperand(0).getValueType().getSizeInBits() >=
754 N->getValueType(0).getVectorElementType().getSizeInBits() &&
755 "Type of inserted value narrower than vector element type!");
757 SmallVector<SDValue, 16> NewOps;
758 for (unsigned i = 0; i < NumElts; ++i)
759 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
761 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
764 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
765 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
766 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
767 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
768 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
769 "can only promote integer arguments");
770 SDValue InOp = GetPromotedInteger(N->getOperand(0));
771 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
772 N->getOperand(1), N->getOperand(2),
773 N->getOperand(3), N->getOperand(4), CvtCode);
776 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
779 // Promote the inserted value. This is valid because the type does not
780 // have to match the vector element type.
782 // Check that any extra bits introduced will be truncated away.
783 assert(N->getOperand(1).getValueType().getSizeInBits() >=
784 N->getValueType(0).getVectorElementType().getSizeInBits() &&
785 "Type of inserted value narrower than vector element type!");
786 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
787 GetPromotedInteger(N->getOperand(1)),
791 assert(OpNo == 2 && "Different operand and result vector types?");
793 // Promote the index.
794 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
795 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
796 N->getOperand(1), Idx);
799 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
801 DebugLoc dl = N->getDebugLoc();
802 NewOps[0] = N->getOperand(0);
803 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
804 SDValue Flag = GetPromotedInteger(N->getOperand(i));
805 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
807 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
808 array_lengthof(NewOps));
811 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
812 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
813 // the operand in place.
814 return DAG.UpdateNodeOperands(SDValue(N, 0),
815 GetPromotedInteger(N->getOperand(0)));
818 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
819 assert(OpNo == 0 && "Only know how to promote condition");
821 // Promote all the way up to the canonical SetCC type.
822 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
823 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
825 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
826 N->getOperand(1), N->getOperand(2));
829 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
830 assert(OpNo == 0 && "Don't know how to promote this operand!");
832 SDValue LHS = N->getOperand(0);
833 SDValue RHS = N->getOperand(1);
834 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
836 // The CC (#4) and the possible return values (#2 and #3) have legal types.
837 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
838 N->getOperand(3), N->getOperand(4));
841 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
842 assert(OpNo == 0 && "Don't know how to promote this operand!");
844 SDValue LHS = N->getOperand(0);
845 SDValue RHS = N->getOperand(1);
846 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
848 // The CC (#2) is always legal.
849 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
852 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
853 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
854 ZExtPromotedInteger(N->getOperand(1)));
857 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
858 SDValue Op = GetPromotedInteger(N->getOperand(0));
859 DebugLoc dl = N->getDebugLoc();
860 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
861 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
862 Op, DAG.getValueType(N->getOperand(0).getValueType()));
865 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
866 return DAG.UpdateNodeOperands(SDValue(N, 0),
867 SExtPromotedInteger(N->getOperand(0)));
870 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
871 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
872 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
873 int SVOffset = N->getSrcValueOffset();
874 unsigned Alignment = N->getAlignment();
875 bool isVolatile = N->isVolatile();
876 DebugLoc dl = N->getDebugLoc();
878 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
880 // Truncate the value and store the result.
881 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
882 SVOffset, N->getMemoryVT(),
883 isVolatile, Alignment);
886 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
887 SDValue Op = GetPromotedInteger(N->getOperand(0));
888 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
891 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
892 return DAG.UpdateNodeOperands(SDValue(N, 0),
893 ZExtPromotedInteger(N->getOperand(0)));
896 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
897 DebugLoc dl = N->getDebugLoc();
898 SDValue Op = GetPromotedInteger(N->getOperand(0));
899 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
900 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
904 //===----------------------------------------------------------------------===//
905 // Integer Result Expansion
906 //===----------------------------------------------------------------------===//
908 /// ExpandIntegerResult - This method is called when the specified result of the
909 /// specified node is found to need expansion. At this point, the node may also
910 /// have invalid operands or may have other results that need promotion, we just
911 /// know that (at least) one result needs expansion.
912 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
913 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
917 // See if the target wants to custom expand this node.
918 if (CustomLowerNode(N, N->getValueType(ResNo), true))
921 switch (N->getOpcode()) {
924 cerr << "ExpandIntegerResult #" << ResNo << ": ";
925 N->dump(&DAG); cerr << "\n";
927 assert(0 && "Do not know how to expand the result of this operator!");
930 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
931 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
932 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
933 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
935 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
936 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
937 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
938 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
939 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
941 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
942 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
943 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
944 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
945 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
946 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
947 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
948 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
949 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
950 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
951 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
952 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
953 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
954 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
955 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
956 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
957 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
958 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
959 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
960 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
964 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
967 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
970 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
973 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
977 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
980 // If Lo/Hi is null, the sub-method took care of registering results etc.
982 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
985 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
986 /// and the shift amount is a constant 'Amt'. Expand the operation.
987 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
988 SDValue &Lo, SDValue &Hi) {
989 DebugLoc dl = N->getDebugLoc();
990 // Expand the incoming operand to be shifted, so that we have its parts
992 GetExpandedInteger(N->getOperand(0), InL, InH);
994 MVT NVT = InL.getValueType();
995 unsigned VTBits = N->getValueType(0).getSizeInBits();
996 unsigned NVTBits = NVT.getSizeInBits();
997 MVT ShTy = N->getOperand(1).getValueType();
999 if (N->getOpcode() == ISD::SHL) {
1001 Lo = Hi = DAG.getConstant(0, NVT);
1002 } else if (Amt > NVTBits) {
1003 Lo = DAG.getConstant(0, NVT);
1004 Hi = DAG.getNode(ISD::SHL, dl,
1005 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1006 } else if (Amt == NVTBits) {
1007 Lo = DAG.getConstant(0, NVT);
1009 } else if (Amt == 1 &&
1010 TLI.isOperationLegalOrCustom(ISD::ADDC,
1011 TLI.getTypeToExpandTo(NVT))) {
1012 // Emit this X << 1 as X+X.
1013 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1014 SDValue LoOps[2] = { InL, InL };
1015 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1016 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1017 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1019 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1020 Hi = DAG.getNode(ISD::OR, dl, NVT,
1021 DAG.getNode(ISD::SHL, dl, NVT, InH,
1022 DAG.getConstant(Amt, ShTy)),
1023 DAG.getNode(ISD::SRL, dl, NVT, InL,
1024 DAG.getConstant(NVTBits-Amt, ShTy)));
1029 if (N->getOpcode() == ISD::SRL) {
1031 Lo = DAG.getConstant(0, NVT);
1032 Hi = DAG.getConstant(0, NVT);
1033 } else if (Amt > NVTBits) {
1034 Lo = DAG.getNode(ISD::SRL, dl,
1035 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1036 Hi = DAG.getConstant(0, NVT);
1037 } else if (Amt == NVTBits) {
1039 Hi = DAG.getConstant(0, NVT);
1041 Lo = DAG.getNode(ISD::OR, dl, NVT,
1042 DAG.getNode(ISD::SRL, dl, NVT, InL,
1043 DAG.getConstant(Amt, ShTy)),
1044 DAG.getNode(ISD::SHL, dl, NVT, InH,
1045 DAG.getConstant(NVTBits-Amt, ShTy)));
1046 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1051 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1053 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1054 DAG.getConstant(NVTBits-1, ShTy));
1055 } else if (Amt > NVTBits) {
1056 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1057 DAG.getConstant(Amt-NVTBits, ShTy));
1058 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1059 DAG.getConstant(NVTBits-1, ShTy));
1060 } else if (Amt == NVTBits) {
1062 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1063 DAG.getConstant(NVTBits-1, ShTy));
1065 Lo = DAG.getNode(ISD::OR, dl, NVT,
1066 DAG.getNode(ISD::SRL, dl, NVT, InL,
1067 DAG.getConstant(Amt, ShTy)),
1068 DAG.getNode(ISD::SHL, dl, NVT, InH,
1069 DAG.getConstant(NVTBits-Amt, ShTy)));
1070 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1074 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1075 /// this shift based on knowledge of the high bit of the shift amount. If we
1076 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1078 bool DAGTypeLegalizer::
1079 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1080 SDValue Amt = N->getOperand(1);
1081 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1082 MVT ShTy = Amt.getValueType();
1083 unsigned ShBits = ShTy.getSizeInBits();
1084 unsigned NVTBits = NVT.getSizeInBits();
1085 assert(isPowerOf2_32(NVTBits) &&
1086 "Expanded integer type size not a power of two!");
1087 DebugLoc dl = N->getDebugLoc();
1089 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1090 APInt KnownZero, KnownOne;
1091 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1093 // If we don't know anything about the high bits, exit.
1094 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1097 // Get the incoming operand to be shifted.
1099 GetExpandedInteger(N->getOperand(0), InL, InH);
1101 // If we know that any of the high bits of the shift amount are one, then we
1102 // can do this as a couple of simple shifts.
1103 if (KnownOne.intersects(HighBitMask)) {
1104 // Mask out the high bit, which we know is set.
1105 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1106 DAG.getConstant(~HighBitMask, ShTy));
1108 switch (N->getOpcode()) {
1109 default: assert(0 && "Unknown shift");
1111 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1112 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1115 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1116 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1119 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1120 DAG.getConstant(NVTBits-1, ShTy));
1121 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1127 // FIXME: This code is broken for shifts with a zero amount!
1128 // If we know that all of the high bits of the shift amount are zero, then we
1129 // can do this as a couple of simple shifts.
1130 if ((KnownZero & HighBitMask) == HighBitMask) {
1132 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1133 DAG.getConstant(NVTBits, ShTy),
1136 switch (N->getOpcode()) {
1137 default: assert(0 && "Unknown shift");
1138 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1140 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1143 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1144 Hi = DAG.getNode(ISD::OR, NVT,
1145 DAG.getNode(Op1, NVT, InH, Amt),
1146 DAG.getNode(Op2, NVT, InL, Amt2));
1154 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1156 bool DAGTypeLegalizer::
1157 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1158 SDValue Amt = N->getOperand(1);
1159 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1160 MVT ShTy = Amt.getValueType();
1161 unsigned NVTBits = NVT.getSizeInBits();
1162 assert(isPowerOf2_32(NVTBits) &&
1163 "Expanded integer type size not a power of two!");
1164 DebugLoc dl = N->getDebugLoc();
1166 // Get the incoming operand to be shifted.
1168 GetExpandedInteger(N->getOperand(0), InL, InH);
1170 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1171 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1172 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1173 Amt, NVBitsNode, ISD::SETULT);
1175 SDValue Lo1, Hi1, Lo2, Hi2;
1176 switch (N->getOpcode()) {
1177 default: assert(0 && "Unknown shift");
1180 Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
1181 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1184 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1185 Hi2 = DAG.getNode(ISD::OR, dl, NVT,
1186 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1187 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
1189 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1190 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1194 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
1195 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1198 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1199 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1200 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1201 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1203 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1204 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1208 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1209 DAG.getConstant(NVTBits-1, ShTy));
1210 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1213 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1214 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1215 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1216 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1218 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1219 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1226 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1227 SDValue &Lo, SDValue &Hi) {
1228 DebugLoc dl = N->getDebugLoc();
1229 // Expand the subcomponents.
1230 SDValue LHSL, LHSH, RHSL, RHSH;
1231 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1232 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1234 MVT NVT = LHSL.getValueType();
1235 SDValue LoOps[2] = { LHSL, RHSL };
1236 SDValue HiOps[3] = { LHSH, RHSH };
1238 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1239 // them. TODO: Teach operation legalization how to expand unsupported
1240 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1241 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1242 // generate a value of this type in the expanded code sequence.
1244 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1245 ISD::ADDC : ISD::SUBC,
1246 TLI.getTypeToExpandTo(NVT));
1249 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1250 if (N->getOpcode() == ISD::ADD) {
1251 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1252 HiOps[2] = Lo.getValue(1);
1253 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1255 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1256 HiOps[2] = Lo.getValue(1);
1257 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1260 if (N->getOpcode() == ISD::ADD) {
1261 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1262 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1263 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1265 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1266 DAG.getConstant(1, NVT),
1267 DAG.getConstant(0, NVT));
1268 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1270 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1271 DAG.getConstant(1, NVT), Carry1);
1272 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1274 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1275 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1277 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1278 LoOps[0], LoOps[1], ISD::SETULT);
1279 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1280 DAG.getConstant(1, NVT),
1281 DAG.getConstant(0, NVT));
1282 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1287 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1288 SDValue &Lo, SDValue &Hi) {
1289 // Expand the subcomponents.
1290 SDValue LHSL, LHSH, RHSL, RHSH;
1291 DebugLoc dl = N->getDebugLoc();
1292 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1293 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1294 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1295 SDValue LoOps[2] = { LHSL, RHSL };
1296 SDValue HiOps[3] = { LHSH, RHSH };
1298 if (N->getOpcode() == ISD::ADDC) {
1299 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1300 HiOps[2] = Lo.getValue(1);
1301 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1303 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1304 HiOps[2] = Lo.getValue(1);
1305 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1308 // Legalized the flag result - switch anything that used the old flag to
1310 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1313 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1314 SDValue &Lo, SDValue &Hi) {
1315 // Expand the subcomponents.
1316 SDValue LHSL, LHSH, RHSL, RHSH;
1317 DebugLoc dl = N->getDebugLoc();
1318 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1319 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1320 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1321 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1322 SDValue HiOps[3] = { LHSH, RHSH };
1324 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1325 HiOps[2] = Lo.getValue(1);
1326 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1328 // Legalized the flag result - switch anything that used the old flag to
1330 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1333 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1334 SDValue &Lo, SDValue &Hi) {
1335 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1336 DebugLoc dl = N->getDebugLoc();
1337 SDValue Op = N->getOperand(0);
1338 if (Op.getValueType().bitsLE(NVT)) {
1339 // The low part is any extension of the input (which degenerates to a copy).
1340 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1341 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1343 // For example, extension of an i48 to an i64. The operand type necessarily
1344 // promotes to the result type, so will end up being expanded too.
1345 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1346 "Only know how to promote this result!");
1347 SDValue Res = GetPromotedInteger(Op);
1348 assert(Res.getValueType() == N->getValueType(0) &&
1349 "Operand over promoted?");
1350 // Split the promoted operand. This will simplify when it is expanded.
1351 SplitInteger(Res, Lo, Hi);
1355 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1356 SDValue &Lo, SDValue &Hi) {
1357 DebugLoc dl = N->getDebugLoc();
1358 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1359 MVT NVT = Lo.getValueType();
1360 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1361 unsigned NVTBits = NVT.getSizeInBits();
1362 unsigned EVTBits = EVT.getSizeInBits();
1364 if (NVTBits < EVTBits) {
1365 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1366 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1368 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1369 // The high part replicates the sign bit of Lo, make it explicit.
1370 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1371 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1375 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1376 SDValue &Lo, SDValue &Hi) {
1377 DebugLoc dl = N->getDebugLoc();
1378 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1379 MVT NVT = Lo.getValueType();
1380 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1381 unsigned NVTBits = NVT.getSizeInBits();
1382 unsigned EVTBits = EVT.getSizeInBits();
1384 if (NVTBits < EVTBits) {
1385 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1386 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1388 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1389 // The high part must be zero, make it explicit.
1390 Hi = DAG.getConstant(0, NVT);
1394 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1395 SDValue &Lo, SDValue &Hi) {
1396 DebugLoc dl = N->getDebugLoc();
1397 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1398 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1399 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1402 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1403 SDValue &Lo, SDValue &Hi) {
1404 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1405 unsigned NBitWidth = NVT.getSizeInBits();
1406 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1407 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1408 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1411 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1412 SDValue &Lo, SDValue &Hi) {
1413 DebugLoc dl = N->getDebugLoc();
1414 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1415 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1416 MVT NVT = Lo.getValueType();
1418 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1419 DAG.getConstant(0, NVT), ISD::SETNE);
1421 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1422 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1424 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1425 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1426 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1427 Hi = DAG.getConstant(0, NVT);
1430 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1431 SDValue &Lo, SDValue &Hi) {
1432 DebugLoc dl = N->getDebugLoc();
1433 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1434 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1435 MVT NVT = Lo.getValueType();
1436 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1437 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1438 Hi = DAG.getConstant(0, NVT);
1441 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1442 SDValue &Lo, SDValue &Hi) {
1443 DebugLoc dl = N->getDebugLoc();
1444 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1445 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1446 MVT NVT = Lo.getValueType();
1448 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1449 DAG.getConstant(0, NVT), ISD::SETNE);
1451 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1452 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1454 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1455 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1456 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1457 Hi = DAG.getConstant(0, NVT);
1460 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1462 DebugLoc dl = N->getDebugLoc();
1463 MVT VT = N->getValueType(0);
1464 SDValue Op = N->getOperand(0);
1465 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1466 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1467 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1470 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1472 DebugLoc dl = N->getDebugLoc();
1473 MVT VT = N->getValueType(0);
1474 SDValue Op = N->getOperand(0);
1475 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1476 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1477 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1480 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1481 SDValue &Lo, SDValue &Hi) {
1482 if (ISD::isNormalLoad(N)) {
1483 ExpandRes_NormalLoad(N, Lo, Hi);
1487 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1489 MVT VT = N->getValueType(0);
1490 MVT NVT = TLI.getTypeToTransformTo(VT);
1491 SDValue Ch = N->getChain();
1492 SDValue Ptr = N->getBasePtr();
1493 ISD::LoadExtType ExtType = N->getExtensionType();
1494 int SVOffset = N->getSrcValueOffset();
1495 unsigned Alignment = N->getAlignment();
1496 bool isVolatile = N->isVolatile();
1497 DebugLoc dl = N->getDebugLoc();
1499 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1501 if (N->getMemoryVT().bitsLE(NVT)) {
1502 MVT EVT = N->getMemoryVT();
1504 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1505 EVT, isVolatile, Alignment);
1507 // Remember the chain.
1508 Ch = Lo.getValue(1);
1510 if (ExtType == ISD::SEXTLOAD) {
1511 // The high part is obtained by SRA'ing all but one of the bits of the
1513 unsigned LoSize = Lo.getValueType().getSizeInBits();
1514 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1515 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1516 } else if (ExtType == ISD::ZEXTLOAD) {
1517 // The high part is just a zero.
1518 Hi = DAG.getConstant(0, NVT);
1520 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1521 // The high part is undefined.
1522 Hi = DAG.getUNDEF(NVT);
1524 } else if (TLI.isLittleEndian()) {
1525 // Little-endian - low bits are at low addresses.
1526 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1527 isVolatile, Alignment);
1529 unsigned ExcessBits =
1530 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1531 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1533 // Increment the pointer to the other half.
1534 unsigned IncrementSize = NVT.getSizeInBits()/8;
1535 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1536 DAG.getIntPtrConstant(IncrementSize));
1537 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1538 SVOffset+IncrementSize, NEVT,
1539 isVolatile, MinAlign(Alignment, IncrementSize));
1541 // Build a factor node to remember that this load is independent of the
1543 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1546 // Big-endian - high bits are at low addresses. Favor aligned loads at
1547 // the cost of some bit-fiddling.
1548 MVT EVT = N->getMemoryVT();
1549 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1550 unsigned IncrementSize = NVT.getSizeInBits()/8;
1551 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1553 // Load both the high bits and maybe some of the low bits.
1554 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1555 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1556 isVolatile, Alignment);
1558 // Increment the pointer to the other half.
1559 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1560 DAG.getIntPtrConstant(IncrementSize));
1561 // Load the rest of the low bits.
1562 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1563 SVOffset+IncrementSize,
1564 MVT::getIntegerVT(ExcessBits),
1565 isVolatile, MinAlign(Alignment, IncrementSize));
1567 // Build a factor node to remember that this load is independent of the
1569 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1572 if (ExcessBits < NVT.getSizeInBits()) {
1573 // Transfer low bits from the bottom of Hi to the top of Lo.
1574 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1575 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1576 DAG.getConstant(ExcessBits,
1577 TLI.getPointerTy())));
1578 // Move high bits to the right position in Hi.
1579 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1581 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1582 TLI.getPointerTy()));
1586 // Legalized the chain result - switch anything that used the old chain to
1588 ReplaceValueWith(SDValue(N, 1), Ch);
1591 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1592 SDValue &Lo, SDValue &Hi) {
1593 DebugLoc dl = N->getDebugLoc();
1594 SDValue LL, LH, RL, RH;
1595 GetExpandedInteger(N->getOperand(0), LL, LH);
1596 GetExpandedInteger(N->getOperand(1), RL, RH);
1597 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1598 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1601 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1602 SDValue &Lo, SDValue &Hi) {
1603 MVT VT = N->getValueType(0);
1604 MVT NVT = TLI.getTypeToTransformTo(VT);
1605 DebugLoc dl = N->getDebugLoc();
1607 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1608 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1609 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1610 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1611 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1612 SDValue LL, LH, RL, RH;
1613 GetExpandedInteger(N->getOperand(0), LL, LH);
1614 GetExpandedInteger(N->getOperand(1), RL, RH);
1615 unsigned OuterBitSize = VT.getSizeInBits();
1616 unsigned InnerBitSize = NVT.getSizeInBits();
1617 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1618 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1620 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1621 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1622 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1623 // The inputs are both zero-extended.
1625 // We can emit a umul_lohi.
1626 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1627 Hi = SDValue(Lo.getNode(), 1);
1631 // We can emit a mulhu+mul.
1632 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1633 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1637 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1638 // The input values are both sign-extended.
1640 // We can emit a smul_lohi.
1641 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1642 Hi = SDValue(Lo.getNode(), 1);
1646 // We can emit a mulhs+mul.
1647 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1648 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1653 // Lo,Hi = umul LHS, RHS.
1654 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1655 DAG.getVTList(NVT, NVT), LL, RL);
1657 Hi = UMulLOHI.getValue(1);
1658 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1659 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1660 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1661 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1665 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1666 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1667 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1668 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1669 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1670 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1675 // If nothing else, we can make a libcall.
1676 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1678 LC = RTLIB::MUL_I16;
1679 else if (VT == MVT::i32)
1680 LC = RTLIB::MUL_I32;
1681 else if (VT == MVT::i64)
1682 LC = RTLIB::MUL_I64;
1683 else if (VT == MVT::i128)
1684 LC = RTLIB::MUL_I128;
1685 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1687 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1688 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1691 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1692 SDValue &Lo, SDValue &Hi) {
1693 MVT VT = N->getValueType(0);
1694 DebugLoc dl = N->getDebugLoc();
1696 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1698 LC = RTLIB::SDIV_I16;
1699 else if (VT == MVT::i32)
1700 LC = RTLIB::SDIV_I32;
1701 else if (VT == MVT::i64)
1702 LC = RTLIB::SDIV_I64;
1703 else if (VT == MVT::i128)
1704 LC = RTLIB::SDIV_I128;
1705 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1707 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1708 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1711 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1712 SDValue &Lo, SDValue &Hi) {
1713 MVT VT = N->getValueType(0);
1714 DebugLoc dl = N->getDebugLoc();
1716 // If we can emit an efficient shift operation, do so now. Check to see if
1717 // the RHS is a constant.
1718 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1719 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1721 // If we can determine that the high bit of the shift is zero or one, even if
1722 // the low bits are variable, emit this shift in an optimized form.
1723 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1726 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1728 if (N->getOpcode() == ISD::SHL) {
1729 PartsOpc = ISD::SHL_PARTS;
1730 } else if (N->getOpcode() == ISD::SRL) {
1731 PartsOpc = ISD::SRL_PARTS;
1733 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1734 PartsOpc = ISD::SRA_PARTS;
1737 // Next check to see if the target supports this SHL_PARTS operation or if it
1738 // will custom expand it.
1739 MVT NVT = TLI.getTypeToTransformTo(VT);
1740 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1741 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1742 Action == TargetLowering::Custom) {
1743 // Expand the subcomponents.
1745 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1747 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1748 MVT VT = LHSL.getValueType();
1749 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1750 Hi = Lo.getValue(1);
1754 // Otherwise, emit a libcall.
1755 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1757 if (N->getOpcode() == ISD::SHL) {
1758 isSigned = false; /*sign irrelevant*/
1760 LC = RTLIB::SHL_I16;
1761 else if (VT == MVT::i32)
1762 LC = RTLIB::SHL_I32;
1763 else if (VT == MVT::i64)
1764 LC = RTLIB::SHL_I64;
1765 else if (VT == MVT::i128)
1766 LC = RTLIB::SHL_I128;
1767 } else if (N->getOpcode() == ISD::SRL) {
1770 LC = RTLIB::SRL_I16;
1771 else if (VT == MVT::i32)
1772 LC = RTLIB::SRL_I32;
1773 else if (VT == MVT::i64)
1774 LC = RTLIB::SRL_I64;
1775 else if (VT == MVT::i128)
1776 LC = RTLIB::SRL_I128;
1778 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1781 LC = RTLIB::SRA_I16;
1782 else if (VT == MVT::i32)
1783 LC = RTLIB::SRA_I32;
1784 else if (VT == MVT::i64)
1785 LC = RTLIB::SRA_I64;
1786 else if (VT == MVT::i128)
1787 LC = RTLIB::SRA_I128;
1790 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1791 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1792 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1796 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1797 assert(0 && "Unsupported shift!");
1800 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1801 SDValue &Lo, SDValue &Hi) {
1802 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1803 DebugLoc dl = N->getDebugLoc();
1804 SDValue Op = N->getOperand(0);
1805 if (Op.getValueType().bitsLE(NVT)) {
1806 // The low part is sign extension of the input (degenerates to a copy).
1807 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1808 // The high part is obtained by SRA'ing all but one of the bits of low part.
1809 unsigned LoSize = NVT.getSizeInBits();
1810 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1811 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1813 // For example, extension of an i48 to an i64. The operand type necessarily
1814 // promotes to the result type, so will end up being expanded too.
1815 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1816 "Only know how to promote this result!");
1817 SDValue Res = GetPromotedInteger(Op);
1818 assert(Res.getValueType() == N->getValueType(0) &&
1819 "Operand over promoted?");
1820 // Split the promoted operand. This will simplify when it is expanded.
1821 SplitInteger(Res, Lo, Hi);
1822 unsigned ExcessBits =
1823 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1824 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1825 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1829 void DAGTypeLegalizer::
1830 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1831 DebugLoc dl = N->getDebugLoc();
1832 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1833 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1835 if (EVT.bitsLE(Lo.getValueType())) {
1836 // sext_inreg the low part if needed.
1837 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1840 // The high part gets the sign extension from the lo-part. This handles
1841 // things like sextinreg V:i64 from i8.
1842 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1843 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1844 TLI.getPointerTy()));
1846 // For example, extension of an i48 to an i64. Leave the low part alone,
1847 // sext_inreg the high part.
1848 unsigned ExcessBits =
1849 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1850 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1851 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1855 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1856 SDValue &Lo, SDValue &Hi) {
1857 MVT VT = N->getValueType(0);
1858 DebugLoc dl = N->getDebugLoc();
1860 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1862 LC = RTLIB::SREM_I16;
1863 else if (VT == MVT::i32)
1864 LC = RTLIB::SREM_I32;
1865 else if (VT == MVT::i64)
1866 LC = RTLIB::SREM_I64;
1867 else if (VT == MVT::i128)
1868 LC = RTLIB::SREM_I128;
1869 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1871 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1872 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1875 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1876 SDValue &Lo, SDValue &Hi) {
1877 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1878 DebugLoc dl = N->getDebugLoc();
1879 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1880 Hi = DAG.getNode(ISD::SRL, dl,
1881 N->getOperand(0).getValueType(), N->getOperand(0),
1882 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1883 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1886 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1887 SDValue &Lo, SDValue &Hi) {
1888 MVT VT = N->getValueType(0);
1889 DebugLoc dl = N->getDebugLoc();
1891 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1893 LC = RTLIB::UDIV_I16;
1894 else if (VT == MVT::i32)
1895 LC = RTLIB::UDIV_I32;
1896 else if (VT == MVT::i64)
1897 LC = RTLIB::UDIV_I64;
1898 else if (VT == MVT::i128)
1899 LC = RTLIB::UDIV_I128;
1900 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1902 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1903 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1906 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1907 SDValue &Lo, SDValue &Hi) {
1908 MVT VT = N->getValueType(0);
1909 DebugLoc dl = N->getDebugLoc();
1911 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1913 LC = RTLIB::UREM_I16;
1914 else if (VT == MVT::i32)
1915 LC = RTLIB::UREM_I32;
1916 else if (VT == MVT::i64)
1917 LC = RTLIB::UREM_I64;
1918 else if (VT == MVT::i128)
1919 LC = RTLIB::UREM_I128;
1920 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1922 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1923 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1926 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1927 SDValue &Lo, SDValue &Hi) {
1928 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1929 DebugLoc dl = N->getDebugLoc();
1930 SDValue Op = N->getOperand(0);
1931 if (Op.getValueType().bitsLE(NVT)) {
1932 // The low part is zero extension of the input (degenerates to a copy).
1933 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1934 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1936 // For example, extension of an i48 to an i64. The operand type necessarily
1937 // promotes to the result type, so will end up being expanded too.
1938 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1939 "Only know how to promote this result!");
1940 SDValue Res = GetPromotedInteger(Op);
1941 assert(Res.getValueType() == N->getValueType(0) &&
1942 "Operand over promoted?");
1943 // Split the promoted operand. This will simplify when it is expanded.
1944 SplitInteger(Res, Lo, Hi);
1945 unsigned ExcessBits =
1946 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1947 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
1952 //===----------------------------------------------------------------------===//
1953 // Integer Operand Expansion
1954 //===----------------------------------------------------------------------===//
1956 /// ExpandIntegerOperand - This method is called when the specified operand of
1957 /// the specified node is found to need expansion. At this point, all of the
1958 /// result types of the node are known to be legal, but other operands of the
1959 /// node may need promotion or expansion as well as the specified one.
1960 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1961 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1962 SDValue Res = SDValue();
1964 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1967 switch (N->getOpcode()) {
1970 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1971 N->dump(&DAG); cerr << "\n";
1973 assert(0 && "Do not know how to expand this operator's operand!");
1976 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1977 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1978 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1979 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1980 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1981 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1982 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1983 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1984 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1985 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
1986 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1987 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1993 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
1996 // If the result is null, the sub-method took care of registering results etc.
1997 if (!Res.getNode()) return false;
1999 // If the result is N, the sub-method updated N in place. Tell the legalizer
2001 if (Res.getNode() == N)
2004 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2005 "Invalid operand expansion");
2007 ReplaceValueWith(SDValue(N, 0), Res);
2011 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2012 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2013 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2015 ISD::CondCode &CCCode,
2017 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2018 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2019 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2021 MVT VT = NewLHS.getValueType();
2023 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2024 if (RHSLo == RHSHi) {
2025 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2026 if (RHSCST->isAllOnesValue()) {
2027 // Equality comparison to -1.
2028 NewLHS = DAG.getNode(ISD::AND, dl,
2029 LHSLo.getValueType(), LHSLo, LHSHi);
2036 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2037 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2038 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2039 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2043 // If this is a comparison of the sign bit, just look at the top part.
2045 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2046 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2047 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2053 // FIXME: This generated code sucks.
2054 ISD::CondCode LowCC;
2056 default: assert(0 && "Unknown integer setcc!");
2058 case ISD::SETULT: LowCC = ISD::SETULT; break;
2060 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2062 case ISD::SETULE: LowCC = ISD::SETULE; break;
2064 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2067 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2068 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2069 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2071 // NOTE: on targets without efficient SELECT of bools, we can always use
2072 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2073 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2075 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2076 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2077 if (!Tmp1.getNode())
2078 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2079 LHSLo, RHSLo, LowCC);
2080 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2081 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2082 if (!Tmp2.getNode())
2083 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2084 TLI.getSetCCResultType(LHSHi.getValueType()),
2085 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2087 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2088 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2089 if ((Tmp1C && Tmp1C->isNullValue()) ||
2090 (Tmp2C && Tmp2C->isNullValue() &&
2091 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2092 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2093 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2094 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2095 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2096 // low part is known false, returns high part.
2097 // For LE / GE, if high part is known false, ignore the low part.
2098 // For LT / GT, if high part is known true, ignore the low part.
2104 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2105 LHSHi, RHSHi, ISD::SETEQ, false,
2106 DagCombineInfo, dl);
2107 if (!NewLHS.getNode())
2108 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2109 LHSHi, RHSHi, ISD::SETEQ);
2110 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2111 NewLHS, Tmp1, Tmp2);
2115 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2116 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2117 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2118 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2120 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2121 // against zero to select between true and false values.
2122 if (NewRHS.getNode() == 0) {
2123 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2124 CCCode = ISD::SETNE;
2127 // Update N to have the operands specified.
2128 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2129 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2133 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2134 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2135 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2136 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2138 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2139 // against zero to select between true and false values.
2140 if (NewRHS.getNode() == 0) {
2141 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2142 CCCode = ISD::SETNE;
2145 // Update N to have the operands specified.
2146 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2147 N->getOperand(2), N->getOperand(3),
2148 DAG.getCondCode(CCCode));
2151 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2152 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2153 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2154 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2156 // If ExpandSetCCOperands returned a scalar, use it.
2157 if (NewRHS.getNode() == 0) {
2158 assert(NewLHS.getValueType() == N->getValueType(0) &&
2159 "Unexpected setcc expansion!");
2163 // Otherwise, update N to have the operands specified.
2164 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2165 DAG.getCondCode(CCCode));
2168 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2169 // The value being shifted is legal, but the shift amount is too big.
2170 // It follows that either the result of the shift is undefined, or the
2171 // upper half of the shift amount is zero. Just use the lower half.
2173 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2174 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2177 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2178 SDValue Op = N->getOperand(0);
2179 MVT DstVT = N->getValueType(0);
2180 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2181 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2182 "Don't know how to expand this SINT_TO_FP!");
2183 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2186 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2187 if (ISD::isNormalStore(N))
2188 return ExpandOp_NormalStore(N, OpNo);
2190 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2191 assert(OpNo == 1 && "Can only expand the stored value so far");
2193 MVT VT = N->getOperand(1).getValueType();
2194 MVT NVT = TLI.getTypeToTransformTo(VT);
2195 SDValue Ch = N->getChain();
2196 SDValue Ptr = N->getBasePtr();
2197 int SVOffset = N->getSrcValueOffset();
2198 unsigned Alignment = N->getAlignment();
2199 bool isVolatile = N->isVolatile();
2200 DebugLoc dl = N->getDebugLoc();
2203 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2205 if (N->getMemoryVT().bitsLE(NVT)) {
2206 GetExpandedInteger(N->getValue(), Lo, Hi);
2207 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2208 N->getMemoryVT(), isVolatile, Alignment);
2209 } else if (TLI.isLittleEndian()) {
2210 // Little-endian - low bits are at low addresses.
2211 GetExpandedInteger(N->getValue(), Lo, Hi);
2213 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2214 isVolatile, Alignment);
2216 unsigned ExcessBits =
2217 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2218 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2220 // Increment the pointer to the other half.
2221 unsigned IncrementSize = NVT.getSizeInBits()/8;
2222 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2223 DAG.getIntPtrConstant(IncrementSize));
2224 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2225 SVOffset+IncrementSize, NEVT,
2226 isVolatile, MinAlign(Alignment, IncrementSize));
2227 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2229 // Big-endian - high bits are at low addresses. Favor aligned stores at
2230 // the cost of some bit-fiddling.
2231 GetExpandedInteger(N->getValue(), Lo, Hi);
2233 MVT EVT = N->getMemoryVT();
2234 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2235 unsigned IncrementSize = NVT.getSizeInBits()/8;
2236 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2237 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2239 if (ExcessBits < NVT.getSizeInBits()) {
2240 // Transfer high bits from the top of Lo to the bottom of Hi.
2241 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2242 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2243 TLI.getPointerTy()));
2244 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2245 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2246 DAG.getConstant(ExcessBits,
2247 TLI.getPointerTy())));
2250 // Store both the high bits and maybe some of the low bits.
2251 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2252 SVOffset, HiVT, isVolatile, Alignment);
2254 // Increment the pointer to the other half.
2255 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2256 DAG.getIntPtrConstant(IncrementSize));
2257 // Store the lowest ExcessBits bits in the second half.
2258 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2259 SVOffset+IncrementSize,
2260 MVT::getIntegerVT(ExcessBits),
2261 isVolatile, MinAlign(Alignment, IncrementSize));
2262 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2266 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2268 GetExpandedInteger(N->getOperand(0), InL, InH);
2269 // Just truncate the low part of the source.
2270 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2273 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2274 SDValue Op = N->getOperand(0);
2275 MVT SrcVT = Op.getValueType();
2276 MVT DstVT = N->getValueType(0);
2277 DebugLoc dl = N->getDebugLoc();
2279 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2280 // Do a signed conversion then adjust the result.
2281 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2282 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2284 // The result of the signed conversion needs adjusting if the 'sign bit' of
2285 // the incoming integer was set. To handle this, we dynamically test to see
2286 // if it is set, and, if so, add a fudge factor.
2288 const uint64_t F32TwoE32 = 0x4F800000ULL;
2289 const uint64_t F32TwoE64 = 0x5F800000ULL;
2290 const uint64_t F32TwoE128 = 0x7F800000ULL;
2293 if (SrcVT == MVT::i32)
2294 FF = APInt(32, F32TwoE32);
2295 else if (SrcVT == MVT::i64)
2296 FF = APInt(32, F32TwoE64);
2297 else if (SrcVT == MVT::i128)
2298 FF = APInt(32, F32TwoE128);
2300 assert(false && "Unsupported UINT_TO_FP!");
2302 // Check whether the sign bit is set.
2304 GetExpandedInteger(Op, Lo, Hi);
2305 SDValue SignSet = DAG.getSetCC(dl,
2306 TLI.getSetCCResultType(Hi.getValueType()),
2307 Hi, DAG.getConstant(0, Hi.getValueType()),
2310 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2311 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2312 TLI.getPointerTy());
2314 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2315 SDValue Zero = DAG.getIntPtrConstant(0);
2316 SDValue Four = DAG.getIntPtrConstant(4);
2317 if (TLI.isBigEndian()) std::swap(Zero, Four);
2318 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2320 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2321 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2322 Alignment = std::min(Alignment, 4u);
2324 // Load the value out, extending it from f32 to the destination float type.
2325 // FIXME: Avoid the extend by constructing the right constant pool?
2326 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2327 FudgePtr, NULL, 0, MVT::f32,
2329 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2332 // Otherwise, use a libcall.
2333 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2334 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2335 "Don't know how to expand this UINT_TO_FP!");
2336 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);